arch及bsp多核相关部分代码整理

bsp/qemu-vexpress-a9/drivers/realview.h

@@ -317,7 +317,7 @@ struct rt_hw_register
 };
 
 #include <rtdef.h>
-#include <armv7.h>
+#include <cpuport.h>
 
 /* Interrupt Control Interface */
 #define ARM_GIC_CPU_BASE    0x1E000000

bsp/qemu-vexpress-a9/drivers/secondary_cpu.c

@@ -30,27 +30,28 @@ static void rt_hw_timer2_isr(int vector, void *param)
     timer_clear_pending(0);
 }
 
-#ifdef RT_USING_USERSPACE
-extern void set_secondary_cpu_boot_address(uint32_t pv_off, void *second_boot_reg);
-#else
-extern void set_secondary_cpu_boot_address(void);
-#endif
-
 void rt_hw_secondary_cpu_up(void)
 {
-#ifdef RT_USING_USERSPACE
-    void *plat_boot_reg;
+    volatile void **plat_boot_reg = (volatile void **)0x10000034;
+    char *entry = (char *)rt_secondary_cpu_entry;
 
-    plat_boot_reg = rt_hw_mmu_map(&mmu_info, 0, (void*)0x10000034, 0x1000, MMU_MAP_K_RW);
-    set_secondary_cpu_boot_address(PV_OFFSET, plat_boot_reg);
-#else
-    extern void set_secondary_cpu_boot_address(void);
+#ifdef RT_USING_USERSPACE
+    plat_boot_reg = (volatile void **)rt_hw_mmu_map(&mmu_info, 0, (void *)plat_boot_reg, 0x1000, MMU_MAP_K_RW);
+    if (!plat_boot_reg)
+    {
+        /* failed */
+        return;
+    }
+    entry += PV_OFFSET;
 #endif
-    __asm__ volatile ("dsb":::"memory");
+    *plat_boot_reg-- = (void *)(size_t)-1;
+    *plat_boot_reg = (void *)entry;
+    rt_hw_dsb();
     rt_hw_ipi_send(0, 1 << 1);
 }
 
-void secondary_cpu_c_start(void)
+/* Interface */
+void rt_hw_secondary_cpu_bsp_start(void)
 {
     rt_hw_vector_init();
 

components/lwp/lwp.h

@@ -22,8 +22,6 @@
 #include <rtthread.h>
 #include <dfs.h>
 
-#include "arch.h"
-
 #include "lwp_pid.h"
 #include "lwp_ipc.h"
 #include "lwp_signal.h"

components/lwp/lwp_pid.c

@@ -896,7 +896,7 @@ void lwp_request_thread_exit(rt_thread_t thread_to_exit)
         if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK)
         {
             thread->error = RT_EINTR;
-            dsb();
+            rt_hw_dsb();
             rt_thread_wakeup(thread);
         }
         break;
@@ -936,7 +936,7 @@ void lwp_terminate(struct rt_lwp *lwp)
         if ((thread->stat & RT_THREAD_SUSPEND_MASK) == RT_THREAD_SUSPEND_MASK)
         {
             thread->error = RT_EINTR;
-            dsb();
+            rt_hw_dsb();
             rt_thread_wakeup(thread);
         }
     }

include/rtdef.h

@@ -200,6 +200,8 @@ typedef rt_base_t                       rt_off_t;       /**< Type for offset */
     #error not supported tool chain
 #endif
 
+#include <cpuport.h>
+
 /* initialization export */
 #ifdef RT_USING_COMPONENTS_INIT
 typedef int (*init_fn_t)(void);

include/rthw.h

@@ -63,15 +63,15 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size);
 #else
 
 /* define cache ops as empty */
-#define rt_hw_cpu_icache_enable
-#define rt_hw_cpu_icache_disable
-#define rt_hw_cpu_icache_ops
-#define rt_hw_cpu_dcache_enable
-#define rt_hw_cpu_dcache_disable
-#define rt_hw_cpu_dcache_ops
+#define rt_hw_cpu_icache_enable(...)
+#define rt_hw_cpu_icache_disable(...)
+#define rt_hw_cpu_icache_ops(...)
+#define rt_hw_cpu_dcache_enable(...)
+#define rt_hw_cpu_dcache_disable(...)
+#define rt_hw_cpu_dcache_ops(...)
 
-#define rt_hw_cpu_icache_status 0
-#define rt_hw_cpu_dcache_status 0
+#define rt_hw_cpu_icache_status(...) 0
+#define rt_hw_cpu_dcache_status(...) 0
 
 #endif
 
@@ -151,13 +151,6 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context));
 void rt_hw_us_delay(rt_uint32_t us);
 
 #ifdef RT_USING_SMP
-typedef union {
-    unsigned long slock;
-    struct __arch_tickets {
-        unsigned short owner;
-        unsigned short next;
-    } tickets;
-} rt_hw_spinlock_t;
 
 struct rt_spinlock
 {
@@ -197,7 +190,7 @@ void rt_hw_secondary_cpu_up(void);
 void rt_hw_secondary_cpu_idle_exec(void);
 #else
 
-#define RT_DEFINE_SPINLOCK(x)  
+#define RT_DEFINE_SPINLOCK(x)
 #define RT_DECLARE_SPINLOCK(x)    rt_ubase_t x
 
 #define rt_hw_spin_lock(lock)     *(lock) = rt_hw_interrupt_disable()

include/rtthread.h

@@ -22,6 +22,7 @@
 #include <rtconfig.h>
 #include <rtdebug.h>
 #include <rtdef.h>
+#include <cpuport.h>
 #include <rtservice.h>
 #include <rtm.h>
 
@@ -203,6 +204,7 @@ void rt_scheduler_sethook(void (*hook)(rt_thread_t from, rt_thread_t to));
 #endif
 
 #ifdef RT_USING_SMP
+void rt_secondary_cpu_entry(void);
 void rt_scheduler_ipi_handler(int vector, void *param);
 #endif
 

libcpu/arm/cortex-a/arch.h

@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-#ifndef  ARCH_H__
-#define  ARCH_H__
-
-#include <armv7.h>
-
-#endif  /*ARCH_H__*/

libcpu/arm/cortex-a/backtrace.h

@@ -2,7 +2,7 @@
 #define __BACKTRACE_H
 
 #ifndef __ASSEMBLY__
-#include <armv7.h>
+#include <cpuport.h>
 
 /* Unwind reason code according the the ARM EABI documents */
 enum unwind_reason_code

libcpu/arm/cortex-a/armv7.h → libcpu/arm/cortex-a/cpuport.h

@@ -6,8 +6,9 @@
  * Change Logs:
  * Date           Author       Notes
  */
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
+
+#ifndef  CPUPORT_H__
+#define  CPUPORT_H__
 
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
@@ -69,24 +70,29 @@ struct rt_hw_stack
 #define E_Bit       (1<<9)
 #define J_Bit       (1<<24)
 
-rt_inline void isb(void)
+#ifdef RT_USING_SMP
+typedef union {
+    unsigned long slock;
+    struct __arch_tickets {
+        unsigned short owner;
+        unsigned short next;
+    } tickets;
+} rt_hw_spinlock_t;
+#endif
+
+rt_inline void rt_hw_isb(void)
 {
     asm volatile ("isb":::"memory");
 }
 
-rt_inline void dmb(void)
+rt_inline void rt_hw_dmb(void)
 {
     asm volatile ("dmb":::"memory");
 }
 
-rt_inline void dsb(void)
+rt_inline void rt_hw_dsb(void)
 {
     asm volatile ("dsb":::"memory");
 }
 
-rt_inline void icache_invalid_all(void)
-{
-    asm volatile ("mcr p15, 0, r0, c7, c5, 0":::"memory");//iciallu
-    isb();
-}
-#endif
+#endif  /*CPUPORT_H__*/

libcpu/arm/cortex-a/stack.c

@@ -10,7 +10,6 @@
  */
 #include <rtthread.h>
 #include <board.h>
-#include <arch.h>
 
 /**
  * @addtogroup ARM Cortex-A

libcpu/arm/cortex-a/start_gcc.S

@@ -613,32 +613,13 @@ vector_resv:
     b       .
 
 #ifdef RT_USING_SMP
-.global set_secondary_cpu_boot_address
-set_secondary_cpu_boot_address:
-#ifdef RT_USING_USERSPACE
-    ldr     r2,  =secondary_cpu_start
-    add     r0, r2
-
-    mvn     r2, #0 //0xffffffff
-    str     r2, [r1]
-    str     r0, [r1, #-4]
-#else
-    ldr     r0, =secondary_cpu_start
-
-    mvn     r1, #0 //0xffffffff
-    ldr     r2, =0x10000034
-    str     r1, [r2]
-    str     r0, [r2, #-4]
-#endif
-    mov     pc, lr
-
 .global rt_clz
 rt_clz:
     clz r0, r0
     bx lr
 
-.global secondary_cpu_start
-secondary_cpu_start:
+.global rt_secondary_cpu_entry
+rt_secondary_cpu_entry:
 #ifdef RT_USING_USERSPACE
     ldr     r5, =PV_OFFSET
 
@@ -687,7 +668,7 @@ after_enable_mmu2:
     bl rt_hw_mmu_init
 #endif
 
-    b secondary_cpu_c_start
+    b rt_hw_secondary_cpu_bsp_start
 #endif
 
 .bss

libcpu/arm/cortex-a/trap.c

@@ -13,7 +13,6 @@
 #include <board.h>
 #include <backtrace.h>
 
-#include "arch.h"
 #include "interrupt.h"
 
 #ifdef RT_USING_FINSH