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+/*
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+ * File : context.asm
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+ * This file is part of RT-Thread RTOS
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+ * COPYRIGHT (C) 2009, RT-Thread Development Team
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+ *
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+ * The license and distribution terms for this file may be
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+ * found in the file LICENSE in this distribution or at
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+ * http://www.rt-thread.org/license/LICENSE
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2010-04-09 fify the first version
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+ *
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+ * For : Renesas M16C
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+ * Toolchain : IAR's EW for M16C v3.401
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+*/
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+
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+;********************************************************************************************************
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+; PUBLIC FUNCTIONS
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+;********************************************************************************************************
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+
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+ RSEG CSTACK
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+
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+ RSEG ISTACK
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+
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+ RSEG CODE(1)
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+
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+ EXTERN rt_thread_switch_interrput_flag
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+ EXTERN rt_interrupt_from_thread
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+ EXTERN rt_interrupt_to_thread
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+ EXTERN rt_interrupt_enter
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+ EXTERN rt_tick_increase
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+ EXTERN rt_interrupt_leave
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+ EXTERN u0rec_handler
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+
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+ PUBLIC rt_hw_interrupt_disable
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+ PUBLIC rt_hw_interrupt_enable
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+ PUBLIC rt_hw_context_switch_to
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+ PUBLIC rt_hw_context_switch
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+ PUBLIC rt_hw_context_switch_interrupt
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+ PUBLIC rt_hw_timer_handler
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+ PUBLIC rt_hw_uart0_receive_handler
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+
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+rt_hw_interrupt_disable
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+ FCLR I
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+ RTS
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+
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+rt_hw_interrupt_enable
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+ FSET I
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+ RTS
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+
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+;/*
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+; * void rt_hw_context_switch_to(rt_uint32 to);
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+; * r0 --> to
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+; * this fucntion is used to perform the first thread switch
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+; */
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+rt_hw_context_switch_to
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+ MOV.W R0, A0
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+ LDC [A0], ISP
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+ POPM R0,R1,R2,R3,A0,A1,SB,FB
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+ REIT
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+
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+rt_hw_context_switch
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+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB
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+ MOV.W R0, A0
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+ STC ISP, [A0]
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+ MOV.W R1, A0
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+ LDC [A0], ISP
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+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack
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+ REIT
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+
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+rt_hw_context_switch_interrupt
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+ CMP.W #1,rt_thread_switch_interrput_flag
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+ JEQ jump
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+ MOV.W #1,rt_thread_switch_interrput_flag
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+ MOV.W R0, rt_interrupt_from_thread
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+jump
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+ MOV.W R1, rt_interrupt_to_thread
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+ RTS
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+
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+rt_hw_context_switch_interrupt_do
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+ MOV.W #0, rt_thread_switch_interrput_flag
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+ MOV.W rt_interrupt_from_thread, A0
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+ STC ISP, [A0]
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+
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+ MOV.W rt_interrupt_to_thread, A0
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+ LDC [A0], ISP
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+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore all processor registers from the new task's stack
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+ RTS ; Normal return
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+
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+ .EVEN
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+rt_hw_timer_handler:
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+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers
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+ JSR rt_interrupt_enter
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+ JSR rt_tick_increase
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+ JSR rt_interrupt_leave
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+
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+ CMP.W #1,rt_thread_switch_interrput_flag
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+ JEQ rt_hw_context_switch_interrupt_do
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+
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+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
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+ REIT ; Return from interrup
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+
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+ .EVEN
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+rt_hw_uart0_receive_handler:
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+ PUSHM R0,R1,R2,R3,A0,A1,SB,FB ; Save current task's registers
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+ JSR rt_interrupt_enter
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+ JSR u0rec_handler
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+ JSR rt_interrupt_leave
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+
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+ CMP.W #1, rt_thread_switch_interrput_flag
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+ JEQ rt_hw_context_switch_interrupt_do
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+
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+ POPM R0,R1,R2,R3,A0,A1,SB,FB ; Restore registers from the new task's stack
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+ REIT ; Return from interrup
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+
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+ END
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