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@@ -0,0 +1,1449 @@
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+/*
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+ * Copyright (c) 2006-2025, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2025-07-16 CYFS first version
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+ */
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+
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+#include <rtthread.h>
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+#include <rtdevice.h>
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+#include "board.h"
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+#include "drv_usart_v2.h"
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+#ifdef RT_USING_SERIAL_V2
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+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
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+#error "Please define at least one BSP_USING_UARTx"
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+/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
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+#endif
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+
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+/******************************* declare ****************************************************************************************** */
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+enum
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+{
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+#ifdef BSP_USING_UART1
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+ UART1_INDEX,
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+#endif
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+#ifdef BSP_USING_UART2
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+ UART2_INDEX,
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+#endif
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+#ifdef BSP_USING_UART3
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+ UART3_INDEX,
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+#endif
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+#ifdef BSP_USING_UART4
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+ UART4_INDEX,
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+#endif
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+#ifdef BSP_USING_UART5
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+ UART5_INDEX,
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+#endif
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+#ifdef BSP_USING_UART6
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+ UART6_INDEX,
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+#endif
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+#ifdef BSP_USING_UART7
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+ UART7_INDEX,
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+#endif
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+#ifdef BSP_USING_UART8
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+ UART8_INDEX,
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+#endif
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+};
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+
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+
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+
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+struct DMA_HandleTypeDef
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+{
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+ DMA_Channel_TypeDef *Instance; /* DMA registers base address */
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+ struct UART_HandleTypeDef *Parent;
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+ DMA_InitTypeDef Init; /* DMA initialization parameters */
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+ rt_uint32_t dma_rcc;
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+ IRQn_Type dma_irq;
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+ void (*DMA_ITC_Callback)(struct UART_HandleTypeDef *huart) ;/* DMA transfer complete callback */
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+ void (*DMA_IE_Callback)(void); /* DMA error complete callback */
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+};
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+
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+struct UART_HandleTypeDef
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+{
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+ USART_TypeDef *Instance; /*!< UART registers base address */
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+ USART_InitTypeDef Init; /*!< UART communication parameters */
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+ struct DMA_HandleTypeDef *HDMA_Tx; /*!< UART Tx DMA handle parameters */
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+ struct DMA_HandleTypeDef *HDMA_Rx; /*!< UART Rx DMA handle parameters */
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+};
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+
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+struct ch32_uart_config
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+{
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+ const char *name;
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+ USART_TypeDef *Instance;
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+ rt_uint32_t rcc;
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+ IRQn_Type irq_type;
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+ GPIO_TypeDef *tx_port;
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+ uint16_t tx_pin;
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+ GPIO_TypeDef *rx_port;
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+ uint16_t rx_pin;
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+};
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+
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+struct ch32_uart
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+{
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+ struct UART_HandleTypeDef handle;
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+ struct ch32_uart_config *config;
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+#ifdef RT_SERIAL_USING_DMA
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+ struct
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+ {
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+ struct DMA_HandleTypeDef handle;
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+ rt_size_t remaining_cnt;
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+ } dma_rx;
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+ struct
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+ {
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+ struct DMA_HandleTypeDef handle;
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+ } dma_tx;
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+#endif
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+ rt_uint16_t uart_dma_flag;
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+ struct rt_serial_device serial;
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+};
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+/********************************************************************************************************************************** */
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+/******************************* funtion ****************************************************************************************** */
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+static void ch32_uart_get_config(void);
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+static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
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+static void NVIC_Set(IRQn_Type irq, FunctionalState state);
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+#ifdef RT_SERIAL_USING_DMA
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+static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag);
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+static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
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+void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart);
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+void HAL_UART_RxCpltCallback(struct UART_HandleTypeDef *huart);
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+static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma);
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+#endif
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+static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin);
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+/********************************************************************************************************************************** */
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+/******************************** value ******************************************************************************************* */
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+static struct ch32_uart_config uart_config[] =
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+{
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+#ifdef BSP_USING_UART1
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+ {
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+ .name = "uart1",
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+ .Instance = USART1,
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+ .rcc = RCC_APB2Periph_USART1,
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+ .irq_type = USART1_IRQn,
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+ .tx_port = GPIOA,
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+ .tx_pin = GPIO_Pin_9,
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+ .rx_port = GPIOA,
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+ .rx_pin = GPIO_Pin_10
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+ },
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+#endif
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+#ifdef BSP_USING_UART2
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+ {
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+ .name = "uart2",
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+ .Instance = USART2,
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+ .rcc = RCC_APB1Periph_USART2,
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+ .irq_type = USART2_IRQn,
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+ .tx_port = GPIOA,
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+ .tx_pin = GPIO_Pin_2,
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+ .rx_port = GPIOA,
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+ .rx_pin = GPIO_Pin_3
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+ },
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+#endif
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+#ifdef BSP_USING_UART3
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+ {
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+ .name = "uart3",
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+ .Instance = USART3,
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+ .rcc = RCC_APB1Periph_USART3,
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+ .irq_type = USART3_IRQn,
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+ .tx_port = GPIOB,
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+ .tx_pin = GPIO_Pin_10,
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+ .rx_port = GPIOB,
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+ .rx_pin = GPIO_Pin_11,
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+ },
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+#endif
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+#ifdef BSP_USING_UART4
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+ {
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+ .name = "uart4",
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+ .Instance = UART4,
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+ .rcc = RCC_APB1Periph_UART4,
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+ .irq_type = UART4_IRQn,
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+ .tx_port = GPIOC,
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+ .tx_pin = GPIO_Pin_10,
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+ .rx_port = GPIOC,
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+ .rx_pin = GPIO_Pin_11,
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+ },
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+#endif
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+#ifdef BSP_USING_UART5
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+ {
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+ .name = "uart5",
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+ .Instance = UART5,
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+ .rcc = RCC_APB1Periph_UART5,
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+ .irq_type = UART5_IRQn,
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+ .tx_port = GPIOC,
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+ .tx_pin = GPIO_Pin_12,
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+ .rx_port = GPIOD,
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+ .rx_pin = GPIO_Pin_2,
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+ },
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+#endif
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+#ifdef BSP_USING_UART6
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+ {
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+ .name = "uart6",
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+ .Instance = UART6,
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+ .rcc = RCC_APB1Periph_UART6,
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+ .irq_type = UART6_IRQn,
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+ .tx_port = GPIOC,
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+ .tx_pin = GPIO_Pin_0,
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+ .rx_port = GPIOC,
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+ .rx_pin = GPIO_Pin_1,
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+
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+ },
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+#endif
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+#ifdef BSP_USING_UART7
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+ {
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+ .name = "uart7",
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+ .Instance = UART7,
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+ .rcc = RCC_APB1Periph_UART7,
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+ .irq_type = UART7_IRQn,
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+ .tx_port = GPIOC,
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+ .tx_pin = GPIO_Pin_2,
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+ .rx_port = GPIOC,
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+ .rx_pin = GPIO_Pin_3,
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+ },
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+#endif
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+#ifdef BSP_USING_UART8
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+ {
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+ .name = "uart8",
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+ .Instance = UART8,
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+ .rcc = RCC_APB1Periph_UART8,
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+ .irq_type = UART8_IRQn,
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+ .tx_port = GPIOC,
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+ .tx_pin = GPIO_Pin_4,
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+ .rx_port = GPIOC,
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+ .rx_pin = GPIO_Pin_5,
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+ },
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+#endif
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+};
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+static struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(struct ch32_uart_config)];
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+/********************************************************************************************************************************** */
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+
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+static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin)
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+{
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+ GPIO_InitTypeDef GPIO_InitStructure;
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+ /* Enable the GPIO Clock */
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+ if (GPIOx == GPIOA)
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+ {
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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+ }
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+ else if (GPIOx == GPIOB)
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+ {
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
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+ }
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+ else if (GPIOx == GPIOC)
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+ {
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
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+ }
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+ else if (GPIOx == GPIOD)
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+ {
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
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+ }
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+ else if (GPIOx == GPIOE)
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+ {
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+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE);
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+ }
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+ /* Configure the GPIO pin */
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+ GPIO_InitStructure.GPIO_Pin = Pin;
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+ GPIO_InitStructure.GPIO_Mode = mode;
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+ GPIO_InitStructure.GPIO_Speed = speed;
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+ GPIO_Init(GPIOx, &GPIO_InitStructure);
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+}
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+
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+static void ch32_uart_init(struct ch32_uart_config *uart)
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+{
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+ if (uart->Instance==USART1)
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+ {
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+ RCC_APB2PeriphClockCmd(uart->rcc, ENABLE);
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+ }
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+ else
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+ {
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+ RCC_APB1PeriphClockCmd(uart->rcc, ENABLE);
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+ }
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+ NVIC_SetPriority(uart->irq_type, 0);
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+ GPIOInit(uart->rx_port, GPIO_Mode_IPU, GPIO_Speed_50MHz, uart->rx_pin);
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+ GPIOInit(uart->tx_port, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, uart->tx_pin);
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+}
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+
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+static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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+{
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+ struct ch32_uart *uart;
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+
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+ RT_ASSERT(serial != RT_NULL);
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+ RT_ASSERT(cfg != RT_NULL);
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+ uart = rt_container_of(serial, struct ch32_uart, serial);
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+ ch32_uart_init(uart->config);
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+ uart->handle.Init.USART_BaudRate = cfg->baud_rate;
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+
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+ switch (cfg->data_bits)
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+ {
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+ case DATA_BITS_8:
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+ uart->handle.Init.USART_WordLength = USART_WordLength_8b;
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+ break;
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+ case DATA_BITS_9:
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+ uart->handle.Init.USART_WordLength = USART_WordLength_9b;
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+ break;
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+
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+ default:
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+ uart->handle.Init.USART_WordLength = USART_WordLength_8b;
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+ ;
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+ break;
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+ }
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+
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+ switch (cfg->stop_bits)
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+ {
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+ case STOP_BITS_1:
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+ uart->handle.Init.USART_StopBits = USART_StopBits_1;
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+ break;
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+ case STOP_BITS_2:
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+ uart->handle.Init.USART_StopBits = USART_StopBits_0_5;
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+ break;
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+ case STOP_BITS_3:
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+ uart->handle.Init.USART_StopBits = USART_StopBits_2;
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+ break;
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+ case STOP_BITS_4:
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+ uart->handle.Init.USART_StopBits = USART_StopBits_1_5;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ switch (cfg->parity)
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+ {
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+ case PARITY_ODD:
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+ uart->handle.Init.USART_Parity = USART_Parity_Odd;
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+ break;
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+ case PARITY_EVEN:
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+ uart->handle.Init.USART_Parity = USART_Parity_Even;
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+ break;
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+ case PARITY_NONE:
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+ uart->handle.Init.USART_Parity = USART_Parity_No;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ switch (cfg->flowcontrol)
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+ {
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+ case RT_SERIAL_FLOWCONTROL_NONE:
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+ uart->handle.Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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+ break;
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+ case RT_SERIAL_FLOWCONTROL_CTSRTS:
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+ uart->handle.Init.USART_HardwareFlowControl = USART_HardwareFlowControl_CTS;
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+ break;
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+ default:
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+ uart->handle.Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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+ break;
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+ }
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+ uart->handle.Init.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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+ USART_DeInit(uart->handle.Instance);
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+ USART_Init(uart->handle.Instance, &uart->handle.Init);
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+ USART_Cmd(uart->handle.Instance, ENABLE);
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+#ifdef RT_SERIAL_USING_DMA
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+ uart->dma_rx.remaining_cnt = serial->config.dma_ping_bufsz;
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+#endif
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+ return RT_EOK;
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+}
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+
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+/**
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+ * @brief Configures the nested vectored interrupt controller.
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+ */
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+static void NVIC_Set(IRQn_Type irq, FunctionalState state)
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+{
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+ if (state == ENABLE)
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+ {
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+ NVIC_SetPriority(irq, 0);
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+ NVIC_EnableIRQ(irq);
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+ }
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+ else if (state == DISABLE)
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+ {
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+ NVIC_DisableIRQ(irq);
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+ }
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+}
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+
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+static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg)
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+{
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+ struct ch32_uart *uart;
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+ rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
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+
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+ RT_ASSERT(serial != RT_NULL);
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+ uart = rt_container_of(serial, struct ch32_uart, serial);
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+ if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
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+ {
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+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
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+ ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
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+ else
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+ ctrl_arg = RT_DEVICE_FLAG_INT_RX;
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+ }
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+ else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
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+ {
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+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
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+ ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
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+ else
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+ ctrl_arg = RT_DEVICE_FLAG_INT_TX;
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+ }
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+
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+ switch (cmd)
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+ {
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+ /* disable interrupt */
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+ case RT_DEVICE_CTRL_CLR_INT:
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+ NVIC_Set(uart->config->irq_type, DISABLE);
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+ if (ctrl_arg & RT_DEVICE_FLAG_INT_RX)
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+ {
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+ USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, DISABLE);
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+ }
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+
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+ if (ctrl_arg & RT_DEVICE_FLAG_INT_TX)
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+ {
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+ USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE);
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+
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+ }
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+#ifdef RT_SERIAL_USING_DMA
|
|
|
+ if (ctrl_arg & RT_DEVICE_FLAG_DMA_RX)
|
|
|
+ {
|
|
|
+ NVIC_Set(uart->dma_rx.handle.dma_irq, DISABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, DISABLE);
|
|
|
+ DMA_DeInit(uart->dma_rx.handle.Instance);
|
|
|
+
|
|
|
+ }
|
|
|
+ else if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
|
|
|
+ {
|
|
|
+ NVIC_Set(uart->dma_tx.handle.dma_irq, DISABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE);
|
|
|
+ USART_ClearFlag(uart->handle.Instance, USART_FLAG_TC);
|
|
|
+ DMA_DeInit(uart->dma_tx.handle.Instance);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ break;
|
|
|
+
|
|
|
+ case RT_DEVICE_CTRL_CONFIG:
|
|
|
+#ifdef RT_SERIAL_USING_DMA
|
|
|
+ if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
|
|
|
+ {
|
|
|
+ ch32_uart_dma_config(serial, ctrl_arg);
|
|
|
+
|
|
|
+ }
|
|
|
+ else
|
|
|
+ ch32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+ case RT_DEVICE_CTRL_SET_INT:
|
|
|
+ NVIC_Set(uart->config->irq_type, ENABLE);
|
|
|
+ if (ctrl_arg & RT_DEVICE_FLAG_INT_RX)
|
|
|
+ {
|
|
|
+
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, ENABLE);
|
|
|
+ USART_ClearITPendingBit(uart->config->Instance, USART_IT_RXNE);
|
|
|
+ USART_ClearFlag(uart->handle.Instance, USART_FLAG_RXNE);
|
|
|
+ }
|
|
|
+ else if (ctrl_arg & RT_DEVICE_FLAG_INT_TX)
|
|
|
+ {
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_TC, ENABLE);
|
|
|
+ USART_ClearFlag(uart->handle.Instance, USART_FLAG_TC);
|
|
|
+ }
|
|
|
+ NVIC_Set(uart->config->irq_type, ENABLE);
|
|
|
+ break;
|
|
|
+
|
|
|
+ case RT_DEVICE_CHECK_OPTMODE:
|
|
|
+ if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
|
|
|
+ return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
|
|
|
+ else
|
|
|
+ return RT_SERIAL_TX_BLOCKING_BUFFER;
|
|
|
+ case RT_DEVICE_CTRL_CLOSE:
|
|
|
+#ifdef RT_SERIAL_USING_DMA
|
|
|
+ DMA_Cmd(uart->dma_tx.handle.Instance, DISABLE);
|
|
|
+ DMA_Cmd(uart->dma_rx.handle.Instance, DISABLE);
|
|
|
+ NVIC_Set(uart->dma_rx.handle.dma_irq, DISABLE);
|
|
|
+#endif
|
|
|
+ USART_DeInit(uart->handle.Instance);
|
|
|
+ NVIC_Set(uart->config->irq_type, DISABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, DISABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, DISABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, DISABLE);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+static int ch32_putc(struct rt_serial_device *serial, char c)
|
|
|
+{
|
|
|
+ struct ch32_uart *uart;
|
|
|
+
|
|
|
+ RT_ASSERT(serial != RT_NULL);
|
|
|
+ uart = rt_container_of(serial, struct ch32_uart, serial);
|
|
|
+ while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET);
|
|
|
+ uart->config->Instance->DATAR = c;
|
|
|
+/* Transmit Data */
|
|
|
+
|
|
|
+ return 1;
|
|
|
+}
|
|
|
+
|
|
|
+static int ch32_getc(struct rt_serial_device *serial)
|
|
|
+{
|
|
|
+ struct ch32_uart *uart;
|
|
|
+
|
|
|
+ RT_ASSERT(serial != RT_NULL);
|
|
|
+ uart = rt_container_of(serial, struct ch32_uart, serial);
|
|
|
+
|
|
|
+ return (int)(uart->handle.Instance->DATAR & (uint16_t)0xFF);
|
|
|
+}
|
|
|
+
|
|
|
+static rt_ssize_t ch32_transmit(struct rt_serial_device *serial,
|
|
|
+ rt_uint8_t *buf,
|
|
|
+ rt_size_t size,
|
|
|
+ rt_uint32_t tx_flag)
|
|
|
+{
|
|
|
+ struct ch32_uart *uart;
|
|
|
+
|
|
|
+ RT_ASSERT(serial != RT_NULL);
|
|
|
+ RT_ASSERT(buf != RT_NULL);
|
|
|
+ uart = rt_container_of(serial, struct ch32_uart, serial);
|
|
|
+
|
|
|
+#ifdef RT_SERIAL_USING_DMA
|
|
|
+ if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
|
|
|
+ {
|
|
|
+ DMA_Cmd(uart->dma_tx.handle.Instance, DISABLE);
|
|
|
+ uart->dma_tx.handle.Instance->MADDR = (unsigned int)buf;
|
|
|
+ uart->dma_tx.handle.Instance->CNTR = size & 0xFFFF;
|
|
|
+ DMA_Cmd(uart->dma_tx.handle.Instance, ENABLE);
|
|
|
+
|
|
|
+ return size & 0xFFFF;
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ return size;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * Uart common interrupt process. This need add to uart ISR.
|
|
|
+ *
|
|
|
+ * @param serial serial device
|
|
|
+ */
|
|
|
+static void uart_isr(struct rt_serial_device *serial)
|
|
|
+{
|
|
|
+ struct ch32_uart *uart;
|
|
|
+
|
|
|
+ RT_ASSERT(serial != RT_NULL);
|
|
|
+ uart = rt_container_of(serial, struct ch32_uart, serial);
|
|
|
+ /* If the Read data register is not empty and the RXNE interrupt is enabled （RDR） */
|
|
|
+ if (USART_GetITStatus(uart->handle.Instance, USART_IT_RXNE) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_RXNE) != RESET)
|
|
|
+ {
|
|
|
+ char chr = uart->handle.Instance->DATAR;
|
|
|
+ rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr);
|
|
|
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
|
|
+ USART_ClearITPendingBit(uart->config->Instance, USART_IT_RXNE);
|
|
|
+ }
|
|
|
+ /* If the Transmit data register is empty and the TXE interrupt enable is enabled （TDR）*/
|
|
|
+ else if (USART_GetITStatus(uart->handle.Instance, USART_IT_TXE) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TXE) != RESET)
|
|
|
+ {
|
|
|
+ rt_uint8_t put_char = 0;
|
|
|
+ if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, &put_char) == RT_EOK)
|
|
|
+ {
|
|
|
+ USART_SendData(uart->handle.Instance, put_char);
|
|
|
+ }
|
|
|
+ USART_ClearITPendingBit(uart->config->Instance, USART_IT_TXE);
|
|
|
+ }
|
|
|
+ else if (USART_GetITStatus(uart->handle.Instance, USART_IT_TC) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TC))
|
|
|
+ {
|
|
|
+ /* Clear Transmission complete interrupt flag ( ISR Register ) */
|
|
|
+ USART_ClearITPendingBit(uart->handle.Instance, USART_IT_TC);
|
|
|
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
|
|
|
+ }
|
|
|
+
|
|
|
+#ifdef RT_SERIAL_USING_DMA
|
|
|
+ else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_IDLE) != RESET)
|
|
|
+ && (USART_GetITStatus(uart->handle.Instance, USART_IT_IDLE) != RESET))
|
|
|
+ {
|
|
|
+ /* clean IDLEF flag */
|
|
|
+ dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
|
|
|
+ USART_ReceiveData(uart->handle.Instance);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART1)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void USART1_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void USART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void USART1_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART1_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA1_Channel5_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA1_Channel4_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA1_Channel4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA1_Channel4_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART1 */
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART2)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void USART2_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void USART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void USART2_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART2_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA1_Channel6_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA1_Channel6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA1_Channel6_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA1_Channel7_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART2 */
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART3)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void USART3_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void USART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void USART3_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART3_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA1_Channel3_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA1_Channel2_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA1_Channel2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA1_Channel2_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART3*/
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART4)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void UART4_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void UART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void UART4_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART4_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel3_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel3_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
|
|
|
+
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel5_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel5_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART4*/
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART5)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void UART5_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void UART5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void UART5_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART5_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel2_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel2_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel4_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel4_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART5*/
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART6)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void UART6_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void UART6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void UART6_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART6_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel7_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel7_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel6_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel6_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART6*/
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART7)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void UART7_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void UART7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void UART7_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART7_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel9_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel9_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel9_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel8_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel8_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART7*/
|
|
|
+
|
|
|
+#if defined(BSP_USING_UART8)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void UART8_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void UART8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void UART8_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ uart_isr(&(uart_obj[UART8_INDEX].serial));
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel11_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel11_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel11_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
|
|
|
+#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
|
|
|
+#if defined (SOC_RISCV_SERIES_CH32V2)
|
|
|
+void DMA2_Channel10_IRQHandler(void) __attribute__((interrupt()));
|
|
|
+#else
|
|
|
+void DMA2_Channel10_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
|
|
+#endif
|
|
|
+void DMA2_Channel10_IRQHandler(void)
|
|
|
+{
|
|
|
+ GET_INT_SP();
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+ FREE_INT_SP();
|
|
|
+}
|
|
|
+#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
|
|
|
+#endif /* BSP_USING_UART8*/
|
|
|
+static void ch32_uart_get_config(void)
|
|
|
+{
|
|
|
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART1
|
|
|
+ uart_obj[UART1_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
|
|
|
+ uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
|
|
|
+ uart_obj[UART1_INDEX].handle.Instance = USART1;
|
|
|
+ uart_obj[UART1_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART1_RX_USING_DMA
|
|
|
+ uart_obj[UART1_INDEX].handle.HDMA_Rx = &uart_obj[UART1_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART1_INDEX].serial.config.dma_ping_bufsz = BSP_UART1_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART1_INDEX].dma_rx.handle.Parent = &uart_obj[UART1_INDEX].handle;
|
|
|
+ uart_obj[UART1_INDEX].dma_rx.handle.Instance = DMA1_Channel5;
|
|
|
+ uart_obj[UART1_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
|
|
|
+ uart_obj[UART1_INDEX].dma_rx.handle.dma_irq = DMA1_Channel5_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART1_TX_USING_DMA
|
|
|
+ uart_obj[UART1_INDEX].handle.HDMA_Tx = &uart_obj[UART1_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART1_INDEX].dma_tx.handle.Parent = &uart_obj[UART1_INDEX].handle;
|
|
|
+ uart_obj[UART1_INDEX].dma_tx.handle.Instance = DMA1_Channel4;
|
|
|
+ uart_obj[UART1_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
|
|
|
+ uart_obj[UART1_INDEX].dma_tx.handle.dma_irq = DMA1_Channel4_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART2
|
|
|
+ uart_obj[UART2_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
|
|
|
+ uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
|
|
|
+ uart_obj[UART2_INDEX].handle.Instance = USART2;
|
|
|
+ uart_obj[UART2_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART2_RX_USING_DMA
|
|
|
+ uart_obj[UART2_INDEX].handle.HDMA_Rx = &uart_obj[UART2_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART2_INDEX].serial.config.dma_ping_bufsz = BSP_UART2_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART2_INDEX].dma_rx.handle.Parent = &uart_obj[UART2_INDEX].handle;
|
|
|
+ uart_obj[UART2_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART2_INDEX].dma_rx.handle.Instance = DMA1_Channel6;
|
|
|
+ uart_obj[UART2_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
|
|
|
+ uart_obj[UART2_INDEX].dma_rx.handle.dma_irq = DMA1_Channel6_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART2_TX_USING_DMA
|
|
|
+ uart_obj[UART2_INDEX].handle.HDMA_Tx = &uart_obj[UART2_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART2_INDEX].dma_tx.handle.Parent = &uart_obj[UART2_INDEX].handle;
|
|
|
+ uart_obj[UART2_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART2_INDEX].dma_tx.handle.Instance = DMA1_Channel7;
|
|
|
+ uart_obj[UART2_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
|
|
|
+ uart_obj[UART2_INDEX].dma_tx.handle.dma_irq = DMA1_Channel7_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART3
|
|
|
+ uart_obj[UART3_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
|
|
|
+ uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
|
|
|
+ uart_obj[UART3_INDEX].handle.Instance = USART3;
|
|
|
+ uart_obj[UART3_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART3_RX_USING_DMA
|
|
|
+ uart_obj[UART3_INDEX].handle.HDMA_Rx = &uart_obj[UART3_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART3_INDEX].serial.config.dma_ping_bufsz = BSP_UART3_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART3_INDEX].dma_rx.handle.Parent = &uart_obj[UART3_INDEX].handle;
|
|
|
+ uart_obj[UART3_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART3_INDEX].dma_rx.handle.Instance = DMA1_Channel3;
|
|
|
+ uart_obj[UART3_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
|
|
|
+ uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART3_TX_USING_DMA
|
|
|
+ uart_obj[UART3_INDEX].handle.HDMA_Tx = &uart_obj[UART3_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART3_INDEX].dma_tx.handle.Parent = &uart_obj[UART3_INDEX].handle;
|
|
|
+ uart_obj[UART3_INDEX].dma_tx.handle.Instance = DMA1_Channel2;
|
|
|
+ uart_obj[UART3_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART3_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
|
|
|
+ uart_obj[UART3_INDEX].dma_tx.handle.dma_irq = DMA1_Channel2_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART4
|
|
|
+ uart_obj[UART4_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
|
|
|
+ uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
|
|
|
+ uart_obj[UART4_INDEX].handle.Instance = UART4;
|
|
|
+ uart_obj[UART4_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART4_RX_USING_DMA
|
|
|
+ uart_obj[UART4_INDEX].handle.HDMA_Rx = &uart_obj[UART4_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART4_INDEX].serial.config.dma_ping_bufsz = BSP_UART4_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART4_INDEX].dma_rx.handle.Parent = &uart_obj[UART4_INDEX].handle;
|
|
|
+ uart_obj[UART4_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART4_INDEX].dma_rx.handle.Instance = DMA2_Channel3;
|
|
|
+ uart_obj[UART4_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART4_INDEX].dma_rx.handle.dma_irq = DMA2_Channel3_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART4_TX_USING_DMA
|
|
|
+ uart_obj[UART4_INDEX].handle.HDMA_Tx = &uart_obj[UART4_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART4_INDEX].dma_tx.handle.Parent = &uart_obj[UART4_INDEX].handle;
|
|
|
+ uart_obj[UART4_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART4_INDEX].dma_tx.handle.Instance = DMA2_Channel5;
|
|
|
+ uart_obj[UART4_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART4_INDEX].dma_tx.handle.dma_irq = DMA2_Channel5_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART5
|
|
|
+ uart_obj[UART5_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
|
|
|
+ uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
|
|
|
+ uart_obj[UART5_INDEX].handle.Instance = UART5;
|
|
|
+ uart_obj[UART5_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART5_RX_USING_DMA
|
|
|
+ uart_obj[UART5_INDEX].handle.HDMA_Rx = &uart_obj[UART5_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART5_INDEX].serial.config.dma_ping_bufsz = BSP_UART5_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART5_INDEX].dma_rx.handle.Parent = &uart_obj[UART5_INDEX].handle;
|
|
|
+ uart_obj[UART5_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART5_INDEX].dma_rx.handle.Instance = DMA2_Channel2;
|
|
|
+ uart_obj[UART5_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART5_INDEX].dma_rx.handle.dma_irq = DMA2_Channel2_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART5_TX_USING_DMA
|
|
|
+ uart_obj[UART5_INDEX].handle.HDMA_Tx = &uart_obj[UART5_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART5_INDEX].dma_tx.handle.Parent = &uart_obj[UART5_INDEX].handle;
|
|
|
+ uart_obj[UART5_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART5_INDEX].dma_tx.handle.Instance = DMA2_Channel4;
|
|
|
+ uart_obj[UART5_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART5_INDEX].dma_tx.handle.dma_irq = DMA2_Channel4_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART6
|
|
|
+ uart_obj[UART6_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
|
|
|
+ uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
|
|
|
+ uart_obj[UART6_INDEX].handle.Instance = UART6;
|
|
|
+ uart_obj[UART6_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART6_RX_USING_DMA
|
|
|
+ uart_obj[UART6_INDEX].handle.HDMA_Rx = &uart_obj[UART6_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART6_INDEX].serial.config.dma_ping_bufsz = BSP_UART6_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART6_INDEX].dma_rx.handle.Parent = &uart_obj[UART6_INDEX].handle;
|
|
|
+ uart_obj[UART6_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART6_INDEX].dma_rx.handle.Instance = DMA2_Channel7;
|
|
|
+ uart_obj[UART6_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART6_INDEX].dma_rx.handle.dma_irq = DMA2_Channel7_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART6_TX_USING_DMA
|
|
|
+ uart_obj[UART6_INDEX].handle.HDMA_Tx = &uart_obj[UART6_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART6_INDEX].dma_tx.handle.Parent = &uart_obj[UART6_INDEX].handle;
|
|
|
+ uart_obj[UART6_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART6_INDEX].dma_tx.handle.Instance = DMA2_Channel6;
|
|
|
+ uart_obj[UART6_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART6_INDEX].dma_tx.handle.dma_irq = DMA2_Channel6_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART7
|
|
|
+ uart_obj[UART7_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
|
|
|
+ uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
|
|
|
+ uart_obj[UART7_INDEX].handle.Instance = UART7;
|
|
|
+ uart_obj[UART7_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART7_RX_USING_DMA
|
|
|
+ uart_obj[UART7_INDEX].handle.HDMA_Rx = &uart_obj[UART7_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART7_INDEX].serial.config.dma_ping_bufsz = BSP_UART7_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART7_INDEX].dma_rx.handle.Parent = &uart_obj[UART7_INDEX].handle;
|
|
|
+ uart_obj[UART7_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART7_INDEX].dma_rx.handle.Instance = DMA2_Channel9;
|
|
|
+ uart_obj[UART7_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART7_INDEX].dma_rx.handle.dma_irq = DMA2_Channel9_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART7_TX_USING_DMA
|
|
|
+ uart_obj[UART7_INDEX].handle.HDMA_Tx = &uart_obj[UART7_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART7_INDEX].dma_tx.handle.Parent = &uart_obj[UART7_INDEX].handle;
|
|
|
+ uart_obj[UART7_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART7_INDEX].dma_tx.handle.Instance = DMA2_Channel8;
|
|
|
+ uart_obj[UART7_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART7_INDEX].dma_tx.handle.dma_irq = DMA2_Channel8_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_UART8
|
|
|
+ uart_obj[UART8_INDEX].serial.config = config;
|
|
|
+ uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE;
|
|
|
+ uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE;
|
|
|
+ uart_obj[UART8_INDEX].handle.Instance = UART8;
|
|
|
+ uart_obj[UART8_INDEX].uart_dma_flag = 0;
|
|
|
+#ifdef BSP_UART8_RX_USING_DMA
|
|
|
+ uart_obj[UART8_INDEX].handle.HDMA_Rx = &uart_obj[UART8_INDEX].dma_rx.handle;
|
|
|
+ uart_obj[UART8_INDEX].serial.config.dma_ping_bufsz = BSP_UART8_DMA_PING_BUFSIZE;
|
|
|
+ uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
+ uart_obj[UART8_INDEX].dma_rx.handle.Parent = &uart_obj[UART8_INDEX].handle;
|
|
|
+ uart_obj[UART8_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
|
|
|
+ uart_obj[UART8_INDEX].dma_rx.handle.Instance = DMA2_Channel10;
|
|
|
+ uart_obj[UART8_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART8_INDEX].dma_rx.handle.dma_irq = DMA2_Channel10_IRQn;
|
|
|
+#endif
|
|
|
+#ifdef BSP_UART8_TX_USING_DMA
|
|
|
+ uart_obj[UART8_INDEX].handle.HDMA_Tx = &uart_obj[UART8_INDEX].dma_tx.handle;
|
|
|
+ uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
+ uart_obj[UART8_INDEX].dma_tx.handle.Parent = &uart_obj[UART8_INDEX].handle;
|
|
|
+ uart_obj[UART8_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
|
|
|
+ uart_obj[UART8_INDEX].dma_tx.handle.Instance = DMA2_Channel11;
|
|
|
+ uart_obj[UART8_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
|
|
|
+ uart_obj[UART8_INDEX].dma_tx.handle.dma_irq = DMA2_Channel11_IRQn;
|
|
|
+#endif
|
|
|
+#endif
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef RT_SERIAL_USING_DMA
|
|
|
+static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|
|
+{
|
|
|
+ struct DMA_HandleTypeDef *DMA_Handle;
|
|
|
+ struct ch32_uart *uart;
|
|
|
+
|
|
|
+ RT_ASSERT(serial != RT_NULL);
|
|
|
+ RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
|
|
|
+ uart = rt_container_of(serial, struct ch32_uart, serial);
|
|
|
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
|
|
|
+ {
|
|
|
+ DMA_Handle = &uart->dma_rx.handle;
|
|
|
+ }
|
|
|
+ else /* RT_DEVICE_FLAG_DMA_TX == flag */
|
|
|
+ {
|
|
|
+ DMA_Handle = &uart->dma_tx.handle;
|
|
|
+ }
|
|
|
+
|
|
|
+ RCC_AHBPeriphClockCmd(DMA_Handle->dma_rcc, ENABLE);
|
|
|
+ DMA_DeInit(DMA_Handle->Instance);
|
|
|
+ DMA_Handle->Init.DMA_PeripheralBaseAddr = (unsigned int)uart->config->Instance + 0x4;
|
|
|
+ DMA_Handle->Init.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
|
|
+ DMA_Handle->Init.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
|
|
+ DMA_Handle->Init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
|
|
+ DMA_Handle->Init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
|
|
+ DMA_Handle->Init.DMA_M2M = DMA_M2M_Disable;
|
|
|
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
|
|
|
+ {
|
|
|
+ rt_uint8_t *ptr = NULL;
|
|
|
+ rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
|
|
|
+ DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralSRC;
|
|
|
+ DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)ptr;
|
|
|
+ DMA_Handle->Init.DMA_BufferSize = serial->config.dma_ping_bufsz;
|
|
|
+ DMA_Handle->Init.DMA_Mode = DMA_Mode_Circular;
|
|
|
+ DMA_Handle->Init.DMA_Priority = DMA_Priority_VeryHigh;
|
|
|
+ }
|
|
|
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
|
|
|
+ {
|
|
|
+ DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralDST;
|
|
|
+ DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)1;
|
|
|
+ DMA_Handle->Init.DMA_BufferSize = 1;
|
|
|
+ DMA_Handle->Init.DMA_Mode = DMA_Mode_Normal;
|
|
|
+ DMA_Handle->Init.DMA_Priority = DMA_Priority_High;
|
|
|
+ }
|
|
|
+ DMA_Init(DMA_Handle->Instance, &DMA_Handle->Init);
|
|
|
+ NVIC_Set(DMA_Handle->dma_irq, ENABLE);
|
|
|
+ /* Enable USART DMA Rx or TX request */
|
|
|
+ if (RT_DEVICE_FLAG_DMA_RX == flag)
|
|
|
+ {
|
|
|
+ DMA_Cmd(DMA_Handle->Instance, DISABLE);
|
|
|
+ USART_DMACmd(uart->handle.Instance, USART_DMAReq_Rx, ENABLE);
|
|
|
+ USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, ENABLE);
|
|
|
+ USART_ReceiveData(uart->handle.Instance);
|
|
|
+ DMA_ITConfig(DMA_Handle->Instance, DMA_IT_TC, ENABLE);
|
|
|
+ NVIC_Set(uart->config->irq_type, ENABLE);
|
|
|
+ DMA_Cmd(DMA_Handle->Instance, ENABLE);
|
|
|
+ }
|
|
|
+ else if (RT_DEVICE_FLAG_DMA_TX == flag)
|
|
|
+ {
|
|
|
+ USART_DMACmd(uart->handle.Instance, USART_DMAReq_Tx, ENABLE);
|
|
|
+ DMA_ITConfig(uart->dma_tx.handle.Instance, DMA_IT_TC, ENABLE);
|
|
|
+ }
|
|
|
+ USART_Cmd(uart->handle.Instance, ENABLE);
|
|
|
+}
|
|
|
+/**
|
|
|
+ * @brief Handle DMA interrupt request.
|
|
|
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified DMA Channel.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma)
|
|
|
+{
|
|
|
+ DMA_TypeDef *dmax = RT_NULL;
|
|
|
+ if ((unsigned int)hdma->Instance < DMA2_BASE)
|
|
|
+ {
|
|
|
+ dmax = DMA1;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ dmax = DMA2;
|
|
|
+ }
|
|
|
+ unsigned int flag_it = dmax->INTFR;
|
|
|
+ unsigned int channel_offset = ((unsigned int)hdma->Instance - (unsigned int)dmax - 8) / 20;
|
|
|
+ /* Transfer Complete Interrupt management ***********************************/
|
|
|
+ if ((flag_it & 2u << (4 * channel_offset)))
|
|
|
+ {
|
|
|
+ /* Clear the transfer complete flag */
|
|
|
+ dmax->INTFCR |= 2u << (4 * channel_offset);
|
|
|
+ struct ch32_uart *uart = (struct ch32_uart *)hdma->Parent;
|
|
|
+ /* Call the transfer complete callback */
|
|
|
+ if (hdma->DMA_ITC_Callback != RT_NULL)
|
|
|
+ {
|
|
|
+ hdma->DMA_ITC_Callback(&uart->handle);
|
|
|
+ }
|
|
|
+
|
|
|
+ }
|
|
|
+
|
|
|
+ if(flag_it & (8u << (4 * channel_offset)))
|
|
|
+ {
|
|
|
+ rt_kprintf("DMA error: %d\n", flag_it & (8u << (4 * channel_offset)));
|
|
|
+ dmax->INTFCR |= 8u << (4 * channel_offset);
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
|
|
|
+{
|
|
|
+ struct ch32_uart *uart;
|
|
|
+ rt_base_t level;
|
|
|
+ rt_size_t recv_len, counter;
|
|
|
+
|
|
|
+ RT_ASSERT(serial != RT_NULL);
|
|
|
+ uart = rt_container_of(serial, struct ch32_uart, serial);
|
|
|
+ recv_len = 0;
|
|
|
+ counter = uart->dma_rx.handle.Instance->CNTR;
|
|
|
+
|
|
|
+ switch (isr_flag)
|
|
|
+ {
|
|
|
+ case UART_RX_DMA_IT_IDLE_FLAG:
|
|
|
+ if (counter <= uart->dma_rx.remaining_cnt)
|
|
|
+ recv_len = uart->dma_rx.remaining_cnt - counter;
|
|
|
+ else
|
|
|
+ recv_len = serial->config.dma_ping_bufsz + uart->dma_rx.remaining_cnt - counter;
|
|
|
+
|
|
|
+ break;
|
|
|
+ case UART_RX_DMA_IT_HT_FLAG:
|
|
|
+ if (counter < uart->dma_rx.remaining_cnt)
|
|
|
+ recv_len = uart->dma_rx.remaining_cnt - counter;
|
|
|
+ else
|
|
|
+ recv_len = 0;
|
|
|
+ break;
|
|
|
+ case UART_RX_DMA_IT_TC_FLAG:
|
|
|
+ recv_len = uart->dma_rx.remaining_cnt;
|
|
|
+ break;
|
|
|
+
|
|
|
+ default:
|
|
|
+ recv_len = 0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (recv_len)
|
|
|
+ {
|
|
|
+ uart->dma_rx.remaining_cnt = counter;
|
|
|
+
|
|
|
+ rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
|
|
|
+ }
|
|
|
+
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart)
|
|
|
+{
|
|
|
+ RT_ASSERT(huart != NULL);
|
|
|
+ struct ch32_uart *uart = (struct ch32_uart *)huart;
|
|
|
+
|
|
|
+ rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
|
|
|
+}
|
|
|
+
|
|
|
+void HAL_UART_RxCpltCallback(struct UART_HandleTypeDef *huart)
|
|
|
+{
|
|
|
+ struct ch32_uart *uart;
|
|
|
+ RT_ASSERT(huart != NULL);
|
|
|
+ uart = (struct ch32_uart *)huart;
|
|
|
+ dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
|
|
|
+}
|
|
|
+#endif /* RT_SERIAL_USING_DMA */
|
|
|
+
|
|
|
+static const struct rt_uart_ops ch32_uart_ops =
|
|
|
+{
|
|
|
+ .configure = ch32_configure,
|
|
|
+ .control = ch32_control,
|
|
|
+ .putc = ch32_putc,
|
|
|
+ .getc = ch32_getc,
|
|
|
+ .transmit = ch32_transmit
|
|
|
+};
|
|
|
+
|
|
|
+int rt_hw_usart_init(void)
|
|
|
+{
|
|
|
+ rt_err_t result = 0;
|
|
|
+ rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ch32_uart);
|
|
|
+
|
|
|
+ ch32_uart_get_config();
|
|
|
+ for (int i = 0; i < obj_num; i++)
|
|
|
+ {
|
|
|
+ uart_obj[i].config = &uart_config[i];
|
|
|
+ /* init UART object */
|
|
|
+ uart_obj[i].serial.ops = &ch32_uart_ops;
|
|
|
+ /* register UART device */
|
|
|
+ rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_TX, NULL);
|
|
|
+ RT_ASSERT(result == RT_EOK);
|
|
|
+ }
|
|
|
+
|
|
|
+ return result;
|
|
|
+}
|
|
|
+
|
|
|
+#endif /* RT_USING_SERIAL_V2 */
|
|
|
+
|
CYFS