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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1570 bbd45198-f89e-11dd-88c7-29a3b14d5316
bernard.xiong@gmail.com 14 years ago
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      bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html
  2. 1094 0
      bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
  3. 342 0
      bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html

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bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/Release_Notes.html
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+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../../Release_Notes.html">Back to Release page</a></span></td>

+          </tr>

+<tr style="">

+<td style="padding: 1.5pt;">

+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release

+Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>

+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>

+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>

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+</tbody>

+</table>

+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>

+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">

+<tbody>

+<tr>

+<td style="padding: 0cm;" valign="top">

+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>

+<ol style="margin-top: 0cm;" start="1" type="1">

+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS

+update History</a><o:p></o:p></span></li>

+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>

+</ol>

+<span style="font-family: &quot;Times New Roman&quot;;"></span>

+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS

+update History</span></h2><br>

+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>

+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main

+Changes<o:p></o:p></span></u></b></p>

+

+            <ul style="margin-top: 0cm;" type="square">

+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h

+</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt

+definition for STM32F10x High-density Value line devices.<br>

+</span></li>

+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file&nbsp;provided within the CMSIS folder. <br>

+</span></li>

+

+            </ul>

+

+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0

+- 10/15/2010</span></h3>

+

+            <ol>

+<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li>

+            </ol>

+

+            <ul style="margin-top: 0in;" type="disc">

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support

+for&nbsp;<b>STM32F10x High-density Value line devices</b>.</span></li>

+            </ul>

+            <ol start="2">

+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li>

+            </ol>

+

+

+            

+            <ul style="margin-top: 0in;" type="disc">

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>

+              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li>

+                  <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li>

+</ul>

+                <li class="MsoNormal" style="">

+

+                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">All

+STM32 devices definitions are commented by default. User has to select the

+appropriate device before starting else an error will be signaled on compile

+time.</span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>

+                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li>

+</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>

+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>

+<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"

+to select if the user want to place the Vector Table in internal SRAM.

+An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>

+                  </span></li>

+

+              </ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three

+startup files for STM32 High-density Value line devices:

+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul>

+            </ul>

+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0

+- 04/16/2010</span></h3>

+

+<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>

+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support

+for&nbsp;<b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>

+

+            <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>

+              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices&nbsp;(remove&nbsp;comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>

+                <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><br>

+                  </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three

+startup files for STM32 XL-density&nbsp;devices:

+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ&nbsp;Handler (was missing in&nbsp;previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>

+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0

+- 03/01/2010</span></h3>

+<ol style="margin-top: 0in;" start="1" type="1">

+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>

+</ol>

+<ul style="margin-top: 0in;" type="disc">

+

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>

+                </span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support

+for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and

+Medium-density Value line (STM32F100x8/B) devices</b>.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li>

+

+</ul>

+<ol style="margin-top: 0in;" start="2" type="1">

+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>

+            <ul>

+              <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>

+            </ul>

+            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">

+              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>

+

+            </ol>

+

+            <ul style="margin-top: 0in;" type="disc">

+

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>

+              </li>

+              <ul>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update

+the stm32f10x.h file to support new Value line devices features: CEC

+peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>

+                  </span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,

+HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,

+HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy

+purposes.<br>

+                  </span></li>

+              </ul>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>

+                <span style="font-size: 10pt; font-family: Verdana;"></span></li>

+              <ul>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>

+                  <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default

+                  </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>

+                  </span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>

+                  </span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>

+                  </span></li>

+              </ul>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li>

+              <ul>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new

+startup files for STM32 Low-density Value line devices:

+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup

+files for STM32 Medium-density Value line devices:

+                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>

+To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>

+</span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>

+</span></li>

+              </ul>

+

+            </ul>

+

+<ul style="margin-top: 0in;" type="disc">

+</ul>

+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>

+<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The

+enclosed firmware and all the related documentation are not covered by

+a License Agreement, if you need such License you can contact your

+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>

+<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE

+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO

+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR

+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY

+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY

+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH

+THEIR PRODUCTS. <o:p></o:p></span></b></p>

+<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>

+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">

+<hr align="center" size="2" width="100%"></span></div>

+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For

+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers

+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>

+</td>

+</tr>

+</tbody>

+</table>

+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>

+</td>

+</tr>

+</tbody>

+</table>

+</div>

+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>

+</div>

+</body></html>

+ 1094 - 0
bsp/stm32f107/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
View File 

@@ -0,0 +1,1094 @@
 
+/**

+  ******************************************************************************

+  * @file    system_stm32f10x.c

+  * @author  MCD Application Team

+  * @version V3.5.0

+  * @date    11-March-2011

+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.

+  * 

+  * 1.  This file provides two functions and one global variable to be called from 

+  *     user application:

+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier

+  *                      factors, AHB/APBx prescalers and Flash settings). 

+  *                      This function is called at startup just after reset and 

+  *                      before branch to main program. This call is made inside

+  *                      the "startup_stm32f10x_xx.s" file.

+  *

+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used

+  *                                  by the user application to setup the SysTick 

+  *                                  timer or configure other parameters.

+  *                                     

+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must

+  *                                 be called whenever the core clock is changed

+  *                                 during program execution.

+  *

+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.

+  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to

+  *    configure the system clock before to branch to main program.

+  *

+  * 3. If the system clock source selected by user fails to startup, the SystemInit()

+  *    function will do nothing and HSI still used as system clock source. User can 

+  *    add some code to deal with this issue inside the SetSysClock() function.

+  *

+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on

+  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 

+  *    When HSE is used as system clock source, directly or through PLL, and you

+  *    are using different crystal you have to adapt the HSE value to your own

+  *    configuration.

+  *        

+  ******************************************************************************

+  * @attention

+  *

+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+  *

+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS

+  * @{

+  */

+

+/** @addtogroup stm32f10x_system

+  * @{

+  */  

+  

+/** @addtogroup STM32F10x_System_Private_Includes

+  * @{

+  */

+

+#include "stm32f10x.h"

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F10x_System_Private_TypesDefinitions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F10x_System_Private_Defines

+  * @{

+  */

+

+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)

+   frequency (after reset the HSI is used as SYSCLK source)

+   

+   IMPORTANT NOTE:

+   ============== 

+   1. After each device reset the HSI is used as System clock source.

+

+   2. Please make sure that the selected System clock doesn't exceed your device's

+      maximum frequency.

+      

+   3. If none of the define below is enabled, the HSI is used as System clock

+    source.

+

+   4. The System clock configuration functions provided within this file assume that:

+        - For Low, Medium and High density Value line devices an external 8MHz 

+          crystal is used to drive the System clock.

+        - For Low, Medium and High density devices an external 8MHz crystal is

+          used to drive the System clock.

+        - For Connectivity line devices an external 25MHz crystal is used to drive

+          the System clock.

+     If you are using different crystal you have to adapt those functions accordingly.

+    */

+    

+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)

+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */

+ #define SYSCLK_FREQ_24MHz  24000000

+#else

+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */

+/* #define SYSCLK_FREQ_24MHz  24000000 */ 

+/* #define SYSCLK_FREQ_36MHz  36000000 */

+/* #define SYSCLK_FREQ_48MHz  48000000 */

+/* #define SYSCLK_FREQ_56MHz  56000000 */

+#define SYSCLK_FREQ_72MHz  72000000

+#endif

+

+/*!< Uncomment the following line if you need to use external SRAM mounted

+     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 

+     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 

+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)

+/* #define DATA_IN_ExtSRAM */

+#endif

+

+/*!< Uncomment the following line if you need to relocate your vector Table in

+     Internal SRAM. */ 

+/* #define VECT_TAB_SRAM */

+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 

+                                  This value must be a multiple of 0x200. */

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F10x_System_Private_Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F10x_System_Private_Variables

+  * @{

+  */

+

+/*******************************************************************************

+*  Clock Definitions

+*******************************************************************************/

+#ifdef SYSCLK_FREQ_HSE

+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */

+#elif defined SYSCLK_FREQ_24MHz

+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */

+#elif defined SYSCLK_FREQ_36MHz

+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */

+#elif defined SYSCLK_FREQ_48MHz

+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */

+#elif defined SYSCLK_FREQ_56MHz

+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */

+#elif defined SYSCLK_FREQ_72MHz

+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */

+#else /*!< HSI Selected as System Clock source */

+  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */

+#endif

+

+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes

+  * @{

+  */

+

+static void SetSysClock(void);

+

+#ifdef SYSCLK_FREQ_HSE

+  static void SetSysClockToHSE(void);

+#elif defined SYSCLK_FREQ_24MHz

+  static void SetSysClockTo24(void);

+#elif defined SYSCLK_FREQ_36MHz

+  static void SetSysClockTo36(void);

+#elif defined SYSCLK_FREQ_48MHz

+  static void SetSysClockTo48(void);

+#elif defined SYSCLK_FREQ_56MHz

+  static void SetSysClockTo56(void);  

+#elif defined SYSCLK_FREQ_72MHz

+  static void SetSysClockTo72(void);

+#endif

+

+#ifdef DATA_IN_ExtSRAM

+  static void SystemInit_ExtMemCtl(void); 

+#endif /* DATA_IN_ExtSRAM */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F10x_System_Private_Functions

+  * @{

+  */

+

+/**

+  * @brief  Setup the microcontroller system

+  *         Initialize the Embedded Flash Interface, the PLL and update the 

+  *         SystemCoreClock variable.

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+void SystemInit (void)

+{

+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */

+  /* Set HSION bit */

+  RCC->CR |= (uint32_t)0x00000001;

+

+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */

+#ifndef STM32F10X_CL

+  RCC->CFGR &= (uint32_t)0xF8FF0000;

+#else

+  RCC->CFGR &= (uint32_t)0xF0FF0000;

+#endif /* STM32F10X_CL */   

+  

+  /* Reset HSEON, CSSON and PLLON bits */

+  RCC->CR &= (uint32_t)0xFEF6FFFF;

+

+  /* Reset HSEBYP bit */

+  RCC->CR &= (uint32_t)0xFFFBFFFF;

+

+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */

+  RCC->CFGR &= (uint32_t)0xFF80FFFF;

+

+#ifdef STM32F10X_CL

+  /* Reset PLL2ON and PLL3ON bits */

+  RCC->CR &= (uint32_t)0xEBFFFFFF;

+

+  /* Disable all interrupts and clear pending bits  */

+  RCC->CIR = 0x00FF0000;

+

+  /* Reset CFGR2 register */

+  RCC->CFGR2 = 0x00000000;

+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)

+  /* Disable all interrupts and clear pending bits  */

+  RCC->CIR = 0x009F0000;

+

+  /* Reset CFGR2 register */

+  RCC->CFGR2 = 0x00000000;      

+#else

+  /* Disable all interrupts and clear pending bits  */

+  RCC->CIR = 0x009F0000;

+#endif /* STM32F10X_CL */

+    

+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)

+  #ifdef DATA_IN_ExtSRAM

+    SystemInit_ExtMemCtl(); 

+  #endif /* DATA_IN_ExtSRAM */

+#endif 

+

+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */

+  /* Configure the Flash Latency cycles and enable prefetch buffer */

+  SetSysClock();

+

+#ifdef VECT_TAB_SRAM

+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */

+#else

+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */

+#endif 

+}

+

+/**

+  * @brief  Update SystemCoreClock variable according to Clock Register Values.

+  *         The SystemCoreClock variable contains the core clock (HCLK), it can

+  *         be used by the user application to setup the SysTick timer or configure

+  *         other parameters.

+  *           

+  * @note   Each time the core clock (HCLK) changes, this function must be called

+  *         to update SystemCoreClock variable value. Otherwise, any configuration

+  *         based on this variable will be incorrect.         

+  *     

+  * @note   - The system frequency computed by this function is not the real 

+  *           frequency in the chip. It is calculated based on the predefined 

+  *           constant and the selected clock source:

+  *             

+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)

+  *                                              

+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)

+  *                          

+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 

+  *             or HSI_VALUE(*) multiplied by the PLL factors.

+  *         

+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value

+  *             8 MHz) but the real value may vary depending on the variations

+  *             in voltage and temperature.   

+  *    

+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value

+  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure

+  *              that HSE_VALUE is same as the real frequency of the crystal used.

+  *              Otherwise, this function may have wrong result.

+  *                

+  *         - The result of this function could be not correct when using fractional

+  *           value for HSE crystal.

+  * @param  None

+  * @retval None

+  */

+void SystemCoreClockUpdate (void)

+{

+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;

+

+#ifdef  STM32F10X_CL

+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;

+#endif /* STM32F10X_CL */

+

+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)

+  uint32_t prediv1factor = 0;

+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */

+    

+  /* Get SYSCLK source -------------------------------------------------------*/

+  tmp = RCC->CFGR & RCC_CFGR_SWS;

+  

+  switch (tmp)

+  {

+    case 0x00:  /* HSI used as system clock */

+      SystemCoreClock = HSI_VALUE;

+      break;

+    case 0x04:  /* HSE used as system clock */

+      SystemCoreClock = HSE_VALUE;

+      break;

+    case 0x08:  /* PLL used as system clock */

+

+      /* Get PLL clock source and multiplication factor ----------------------*/

+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;

+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

+      

+#ifndef STM32F10X_CL      

+      pllmull = ( pllmull >> 18) + 2;

+      

+      if (pllsource == 0x00)

+      {

+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */

+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;

+      }

+      else

+      {

+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)

+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;

+       /* HSE oscillator clock selected as PREDIV1 clock entry */

+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 

+ #else

+        /* HSE selected as PLL clock entry */

+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)

+        {/* HSE oscillator clock divided by 2 */

+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;

+        }

+        else

+        {

+          SystemCoreClock = HSE_VALUE * pllmull;

+        }

+ #endif

+      }

+#else

+      pllmull = pllmull >> 18;

+      

+      if (pllmull != 0x0D)

+      {

+         pllmull += 2;

+      }

+      else

+      { /* PLL multiplication factor = PLL input clock * 6.5 */

+        pllmull = 13 / 2; 

+      }

+            

+      if (pllsource == 0x00)

+      {

+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */

+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;

+      }

+      else

+      {/* PREDIV1 selected as PLL clock entry */

+        

+        /* Get PREDIV1 clock source and division factor */

+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;

+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;

+        

+        if (prediv1source == 0)

+        { 

+          /* HSE oscillator clock selected as PREDIV1 clock entry */

+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          

+        }

+        else

+        {/* PLL2 clock selected as PREDIV1 clock entry */

+          

+          /* Get PREDIV2 division factor and PLL2 multiplication factor */

+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;

+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 

+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         

+        }

+      }

+#endif /* STM32F10X_CL */ 

+      break;

+

+    default:

+      SystemCoreClock = HSI_VALUE;

+      break;

+  }

+  

+  /* Compute HCLK clock frequency ----------------*/

+  /* Get HCLK prescaler */

+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];

+  /* HCLK clock frequency */

+  SystemCoreClock >>= tmp;  

+}

+

+/**

+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClock(void)

+{

+#ifdef SYSCLK_FREQ_HSE

+  SetSysClockToHSE();

+#elif defined SYSCLK_FREQ_24MHz

+  SetSysClockTo24();

+#elif defined SYSCLK_FREQ_36MHz

+  SetSysClockTo36();

+#elif defined SYSCLK_FREQ_48MHz

+  SetSysClockTo48();

+#elif defined SYSCLK_FREQ_56MHz

+  SetSysClockTo56();  

+#elif defined SYSCLK_FREQ_72MHz

+  SetSysClockTo72();

+#endif

+ 

+ /* If none of the define above is enabled, the HSI is used as System clock

+    source (default after reset) */ 

+}

+

+/**

+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 

+  *          before jump to __main

+  * @param  None

+  * @retval None

+  */ 

+#ifdef DATA_IN_ExtSRAM

+/**

+  * @brief  Setup the external memory controller. 

+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.

+  * 	      This function configures the external SRAM mounted on STM3210E-EVAL

+  *         board (STM32 High density devices). This SRAM will be used as program

+  *         data memory (including heap and stack).

+  * @param  None

+  * @retval None

+  */ 

+void SystemInit_ExtMemCtl(void) 

+{

+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 

+  required, then adjust the Register Addresses */

+

+  /* Enable FSMC clock */

+  RCC->AHBENR = 0x00000114;

+  

+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  

+  RCC->APB2ENR = 0x000001E0;

+  

+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/

+/*----------------  SRAM Address lines configuration -------------------------*/

+/*----------------  NOE and NWE configuration --------------------------------*/  

+/*----------------  NE3 configuration ----------------------------------------*/

+/*----------------  NBL0, NBL1 configuration ---------------------------------*/

+  

+  GPIOD->CRL = 0x44BB44BB;  

+  GPIOD->CRH = 0xBBBBBBBB;

+

+  GPIOE->CRL = 0xB44444BB;  

+  GPIOE->CRH = 0xBBBBBBBB;

+

+  GPIOF->CRL = 0x44BBBBBB;  

+  GPIOF->CRH = 0xBBBB4444;

+

+  GPIOG->CRL = 0x44BBBBBB;  

+  GPIOG->CRH = 0x44444B44;

+   

+/*----------------  FSMC Configuration ---------------------------------------*/  

+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/

+  

+  FSMC_Bank1->BTCR[4] = 0x00001011;

+  FSMC_Bank1->BTCR[5] = 0x00000200;

+}

+#endif /* DATA_IN_ExtSRAM */

+

+#ifdef SYSCLK_FREQ_HSE

+/**

+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2

+  *         and PCLK1 prescalers.

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClockToHSE(void)

+{

+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

+  

+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    

+  /* Enable HSE */    

+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

+ 

+  /* Wait till HSE is ready and if Time out is reached exit */

+  do

+  {

+    HSEStatus = RCC->CR & RCC_CR_HSERDY;

+    StartUpCounter++;  

+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

+

+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

+  {

+    HSEStatus = (uint32_t)0x01;

+  }

+  else

+  {

+    HSEStatus = (uint32_t)0x00;

+  }  

+

+  if (HSEStatus == (uint32_t)0x01)

+  {

+

+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL

+    /* Enable Prefetch Buffer */

+    FLASH->ACR |= FLASH_ACR_PRFTBE;

+

+    /* Flash 0 wait state */

+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

+

+#ifndef STM32F10X_CL

+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;

+#else

+    if (HSE_VALUE <= 24000000)

+	{

+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;

+	}

+	else

+	{

+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;

+	}

+#endif /* STM32F10X_CL */

+#endif

+ 

+    /* HCLK = SYSCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

+      

+    /* PCLK2 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

+    

+    /* PCLK1 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;

+    

+    /* Select HSE as system clock source */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    

+

+    /* Wait till HSE is used as system clock source */

+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)

+    {

+    }

+  }

+  else

+  { /* If HSE fails to start-up, the application will have wrong clock 

+         configuration. User can add here some code to deal with this error */

+  }  

+}

+#elif defined SYSCLK_FREQ_24MHz

+/**

+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 

+  *         and PCLK1 prescalers.

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClockTo24(void)

+{

+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

+  

+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    

+  /* Enable HSE */    

+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

+ 

+  /* Wait till HSE is ready and if Time out is reached exit */

+  do

+  {

+    HSEStatus = RCC->CR & RCC_CR_HSERDY;

+    StartUpCounter++;  

+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

+

+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

+  {

+    HSEStatus = (uint32_t)0x01;

+  }

+  else

+  {

+    HSEStatus = (uint32_t)0x00;

+  }  

+

+  if (HSEStatus == (uint32_t)0x01)

+  {

+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 

+    /* Enable Prefetch Buffer */

+    FLASH->ACR |= FLASH_ACR_PRFTBE;

+

+    /* Flash 0 wait state */

+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    

+#endif

+ 

+    /* HCLK = SYSCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

+      

+    /* PCLK2 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

+    

+    /* PCLK1 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;

+    

+#ifdef STM32F10X_CL

+    /* Configure PLLs ------------------------------------------------------*/

+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 

+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 

+                            RCC_CFGR_PLLMULL6); 

+

+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */

+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       

+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |

+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |

+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);

+  

+    /* Enable PLL2 */

+    RCC->CR |= RCC_CR_PLL2ON;

+    /* Wait till PLL2 is ready */

+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)

+    {

+    }   

+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)

+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);

+#else    

+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);

+#endif /* STM32F10X_CL */

+

+    /* Enable PLL */

+    RCC->CR |= RCC_CR_PLLON;

+

+    /* Wait till PLL is ready */

+    while((RCC->CR & RCC_CR_PLLRDY) == 0)

+    {

+    }

+

+    /* Select PLL as system clock source */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

+

+    /* Wait till PLL is used as system clock source */

+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)

+    {

+    }

+  }

+  else

+  { /* If HSE fails to start-up, the application will have wrong clock 

+         configuration. User can add here some code to deal with this error */

+  } 

+}

+#elif defined SYSCLK_FREQ_36MHz

+/**

+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 

+  *         and PCLK1 prescalers. 

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClockTo36(void)

+{

+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

+  

+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    

+  /* Enable HSE */    

+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

+ 

+  /* Wait till HSE is ready and if Time out is reached exit */

+  do

+  {

+    HSEStatus = RCC->CR & RCC_CR_HSERDY;

+    StartUpCounter++;  

+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

+

+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

+  {

+    HSEStatus = (uint32_t)0x01;

+  }

+  else

+  {

+    HSEStatus = (uint32_t)0x00;

+  }  

+

+  if (HSEStatus == (uint32_t)0x01)

+  {

+    /* Enable Prefetch Buffer */

+    FLASH->ACR |= FLASH_ACR_PRFTBE;

+

+    /* Flash 1 wait state */

+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    

+ 

+    /* HCLK = SYSCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

+      

+    /* PCLK2 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

+    

+    /* PCLK1 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;

+    

+#ifdef STM32F10X_CL

+    /* Configure PLLs ------------------------------------------------------*/

+    

+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 

+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 

+                            RCC_CFGR_PLLMULL9); 

+

+	/*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */

+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */

+        

+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |

+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |

+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);

+  

+    /* Enable PLL2 */

+    RCC->CR |= RCC_CR_PLL2ON;

+    /* Wait till PLL2 is ready */

+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)

+    {

+    }

+    

+#else    

+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);

+#endif /* STM32F10X_CL */

+

+    /* Enable PLL */

+    RCC->CR |= RCC_CR_PLLON;

+

+    /* Wait till PLL is ready */

+    while((RCC->CR & RCC_CR_PLLRDY) == 0)

+    {

+    }

+

+    /* Select PLL as system clock source */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

+

+    /* Wait till PLL is used as system clock source */

+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)

+    {

+    }

+  }

+  else

+  { /* If HSE fails to start-up, the application will have wrong clock 

+         configuration. User can add here some code to deal with this error */

+  } 

+}

+#elif defined SYSCLK_FREQ_48MHz

+/**

+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 

+  *         and PCLK1 prescalers. 

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClockTo48(void)

+{

+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

+  

+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    

+  /* Enable HSE */    

+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

+ 

+  /* Wait till HSE is ready and if Time out is reached exit */

+  do

+  {

+    HSEStatus = RCC->CR & RCC_CR_HSERDY;

+    StartUpCounter++;  

+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

+

+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

+  {

+    HSEStatus = (uint32_t)0x01;

+  }

+  else

+  {

+    HSEStatus = (uint32_t)0x00;

+  }  

+

+  if (HSEStatus == (uint32_t)0x01)

+  {

+    /* Enable Prefetch Buffer */

+    FLASH->ACR |= FLASH_ACR_PRFTBE;

+

+    /* Flash 1 wait state */

+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    

+ 

+    /* HCLK = SYSCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

+      

+    /* PCLK2 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

+    

+    /* PCLK1 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

+    

+#ifdef STM32F10X_CL

+    /* Configure PLLs ------------------------------------------------------*/

+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */

+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */

+        

+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |

+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |

+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

+  

+    /* Enable PLL2 */

+    RCC->CR |= RCC_CR_PLL2ON;

+    /* Wait till PLL2 is ready */

+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)

+    {

+    }

+    

+   

+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 

+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 

+                            RCC_CFGR_PLLMULL6); 

+#else    

+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);

+#endif /* STM32F10X_CL */

+

+    /* Enable PLL */

+    RCC->CR |= RCC_CR_PLLON;

+

+    /* Wait till PLL is ready */

+    while((RCC->CR & RCC_CR_PLLRDY) == 0)

+    {

+    }

+

+    /* Select PLL as system clock source */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

+

+    /* Wait till PLL is used as system clock source */

+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)

+    {

+    }

+  }

+  else

+  { /* If HSE fails to start-up, the application will have wrong clock 

+         configuration. User can add here some code to deal with this error */

+  } 

+}

+

+#elif defined SYSCLK_FREQ_56MHz

+/**

+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 

+  *         and PCLK1 prescalers. 

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClockTo56(void)

+{

+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

+  

+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   

+  /* Enable HSE */    

+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

+ 

+  /* Wait till HSE is ready and if Time out is reached exit */

+  do

+  {

+    HSEStatus = RCC->CR & RCC_CR_HSERDY;

+    StartUpCounter++;  

+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

+

+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

+  {

+    HSEStatus = (uint32_t)0x01;

+  }

+  else

+  {

+    HSEStatus = (uint32_t)0x00;

+  }  

+

+  if (HSEStatus == (uint32_t)0x01)

+  {

+    /* Enable Prefetch Buffer */

+    FLASH->ACR |= FLASH_ACR_PRFTBE;

+

+    /* Flash 2 wait state */

+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    

+ 

+    /* HCLK = SYSCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

+      

+    /* PCLK2 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

+    

+    /* PCLK1 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

+

+#ifdef STM32F10X_CL

+    /* Configure PLLs ------------------------------------------------------*/

+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */

+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */

+        

+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |

+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |

+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

+  

+    /* Enable PLL2 */

+    RCC->CR |= RCC_CR_PLL2ON;

+    /* Wait till PLL2 is ready */

+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)

+    {

+    }

+    

+   

+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 

+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 

+                            RCC_CFGR_PLLMULL7); 

+#else     

+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);

+

+#endif /* STM32F10X_CL */

+

+    /* Enable PLL */

+    RCC->CR |= RCC_CR_PLLON;

+

+    /* Wait till PLL is ready */

+    while((RCC->CR & RCC_CR_PLLRDY) == 0)

+    {

+    }

+

+    /* Select PLL as system clock source */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

+

+    /* Wait till PLL is used as system clock source */

+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)

+    {

+    }

+  }

+  else

+  { /* If HSE fails to start-up, the application will have wrong clock 

+         configuration. User can add here some code to deal with this error */

+  } 

+}

+

+#elif defined SYSCLK_FREQ_72MHz

+/**

+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 

+  *         and PCLK1 prescalers. 

+  * @note   This function should be used only after reset.

+  * @param  None

+  * @retval None

+  */

+static void SetSysClockTo72(void)

+{

+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

+  

+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    

+  /* Enable HSE */    

+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

+ 

+  /* Wait till HSE is ready and if Time out is reached exit */

+  do

+  {

+    HSEStatus = RCC->CR & RCC_CR_HSERDY;

+    StartUpCounter++;  

+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

+

+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

+  {

+    HSEStatus = (uint32_t)0x01;

+  }

+  else

+  {

+    HSEStatus = (uint32_t)0x00;

+  }  

+

+  if (HSEStatus == (uint32_t)0x01)

+  {

+    /* Enable Prefetch Buffer */

+    FLASH->ACR |= FLASH_ACR_PRFTBE;

+

+    /* Flash 2 wait state */

+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);

+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    

+

+ 

+    /* HCLK = SYSCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

+      

+    /* PCLK2 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

+    

+    /* PCLK1 = HCLK */

+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

+

+#ifdef STM32F10X_CL

+    /* Configure PLLs ------------------------------------------------------*/

+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */

+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */

+        

+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |

+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |

+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);

+  

+    /* Enable PLL2 */

+    RCC->CR |= RCC_CR_PLL2ON;

+    /* Wait till PLL2 is ready */

+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)

+    {

+    }

+    

+   

+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 

+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 

+                            RCC_CFGR_PLLMULL9); 

+#else    

+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |

+                                        RCC_CFGR_PLLMULL));

+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);

+#endif /* STM32F10X_CL */

+

+    /* Enable PLL */

+    RCC->CR |= RCC_CR_PLLON;

+

+    /* Wait till PLL is ready */

+    while((RCC->CR & RCC_CR_PLLRDY) == 0)

+    {

+    }

+    

+    /* Select PLL as system clock source */

+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

+

+    /* Wait till PLL is used as system clock source */

+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)

+    {

+    }

+  }

+  else

+  { /* If HSE fails to start-up, the application will have wrong clock 

+         configuration. User can add here some code to deal with this error */

+  }

+}

+#endif

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+  

+/**

+  * @}

+  */    

+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

+ 342 - 0
bsp/stm32f107/Libraries/STM32F10x_StdPeriph_Driver/Release_Notes.html
View File 

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+<tbody>

+          <tr>

+            <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>

+          </tr>

+<tr style="">

+<td style="padding: 1.5pt;">

+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release

+Notes for STM32F10x Standard Peripherals Library Drivers

+(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>

+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>

+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>

+</td>

+</tr>

+</tbody>

+</table>

+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>

+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">

+<tbody>

+<tr>

+<td style="padding: 0cm;" valign="top">

+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>

+<ol style="margin-top: 0cm;" start="1" type="1">

+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library

+Drivers update History</a><o:p></o:p></span></li>

+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>

+</ol>

+<span style="font-family: &quot;Times New Roman&quot;;">

+</span>

+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard

+Peripherals Library Drivers&nbsp; update History</span></h2><br>

+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>

+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main

+Changes<o:p></o:p></span></u></b></p>

+

+            <ul style="margin-top: 0cm;" type="square">

+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c files:</span></li>

+              <ul>

+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 5 new functions</span></li>

+                <ul>

+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">3

+new functions controlling the counter errors: CAN_GetLastErrorCode(),

+CAN_GetReceiveErrorCounter() and CAN_GetLSBTransmitErrorCounter().</span></li>

+                </ul>

+                <ul>

+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to select the CAN operating mode: CAN_OperatingModeRequest().</span></li>

+                </ul>

+                <ul>

+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">1 new function to support CAN TT mode: CAN_TTComModeCmd().</span><span style="font-size: 10pt; font-family: Verdana;"><br>

+  </span></li>

+                </ul>

+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">CAN_TransmitStatus() function updated to support all CAN transmit intermediate states<br>

+                  </span></li>

+              </ul>

+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c files:</span></li>

+              <ul>

+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 1 new function:</span></li>

+                <ul>

+                  <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">I2C_NACKPositionConfig():

+This function configures the same bit (POS) as I2C_PECPositionConfig()

+but is intended to be used in I2C mode while I2C_PECPositionConfig() is

+intended to used in SMBUS mode.</span></li>

+                </ul>

+              </ul>

+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c files:</span></li>

+              <ul>

+                <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the <span style="font-style: italic;">TIM_DMABurstLength_xBytes</span> definitions to <span style="font-style: italic;">TIM_DMABurstLength_xTansfers</span><br>

+                  </span></li>

+              </ul>

+

+

+            </ul>

+

+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0

+- 10/15/2010</span></h3>

+

+            <ol style="margin-top: 0in;" start="1" type="1">

+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>

+            </ol>

+

+            <ul style="margin-top: 0in;" type="disc">

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>

+            </ul>

+

+            <ol style="margin-top: 0in;" start="2" type="1">

+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>

+            </ol>

+

+            

+            <ul style="margin-top: 0in;" type="disc">

+

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>

+</span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>

+                  </span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()

+and CAN_ClearFlag() functions: updated to support new flags (were not

+supported in previous version). These flags are:&nbsp; CAN_FLAG_RQCP0,

+CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,

+CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0,&nbsp;&nbsp; CAN_FLAG_FOV0,

+CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>

+                  </span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()

+function: add a check of the interrupt enable bit before getting the

+status of corresponding interrupt pending bit. <br>

+                  </span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>

+                  </span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>

+                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>

+                  </span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>

+              <ul>

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>

+              </ul>

+              <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>

+<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>

+            

+            </ul>

+

+            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0

+- 04/16/2010</span></h3>

+

+<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>

+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>

+<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>

+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:

+updated to support Bank2 of XL-density devices (up to 1MByte of Flash

+memory). For more details, refer to the description provided within

+stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>

+function: updated to check whether the last event contains the

+I2C_EVENT&nbsp; (instead of check whether the last event is equal to

+I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add

+detailed description of I2C events and how to manage them using the

+functions provided by this driver. For more information, refer to

+stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h:&nbsp;</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br>&nbsp;

+#define

+SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;

+&nbsp; ((uint32_t)0x00000000)<br>&nbsp; #define

+SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;

+((uint32_t)0x00000001)<br>by<br>&nbsp; #define

+SDIO_ReadWaitMode_CLK&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;

+&nbsp; ((uint32_t)0x00000001)<br>&nbsp; #define

+SDIO_ReadWaitMode_DATA2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;

+((uint32_t)0x00000000)</span></li></ul></ul>

+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0

+- 03/01/2010</span></h3>

+<ol style="margin-top: 0in;" start="1" type="1">

+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>

+</ol>

+<ul style="margin-top: 0in;" type="disc">

+

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support

+for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and

+Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost

+peripherals drivers were updated to support Value

+line devices features</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>

+

+</ul>

+<ol style="margin-top: 0in;" start="2" type="1">

+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>

+</ol>

+<ul style="margin-top: 0in;" type="disc">

+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new

+firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART

+driver: add support for Oversampling by 8 mode and onebit method. 2

+functions has been added: USART_OverSampling8Cmd() and

+USART_OneBitMethodCmd().<br>

+                </span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC

+driver: add new functions handling the DAC under run feature:

+DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()

+and DAC_ClearITPendingBit().</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>

+                </span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH

+driver: the FLASH_EraseOptionBytes() function updated. This is now just

+erasing the option bytes without modifying the RDP status either

+enabled or disabled.</span></li>

+              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR

+driver: the PWR_EnterSTOPMode() function updated. When woken up from

+STOP mode, this function resets again the SLEEPDEEP bit in the

+Cortex-M3 System Control register to allow Sleep mode entering.</span></li>

+              

+

+</ul>

+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>

+<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The

+enclosed firmware and all the related documentation are not covered by

+a License Agreement, if you need such License you can contact your

+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>

+<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE

+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO

+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR

+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY

+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY

+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH

+THEIR PRODUCTS. <o:p></o:p></span></b></p>

+<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>

+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">

+<hr align="center" size="2" width="100%"></span></div>

+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For

+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers

+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>

+</td>

+</tr>

+</tbody>

+</table>

+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>

+</td>

+</tr>

+</tbody>

+</table>

+</div>

+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>

+</div>

+</body></html>