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@@ -10,6 +10,7 @@
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* Change Logs:
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* Date Author Notes
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* 2009-09-22 Bernard add board.h to this bsp
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+ * 2017-12-29 ZYH Correctly generate the 48M clock
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*/
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#include <rtthread.h>
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@@ -20,12 +21,24 @@
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*/
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/*@{*/
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-
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+#ifdef RT_USING_HSI
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+ #error Can not using HSI on this bsp
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+#endif
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+#if defined(RCC_PERIPHCLK_SDIO) || defined(RCC_PERIPHCLK_CEC) || defined(RCC_PERIPHCLK_LTDC)\
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+ || defined(RCC_PERIPHCLK_SPDIFRX) || defined(RCC_PERIPHCLK_FMPI2C1) || defined(RCC_PERIPHCLK_LPTIM1)
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+#warning Please give priority to the correctness of the clock tree when the peripherals are abnormal
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+#endif
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static void SystemClock_Config(void)
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{
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+ rt_uint32_t hse_clk,sys_clk;
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+#if (RT_HSE_VALVE % 1000000 != 0)
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+ #error HSE must be integer of MHz
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+#endif
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+ hse_clk = HSE_VALUE/1000000UL;
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+ sys_clk = HCLK_VALUE/1000000UL;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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-#ifdef RT_USING_RTC
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+#if defined(RT_USING_RTC) || defined(RCC_PERIPHCLK_CLK48)
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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#endif
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/**Configure the main internal regulator output voltage
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@@ -44,10 +57,55 @@ static void SystemClock_Config(void)
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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- RCC_OscInitStruct.PLL.PLLM = (HSE_VALUE/1000000UL);//Get 1M clock
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- RCC_OscInitStruct.PLL.PLLN = (HCLK_VALUE/1000000UL)*2;//Get 2*HCLK_VALUE
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- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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- RCC_OscInitStruct.PLL.PLLQ = RCC_OscInitStruct.PLL.PLLN/48;//Get 48M Clock
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+ if(hse_clk % 2 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLM = hse_clk/2;//Get 2M clock
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+ if((sys_clk * 2) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk;//Get 2*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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+ }
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+ else if((sys_clk * 4) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 4*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;//Get HCLK_VALUE
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+ }
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+ else if((sys_clk * 6) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 3;//Get 6*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV6;//Get HCLK_VALUE
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+ }
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+ else if((sys_clk * 8) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 4;//Get 8*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;//Get HCLK_VALUE
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+ }
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+ }
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+ else
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+ {
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+ RCC_OscInitStruct.PLL.PLLM = hse_clk;//Get 1M clock
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+ if((sys_clk * 2) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 2*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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+ }
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+ else if((sys_clk * 4) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 4;//Get 4*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;//Get HCLK_VALUE
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+ }
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+ else if((sys_clk * 6) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 6;//Get 6*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV6;//Get HCLK_VALUE
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+ }
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+ else if((sys_clk * 8) % 48 == 0)
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+ {
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+ RCC_OscInitStruct.PLL.PLLN = sys_clk * 8;//Get 8*HCLK_VALUE
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;//Get HCLK_VALUE
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+ }
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+ }
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+ RCC_OscInitStruct.PLL.PLLQ = hse_clk / RCC_OscInitStruct.PLL.PLLM * RCC_OscInitStruct.PLL.PLLN/48;//Get 48M Clock
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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while(1)
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@@ -94,9 +152,16 @@ static void SystemClock_Config(void)
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{}
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}
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#endif
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-#ifdef RT_USING_RTC
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- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
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+#if defined(RT_USING_RTC) || defined(RCC_PERIPHCLK_CLK48)
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+ PeriphClkInitStruct.PeriphClockSelection = 0;
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+ #ifdef RT_USING_RTC
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+ PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_RTC;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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+ #endif
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+ #ifdef RCC_PERIPHCLK_CLK48
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+ PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CLK48;
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+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
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+ #endif
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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while(1)
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