import STM32F2xx branch.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1559 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm32f20x/SConscript

@@ -0,0 +1,13 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f20x_it.c']
+src_drv = ['usart.c', 'serial.c']
+
+src = src_bsp + src_drv
+CPPPATH = [str(Dir('#'))]
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/stm32f20x/SConstruct

@@ -0,0 +1,35 @@
+import os
+import sys
+import rtconfig
+
+RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-stm32.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# STM32 firemare library building script
+objs = objs + SConscript('Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
+
+# build program 
+env.Program(TARGET, objs)
+
+# end building 
+EndBuilding(TARGET)

bsp/stm32f20x/application.c

@@ -0,0 +1,103 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+#include <board.h>
+#include <rtthread.h>
+#include "stm32f2xx_eth.h"
+
+#ifdef RT_USING_DFS
+/* dfs init */
+#include <dfs_init.h>
+/* dfs filesystem:ELM filesystem init */
+#include <dfs_elm.h>
+/* dfs Filesystem APIs */
+#include <dfs_fs.h>
+#endif
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#include <lwip/api.h>
+#include <netif/ethernetif.h>
+#endif
+
+void rt_init_thread_entry(void* parameter)
+{
+/* Filesystem Initialization */
+#ifdef RT_USING_DFS
+	{
+		/* init the device filesystem */
+		dfs_init();
+
+#ifdef RT_USING_DFS_ELMFAT
+		/* init the elm chan FatFs filesystam*/
+		elm_init();
+
+		/* mount sd card fat partition 1 as root directory */
+		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+		{
+			rt_kprintf("File System initialized!\n");
+		}
+		else
+			rt_kprintf("File System initialzation failed!\n");
+#endif
+	}
+#endif
+
+/* LwIP Initialization */
+#ifdef RT_USING_LWIP
+	{
+		extern void lwip_sys_init(void);
+
+		/* register ethernetif device */
+		eth_system_device_init();
+	
+		/* initialize eth interface */
+		rt_hw_stm32_eth_init();
+	
+		/* re-init device driver */
+		rt_device_init_all();
+
+		/* init lwip system */
+		lwip_sys_init();
+		rt_kprintf("TCP/IP initialized!\n");
+	}
+#endif
+}
+
+int rt_application_init()
+{
+	rt_thread_t init_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+	init_thread = rt_thread_create("init",
+								rt_init_thread_entry, RT_NULL,
+								2048, 8, 20);
+#else
+	init_thread = rt_thread_create("init",
+								rt_init_thread_entry, RT_NULL,
+								2048, 80, 20);
+#endif
+
+	if (init_thread != RT_NULL)
+		rt_thread_startup(init_thread);
+
+	return 0;
+}
+
+/*@}*/

bsp/stm32f20x/board.c

@@ -0,0 +1,95 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <stm32f2xx.h>
+#include "board.h"
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+	/* Set the Vector Table base location at 0x20000000 */
+	NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else  /* VECT_TAB_FLASH  */
+	/* Set the Vector Table base location at 0x08000000 */
+	NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+	RCC_ClocksTypeDef  rcc_clocks;
+	rt_uint32_t         cnts;
+
+	RCC_GetClocksFreq(&rcc_clocks);
+
+	cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+
+	SysTick_Config(cnts);
+	SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_timer_handler(void)
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+void rt_hw_board_init()
+{
+	/* NVIC Configuration */
+	NVIC_Configuration();
+
+	/* Configure the SysTick */
+	SysTick_Configuration();
+
+	rt_hw_usart_init();
+	rt_console_set_device(CONSOLE_DEVICE);
+}
+
+/*@}*/

bsp/stm32f20x/board.h

@@ -0,0 +1,68 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+/* board configuration */
+// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
+// 	<i>Default: 1
+#define STM32_USE_SDIO			0
+
+/* whether use board external SRAM memory */
+// <e>Use external SRAM memory on the board
+// 	<i>Enable External SRAM memory
+#define STM32_EXT_SRAM          0
+//	<o>Begin Address of External SRAM
+//		<i>Default: 0x68000000
+#define STM32_EXT_SRAM_BEGIN    0x68000000 /* the begining address of external SRAM */
+//	<o>End Address of External SRAM
+//		<i>Default: 0x68080000
+#define STM32_EXT_SRAM_END      0x68080000 /* the end address of external SRAM */
+// </e>
+
+// <o> Internal SRAM memory size[Kbytes] <8-128>
+//	<i>Default: 64
+#define STM32_SRAM_SIZE         128
+#define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
+// 	<i>Default: 1
+#define STM32_CONSOLE_USART		1
+
+void rt_hw_board_led_on(int n);
+void rt_hw_board_led_off(int n);
+void rt_hw_board_init(void);
+
+#if STM32_CONSOLE_USART == 0
+#define CONSOLE_DEVICE "no"
+#elif STM32_CONSOLE_USART == 1
+#define CONSOLE_DEVICE "uart1"
+#elif STM32_CONSOLE_USART == 2
+#define CONSOLE_DEVICE "uart2"
+#elif STM32_CONSOLE_USART == 3
+#define CONSOLE_DEVICE "uart3"
+#endif
+
+void rt_hw_usart_init(void);
+
+/* SD Card init function */
+void rt_hw_msd_init(void);
+
+/* ETH interface init function */
+
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>

bsp/stm32f20x/project.uvopt

@@ -0,0 +1,1216 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>RT-Thread STM32</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F20x.PDF</Path>
+        </Book>
+      </Books>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments>-MPU</SimDllArguments>
+        <SimDlgDllName>DARMSTM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pSTM32F207VG</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments>-MPU</TargetDllArguments>
+        <TargetDlgDllName>TARMSTM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pSTM32F207VG</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>0</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>7</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Startup</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>.\application.c</PathWithFileName>
+      <FilenameWithoutPath>application.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>2</FileNumber>
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+      <PathWithFileName>.\startup.c</PathWithFileName>
+      <FilenameWithoutPath>startup.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>3</FileNumber>
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+      <PathWithFileName>.\board.c</PathWithFileName>
+      <FilenameWithoutPath>board.c</FilenameWithoutPath>
+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>4</FileNumber>
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+      <PathWithFileName>.\stm32f20x_it.c</PathWithFileName>
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+    </File>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>5</FileNumber>
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+      <PathWithFileName>.\usart.c</PathWithFileName>
+      <FilenameWithoutPath>usart.c</FilenameWithoutPath>
+    </File>
+    <File>
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+      <FileNumber>6</FileNumber>
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+      <PathWithFileName>.\serial.c</PathWithFileName>
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+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Kernel</GroupName>
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+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER</Define>
+              <Undefine></Undefine>
+              <IncludePath>..\..\components\finsh;.;..\..\include;Libraries\CMSIS\CM3\CoreSupport;Libraries\STM32F2xx_StdPeriph_Driver\inc;..\..\libcpu\arm\common;..\..\libcpu\arm\stm32;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>--keep __fsym_* --keep __vsym_*</Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Startup</GroupName>
+          <Files>
+            <File>
+              <FileName>application.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\application.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\startup.c</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f20x_it.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\stm32f20x_it.c</FilePath>
+            </File>
+            <File>
+              <FileName>usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\serial.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>module.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\module.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\rtm.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>slab.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\slab.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32</GroupName>
+          <Files>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\stm32\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\stm32\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>start_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\stm32\start_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>symbol.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\symbol.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32_StdPeriph</GroupName>
+          <Files>
+            <File>
+              <FileName>core_cm3.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\CMSIS\CM3\CoreSupport\core_cm3.c</FilePath>
+            </File>
+            <File>
+              <FileName>system_stm32f2xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>misc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_can.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_cryp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_cryp_aes.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_cryp_des.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_cryp_tdes.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_dac.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_dbgmcu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_dcmi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_exti.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_flash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_fsmc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_hash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_hash_md5.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_hash_sha1.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_i2c.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_iwdg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_rng.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_sdio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_syscfg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32f2xx_wwdg.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

bsp/stm32f20x/readme.txt

@@ -0,0 +1,3 @@
+1. support board
+# U-EasyTech STM32F207VG network debug board
+   - LCD

bsp/stm32f20x/rtconfig.h

@@ -0,0 +1,128 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX		8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_THREAD_DEBUG
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+#define RT_USING_DFS_ELMFAT
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* #define RT_USING_LWIP */
+/* LwIP uses RT-Thread Memory Management */
+#define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+#endif

bsp/stm32f20x/rtconfig.py

@@ -0,0 +1,114 @@
+# toolchains options
+ARCH='arm'
+CPU='stm32'
+CROSS_TOOL='keil'
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'E:/SourceryGCC/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'E:/Keil'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	IAR_PATH 	= 'E:/Program Files/IAR Systems/Embedded Workbench 5.4 Evaluation_0'	
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' --cpu DARMSTM --thumb'
+
+    CFLAGS = ''
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    CFLAGS += ' --cpu=Cortex-M3' 
+    CFLAGS += ' -e' 
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+    CFLAGS += ' -I"' + IAR_PATH + '/arm/inc"'
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    AFLAGS += ' --cpu Cortex-M3' 
+    AFLAGS += ' --fpu None' 
+    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+
+    LFLAGS = ' --config stm32f10x_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny' 
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''

bsp/stm32f20x/serial.c

@@ -0,0 +1,418 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-02-05     Bernard      first version
+ * 2009-10-25     Bernard      fix rt_serial_read bug when there is no data
+ *                             in the buffer.
+ * 2010-03-29     Bernard      cleanup code.
+ */
+
+#include "serial.h"
+#include <stm32f2xx_dma.h>
+#include <stm32f2xx_usart.h>
+
+static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
+	rt_uint32_t address, rt_uint32_t size);
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
+
+	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+	{
+		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+		{
+			rt_memset(uart->int_rx->rx_buffer, 0,
+				sizeof(uart->int_rx->rx_buffer));
+			uart->int_rx->read_index = 0;
+			uart->int_rx->save_index = 0;
+		}
+
+		if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+		{
+			RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
+			uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
+
+			/* init data node memory pool */
+			rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
+				uart->dma_tx->data_node_mem_pool,
+				sizeof(uart->dma_tx->data_node_mem_pool),
+				sizeof(struct stm32_serial_data_node));
+		}
+
+		/* Enable USART */
+		USART_Cmd(uart->uart_device, ENABLE);
+
+		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct stm32_serial_device* uart;
+
+	ptr = buffer;
+	err_code = RT_EOK;
+	uart = (struct stm32_serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* interrupt mode Rx */
+		while (size)
+		{
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			if (uart->int_rx->read_index != uart->int_rx->save_index)
+			{
+				/* read a character */
+				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+				size--;
+
+				/* move to next position */
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+			}
+			else
+			{
+				/* set error code */
+				err_code = -RT_EEMPTY;
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+	}
+	else
+	{
+		/* polling mode */
+		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+		{
+			while (uart->uart_device->SR & USART_FLAG_RXNE)
+			{
+				*ptr = uart->uart_device->DR & 0xff;
+				ptr ++;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
+	rt_uint32_t address, rt_uint32_t size)
+{
+	RT_ASSERT(dma_channel != RT_NULL);
+
+	/* disable DMA */
+	DMA_Cmd(dma_channel, DISABLE);
+
+	/* set buffer address */
+	dma_channel->M0AR = address;
+	/* set size */
+	dma_channel->NDTR = size;
+
+	/* enable DMA */
+	DMA_Cmd(dma_channel, ENABLE);
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct stm32_serial_device* uart;
+
+	err_code = RT_EOK;
+	ptr = (rt_uint8_t*)buffer;
+	uart = (struct stm32_serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		/* interrupt mode Tx, does not support */
+		RT_ASSERT(0);
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		/* DMA mode Tx */
+
+		/* allocate a data node */
+		struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
+			rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
+		if (data_node == RT_NULL)
+		{
+			/* set error code */
+			err_code = -RT_ENOMEM;
+		}
+		else
+		{
+			rt_uint32_t level;
+
+			/* fill data node */
+			data_node->data_ptr 	= ptr;
+			data_node->data_size 	= size;
+
+			/* insert to data link */
+			data_node->next = RT_NULL;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			data_node->prev = uart->dma_tx->list_tail;
+			if (uart->dma_tx->list_tail != RT_NULL)
+				uart->dma_tx->list_tail->next = data_node;
+			uart->dma_tx->list_tail = data_node;
+
+			if (uart->dma_tx->list_head == RT_NULL)
+			{
+				/* start DMA to transmit data */
+				uart->dma_tx->list_head = data_node;
+
+				/* Enable DMA Channel */
+				rt_serial_enable_dma(uart->dma_tx->dma_channel,
+					(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+					uart->dma_tx->list_head->data_size);
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+	}
+	else
+	{
+		/* polling mode */
+		if (dev->flag & RT_DEVICE_FLAG_STREAM)
+		{
+			/* stream mode */
+			while (size)
+			{
+				if (*ptr == '\n')
+				{
+					while (!(uart->uart_device->SR & USART_FLAG_TXE));
+					uart->uart_device->DR = '\r';
+				}
+
+				while (!(uart->uart_device->SR & USART_FLAG_TXE));
+				uart->uart_device->DR = (*ptr & 0x1FF);
+
+				++ptr; --size;
+			}
+		}
+		else
+		{
+			/* write data directly */
+			while (size)
+			{
+				while (!(uart->uart_device->SR & USART_FLAG_TXE));
+				uart->uart_device->DR = (*ptr & 0x1FF);
+
+				++ptr; --size;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	struct stm32_serial_device* uart;
+
+	RT_ASSERT(dev != RT_NULL);
+
+	uart = (struct stm32_serial_device*)dev->user_data;
+	switch (cmd)
+	{
+	case RT_DEVICE_CTRL_SUSPEND:
+		/* suspend device */
+		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+		USART_Cmd(uart->uart_device, DISABLE);
+		break;
+
+	case RT_DEVICE_CTRL_RESUME:
+		/* resume device */
+		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+		USART_Cmd(uart->uart_device, ENABLE);
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/*
+ * serial register for STM32
+ * support STM32F103VB and STM32F103ZE
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
+{
+	RT_ASSERT(device != RT_NULL);
+
+	if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+		(flag & RT_DEVICE_FLAG_INT_TX))
+	{
+		RT_ASSERT(0);
+	}
+
+	device->type 		= RT_Device_Class_Char;
+	device->rx_indicate = RT_NULL;
+	device->tx_complete = RT_NULL;
+	device->init 		= rt_serial_init;
+	device->open		= rt_serial_open;
+	device->close		= rt_serial_close;
+	device->read 		= rt_serial_read;
+	device->write 		= rt_serial_write;
+	device->control 	= rt_serial_control;
+	device->user_data	= serial;
+
+	/* register a character device */
+	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+	if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+	{
+		/* interrupt mode receive */
+		RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+		/* save on rx buffer */
+		while (uart->uart_device->SR & USART_FLAG_RXNE)
+		{
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			/* save character */
+			uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
+			uart->int_rx->save_index ++;
+			if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+				uart->int_rx->save_index = 0;
+
+			/* if the next position is read index, discard this 'read char' */
+			if (uart->int_rx->save_index == uart->int_rx->read_index)
+			{
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+
+		/* clear interrupt */
+		USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+
+		/* invoke callback */
+		if (device->rx_indicate != RT_NULL)
+		{
+			rt_size_t rx_length;
+
+			/* get rx length */
+			rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+				UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+				uart->int_rx->save_index - uart->int_rx->read_index;
+
+			device->rx_indicate(device, rx_length);
+		}
+	}
+
+	if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+	{
+		/* clear interrupt */
+		USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+	}
+}
+
+/*
+ * ISR for DMA mode Tx
+ */
+void rt_hw_serial_dma_tx_isr(rt_device_t device)
+{
+	rt_uint32_t level;
+	struct stm32_serial_data_node* data_node;
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+	/* DMA mode receive */
+	RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
+
+	/* get the first data node */
+	data_node = uart->dma_tx->list_head;
+	RT_ASSERT(data_node != RT_NULL);
+
+	/* invoke call to notify tx complete */
+	if (device->tx_complete != RT_NULL)
+		device->tx_complete(device, data_node->data_ptr);
+
+	/* disable interrupt */
+	level = rt_hw_interrupt_disable();
+
+	/* remove list head */
+	uart->dma_tx->list_head = data_node->next;
+	if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
+		uart->dma_tx->list_tail = RT_NULL;
+
+	/* enable interrupt */
+	rt_hw_interrupt_enable(level);
+
+	/* release data node memory */
+	rt_mp_free(data_node);
+
+	if (uart->dma_tx->list_head != RT_NULL)
+	{
+		/* transmit next data node */
+		rt_serial_enable_dma(uart->dma_tx->dma_channel,
+			(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+			uart->dma_tx->list_head->data_size);
+	}
+	else
+	{
+		/* no data to be transmitted, disable DMA */
+		DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
+	}
+}
+
+/*@}*/

bsp/stm32f20x/serial.h

@@ -0,0 +1,70 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ * 2010-03-29     Bernard      remove interrupt tx and DMA rx mode.
+ */
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/* STM32F10x library definitions */
+#include <stm32f2xx.h>
+
+#define UART_RX_BUFFER_SIZE		64
+#define UART_TX_DMA_NODE_SIZE	4
+
+/* data node for Tx Mode */
+struct stm32_serial_data_node
+{
+	rt_uint8_t *data_ptr;
+	rt_size_t  data_size;
+	struct stm32_serial_data_node *next, *prev;
+};
+struct stm32_serial_dma_tx
+{
+	/* DMA Channel */
+	DMA_Stream_TypeDef* dma_channel;
+
+	/* data list head and tail */
+	struct stm32_serial_data_node *list_head, *list_tail;
+
+	/* data node memory pool */
+	struct rt_mempool data_node_mp;
+	rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
+		(sizeof(struct stm32_serial_data_node) + sizeof(void*))];
+};
+
+struct stm32_serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct stm32_serial_device
+{
+	USART_TypeDef* uart_device;
+
+	/* rx structure */
+	struct stm32_serial_int_rx* int_rx;
+
+	/* tx structure */
+	struct stm32_serial_dma_tx* dma_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_dma_tx_isr(rt_device_t device);
+
+#endif

bsp/stm32f20x/startup.c

@@ -0,0 +1,147 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <stm32f2xx.h>
+#include "board.h"
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+#ifdef  DEBUG
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(u8* file, u32 line)
+{
+	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+	rt_kprintf("       file  %s\r\n", file);
+	rt_kprintf("       line  %d\r\n", line);
+
+	while (1) ;
+}
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init kernel object */
+	rt_system_object_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+#if STM32_EXT_SRAM
+	rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
+#else
+	#ifdef __CC_ARM
+		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
+	#elif __ICCARM__
+	    rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
+	#else
+		/* init memory system */
+		rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END);
+	#endif
+#endif
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+#ifdef RT_USING_DFS
+	/* init sdcard driver */
+#if STM32_USE_SDIO
+	rt_hw_sdcard_init();
+#else
+	rt_hw_msd_init();
+#endif
+#endif
+
+	/* init all device */
+	rt_device_init_all();
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device("uart1");
+#endif
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* init system setting */
+	SystemInit();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}
+
+/*@}*/

bsp/stm32f20x/stm32_eth.c

@@ -0,0 +1,3584 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eth.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    06/19/2009
+  * @brief   This file provides all the ETH firmware functions.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eth.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32_ETH_Driver
+  * @brief ETH driver modules
+  * @{
+  */
+
+/** @defgroup ETH_Private_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/** @defgroup ETH_Private_Defines
+  * @{
+  */
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
+ETH_DMADESCTypeDef  *DMATxDescToSet;
+ETH_DMADESCTypeDef  *DMARxDescToGet;
+ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
+ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_AddrHighBase   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
+#define ETH_MAC_AddrLowBase    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_Mask    ((uint32_t)0xFFFFFFE3)
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_Mask    ((uint32_t)0xFF20810F)
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_Mask   ((uint32_t)0x0000FF41)
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_Mask   ((uint32_t)0xF8DE3F23)
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WakeupRegisterLength      8
+/* ETHERNET Missed frames counter Shift */
+#define  ETH_DMA_RxOverflowMissedFramesCounterShift     17
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define  ETH_DMATxDesc_CollisionCountShift        3
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define  ETH_DMATxDesc_BufferSize2Shift           16
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  ETH_DMARxDesc_FrameLengthShift           16
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define  ETH_DMARxDesc_Buffer2SizeShift           16
+/* ETHERNET errors */
+#define  ETH_ERROR              ((uint32_t)0)
+#define  ETH_SUCCESS            ((uint32_t)1)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Variables
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_FunctionPrototypes
+  * @{
+  */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ETHERNET peripheral registers to their
+  *   default reset values.
+  * @param  None
+  * @retval : None
+  */
+void ETH_DeInit(void)
+{
+  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
+  RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the ETHERNET peripheral according to the specified
+  *   parameters in the ETH_InitStruct .
+  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
+  *   that contains the configuration information for the
+  *   specified ETHERNET peripheral.
+  * @param PHYAddress: external PHY address
+  * @retval : ETH_ERROR: Ethernet initialization failed
+  *   ETH_SUCCESS: Ethernet successfully initialized
+  */
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
+{
+  uint32_t RegValue = 0, tmpreg = 0;
+  __IO uint32_t i = 0;
+  RCC_ClocksTypeDef  rcc_clocks;
+  uint32_t hclk = 60000000;
+  __IO uint32_t timeout = 0;
+  /* Check the parameters */
+  /* MAC --------------------------*/
+  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
+  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
+  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
+  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
+  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
+  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
+  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
+  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
+  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
+  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
+  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
+  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
+  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
+  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
+  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
+  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
+  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
+  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
+  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
+  assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
+  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
+  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
+  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
+  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
+  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
+  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
+  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
+  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
+  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
+  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
+  /* DMA --------------------------*/
+  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
+  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
+  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
+  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
+  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
+  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
+  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
+  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
+  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
+  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
+  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
+  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
+  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
+  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
+  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
+  /*-------------------------------- MAC Config ------------------------------*/
+  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIAR;
+  /* Clear CSR Clock Range CR[2:0] bits */
+  tmpreg &= MACMIIAR_CR_Mask;
+  /* Get hclk frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  hclk = rcc_clocks.HCLK_Frequency;
+  /* Set CR bits depending on hclk value */
+  if((hclk >= 20000000)&&(hclk < 35000000))
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+  }
+  else if((hclk >= 35000000)&&(hclk < 60000000))
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+  }
+  else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
+  {
+    /* CSR Clock Range between 60-72 MHz */
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+  }
+  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+  ETH->MACMIIAR = (uint32_t)tmpreg;
+  /*-------------------- PHY initialization and configuration ----------------*/
+  /* Put the PHY in reset mode */
+  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
+  {
+    /* Return ERROR in case of write timeout */
+    return ETH_ERROR;
+  }
+
+  /* Delay to assure PHY reset */
+  for(i = PHY_ResetDelay; i != 0; i--)
+  {
+  }
+
+  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
+  {
+    /* We wait for linked satus... */
+    do
+    {
+      timeout++;
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+      return ETH_ERROR;
+    }
+    /* Reset Timeout counter */
+    timeout = 0;
+
+    /* Enable Auto-Negotiation */
+    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+
+    /* Wait until the autonegotiation will be completed */
+    do
+    {
+      timeout++;
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+      return ETH_ERROR;
+    }
+    /* Reset Timeout counter */
+    timeout = 0;
+
+    /* Read the result of the autonegotiation */
+    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
+
+    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
+    if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
+    {
+      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
+      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
+
+    }
+    else
+    {
+      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
+      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+    }
+    /* Configure the MAC with the speed fixed by the autonegotiation process */
+    if(RegValue & PHY_Speed_Status)
+    {
+      /* Set Ethernet speed to 10M following the autonegotiation */
+      ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+    }
+    else
+    {
+      /* Set Ethernet speed to 100M following the autonegotiation */
+      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
+    }
+  }
+  else
+  {
+    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
+                                                   (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+    /* Delay to assure PHY configuration */
+    for(i = PHY_ConfigDelay; i != 0; i--)
+    {
+    }
+  }
+  /*------------------------ ETHERNET MACCR Configuration --------------------*/
+  /* Get the ETHERNET MACCR value */
+  tmpreg = ETH->MACCR;
+  /* Clear WD, PCE, PS, TE and RE bits */
+  tmpreg &= MACCR_CLEAR_Mask;
+  /* Set the WD bit according to ETH_Watchdog value */
+  /* Set the JD: bit according to ETH_Jabber value */
+  /* Set the IFG bit according to ETH_InterFrameGap value */
+  /* Set the DCRS bit according to ETH_CarrierSense value */
+  /* Set the FES bit according to ETH_Speed value */
+  /* Set the DO bit according to ETH_ReceiveOwn value */
+  /* Set the LM bit according to ETH_LoopbackMode value */
+  /* Set the DM bit according to ETH_Mode value */
+  /* Set the IPC bit according to ETH_ChecksumOffload value */
+  /* Set the DR bit according to ETH_RetryTransmission value */
+  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
+  /* Set the BL bit according to ETH_BackOffLimit value */
+  /* Set the DC bit according to ETH_DeferralCheck value */
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
+                  ETH_InitStruct->ETH_Jabber |
+                  ETH_InitStruct->ETH_InterFrameGap |
+                  ETH_InitStruct->ETH_CarrierSense |
+                  ETH_InitStruct->ETH_Speed |
+                  ETH_InitStruct->ETH_ReceiveOwn |
+                  ETH_InitStruct->ETH_LoopbackMode |
+                  ETH_InitStruct->ETH_Mode |
+                  ETH_InitStruct->ETH_ChecksumOffload |
+                  ETH_InitStruct->ETH_RetryTransmission |
+                  ETH_InitStruct->ETH_AutomaticPadCRCStrip |
+                  ETH_InitStruct->ETH_BackOffLimit |
+                  ETH_InitStruct->ETH_DeferralCheck);
+  /* Write to ETHERNET MACCR */
+  ETH->MACCR = (uint32_t)tmpreg;
+
+  /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+  /* Set the RA bit according to ETH_ReceiveAll value */
+  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
+  /* Set the PCF bit according to ETH_PassControlFrames value */
+  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
+  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
+  /* Set the PR bit according to ETH_PromiscuousMode value */
+  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
+  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
+  /* Write to ETHERNET MACFFR */
+  ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
+                          ETH_InitStruct->ETH_SourceAddrFilter |
+                          ETH_InitStruct->ETH_PassControlFrames |
+                          ETH_InitStruct->ETH_BroadcastFramesReception |
+                          ETH_InitStruct->ETH_DestinationAddrFilter |
+                          ETH_InitStruct->ETH_PromiscuousMode |
+                          ETH_InitStruct->ETH_MulticastFramesFilter |
+                          ETH_InitStruct->ETH_UnicastFramesFilter);
+  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+  /* Write to ETHERNET MACHTHR */
+  ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
+  /* Write to ETHERNET MACHTLR */
+  ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
+  /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+  /* Get the ETHERNET MACFCR value */
+  tmpreg = ETH->MACFCR;
+  /* Clear xx bits */
+  tmpreg &= MACFCR_CLEAR_Mask;
+
+  /* Set the PT bit according to ETH_PauseTime value */
+  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
+  /* Set the PLT bit according to ETH_PauseLowThreshold value */
+  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
+  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
+  /* Set the TFE bit according to ETH_TransmitFlowControl value */
+  tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
+                   ETH_InitStruct->ETH_ZeroQuantaPause |
+                   ETH_InitStruct->ETH_PauseLowThreshold |
+                   ETH_InitStruct->ETH_UnicastPauseFrameDetect |
+                   ETH_InitStruct->ETH_ReceiveFlowControl |
+                   ETH_InitStruct->ETH_TransmitFlowControl);
+  /* Write to ETHERNET MACFCR */
+  ETH->MACFCR = (uint32_t)tmpreg;
+  /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+  /* Set the ETV bit according to ETH_VLANTagComparison value */
+  /* Set the VL bit according to ETH_VLANTagIdentifier value */
+  ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
+                             ETH_InitStruct->ETH_VLANTagIdentifier);
+
+  /*-------------------------------- DMA Config ------------------------------*/
+  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+  /* Get the ETHERNET DMAOMR value */
+  tmpreg = ETH->DMAOMR;
+  /* Clear xx bits */
+  tmpreg &= DMAOMR_CLEAR_Mask;
+
+  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
+  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
+  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
+  /* Set the TSF bit according to ETH_TransmitStoreForward value */
+  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
+  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
+  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
+  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
+  /* Set the OSF bit according to ETH_SecondFrameOperate value */
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
+                  ETH_InitStruct->ETH_ReceiveStoreForward |
+                  ETH_InitStruct->ETH_FlushReceivedFrame |
+                  ETH_InitStruct->ETH_TransmitStoreForward |
+                  ETH_InitStruct->ETH_TransmitThresholdControl |
+                  ETH_InitStruct->ETH_ForwardErrorFrames |
+                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
+                  ETH_InitStruct->ETH_ReceiveThresholdControl |
+                  ETH_InitStruct->ETH_SecondFrameOperate);
+  /* Write to ETHERNET DMAOMR */
+  ETH->DMAOMR = (uint32_t)tmpreg;
+
+  /*----------------------- ETHERNET DMABMR Configuration --------------------*/
+  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
+  /* Set the FB bit according to ETH_FixedBurst value */
+  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
+  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
+  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
+  /* Set the PR and DA bits according to ETH_DMAArbitration value */
+  ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
+                          ETH_InitStruct->ETH_FixedBurst |
+                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                          ETH_InitStruct->ETH_TxDMABurstLength |
+                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
+                          ETH_InitStruct->ETH_DMAArbitration |
+                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+  /* Return Ethernet configuration success */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Fills each ETH_InitStruct member with its default value.
+  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
+  *   which will be initialized.
+  * @retval : None
+  */
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
+{
+  /* ETH_InitStruct members default value */
+  /*------------------------   MAC   -----------------------------------*/
+  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
+  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
+  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
+  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
+  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
+  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
+  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
+  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
+  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
+  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
+  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
+  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
+  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
+  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
+  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+  ETH_InitStruct->ETH_HashTableHigh = 0x0;
+  ETH_InitStruct->ETH_HashTableLow = 0x0;
+  ETH_InitStruct->ETH_PauseTime = 0x0;
+  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
+  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
+  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
+  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
+  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
+  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
+  /*------------------------   DMA   -----------------------------------*/
+  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
+  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
+  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
+  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
+  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
+  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
+  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
+  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
+}
+
+/**
+  * @brief  Enables ENET MAC and DMA reception/transmission
+  * @param  None
+  * @retval : None
+  */
+void ETH_Start(void)
+{
+  /* Enable transmit state machine of the MAC for transmission on the MII */
+  ETH_MACTransmissionCmd(ENABLE);
+  /* Flush Transmit FIFO */
+  ETH_FlushTransmitFIFO();
+  /* Enable receive state machine of the MAC for reception from the MII */
+  ETH_MACReceptionCmd(ENABLE);
+
+  /* Start DMA transmission */
+  ETH_DMATransmissionCmd(ENABLE);
+  /* Start DMA reception */
+  ETH_DMAReceptionCmd(ENABLE);
+}
+
+/**
+  * @brief  Transmits a packet, from application buffer, pointed by ppkt.
+  * @param ppkt: pointer to application packet buffer to transmit.
+  * @param FrameLength: Tx Packet size.
+  * @retval : ETH_ERROR: in case of Tx desc owned by DMA
+  *   ETH_SUCCESS: for correct transmission
+  */
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
+{
+  uint32_t offset = 0;
+
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+  for(offset=0; offset<FrameLength; offset++)
+  {
+    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+
+  /* Setting the Frame Length: bits[12:0] */
+  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_TBUS;
+    /* Resume DMA transmission*/
+    ETH->DMATPDR = 0;
+  }
+
+  /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
+  /* Chained Mode */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Tx descriptor list for next buffer to send */
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
+  }
+  else /* Ring Mode */
+  {
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer to send */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+  /* Return SUCCESS */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Receives a packet and copies it to memory pointed by ppkt.
+  * @param  ppkt: pointer to application packet receive buffer.
+  * @retval : ETH_ERROR: if there is error in reception
+  *   framelength: received packet size if packet reception is correct
+  */
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
+{
+  uint32_t offset = 0, framelength = 0;
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR;
+  }
+
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+  {
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+    for(offset=0; offset<framelength; offset++)
+    {
+      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+    }
+  }
+  else
+  {
+    /* Return ERROR */
+    framelength = ETH_ERROR;
+  }
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_RBUS;
+    /* Resume DMA reception */
+    ETH->DMARPDR = 0;
+  }
+
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer to read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+
+  /* Return Frame Length/ERROR */
+  return (framelength);
+}
+
+/**
+  * @brief  Get the size of received the received packet.
+  * @param  None
+  * @retval : framelength: received packet size
+  */
+uint32_t ETH_GetRxPktSize(void)
+{
+  uint32_t frameLength = 0;
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+  {
+    /* Get the size of the packet: including 4 bytes of the CRC */
+    frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
+  }
+
+ /* Return Frame Length */
+ return frameLength;
+}
+
+/**
+  * @brief  Drop a Received packet (too small packet, etc...)
+  * @param  None
+  * @retval : None
+  */
+void ETH_DropRxPkt(void)
+{
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer read: this will
+         be the first Rx descriptor in this case */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+}
+
+/*---------------------------------  PHY  ------------------------------------*/
+/**
+  * @brief  Read a PHY register
+  * @param PHYAddress: PHY device address, is the index of one of supported
+  *   32 PHY devices.
+  *   This parameter can be one of the following values: 0,..,31
+  * @param PHYReg: PHY register address, is the index of one of the 32
+  *   PHY register.
+  *   This parameter can be one of the following values:
+  * @arg PHY_BCR    : Tranceiver Basic Control Register
+  * @arg PHY_BSR    : Tranceiver Basic Status Register
+  * @arg PHY_SR     : Tranceiver Status Register
+  * @arg More PHY register could be read depending on the used PHY
+  * @retval : ETH_ERROR: in case of timeout
+  *   MAC MIIDR register value: Data read from the selected PHY register (correct read )
+  */
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
+{
+  uint32_t tmpreg = 0;
+__IO uint32_t timeout = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_ETH_PHY_REG(PHYReg));
+
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIAR;
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_Mask;
+  /* Prepare the MII address register value */
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
+  tmpreg &= ~ETH_MACMIIAR_MW;                              /* Set the read mode */
+  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
+  /* Write the result value into the MII Address register */
+  ETH->MACMIIAR = tmpreg;
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH->MACMIIAR;
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return (uint16_t)ETH_ERROR;
+  }
+
+  /* Return data register value */
+  return (uint16_t)(ETH->MACMIIDR);
+}
+
+/**
+  * @brief  Write to a PHY register
+  * @param PHYAddress: PHY device address, is the index of one of supported
+  *   32 PHY devices.
+  *   This parameter can be one of the following values: 0,..,31
+  * @param PHYReg: PHY register address, is the index of one of the 32
+  *   PHY register.
+  *   This parameter can be one of the following values:
+  * @arg PHY_BCR    : Tranceiver Control Register
+  * @arg More PHY register could be written depending on the used PHY
+  * @param PHYValue: the value to write
+  * @retval : ETH_ERROR: in case of timeout
+  *   ETH_SUCCESS: for correct write
+  */
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
+{
+  uint32_t tmpreg = 0;
+  __IO uint32_t timeout = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_ETH_PHY_REG(PHYReg));
+
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIAR;
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_Mask;
+  /* Prepare the MII register address value */
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
+  tmpreg |= ETH_MACMIIAR_MW;                               /* Set the write mode */
+  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
+  /* Give the value to the MII data register */
+  ETH->MACMIIDR = PHYValue;
+  /* Write the result value into the MII Address register */
+  ETH->MACMIIAR = tmpreg;
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH->MACMIIAR;
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_WRITE_TO)
+  {
+    return ETH_ERROR;
+  }
+
+  /* Return SUCCESS */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Enables or disables the PHY loopBack mode.
+  * @param PHYAddress: PHY device address, is the index of one of supported
+  *   32 PHY devices.
+  *   This parameter can be one of the following values:
+  * @param NewState: new state of the PHY loopBack mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  *   Note: Don't be confused with ETH_MACLoopBackCmd function
+  *   which enables internal loopback at MII level
+  * @retval : ETH_ERROR: in case of bad PHY configuration
+  *   ETH_SUCCESS: for correct PHY configuration
+  */
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the PHY configuration to update it */
+  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PHY loopback mode */
+    tmpreg |= PHY_Loopback;
+  }
+  else
+  {
+    /* Disable the PHY loopback mode: normal mode */
+    tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
+  }
+  /* Update the PHY control register with the new configuration */
+  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
+  {
+    return ETH_SUCCESS;
+  }
+  else
+  {
+    /* Return SUCCESS */
+    return ETH_ERROR;
+  }
+}
+
+/*---------------------------------  MAC  ------------------------------------*/
+/**
+  * @brief  Enables or disables the MAC transmission.
+  * @param NewState: new state of the MAC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MACTransmissionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC transmission */
+    ETH->MACCR |= ETH_MACCR_TE;
+  }
+  else
+  {
+    /* Disable the MAC transmission */
+    ETH->MACCR &= ~ETH_MACCR_TE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC reception.
+  * @param NewState: new state of the MAC reception.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MACReceptionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC reception */
+    ETH->MACCR |= ETH_MACCR_RE;
+  }
+  else
+  {
+    /* Disable the MAC reception */
+    ETH->MACCR &= ~ETH_MACCR_RE;
+  }
+}
+
+/**
+  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
+  * @param  None
+  * @retval : The new state of flow control busy status bit (SET or RESET).
+  */
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  /* The Flow Control register should not be written to until this bit is cleared */
+  if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Initiate a Pause Control Frame (Full-duplex only).
+  * @param  None
+  * @retval : None
+  */
+void ETH_InitiatePauseControlFrame(void)
+{
+  /* When Set In full duplex MAC initiates pause control frame */
+  ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+/**
+  * @brief  Enables or disables the MAC BackPressure operation activation (Half-duplex only).
+  * @param NewState: new state of the MAC BackPressure operation activation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_BackPressureActivationCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Activate the MAC BackPressure operation */
+    /* In Half duplex: during backpressure, when the MAC receives a new frame,
+    the transmitter starts sending a JAM pattern resulting in a collision */
+    ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+  }
+  else
+  {
+    /* Desactivate the MAC BackPressure operation */
+    ETH->MACFCR &= ~ETH_MACFCR_FCBBPA;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
+  * @param ETH_MAC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
+  * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+  * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+  * @arg ETH_MAC_FLAG_MMC  : MMC flag
+  * @arg ETH_MAC_FLAG_PMT  : PMT flag
+  * @retval : The new state of ETHERNET MAC flag (SET or RESET).
+  */
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
+  if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC interrupt has occurred or not.
+  * @param ETH_MAC_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_IT_TST   : Time stamp trigger interrupt
+  * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt
+  * @arg ETH_MAC_IT_MMCR : MMC receive interrupt
+  * @arg ETH_MAC_IT_MMC  : MMC interrupt
+  * @arg ETH_MAC_IT_PMT  : PMT interrupt
+  * @retval : The new state of ETHERNET MAC interrupt (SET or RESET).
+  */
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
+  if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET MAC interrupts.
+  * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+  * @arg ETH_MAC_IT_PMT : PMT interrupt
+  * @param NewState: new state of the specified ETHERNET MAC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC interrupts */
+    ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC interrupts */
+    ETH->MACIMR |= ETH_MAC_IT;
+  }
+}
+
+/**
+  * @brief  Configures the selected MAC address.
+  * @param MacAddr: The MAC addres to configure.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_Address0 : MAC Address0
+  * @arg ETH_MAC_Address1 : MAC Address1
+  * @arg ETH_MAC_Address2 : MAC Address2
+  * @arg ETH_MAC_Address3 : MAC Address3
+  * @param Addr: Pointer on MAC address buffer data (6 bytes).
+  * @retval : None
+  */
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+  /* Calculate the selectecd MAC address high register */
+  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+  /* Load the selectecd MAC address high register */
+  (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg;
+  /* Calculate the selectecd MAC address low register */
+  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+
+  /* Load the selectecd MAC address low register */
+  (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg;
+}
+
+/**
+  * @brief  Get the selected MAC address.
+  * @param MacAddr: The MAC addres to return.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_Address0 : MAC Address0
+  * @arg ETH_MAC_Address1 : MAC Address1
+  * @arg ETH_MAC_Address2 : MAC Address2
+  * @arg ETH_MAC_Address3 : MAC Address3
+  * @param Addr: Pointer on MAC address buffer data (6 bytes).
+  * @retval : None
+  */
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+  /* Get the selectecd MAC address high register */
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr));
+
+  /* Calculate the selectecd MAC address buffer */
+  Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
+  Addr[4] = (tmpreg & (uint8_t)0xFF);
+  /* Load the selectecd MAC address low register */
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr));
+  /* Calculate the selectecd MAC address buffer */
+  Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
+  Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
+  Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
+  Addr[0] = (tmpreg & (uint8_t)0xFF);
+}
+
+/**
+  * @brief  Enables or disables the Address filter module uses the specified
+  *   ETHERNET MAC address for perfect filtering
+  * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_Address1 : MAC Address1
+  * @arg ETH_MAC_Address2 : MAC Address2
+  * @arg ETH_MAC_Address3 : MAC Address3
+  * @param NewState: new state of the specified ETHERNET MAC address use.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC address for perfect filtering */
+    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC address for perfect filtering */
+    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
+  }
+}
+
+/**
+  * @brief  Set the filter type for the specified ETHERNET MAC address
+  * @param MacAddr: specifies the ETHERNET MAC address
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_Address1 : MAC Address1
+  * @arg ETH_MAC_Address2 : MAC Address2
+  * @arg ETH_MAC_Address3 : MAC Address3
+  * @param Filter: specifies the used frame received field for comparaison
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare
+  *   with the SA fields of the received frame.
+  * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare
+  *   with the DA fields of the received frame.
+  * @retval : None
+  */
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
+
+  if (Filter != ETH_MAC_AddressFilter_DA)
+  {
+    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
+       received frame. */
+    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA;
+  }
+  else
+  {
+    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
+       received frame. */
+    (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
+  }
+}
+
+/**
+  * @brief  Set the filter type for the specified ETHERNET MAC address
+  * @param MacAddr: specifies the ETHERNET MAC address
+  *   This parameter can be one of the following values:
+  * @arg ETH_MAC_Address1 : MAC Address1
+  * @arg ETH_MAC_Address2 : MAC Address2
+  * @arg ETH_MAC_Address3 : MAC Address3
+  * @param MaskByte: specifies the used address bytes for comparaison
+  *   This parameter can be any combination of the following values:
+  * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
+  * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
+  * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
+  * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
+  * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
+  * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
+  * @retval : None
+  */
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
+
+  /* Clear MBC bits in the selected MAC address  high register */
+  (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
+  /* Set the selected Filetr mask bytes */
+  (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte;
+}
+/*------------------------  DMA Tx/Rx Desciptors -----------------------------*/
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode.
+  * @param DMATxDescTab: Pointer on the first Tx desc list
+  * @param TxBuff: Pointer on the first TxBuffer list
+  * @param TxBuffCount: Number of the used Tx desc in the list
+  * @retval : None
+  */
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+    /* Set Second Address Chained bit */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH;
+
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+    }
+  }
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLAR = (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in ring mode.
+  * @param DMATxDescTab: Pointer on the first Tx desc list
+  * @param TxBuff1: Pointer on the first TxBuffer1 list
+  * @param TxBuff2: Pointer on the first TxBuffer2 list
+  * @param TxBuffCount: Number of the used Tx desc in the list
+  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
+  *   for the number of Words to skip between two unchained descriptors.
+  * @retval : None
+  */
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Buffer2 address pointer */
+    DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (TxBuffCount-1))
+    {
+      /* Set Transmit End of Ring bit */
+      DMATxDesc->Status = ETH_DMATxDesc_TER;
+    }
+  }
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLAR =  (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param ETH_DMATxDescFlag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
+  * @arg ETH_DMATxDesc_IC  : Interrupt on completetion
+  * @arg ETH_DMATxDesc_LS  : Last Segment
+  * @arg ETH_DMATxDesc_FS  : First Segment
+  * @arg ETH_DMATxDesc_DC  : Disable CRC
+  * @arg ETH_DMATxDesc_DP  : Disable Pad
+  * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
+  * @arg ETH_DMATxDesc_TER : Transmit End of Ring
+  * @arg ETH_DMATxDesc_TCH : Second Address Chained
+  * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
+  * @arg ETH_DMATxDesc_IHE : IP Header Error
+  * @arg ETH_DMATxDesc_ES  : Error summary
+  * @arg ETH_DMATxDesc_JT  : Jabber Timeout
+  * @arg ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
+  * @arg ETH_DMATxDesc_PCE : Payload Checksum Error
+  * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
+  * @arg ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the tranceiver
+  * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
+  * @arg ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
+  * @arg ETH_DMATxDesc_VF  : VLAN Frame
+  * @arg ETH_DMATxDesc_CC  : Collision Count
+  * @arg ETH_DMATxDesc_ED  : Excessive Deferral
+  * @arg ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
+  * @arg ETH_DMATxDesc_DB  : Deferred Bit
+  * @retval : The new state of ETH_DMATxDescFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
+
+  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @retval : The Transmit descriptor collision counter value.
+  */
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift);
+}
+
+/**
+  * @brief  Set the specified DMA Tx Desc Own bit.
+  * @param DMATxDesc: Pointer on a Tx desc
+  * @retval : None
+  */
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Set the DMA Tx Desc Own bit */
+  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
+  * @param DMATxDesc: Pointer on a Tx desc
+  * @param NewState: new state of the DMA Tx Desc transmit interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status |= ETH_DMATxDesc_IC;
+  }
+  else
+  {
+    /* Disable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
+  * @param DMATxDesc: Pointer on a Tx desc
+  * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment
+  * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
+  * @retval : None
+  */
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
+
+  /* Selects the DMA Tx Desc Frame segment */
+  DMATxDesc->Status |= DMATxDesc_FrameSegment;
+}
+
+/**
+  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
+  * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
+  * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+  * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+  * @retval : None
+  */
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
+
+  /* Set the selected DMA Tx desc checksum insertion control */
+  DMATxDesc->Status |= DMATxDesc_Checksum;
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc CRC.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param NewState: new state of the specified DMA Tx Desc CRC.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status |= ETH_DMATxDesc_DC;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc end of ring.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param NewState: new state of the specified DMA Tx Desc end of ring.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status |= ETH_DMATxDesc_TER;
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER);
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc second address chained.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param NewState: new state of the specified DMA Tx Desc second address chained.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status |= ETH_DMATxDesc_TCH;
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH);
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param NewState: new state of the specified DMA Tx Desc padding for
+  *   frame shorter than 64 bytes.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
+    DMATxDesc->Status |= ETH_DMATxDesc_DP;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc time stamp.
+  * @param DMATxDesc: pointer on a DMA Tx descriptor
+  * @param NewState: new state of the specified DMA Tx Desc time stamp.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE);
+  }
+}
+
+/**
+  * @brief  Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
+  * @param DMATxDesc: Pointer on a Tx desc
+  * @param BufferSize1: specifies the Tx desc buffer1 size.
+  * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
+  * @retval : None
+  */
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
+
+  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
+  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift));
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param DMARxDescTab: Pointer on the first Rx desc list
+  * @param RxBuff: Pointer on the first RxBuffer list
+  * @param RxBuffCount: Number of the used Rx desc in the list
+  * @retval : None
+  */
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab;
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+    }
+  }
+
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLAR = (uint32_t) DMARxDescTab;
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in ring mode.
+  * @param DMARxDescTab: Pointer on the first Rx desc list
+  * @param RxBuff1: Pointer on the first RxBuffer1 list
+  * @param RxBuff2: Pointer on the first RxBuffer2 list
+  * @param RxBuffCount: Number of the used Rx desc in the list
+  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
+  *   for the number of Words to skip between two unchained descriptors.
+  * @retval : None
+  */
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab;
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+    /* Set Buffer1 size */
+    DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Buffer2 address pointer */
+    DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (RxBuffCount-1))
+    {
+      /* Set Receive End of Ring bit */
+      DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+    }
+  }
+
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLAR = (uint32_t) DMARxDescTab;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
+  * @param DMARxDesc: pointer on a DMA Rx descriptor
+  * @param ETH_DMARxDescFlag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine
+  * @arg ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
+  * @arg ETH_DMARxDesc_ES:          Error summary
+  * @arg ETH_DMARxDesc_DE:          Desciptor error: no more descriptors for receive frame
+  * @arg ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
+  * @arg ETH_DMARxDesc_LE:          Frame size not matching with length field
+  * @arg ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
+  * @arg ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
+  * @arg ETH_DMARxDesc_FS:          First descriptor of the frame
+  * @arg ETH_DMARxDesc_LS:          Last descriptor of the frame
+  * @arg ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
+  * @arg ETH_DMARxDesc_LC:          Late collision occurred during reception
+  * @arg ETH_DMARxDesc_FT:          Frame type - Ethernet, otherwise 802.3
+  * @arg ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
+  * @arg ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
+  * @arg ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
+  * @arg ETH_DMARxDesc_CE:          CRC error
+  * @arg ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+  * @retval : The new state of ETH_DMARxDescFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
+  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set the specified DMA Rx Desc Own bit.
+  * @param DMARxDesc: Pointer on a Rx desc
+  * @retval : None
+  */
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Set the DMA Rx Desc Own bit */
+  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
+}
+
+/**
+  * @brief  Returns the specified DMA Rx Desc frame length.
+  * @param DMARxDesc: pointer on a DMA Rx descriptor
+  * @retval : The Rx descriptor received frame length.
+  */
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift);
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Rx Desc receive interrupt.
+  * @param DMARxDesc: Pointer on a Rx desc
+  * @param NewState: new state of the specified DMA Rx Desc interrupt.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
+  }
+  else
+  {
+    /* Disable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Rx Desc end of ring.
+  * @param DMARxDesc: pointer on a DMA Rx descriptor
+  * @param NewState: new state of the specified DMA Rx Desc end of ring.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER);
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Rx Desc second address chained.
+  * @param DMARxDesc: pointer on a DMA Rx descriptor
+  * @param NewState: new state of the specified DMA Rx Desc second address chained.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH);
+  }
+}
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Rx Desc buffer size.
+  * @param DMARxDesc: pointer on a DMA Rx descriptor
+  * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
+  *   This parameter can be any one of the following values:
+  * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
+  * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
+  * @retval : The Receive descriptor frame length.
+  */
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
+
+  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
+  {
+    /* Return the DMA Rx Desc buffer2 size */
+    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift);
+  }
+  else
+  {
+    /* Return the DMA Rx Desc buffer1 size */
+    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
+  }
+}
+
+/*---------------------------------  DMA  ------------------------------------*/
+/**
+  * @brief  Resets all MAC subsystem internal registers and logic.
+  * @param  None
+  * @retval : None
+  */
+void ETH_SoftwareReset(void)
+{
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+/**
+  * @brief  Checks whether the ETHERNET software reset bit is set or not.
+  * @param  None
+  * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET).
+  */
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+  * @param ETH_DMA_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
+  * @arg ETH_DMA_FLAG_PMT : PMT flag
+  * @arg ETH_DMA_FLAG_MMC : MMC flag
+  * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
+  * @arg ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
+  * @arg ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
+  * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+  * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+  * @arg ETH_DMA_FLAG_ER  : Early receive flag
+  * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
+  * @arg ETH_DMA_FLAG_ET  : Early transmit flag
+  * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+  * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
+  * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+  * @arg ETH_DMA_FLAG_R   : Receive flag
+  * @arg ETH_DMA_FLAG_TU  : Underflow flag
+  * @arg ETH_DMA_FLAG_RO  : Overflow flag
+  * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+  * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+  * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
+  * @arg ETH_DMA_FLAG_T   : Transmit flag
+  * @retval : The new state of ETH_DMA_FLAG (SET or RESET).
+  */
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
+  if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ETHERNET’s DMA pending flag.
+  * @param ETH_DMA_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+  * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+  * @arg ETH_DMA_FLAG_ER  : Early receive flag
+  * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
+  * @arg ETH_DMA_FLAG_ETI : Early transmit flag
+  * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+  * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
+  * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+  * @arg ETH_DMA_FLAG_R   : Receive flag
+  * @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag
+  * @arg ETH_DMA_FLAG_RO  : Receive Overflow flag
+  * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+  * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+  * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
+  * @arg ETH_DMA_FLAG_T   : Transmit flag
+  * @retval : None
+  */
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
+
+  /* Clear the selected ETHERNET DMA FLAG */
+  ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA interrupt has occured or not.
+  * @param ETH_DMA_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
+  * @arg ETH_DMA_IT_PMT : PMT interrupt
+  * @arg ETH_DMA_IT_MMC : MMC interrupt
+  * @arg ETH_DMA_IT_NIS : Normal interrupt summary
+  * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
+  * @arg ETH_DMA_IT_ER  : Early receive interrupt
+  * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
+  * @arg ETH_DMA_IT_ET  : Early transmit interrupt
+  * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+  * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
+  * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+  * @arg ETH_DMA_IT_R   : Receive interrupt
+  * @arg ETH_DMA_IT_TU  : Underflow interrupt
+  * @arg ETH_DMA_IT_RO  : Overflow interrupt
+  * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+  * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+  * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
+  * @arg ETH_DMA_IT_T   : Transmit interrupt
+  * @retval : The new state of ETH_DMA_IT (SET or RESET).
+  */
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
+  if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ETHERNET’s DMA IT pending bit.
+  * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  * @arg ETH_DMA_IT_NIS : Normal interrupt summary
+  * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
+  * @arg ETH_DMA_IT_ER  : Early receive interrupt
+  * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
+  * @arg ETH_DMA_IT_ETI : Early transmit interrupt
+  * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+  * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
+  * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+  * @arg ETH_DMA_IT_R   : Receive interrupt
+  * @arg ETH_DMA_IT_TU  : Transmit Underflow interrupt
+  * @arg ETH_DMA_IT_RO  : Receive Overflow interrupt
+  * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+  * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+  * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
+  * @arg ETH_DMA_IT_T   : Transmit interrupt
+  * @retval : None
+  */
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+
+  /* Clear the selected ETHERNET DMA IT */
+  ETH->DMASR = (uint32_t) ETH_DMA_IT;
+}
+
+/**
+  * @brief  Returns the ETHERNET DMA Transmit Process State.
+  * @param  None
+  * @retval : The new ETHERNET DMA Transmit Process State:
+  *   This can be one of the following values:
+  * - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
+  * - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor
+  * - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
+  * - ETH_DMA_TransmitProcess_Reading   : unning - reading the data from host memory
+  * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
+  * - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor
+  */
+uint32_t ETH_GetTransmitProcessState(void)
+{
+  return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS));
+}
+
+/**
+  * @brief  Returns the ETHERNET DMA Receive Process State.
+  * @param  None
+  * @retval : The new ETHERNET DMA Receive Process State:
+  *   This can be one of the following values:
+  * - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
+  * - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor
+  * - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
+  * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
+  * - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
+  * - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the recieve frame into host memory
+  */
+uint32_t ETH_GetReceiveProcessState(void)
+{
+  return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS));
+}
+
+/**
+  * @brief  Clears the ETHERNET transmit FIFO.
+  * @param  None
+  * @retval : None
+  */
+void ETH_FlushTransmitFIFO(void)
+{
+  /* Set the Flush Transmit FIFO bit */
+  ETH->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+/**
+  * @brief  Checks whether the ETHERNET transmit FIFO bit is cleared or not.
+  * @param  None
+  * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
+  */
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the DMA transmission.
+  * @param NewState: new state of the DMA transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMATransmissionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transmission */
+    ETH->DMAOMR |= ETH_DMAOMR_ST;
+  }
+  else
+  {
+    /* Disable the DMA transmission */
+    ETH->DMAOMR &= ~ETH_DMAOMR_ST;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA reception.
+  * @param NewState: new state of the DMA reception.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMAReceptionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA reception */
+    ETH->DMAOMR |= ETH_DMAOMR_SR;
+  }
+  else
+  {
+    /* Disable the DMA reception */
+    ETH->DMAOMR &= ~ETH_DMAOMR_SR;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET DMA interrupts.
+  * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  * @arg ETH_DMA_IT_NIS : Normal interrupt summary
+  * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
+  * @arg ETH_DMA_IT_ER  : Early receive interrupt
+  * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
+  * @arg ETH_DMA_IT_ET  : Early transmit interrupt
+  * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+  * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
+  * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+  * @arg ETH_DMA_IT_R   : Receive interrupt
+  * @arg ETH_DMA_IT_TU  : Underflow interrupt
+  * @arg ETH_DMA_IT_RO  : Overflow interrupt
+  * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+  * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+  * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
+  * @arg ETH_DMA_IT_T   : Transmit interrupt
+  * @param NewState: new state of the specified ETHERNET DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET DMA interrupts */
+    ETH->DMAIER |= ETH_DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET DMA interrupts */
+    ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
+  * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
+  * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
+  * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET).
+  */
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
+
+  if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
+  * @param  None
+  * @retval : The value of Rx overflow Missed Frame Counter.
+  */
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
+{
+  return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
+  * @param  None
+  * @retval : The value of Buffer unavailable Missed Frame Counter.
+  */
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+  return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHTDR register value.
+  * @param  None
+  * @retval : The value of the current Tx desc start address.
+  */
+uint32_t ETH_GetCurrentTxDescStartAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHTDR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHRDR register value.
+  * @param  None
+  * @retval : The value of the current Rx desc start address.
+  */
+uint32_t ETH_GetCurrentRxDescStartAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHRDR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHTBAR register value.
+  * @param  None
+  * @retval : The value of the current Tx desc buffer address.
+  */
+uint32_t ETH_GetCurrentTxBufferAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHTBAR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHRBAR register value.
+  * @param  None
+  * @retval : The value of the current Rx desc buffer address.
+  */
+uint32_t ETH_GetCurrentRxBufferAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHRBAR));
+}
+
+/**
+  * @brief  Resumes the DMA Transmission by writing to the DmaTxPollDemand
+  *   register: (the data written could be anything). This forces
+  *   the DMA to resume transmission.
+  * @param  None
+  * @retval : None.
+  */
+void ETH_ResumeDMATransmission(void)
+{
+  ETH->DMATPDR = 0;
+}
+
+/**
+  * @brief  Resumes the DMA Transmission by writing to the DmaRxPollDemand
+  *   register: (the data written could be anything). This forces
+  *   the DMA to resume reception.
+  * @param  None
+  * @retval : None.
+  */
+void ETH_ResumeDMAReception(void)
+{
+  ETH->DMARPDR = 0;
+}
+
+/*---------------------------------  PMT  ------------------------------------*/
+/**
+  * @brief  Reset Wakeup frame filter register pointer.
+  * @param  None
+  * @retval : None
+  */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
+  ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+/**
+  * @brief  Populates the remote wakeup frame registers.
+  * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer
+  *   data (8 words).
+  * @retval : None
+  */
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
+{
+  uint32_t i = 0;
+
+  /* Fill Remote Wake-up Frame Filter register with Buffer data */
+  for(i =0; i<ETH_WakeupRegisterLength; i++)
+  {
+    /* Write each time to the same register */
+    ETH->MACRWUFFR = Buffer[i];
+  }
+}
+
+/**
+  * @brief  Enables or disables any unicast packet filtered by the MAC
+  *   (DAF) address recognition to be a wake-up frame.
+  * @param NewState: new state of the MAC Global Unicast Wake-Up.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Global Unicast Wake-Up */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;
+  }
+  else
+  {
+    /* Disable the MAC Global Unicast Wake-Up */
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
+  * @param ETH_PMT_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
+  * @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
+  * @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
+  * @retval : The new state of ETHERNET PMT Flag (SET or RESET).
+  */
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
+
+  if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the MAC Wake-Up Frame Detection.
+  * @param NewState: new state of the MAC Wake-Up Frame Detection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Wake-Up Frame Detection */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;
+  }
+  else
+  {
+    /* Disable the MAC Wake-Up Frame Detection */
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC Magic Packet Detection.
+  * @param NewState: new state of the MAC Magic Packet Detection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Magic Packet Detection */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;
+  }
+  else
+  {
+    /* Disable the MAC Magic Packet Detection */
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC Power Down.
+  * @param NewState: new state of the MAC Power Down.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_PowerDownCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Power Down */
+    /* This puts the MAC in power down mode */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;
+  }
+  else
+  {
+    /* Disable the MAC Power Down */
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
+  }
+}
+
+/*---------------------------------  MMC  ------------------------------------*/
+/**
+  * @brief  Enables or disables the MMC Counter Freeze.
+  * @param NewState: new state of the MMC Counter Freeze.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter Freeze */
+    ETH->MMCCR |= ETH_MMCCR_MCF;
+  }
+  else
+  {
+    /* Disable the MMC Counter Freeze */
+    ETH->MMCCR &= ~ETH_MMCCR_MCF;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MMC Reset On Read.
+  * @param NewState: new state of the MMC Reset On Read.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter reset on read */
+    ETH->MMCCR |= ETH_MMCCR_ROR;
+  }
+  else
+  {
+    /* Disable the MMC Counter reset on read */
+    ETH->MMCCR &= ~ETH_MMCCR_ROR;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MMC Counter Stop Rollover.
+  * @param NewState: new state of the MMC Counter Stop Rollover.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Disable the MMC Counter Stop Rollover  */
+    ETH->MMCCR &= ~ETH_MMCCR_CSR;
+  }
+  else
+  {
+    /* Enable the MMC Counter Stop Rollover */
+    ETH->MMCCR |= ETH_MMCCR_CSR;
+  }
+}
+
+/**
+  * @brief  Resets the MMC Counters.
+  * @param  None
+  * @retval : None
+  */
+void ETH_MMCCountersReset(void)
+{
+  /* Resets the MMC Counters */
+  ETH->MMCCR |= ETH_MMCCR_CR;
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET MMC interrupts.
+  * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt
+  *   sources to be enabled or disabled.
+  *   This parameter can be any combination of Tx interrupt or
+  *   any combination of Rx interrupt (but not both)of the following values:
+  * @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
+  * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+  * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+  * @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
+  * @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
+  * @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
+  * @param NewState: new state of the specified ETHERNET MMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+  {
+    /* Remove egister mak from IT */
+    ETH_MMC_IT &= 0xEFFFFFFF;
+
+    /* ETHERNET MMC Rx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH->MMCRIMR |= ETH_MMC_IT;
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH->MMCTIMR |= ETH_MMC_IT;
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MMC IT is set or not.
+  * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
+  * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
+  * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
+  * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
+  * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
+  * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
+  * @retval : The value of ETHERNET MMC IT (SET or RESET).
+  */
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
+
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+  {
+    /* ETHERNET MMC Rx interrupts selected */
+    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
+    if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
+    if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Get the specified ETHERNET MMC register value.
+  * @param ETH_MMCReg: specifies the ETHERNET MMC register.
+  *   This parameter can be one of the following values:
+  * @arg ETH_MMCCR      : MMC CR register
+  * @arg ETH_MMCRIR     : MMC RIR register
+  * @arg ETH_MMCTIR     : MMC TIR register
+  * @arg ETH_MMCRIMR    : MMC RIMR register
+  * @arg ETH_MMCTIMR    : MMC TIMR register
+  * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register
+  * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register
+  * @arg ETH_MMCTGFCR   : MMC TGFCR register
+  * @arg ETH_MMCRFCECR  : MMC RFCECR register
+  * @arg ETH_MMCRFAECR  : MMC RFAECR register
+  * @arg ETH_MMCRGUFCR  : MMC RGUFCRregister
+  * @retval : The value of ETHERNET MMC Register value.
+  */
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
+
+  /* Return the selected register value */
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
+}
+/*---------------------------------  PTP  ------------------------------------*/
+
+/**
+  * @brief  Updated the PTP block for fine correction with the Time Stamp
+  *   Addend register value.
+  * @param  None
+  * @retval : None
+  */
+void ETH_EnablePTPTimeStampAddend(void)
+{
+  /* Enable the PTP block update with the Time Stamp Addend register value */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;
+}
+
+/**
+  * @brief  Enable the PTP Time Stamp interrupt trigger
+  * @param  None
+  * @retval : None
+  */
+void ETH_EnablePTPTimeStampInterruptTrigger(void)
+{
+  /* Enable the PTP target time interrupt */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;
+}
+
+/**
+  * @brief  Updated the PTP system time with the Time Stamp Update register
+  *   value.
+  * @param  None
+  * @retval : None
+  */
+void ETH_EnablePTPTimeStampUpdate(void)
+{
+  /* Enable the PTP system time update with the Time Stamp Update register value */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;
+}
+
+/**
+  * @brief  Initialize the PTP Time Stamp
+  * @param  None
+  * @retval : None
+  */
+void ETH_InitializePTPTimeStamp(void)
+{
+  /* Initialize the PTP Time Stamp */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;
+}
+
+/**
+  * @brief  Selects the PTP Update method
+  * @param UpdateMethod: the PTP Update method
+  *   This parameter can be one of the following values:
+  * @arg ETH_PTP_FineUpdate   : Fine Update method
+  * @arg ETH_PTP_CoarseUpdate : Coarse Update method
+  * @retval : None
+  */
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
+
+  if (UpdateMethod != ETH_PTP_CoarseUpdate)
+  {
+    /* Enable the PTP Fine Update method */
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
+  }
+  else
+  {
+    /* Disable the PTP Coarse Update method */
+    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
+  }
+}
+
+/**
+  * @brief  Enables or disables the PTP time stamp for transmit and receive frames.
+  * @param NewState: new state of the PTP time stamp for transmit and receive frames
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval : None
+  */
+void ETH_PTPTimeStampCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the PTP time stamp for transmit and receive frames */
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
+  }
+  else
+  {
+    /* Disable the PTP time stamp for transmit and receive frames */
+    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET PTP flag is set or not.
+  * @param ETH_PTP_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  * @arg ETH_PTP_FLAG_TSARU : Addend Register Update
+  * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
+  * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update
+  * @arg ETH_PTP_FLAG_TSSTI  : Time Stamp Initialize
+  * @retval : The new state of ETHERNET PTP Flag (SET or RESET).
+  */
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
+
+  if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets the system time Sub-Second Increment value.
+  * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.
+  * @retval : None
+  */
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
+  /* Set the PTP Sub-Second Increment Register */
+  ETH->PTPSSIR = SubSecondValue;
+}
+
+/**
+  * @brief  Sets the Time Stamp update sign and values.
+  * @param Sign: specifies the PTP Time update value sign.
+  *   This parameter can be one of the following values:
+  * @arg ETH_PTP_PositiveTime : positive time value.
+  * @arg ETH_PTP_NegativeTime : negative time value.
+  * @param SecondValue: specifies the PTP Time update second value.
+  * @param SubSecondValue: specifies the PTP Time update sub-second value.
+  *   this is a 31 bit value. bit32 correspond to the sign.
+  * @retval : None
+  */
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
+  assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
+  /* Set the PTP Time Update High Register */
+  ETH->PTPTSHUR = SecondValue;
+
+  /* Set the PTP Time Update Low Register with sign */
+  ETH->PTPTSLUR = Sign | SubSecondValue;
+}
+
+/**
+  * @brief  Sets the Time Stamp Addend value.
+  * @param Value: specifies the PTP Time Stamp Addend Register value.
+  * @retval : None
+  */
+void ETH_SetPTPTimeStampAddend(uint32_t Value)
+{
+  /* Set the PTP Time Stamp Addend Register */
+  ETH->PTPTSAR = Value;
+}
+
+/**
+  * @brief  Sets the Target Time registers values.
+  * @param HighValue: specifies the PTP Target Time High Register value.
+  * @param LowValue: specifies the PTP Target Time Low Register value.
+  * @retval : None
+  */
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
+{
+  /* Set the PTP Target Time High Register */
+  ETH->PTPTTHR = HighValue;
+  /* Set the PTP Target Time Low Register */
+  ETH->PTPTTLR = LowValue;
+}
+
+/**
+  * @brief  Get the specified ETHERNET PTP register value.
+  * @param ETH_PTPReg: specifies the ETHERNET PTP register.
+  *   This parameter can be one of the following values:
+  * @arg ETH_PTPTSCR  : Sub-Second Increment Register
+  * @arg ETH_PTPSSIR  : Sub-Second Increment Register
+  * @arg ETH_PTPTSHR  : Time Stamp High Register
+  * @arg ETH_PTPTSLR  : Time Stamp Low Register
+  * @arg ETH_PTPTSHUR : Time Stamp High Update Register
+  * @arg ETH_PTPTSLUR : Time Stamp Low Update Register
+  * @arg ETH_PTPTSAR  : Time Stamp Addend Register
+  * @arg ETH_PTPTTHR  : Target Time High Register
+  * @arg ETH_PTPTTLR  : Target Time Low Register
+  * @retval : The value of ETHERNET PTP Register value.
+  */
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
+
+  /* Return the selected register value */
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode with PTP.
+  * @param DMATxDescTab: Pointer on the first Tx desc list
+  * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
+  * @param TxBuff: Pointer on the first TxBuffer list
+  * @param TxBuffCount: Number of the used Tx desc in the list
+  * @retval : None
+  */
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  DMAPTPTxDescToSet = DMAPTPTxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab+i;
+    /* Set Second Address Chained bit and enable PTP */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
+
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+    }
+    /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
+    (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
+    (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
+  }
+  /* Store on the last DMAPTPTxDescTab desc status record the first list address */
+  (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;
+
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLAR = (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param DMARxDescTab: Pointer on the first Rx desc list
+  * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
+  * @param RxBuff: Pointer on the first RxBuffer list
+  * @param RxBuffCount: Number of the used Rx desc in the list
+  * @retval : None
+  */
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab;
+  DMAPTPRxDescToGet = DMAPTPRxDescTab;
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+    }
+    /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
+    (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
+    (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
+  }
+  /* Store on the last DMAPTPRxDescTab desc status record the first list address */
+  (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;
+
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLAR = (uint32_t) DMARxDescTab;
+}
+
+/**
+  * @brief  Transmits a packet, from application buffer, pointed by ppkt with
+  *   Time Stamp values.
+  * @param ppkt: pointer to application packet buffer to transmit.
+  * @param FrameLength: Tx Packet size.
+  * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
+  * @retval : ETH_ERROR: in case of Tx desc owned by DMA
+  *   ETH_SUCCESS: for correct transmission
+  */
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
+{
+  uint32_t offset = 0, timeout = 0;
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+  for(offset=0; offset<FrameLength; offset++)
+  {
+    (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+  /* Setting the Frame Length: bits[12:0] */
+  DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_TBUS;
+    /* Resume DMA transmission*/
+    ETH->DMATPDR = 0;
+  }
+  /* Wait for ETH_DMATxDesc_TTSS flag to be set */
+  do
+  {
+    timeout++;
+  } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return ETH_ERROR;
+  }
+  /* Clear the DMATxDescToSet status register TTSS flag */
+  DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
+  *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
+  *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
+  /* Update the ENET DMA current descriptor */
+  /* Chained Mode */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Tx descriptor list for next buffer read */
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
+    if(DMAPTPTxDescToSet->Status != 0)
+    {
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
+    }
+    else
+    {
+      DMAPTPTxDescToSet++;
+    }
+  }
+  else /* Ring Mode */
+  {
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer read: this will
+         be the first Tx descriptor in this case */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Tx descriptor list for next buffer read */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+  /* Return SUCCESS */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Receives a packet and copies it to memory pointed by ppkt with
+  *   Time Stamp values.
+  * @param  ppkt: pointer to application packet receive buffer.
+  * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
+  * @retval : ETH_ERROR: if there is error in reception
+  *   framelength: received packet size if packet reception is correct
+  */
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
+{
+  uint32_t offset = 0, framelength = 0;
+  /* Check if the descriptor is owned by the ENET or CPU */
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR;
+  }
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+  {
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+    for(offset=0; offset<framelength; offset++)
+    {
+      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
+    }
+  }
+  else
+  {
+    /* Return ERROR */
+    framelength = ETH_ERROR;
+  }
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_RBUS;
+    /* Resume DMA reception */
+    ETH->DMARPDR = 0;
+  }
+  *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
+  *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
+    if(DMAPTPRxDescToGet->Status != 0)
+    {
+      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
+    }
+    else
+    {
+      DMAPTPRxDescToGet++;
+    }
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+  /* Return Frame Length/ERROR */
+  return (framelength);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
+/*
+ * STM32 Eth Driver for RT-Thread
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-10-05     Bernard      eth interface driver for STM32F107 CL
+ */
+#include <rtthread.h>
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+
+#define STM32_ETH_DEBUG		0
+
+#define MII_MODE          /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */
+
+#define DP83848_PHY        	/* Ethernet pins mapped on STM3210C-EVAL Board */
+#define PHY_ADDRESS       	0x01 /* Relative to STM3210C-EVAL Board */
+
+#define ETH_RXBUFNB        	4
+#define ETH_TXBUFNB        	2
+static ETH_InitTypeDef ETH_InitStructure;
+static ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
+static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
+
+#define MAX_ADDR_LEN 6
+struct rt_stm32_eth
+{
+	/* inherit from ethernet device */
+	struct eth_device parent;
+
+	/* interface address info. */
+	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+};
+static struct rt_stm32_eth stm32_eth_device;
+static struct rt_semaphore tx_wait;
+static rt_bool_t tx_is_waiting = RT_FALSE;
+
+/* interrupt service routine */
+void rt_hw_stm32_eth_isr(int irqno)
+{
+	rt_uint32_t status;
+
+	status = ETH->DMASR;
+
+#if STM32_ETH_DEBUG
+	rt_kprintf("eth dma status: 0x%08x\n", ETH->DMASR);
+#endif
+	
+	//Clear received IT
+	if ((status & ETH_DMA_IT_NIS) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_NIS;
+	if ((status & ETH_DMA_IT_AIS) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_AIS;
+	if ((status & ETH_DMA_IT_RO) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_RO;
+	if ((status & ETH_DMA_IT_RBU) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_RBU;
+
+	if (ETH_GetDMAITStatus(ETH_DMA_IT_R) == SET) /* packet receiption */
+	{
+		rt_err_t result;
+
+		/* a frame has been received */
+		result = eth_device_ready(&(stm32_eth_device.parent));
+		RT_ASSERT(result == RT_EOK);
+
+		ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
+	}
+
+	if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
+	{
+		if (tx_is_waiting == RT_TRUE)
+		{
+			tx_is_waiting = RT_FALSE;
+			rt_sem_release(&tx_wait);
+		}
+
+		ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
+	}
+}
+
+/* RT-Thread Device Interface */
+/* initialize the interface */
+static rt_err_t rt_stm32_eth_init(rt_device_t dev)
+{
+	vu32 Value = 0;
+
+	/* Reset ETHERNET on AHB Bus */
+	ETH_DeInit();
+
+	/* Software reset */
+	ETH_SoftwareReset();
+
+	/* Wait for software reset */
+	while(ETH_GetSoftwareResetStatus()==SET);
+
+	/* ETHERNET Configuration ------------------------------------------------------*/
+	/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
+	ETH_StructInit(&ETH_InitStructure);
+
+	/* Fill ETH_InitStructure parametrs */
+	/*------------------------   MAC   -----------------------------------*/
+	ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable  ;
+	ETH_InitStructure.ETH_Speed = ETH_Speed_100M;
+	ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+	ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;
+	ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
+	ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+	ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;
+	ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+	ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+	ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+	ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+
+	/* Configure ETHERNET */
+	Value = ETH_Init(&ETH_InitStructure, PHY_ADDRESS);
+
+	/* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
+	ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
+	
+	/* Initialize Tx Descriptors list: Chain Mode */
+	ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
+	/* Initialize Rx Descriptors list: Chain Mode  */
+	ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
+
+	/* MAC address configuration */
+	ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
+
+	/* Enable MAC and DMA transmission and reception */
+	ETH_Start();
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	switch(cmd)
+	{
+	case NIOCTL_GADDR:
+		/* get mac address */
+		if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+		else return -RT_ERROR;
+		break;
+
+	default :
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit packet. */
+rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
+{
+#if STM32_ETH_DEBUG	
+	int cnt = 0;
+#endif
+	struct pbuf* q;
+	rt_uint32_t offset;
+
+	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+	while ((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+	{
+		rt_err_t result;
+		rt_uint32_t level;
+
+#if STM32_ETH_DEBUG	
+		rt_kprintf("error: own bit set\n");
+#endif
+		level = rt_hw_interrupt_disable();
+		tx_is_waiting = RT_TRUE;
+		rt_hw_interrupt_enable(level);
+
+		/* it's own bit set, wait it */
+		result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER);
+		if (result == RT_EOK) break;
+		if (result == -RT_ERROR) return -RT_ERROR;
+	}
+
+#if STM32_ETH_DEBUG
+	rt_kprintf("tx dump:\n");
+#endif
+	offset = 0;
+	for (q = p; q != NULL; q = q->next)
+	{
+		rt_uint8_t* ptr;
+		rt_uint32_t len;
+
+		len = q->len;
+		ptr = q->payload;
+
+		/* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+		while (len)
+		{
+			(*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = *ptr;
+
+#if STM32_ETH_DEBUG
+			rt_kprintf("%02x ", *ptr);
+			if (++cnt % 16 == 0) rt_kprintf("\n");
+#endif
+			offset ++; ptr ++; len --;
+		}
+	}
+
+#if STM32_ETH_DEBUG
+	rt_kprintf("\n");
+#endif
+
+	/* Setting the Frame Length: bits[12:0] */
+	DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1);
+	/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+	DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+	DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+	if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+	{
+		/* Clear TBUS ETHERNET DMA flag */
+		ETH->DMASR = ETH_DMASR_TBUS;
+		/* Transmit Poll Demand to resume DMA transmission*/
+		ETH->DMATPDR = 0;
+#if STM32_ETH_DEBUG
+		rt_kprintf("transmit poll demand\n");
+#endif
+	}
+
+	/* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
+	/* Chained Mode */
+	if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+	{
+		/* Selects the next DMA Tx descriptor list for next buffer to send */
+		DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
+	}
+	else /* Ring Mode */
+	{
+		if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+		{
+			/* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+			DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+		}
+		else
+		{
+			/* Selects the next DMA Tx descriptor list for next buffer to send */
+			DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+		}
+	}
+
+	/* Return SUCCESS */
+	return RT_EOK;
+}
+
+/* reception packet. */
+struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
+{
+	struct pbuf* p;
+	rt_uint32_t offset = 0, framelength = 0;
+
+	/* init p pointer */
+	p = RT_NULL;
+
+	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+	if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET))
+		return p;
+
+	if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+		((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+		((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+	{
+#if STM32_ETH_DEBUG
+		int cnt = 0;
+		
+		rt_kprintf("rx dump:\n");
+#endif
+		
+		/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+		framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
+
+		/* allocate buffer */
+		p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM);
+		if (p != RT_NULL)
+		{
+			rt_uint8_t* ptr;
+			struct pbuf* q;
+			rt_size_t len;
+
+			for (q = p; q != RT_NULL; q= q->next)
+			{
+				ptr = q->payload;
+				len = q->len;
+
+				/* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+				while (len)
+				{
+					*ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+#if STM32_ETH_DEBUG
+					rt_kprintf("%02x ", *ptr);
+					if (++cnt % 16 == 0) rt_kprintf("\n");
+#endif
+
+					offset ++; ptr ++; len --;
+				}
+			}
+			
+#if STM32_ETH_DEBUG
+			rt_kprintf("\n");
+#endif
+		}
+	}
+
+	/* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+	DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+	/* When Rx Buffer unavailable flag is set: clear it and resume reception */
+	if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+	{
+		/* Clear RBUS ETHERNET DMA flag */
+		ETH->DMASR = ETH_DMASR_RBUS;
+		/* Resume DMA reception */
+		ETH->DMARPDR = 0;
+	}
+
+	/* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+	/* Chained Mode */
+	if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+	{
+		/* Selects the next DMA Rx descriptor list for next buffer to read */
+		DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+	}
+	else /* Ring Mode */
+	{
+		if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+		{
+			/* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+			DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+		}
+		else
+		{
+			/* Selects the next DMA Rx descriptor list for next buffer to read */
+			DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+		}
+	}
+
+	return p;
+}
+
+static void RCC_Configuration(void)
+{
+	/* Enable ETHERNET clock  */
+	RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx |
+		RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
+
+	/* Enable GPIOs clocks */
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |	RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC |
+		RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE| RCC_APB2Periph_AFIO, ENABLE);
+}
+
+static void NVIC_Configuration(void)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    /* Configure one bit for preemption priority */
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
+
+    /* Enable the EXTI0 Interrupt */
+    NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+/*
+ * GPIO Configuration for ETH
+ */
+static void GPIO_Configuration(void)
+{
+	GPIO_InitTypeDef GPIO_InitStructure;
+
+	/* ETHERNET pins remapp in STM3210C-EVAL board: RX_DV and RxD[3:0] */
+	GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE);
+
+	/* MII/RMII Media interface selection */
+#ifdef MII_MODE /* Mode MII with STM3210C-EVAL  */
+	GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
+
+	/* Get HSE clock = 25MHz on PA8 pin(MCO) */
+	RCC_MCOConfig(RCC_MCO_HSE);
+
+#elif defined RMII_MODE  /* Mode RMII with STM3210C-EVAL */
+	GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
+
+	/* Get HSE clock = 25MHz on PA8 pin(MCO) */
+	/* set PLL3 clock output to 50MHz (25MHz /5 *10 =50MHz) */
+	RCC_PLL3Config(RCC_PLL3Mul_10);
+	/* Enable PLL3 */
+	RCC_PLL3Cmd(ENABLE);
+	/* Wait till PLL3 is ready */
+	while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
+	{}
+
+	/* Get clock PLL3 clock on PA8 pin */
+	RCC_MCOConfig(RCC_MCO_PLL3CLK);
+#endif
+
+	/* ETHERNET pins configuration */
+	/* AF Output Push Pull:
+	- ETH_MII_MDIO / ETH_RMII_MDIO: PA2
+	- ETH_MII_MDC / ETH_RMII_MDC: PC1
+	- ETH_MII_TXD2: PC2
+	- ETH_MII_TX_EN / ETH_RMII_TX_EN: PB11
+	- ETH_MII_TXD0 / ETH_RMII_TXD0: PB12
+	- ETH_MII_TXD1 / ETH_RMII_TXD1: PB13
+	- ETH_MII_PPS_OUT / ETH_RMII_PPS_OUT: PB5
+	- ETH_MII_TXD3: PB8 */
+
+	/* Configure PA2 as alternate function push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	/* Configure PC1, PC2 and PC3 as alternate function push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	/* Configure PB5, PB8, PB11, PB12 and PB13 as alternate function push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 |
+								  GPIO_Pin_12 | GPIO_Pin_13;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+	/**************************************************************/
+	/*               For Remapped Ethernet pins                   */
+	/*************************************************************/
+	/* Input (Reset Value):
+	- ETH_MII_CRS CRS: PA0
+	- ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1
+	- ETH_MII_COL: PA3
+	- ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8
+	- ETH_MII_TX_CLK: PC3
+	- ETH_MII_RXD0 / ETH_RMII_RXD0: PD9
+	- ETH_MII_RXD1 / ETH_RMII_RXD1: PD10
+	- ETH_MII_RXD2: PD11
+	- ETH_MII_RXD3: PD12
+	- ETH_MII_RX_ER: PB10 */
+
+	/* Configure PA0, PA1 and PA3 as input */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	/* Configure PB10 as input */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+	/* Configure PC3 as input */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+	/* Configure PD8, PD9, PD10, PD11 and PD12 as input */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOD, &GPIO_InitStructure); /**/
+
+	/* MCO pin configuration------------------------------------------------- */
+	/* Configure MCO (PA8) as alternate function push-pull */
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+}
+
+void rt_hw_stm32_eth_init()
+{
+	RCC_Configuration();
+	GPIO_Configuration();
+	NVIC_Configuration();
+
+    stm32_eth_device.dev_addr[0] = 0x00;
+    stm32_eth_device.dev_addr[1] = 0x60;
+    stm32_eth_device.dev_addr[2] = 0x6E;
+    stm32_eth_device.dev_addr[3] = 0x11;
+    stm32_eth_device.dev_addr[4] = 0x22;
+    stm32_eth_device.dev_addr[5] = 0x33;
+
+	stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
+	stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
+	stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
+	stm32_eth_device.parent.parent.read       = rt_stm32_eth_read;
+	stm32_eth_device.parent.parent.write      = rt_stm32_eth_write;
+	stm32_eth_device.parent.parent.control    = rt_stm32_eth_control;
+	stm32_eth_device.parent.parent.user_data  = RT_NULL;
+
+	stm32_eth_device.parent.eth_rx     = rt_stm32_eth_rx;
+	stm32_eth_device.parent.eth_tx     = rt_stm32_eth_tx;
+
+	/* init tx semaphore */
+	rt_sem_init(&tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
+
+	/* register eth device */
+	eth_device_init(&(stm32_eth_device.parent), "e0");
+}

bsp/stm32f20x/stm32_eth.h

@@ -0,0 +1,1610 @@
+/**
+  ******************************************************************************
+  * @file    stm32_eth.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    06/19/2009
+  * @brief   This file contains all the functions prototypes for the Ethernet
+  *          firmware library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ETH_H
+#define __STM32_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32_ETH_Driver
+  * @{
+  */
+
+/** @defgroup ETH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ETH MAC Init structure definition
+  */ 
+typedef struct {
+/** 
+  * @brief / * MAC  
+  */ 
+  uint32_t             ETH_AutoNegotiation;           /*!< Selects or not the AutoNegotiation with the external PHY */  
+  uint32_t             ETH_Watchdog;                  /*!< Enable/disable Watchdog timer */  
+  uint32_t             ETH_Jabber;                    /*!< Enable/disable Jabber timer */ 
+  uint32_t             ETH_InterFrameGap;             /*!< Selects minimum IFG between frames during transmission */   
+  uint32_t             ETH_CarrierSense;              /*!< Enable/disable Carrier Sense */ 
+  uint32_t             ETH_Speed;                     /*!< Indicates the Ethernet speed: 10/100 Mbps */  
+  uint32_t             ETH_ReceiveOwn;                /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */  
+  uint32_t             ETH_LoopbackMode;              /*!< Enable/disable internal MAC MII Loopback mode */ 
+  uint32_t             ETH_Mode;                      /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ 
+  uint32_t             ETH_ChecksumOffload;           /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */   
+  uint32_t             ETH_RetryTransmission;         /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */
+  uint32_t             ETH_AutomaticPadCRCStrip;      /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ 
+  uint32_t             ETH_BackOffLimit;              /*!< Selects the BackOff limit value */ 
+  uint32_t             ETH_DeferralCheck;             /*!< Enable/disable deferral check function (Half-Duplex mode) */                                                                                                       
+  uint32_t             ETH_ReceiveAll;                /*!< Enable/disable all frames reception by the MAC (No fitering)*/ 
+  uint32_t             ETH_SourceAddrFilter;          /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */                  
+  uint32_t             ETH_PassControlFrames;         /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ 
+  uint32_t             ETH_BroadcastFramesReception;  /*!< Enable/disable reception of Broadcast Frames */
+  uint32_t             ETH_DestinationAddrFilter;     /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ 
+  uint32_t             ETH_PromiscuousMode;           /*!< Enable/disable Promiscuous Mode */
+  uint32_t             ETH_MulticastFramesFilter;     /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ 
+  uint32_t             ETH_UnicastFramesFilter;       /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter  */
+  uint32_t             ETH_HashTableHigh;             /*!< This field contains the higher 32 bits of Hash table.  */    
+  uint32_t             ETH_HashTableLow;              /*!< This field contains the lower 32 bits of Hash table.  */    
+  uint32_t             ETH_PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */
+  uint32_t             ETH_ZeroQuantaPause;           /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ 
+  uint32_t             ETH_PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
+  uint32_t             ETH_UnicastPauseFrameDetect;   /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ 
+  uint32_t             ETH_ReceiveFlowControl;        /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */
+  uint32_t             ETH_TransmitFlowControl;       /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */     
+  uint32_t             ETH_VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ 
+  uint32_t             ETH_VLANTagIdentifier;         /*!< VLAN tag identifier for receive frames */
+
+/** 
+  * @brief / * DMA  
+  */ 
+  uint32_t             ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */
+  uint32_t             ETH_ReceiveStoreForward;         /*!< Enable/disable Receive store and forward */
+  uint32_t             ETH_FlushReceivedFrame;          /*!< Enable/disable flushing of received frames */
+  uint32_t             ETH_TransmitStoreForward;        /*!< Enable/disable Transmit store and forward */
+  uint32_t             ETH_TransmitThresholdControl;    /*!< Selects the Transmit Threshold Control */
+  uint32_t             ETH_ForwardErrorFrames;          /*!< Enable/disable forward to DMA of all frames except runt error frames */
+  uint32_t             ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */
+  uint32_t             ETH_ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO */
+  uint32_t             ETH_SecondFrameOperate;          /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */
+  uint32_t             ETH_AddressAlignedBeats;         /*!< Enable/disable Address Aligned Beats */
+  uint32_t             ETH_FixedBurst;                  /*!< Enable/disable the AHB Master interface fixed burst transfers */
+  uint32_t             ETH_RxDMABurstLength;            /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */
+  uint32_t             ETH_TxDMABurstLength;            /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */                                                 
+  uint32_t             ETH_DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */
+  uint32_t             ETH_DMAArbitration;              /*!< Selects DMA Tx/Rx arbitration */  
+}ETH_InitTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           DMA descriptors types
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/** 
+  * @brief  ETH DMA Desciptors data structure definition
+  */ 
+typedef struct  {
+  uint32_t   Status;                /*!< Status */
+  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
+  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
+  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
+} ETH_DMADESCTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Constants
+  * @{
+  */ 
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                          ETH Frames defines
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/** @defgroup ENET_Buffers_setting 
+  * @{
+  */ 
+#define ETH_MAX_PACKET_SIZE    1520    /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               14    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   4    /*!< Ethernet CRC */
+#define ETH_EXTRA                 2    /*!< Extra bytes in some cases */   
+#define VLAN_TAG                  4    /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD          46    /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD        1500    /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    9000    /*!< Jumbo frame payload size */      
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                 Ethernet DMA descriptors registers bits definition
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/* DMA Tx Desciptor -----------------------------------------------------------*/
+/**----------------------------------------------------------------------------------------------
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Buffer1 Address [31:0]                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 |                   Buffer2 Address [31:0] / Next Desciptor Address [31:0]               |
+  ---------------------------------------------------------------------------------------------**/
+
+/** 
+  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
+  */ 
+#define ETH_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATxDesc_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
+#define ETH_DMATxDesc_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
+#define ETH_DMATxDesc_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
+#define ETH_DMATxDesc_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
+#define ETH_DMATxDesc_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
+#define ETH_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
+#define ETH_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
+#define ETH_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
+#define ETH_DMATxDesc_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
+#define ETH_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
+#define ETH_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
+#define ETH_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
+#define ETH_DMATxDesc_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATxDesc_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
+#define ETH_DMATxDesc_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
+#define ETH_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during tramsmission */
+#define ETH_DMATxDesc_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the tranceiver */
+#define ETH_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATxDesc_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATxDesc_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
+#define ETH_DMATxDesc_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
+#define ETH_DMATxDesc_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
+#define ETH_DMATxDesc_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATxDesc_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
+
+/** 
+  * @brief  Bit definition of TDES1 register
+  */ 
+#define ETH_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
+#define ETH_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of TDES2 register
+  */ 
+#define ETH_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of TDES3 register
+  */ 
+#define ETH_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_Rx_descriptor 
+  * @{
+  */
+
+/**--------------------------------------------------------------------------------------------------------------------
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 |                          Buffer2 Address [31:0] / Next Desciptor Address [31:0]                              |
+  -------------------------------------------------------------------------------------------------------------------**/
+
+/** 
+  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
+  */ 
+#define ETH_DMARxDesc_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARxDesc_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
+#define ETH_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
+#define ETH_DMARxDesc_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARxDesc_DE          ((uint32_t)0x00004000)  /*!< Desciptor error: no more descriptors for receive frame  */
+#define ETH_DMARxDesc_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
+#define ETH_DMARxDesc_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
+#define ETH_DMARxDesc_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARxDesc_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
+#define ETH_DMARxDesc_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
+#define ETH_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
+#define ETH_DMARxDesc_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
+#define ETH_DMARxDesc_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
+#define ETH_DMARxDesc_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARxDesc_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
+#define ETH_DMARxDesc_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARxDesc_CE          ((uint32_t)0x00000002)  /*!< CRC error */
+#define ETH_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/** 
+  * @brief  Bit definition of RDES1 register
+  */ 
+#define ETH_DMARxDesc_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
+#define ETH_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
+#define ETH_DMARxDesc_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
+#define ETH_DMARxDesc_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
+#define ETH_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of RDES2 register  
+  */ 
+#define ETH_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of RDES3 register  
+  */ 
+#define ETH_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                     Desciption of common PHY registers
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Read_write_Timeouts 
+  * @{
+  */ 
+#define PHY_READ_TO                     ((uint32_t)0x0004FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0004FFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Reset_Delay 
+  * @{
+  */ 
+#define PHY_ResetDelay                  ((uint32_t)0x000FFFFF) 
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Config_Delay 
+  * @{
+  */ 
+#define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Register_address 
+  * @{
+  */ 
+#define PHY_BCR                          0          /*!< Tranceiver Basic Control Register */
+#define PHY_BSR                          1          /*!< Tranceiver Basic Status Register */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_basic_Control_register 
+  * @{
+  */ 
+#define PHY_Reset                       ((u16)0x8000)      /*!< PHY Reset */
+#define PHY_Loopback                    ((u16)0x4000)      /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((u16)0x2100)      /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((u16)0x2000)      /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((u16)0x0100)      /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M              ((u16)0x0000)      /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AutoNegotiation             ((u16)0x1000)      /*!< Enable auto-negotiation function */
+#define PHY_Restart_AutoNegotiation     ((u16)0x0200)      /*!< Restart auto-negotiation function */
+#define PHY_Powerdown                   ((u16)0x0800)      /*!< Select the power down mode */
+#define PHY_Isolate                     ((u16)0x0400)      /*!< Isolate PHY from MII */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_basic_status_register 
+  * @{
+  */ 
+#define PHY_AutoNego_Complete           ((u16)0x0020)      /*!< Auto-Negotioation process completed */
+#define PHY_Linked_Status               ((u16)0x0004)      /*!< Valid link established */
+#define PHY_Jabber_detection            ((u16)0x0002)      /*!< Jabber condition detected */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_status_register 
+  * @{
+  */ 
+/* The PHY status register value change from a PHY to another so the user have 
+   to update this value depending on the used external PHY */
+/** 
+  * @brief  For LAN8700  
+  */ 
+//#define PHY_SR                           31         /*!< Tranceiver Status Register */
+/** 
+  * @brief  For DP83848  
+  */ 
+#define PHY_SR                           16     /*!< Tranceiver Status Register */
+
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update
+   this value depending on the used external PHY */
+/** 
+  * @brief  For LAN8700  
+  */ 
+//#define PHY_Speed_Status            ((u16)0x0004)       /*!< Configured information of Speed: 10Mbps */
+//#define PHY_Duplex_Status           ((u16)0x0010)       /*!< Configured information of Duplex: Full-duplex */
+
+/** 
+  * @brief  For DP83848  
+  */ 
+#define PHY_Speed_Status            ((u16)0x0002)    /*!< Configured information of Speed: 10Mbps */
+#define PHY_Duplex_Status           ((u16)0x0004)    /*!< Configured information of Duplex: Full-duplex */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
+                             ((REG) == PHY_BSR) || \
+                             ((REG) == PHY_SR))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                                  MAC defines
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ETH_AutoNegotiation 
+  * @{
+  */ 
+#define ETH_AutoNegotiation_Enable     ((uint32_t)0x00000001)
+#define ETH_AutoNegotiation_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
+                                     ((CMD) == ETH_AutoNegotiation_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_watchdog 
+  * @{
+  */ 
+#define ETH_Watchdog_Enable       ((uint32_t)0x00000000)
+#define ETH_Watchdog_Disable      ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
+                              ((CMD) == ETH_Watchdog_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Jabber 
+  * @{
+  */ 
+#define ETH_Jabber_Enable    ((uint32_t)0x00000000)
+#define ETH_Jabber_Disable   ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
+                            ((CMD) == ETH_Jabber_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Inter_Frame_Gap 
+  * @{
+  */ 
+#define ETH_InterFrameGap_96Bit   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_InterFrameGap_88Bit   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_InterFrameGap_80Bit   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_InterFrameGap_72Bit   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_InterFrameGap_64Bit   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_InterFrameGap_56Bit   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_InterFrameGap_48Bit   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_InterFrameGap_40Bit   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_88Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_80Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_72Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_64Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_56Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_48Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_40Bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Carrier_Sense 
+  * @{
+  */ 
+#define ETH_CarrierSense_Enable   ((uint32_t)0x00000000)
+#define ETH_CarrierSense_Disable  ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
+                                   ((CMD) == ETH_CarrierSense_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Speed 
+  * @{
+  */ 
+#define ETH_Speed_10M        ((uint32_t)0x00000000)
+#define ETH_Speed_100M       ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
+                             ((SPEED) == ETH_Speed_100M))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Own 
+  * @{
+  */ 
+#define ETH_ReceiveOwn_Enable     ((uint32_t)0x00000000)
+#define ETH_ReceiveOwn_Disable    ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
+                                 ((CMD) == ETH_ReceiveOwn_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Loop_back_Mode 
+  * @{
+  */ 
+#define ETH_LoopbackMode_Enable        ((uint32_t)0x00001000)
+#define ETH_LoopbackMode_Disable       ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
+                                   ((CMD) == ETH_LoopbackMode_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Duplex_mode 
+  * @{
+  */ 
+#define ETH_Mode_FullDuplex       ((uint32_t)0x00000800)
+#define ETH_Mode_HalfDuplex       ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
+                                  ((MODE) == ETH_Mode_HalfDuplex))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Checksum_Offload 
+  * @{
+  */ 
+#define ETH_ChecksumOffload_Enable     ((uint32_t)0x00000400)
+#define ETH_ChecksumOffload_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
+                                      ((CMD) == ETH_ChecksumOffload_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Retry_Transmission 
+  * @{
+  */ 
+#define ETH_RetryTransmission_Enable   ((uint32_t)0x00000000)
+#define ETH_RetryTransmission_Disable  ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
+                                        ((CMD) == ETH_RetryTransmission_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip 
+  * @{
+  */ 
+#define ETH_AutomaticPadCRCStrip_Enable     ((uint32_t)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
+                                            ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Back-Off_limit 
+  * @{
+  */ 
+#define ETH_BackOffLimit_10  ((uint32_t)0x00000000)
+#define ETH_BackOffLimit_8   ((uint32_t)0x00000020)
+#define ETH_BackOffLimit_4   ((uint32_t)0x00000040)
+#define ETH_BackOffLimit_1   ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
+                                     ((LIMIT) == ETH_BackOffLimit_8) || \
+                                     ((LIMIT) == ETH_BackOffLimit_4) || \
+                                     ((LIMIT) == ETH_BackOffLimit_1))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Deferral_Check 
+  * @{
+  */
+#define ETH_DeferralCheck_Enable       ((uint32_t)0x00000010)
+#define ETH_DeferralCheck_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
+                                    ((CMD) == ETH_DeferralCheck_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_All 
+  * @{
+  */ 
+#define ETH_ReceiveAll_Enable     ((uint32_t)0x80000000)
+#define ETH_ReceiveAll_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
+                                 ((CMD) == ETH_ReceiveAll_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Source_Addr_Filter 
+  * @{
+  */ 
+#define ETH_SourceAddrFilter_Normal_Enable       ((uint32_t)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable      ((uint32_t)0x00000300)
+#define ETH_SourceAddrFilter_Disable             ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pass_Control_Frames 
+  * @{
+  */ 
+#define ETH_PassControlFrames_BlockAll                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
+#define ETH_PassControlFrames_ForwardAll              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Broadcast_Frames_Reception 
+  * @{
+  */ 
+#define ETH_BroadcastFramesReception_Enable      ((uint32_t)0x00000000)
+#define ETH_BroadcastFramesReception_Disable     ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
+                                                ((CMD) == ETH_BroadcastFramesReception_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Destination_Addr_Filter 
+  * @{
+  */ 
+#define ETH_DestinationAddrFilter_Normal    ((uint32_t)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse   ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
+                                                ((FILTER) == ETH_DestinationAddrFilter_Inverse))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Promiscuous_Mode 
+  * @{
+  */ 
+#define ETH_PromiscuousMode_Enable     ((uint32_t)0x00000001)
+#define ETH_PromiscuousMode_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
+                                      ((CMD) == ETH_PromiscuousMode_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_multicast_frames_filter 
+  * @{
+  */ 
+#define ETH_MulticastFramesFilter_PerfectHashTable    ((uint32_t)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable           ((uint32_t)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect             ((uint32_t)0x00000000)
+#define ETH_MulticastFramesFilter_None                ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_None))
+                                                     
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_unicast_frames_filter 
+  * @{
+  */ 
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable        ((uint32_t)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect          ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_Perfect))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Time 
+  * @{
+  */ 
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Zero_Quanta_Pause 
+  * @{
+  */ 
+#define ETH_ZeroQuantaPause_Enable     ((uint32_t)0x00000000)
+#define ETH_ZeroQuantaPause_Disable    ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZeroQuantaPause_Enable) || \
+                                        ((CMD) == ETH_ZeroQuantaPause_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Low_Threshold 
+  * @{
+  */ 
+#define ETH_PauseLowThreshold_Minus4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
+#define ETH_PauseLowThreshold_Minus28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
+#define ETH_PauseLowThreshold_Minus144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
+#define ETH_PauseLowThreshold_Minus256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect 
+  * @{
+  */ 
+#define ETH_UnicastPauseFrameDetect_Enable  ((uint32_t)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
+                                                ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Flow_Control 
+  * @{
+  */ 
+#define ETH_ReceiveFlowControl_Enable       ((uint32_t)0x00000004)
+#define ETH_ReceiveFlowControl_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
+                                         ((CMD) == ETH_ReceiveFlowControl_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Flow_Control 
+  * @{
+  */ 
+#define ETH_TransmitFlowControl_Enable      ((uint32_t)0x00000002)
+#define ETH_TransmitFlowControl_Disable     ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
+                                          ((CMD) == ETH_TransmitFlowControl_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_VLAN_Tag_Comparison 
+  * @{
+  */ 
+#define ETH_VLANTagComparison_12Bit    ((uint32_t)0x00010000)
+#define ETH_VLANTagComparison_16Bit    ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
+                                                ((COMPARISON) == ETH_VLANTagComparison_16Bit))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Flags 
+  * @{
+  */ 
+#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+                                   ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Interrupts 
+  * @{
+  */ 
+#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+                               ((IT) == ETH_MAC_IT_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses 
+  * @{
+  */ 
+#define ETH_MAC_Address0     ((uint32_t)0x00000000)
+#define ETH_MAC_Address1     ((uint32_t)0x00000008)
+#define ETH_MAC_Address2     ((uint32_t)0x00000010)
+#define ETH_MAC_Address3     ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
+                                         ((ADDRESS) == ETH_MAC_Address1) || \
+                                         ((ADDRESS) == ETH_MAC_Address2) || \
+                                         ((ADDRESS) == ETH_MAC_Address3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
+                                        ((ADDRESS) == ETH_MAC_Address2) || \
+                                        ((ADDRESS) == ETH_MAC_Address3))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames 
+  * @{
+  */ 
+#define ETH_MAC_AddressFilter_SA       ((uint32_t)0x00000000)
+#define ETH_MAC_AddressFilter_DA       ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
+                                           ((FILTER) == ETH_MAC_AddressFilter_DA))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes 
+  * @{
+  */ 
+#define ETH_MAC_AddressMask_Byte6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_AddressMask_Byte4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_AddressMask_Byte3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_AddressMask_Byte2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte5) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte4) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte3) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte2) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte1))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                      Ethernet DMA Desciptors defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMATxDesc_IC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LS) || \
+                                         ((FLAG) == ETH_DMATxDesc_FS) || \
+                                         ((FLAG) == ETH_DMATxDesc_DC) || \
+                                         ((FLAG) == ETH_DMATxDesc_DP) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSE) || \
+                                         ((FLAG) == ETH_DMATxDesc_TER) || \
+                                         ((FLAG) == ETH_DMATxDesc_TCH) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSS) || \
+                                         ((FLAG) == ETH_DMATxDesc_IHE) || \
+                                         ((FLAG) == ETH_DMATxDesc_ES) || \
+                                         ((FLAG) == ETH_DMATxDesc_JT) || \
+                                         ((FLAG) == ETH_DMATxDesc_FF) || \
+                                         ((FLAG) == ETH_DMATxDesc_PCE) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCA) || \
+                                         ((FLAG) == ETH_DMATxDesc_NC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCO) || \
+                                         ((FLAG) == ETH_DMATxDesc_EC) || \
+                                         ((FLAG) == ETH_DMATxDesc_VF) || \
+                                         ((FLAG) == ETH_DMATxDesc_CC) || \
+                                         ((FLAG) == ETH_DMATxDesc_ED) || \
+                                         ((FLAG) == ETH_DMATxDesc_UF) || \
+                                         ((FLAG) == ETH_DMATxDesc_DB))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment 
+  * @{
+  */ 
+#define ETH_DMATxDesc_LastSegment      ((uint32_t)0x40000000)  /*!< Last Segment */
+#define ETH_DMATxDesc_FirstSegment     ((uint32_t)0x20000000)  /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
+                                            ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+  * @{
+  */ 
+#define ETH_DMATxDesc_ChecksumByPass             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
+#define ETH_DMATxDesc_ChecksumIPV4Header         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
+/** 
+  * @brief  ETH DMA Tx Desciptor buffer size
+  */ 
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMARxDesc_AFM) || \
+                                         ((FLAG) == ETH_DMARxDesc_ES) || \
+                                         ((FLAG) == ETH_DMARxDesc_DE) || \
+                                         ((FLAG) == ETH_DMARxDesc_SAF) || \
+                                         ((FLAG) == ETH_DMARxDesc_LE) || \
+                                         ((FLAG) == ETH_DMARxDesc_OE) || \
+                                         ((FLAG) == ETH_DMARxDesc_VLAN) || \
+                                         ((FLAG) == ETH_DMARxDesc_FS) || \
+                                         ((FLAG) == ETH_DMARxDesc_LS) || \
+                                         ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
+                                         ((FLAG) == ETH_DMARxDesc_LC) || \
+                                         ((FLAG) == ETH_DMARxDesc_FT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RWT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RE) || \
+                                         ((FLAG) == ETH_DMARxDesc_DBE) || \
+                                         ((FLAG) == ETH_DMARxDesc_CE) || \
+                                         ((FLAG) == ETH_DMARxDesc_MAMPCE))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ 
+  * @{
+  */ 
+#define ETH_DMARxDesc_Buffer1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARxDesc_Buffer2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
+                                          ((BUFFER) == ETH_DMARxDesc_Buffer2))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet DMA defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame 
+  * @{
+  */ 
+#define ETH_DropTCPIPChecksumErrorFrame_Enable   ((uint32_t)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable  ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
+                                               ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Store_Forward 
+  * @{
+  */ 
+#define ETH_ReceiveStoreForward_Enable      ((uint32_t)0x02000000)
+#define ETH_ReceiveStoreForward_Disable     ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
+                                           ((CMD) == ETH_ReceiveStoreForward_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Flush_Received_Frame 
+  * @{
+  */ 
+#define ETH_FlushReceivedFrame_Enable       ((uint32_t)0x00000000)
+#define ETH_FlushReceivedFrame_Disable      ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
+                                         ((CMD) == ETH_FlushReceivedFrame_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Store_Forward 
+  * @{
+  */ 
+#define ETH_TransmitStoreForward_Enable     ((uint32_t)0x00200000)
+#define ETH_TransmitStoreForward_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
+                                            ((CMD) == ETH_TransmitStoreForward_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Threshold_Control 
+  * @{
+  */ 
+#define ETH_TransmitThresholdControl_64Bytes     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TransmitThresholdControl_128Bytes    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TransmitThresholdControl_192Bytes    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TransmitThresholdControl_256Bytes    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TransmitThresholdControl_40Bytes     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TransmitThresholdControl_32Bytes     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TransmitThresholdControl_24Bytes     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TransmitThresholdControl_16Bytes     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Error_Frames 
+  * @{
+  */ 
+#define ETH_ForwardErrorFrames_Enable       ((uint32_t)0x00000080)
+#define ETH_ForwardErrorFrames_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
+                                          ((CMD) == ETH_ForwardErrorFrames_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames 
+  * @{
+  */ 
+#define ETH_ForwardUndersizedGoodFrames_Enable   ((uint32_t)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable  ((uint32_t)0x00000000)     
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
+                                                    ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Threshold_Control 
+  * @{
+  */ 
+#define ETH_ReceiveThresholdControl_64Bytes      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_ReceiveThresholdControl_32Bytes      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_ReceiveThresholdControl_96Bytes      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_ReceiveThresholdControl_128Bytes     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Second_Frame_Operate 
+  * @{
+  */ 
+#define ETH_SecondFrameOperate_Enable       ((uint32_t)0x00000004)
+#define ETH_SecondFrameOperate_Disable      ((uint32_t)0x00000000)  
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
+                                          ((CMD) == ETH_SecondFrameOperate_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Address_Aligned_Beats 
+  * @{
+  */ 
+#define ETH_AddressAlignedBeats_Enable      ((uint32_t)0x02000000)
+#define ETH_AddressAlignedBeats_Disable     ((uint32_t)0x00000000) 
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
+                                           ((CMD) == ETH_AddressAlignedBeats_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Fixed_Burst 
+  * @{
+  */ 
+#define ETH_FixedBurst_Enable     ((uint32_t)0x00010000)
+#define ETH_FixedBurst_Disable    ((uint32_t)0x00000000) 
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
+                                 ((CMD) == ETH_FixedBurst_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_RxDMABurstLength_1Beat          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RxDMABurstLength_2Beat          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RxDMABurstLength_4Beat          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_8Beat          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_16Beat         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_32Beat         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_TxDMABurstLength_1Beat          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TxDMABurstLength_2Beat          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TxDMABurstLength_4Beat          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_8Beat          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_16Beat         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_32Beat         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
+/** 
+  * @brief  ETH DMA Desciptor SkipLength  
+  */ 
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Arbitration 
+  * @{
+  */ 
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1   ((uint32_t)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1   ((uint32_t)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1   ((uint32_t)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1   ((uint32_t)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx             ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RxPriorTx))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Flags 
+  * @{
+  */ 
+#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_ReadWriteError    ((uint32_t)0x01000000)  /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_AccessError       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
+#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) 
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_T))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Interrupts 
+  * @{
+  */ 
+#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
+#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_transmit_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_TransmitProcess_Stopped     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TransmitProcess_Fetching    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TransmitProcess_Waiting     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
+#define ETH_DMA_TransmitProcess_Reading     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
+#define ETH_DMA_TransmitProcess_Suspended   ((uint32_t)0x00600000)  /*!< Suspended - Tx Desciptor unavailabe */
+#define ETH_DMA_TransmitProcess_Closing     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_DMA_receive_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_ReceiveProcess_Stopped      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_ReceiveProcess_Fetching     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_ReceiveProcess_Waiting      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
+#define ETH_DMA_ReceiveProcess_Suspended    ((uint32_t)0x00080000)  /*!< Suspended - Rx Desciptor unavailable */
+#define ETH_DMA_ReceiveProcess_Closing      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
+#define ETH_DMA_ReceiveProcess_Queuing      ((uint32_t)0x000E0000)  /*!< Running - queuing the recieve frame into host memory */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_overflow_ 
+  * @{
+  */ 
+#define ETH_DMA_Overflow_RxFIFOCounter      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
+                                           ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet PMT defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PMT_Flags 
+  * @{
+  */ 
+#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Poniter Reset */
+#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+                                   ((FLAG) == ETH_PMT_FLAG_MPR))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet MMC defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Tx_Interrupts 
+  * @{
+  */ 
+#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Rx_Interrupts 
+  * @{
+  */
+#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+                           ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Registers 
+  * @{
+  */ 
+#define ETH_MMCCR            ((uint32_t)0x00000100)  /*!< MMC CR register */
+#define ETH_MMCRIR           ((uint32_t)0x00000104)  /*!< MMC RIR register */
+#define ETH_MMCTIR           ((uint32_t)0x00000108)  /*!< MMC TIR register */
+#define ETH_MMCRIMR          ((uint32_t)0x0000010C)  /*!< MMC RIMR register */
+#define ETH_MMCTIMR          ((uint32_t)0x00000110)  /*!< MMC TIMR register */ 
+#define ETH_MMCTGFSCCR       ((uint32_t)0x0000014C)  /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR      ((uint32_t)0x00000150)  /*!< MMC TGFMSCCR register */ 
+#define ETH_MMCTGFCR         ((uint32_t)0x00000168)  /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR        ((uint32_t)0x00000194)  /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR        ((uint32_t)0x00000198)  /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR        ((uint32_t)0x000001C4)  /*!< MMC RGUFCR register */
+
+/** 
+  * @brief  ETH MMC registers  
+  */ 
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR)  || ((REG) == ETH_MMCRIR) || \
+                                  ((REG) == ETH_MMCTIR)  || ((REG) == ETH_MMCRIMR) || \
+                                  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+                                  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+                                  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+                                  ((REG) == ETH_MMCRGUFCR)) 
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet PTP defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PTP_time_update_method 
+  * @{
+  */ 
+#define ETH_PTP_FineUpdate        ((uint32_t)0x00000001)  /*!< Fine Update method */
+#define ETH_PTP_CoarseUpdate      ((uint32_t)0x00000000)  /*!< Coarse Update method */
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
+                                   ((UPDATE) == ETH_PTP_CoarseUpdate))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_PTP_Flags 
+  * @{
+  */ 
+#define ETH_PTP_FLAG_TSARU        ((uint32_t)0x00000020)  /*!< Addend Register Update */
+#define ETH_PTP_FLAG_TSITE        ((uint32_t)0x00000010)  /*!< Time Stamp Interrupt Trigger */
+#define ETH_PTP_FLAG_TSSTU        ((uint32_t)0x00000008)  /*!< Time Stamp Update */
+#define ETH_PTP_FLAG_TSSTI        ((uint32_t)0x00000004)  /*!< Time Stamp Initialize */
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSITE) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
+                                   ((FLAG) == ETH_PTP_FLAG_TSSTI))
+/** 
+  * @brief  ETH PTP subsecond increment  
+  */ 
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_PTP_time_sign 
+  * @{
+  */ 
+#define ETH_PTP_PositiveTime      ((uint32_t)0x00000000)  /*!< Positive time value */
+#define ETH_PTP_NegativeTime      ((uint32_t)0x80000000)  /*!< Negative time value */
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
+                                    ((SIGN) == ETH_PTP_NegativeTime))
+
+/** 
+  * @brief  ETH PTP time stamp low update  
+  */ 
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
+
+/** 
+  * @brief  ETH PTP registers  
+  */ 
+#define ETH_PTPTSCR     ((uint32_t)0x00000700)  /*!< PTP TSCR register */
+#define ETH_PTPSSIR     ((uint32_t)0x00000704)  /*!< PTP SSIR register */
+#define ETH_PTPTSHR     ((uint32_t)0x00000708)  /*!< PTP TSHR register */
+#define ETH_PTPTSLR     ((uint32_t)0x0000070C)  /*!< PTP TSLR register */
+#define ETH_PTPTSHUR    ((uint32_t)0x00000710)  /*!< PTP TSHUR register */
+#define ETH_PTPTSLUR    ((uint32_t)0x00000714)  /*!< PTP TSLUR register */
+#define ETH_PTPTSAR     ((uint32_t)0x00000718)  /*!< PTP TSAR register */
+#define ETH_PTPTTHR     ((uint32_t)0x0000071C)  /*!< PTP TTHR register */
+#define ETH_PTPTTLR     ((uint32_t)0x00000720)  /* PTP TTLR register */
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
+                                  ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
+                                  ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
+                                  ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
+                                  ((REG) == ETH_PTPTTLR)) 
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions
+  * @{
+  */ 
+void ETH_DeInit(void);
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+void  ETH_Start(void);
+uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength);
+uint32_t ETH_HandleRxPkt(u8 *ppkt);
+uint32_t ETH_GetRxPktSize(void);
+void ETH_DropRxPkt(void);
+
+/** 
+  * @brief  PHY  
+  */ 
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
+uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
+uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
+
+/** 
+  * @brief  MAC  
+  */ 
+void ETH_MACTransmissionCmd(FunctionalState NewState);
+void ETH_MACReceptionCmd(FunctionalState NewState);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);  
+void ETH_BackPressureActivationCmd(FunctionalState NewState); 
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);  
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
+void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);
+void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
+
+/** 
+  * @brief  DMA Tx/Rx descriptors  
+  */ 
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
+
+/** 
+  * @brief  DMA
+  */ 
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
+uint32_t ETH_GetTransmitProcessState(void);
+uint32_t ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState NewState);
+void ETH_DMAReceptionCmd(FunctionalState NewState);
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
+uint32_t ETH_GetCurrentTxDescStartAddress(void);
+uint32_t ETH_GetCurrentRxDescStartAddress(void);
+uint32_t ETH_GetCurrentTxBufferAddress(void);
+uint32_t ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+
+/** 
+  * @brief  PMT  
+  */ 
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
+void ETH_PowerDownCmd(FunctionalState NewState);
+
+/** 
+  * @brief  MMC  
+  */ 
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
+
+/** 
+  * @brief  PTP  
+  */ 
+uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab);
+uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab);
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
+void ETH_EnablePTPTimeStampAddend(void);
+void ETH_EnablePTPTimeStampInterruptTrigger(void);
+void ETH_EnablePTPTimeStampUpdate(void);
+void ETH_InitializePTPTimeStamp(void);
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
+void ETH_PTPTimeStampCmd(FunctionalState NewState);
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampAddend(uint32_t Value);
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ETH_H */
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

bsp/stm32f20x/stm32f20x_it.c

@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    Project/Template/stm32f10x_it.c 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f20x_it.h"
+#include <board.h>
+#include <rtthread.h>
+
+/** @addtogroup Template_Project
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @}
+  */ 
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

bsp/stm32f20x/stm32f20x_it.h

@@ -0,0 +1,53 @@
+/**
+  ******************************************************************************
+  * @file    Project/Template/stm32f10x_it.h 
+  * @author  MCD Application Team
+  * @version V3.1.0
+  * @date    06/19/2009
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include <stm32f2xx.h>
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

bsp/stm32f20x/stm32f2xx_conf.h

@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    USART/USART_Printf/stm32f2xx_conf.h  
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F2xx_CONF_H
+#define __STM32F2xx_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f2xx_adc.h"
+#include "stm32f2xx_can.h"
+#include "stm32f2xx_crc.h"
+#include "stm32f2xx_cryp.h"
+#include "stm32f2xx_dac.h"
+#include "stm32f2xx_dbgmcu.h"
+#include "stm32f2xx_dcmi.h"
+#include "stm32f2xx_dma.h"
+#include "stm32f2xx_exti.h"
+#include "stm32f2xx_flash.h"
+#include "stm32f2xx_fsmc.h"
+#include "stm32f2xx_hash.h"
+#include "stm32f2xx_gpio.h"
+#include "stm32f2xx_i2c.h"
+#include "stm32f2xx_iwdg.h"
+#include "stm32f2xx_pwr.h"
+#include "stm32f2xx_rcc.h"
+#include "stm32f2xx_rng.h"
+#include "stm32f2xx_rtc.h"
+#include "stm32f2xx_sdio.h"
+#include "stm32f2xx_spi.h"
+#include "stm32f2xx_syscfg.h"
+#include "stm32f2xx_tim.h"
+#include "stm32f2xx_usart.h"
+#include "stm32f2xx_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* If an external clock source is used, then the value of the following define 
+   should be set to the value of the external clock source, else, if no external 
+   clock is used, keep this define commented */
+/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
+
+
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F2xx_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

bsp/stm32f20x/stm32f2xx_eth.c

@@ -0,0 +1,3741 @@
+/**
+  ******************************************************************************
+  * @file    stm32f2xx_eth.c
+  * @author  MCD Application Team
+  * @version V0.0.1
+  * @date    10/21/2010
+  * @brief   This file provides all the ETH firmware functions for STM32F2xx devices.
+  *          This driver is based on V1.1.0 of "stm32_eth.c" driver, and updated
+  *          to support new feature added in STM32F2xx devices (Enhanced DMA descriptors)    
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx_eth.h"
+#include "stm32f2xx_rcc.h"
+
+
+/** @addtogroup STM32F2XX_ETH_Driver
+  * @brief ETH driver modules
+  * @{
+  */
+
+/** @defgroup ETH_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+#define DP83848_PHY_ADDRESS       0x01 /* Relative to STM3220F-EVAL Board */
+
+/** @defgroup ETH_Private_Defines
+  * @{
+  */ 
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
+ETH_DMADESCTypeDef  *DMATxDescToSet;
+ETH_DMADESCTypeDef  *DMARxDescToGet;
+
+ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
+ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3) 
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)  
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH      8
+
+/* ETHERNET Missed frames counter Shift */
+#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT        3
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16
+
+/* ETHERNET errors */
+#define  ETH_ERROR              ((uint32_t)0)
+#define  ETH_SUCCESS            ((uint32_t)1)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_FunctionPrototypes
+  * @{
+  */ 
+  
+#ifndef USE_Delay
+static void ETH_Delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+  
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the ETHERNET peripheral registers to their default reset values.
+  * @param  None 
+  * @retval None
+  */
+void ETH_DeInit(void)
+{
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
+  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the ETHERNET peripheral according to the specified
+  *   parameters in the ETH_InitStruct .
+  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains
+  *   the configuration information for the specified ETHERNET peripheral.
+  * @param PHYAddress: external PHY address                    
+  * @retval ETH_ERROR: Ethernet initialization failed
+  *         ETH_SUCCESS: Ethernet successfully initialized                 
+  */
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
+{
+  uint32_t RegValue = 0, tmpreg = 0;
+  __IO uint32_t i = 0;
+  RCC_ClocksTypeDef  rcc_clocks;
+  uint32_t hclk = 60000000;
+  __IO uint32_t timeout = 0;
+  /* Check the parameters */
+  /* MAC --------------------------*/ 
+  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
+  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
+  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
+  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
+  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
+  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
+  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
+  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
+  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
+  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
+  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
+  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
+  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
+  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
+  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
+  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
+  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
+  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
+  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
+  assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
+  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));  
+  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
+  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
+  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
+  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
+  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
+  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
+  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
+  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
+  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
+  /* DMA --------------------------*/
+  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
+  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
+  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
+  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
+  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
+  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
+  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
+  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
+  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
+  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
+  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
+  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
+  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); 
+  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));  
+  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));       
+  /*-------------------------------- MAC Config ------------------------------*/   
+  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIAR;
+  /* Clear CSR Clock Range CR[2:0] bits */
+  tmpreg &= MACMIIAR_CR_MASK;
+  /* Get hclk frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  hclk = rcc_clocks.HCLK_Frequency;
+  /* Set CR bits depending on hclk value */
+  if((hclk >= 20000000)&&(hclk < 35000000))
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+  }
+  else if((hclk >= 35000000)&&(hclk < 60000000))
+  {
+    /* CSR Clock Range between 35-60 MHz */ 
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;    
+  }  
+  else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
+  {
+    /* CSR Clock Range between 60-72 MHz */   
+    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;    
+  }
+  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+  ETH->MACMIIAR = (uint32_t)tmpreg;  
+  /*-------------------- PHY initialization and configuration ----------------*/
+  /* Put the PHY in reset mode */
+  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
+  {
+    /* Return ERROR in case of write timeout */
+    return ETH_ERROR;
+  }
+  
+  /* Delay to assure PHY reset */
+  _eth_delay_(PHY_ResetDelay);
+  
+    
+  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
+  {  
+    /* We wait for linked satus... */
+    do
+    {
+      timeout++;
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+      return ETH_ERROR;
+    }
+    /* Reset Timeout counter */
+    timeout = 0;
+    
+    /* Enable Auto-Negotiation */
+    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+    
+    /* Wait until the autonegotiation will be completed */
+    do
+    {
+      timeout++;
+    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));  
+    /* Return ERROR in case of timeout */
+    if(timeout == PHY_READ_TO)
+    {
+      return ETH_ERROR;
+    }
+    /* Reset Timeout counter */
+    timeout = 0;
+    
+    /* Read the result of the autonegotiation */
+    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
+  
+    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
+    if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
+    {
+      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
+      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
+            
+    }
+    else
+    {
+      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
+      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;           
+    }
+    /* Configure the MAC with the speed fixed by the autonegotiation process */
+    if(RegValue & PHY_Speed_Status)
+    {  
+      /* Set Ethernet speed to 10M following the autonegotiation */    
+      ETH_InitStruct->ETH_Speed = ETH_Speed_10M; 
+    }
+    else
+    {   
+      /* Set Ethernet speed to 100M following the autonegotiation */ 
+      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;      
+    }    
+  }
+  else
+  {
+    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
+                                                   (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
+    {
+      /* Return ERROR in case of write timeout */
+      return ETH_ERROR;
+    }
+    /* Delay to assure PHY configuration */
+    _eth_delay_(PHY_ConfigDelay);
+    
+  }
+  /*------------------------ ETHERNET MACCR Configuration --------------------*/
+  /* Get the ETHERNET MACCR value */  
+  tmpreg = ETH->MACCR;
+  /* Clear WD, PCE, PS, TE and RE bits */
+  tmpreg &= MACCR_CLEAR_MASK;
+  /* Set the WD bit according to ETH_Watchdog value */
+  /* Set the JD: bit according to ETH_Jabber value */
+  /* Set the IFG bit according to ETH_InterFrameGap value */ 
+  /* Set the DCRS bit according to ETH_CarrierSense value */  
+  /* Set the FES bit according to ETH_Speed value */ 
+  /* Set the DO bit according to ETH_ReceiveOwn value */ 
+  /* Set the LM bit according to ETH_LoopbackMode value */ 
+  /* Set the DM bit according to ETH_Mode value */ 
+  /* Set the IPCO bit according to ETH_ChecksumOffload value */                   
+  /* Set the DR bit according to ETH_RetryTransmission value */ 
+  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ 
+  /* Set the BL bit according to ETH_BackOffLimit value */ 
+  /* Set the DC bit according to ETH_DeferralCheck value */                          
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | 
+                  ETH_InitStruct->ETH_Jabber | 
+                  ETH_InitStruct->ETH_InterFrameGap |
+                  ETH_InitStruct->ETH_CarrierSense |
+                  ETH_InitStruct->ETH_Speed | 
+                  ETH_InitStruct->ETH_ReceiveOwn |
+                  ETH_InitStruct->ETH_LoopbackMode |
+                  ETH_InitStruct->ETH_Mode | 
+                  ETH_InitStruct->ETH_ChecksumOffload |    
+                  ETH_InitStruct->ETH_RetryTransmission | 
+                  ETH_InitStruct->ETH_AutomaticPadCRCStrip | 
+                  ETH_InitStruct->ETH_BackOffLimit | 
+                  ETH_InitStruct->ETH_DeferralCheck);
+  /* Write to ETHERNET MACCR */
+  ETH->MACCR = (uint32_t)tmpreg;
+  
+  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
+  /* Set the RA bit according to ETH_ReceiveAll value */
+  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
+  /* Set the PCF bit according to ETH_PassControlFrames value */
+  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
+  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
+  /* Set the PR bit according to ETH_PromiscuousMode value */
+  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
+  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
+  /* Write to ETHERNET MACFFR */  
+  ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | 
+                          ETH_InitStruct->ETH_SourceAddrFilter |
+                          ETH_InitStruct->ETH_PassControlFrames |
+                          ETH_InitStruct->ETH_BroadcastFramesReception | 
+                          ETH_InitStruct->ETH_DestinationAddrFilter |
+                          ETH_InitStruct->ETH_PromiscuousMode |
+                          ETH_InitStruct->ETH_MulticastFramesFilter |
+                          ETH_InitStruct->ETH_UnicastFramesFilter); 
+  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+  /* Write to ETHERNET MACHTHR */
+  ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
+  /* Write to ETHERNET MACHTLR */
+  ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
+  /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+  /* Get the ETHERNET MACFCR value */  
+  tmpreg = ETH->MACFCR;
+  /* Clear xx bits */
+  tmpreg &= MACFCR_CLEAR_MASK;
+  
+  /* Set the PT bit according to ETH_PauseTime value */
+  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
+  /* Set the PLT bit according to ETH_PauseLowThreshold value */
+  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
+  /* Set the RFE bit according to ETH_ReceiveFlowControl value */
+  /* Set the TFE bit according to ETH_TransmitFlowControl value */  
+  tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | 
+                   ETH_InitStruct->ETH_ZeroQuantaPause |
+                   ETH_InitStruct->ETH_PauseLowThreshold |
+                   ETH_InitStruct->ETH_UnicastPauseFrameDetect | 
+                   ETH_InitStruct->ETH_ReceiveFlowControl |
+                   ETH_InitStruct->ETH_TransmitFlowControl); 
+  /* Write to ETHERNET MACFCR */
+  ETH->MACFCR = (uint32_t)tmpreg;
+  /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+  /* Set the ETV bit according to ETH_VLANTagComparison value */
+  /* Set the VL bit according to ETH_VLANTagIdentifier value */  
+  ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | 
+                             ETH_InitStruct->ETH_VLANTagIdentifier); 
+       
+  /*-------------------------------- DMA Config ------------------------------*/
+  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+  /* Get the ETHERNET DMAOMR value */  
+  tmpreg = ETH->DMAOMR;
+  /* Clear xx bits */
+  tmpreg &= DMAOMR_CLEAR_MASK;
+  
+  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
+  /* Set the RSF bit according to ETH_ReceiveStoreForward value */
+  /* Set the DFF bit according to ETH_FlushReceivedFrame value */
+  /* Set the TSF bit according to ETH_TransmitStoreForward value */
+  /* Set the TTC bit according to ETH_TransmitThresholdControl value */
+  /* Set the FEF bit according to ETH_ForwardErrorFrames value */
+  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
+  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
+  /* Set the OSF bit according to ETH_SecondFrameOperate value */
+  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | 
+                  ETH_InitStruct->ETH_ReceiveStoreForward |
+                  ETH_InitStruct->ETH_FlushReceivedFrame |
+                  ETH_InitStruct->ETH_TransmitStoreForward | 
+                  ETH_InitStruct->ETH_TransmitThresholdControl |
+                  ETH_InitStruct->ETH_ForwardErrorFrames |
+                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
+                  ETH_InitStruct->ETH_ReceiveThresholdControl |                                   
+                  ETH_InitStruct->ETH_SecondFrameOperate); 
+  /* Write to ETHERNET DMAOMR */
+  ETH->DMAOMR = (uint32_t)tmpreg;
+  
+  /*----------------------- ETHERNET DMABMR Configuration --------------------*/ 
+  /* Set the AAL bit according to ETH_AddressAlignedBeats value */
+  /* Set the FB bit according to ETH_FixedBurst value */
+  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
+  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
+  /* Set the DSL bit according to ETH_DesciptorSkipLength value */
+  /* Set the PR and DA bits according to ETH_DMAArbitration value */         
+  ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | 
+                          ETH_InitStruct->ETH_FixedBurst |
+                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+                          ETH_InitStruct->ETH_TxDMABurstLength | 
+                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
+                          ETH_InitStruct->ETH_DMAArbitration |
+                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+                          
+  #ifdef USE_ENHANCED_DMA_DESCRIPTORS
+    /* Enable the Enhanced DMA descriptors */
+    ETH->DMABMR |= ETH_DMABMR_EDE;
+  #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+  /* Return Ethernet configuration success */
+  return ETH_SUCCESS;
+}
+
+/**
+  * @brief  Fills each ETH_InitStruct member with its default value.
+  * @param  ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
+{
+  /* ETH_InitStruct members default value */
+  /*------------------------   MAC   -----------------------------------*/     
+  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;           
+  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;                   
+  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;                                                     
+  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;                                                                                                                          
+  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;                              
+  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;                       
+  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;               
+  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;              
+  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;                       
+  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;                                                            
+  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;                                                                                  
+  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                         
+  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;                                                                
+  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;                                                                                                                  
+  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;                                                               
+  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;                                
+  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;          
+  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;      
+  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                             
+  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;      
+  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;      
+  ETH_InitStruct->ETH_HashTableHigh = 0x0;                
+  ETH_InitStruct->ETH_HashTableLow = 0x0;                     
+  ETH_InitStruct->ETH_PauseTime = 0x0;                 
+  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;            
+  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;         
+  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;   
+  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;        
+  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;      
+  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;          
+  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;          
+  /*------------------------   DMA   -----------------------------------*/  
+  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; 
+  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;       
+  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;       
+  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
+  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;  
+  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
+  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; 
+  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;   
+  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
+  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
+  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
+  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
+  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
+}
+
+/**
+  * @brief  Enables ENET MAC and DMA reception/transmission 
+  * @param  None
+  * @retval None
+  */
+void ETH_Start(void)
+{
+  /* Enable transmit state machine of the MAC for transmission on the MII */  
+  ETH_MACTransmissionCmd(ENABLE);
+  /* Flush Transmit FIFO */
+  ETH_FlushTransmitFIFO();
+  /* Enable receive state machine of the MAC for reception from the MII */  
+  ETH_MACReceptionCmd(ENABLE);
+ 
+  /* Start DMA transmission */
+  ETH_DMATransmissionCmd(ENABLE); 
+  /* Start DMA reception */
+  ETH_DMAReceptionCmd(ENABLE);   
+}
+
+/**
+  * @brief  Transmits a packet, from application buffer, pointed by ppkt.
+  * @param  ppkt: pointer to the application's packet buffer to transmit.
+  * @param  FrameLength: Tx Packet size.
+  * @retval ETH_ERROR: in case of Tx desc owned by DMA
+  *         ETH_SUCCESS: for correct transmission
+  */
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
+{ 
+  uint32_t offset = 0;
+    
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+  
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      
+  for(offset=0; offset<FrameLength; offset++)       
+  {
+    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+        
+  /* Setting the Frame Length: bits[12:0] */
+  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    
+  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_TBUS;
+    /* Resume DMA transmission*/
+    ETH->DMATPDR = 0;
+  }
+  
+  /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */  
+  /* Chained Mode */
+  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+  {     
+    /* Selects the next DMA Tx descriptor list for next buffer to send */ 
+    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);    
+  }
+  else /* Ring Mode */
+  {  
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);      
+    }
+    else
+    {  
+      /* Selects the next DMA Tx descriptor list for next buffer to send */
+      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
+    }
+  }
+  /* Return SUCCESS */
+  return ETH_SUCCESS;   
+}
+
+/**
+  * @brief  Receives a packet and copies it to memory pointed by ppkt.
+  * @param  ppkt: pointer to the application packet receive buffer.
+  * @retval ETH_ERROR: if there is error in reception
+  *         framelength: received packet size if packet reception is correct
+  */
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
+{ 
+  uint32_t offset = 0, framelength = 0;
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR; 
+  }
+  
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && 
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&  
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))  
+  {      
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+    for(offset=0; offset<framelength; offset++)       
+    {
+      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+    }
+  }
+  else
+  {
+    /* Return ERROR */
+    framelength = ETH_ERROR;
+  }
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN; 
+ 
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)  
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_RBUS;
+    /* Resume DMA reception */
+    ETH->DMARPDR = 0;
+  }
+  
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */      
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {     
+    /* Selects the next DMA Rx descriptor list for next buffer to read */ 
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);    
+  }
+  else /* Ring Mode */
+  {   
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);      
+    }
+    else
+    { 
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
+    }
+  }
+  
+  /* Return Frame Length/ERROR */
+  return (framelength);  
+}
+
+/**
+  * @brief  Get the size of received the received packet.
+  * @param  None
+  * @retval framelength: received packet size 
+  */
+uint32_t ETH_GetRxPktSize(void)
+{
+  uint32_t frameLength = 0;
+  if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+  {
+    /* Get the size of the packet: including 4 bytes of the CRC */
+    frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
+  }
+ 
+ /* Return Frame Length */ 
+ return frameLength;
+}
+
+/**
+  * @brief  Drop a Received packet (too small packet, etc...)
+  * @param  None
+  * @retval None
+  */
+void ETH_DropRxPkt(void)
+{
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;  
+  /* Chained Mode */
+  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {
+    /* Selects the next DMA Rx descriptor list for next buffer read */
+    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+  }
+  else /* Ring Mode */
+  {
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer read: this will
+         be the first Rx descriptor in this case */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+    }
+    else
+    {
+      /* Selects the next DMA Rx descriptor list for next buffer read */
+      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+    }
+  }
+}
+
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+/**
+  * @brief  Enables or disables the Enhanced descriptor structure.
+  * @param  NewState: new state of the Enhanced descriptor structure.
+  *   This parameter can be: ENABLE or DISABLE. 
+  * @retval None
+  */
+void ETH_EnhancedDescriptorCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable enhanced descriptor structure */
+    ETH->DMABMR |= ETH_DMABMR_EDE;  
+  }
+  else
+  {
+    /* Disable enhanced descriptor structure */
+    ETH->DMABMR &= ~ETH_DMABMR_EDE;
+  }
+}
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+/*---------------------------------  PHY  ------------------------------------*/
+/**
+  * @brief  Read a PHY register
+  * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values: 0,..,31                  
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *   This parameter can be one of the following values: 
+  *     @arg PHY_BCR: Tranceiver Basic Control Register 
+  *     @arg PHY_BSR: Tranceiver Basic Status Register 
+  *     @arg PHY_SR : Tranceiver Status Register    
+  *     @arg More PHY register could be read depending on the used PHY
+  * @retval ETH_ERROR: in case of timeout
+  *         MAC MIIDR register value: Data read from the selected PHY register (correct read )
+  */
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
+{
+  uint32_t tmpreg = 0;     
+__IO uint32_t timeout = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_ETH_PHY_REG(PHYReg));
+  
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIAR;
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_MASK;
+  /* Prepare the MII address register value */
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
+  tmpreg &= ~ETH_MACMIIAR_MW;                              /* Set the read mode */
+  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
+  /* Write the result value into the MII Address register */
+  ETH->MACMIIAR = tmpreg;
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH->MACMIIAR;
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return (uint16_t)ETH_ERROR;
+  }
+  
+  /* Return data register value */
+  return (uint16_t)(ETH->MACMIIDR);
+}
+
+/**
+  * @brief  Write to a PHY register
+  * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values: 0,..,31
+  * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. 
+  *   This parameter can be one of the following values: 
+  *     @arg PHY_BCR    : Tranceiver Control Register  
+  *     @arg More PHY register could be written depending on the used PHY
+  * @param  PHYValue: the value to write
+  * @retval ETH_ERROR: in case of timeout
+  *         ETH_SUCCESS: for correct write
+  */
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
+{
+  uint32_t tmpreg = 0;     
+  __IO uint32_t timeout = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_ETH_PHY_REG(PHYReg));
+  
+  /* Get the ETHERNET MACMIIAR value */
+  tmpreg = ETH->MACMIIAR;
+  /* Keep only the CSR Clock Range CR[2:0] bits value */
+  tmpreg &= ~MACMIIAR_CR_MASK;
+  /* Prepare the MII register address value */
+  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */
+  tmpreg |= ETH_MACMIIAR_MW;                               /* Set the write mode */
+  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */
+  /* Give the value to the MII data register */
+  ETH->MACMIIDR = PHYValue;
+  /* Write the result value into the MII Address register */
+  ETH->MACMIIAR = tmpreg;
+  /* Check for the Busy flag */
+  do
+  {
+    timeout++;
+    tmpreg = ETH->MACMIIAR;
+  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_WRITE_TO)
+  {
+    return ETH_ERROR;
+  }
+  
+  /* Return SUCCESS */
+  return ETH_SUCCESS;  
+}
+
+/**
+  * @brief  Enables or disables the PHY loopBack mode.
+  * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal
+  *  loopback at MII level
+  * @param  PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. 
+  *   This parameter can be one of the following values:                   
+  * @param  NewState: new state of the PHY loopBack mode.
+  *   This parameter can be: ENABLE or DISABLE.    
+  * @retval ETH_ERROR: in case of bad PHY configuration
+  *         ETH_SUCCESS: for correct PHY configuration
+  */
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
+{
+  uint16_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  /* Get the PHY configuration to update it */
+  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PHY loopback mode */
+    tmpreg |= PHY_Loopback;  
+  }
+  else
+  {
+    /* Disable the PHY loopback mode: normal mode */
+    tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
+  }
+  /* Update the PHY control register with the new configuration */
+  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
+  {
+    return ETH_SUCCESS;
+  }
+  else
+  {
+    /* Return SUCCESS */
+    return ETH_ERROR; 
+  }   
+}
+
+/*---------------------------------  MAC  ------------------------------------*/
+/**
+  * @brief  Enables or disables the MAC transmission.
+  * @param  NewState: new state of the MAC transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACTransmissionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC transmission */
+    ETH->MACCR |= ETH_MACCR_TE;  
+  }
+  else
+  {
+    /* Disable the MAC transmission */
+    ETH->MACCR &= ~ETH_MACCR_TE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC reception.
+  * @param  NewState: new state of the MAC reception.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACReceptionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC reception */
+    ETH->MACCR |= ETH_MACCR_RE;  
+  }
+  else
+  {
+    /* Disable the MAC reception */
+    ETH->MACCR &= ~ETH_MACCR_RE;
+  }
+}
+
+/**
+  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
+  * @param  None
+  * @retval The new state of flow control busy status bit (SET or RESET).
+  */
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  /* The Flow Control register should not be written to until this bit is cleared */
+  if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Initiate a Pause Control Frame (Full-duplex only).
+  * @param  None
+  * @retval None
+  */
+void ETH_InitiatePauseControlFrame(void)  
+{ 
+  /* When Set In full duplex MAC initiates pause control frame */
+  ETH->MACFCR |= ETH_MACFCR_FCBBPA;  
+}
+
+/**
+  * @brief  Enables or disables the MAC BackPressure operation activation (Half-duplex only).
+  * @param  NewState: new state of the MAC BackPressure operation activation.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_BackPressureActivationCmd(FunctionalState NewState)   
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Activate the MAC BackPressure operation */
+    /* In Half duplex: during backpressure, when the MAC receives a new frame,
+    the transmitter starts sending a JAM pattern resulting in a collision */
+    ETH->MACFCR |= ETH_MACFCR_FCBBPA; 
+  }
+  else
+  {
+    /* Desactivate the MAC BackPressure operation */
+    ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; 
+  } 
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
+  * @param  ETH_MAC_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   
+  *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  
+  *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag   
+  *     @arg ETH_MAC_FLAG_MMC  : MMC flag  
+  *     @arg ETH_MAC_FLAG_PMT  : PMT flag  
+  * @retval The new state of ETHERNET MAC flag (SET or RESET).
+  */
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); 
+  if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC interrupt has occurred or not.
+  * @param  ETH_MAC_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_IT_TST   : Time stamp trigger interrupt  
+  *     @arg ETH_MAC_IT_MMCT : MMC transmit interrupt 
+  *     @arg ETH_MAC_IT_MMCR : MMC receive interrupt  
+  *     @arg ETH_MAC_IT_MMC  : MMC interrupt 
+  *     @arg ETH_MAC_IT_PMT  : PMT interrupt 
+  * @retval The new state of ETHERNET MAC interrupt (SET or RESET).
+  */
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); 
+  if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET MAC interrupts.
+  * @param  ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 
+  *     @arg ETH_MAC_IT_PMT : PMT interrupt 
+  * @param  NewState: new state of the specified ETHERNET MAC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC interrupts */
+    ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC interrupts */
+    ETH->MACIMR |= ETH_MAC_IT;
+  }
+}
+
+/**
+  * @brief  Configures the selected MAC address.
+  * @param  MacAddr: The MAC addres to configure.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_Address0 : MAC Address0 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  Addr: Pointer on MAC address buffer data (6 bytes).
+  * @retval None
+  */
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+  
+  /* Calculate the selectecd MAC address high register */
+  tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+  /* Load the selectecd MAC address high register */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
+  /* Calculate the selectecd MAC address low register */
+  tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+ 
+  /* Load the selectecd MAC address low register */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
+}
+
+/**
+  * @brief  Get the selected MAC address.
+  * @param  MacAddr: The MAC addres to return.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MAC_Address0 : MAC Address0 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  Addr: Pointer on MAC address buffer data (6 bytes).
+  * @retval None
+  */
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
+{
+  uint32_t tmpreg;
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+  
+  /* Get the selectecd MAC address high register */
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));
+ 
+  /* Calculate the selectecd MAC address buffer */
+  Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
+  Addr[4] = (tmpreg & (uint8_t)0xFF);
+  /* Load the selectecd MAC address low register */
+  tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));
+  /* Calculate the selectecd MAC address buffer */
+  Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
+  Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
+  Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
+  Addr[0] = (tmpreg & (uint8_t)0xFF);
+}
+
+/**
+  * @brief  Enables or disables the Address filter module uses the specified
+  *   ETHERNET MAC address for perfect filtering 
+  * @param  MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  NewState: new state of the specified ETHERNET MAC address use.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET MAC address for perfect filtering */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET MAC address for perfect filtering */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
+  }
+}
+
+/**
+  * @brief  Set the filter type for the specified ETHERNET MAC address 
+  * @param  MacAddr: specifies the ETHERNET MAC address 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  Filter: specifies the used frame received field for comparaison 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the
+  *                                     SA fields of the received frame.
+  *     @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the
+  *                                     DA fields of the received frame.
+  * @retval None
+  */
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
+  
+  if (Filter != ETH_MAC_AddressFilter_DA)
+  {
+    /* The selected ETHERNET MAC address is used to compare with the SA fields of the
+       received frame. */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;
+  }
+  else
+  {
+    /* The selected ETHERNET MAC address is used to compare with the DA fields of the
+       received frame. */
+    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
+  }
+}
+
+/**
+  * @brief  Set the filter type for the specified ETHERNET MAC address 
+  * @param  MacAddr: specifies the ETHERNET MAC address 
+  *   This parameter can be one of the following values: 
+  *     @arg ETH_MAC_Address1 : MAC Address1 
+  *     @arg ETH_MAC_Address2 : MAC Address2
+  *     @arg ETH_MAC_Address3 : MAC Address3
+  * @param  MaskByte: specifies the used address bytes for comparaison 
+  *   This parameter can be any combination of the following values: 
+  *     @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
+  *     @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
+  *     @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
+  *     @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
+  *     @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
+  *     @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
+  * @retval None
+  */
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+  assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
+  
+  /* Clear MBC bits in the selected MAC address  high register */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
+  /* Set the selected Filetr mask bytes */
+  (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
+}
+/*------------------------  DMA Tx/Rx Desciptors -----------------------------*/
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode.
+  * @param  DMATxDescTab: Pointer on the first Tx desc list 
+  * @param  TxBuff: Pointer on the first TxBuffer list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  * @retval None
+  */
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+  
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */   
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+    /* Set Second Address Chained bit */
+    DMATxDesc->Status = ETH_DMATxDesc_TCH;  
+       
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;  
+    }
+  }
+   
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLAR = (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors in ring mode.
+  * @param  DMATxDescTab: Pointer on the first Tx desc list 
+  * @param  TxBuff1: Pointer on the first TxBuffer1 list 
+  * @param  TxBuff2: Pointer on the first TxBuffer2 list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
+  *   for the number of Words to skip between two unchained descriptors.  
+  * @retval None
+  */
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMATxDesc;
+ 
+  /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+  DMATxDescToSet = DMATxDescTab;
+  /* Fill each DMATxDesc descriptor with the right values */  
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMATxDesc = DMATxDescTab + i;
+    /* Set Buffer1 address pointer */
+    DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Set Buffer2 address pointer */
+    DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (TxBuffCount-1))
+    {
+      /* Set Transmit End of Ring bit */
+      DMATxDesc->Status = ETH_DMATxDesc_TER;
+    }
+  }
+   
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLAR =  (uint32_t) DMATxDescTab;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  ETH_DMATxDescFlag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
+  *     @arg ETH_DMATxDesc_IC  : Interrupt on completetion
+  *     @arg ETH_DMATxDesc_LS  : Last Segment
+  *     @arg ETH_DMATxDesc_FS  : First Segment
+  *     @arg ETH_DMATxDesc_DC  : Disable CRC
+  *     @arg ETH_DMATxDesc_DP  : Disable Pad
+  *     @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
+  *     @arg ETH_DMATxDesc_CIC : Checksum insertion control    
+  *     @arg ETH_DMATxDesc_TER : Transmit End of Ring
+  *     @arg ETH_DMATxDesc_TCH : Second Address Chained
+  *     @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
+  *     @arg ETH_DMATxDesc_IHE : IP Header Error
+  *     @arg ETH_DMATxDesc_ES  : Error summary
+  *     @arg ETH_DMATxDesc_JT  : Jabber Timeout
+  *     @arg ETH_DMATxDesc_FF  : Frame Flushed: DMA/MTL flushed the frame due to SW flush
+  *     @arg ETH_DMATxDesc_PCE : Payload Checksum Error
+  *     @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
+  *     @arg ETH_DMATxDesc_NC  : No Carrier: no carrier signal from the tranceiver
+  *     @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
+  *     @arg ETH_DMATxDesc_EC  : Excessive Collision: transmission aborted after 16 collisions
+  *     @arg ETH_DMATxDesc_VF  : VLAN Frame
+  *     @arg ETH_DMATxDesc_CC  : Collision Count 
+  *     @arg ETH_DMATxDesc_ED  : Excessive Deferral
+  *     @arg ETH_DMATxDesc_UF  : Underflow Error: late data arrival from the memory
+  *     @arg ETH_DMATxDesc_DB  : Deferred Bit
+  * @retval The new state of ETH_DMATxDescFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
+  
+  if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor                     
+  * @retval The Transmit descriptor collision counter value.
+  */
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
+}
+
+/**
+  * @brief  Set the specified DMA Tx Desc Own bit.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @retval None
+  */
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
+{
+  /* Set the DMA Tx Desc Own bit */
+  DMATxDesc->Status |= ETH_DMATxDesc_OWN;
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @param  NewState: new state of the DMA Tx Desc transmit interrupt.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status |= ETH_DMATxDesc_IC;
+  }
+  else
+  {
+    /* Disable the DMA Tx Desc Transmit interrupt */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Tx Desc Transmit interrupt.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @param  DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATxDesc_LastSegment  : actual Tx desc contain last segment 
+  *     @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment                   
+  * @retval None
+  */
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
+  
+  /* Selects the DMA Tx Desc Frame segment */
+  DMATxDesc->Status |= DMATxDesc_FrameSegment;
+}
+
+/**
+  * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor 
+  * @param  DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
+  *     @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
+  *     @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+  *     @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header                                                                
+  * @retval None
+  */
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
+  
+  /* Set the selected DMA Tx desc checksum insertion control */
+  DMATxDesc->Status |= DMATxDesc_Checksum;
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc CRC.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc CRC.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc CRC */
+    DMATxDesc->Status |= ETH_DMATxDesc_DC; 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc end of ring.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc end of ring.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status |= ETH_DMATxDesc_TER;  
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc end of ring */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc second address chained.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc second address chained.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status |= ETH_DMATxDesc_TCH;  
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc second address chained */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
+    DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
+    DMATxDesc->Status |= ETH_DMATxDesc_DP; 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Tx Desc time stamp.
+  * @param  DMATxDesc: pointer on a DMA Tx descriptor
+  * @param  NewState: new state of the specified DMA Tx Desc time stamp.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status |= ETH_DMATxDesc_TTSE;  
+  }
+  else
+  {
+    /* Disable the selected DMA Tx Desc time stamp */
+    DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); 
+  }
+}
+
+/**
+  * @brief  Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
+  * @param  DMATxDesc: Pointer on a Tx desc
+  * @param  BufferSize1: specifies the Tx desc buffer1 size.
+  * @param  BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
+  * @retval None
+  */
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
+  assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
+  
+  /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
+  DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param  DMARxDescTab: Pointer on the first Rx desc list 
+  * @param  RxBuff: Pointer on the first RxBuffer list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  * @retval None
+  */
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+  
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab; 
+  /* Fill each DMARxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i;
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;  
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); 
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); 
+    }
+  }
+   
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLAR = (uint32_t) DMARxDescTab;  
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in ring mode.
+  * @param  DMARxDescTab: Pointer on the first Rx desc list 
+  * @param  RxBuff1: Pointer on the first RxBuffer1 list 
+  * @param  RxBuff2: Pointer on the first RxBuffer2 list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  *   Note: see decriptor skip length defined in ETH_DMA_InitStruct
+  *   for the number of Words to skip between two unchained descriptors.  
+  * @retval None
+  */
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMARxDesc;
+  /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+  DMARxDescToGet = DMARxDescTab; 
+  /* Fill each DMARxDesc descriptor with the right values */  
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMARxDesc = DMARxDescTab+i; 
+    /* Set Own bit of the Rx descriptor Status */
+    DMARxDesc->Status = ETH_DMARxDesc_OWN; 
+    /* Set Buffer1 size */
+    DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;  
+    /* Set Buffer1 address pointer */
+    DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); 
+    
+    /* Set Buffer2 address pointer */
+    DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); 
+    
+    /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
+       address of the list, creating a Desciptor Ring */
+    if(i == (RxBuffCount-1))
+    {
+      /* Set Receive End of Ring bit */
+      DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+    }
+  }
+   
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLAR = (uint32_t) DMARxDescTab;  
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
+  * @param  ETH_DMARxDescFlag: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMARxDesc_OWN:         OWN bit: descriptor is owned by DMA engine 
+  *     @arg ETH_DMARxDesc_AFM:         DA Filter Fail for the rx frame
+  *     @arg ETH_DMARxDesc_ES:          Error summary
+  *     @arg ETH_DMARxDesc_DE:          Desciptor error: no more descriptors for receive frame
+  *     @arg ETH_DMARxDesc_SAF:         SA Filter Fail for the received frame
+  *     @arg ETH_DMARxDesc_LE:          Frame size not matching with length field
+  *     @arg ETH_DMARxDesc_OE:          Overflow Error: Frame was damaged due to buffer overflow
+  *     @arg ETH_DMARxDesc_VLAN:        VLAN Tag: received frame is a VLAN frame
+  *     @arg ETH_DMARxDesc_FS:          First descriptor of the frame
+  *     @arg ETH_DMARxDesc_LS:          Last descriptor of the frame
+  *     @arg ETH_DMARxDesc_IPV4HCE:     IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error 
+  *     @arg ETH_DMARxDesc_LC:          Late collision occurred during reception
+  *     @arg ETH_DMARxDesc_FT:          Frame type - Ethernet, otherwise 802.3
+  *     @arg ETH_DMARxDesc_RWT:         Receive Watchdog Timeout: watchdog timer expired during reception
+  *     @arg ETH_DMARxDesc_RE:          Receive error: error reported by MII interface
+  *     @arg ETH_DMARxDesc_DE:          Dribble bit error: frame contains non int multiple of 8 bits
+  *     @arg ETH_DMARxDesc_CE:          CRC error
+  *     @arg ETH_DMARxDesc_MAMPCE:      Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+  * @retval The new state of ETH_DMARxDescFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
+  if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+/**
+  * @brief  Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not.
+  * @param  DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor
+  * @param  ETH_DMAPTPRxDescFlag: specifies the extended flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMAPTPRxDesc_PTPV:   PTP version  
+  *     @arg ETH_DMAPTPRxDesc_PTPFT:  PTP frame type
+  *     @arg ETH_DMAPTPRxDesc_PTPMT:  PTP message type   
+  *     @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received   
+  *     @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received    
+  *     @arg ETH_DMAPTPRxDesc_IPCB:   IP checksum bypassed  
+  *     @arg ETH_DMAPTPRxDesc_IPPE:   IP payload error
+  *     @arg ETH_DMAPTPRxDesc_IPHE:   IP header error 
+  *     @arg ETH_DMAPTPRxDesc_IPPT:   IP payload type 
+  * @retval The new state of ETH_DMAPTPRxDescExtendedFlag (SET or RESET).
+  */
+FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag)
+{
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(ETH_DMAPTPRxDescExtendedFlag));
+
+  if ((DMAPTPRxDesc->ExtendedStatus & ETH_DMAPTPRxDescExtendedFlag) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+
+/**
+  * @brief  Set the specified DMA Rx Desc Own bit.
+  * @param  DMARxDesc: Pointer on a Rx desc
+  * @retval None
+  */
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Set the DMA Rx Desc Own bit */
+  DMARxDesc->Status |= ETH_DMARxDesc_OWN;
+}
+
+/**
+  * @brief  Returns the specified DMA Rx Desc frame length.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor                     
+  * @retval The Rx descriptor received frame length.
+  */
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
+{
+  /* Return the Receive descriptor frame length */
+  return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/**
+  * @brief  Enables or disables the specified DMA Rx Desc receive interrupt.
+  * @param  DMARxDesc: Pointer on a Rx desc
+  * @param  NewState: new state of the specified DMA Rx Desc interrupt.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
+  }
+  else
+  {
+    /* Disable the DMA Rx Desc receive interrupt */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Rx Desc end of ring.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
+  * @param  NewState: new state of the specified DMA Rx Desc end of ring.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;  
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc end of ring */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); 
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA Rx Desc second address chained.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor
+  * @param  NewState: new state of the specified DMA Rx Desc second address chained.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;  
+  }
+  else
+  {
+    /* Disable the selected DMA Rx Desc second address chained */
+    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); 
+  }
+}
+
+/**
+  * @brief  Returns the specified ETHERNET DMA Rx Desc buffer size.
+  * @param  DMARxDesc: pointer on a DMA Rx descriptor 
+  * @param  DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
+  *   This parameter can be any one of the following values:
+  *     @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
+  *     @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2                     
+  * @retval The Receive descriptor frame length.
+  */
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
+  
+  if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
+  {
+    /* Return the DMA Rx Desc buffer2 size */
+    return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); 
+  }
+  else
+  {
+    /* Return the DMA Rx Desc buffer1 size */
+    return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); 
+  }
+}
+
+/*---------------------------------  DMA  ------------------------------------*/
+/**
+  * @brief  Resets all MAC subsystem internal registers and logic.
+  * @param  None
+  * @retval None
+  */
+void ETH_SoftwareReset(void)
+{
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+/**
+  * @brief  Checks whether the ETHERNET software reset bit is set or not.
+  * @param  None
+  * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
+  */
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+  if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+  * @param  ETH_DMA_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
+  *     @arg ETH_DMA_FLAG_PMT : PMT flag 
+  *     @arg ETH_DMA_FLAG_MMC : MMC flag 
+  *     @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
+  *     @arg ETH_DMA_FLAG_ReadWriteError    : Error bits 0-write trnsf, 1-read transfr
+  *     @arg ETH_DMA_FLAG_AccessError       : Error bits 0-Rx DMA, 1-Tx DMA
+  *     @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+  *     @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag  
+  *     @arg ETH_DMA_FLAG_ER  : Early receive flag 
+  *     @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
+  *     @arg ETH_DMA_FLAG_ET  : Early transmit flag 
+  *     @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
+  *     @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
+  *     @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_R   : Receive flag 
+  *     @arg ETH_DMA_FLAG_TU  : Underflow flag 
+  *     @arg ETH_DMA_FLAG_RO  : Overflow flag 
+  *     @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
+  *     @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
+  *     @arg ETH_DMA_FLAG_T   : Transmit flag 
+  * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+  */
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
+{  
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
+  if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ETHERNET’s DMA pending flag.
+  * @param  ETH_DMA_FLAG: specifies the flag to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+  *     @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag 
+  *     @arg ETH_DMA_FLAG_ER  : Early receive flag 
+  *     @arg ETH_DMA_FLAG_FBE : Fatal bus error flag 
+  *     @arg ETH_DMA_FLAG_ETI : Early transmit flag 
+  *     @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag 
+  *     @arg ETH_DMA_FLAG_RPS : Receive process stopped flag 
+  *     @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_R   : Receive flag 
+  *     @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag 
+  *     @arg ETH_DMA_FLAG_RO  : Receive Overflow flag 
+  *     @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag 
+  *     @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag 
+  *     @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag 
+  *     @arg ETH_DMA_FLAG_T   : Transmit flag
+  * @retval None
+  */
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
+  
+  /* Clear the selected ETHERNET DMA FLAG */
+  ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA interrupt has occured or not.
+  * @param  ETH_DMA_IT: specifies the interrupt source to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
+  *     @arg ETH_DMA_IT_PMT : PMT interrupt 
+  *     @arg ETH_DMA_IT_MMC : MMC interrupt
+  *     @arg ETH_DMA_IT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_IT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ET  : Early transmit interrupt 
+  *     @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_R   : Receive interrupt 
+  *     @arg ETH_DMA_IT_TU  : Underflow interrupt 
+  *     @arg ETH_DMA_IT_RO  : Overflow interrupt 
+  *     @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_IT_T   : Transmit interrupt 
+  * @retval The new state of ETH_DMA_IT (SET or RESET).
+  */
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
+{  
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
+  if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the ETHERNET’s DMA IT pending bit.
+  * @param  ETH_DMA_IT: specifies the interrupt pending bit to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_DMA_IT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_IT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ETI : Early transmit interrupt 
+  *     @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_R   : Receive interrupt 
+  *     @arg ETH_DMA_IT_TU  : Transmit Underflow interrupt 
+  *     @arg ETH_DMA_IT_RO  : Receive Overflow interrupt 
+  *     @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_IT_T   : Transmit interrupt
+  * @retval None
+  */
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+  
+  /* Clear the selected ETHERNET DMA IT */
+  ETH->DMASR = (uint32_t) ETH_DMA_IT;
+}
+
+/**
+  * @brief  Returns the ETHERNET DMA Transmit Process State.
+  * @param  None
+  * @retval The new ETHERNET DMA Transmit Process State:
+  *   This can be one of the following values:
+  *     - ETH_DMA_TransmitProcess_Stopped   : Stopped - Reset or Stop Tx Command issued
+  *     - ETH_DMA_TransmitProcess_Fetching  : Running - fetching the Tx descriptor 
+  *     - ETH_DMA_TransmitProcess_Waiting   : Running - waiting for status
+  *     - ETH_DMA_TransmitProcess_Reading   : unning - reading the data from host memory
+  *     - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
+  *     - ETH_DMA_TransmitProcess_Closing   : Running - closing Rx descriptor  
+  */
+uint32_t ETH_GetTransmitProcessState(void)
+{
+  return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); 
+}
+
+/**
+  * @brief  Returns the ETHERNET DMA Receive Process State.
+  * @param  None
+  * @retval The new ETHERNET DMA Receive Process State:
+  *   This can be one of the following values:
+  *     - ETH_DMA_ReceiveProcess_Stopped   : Stopped - Reset or Stop Rx Command issued
+  *     - ETH_DMA_ReceiveProcess_Fetching  : Running - fetching the Rx descriptor 
+  *     - ETH_DMA_ReceiveProcess_Waiting   : Running - waiting for packet
+  *     - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
+  *     - ETH_DMA_ReceiveProcess_Closing   : Running - closing descriptor
+  *     - ETH_DMA_ReceiveProcess_Queuing   : Running - queuing the recieve frame into host memory  
+  */
+uint32_t ETH_GetReceiveProcessState(void)
+{
+  return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); 
+}
+
+/**
+  * @brief  Clears the ETHERNET transmit FIFO.
+  * @param  None                
+  * @retval None
+  */
+void ETH_FlushTransmitFIFO(void)
+{
+  /* Set the Flush Transmit FIFO bit */
+  ETH->DMAOMR |= ETH_DMAOMR_FTF;  
+}
+
+/**
+  * @brief  Checks whether the ETHERNET transmit FIFO bit is cleared or not.
+  * @param  None                
+  * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
+  */
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{   
+  FlagStatus bitstatus = RESET;
+  if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus; 
+}
+
+/**
+  * @brief  Enables or disables the DMA transmission.
+  * @param  NewState: new state of the DMA transmission.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMATransmissionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transmission */
+    ETH->DMAOMR |= ETH_DMAOMR_ST;  
+  }
+  else
+  {
+    /* Disable the DMA transmission */
+    ETH->DMAOMR &= ~ETH_DMAOMR_ST;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DMA reception.
+  * @param  NewState: new state of the DMA reception.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMAReceptionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA reception */
+    ETH->DMAOMR |= ETH_DMAOMR_SR;  
+  }
+  else
+  {
+    /* Disable the DMA reception */
+    ETH->DMAOMR &= ~ETH_DMAOMR_SR;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET DMA interrupts.
+  * @param  ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
+  *   enabled or disabled.
+  *   This parameter can be any combination of the following values:
+  *     @arg ETH_DMA_IT_NIS : Normal interrupt summary 
+  *     @arg ETH_DMA_IT_AIS : Abnormal interrupt summary  
+  *     @arg ETH_DMA_IT_ER  : Early receive interrupt 
+  *     @arg ETH_DMA_IT_FBE : Fatal bus error interrupt 
+  *     @arg ETH_DMA_IT_ET  : Early transmit interrupt 
+  *     @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt 
+  *     @arg ETH_DMA_IT_RPS : Receive process stopped interrupt 
+  *     @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_R   : Receive interrupt 
+  *     @arg ETH_DMA_IT_TU  : Underflow interrupt 
+  *     @arg ETH_DMA_IT_RO  : Overflow interrupt 
+  *     @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt 
+  *     @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt 
+  *     @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt 
+  *     @arg ETH_DMA_IT_T   : Transmit interrupt
+  * @param  NewState: new state of the specified ETHERNET DMA interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ETHERNET DMA interrupts */
+    ETH->DMAIER |= ETH_DMA_IT;
+  }
+  else
+  {
+    /* Disable the selected ETHERNET DMA interrupts */
+    ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
+  * @param  ETH_DMA_Overflow: specifies the DMA overflow flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
+  *     @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
+  * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).
+  */
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
+  
+  if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
+  * @param  None
+  * @retval The value of Rx overflow Missed Frame Counter.
+  */
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
+{
+  return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
+  * @param  None
+  * @retval The value of Buffer unavailable Missed Frame Counter.
+  */
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+  return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHTDR register value.
+  * @param  None
+  * @retval The value of the current Tx desc start address.
+  */
+uint32_t ETH_GetCurrentTxDescStartAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHTDR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHRDR register value.
+  * @param  None
+  * @retval The value of the current Rx desc start address.
+  */
+uint32_t ETH_GetCurrentRxDescStartAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHRDR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHTBAR register value.
+  * @param  None
+  * @retval The value of the current Tx buffer address.
+  */
+uint32_t ETH_GetCurrentTxBufferAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHTBAR));
+}
+
+/**
+  * @brief  Get the ETHERNET DMA DMACHRBAR register value.
+  * @param  None
+  * @retval The value of the current Rx buffer address.
+  */
+uint32_t ETH_GetCurrentRxBufferAddress(void)
+{
+  return ((uint32_t)(ETH->DMACHRBAR));
+}
+
+/**
+  * @brief  Resumes the DMA Transmission by writing to the DmaTxPollDemand register
+  *   (the data written could be anything). This forces  the DMA to resume transmission.
+  * @param  None
+  * @retval None.
+  */
+void ETH_ResumeDMATransmission(void)
+{
+  ETH->DMATPDR = 0;
+}
+
+/**
+  * @brief  Resumes the DMA Transmission by writing to the DmaRxPollDemand register
+  *   (the data written could be anything). This forces the DMA to resume reception.
+  * @param  None
+  * @retval None.
+  */
+void ETH_ResumeDMAReception(void)
+{
+  ETH->DMARPDR = 0;
+}
+
+/**
+  * @brief  Set the DMA Receive status watchdog timer register value
+  * @param  Value: DMA Receive status watchdog timer register value   
+  * @retval None
+  */
+void ETH_SetReceiveWatchdogTimer(uint8_t Value)
+{
+  /* Set the DMA Receive status watchdog timer register */
+  ETH->DMARSWTR = Value;
+}
+
+/*---------------------------------  PMT  ------------------------------------*/
+/**
+  * @brief  Reset Wakeup frame filter register pointer.
+  * @param  None
+  * @retval None
+  */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{  
+  /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
+  ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;  
+}
+
+/**
+  * @brief  Populates the remote wakeup frame registers.
+  * @param  Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
+  * @retval None
+  */
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
+{
+  uint32_t i = 0;
+  
+  /* Fill Remote Wake-up Frame Filter register with Buffer data */
+  for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)
+  {
+    /* Write each time to the same register */ 
+    ETH->MACRWUFFR = Buffer[i];
+  }
+}
+
+/**
+  * @brief  Enables or disables any unicast packet filtered by the MAC address
+  *   recognition to be a wake-up frame.
+  * @param  NewState: new state of the MAC Global Unicast Wake-Up.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Global Unicast Wake-Up */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;  
+  }
+  else
+  {
+    /* Disable the MAC Global Unicast Wake-Up */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
+  * @param  ETH_PMT_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset 
+  *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received 
+  *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
+  * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+  */
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
+  
+  if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the MAC Wake-Up Frame Detection.
+  * @param  NewState: new state of the MAC Wake-Up Frame Detection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Wake-Up Frame Detection */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;  
+  }
+  else
+  {
+    /* Disable the MAC Wake-Up Frame Detection */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC Magic Packet Detection.
+  * @param  NewState: new state of the MAC Magic Packet Detection.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Magic Packet Detection */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;  
+  }
+  else
+  {
+    /* Disable the MAC Magic Packet Detection */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MAC Power Down.
+  * @param  NewState: new state of the MAC Power Down.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_PowerDownCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MAC Power Down */
+    /* This puts the MAC in power down mode */
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;  
+  }
+  else
+  {
+    /* Disable the MAC Power Down */ 
+    ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
+  }
+}
+
+/*---------------------------------  MMC  ------------------------------------*/
+/**
+  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)   
+  * @param  None
+  * @retval None
+  */
+void ETH_MMCCounterFullPreset(void)
+{
+  /* Preset and Initialize the MMC counters to almost-full value */
+  ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
+}
+
+/**
+  * @brief  Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16). 
+  * @param  None
+  * @retval None
+  */
+void ETH_MMCCounterHalfPreset(void)
+{
+  /* Preset the MMC counters to almost-full value */
+  ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
+  /* Initialize the MMC counters to almost-half value */
+  ETH->MMCCR |= ETH_MMCCR_MCP;
+}
+
+/**
+  * @brief  Enables or disables the MMC Counter Freeze.
+  * @param  NewState: new state of the MMC Counter Freeze.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter Freeze */
+    ETH->MMCCR |= ETH_MMCCR_MCF;
+  }
+  else
+  {
+    /* Disable the MMC Counter Freeze */
+    ETH->MMCCR &= ~ETH_MMCCR_MCF;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MMC Reset On Read.
+  * @param  NewState: new state of the MMC Reset On Read.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the MMC Counter reset on read */
+    ETH->MMCCR |= ETH_MMCCR_ROR; 
+  }
+  else
+  {
+    /* Disable the MMC Counter reset on read */
+    ETH->MMCCR &= ~ETH_MMCCR_ROR;
+  }
+}
+
+/**
+  * @brief  Enables or disables the MMC Counter Stop Rollover.
+  * @param  NewState: new state of the MMC Counter Stop Rollover.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Disable the MMC Counter Stop Rollover  */
+    ETH->MMCCR &= ~ETH_MMCCR_CSR;
+  }
+  else
+  {
+    /* Enable the MMC Counter Stop Rollover */
+    ETH->MMCCR |= ETH_MMCCR_CSR; 
+  }
+}
+
+/**
+  * @brief  Resets the MMC Counters.
+  * @param  None
+  * @retval None
+  */
+void ETH_MMCCountersReset(void)
+{
+  /* Resets the MMC Counters */
+  ETH->MMCCR |= ETH_MMCCR_CR; 
+}
+
+/**
+  * @brief  Enables or disables the specified ETHERNET MMC interrupts.
+  * @param  ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+  *   This parameter can be any combination of Tx interrupt or 
+  *   any combination of Rx interrupt (but not both)of the following values: 
+  *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value  
+  *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
+  * @param  NewState: new state of the specified ETHERNET MMC interrupts.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+  {
+    /* Remove register mak from IT */
+    ETH_MMC_IT &= 0xEFFFFFFF;
+  
+    /* ETHERNET MMC Rx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH->MMCRIMR |= ETH_MMC_IT;    
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected ETHERNET MMC interrupts */
+      ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
+    }
+    else
+    {
+      /* Disable the selected ETHERNET MMC interrupts */
+      ETH->MMCTIMR |= ETH_MMC_IT;    
+    }  
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET MMC IT is set or not.
+  * @param  ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value  
+  *     @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value 
+  *     @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value 
+  * @retval The value of ETHERNET MMC IT (SET or RESET).
+  */
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); 
+  
+  if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+  {
+    /* ETHERNET MMC Rx interrupts selected */
+    /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ 
+    if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }
+  }
+  else
+  {
+    /* ETHERNET MMC Tx interrupts selected */
+    /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */  
+    if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCTIMR & ETH_MMC_IT) == (uint32_t)RESET))
+    {
+      bitstatus = SET;
+    }
+    else
+    {
+      bitstatus = RESET;
+    }  
+  }    
+    
+  return bitstatus;
+}
+
+/**
+  * @brief  Get the specified ETHERNET MMC register value.
+  * @param  ETH_MMCReg: specifies the ETHERNET MMC register.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_MMCCR      : MMC CR register 
+  *     @arg ETH_MMCRIR     : MMC RIR register 
+  *     @arg ETH_MMCTIR     : MMC TIR register 
+  *     @arg ETH_MMCRIMR    : MMC RIMR register 
+  *     @arg ETH_MMCTIMR    : MMC TIMR register 
+  *     @arg ETH_MMCTGFSCCR : MMC TGFSCCR register 
+  *     @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register  
+  *     @arg ETH_MMCTGFCR   : MMC TGFCR register
+  *     @arg ETH_MMCRFCECR  : MMC RFCECR register 
+  *     @arg ETH_MMCRFAECR  : MMC RFAECR register 
+  *     @arg ETH_MMCRGUFCR  : MMC RGUFCRregister 
+  * @retval The value of ETHERNET MMC Register value.
+  */
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
+  
+  /* Return the selected register value */
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
+}
+/*---------------------------------  PTP  ------------------------------------*/
+/**
+  * @brief  Sets the PTP node clock type.
+  * @param  ClockType: specifies the PTP node clock type.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_OrdinaryClock : Ordinary Clock. 
+  *     @arg ETH_PTP_BoundaryClock : Boundary Clock.
+  *     @arg ETH_PTP_EndToEndTransparentClock : End To End Transparent Clock. 
+  *     @arg ETH_PTP_PeerToPeerTransparentClock : Peer To Peer Transparent Clock.  
+  * @retval None
+  */
+void ETH_PTPNodeClockTypeConfig(uint32_t ClockType)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_TYPE_CLOCK(ClockType));  
+
+  /* Clear the PTP node clock type */
+  ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSCNT); 
+  
+  /* Set the new PTP node clock type */
+  ETH->PTPTSCR |= ClockType;   
+}
+
+/**
+  * @brief  Enables or disables the selected PTP snapshot method.
+  * @param  SnapshotMethod: specifies the PTP snapshot method.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_SnapshotMasterMessage  : snapshot for message relevant to master. 
+  *     @arg ETH_PTP_SnapshotEventMessage   : snapshot for event message.
+  *     @arg ETH_PTP_SnapshotIPV4Frames     : snapshot for IPv4 frames. 
+  *     @arg ETH_PTP_SnapshotIPV6Frames     : snapshot for IPv6 frames.
+  *     @arg ETH_PTP_SnapshotPTPOverEthernetFrames : snapshot for PTP over ethernet frames. 
+  *     @arg ETH_PTP_SnapshotAllReceivedFrames      : snapshot for all received frames. 
+  * @param  NewState: new state of the PTP snapshot method
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_PTPSnapshotCmd(uint32_t SnapshotMethod, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_SNAPSHOT(SnapshotMethod));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));   
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected PTP snapshot method */
+    ETH->PTPTSCR |= SnapshotMethod;
+  }
+  else
+  {
+    /* Disable the selected PTP snapshot method */
+    ETH->PTPTSCR &= (~(uint32_t)SnapshotMethod);
+  }
+}
+
+/**
+  * @brief  Enables or disables the PTP packet snooping version 2 format.
+  * @param  NewState: new state of the PTP packet snooping version 2 format
+  *   This parameter can be: ENABLE or DISABLE. 
+  * @retval None
+  */
+void ETH_PTPPacketSnoopingV2FormatCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PTP packet snooping version 2 format */
+    ETH->PTPTSCR |= ETH_PTPTSSR_TSPTPPSV2E;
+  }
+  else
+  {
+    /* Disable the PTP packet snooping version 2 format */
+    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSSR_TSPTPPSV2E);
+  }
+}
+
+/**
+  * @brief  Enables or disables the PTP Subsecond rollover.
+  * @param  NewState: new state of the PTP Subsecond rollover
+  *   This parameter can be: ENABLE or DISABLE. 
+  * @retval None
+  */
+void ETH_PTPSubSecondRolloverCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PTP Subsecond rollover */
+    ETH->PTPTSCR |= ETH_PTPTSSR_TSSSR;
+  }
+  else
+  {
+    /* Disable the PTP Subsecond rollover */
+    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSSR_TSSSR);
+  }
+}
+
+/**
+  * @brief  Updated the PTP block for fine correction with the Time Stamp Addend register value.
+  * @param  None
+  * @retval None
+  */
+void ETH_EnablePTPTimeStampAddend(void)
+{
+  /* Enable the PTP block update with the Time Stamp Addend register value */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;    
+}
+
+/**
+  * @brief  Enable the PTP Time Stamp interrupt trigger
+  * @param  None
+  * @retval None
+  */
+void ETH_EnablePTPTimeStampInterruptTrigger(void)
+{
+  /* Enable the PTP target time interrupt */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;    
+}
+
+/**
+  * @brief  Updated the PTP system time with the Time Stamp Update register value.
+  * @param  None
+  * @retval None
+  */
+void ETH_EnablePTPTimeStampUpdate(void)
+{
+  /* Enable the PTP system time update with the Time Stamp Update register value */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;    
+}
+
+/**
+  * @brief  Initialize the PTP Time Stamp
+  * @param  None
+  * @retval None
+  */
+void ETH_InitializePTPTimeStamp(void)
+{
+  /* Initialize the PTP Time Stamp */
+  ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;    
+}
+
+/**
+  * @brief  Selects the PTP Update method
+  * @param  UpdateMethod: the PTP Update method
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_FineUpdate   : Fine Update method 
+  *     @arg ETH_PTP_CoarseUpdate : Coarse Update method 
+  * @retval None
+  */
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
+  
+  if (UpdateMethod != ETH_PTP_CoarseUpdate)
+  {
+    /* Enable the PTP Fine Update method */
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
+  }
+  else
+  {
+    /* Disable the PTP Coarse Update method */
+    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
+  } 
+}
+
+/**
+  * @brief  Enables or disables the PTP time stamp for transmit and receive frames.
+  * @param  NewState: new state of the PTP time stamp for transmit and receive frames
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ETH_PTPTimeStampCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PTP time stamp for transmit and receive frames */
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
+  }
+  else
+  {
+    /* Disable the PTP time stamp for transmit and receive frames */
+    ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ETHERNET PTP flag is set or not.
+  * @param  ETH_PTP_FLAG: specifies the flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_FLAG_TSARU : Addend Register Update 
+  *     @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable 
+  *     @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update 
+  *     @arg ETH_PTP_FLAG_TSSTI  : Time Stamp Initialize                       
+  * @retval The new state of ETHERNET PTP Flag (SET or RESET).
+  */
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
+{
+  uint32_t flagpos = 0x0;
+  FlagStatus bitstatus = RESET;
+  uint32_t ethernetreg = 0x0;
+
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
+
+  /* Get the Flag position */
+  flagpos &= 0xEFFFFFFF;
+
+  /* Get the Ethernet register index */
+  ethernetreg = (((uint32_t)ETH_PTP_FLAG) & 0x10000000);
+
+  if (ethernetreg != (uint32_t)RESET) /* The flag is in PTPTSCR register */
+  {
+    flagpos &= ETH->PTPTSCR;
+  }
+  else /* The IT  is in PTPTSSR register */
+  {
+    flagpos &= ETH->PTPTSSR;
+  }
+     
+  if (flagpos != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets the system time Sub-Second Increment value.
+  * @param  SubSecondValue: specifies the PTP Sub-Second Increment Register value.
+  * @retval None
+  */
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
+  /* Set the PTP Sub-Second Increment Register */
+  ETH->PTPSSIR = SubSecondValue;    
+}
+
+/**
+  * @brief  Sets the Time Stamp update sign and values.
+  * @param  Sign: specifies the PTP Time update value sign.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTP_PositiveTime : positive time value. 
+  *     @arg ETH_PTP_NegativeTime : negative time value.  
+  * @param  SecondValue: specifies the PTP Time update second value. 
+  * @param  SubSecondValue: specifies the PTP Time update sub-second value.
+  *   This parameter is a 31 bit value, bit32 correspond to the sign.
+  * @retval None
+  */
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_TIME_SIGN(Sign));  
+  assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); 
+  /* Set the PTP Time Update High Register */
+  ETH->PTPTSHUR = SecondValue;
+  
+  /* Set the PTP Time Update Low Register with sign */
+  ETH->PTPTSLUR = Sign | SubSecondValue;   
+}
+
+/**
+  * @brief  Sets the Time Stamp Addend value.
+  * @param  Value: specifies the PTP Time Stamp Addend Register value.
+  * @retval None
+  */
+void ETH_SetPTPTimeStampAddend(uint32_t Value)
+{
+  /* Set the PTP Time Stamp Addend Register */
+  ETH->PTPTSAR = Value;    
+}
+
+/**
+  * @brief  Sets the Target Time registers values.
+  * @param  HighValue: specifies the PTP Target Time High Register value.
+  * @param  LowValue: specifies the PTP Target Time Low Register value.
+  * @retval None
+  */
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
+{
+  /* Set the PTP Target Time High Register */
+  ETH->PTPTTHR = HighValue;
+  /* Set the PTP Target Time Low Register */
+  ETH->PTPTTLR = LowValue;    
+}
+
+/**
+  * @brief  Get the specified ETHERNET PTP register value.
+  * @param  ETH_PTPReg: specifies the ETHERNET PTP register.
+  *   This parameter can be one of the following values:
+  *     @arg ETH_PTPTSCR  : Sub-Second Increment Register 
+  *     @arg ETH_PTPSSIR  : Sub-Second Increment Register 
+  *     @arg ETH_PTPTSHR  : Time Stamp High Register
+  *     @arg ETH_PTPTSLR  : Time Stamp Low Register 
+  *     @arg ETH_PTPTSHUR : Time Stamp High Update Register  
+  *     @arg ETH_PTPTSLUR : Time Stamp Low Update Register
+  *     @arg ETH_PTPTSAR  : Time Stamp Addend Register
+  *     @arg ETH_PTPTTHR  : Target Time High Register 
+  *     @arg ETH_PTPTTLR  : Target Time Low Register 
+  * @retval The value of ETHERNET PTP Register value.
+  */
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
+{
+  /* Check the parameters */
+  assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
+  
+  /* Return the selected register value */
+  return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
+}
+
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+/**
+  * @brief  Initializes the DMA Tx descriptors in chain mode with PTP.
+  * @param  DMAPTPTxDescTab: Pointer on the first Tx desc list 
+  * @param  TxBuff: Pointer on the first TxBuffer list
+  * @param  TxBuffCount: Number of the used Tx desc in the list
+  * @retval None
+  */
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMAPTPTxDesc;
+  
+  /* Set the DMAPTPTxDescToSet pointer with the first one of the DMAPTPTxDescTab list */
+  DMAPTPTxDescToSet = DMAPTPTxDescTab;
+
+  /* Fill each DMAPTPTxDesc descriptor with the right values */   
+  for(i=0; i < TxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Tx Desc list */
+    DMAPTPTxDesc = DMAPTPTxDescTab + i;
+
+    /* Set Second Address Chained bit */
+    DMAPTPTxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;  
+       
+    /* Set Buffer1 address pointer */
+    DMAPTPTxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (TxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMAPTPTxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPTxDescTab+i+1);
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMAPTPTxDesc->Buffer2NextDescAddr = (uint32_t) DMAPTPTxDescTab;  
+    }
+  }
+   
+  /* Set Transmit Desciptor List Address Register */
+  ETH->DMATDLAR = (uint32_t) DMAPTPTxDescTab;	
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  * @param  DMAPTPRxDescTab: Pointer on the first Rx desc list
+  * @param  RxBuff: Pointer on the first RxBuffer list
+  * @param  RxBuffCount: Number of the used Rx desc in the list
+  * @retval None
+  */
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+  uint32_t i = 0;
+  ETH_DMADESCTypeDef *DMAPTPRxDesc;
+  
+  /* Set the DMAPTPRxDescToGet pointer with the first one of the DMAPTPRxDescTab list */
+  DMAPTPRxDescToGet = DMAPTPRxDescTab; 
+
+  /* Fill each DMAPTPRxDesc descriptor with the right values */
+  for(i=0; i < RxBuffCount; i++)
+  {
+    /* Get the pointer on the ith member of the Rx Desc list */
+    DMAPTPRxDesc = DMAPTPRxDescTab+i;
+
+    /* Set Own bit of the Rx descriptor Status */
+    DMAPTPRxDesc->Status = ETH_DMARxDesc_OWN;
+	
+    /* Set Buffer1 size and Second Address Chained bit */
+    DMAPTPRxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; 	 
+
+    /* Set Buffer1 address pointer */
+    DMAPTPRxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+    
+    /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+    if(i < (RxBuffCount-1))
+    {
+      /* Set next descriptor address register with next descriptor base address */
+      DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab+i+1); 
+    }
+    else
+    {
+      /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ 
+      DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab); 
+    }
+  }
+   
+  /* Set Receive Desciptor List Address Register */
+  ETH->DMARDLAR = (uint32_t) DMAPTPRxDescTab;  
+}
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+
+/**
+  * @brief  Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.
+  * @param  ppkt: pointer to application packet buffer to transmit.
+  * @param  FrameLength: Tx Packet size.
+  * @param  PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
+  * @retval ETH_ERROR: in case of Tx desc owned by DMA
+  *         ETH_SUCCESS: for correct transmission
+  */
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
+{ 
+  uint32_t offset = 0, timeout = 0;
+    
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return ERROR: OWN bit set */
+    return ETH_ERROR;
+  }
+  
+  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      
+  for(offset=0; offset<FrameLength; offset++)       
+  {
+    (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+  }
+        
+  /* Setting the Frame Length: bits[12:0] */
+  DMAPTPTxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+
+  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    
+  DMAPTPTxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+
+  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMAPTPTxDescToSet->Status |= ETH_DMATxDesc_OWN;
+
+  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+  {
+    /* Clear TBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_TBUS;
+    /* Resume DMA transmission*/
+    ETH->DMATPDR = 0;
+  }
+
+  /* Wait for ETH_DMATxDesc_TTSS flag to be set */
+  do
+  {
+    timeout++;
+  } while (!(DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+
+  /* Return ERROR in case of timeout */
+  if(timeout == PHY_READ_TO)
+  {
+    return ETH_ERROR;
+  }
+
+  /* Clear the DMATxDescToSet status register TTSS flag */
+  DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
+  
+  *PTPTxTab++ = DMAPTPTxDescToSet->TimeStampLow;
+  *PTPTxTab = DMAPTPTxDescToSet->TimeStampHigh;
+     
+  /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */  
+  /* Chained Mode */
+  if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+  {     
+    /* Selects the next DMA Tx descriptor list for next buffer to send */ 
+    DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);    
+  }
+  else /* Ring Mode */
+  {  
+    if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);      
+    }
+    else
+    {  
+      /* Selects the next DMA Tx descriptor list for next buffer to send */
+      DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
+    }
+  }
+
+  /* Return SUCCESS */
+  return ETH_SUCCESS;   
+}
+
+/**
+  * @brief  Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.
+  * @param  ppkt: pointer to application packet receive buffer.  
+  * @param  PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
+  * @retval ETH_ERROR: if there is error in reception
+  *         framelength: received packet size if packet reception is correct
+  */
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
+{ 
+  uint32_t offset = 0, framelength = 0;
+
+  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+  if((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+  {
+    /* Return error: OWN bit set */
+    return ETH_ERROR; 
+  }
+  
+  if(((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && 
+     ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&  
+     ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))  
+  {      
+    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+    framelength = ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;	    
+
+    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */	 
+    for(offset=0; offset<framelength; offset++)       
+    {
+      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
+    }	
+  }
+  else
+  {
+    /* Return ERROR */
+    framelength = ETH_ERROR;
+  }
+
+  *PTPRxTab++ = DMAPTPRxDescToGet->TimeStampLow;
+  *PTPRxTab = DMAPTPRxDescToGet->TimeStampHigh;
+    
+  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+  DMAPTPRxDescToGet->Status = ETH_DMARxDesc_OWN; 
+ 
+  /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)  
+  {
+    /* Clear RBUS ETHERNET DMA flag */
+    ETH->DMASR = ETH_DMASR_RBUS;
+    /* Resume DMA reception */
+    ETH->DMARPDR = 0;
+  }
+  
+  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */      
+  /* Chained Mode */
+  if((DMAPTPRxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+  {     
+    /* Selects the next DMA Rx descriptor list for next buffer to read */ 
+    DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);    
+  }
+  else /* Ring Mode */
+  {   
+    if((DMAPTPRxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+    {
+      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);      
+    }
+    else
+    { 
+      /* Selects the next DMA Rx descriptor list for next buffer to read */
+      DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPRxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      
+    }
+  }
+  
+  /* Return Frame Length/ERROR */
+  return (framelength);  
+}
+
+#ifndef USE_Delay
+/**
+  * @brief  Inserts a delay time.
+  * @param  nCount: specifies the delay time length.
+  * @retval None
+  */
+static void ETH_Delay(__IO uint32_t nCount)
+{
+  __IO uint32_t index = 0; 
+  for(index = nCount; index != 0; index--)
+  {
+  }
+}
+#endif /* USE_Delay*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
+/*
+ * STM32 Eth Driver for RT-Thread
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-10-05     Bernard      eth interface driver for STM32F107 CL
+ */
+#include <rtthread.h>
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+
+#define STM32_ETH_DEBUG		0
+
+#define MII_MODE          /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */
+
+#define DP83848_PHY        	/* Ethernet pins mapped on STM3210C-EVAL Board */
+#define PHY_ADDRESS       	0x01 /* Relative to STM3210C-EVAL Board */
+
+#define ETH_RXBUFNB        	4
+#define ETH_TXBUFNB        	2
+static ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
+static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
+
+#define MAX_ADDR_LEN 6
+struct rt_stm32_eth
+{
+	/* inherit from ethernet device */
+	struct eth_device parent;
+
+	/* interface address info. */
+	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+};
+static struct rt_stm32_eth stm32_eth_device;
+static struct rt_semaphore tx_wait;
+static rt_bool_t tx_is_waiting = RT_FALSE;
+
+/* interrupt service routine */
+void ETH_IRQHandler(void)
+{
+	rt_uint32_t status;
+
+	status = ETH->DMASR;
+
+    rt_kprintf("ETH ISR\n");
+	
+	/* Clear received IT */
+	if ((status & ETH_DMA_IT_NIS) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_NIS;
+	if ((status & ETH_DMA_IT_AIS) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_AIS;
+	if ((status & ETH_DMA_IT_RO) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_RO;
+	if ((status & ETH_DMA_IT_RBU) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_RBU;
+
+	if (ETH_GetDMAITStatus(ETH_DMA_IT_R) == SET) /* packet receiption */
+	{
+		rt_err_t result;
+
+		/* a frame has been received */
+		result = eth_device_ready(&(stm32_eth_device.parent));
+		RT_ASSERT(result == RT_EOK);
+
+		ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
+	}
+
+	if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
+	{
+		if (tx_is_waiting == RT_TRUE)
+		{
+			tx_is_waiting = RT_FALSE;
+			rt_sem_release(&tx_wait);
+		}
+
+		ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
+	}
+}
+
+/* RT-Thread Device Interface */
+/* initialize the interface */
+static rt_err_t rt_stm32_eth_init(rt_device_t dev)
+{
+  ETH_InitTypeDef ETH_InitStructure;
+
+  /* Reset ETHERNET on AHB Bus */
+  ETH_DeInit();
+
+  /* Software reset */
+  ETH_SoftwareReset();
+
+  /* Wait for software reset */
+  while (ETH_GetSoftwareResetStatus() == SET);
+
+  /* ETHERNET Configuration ------------------------------------------------------*/
+  /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
+  ETH_StructInit(&ETH_InitStructure);
+
+  /* Fill ETH_InitStructure parametrs */
+  /*------------------------   MAC   -----------------------------------*/
+  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;
+
+  ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+  ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
+  ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+  ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
+  ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
+  ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+  ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+  ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+#ifdef CHECKSUM_BY_HARDWARE
+  ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
+#endif
+
+  /*------------------------   DMA   -----------------------------------*/  
+  
+  /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: 
+  the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, 
+  if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
+  ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; 
+  ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;         
+  ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
+ 
+  ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
+  ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;   
+  ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
+  ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;      
+  ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;                
+  ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;          
+  ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
+  ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
+
+  /* Configure Ethernet */
+  ETH_Init(&ETH_InitStructure, DP83848_PHY_ADDRESS);
+
+  /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
+  ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
+
+  /* Initialize Tx Descriptors list: Chain Mode */
+  ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
+  /* Initialize Rx Descriptors list: Chain Mode  */
+  ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
+
+  /* MAC address configuration */
+  ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
+
+  /* Enable MAC and DMA transmission and reception */
+  ETH_Start();
+
+  return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_set_errno(-RT_ENOSYS);
+	return 0;
+}
+
+static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	switch(cmd)
+	{
+	case NIOCTL_GADDR:
+		/* get mac address */
+		if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+		else return -RT_ERROR;
+		break;
+
+	default :
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit packet. */
+rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
+{
+	struct pbuf* q;
+	rt_uint32_t offset;
+
+	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+	while ((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+	{
+		rt_err_t result;
+		rt_uint32_t level;
+
+		level = rt_hw_interrupt_disable();
+		tx_is_waiting = RT_TRUE;
+		rt_hw_interrupt_enable(level);
+
+		/* it's own bit set, wait it */
+		result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER);
+		if (result == RT_EOK) break;
+		if (result == -RT_ERROR) return -RT_ERROR;
+	}
+
+	offset = 0;
+	for (q = p; q != NULL; q = q->next)
+	{
+		rt_uint8_t* ptr;
+		rt_uint32_t len;
+
+		len = q->len;
+		ptr = q->payload;
+
+		/* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+		while (len)
+		{
+			(*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = *ptr;
+
+			offset ++; ptr ++; len --;
+		}
+	}
+
+	/* Setting the Frame Length: bits[12:0] */
+	DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1);
+	/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+	DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+	/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+	DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+	/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+	if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+	{
+		/* Clear TBUS ETHERNET DMA flag */
+		ETH->DMASR = ETH_DMASR_TBUS;
+		/* Transmit Poll Demand to resume DMA transmission*/
+		ETH->DMATPDR = 0;
+	}
+
+	/* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
+	/* Chained Mode */
+	if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+	{
+		/* Selects the next DMA Tx descriptor list for next buffer to send */
+		DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
+	}
+	else /* Ring Mode */
+	{
+		if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+		{
+			/* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+			DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+		}
+		else
+		{
+			/* Selects the next DMA Tx descriptor list for next buffer to send */
+			DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+		}
+	}
+
+	/* Return SUCCESS */
+	return RT_EOK;
+}
+
+/* reception packet. */
+struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
+{
+	struct pbuf* p;
+	rt_uint32_t offset = 0, framelength = 0;
+
+	/* init p pointer */
+	p = RT_NULL;
+
+	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+	if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET))
+		return p;
+
+	if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+		((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+		((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+	{
+		/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+		framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+
+		/* allocate buffer */
+		p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM);
+		if (p != RT_NULL)
+		{
+			rt_uint8_t* ptr;
+			struct pbuf* q;
+			rt_size_t len;
+
+			for (q = p; q != RT_NULL; q= q->next)
+			{
+				ptr = q->payload;
+				len = q->len;
+
+				/* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+				while (len)
+				{
+					*ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+
+					offset ++; ptr ++; len --;
+				}
+			}
+		}
+	}
+
+	/* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+	DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+	/* When Rx Buffer unavailable flag is set: clear it and resume reception */
+	if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+	{
+		/* Clear RBUS ETHERNET DMA flag */
+		ETH->DMASR = ETH_DMASR_RBUS;
+		/* Resume DMA reception */
+		ETH->DMARPDR = 0;
+	}
+
+	/* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+	/* Chained Mode */
+	if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+	{
+		/* Selects the next DMA Rx descriptor list for next buffer to read */
+		DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+	}
+	else /* Ring Mode */
+	{
+		if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+		{
+			/* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+			DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+		}
+		else
+		{
+			/* Selects the next DMA Rx descriptor list for next buffer to read */
+			DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+		}
+	}
+
+	return p;
+}
+
+static void RCC_Configuration(void)
+{
+	/* Enable GPIOs clocks */
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
+						 RCC_AHB1Periph_GPIOC, ENABLE);
+
+	/* Enable SYSCFG and ADC3 clocks */
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG | RCC_APB2Periph_ADC3, ENABLE);
+
+	/* Enable MAC clocks */
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
+						RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);	
+}
+
+static void NVIC_Configuration(void)
+{
+  NVIC_InitTypeDef NVIC_InitStructure;
+
+  /* Enable the Ethernet global Interrupt */
+  NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);    
+}
+
+/*
+ * GPIO Configuration for ETH
+ */
+static void GPIO_Configuration(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Configure PA1, PA2 and PA7 */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
+
+  /* Configure PB5 and PB8 */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_ETH);	
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);
+
+  /* Configure PC1, PC2, PC3, PC4 and PC5 */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
+                                  
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
+  GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
+
+  /* for RMII mode you have to set the system clock frequency to 100MHz,
+     you can do this in system_stm32f2xx.c file */
+
+  /* Configure MCO (PA8) */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  /* Output PLL clock divided by 2 (50MHz) on MCO pin (PA8) to clock the PHY */
+  RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_2);
+
+  SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
+}
+
+void rt_hw_stm32_eth_init(void)
+{
+	RCC_Configuration();
+	GPIO_Configuration();
+	NVIC_Configuration();
+
+    stm32_eth_device.dev_addr[0] = 0x00;
+    stm32_eth_device.dev_addr[1] = 0x60;
+    stm32_eth_device.dev_addr[2] = 0x6E;
+    stm32_eth_device.dev_addr[3] = 0x11;
+    stm32_eth_device.dev_addr[4] = 0x22;
+    stm32_eth_device.dev_addr[5] = 0x33;
+
+	stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
+	stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
+	stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
+	stm32_eth_device.parent.parent.read       = rt_stm32_eth_read;
+	stm32_eth_device.parent.parent.write      = rt_stm32_eth_write;
+	stm32_eth_device.parent.parent.control    = rt_stm32_eth_control;
+	stm32_eth_device.parent.parent.user_data  = RT_NULL;
+
+	stm32_eth_device.parent.eth_rx     = rt_stm32_eth_rx;
+	stm32_eth_device.parent.eth_tx     = rt_stm32_eth_tx;
+
+	/* init tx semaphore */
+	rt_sem_init(&tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
+
+	/* register eth device */
+	eth_device_init(&(stm32_eth_device.parent), "e0");
+}

bsp/stm32f20x/stm32f2xx_eth.h

@@ -0,0 +1,1876 @@
+/**
+  ******************************************************************************
+  * @file    stm32f2xx_eth.h
+  * @author  MCD Application Team
+  * @version V0.0.1
+  * @date    10/21/2010
+  * @brief   This file contains all the functions prototypes for the Ethernet
+  *          firmware library.
+  ******************************************************************************
+  * @copy
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F2XX_ETH_H
+#define __STM32F2XX_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f2xx.h"
+
+/* Uncomment this line when using time stamping and/or IPv4 checksum offload */
+#define USE_ENHANCED_DMA_DESCRIPTORS
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ *        (for precise timing), otherwise default _eth_delay_ function defined within
+ *        this driver is used (less precise timing).  
+ */
+/* #define USE_Delay */
+
+#ifdef USE_Delay
+#include "main.h" 
+  #define _eth_delay_    Delay     /*!< User can provide more timing precise _eth_delay_ function */
+#else
+  #define _eth_delay_    ETH_Delay /*!< Default _eth_delay_ function with less precise timing */
+#endif 
+
+/** @addtogroup STM32F2XX_ETH_Driver
+  * @{
+  */
+
+/** @defgroup ETH_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  ETH MAC Init structure definition
+  * @note   The user should not configure all the ETH_InitTypeDef structure's fields. 
+  *   By calling the ETH_StructInit function the structure’s fields are set to their default values.
+  *   Only the parameters that will be set to a non-default value should be configured.  
+  */ 
+typedef struct {
+/** 
+  * @brief / * MAC  
+  */ 
+  uint32_t             ETH_AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
+                                                           The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                           and the mode (half/full-duplex).
+                                                           This parameter can be a value of @ref ETH_AutoNegotiation */
+
+  uint32_t             ETH_Watchdog;                  /*!< Selects or not the Watchdog timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                           When disabled, the MAC can receive up to 16384 bytes.
+                                                           This parameter can be a value of @ref ETH_watchdog */  
+
+  uint32_t             ETH_Jabber;                    /*!< Selects or not Jabber timer
+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                           When disabled, the MAC can send up to 16384 bytes.
+                                                           This parameter can be a value of @ref ETH_Jabber */
+
+  uint32_t             ETH_InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission
+                                                           This parameter can be a value of @ref ETH_Inter_Frame_Gap */   
+
+  uint32_t             ETH_CarrierSense;              /*!< Selects or not the Carrier Sense
+                                                           This parameter can be a value of @ref ETH_Carrier_Sense */
+
+  uint32_t             ETH_Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps
+                                                           This parameter can be a value of @ref ETH_Speed */
+
+  uint32_t             ETH_ReceiveOwn;                /*!< Selects or not the ReceiveOwn
+                                                           ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                           in Half-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Receive_Own */  
+
+  uint32_t             ETH_LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode
+                                                           This parameter can be a value of @ref ETH_Loop_Back_Mode */  
+
+  uint32_t             ETH_Mode;                      /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */  
+
+  uint32_t             ETH_ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                           This parameter can be a value of @ref ETH_Checksum_Offload */    
+
+  uint32_t             ETH_RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                           when a colision occurs (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Retry_Transmission */
+
+  uint32_t             ETH_AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping
+                                                           This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 
+
+  uint32_t             ETH_BackOffLimit;              /*!< Selects the BackOff limit value
+                                                           This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+  uint32_t             ETH_DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Deferral_Check */                                                                                                        
+
+  uint32_t             ETH_ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No fitering)
+                                                           This parameter can be a value of @ref ETH_Receive_All */   
+
+  uint32_t             ETH_SourceAddrFilter;          /*!< Selects the Source Address Filter mode                                                           
+                                                           This parameter can be a value of @ref ETH_Source_Addr_Filter */                  
+
+  uint32_t             ETH_PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)                                                          
+                                                           This parameter can be a value of @ref ETH_Pass_Control_Frames */ 
+
+  uint32_t             ETH_BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames
+                                                           This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+  uint32_t             ETH_DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames
+                                                           This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 
+
+  uint32_t             ETH_PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
+                                                           This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+  uint32_t             ETH_MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                           This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 
+
+  uint32_t             ETH_UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                           This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 
+
+  uint32_t             ETH_HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.  */    
+
+  uint32_t             ETH_HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.  */    
+
+  uint32_t             ETH_PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the
+                                                           transmit control frame */
+
+  uint32_t             ETH_ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
+                                                           This parameter can be a value of @ref ETH_Zero_Quanta_Pause */  
+
+  uint32_t             ETH_PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
+                                                           automatic retransmission of PAUSE Frame
+                                                           This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+                                                           
+  uint32_t             ETH_UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                           unicast address and unique multicast address)
+                                                           This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */  
+
+  uint32_t             ETH_ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
+                                                           disable its transmitter for a specified time (Pause Time)
+                                                           This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+  uint32_t             ETH_TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                           or the MAC back-pressure operation (Half-Duplex mode)
+                                                           This parameter can be a value of @ref ETH_Transmit_Flow_Control */     
+
+  uint32_t             ETH_VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                           comparison and filtering
+                                                           This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 
+
+  uint32_t             ETH_VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
+
+/** 
+  * @brief / * DMA  
+  */ 
+
+  uint32_t             ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
+                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
+
+  uint32_t             ETH_ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode
+                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
+
+  uint32_t             ETH_FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames
+                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
+
+  uint32_t             ETH_TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode
+                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
+
+  uint32_t             ETH_TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control
+                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+  uint32_t             ETH_ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames
+                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+  uint32_t             ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                             and length less than 64 bytes) including pad-bytes and CRC)
+                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+  uint32_t             ETH_ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO
+                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+  uint32_t             ETH_SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                             frame of Transmit data even before obtaining the status for the first frame.
+                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+  uint32_t             ETH_AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats
+                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+  uint32_t             ETH_FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers
+                                                             This parameter can be a value of @ref ETH_Fixed_Burst */
+                       
+  uint32_t             ETH_RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
+
+  uint32_t             ETH_TxDMABurstLength;            /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */                                                   
+
+  uint32_t             ETH_DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */                                                             
+
+  uint32_t             ETH_DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration
+                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
+}ETH_InitTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           DMA descriptors types
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/** 
+  * @brief  ETH DMA Desciptors data structure definition
+  */ 
+typedef struct  {
+  uint32_t   Status;                /*!< Status */
+  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
+  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
+  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
+/* Enhanced ETHERNET DMA PTP Desciptors */
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+  uint32_t   ExtendedStatus;        /* Extended status for PTP receive descriptor */
+  uint32_t   Reserved1;             /* Reserved */
+  uint32_t   TimeStampLow;          /* Time Stamp Low value for transmit and receive */
+  uint32_t   TimeStampHigh;         /* Time Stamp High value for transmit and receive */
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+} ETH_DMADESCTypeDef;
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Constants
+  * @{
+  */ 
+ 
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                          ETH Frames defines
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/** @defgroup ENET_Buffers_setting 
+  * @{
+  */ 
+#define ETH_MAX_PACKET_SIZE    1520    /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               14    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   4    /*!< Ethernet CRC */
+#define ETH_EXTRA                 2    /*!< Extra bytes in some cases */   
+#define VLAN_TAG                  4    /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD          46    /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD        1500    /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    9000    /*!< Jumbo frame payload size */      
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                 Ethernet DMA descriptors registers bits definition
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+@code 
+   DMA Tx Desciptor
+  -----------------------------------------------------------------------------------------------
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Buffer1 Address [31:0]                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 |                   Buffer2 Address [31:0] / Next Desciptor Address [31:0]               |
+  -----------------------------------------------------------------------------------------------
+@endcode
+*/
+
+/** 
+  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
+  */ 
+#define ETH_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATxDesc_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */
+#define ETH_DMATxDesc_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */
+#define ETH_DMATxDesc_FS                      ((uint32_t)0x10000000)  /*!< First Segment */
+#define ETH_DMATxDesc_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */
+#define ETH_DMATxDesc_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */
+#define ETH_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */
+#define ETH_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 
+#define ETH_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 
+#define ETH_DMATxDesc_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */
+#define ETH_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */
+#define ETH_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */
+#define ETH_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */
+#define ETH_DMATxDesc_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATxDesc_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */
+#define ETH_DMATxDesc_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */
+#define ETH_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during tramsmission */
+#define ETH_DMATxDesc_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the tranceiver */
+#define ETH_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATxDesc_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATxDesc_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */
+#define ETH_DMATxDesc_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */
+#define ETH_DMATxDesc_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */
+#define ETH_DMATxDesc_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATxDesc_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */
+
+/** 
+  * @brief  Bit definition of TDES1 register
+  */ 
+#define ETH_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */
+#define ETH_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of TDES2 register
+  */ 
+#define ETH_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of TDES3 register
+  */ 
+#define ETH_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+  /*---------------------------------------------------------------------------------------------
+  TDES6 |                         Transmit Time Stmap Low [31:0]                                 |
+  -----------------------------------------------------------------------------------------------
+  TDES7 |                         Transmit Time Stmap High [31:0]                                |
+  ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES6 register */
+ #define ETH_DMAPTPTxDesc_TTSL  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stmap Low */
+
+/* Bit definition of TDES7 register */
+ #define ETH_DMAPTPTxDesc_TTSH  ((uint32_t)0xFFFFFFFF)  /* Transmit Time Stmap High */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_Rx_descriptor 
+  * @{
+  */
+
+/**
+@code 
+  DMA Rx Desciptor
+  --------------------------------------------------------------------------------------------------------------------
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 |                          Buffer2 Address [31:0] / Next Desciptor Address [31:0]                              |
+  ---------------------------------------------------------------------------------------------------------------------
+@endcode
+*/
+
+/** 
+  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
+  */ 
+#define ETH_DMARxDesc_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARxDesc_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */
+#define ETH_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */
+#define ETH_DMARxDesc_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARxDesc_DE          ((uint32_t)0x00004000)  /*!< Desciptor error: no more descriptors for receive frame  */
+#define ETH_DMARxDesc_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */
+#define ETH_DMARxDesc_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */
+#define ETH_DMARxDesc_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARxDesc_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */
+#define ETH_DMARxDesc_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 
+#define ETH_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    
+#define ETH_DMARxDesc_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */
+#define ETH_DMARxDesc_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */
+#define ETH_DMARxDesc_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARxDesc_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */
+#define ETH_DMARxDesc_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARxDesc_CE          ((uint32_t)0x00000002)  /*!< CRC error */
+#define ETH_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/** 
+  * @brief  Bit definition of RDES1 register
+  */ 
+#define ETH_DMARxDesc_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */
+#define ETH_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */
+#define ETH_DMARxDesc_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */
+#define ETH_DMARxDesc_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */
+#define ETH_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */
+
+/** 
+  * @brief  Bit definition of RDES2 register  
+  */ 
+#define ETH_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */
+
+/** 
+  * @brief  Bit definition of RDES3 register  
+  */ 
+#define ETH_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */
+
+/*---------------------------------------------------------------------------------------------------------------------
+  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES5 |                                            Reserved[31:0]                                                    |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES6 |                                       Receive Time Stmap Low [31:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES7 |                                       Receive Time Stmap High [31:0]                                         |
+  --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES4 register */
+#define ETH_DMAPTPRxDesc_PTPV     ((uint32_t)0x00002000)  /* PTP Version */
+#define ETH_DMAPTPRxDesc_PTPFT    ((uint32_t)0x00001000)  /* PTP Frame Type */
+#define ETH_DMAPTPRxDesc_PTPMT    ((uint32_t)0x00000F00)  /* PTP Message Type */
+  #define ETH_DMAPTPRxDesc_PTPMT_Sync                      ((uint32_t)0x00000100)  /* SYNC message (all clock types) */
+  #define ETH_DMAPTPRxDesc_PTPMT_FollowUp                  ((uint32_t)0x00000200)  /* FollowUp message (all clock types) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_DelayReq                  ((uint32_t)0x00000300)  /* DelayReq message (all clock types) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_DelayResp                 ((uint32_t)0x00000400)  /* DelayResp message (all clock types) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce        ((uint32_t)0x00000500)  /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag          ((uint32_t)0x00000600)  /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */ 
+  #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700)  /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */           
+#define ETH_DMAPTPRxDesc_IPV6PR   ((uint32_t)0x00000080)  /* IPv6 Packet Received */
+#define ETH_DMAPTPRxDesc_IPV4PR   ((uint32_t)0x00000040)  /* IPv4 Packet Received */
+#define ETH_DMAPTPRxDesc_IPCB  ((uint32_t)0x00000020)  /* IP Checksum Bypassed */
+#define ETH_DMAPTPRxDesc_IPPE  ((uint32_t)0x00000010)  /* IP Payload Error */
+#define ETH_DMAPTPRxDesc_IPHE  ((uint32_t)0x00000008)  /* IP Header Error */
+#define ETH_DMAPTPRxDesc_IPPT  ((uint32_t)0x00000007)  /* IP Payload Type */
+  #define ETH_DMAPTPRxDesc_IPPT_UDP                 ((uint32_t)0x00000001)  /* UDP payload encapsulated in the IP datagram */
+  #define ETH_DMAPTPRxDesc_IPPT_TCP                 ((uint32_t)0x00000002)  /* TCP payload encapsulated in the IP datagram */ 
+  #define ETH_DMAPTPRxDesc_IPPT_ICMP                ((uint32_t)0x00000003)  /* ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RDES6 register */
+#define ETH_DMAPTPRxDesc_RTSL  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stmap Low */
+
+/* Bit definition of RDES7 register */
+#define ETH_DMAPTPRxDesc_RTSH  ((uint32_t)0xFFFFFFFF)  /* Receive Time Stmap High */
+
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                     Desciption of common PHY registers
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Read_write_Timeouts 
+  * @{
+  */ 
+#define PHY_READ_TO                     ((uint32_t)0x0004FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0004FFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Reset_Delay 
+  * @{
+  */ 
+#define PHY_ResetDelay                  ((uint32_t)0x000FFFFF) 
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Config_Delay 
+  * @{
+  */ 
+#define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_Register_address 
+  * @{
+  */ 
+#define PHY_BCR                          0          /*!< Tranceiver Basic Control Register */
+#define PHY_BSR                          1          /*!< Tranceiver Basic Status Register */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_basic_Control_register 
+  * @{
+  */ 
+#define PHY_Reset                       ((uint16_t)0x8000)      /*!< PHY Reset */
+#define PHY_Loopback                    ((uint16_t)0x4000)      /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)      /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)      /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)      /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)      /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AutoNegotiation             ((uint16_t)0x1000)      /*!< Enable auto-negotiation function */
+#define PHY_Restart_AutoNegotiation     ((uint16_t)0x0200)      /*!< Restart auto-negotiation function */
+#define PHY_Powerdown                   ((uint16_t)0x0800)      /*!< Select the power down mode */
+#define PHY_Isolate                     ((uint16_t)0x0400)      /*!< Isolate PHY from MII */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_basic_status_register 
+  * @{
+  */ 
+#define PHY_AutoNego_Complete           ((uint16_t)0x0020)      /*!< Auto-Negotioation process completed */
+#define PHY_Linked_Status               ((uint16_t)0x0004)      /*!< Valid link established */
+#define PHY_Jabber_detection            ((uint16_t)0x0002)      /*!< Jabber condition detected */
+
+/**
+  * @}
+  */
+
+/** @defgroup PHY_status_register 
+  * @{
+  */ 
+/* The PHY status register value change from a PHY to another so the user have 
+   to update this value depending on the used external PHY */
+/** 
+  * @brief  For LAN8700  
+  */ 
+/*#define PHY_SR                           31 */        /*!< Tranceiver Status Register */
+
+/** 
+  * @brief  For DP83848  
+  */ 
+#define PHY_SR                           16     /*!< Tranceiver Status Register */
+
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update
+   this value depending on the used external PHY */
+/** 
+  * @brief  For LAN8700  
+  */ 
+/*#define PHY_Speed_Status            ((uint16_t)0x0004)*/      /*!< Configured information of Speed: 10Mbps */
+/*#define PHY_Duplex_Status           ((uint16_t)0x0010)*/      /*!< Configured information of Duplex: Full-duplex */
+
+/** 
+  * @brief  For DP83848  
+  */ 
+#define PHY_Speed_Status            ((uint16_t)0x0002)    /*!< Configured information of Speed: 10Mbps */
+#define PHY_Duplex_Status           ((uint16_t)0x0004)    /*!< Configured information of Duplex: Full-duplex */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
+                             ((REG) == PHY_BSR) || \
+                             ((REG) == PHY_SR))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                                  MAC defines
+  */ 
+/**--------------------------------------------------------------------------**/
+
+/**
+  * @}
+  */ 
+
+/** @defgroup ETH_AutoNegotiation 
+  * @{
+  */ 
+#define ETH_AutoNegotiation_Enable     ((uint32_t)0x00000001)
+#define ETH_AutoNegotiation_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
+                                     ((CMD) == ETH_AutoNegotiation_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_watchdog 
+  * @{
+  */ 
+#define ETH_Watchdog_Enable       ((uint32_t)0x00000000)
+#define ETH_Watchdog_Disable      ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
+                              ((CMD) == ETH_Watchdog_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Jabber 
+  * @{
+  */ 
+#define ETH_Jabber_Enable    ((uint32_t)0x00000000)
+#define ETH_Jabber_Disable   ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
+                            ((CMD) == ETH_Jabber_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Inter_Frame_Gap 
+  * @{
+  */ 
+#define ETH_InterFrameGap_96Bit   ((uint32_t)0x00000000)  /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_InterFrameGap_88Bit   ((uint32_t)0x00020000)  /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_InterFrameGap_80Bit   ((uint32_t)0x00040000)  /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_InterFrameGap_72Bit   ((uint32_t)0x00060000)  /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_InterFrameGap_64Bit   ((uint32_t)0x00080000)  /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_InterFrameGap_56Bit   ((uint32_t)0x000A0000)  /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_InterFrameGap_48Bit   ((uint32_t)0x000C0000)  /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_InterFrameGap_40Bit   ((uint32_t)0x000E0000)  /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_88Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_80Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_72Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_64Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_56Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_48Bit) || \
+                                     ((GAP) == ETH_InterFrameGap_40Bit))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Carrier_Sense 
+  * @{
+  */ 
+#define ETH_CarrierSense_Enable   ((uint32_t)0x00000000)
+#define ETH_CarrierSense_Disable  ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
+                                   ((CMD) == ETH_CarrierSense_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Speed 
+  * @{
+  */ 
+#define ETH_Speed_10M        ((uint32_t)0x00000000)
+#define ETH_Speed_100M       ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
+                             ((SPEED) == ETH_Speed_100M))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Own 
+  * @{
+  */ 
+#define ETH_ReceiveOwn_Enable     ((uint32_t)0x00000000)
+#define ETH_ReceiveOwn_Disable    ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
+                                 ((CMD) == ETH_ReceiveOwn_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Loop_Back_Mode 
+  * @{
+  */ 
+#define ETH_LoopbackMode_Enable        ((uint32_t)0x00001000)
+#define ETH_LoopbackMode_Disable       ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
+                                   ((CMD) == ETH_LoopbackMode_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Duplex_Mode 
+  * @{
+  */ 
+#define ETH_Mode_FullDuplex       ((uint32_t)0x00000800)
+#define ETH_Mode_HalfDuplex       ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
+                                  ((MODE) == ETH_Mode_HalfDuplex))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Checksum_Offload 
+  * @{
+  */ 
+#define ETH_ChecksumOffload_Enable     ((uint32_t)0x00000400)
+#define ETH_ChecksumOffload_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
+                                      ((CMD) == ETH_ChecksumOffload_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Retry_Transmission 
+  * @{
+  */ 
+#define ETH_RetryTransmission_Enable   ((uint32_t)0x00000000)
+#define ETH_RetryTransmission_Disable  ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
+                                        ((CMD) == ETH_RetryTransmission_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip 
+  * @{
+  */ 
+#define ETH_AutomaticPadCRCStrip_Enable     ((uint32_t)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
+                                            ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Back_Off_Limit 
+  * @{
+  */ 
+#define ETH_BackOffLimit_10  ((uint32_t)0x00000000)
+#define ETH_BackOffLimit_8   ((uint32_t)0x00000020)
+#define ETH_BackOffLimit_4   ((uint32_t)0x00000040)
+#define ETH_BackOffLimit_1   ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
+                                     ((LIMIT) == ETH_BackOffLimit_8) || \
+                                     ((LIMIT) == ETH_BackOffLimit_4) || \
+                                     ((LIMIT) == ETH_BackOffLimit_1))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Deferral_Check 
+  * @{
+  */
+#define ETH_DeferralCheck_Enable       ((uint32_t)0x00000010)
+#define ETH_DeferralCheck_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
+                                    ((CMD) == ETH_DeferralCheck_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_All 
+  * @{
+  */ 
+#define ETH_ReceiveAll_Enable     ((uint32_t)0x80000000)
+#define ETH_ReceiveAll_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
+                                 ((CMD) == ETH_ReceiveAll_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Source_Addr_Filter 
+  * @{
+  */ 
+#define ETH_SourceAddrFilter_Normal_Enable       ((uint32_t)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable      ((uint32_t)0x00000300)
+#define ETH_SourceAddrFilter_Disable             ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
+                                        ((CMD) == ETH_SourceAddrFilter_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pass_Control_Frames 
+  * @{
+  */ 
+#define ETH_PassControlFrames_BlockAll                ((uint32_t)0x00000040)  /*!< MAC filters all control frames from reaching the application */
+#define ETH_PassControlFrames_ForwardAll              ((uint32_t)0x00000080)  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /*!< MAC forwards control frames that pass the Address Filter. */ 
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardAll) || \
+                                     ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Broadcast_Frames_Reception 
+  * @{
+  */ 
+#define ETH_BroadcastFramesReception_Enable      ((uint32_t)0x00000000)
+#define ETH_BroadcastFramesReception_Disable     ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
+                                                ((CMD) == ETH_BroadcastFramesReception_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Destination_Addr_Filter 
+  * @{
+  */ 
+#define ETH_DestinationAddrFilter_Normal    ((uint32_t)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse   ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
+                                                ((FILTER) == ETH_DestinationAddrFilter_Inverse))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Promiscuous_Mode 
+  * @{
+  */ 
+#define ETH_PromiscuousMode_Enable     ((uint32_t)0x00000001)
+#define ETH_PromiscuousMode_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
+                                      ((CMD) == ETH_PromiscuousMode_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Multicast_Frames_Filter 
+  * @{
+  */ 
+#define ETH_MulticastFramesFilter_PerfectHashTable    ((uint32_t)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable           ((uint32_t)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect             ((uint32_t)0x00000000)
+#define ETH_MulticastFramesFilter_None                ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
+                                                ((FILTER) == ETH_MulticastFramesFilter_None))
+                                                     
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Frames_Filter 
+  * @{
+  */ 
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable        ((uint32_t)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect          ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
+                                              ((FILTER) == ETH_UnicastFramesFilter_Perfect))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Time 
+  * @{
+  */ 
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Zero_Quanta_Pause 
+  * @{
+  */ 
+#define ETH_ZeroQuantaPause_Enable     ((uint32_t)0x00000000)
+#define ETH_ZeroQuantaPause_Disable    ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZeroQuantaPause_Enable) || \
+                                        ((CMD) == ETH_ZeroQuantaPause_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Low_Threshold 
+  * @{
+  */ 
+#define ETH_PauseLowThreshold_Minus4        ((uint32_t)0x00000000)  /*!< Pause time minus 4 slot times */
+#define ETH_PauseLowThreshold_Minus28       ((uint32_t)0x00000010)  /*!< Pause time minus 28 slot times */
+#define ETH_PauseLowThreshold_Minus144      ((uint32_t)0x00000020)  /*!< Pause time minus 144 slot times */
+#define ETH_PauseLowThreshold_Minus256      ((uint32_t)0x00000030)  /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
+                                               ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect 
+  * @{
+  */ 
+#define ETH_UnicastPauseFrameDetect_Enable  ((uint32_t)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
+                                                ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Flow_Control 
+  * @{
+  */ 
+#define ETH_ReceiveFlowControl_Enable       ((uint32_t)0x00000004)
+#define ETH_ReceiveFlowControl_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
+                                         ((CMD) == ETH_ReceiveFlowControl_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Flow_Control 
+  * @{
+  */ 
+#define ETH_TransmitFlowControl_Enable      ((uint32_t)0x00000002)
+#define ETH_TransmitFlowControl_Disable     ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
+                                          ((CMD) == ETH_TransmitFlowControl_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_VLAN_Tag_Comparison 
+  * @{
+  */ 
+#define ETH_VLANTagComparison_12Bit    ((uint32_t)0x00010000)
+#define ETH_VLANTagComparison_16Bit    ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
+                                                ((COMPARISON) == ETH_VLANTagComparison_16Bit))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Flags 
+  * @{
+  */ 
+#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /*!< MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+                                   ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+                                   ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Interrupts 
+  * @{
+  */ 
+#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+                               ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+                               ((IT) == ETH_MAC_IT_PMT))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses 
+  * @{
+  */ 
+#define ETH_MAC_Address0     ((uint32_t)0x00000000)
+#define ETH_MAC_Address1     ((uint32_t)0x00000008)
+#define ETH_MAC_Address2     ((uint32_t)0x00000010)
+#define ETH_MAC_Address3     ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
+                                         ((ADDRESS) == ETH_MAC_Address1) || \
+                                         ((ADDRESS) == ETH_MAC_Address2) || \
+                                         ((ADDRESS) == ETH_MAC_Address3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
+                                        ((ADDRESS) == ETH_MAC_Address2) || \
+                                        ((ADDRESS) == ETH_MAC_Address3))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames 
+  * @{
+  */ 
+#define ETH_MAC_AddressFilter_SA       ((uint32_t)0x00000000)
+#define ETH_MAC_AddressFilter_DA       ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
+                                           ((FILTER) == ETH_MAC_AddressFilter_DA))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes 
+  * @{
+  */ 
+#define ETH_MAC_AddressMask_Byte6      ((uint32_t)0x20000000)  /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte5      ((uint32_t)0x10000000)  /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_AddressMask_Byte4      ((uint32_t)0x08000000)  /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_AddressMask_Byte3      ((uint32_t)0x04000000)  /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_AddressMask_Byte2      ((uint32_t)0x02000000)  /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte1      ((uint32_t)0x01000000)  /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte5) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte4) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte3) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte2) || \
+                                       ((MASK) == ETH_MAC_AddressMask_Byte1))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                      Ethernet DMA Desciptors defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMATxDesc_IC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LS) || \
+                                         ((FLAG) == ETH_DMATxDesc_FS) || \
+                                         ((FLAG) == ETH_DMATxDesc_DC) || \
+                                         ((FLAG) == ETH_DMATxDesc_DP) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSE) || \
+                                         ((FLAG) == ETH_DMATxDesc_TER) || \
+                                         ((FLAG) == ETH_DMATxDesc_TCH) || \
+                                         ((FLAG) == ETH_DMATxDesc_TTSS) || \
+                                         ((FLAG) == ETH_DMATxDesc_IHE) || \
+                                         ((FLAG) == ETH_DMATxDesc_ES) || \
+                                         ((FLAG) == ETH_DMATxDesc_JT) || \
+                                         ((FLAG) == ETH_DMATxDesc_FF) || \
+                                         ((FLAG) == ETH_DMATxDesc_PCE) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCA) || \
+                                         ((FLAG) == ETH_DMATxDesc_NC) || \
+                                         ((FLAG) == ETH_DMATxDesc_LCO) || \
+                                         ((FLAG) == ETH_DMATxDesc_EC) || \
+                                         ((FLAG) == ETH_DMATxDesc_VF) || \
+                                         ((FLAG) == ETH_DMATxDesc_CC) || \
+                                         ((FLAG) == ETH_DMATxDesc_ED) || \
+                                         ((FLAG) == ETH_DMATxDesc_UF) || \
+                                         ((FLAG) == ETH_DMATxDesc_DB))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment 
+  * @{
+  */ 
+#define ETH_DMATxDesc_LastSegment      ((uint32_t)0x40000000)  /*!< Last Segment */
+#define ETH_DMATxDesc_FirstSegment     ((uint32_t)0x20000000)  /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
+                                            ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+  * @{
+  */ 
+#define ETH_DMATxDesc_ChecksumByPass             ((uint32_t)0x00000000)   /*!< Checksum engine bypass */
+#define ETH_DMATxDesc_ChecksumIPV4Header         ((uint32_t)0x00400000)   /*!< IPv4 header checksum insertion  */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment  ((uint32_t)0x00800000)   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull     ((uint32_t)0x00C00000)   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
+                                              ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
+/** 
+  * @brief  ETH DMA Tx Desciptor buffer size
+  */ 
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+  * @{
+  */ 
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
+                                         ((FLAG) == ETH_DMARxDesc_AFM) || \
+                                         ((FLAG) == ETH_DMARxDesc_ES) || \
+                                         ((FLAG) == ETH_DMARxDesc_DE) || \
+                                         ((FLAG) == ETH_DMARxDesc_SAF) || \
+                                         ((FLAG) == ETH_DMARxDesc_LE) || \
+                                         ((FLAG) == ETH_DMARxDesc_OE) || \
+                                         ((FLAG) == ETH_DMARxDesc_VLAN) || \
+                                         ((FLAG) == ETH_DMARxDesc_FS) || \
+                                         ((FLAG) == ETH_DMARxDesc_LS) || \
+                                         ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
+                                         ((FLAG) == ETH_DMARxDesc_LC) || \
+                                         ((FLAG) == ETH_DMARxDesc_FT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RWT) || \
+                                         ((FLAG) == ETH_DMARxDesc_RE) || \
+                                         ((FLAG) == ETH_DMARxDesc_DBE) || \
+                                         ((FLAG) == ETH_DMARxDesc_CE) || \
+                                         ((FLAG) == ETH_DMARxDesc_MAMPCE))
+
+/* ETHERNET DMA PTP Rx descriptor extended flags  --------------------------------*/
+#define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \
+                                                     ((FLAG) == ETH_DMAPTPRxDesc_IPPT))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ 
+  * @{
+  */ 
+#define ETH_DMARxDesc_Buffer1     ((uint32_t)0x00000000)  /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARxDesc_Buffer2     ((uint32_t)0x00000001)  /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
+                                          ((BUFFER) == ETH_DMARxDesc_Buffer2))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet DMA defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame 
+  * @{
+  */ 
+#define ETH_DropTCPIPChecksumErrorFrame_Enable   ((uint32_t)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable  ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
+                                               ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Store_Forward 
+  * @{
+  */ 
+#define ETH_ReceiveStoreForward_Enable      ((uint32_t)0x02000000)
+#define ETH_ReceiveStoreForward_Disable     ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
+                                           ((CMD) == ETH_ReceiveStoreForward_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Flush_Received_Frame 
+  * @{
+  */ 
+#define ETH_FlushReceivedFrame_Enable       ((uint32_t)0x00000000)
+#define ETH_FlushReceivedFrame_Disable      ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
+                                         ((CMD) == ETH_FlushReceivedFrame_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Store_Forward 
+  * @{
+  */ 
+#define ETH_TransmitStoreForward_Enable     ((uint32_t)0x00200000)
+#define ETH_TransmitStoreForward_Disable    ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
+                                            ((CMD) == ETH_TransmitStoreForward_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Threshold_Control 
+  * @{
+  */ 
+#define ETH_TransmitThresholdControl_64Bytes     ((uint32_t)0x00000000)  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TransmitThresholdControl_128Bytes    ((uint32_t)0x00004000)  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TransmitThresholdControl_192Bytes    ((uint32_t)0x00008000)  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TransmitThresholdControl_256Bytes    ((uint32_t)0x0000C000)  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TransmitThresholdControl_40Bytes     ((uint32_t)0x00010000)  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TransmitThresholdControl_32Bytes     ((uint32_t)0x00014000)  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TransmitThresholdControl_24Bytes     ((uint32_t)0x00018000)  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TransmitThresholdControl_16Bytes     ((uint32_t)0x0001C000)  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
+                                                      ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Error_Frames 
+  * @{
+  */ 
+#define ETH_ForwardErrorFrames_Enable       ((uint32_t)0x00000080)
+#define ETH_ForwardErrorFrames_Disable      ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
+                                          ((CMD) == ETH_ForwardErrorFrames_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames 
+  * @{
+  */ 
+#define ETH_ForwardUndersizedGoodFrames_Enable   ((uint32_t)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable  ((uint32_t)0x00000000)     
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
+                                                    ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Threshold_Control 
+  * @{
+  */ 
+#define ETH_ReceiveThresholdControl_64Bytes      ((uint32_t)0x00000000)  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_ReceiveThresholdControl_32Bytes      ((uint32_t)0x00000008)  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_ReceiveThresholdControl_96Bytes      ((uint32_t)0x00000010)  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_ReceiveThresholdControl_128Bytes     ((uint32_t)0x00000018)  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
+                                                     ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Second_Frame_Operate 
+  * @{
+  */ 
+#define ETH_SecondFrameOperate_Enable       ((uint32_t)0x00000004)
+#define ETH_SecondFrameOperate_Disable      ((uint32_t)0x00000000)  
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
+                                          ((CMD) == ETH_SecondFrameOperate_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Address_Aligned_Beats 
+  * @{
+  */ 
+#define ETH_AddressAlignedBeats_Enable      ((uint32_t)0x02000000)
+#define ETH_AddressAlignedBeats_Disable     ((uint32_t)0x00000000) 
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
+                                           ((CMD) == ETH_AddressAlignedBeats_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Fixed_Burst 
+  * @{
+  */ 
+#define ETH_FixedBurst_Enable     ((uint32_t)0x00010000)
+#define ETH_FixedBurst_Disable    ((uint32_t)0x00000000) 
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
+                                 ((CMD) == ETH_FixedBurst_Disable))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_RxDMABurstLength_1Beat          ((uint32_t)0x00020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RxDMABurstLength_2Beat          ((uint32_t)0x00040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RxDMABurstLength_4Beat          ((uint32_t)0x00080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_8Beat          ((uint32_t)0x00100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_16Beat         ((uint32_t)0x00200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_32Beat         ((uint32_t)0x00400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01020000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01040000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01080000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01100000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01200000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01400000)  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length 
+  * @{
+  */ 
+#define ETH_TxDMABurstLength_1Beat          ((uint32_t)0x00000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TxDMABurstLength_2Beat          ((uint32_t)0x00000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TxDMABurstLength_4Beat          ((uint32_t)0x00000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_8Beat          ((uint32_t)0x00000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_16Beat         ((uint32_t)0x00001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_32Beat         ((uint32_t)0x00002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01000100)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01000200)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01000400)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01000800)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01001000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01002000)  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
+                                           ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
+/** 
+  * @brief  ETH DMA Desciptor SkipLength  
+  */ 
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Arbitration 
+  * @{
+  */ 
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1   ((uint32_t)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1   ((uint32_t)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1   ((uint32_t)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1   ((uint32_t)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx             ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
+                                                       ((RATIO) == ETH_DMAArbitration_RxPriorTx))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Flags 
+  * @{
+  */ 
+#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000)  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_ReadWriteError    ((uint32_t)0x01000000)  /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_AccessError       ((uint32_t)0x02000000)  /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /*!< Receive flag */
+#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) 
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
+                                   ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+                                   ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+                                   ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+                                   ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+                                   ((FLAG) == ETH_DMA_FLAG_T))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Interrupts 
+  * @{
+  */ 
+#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /*!< Receive interrupt */
+#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+                               ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+                               ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+                               ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+                               ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+                               ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+                               ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+                               ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+                               ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_transmit_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_TransmitProcess_Stopped     ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TransmitProcess_Fetching    ((uint32_t)0x00100000)  /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TransmitProcess_Waiting     ((uint32_t)0x00200000)  /*!< Running - waiting for status */
+#define ETH_DMA_TransmitProcess_Reading     ((uint32_t)0x00300000)  /*!< Running - reading the data from host memory */
+#define ETH_DMA_TransmitProcess_Suspended   ((uint32_t)0x00600000)  /*!< Suspended - Tx Desciptor unavailabe */
+#define ETH_DMA_TransmitProcess_Closing     ((uint32_t)0x00700000)  /*!< Running - closing Rx descriptor */
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_DMA_receive_process_state_ 
+  * @{
+  */ 
+#define ETH_DMA_ReceiveProcess_Stopped      ((uint32_t)0x00000000)  /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_ReceiveProcess_Fetching     ((uint32_t)0x00020000)  /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_ReceiveProcess_Waiting      ((uint32_t)0x00060000)  /*!< Running - waiting for packet */
+#define ETH_DMA_ReceiveProcess_Suspended    ((uint32_t)0x00080000)  /*!< Suspended - Rx Desciptor unavailable */
+#define ETH_DMA_ReceiveProcess_Closing      ((uint32_t)0x000A0000)  /*!< Running - closing descriptor */
+#define ETH_DMA_ReceiveProcess_Queuing      ((uint32_t)0x000E0000)  /*!< Running - queuing the recieve frame into host memory */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_overflow_ 
+  * @{
+  */ 
+#define ETH_DMA_Overflow_RxFIFOCounter      ((uint32_t)0x10000000)  /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000)  /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
+                                           ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet PMT defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PMT_Flags 
+  * @{
+  */ 
+#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /*!< Wake-Up Frame Filter Register Poniter Reset */
+#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+                                   ((FLAG) == ETH_PMT_FLAG_MPR))
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet MMC defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Tx_Interrupts 
+  * @{
+  */ 
+#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Rx_Interrupts 
+  * @{
+  */
+#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+                           ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+                               ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+                               ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MMC_Registers 
+  * @{
+  */ 
+#define ETH_MMCCR            ((uint32_t)0x00000100)  /*!< MMC CR register */
+#define ETH_MMCRIR           ((uint32_t)0x00000104)  /*!< MMC RIR register */
+#define ETH_MMCTIR           ((uint32_t)0x00000108)  /*!< MMC TIR register */
+#define ETH_MMCRIMR          ((uint32_t)0x0000010C)  /*!< MMC RIMR register */
+#define ETH_MMCTIMR          ((uint32_t)0x00000110)  /*!< MMC TIMR register */ 
+#define ETH_MMCTGFSCCR       ((uint32_t)0x0000014C)  /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR      ((uint32_t)0x00000150)  /*!< MMC TGFMSCCR register */ 
+#define ETH_MMCTGFCR         ((uint32_t)0x00000168)  /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR        ((uint32_t)0x00000194)  /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR        ((uint32_t)0x00000198)  /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR        ((uint32_t)0x000001C4)  /*!< MMC RGUFCR register */
+
+/** 
+  * @brief  ETH MMC registers  
+  */ 
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR)  || ((REG) == ETH_MMCRIR) || \
+                                  ((REG) == ETH_MMCTIR)  || ((REG) == ETH_MMCRIMR) || \
+                                  ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+                                  ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+                                  ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+                                  ((REG) == ETH_MMCRGUFCR)) 
+
+/**--------------------------------------------------------------------------**/
+/** 
+  * @brief                           Ethernet PTP defines
+  */ 
+/**--------------------------------------------------------------------------**/
+/**
+  * @}
+  */
+
+/** @defgroup ETH_PTP_time_update_method 
+  * @{
+  */ 
+#define ETH_PTP_FineUpdate        ((uint32_t)0x00000001)  /*!< Fine Update method */
+#define ETH_PTP_CoarseUpdate      ((uint32_t)0x00000000)  /*!< Coarse Update method */
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
+                                   ((UPDATE) == ETH_PTP_CoarseUpdate))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_PTP_Flags 
+  * @{
+  */ 
+#define ETH_PTP_FLAG_TSARU        ((uint32_t)0x00000020)  /*!< Addend Register Update */
+#define ETH_PTP_FLAG_TSITE        ((uint32_t)0x00000010)  /*!< Time Stamp Interrupt Trigger */
+#define ETH_PTP_FLAG_TSSTU        ((uint32_t)0x00000008)  /*!< Time Stamp Update */
+#define ETH_PTP_FLAG_TSSTI        ((uint32_t)0x00000004)  /*!< Time Stamp Initialize */
+
+#define ETH_PTP_FLAG_TSTTR        ((uint32_t)0x10000002)  /* Time stamp target time reached */
+#define ETH_PTP_FLAG_TSSO         ((uint32_t)0x10000001)  /* Time stamp seconds overflow */
+
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
+                                    ((FLAG) == ETH_PTP_FLAG_TSITE) || \
+                                    ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
+                                    ((FLAG) == ETH_PTP_FLAG_TSSTI) || \
+                                    ((FLAG) == ETH_PTP_FLAG_TSTTR) || \
+                                    ((FLAG) == ETH_PTP_FLAG_TSSO)) 
+
+/** 
+  * @brief  ETH PTP subsecond increment  
+  */ 
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ETH_PTP_time_sign 
+  * @{
+  */ 
+#define ETH_PTP_PositiveTime      ((uint32_t)0x00000000)  /*!< Positive time value */
+#define ETH_PTP_NegativeTime      ((uint32_t)0x80000000)  /*!< Negative time value */
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
+                                    ((SIGN) == ETH_PTP_NegativeTime))
+
+/** 
+  * @brief  ETH PTP time stamp low update  
+  */ 
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
+
+/** 
+  * @brief  ETH PTP registers  
+  */ 
+#define ETH_PTPTSCR     ((uint32_t)0x00000700)  /*!< PTP TSCR register */
+#define ETH_PTPSSIR     ((uint32_t)0x00000704)  /*!< PTP SSIR register */
+#define ETH_PTPTSHR     ((uint32_t)0x00000708)  /*!< PTP TSHR register */
+#define ETH_PTPTSLR     ((uint32_t)0x0000070C)  /*!< PTP TSLR register */
+#define ETH_PTPTSHUR    ((uint32_t)0x00000710)  /*!< PTP TSHUR register */
+#define ETH_PTPTSLUR    ((uint32_t)0x00000714)  /*!< PTP TSLUR register */
+#define ETH_PTPTSAR     ((uint32_t)0x00000718)  /*!< PTP TSAR register */
+#define ETH_PTPTTHR     ((uint32_t)0x0000071C)  /*!< PTP TTHR register */
+#define ETH_PTPTTLR     ((uint32_t)0x00000720)  /* PTP TTLR register */
+
+#define ETH_PTPTSSR     ((uint32_t)0x00000728)  /* PTP TSSR register */
+
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
+                                   ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
+                                   ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
+                                   ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
+                                   ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR)) 
+
+/** 
+  * @brief  ETHERNET PTP clock  
+  */ 
+#define ETH_PTP_OrdinaryClock               ((uint32_t)0x00000000)  /* Ordinary Clock */
+#define ETH_PTP_BoundaryClock               ((uint32_t)0x00010000)  /* Boundary Clock */
+#define ETH_PTP_EndToEndTransparentClock    ((uint32_t)0x00020000)  /* End To End Transparent Clock */
+#define ETH_PTP_PeerToPeerTransparentClock  ((uint32_t)0x00030000)  /* Peer To Peer Transparent Clock */
+
+#define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \
+                          ((CLOCK) == ETH_PTP_BoundaryClock) || \
+                          ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \
+                                      ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock))
+/** 
+  * @brief  ETHERNET snapshot
+  */
+#define ETH_PTP_SnapshotMasterMessage          ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTP_SnapshotEventMessage           ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */
+#define ETH_PTP_SnapshotIPV4Frames             ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTP_SnapshotIPV6Frames             ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTP_SnapshotPTPOverEthernetFrames  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTP_SnapshotAllReceivedFrames      ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */
+
+#define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \
+                           ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \
+                           ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \
+                           ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \
+                           ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \
+                           ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames))
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions
+  * @{
+  */ 
+void ETH_DeInit(void);
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress);
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+void  ETH_Start(void);
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength);
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt);
+uint32_t ETH_GetRxPktSize(void);
+void ETH_DropRxPkt(void);
+
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+ void ETH_EnhancedDescriptorCmd(FunctionalState NewState);
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+
+/** 
+  * @brief  PHY  
+  */ 
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg);
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue);
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState);
+
+/** 
+  * @brief  MAC  
+  */ 
+void ETH_MACTransmissionCmd(FunctionalState NewState);
+void ETH_MACReceptionCmd(FunctionalState NewState);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);  
+void ETH_BackPressureActivationCmd(FunctionalState NewState); 
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);  
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr);
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr);
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
+
+/** 
+  * @brief  DMA Tx/Rx descriptors  
+  */ 
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+ FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag);
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
+
+/** 
+  * @brief  DMA
+  */ 
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
+uint32_t ETH_GetTransmitProcessState(void);
+uint32_t ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState NewState);
+void ETH_DMAReceptionCmd(FunctionalState NewState);
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
+uint32_t ETH_GetCurrentTxDescStartAddress(void);
+uint32_t ETH_GetCurrentRxDescStartAddress(void);
+uint32_t ETH_GetCurrentTxBufferAddress(void);
+uint32_t ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+void ETH_SetReceiveWatchdogTimer(uint8_t Value);
+
+
+/** 
+  * @brief  PMT  
+  */ 
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
+void ETH_PowerDownCmd(FunctionalState NewState);
+
+/** 
+  * @brief  MMC  
+  */ 
+void ETH_MMCCounterFullPreset(void);
+void ETH_MMCCounterHalfPreset(void);
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
+
+/** 
+  * @brief  PTP  
+  */ 
+void ETH_PTPNodeClockTypeConfig(uint32_t ClockType);
+void ETH_PTPSnapshotCmd(uint32_t SnapshotMethod, FunctionalState NewState);
+void ETH_PTPPacketSnoopingV2FormatCmd(FunctionalState NewState);
+void ETH_PTPSubSecondRolloverCmd(FunctionalState NewState);
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab);
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab);
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS
+ void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
+ void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+#endif /* USE_ENHANCED_DMA_DESCRIPTORS */
+void ETH_EnablePTPTimeStampAddend(void);
+void ETH_EnablePTPTimeStampInterruptTrigger(void);
+void ETH_EnablePTPTimeStampUpdate(void);
+void ETH_InitializePTPTimeStamp(void);
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
+void ETH_PTPTimeStampCmd(FunctionalState NewState);
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampAddend(uint32_t Value);
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);
+
+/* STM32 ETH HW initialization */
+void rt_hw_stm32_eth_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F2XX_ETH_H */
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/

bsp/stm32f20x/template.uvproj

@@ -0,0 +1,388 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>RT-Thread STM32</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32F207VG</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <Cpu>IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\ST\STM32F2xx\startup_stm32f2xx.s" ("STM32F2xx Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000)</FlashDriverDll>
+          <DeviceId>5118</DeviceId>
+          <RegisterFile>stm32f2xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\ST\STM32F2xx\STM32F2xx.sfr</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>ST\STM32F2xx\</RegisterFilePath>
+          <DBRegisterFilePath>ST\STM32F2xx\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\obj\</OutputDirectory>
+          <OutputName>rtthread-stm32</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DARMSTM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pSTM32F207VG</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pSTM32F207VG</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4099</DriverSelection>
+          </Flash1>
+          <Flash2>Segger\JL2CM3.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>

bsp/stm32f20x/usart.c

@@ -0,0 +1,195 @@
+/*
+ * File      : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2010-03-29     Bernard      remove interrupt Tx and DMA Rx mode
+ */
+
+#include "usart.h"
+#include <serial.h>
+#include <stm32f2xx.h>
+#include <stm32f2xx_dma.h>
+
+/*
+ * Use UART1 as console output and finsh input
+ * interrupt Rx and poll Tx (stream mode)
+ *
+ * Use UART2 with interrupt Rx and poll Tx
+ * Use UART3 with DMA Tx and interrupt Rx -- DMA channel 2
+ *
+ * USART DMA setting on STM32
+ * USART1 Tx --> DMA Channel 4
+ * USART1 Rx --> DMA Channel 5
+ * USART2 Tx --> DMA Channel 7
+ * USART2 Rx --> DMA Channel 6
+ * USART3 Tx --> DMA Channel 2
+ * USART3 Rx --> DMA Channel 3
+ */
+
+#ifdef RT_USING_UART1
+struct stm32_serial_int_rx uart1_int_rx;
+struct stm32_serial_device uart1 =
+{
+	USART1,
+	&uart1_int_rx,
+	RT_NULL
+};
+struct rt_device uart1_device;
+#endif
+
+#ifdef RT_USING_UART2
+struct stm32_serial_int_rx uart2_int_rx;
+struct stm32_serial_device uart2 =
+{
+	USART2,
+	&uart2_int_rx,
+	RT_NULL
+};
+struct rt_device uart2_device;
+#endif
+
+#ifdef RT_USING_UART3
+struct stm32_serial_int_rx uart3_int_rx;
+struct stm32_serial_dma_tx uart3_dma_tx;
+struct stm32_serial_device uart3 =
+{
+	USART3,
+	&uart3_int_rx,
+	&uart3_dma_tx
+};
+struct rt_device uart3_device;
+#endif
+
+#define USART1_DR_Base  0x40013804
+#define USART2_DR_Base  0x40004404
+#define USART3_DR_Base  0x40004804
+
+/* USART1_REMAP = 0 */
+#define UART1_GPIO_TX		GPIO_Pin_9
+#define UART1_GPIO_RX		GPIO_Pin_10
+#define UART1_GPIO			GPIOA
+#define RCC_APBPeriph_UART1	RCC_APB2Periph_USART1
+#define UART1_TX_DMA		DMA1_Channel4
+#define UART1_RX_DMA		DMA1_Channel5
+
+#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL)
+#define UART2_GPIO_TX	    GPIO_Pin_5
+#define UART2_GPIO_RX	    GPIO_Pin_6
+#define UART2_GPIO	    	GPIOD
+#define RCC_APBPeriph_UART2	RCC_APB1Periph_USART2
+#else /* for STM32F10X_HD */
+/* USART2_REMAP = 0 */
+#define UART2_GPIO_TX		GPIO_Pin_2
+#define UART2_GPIO_RX		GPIO_Pin_3
+#define UART2_GPIO			GPIOA
+#define RCC_APBPeriph_UART2	RCC_APB1Periph_USART2
+#define UART2_TX_DMA		DMA1_Channel7
+#define UART2_RX_DMA		DMA1_Channel6
+#endif
+
+/* USART3_REMAP[1:0] = 00 */
+#define UART3_GPIO_RX		GPIO_Pin_11
+#define UART3_GPIO_TX		GPIO_Pin_10
+#define UART3_GPIO			GPIOB
+#define RCC_APBPeriph_UART3	RCC_APB1Periph_USART3
+#define UART3_TX_DMA		DMA1_Channel2
+#define UART3_RX_DMA		DMA1_Channel3
+
+static void RCC_Configuration(void)
+{
+#ifdef RT_USING_UART1
+	/* Enable USART1 and GPIOA clocks */
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+#endif
+}
+
+static void GPIO_Configuration(void)
+{
+	GPIO_InitTypeDef GPIO_InitStruct;
+
+#ifdef RT_USING_UART1
+	GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
+	GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
+	GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
+	GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;  
+
+	GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10;
+	GPIO_Init(GPIOA,&GPIO_InitStruct);
+
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);  
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);	
+#endif
+}
+
+static void NVIC_Configuration(void)
+{
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+#ifdef RT_USING_UART1
+	/* Enable the USART1 Interrupt */
+	NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+	NVIC_Init(&NVIC_InitStructure);
+#endif
+}
+
+/*
+ * Init all related hardware in here
+ * rt_hw_serial_init() will register all supported USART device
+ */
+void rt_hw_usart_init()
+{
+	USART_InitTypeDef USART_InitStructure;
+
+	RCC_Configuration();
+
+	GPIO_Configuration();
+
+	NVIC_Configuration();
+
+	/* uart init */
+#ifdef RT_USING_UART1
+	USART_DeInit(USART1);				
+	USART_InitStructure.USART_BaudRate            = 115200;
+	USART_InitStructure.USART_WordLength          = USART_WordLength_8b;
+	USART_InitStructure.USART_StopBits            = USART_StopBits_1;
+	USART_InitStructure.USART_Parity              = USART_Parity_No ;
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+	USART_InitStructure.USART_Mode                = USART_Mode_Rx | USART_Mode_Tx;
+
+	USART_Init(USART1, &USART_InitStructure);
+
+	/* register uart1 */
+	rt_hw_serial_register(&uart1_device, "uart1",
+		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+		&uart1);
+
+	/* enable interrupt */
+	USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
+	/* Enable USART1 */
+	USART_Cmd(USART1, ENABLE);
+	USART_ClearFlag(USART1,USART_FLAG_TXE);
+#endif
+}
+
+void USART1_IRQHandler()
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_serial_isr(&uart1_device);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}

bsp/stm32f20x/usart.h

@@ -0,0 +1,23 @@
+/*
+ * File      : usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+void rt_hw_usart_init(void);
+
+#endif