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@@ -5,51 +5,94 @@
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*
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* Change Logs:
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* Date Author Notes
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- * 2020-1-13 Leo first version
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+ * 2021-11-11 breo.com first version
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*/
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#include <board.h>
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#include "drv_pwm.h"
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#ifdef RT_USING_PWM
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- #if !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
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- !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4)
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+ #if !defined(BSP_USING_TIM1_CH1) && !defined(BSP_USING_TIM1_CH2) && \
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+ !defined(BSP_USING_TIM1_CH3) && !defined(BSP_USING_TIM1_CH4) && \
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+ !defined(BSP_USING_TIM2_CH1) && !defined(BSP_USING_TIM2_CH2) && \
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+ !defined(BSP_USING_TIM2_CH3) && !defined(BSP_USING_TIM2_CH4) && \
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+ !defined(BSP_USING_TIM3_CH1) && !defined(BSP_USING_TIM3_CH2) && \
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+ !defined(BSP_USING_TIM3_CH3) && !defined(BSP_USING_TIM3_CH4) && \
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+ !defined(BSP_USING_TIM4_CH1) && !defined(BSP_USING_TIM4_CH2) && \
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+ !defined(BSP_USING_TIM4_CH3) && !defined(BSP_USING_TIM4_CH4) && \
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+ !defined(BSP_USING_TIM5_CH1) && !defined(BSP_USING_TIM5_CH2) && \
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+ !defined(BSP_USING_TIM5_CH3) && !defined(BSP_USING_TIM5_CH4) && \
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+ !defined(BSP_USING_TIM8_CH1) && !defined(BSP_USING_TIM8_CH2) && \
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+ !defined(BSP_USING_TIM8_CH3) && !defined(BSP_USING_TIM8_CH4)
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#error "Please define at least one BSP_USING_TIMx_CHx"
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#endif
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#endif /* RT_USING_PWM */
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-#define DRV_DEBUG
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-#define LOG_TAG "drv.pwm"
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-#include <drv_log.h>
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-
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#define MAX_PERIOD 65535
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-struct rt_device_pwm pwm_device;
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+
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+#ifdef BSP_USING_PWM
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struct n32_pwm
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{
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- struct rt_device_pwm pwm_device;
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TIM_Module *tim_handle;
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- rt_uint8_t channel;
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- char *name;
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+ const char *name;
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+ struct rt_device_pwm pwm_device;
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+ int8_t tim_en;
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+ uint8_t ch_en;
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+ uint32_t period;
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+ uint32_t psc;
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};
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static struct n32_pwm n32_pwm_obj[] =
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{
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-#ifdef BSP_USING_TIM3_CH1
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- PWM1_TIM3_CONFIG,
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+#if defined(BSP_USING_TIM1_CH1) || defined(BSP_USING_TIM1_CH2) || \
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+ defined(BSP_USING_TIM1_CH3) || defined(BSP_USING_TIM1_CH4)
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+ {
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+ .tim_handle = TIM1,
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+ .name = "tim1pwm",
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+ },
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#endif
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-#ifdef BSP_USING_TIM3_CH2
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- PWM2_TIM3_CONFIG,
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+#if defined(BSP_USING_TIM2_CH1) || defined(BSP_USING_TIM2_CH2) || \
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+ defined(BSP_USING_TIM2_CH3) || defined(BSP_USING_TIM2_CH4)
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+ {
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+ .tim_handle = TIM2,
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+ .name = "tim2pwm",
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+ },
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#endif
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-#ifdef BSP_USING_TIM3_CH3
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- PWM3_TIM3_CONFIG,
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+#if defined(BSP_USING_TIM3_CH1) || defined(BSP_USING_TIM3_CH2) || \
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+ defined(BSP_USING_TIM3_CH3) || defined(BSP_USING_TIM3_CH4)
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+ {
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+ .tim_handle = TIM3,
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+ .name = "tim3pwm",
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+ },
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#endif
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-#ifdef BSP_USING_TIM3_CH4
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- PWM4_TIM3_CONFIG,
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+#if defined(BSP_USING_TIM4_CH1) || defined(BSP_USING_TIM4_CH2) || \
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+ defined(BSP_USING_TIM4_CH3) || defined(BSP_USING_TIM4_CH4)
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+ {
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+ .tim_handle = TIM4,
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+ .name = "tim4pwm",
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+ },
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+#endif
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+
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+#if defined(BSP_USING_TIM5_CH1) || defined(BSP_USING_TIM5_CH2) || \
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+ defined(BSP_USING_TIM5_CH3) || defined(BSP_USING_TIM5_CH4)
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+ {
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+ .tim_handle = TIM5,
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+ .name = "tim5pwm",
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+ },
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+#endif
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+
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+#if defined(BSP_USING_TIM8_CH1) || defined(BSP_USING_TIM8_CH2) || \
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+ defined(BSP_USING_TIM8_CH3) || defined(BSP_USING_TIM8_CH4)
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+ {
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+ .tim_handle = TIM8,
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+ .name = "tim8pwm",
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+ }
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#endif
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+
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};
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
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@@ -58,61 +101,81 @@ static struct rt_pwm_ops drv_ops =
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drv_pwm_control
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};
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-static rt_err_t drv_pwm_enable(TIM_Module *TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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+static rt_err_t drv_pwm_enable(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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/* Get the value of channel */
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rt_uint32_t channel = configuration->channel;
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+ TIM_Module *TIMx = pwm_dev->tim_handle;
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+
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+ if (enable)
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+ {
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+ pwm_dev->ch_en |= 0x1 << channel;
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+ }
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+ else
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+ {
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+ pwm_dev->ch_en &= ~(0x1 << channel);
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+ }
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- if (!enable)
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+ if (enable)
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{
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if (channel == 1)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
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}
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else if (channel == 2)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
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}
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else if (channel == 3)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
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}
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else if (channel == 4)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
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}
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}
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else
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{
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if (channel == 1)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_ENABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 2)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_ENABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 3)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_ENABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 4)
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{
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- TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_ENABLE);
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
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}
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}
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- TIM_Enable(TIMx, ENABLE);
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+ if (pwm_dev->ch_en)
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+ {
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+ pwm_dev->tim_en = 0x1;
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+ TIM_Enable(TIMx, ENABLE);
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+ }
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+ else
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+ {
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+ pwm_dev->tim_en = 0x0;
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+ TIM_Enable(TIMx, DISABLE);
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+ }
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return RT_EOK;
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}
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-static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
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+static rt_err_t drv_pwm_get(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
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{
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RCC_ClocksType RCC_Clockstruct;
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rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
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- rt_uint32_t channel = configuration->channel;
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rt_uint64_t tim_clock;
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+ rt_uint32_t channel = configuration->channel;
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+ TIM_Module *TIMx = pwm_dev->tim_handle;
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ar = TIMx->AR;
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div = TIMx->PSC;
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@@ -140,9 +203,13 @@ static rt_err_t drv_pwm_get(TIM_Module *TIMx, struct rt_pwm_configuration *confi
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return RT_EOK;
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}
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-static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *configuration)
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+static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration *configuration)
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{
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+ TIM_Module *TIMx = pwm_dev->tim_handle;
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+ rt_uint32_t channel = configuration->channel;
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+
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/* Init timer pin and enable clock */
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+ void n32_msp_tim_init(void *Instance);
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n32_msp_tim_init(TIMx);
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RCC_ClocksType RCC_Clock;
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@@ -167,14 +234,17 @@ static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *confi
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period = period / psc;
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psc = psc * (input_clock / 1000000);
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- /* TIMe base configuration */
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- TIM_TimeBaseInitType TIM_TIMeBaseStructure;
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- TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
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- TIM_TIMeBaseStructure.Period = period;
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- TIM_TIMeBaseStructure.Prescaler = psc - 1;
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- TIM_TIMeBaseStructure.ClkDiv = 0;
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- TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
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- TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
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+ if ((pwm_dev->period != period) || (pwm_dev->psc != psc))
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+ {
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+ /* TIMe base configuration */
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+ TIM_TimeBaseInitType TIM_TIMeBaseStructure;
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+ TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
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+ TIM_TIMeBaseStructure.Period = period;
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+ TIM_TIMeBaseStructure.Prescaler = psc - 1;
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+ TIM_TIMeBaseStructure.ClkDiv = 0;
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+ TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
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+ TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
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+ }
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rt_uint32_t pulse = (unsigned long long)configuration->pulse;
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/* PWM1 Mode configuration: Channel1 */
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@@ -185,26 +255,33 @@ static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *confi
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TIM_OCInitStructure.Pulse = pulse;
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TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
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- rt_uint32_t channel = configuration->channel;
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if (channel == 1)
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{
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TIM_InitOc1(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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+ if (!(pwm_dev->ch_en & (0x1 << channel)))
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_1, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 2)
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{
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TIM_InitOc2(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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+ if (!(pwm_dev->ch_en & (0x1 << channel)))
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_2, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 3)
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{
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TIM_InitOc3(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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+ if (!(pwm_dev->ch_en & (0x1 << channel)))
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_3, TIM_CAP_CMP_DISABLE);
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}
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else if (channel == 4)
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{
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TIM_InitOc4(TIMx, &TIM_OCInitStructure);
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TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
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+ if (!(pwm_dev->ch_en & (0x1 << channel)))
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+ TIM_EnableCapCmpCh(TIMx, TIM_CH_4, TIM_CAP_CMP_DISABLE);
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}
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TIM_ConfigArPreload(TIMx, ENABLE);
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@@ -216,18 +293,18 @@ static rt_err_t drv_pwm_set(TIM_Module *TIMx, struct rt_pwm_configuration *confi
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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- TIM_Module *TIMx = (TIM_Module *)device->parent.user_data;
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+ struct n32_pwm *pwm_dev = (struct n32_pwm *)(device->parent.user_data);
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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- return drv_pwm_enable(TIMx, configuration, RT_TRUE);
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+ return drv_pwm_enable(pwm_dev, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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- return drv_pwm_enable(TIMx, configuration, RT_FALSE);
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+ return drv_pwm_enable(pwm_dev, configuration, RT_FALSE);
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case PWM_CMD_SET:
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- return drv_pwm_set(TIMx, configuration);
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+ return drv_pwm_set(pwm_dev, configuration);
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case PWM_CMD_GET:
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- return drv_pwm_get(TIMx, configuration);
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+ return drv_pwm_get(pwm_dev, configuration);
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default:
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return RT_EINVAL;
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}
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@@ -240,13 +317,12 @@ static int rt_hw_pwm_init(void)
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for (i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
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{
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- if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK)
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+ if (rt_device_pwm_register(&n32_pwm_obj[i].pwm_device,
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+ n32_pwm_obj[i].name, &drv_ops, &(n32_pwm_obj[i])) == RT_EOK)
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{
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- LOG_D("%s register success", n32_pwm_obj[i].name);
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}
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else
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{
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- LOG_D("%s register failed", n32_pwm_obj[i].name);
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result = -RT_ERROR;
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}
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}
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@@ -254,3 +330,6 @@ static int rt_hw_pwm_init(void)
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pwm_init);
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+
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+#endif
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+
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