[bsp][hpmicro] Update libraries, add new BSPs

- Updated hpm_sdk in libraries
- Updated rt-thread driver adapter
- Updated bsp for hpm6750evkmini
- Updated bsp for hpm6750evk
- Added bsp for hpm6750evk2
- Added bsp for hpm6300evk
- Added bsp for hpm6200evk

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>

bsp/hpmicro/.ignore_format.yml

@@ -0,0 +1,11 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+  - hpm6200evk/startup
+  - hpm6300evk/startup
+  - hpm6750evk/startup
+  - hpm6750evk2/startup
+  - hpm6750evkmini/startup
+  - libraries/hpm_sdk

bsp/hpmicro/hpm6200evk/.config

@@ -0,0 +1,1043 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# CONFIG_RT_USING_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_RT_USING_HW_ATOMIC is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_DFS_MQUEUE is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+# CONFIG_RT_USING_KTIME is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HPM6000=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_UART0_RX_USING_DMA is not set
+# CONFIG_BSP_UART0_TX_USING_DMA is not set
+CONFIG_BSP_UART0_RX_DMA_CHANNEL=0
+CONFIG_BSP_UART0_TX_DMA_CHANNEL=1
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_SDXC is not set
+# CONFIG_BSP_USING_GPTMR is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_XPI_FLASH is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_WDG is not set
+# CONFIG_BSP_USING_MCAN is not set
+# CONFIG_BSP_USING_ADC is not set

bsp/hpmicro/hpm6200evk/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/hpmicro/hpm6200evk/README.md

@@ -0,0 +1,114 @@
+# HPMicro HPM6200EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides brief introduction of the BSP (board support package) for the HPM6200EVK development board.
+
+The document consists of the following parts:
+
+- HPM6200EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM6200EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6200EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6200evk)

bsp/hpmicro/hpm6200evk/README_zh.md

@@ -0,0 +1,115 @@
+# 先楫 HPM6200EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM6200EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM6200EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+ HPM6200EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           | 由RT-Thread Industry IO扩展板提供支持    |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6200EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6200evk)

bsp/hpmicro/hpm6200evk/SConscript

@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hpmicro/hpm6200evk/SConstruct

@@ -0,0 +1,75 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hpm_library = 'hpm_sdk'
+rtconfig.BSP_LIBRARY_TYPE = hpm_library
+
+# include soc
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
+
+# include components
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/SConscript → bsp/hpmicro/hpm6200evk/applications/SConscript

@@ -9,6 +9,6 @@ src = Glob('*.c')
 CPPDEFINES=[]
 CPPPATH = [cwd]
 
-group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
 
 Return('group')

bsp/hpmicro/hpm6200evk/applications/main.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+#include <drv_gpio.h>
+
+void thread_entry(void *arg);
+
+
+int main(void)
+{
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+
+void thread_entry(void *arg)
+{
+    rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while(1){
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON);
+        rt_thread_mdelay(500);
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}

bsp/hpmicro/hpm6200evk/board/Kconfig

@@ -0,0 +1,289 @@
+menu "Hardware Drivers Config"
+
+config SOC_HPM6000
+    bool
+    select SOC_SERIES_HPM6000
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN if BSP_USING_GPIO
+        default n
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART0
+                bool "Enable UART0 (Debugger)"
+                default y
+                if BSP_USING_UART0
+                    config BSP_UART0_RX_USING_DMA
+                        bool "Enable UART0 RX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_TX_USING_DMA
+                        bool "Enable UART0 TX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_RX_DMA_CHANNEL
+                        int "Set UART0 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART0_TX_DMA_CHANNEL
+                        int "Set UART0 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART0_RX_BUFSIZE
+                        int "Set UART0 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART0_TX_BUFSIZE
+                        int "Set UART0 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+                if BSP_USING_UART2
+                    config BSP_UART2_RX_USING_DMA
+                        bool "Enable UART2 RX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_TX_USING_DMA
+                        bool "Enable UART2 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_RX_DMA_CHANNEL
+                        int "Set UART2 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART2_TX_DMA_CHANNEL
+                        int "Set UART2 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART2_RX_BUFSIZE
+                        int "Set UART2 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+
+                    config BSP_UART2_TX_BUFSIZE
+                        int "Set UART2 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_USING_DMA
+                        bool "Enable UART6 RX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART6_TX_USING_DMA
+                        bool "Enable UART6 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART6_RX_DMA_CHANNEL
+                        int "Set UART6 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART6_TX_DMA_CHANNEL
+                        int "Set UART6 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 1024
+
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+        endif
+
+
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI if BSP_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                    default y
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                    default n
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_RTC
+       bool "Enable RTC"
+       default n
+
+    menuconfig BSP_USING_ETH
+       bool "Enable Ethernet"
+       default n
+
+       select RT_USING_ETH
+       if BSP_USING_ETH
+       		choice
+		prompt "ETH"
+	    	config BSP_USING_ETH0
+	        bool "Enable ETH0"
+	   	endchoice
+       endif
+
+    menuconfig BSP_USING_SDXC
+        bool "Enable SDXC"
+        default n
+        select RT_USING_SDIO if BSP_USING_SDXC
+        if BSP_USING_SDXC
+            config BSP_USING_SDXC0
+                bool "Enable SDXC0"
+                    default n
+        endif
+
+    menuconfig BSP_USING_GPTMR
+	   	bool "Enable GPTMR"
+	   	default n
+	   	select RT_USING_HWTIMER if BSP_USING_GPTMR
+	   	if BSP_USING_GPTMR
+			config BSP_USING_GPTMR0
+	   			bool "Enable GPTMR0"
+	   			default n
+	   		config BSP_USING_GPTMR1
+	   			bool "Enable GPTMR1"
+	   			default n
+	   		config BSP_USING_GPTMR2
+	   			bool "Enable GPTMR2"
+	   			default n
+        endif
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        default n
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                    default y
+
+            config BSP_USING_I2C3
+                bool "Enable I2C3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_XPI_FLASH
+    	bool "Enable XPI FLASH"
+	default n
+    	select PKG_USING_FAL if BSP_USING_XPI_FLASH
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+	default n
+
+    menuconfig BSP_USING_USB
+       bool "Enable USB"
+       default n
+       if BSP_USING_USB
+       		config BSP_USING_USB_DEVICE
+                bool "Enable USB Device"
+                    default n
+            config BSP_USING_USB_HOST
+                bool "Enable USB HOST"
+                    default n
+       endif
+
+
+     menuconfig BSP_USING_WDG
+     	bool "Enable Watchdog"
+     	default n
+     	select RT_USING_WDT if BSP_USING_WDG
+     	if BSP_USING_WDG
+     		config BSP_USING_WDG0
+     			bool "Enable WDG0"
+     			default n
+     		config BSP_USING_WDG1
+     			bool "Enable WDG1"
+     			default n
+     	endif
+
+     menuconfig BSP_USING_MCAN
+     	bool "Enable MCAN"
+     	default n
+     	select RT_USING_CAN if BSP_USING_MCAN
+     	if BSP_USING_MCAN
+     		config BSP_USING_MCAN0
+     			bool "Enable MCAN0"
+     			default n
+     		config BSP_USING_MCAN1
+     			bool "Enable MCAN1"
+     			default n
+            config BSP_USING_MCAN2
+     			bool "Enable MCAN2"
+     			default n
+     		config BSP_USING_MCAN3
+     			bool "Enable MCAN3"
+     			default n
+     endif
+
+     menuconfig BSP_USING_ADC
+     	bool "Enable ADC"
+     	default n
+     	select RT_USING_ADC if BSP_USING_ADC
+     	if BSP_USING_ADC
+            menuconfig BSP_USING_ADC16
+            bool "Enable ADC16"
+            default y
+            if BSP_USING_ADC16
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default y
+                config BSP_USING_ADC1
+                    bool "Enable ADC1"
+                    default n
+                config BSP_USING_ADC2
+                    bool "Enable ADC2"
+                    default n
+            endif
+        endif
+endmenu
+
+
+
+endmenu

bsp/hpmicro/hpm6200evk/board/SConscript

@@ -0,0 +1,18 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    fal_flash_port.c
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM6280']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/hpm6200evk/board/board.c

@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ *
+ */
+
+#include "board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gptmr_drv.h"
+#include "hpm_lcdc_drv.h"
+#include "hpm_i2c_drv.h"
+#include "hpm_gpio_drv.h"
+#include "pinmux.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include "hpm_pwm_drv.h"
+#include "hpm_trgm_drv.h"
+#include "hpm_pllctlv2_drv.h"
+#include "hpm_pcfg_drv.h"
+
+static board_timer_cb timer_cb;
+ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag;
+
+/**
+ * @brief FLASH configuration option definitions:
+ * option[0]:
+ *    [31:16] 0xfcf9 - FLASH configuration option tag
+ *    [15:4]  0 - Reserved
+ *    [3:0]   option words (exclude option[0])
+ * option[1]:
+ *    [31:28] Flash probe type
+ *      0 - SFDP SDR / 1 - SFDP DDR
+ *      2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+ *      4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+ *      6 - OctaBus DDR (SPI -> OPI DDR)
+ *      8 - Xccela DDR (SPI -> OPI DDR)
+ *      10 - EcoXiP DDR (SPI -> OPI DDR)
+ *    [27:24] Command Pads after Power-on Reset
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [23:20] Command Pads after Configuring FLASH
+ *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+ *    [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+ *      0 - Not needed
+ *      1 - QE bit is at bit 6 in Status Register 1
+ *      2 - QE bit is at bit1 in Status Register 2
+ *      3 - QE bit is at bit7 in Status Register 2
+ *      4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+ *    [15:8] Dummy cycles
+ *      0 - Auto-probed / detected / default value
+ *      Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+ *    [7:4] Misc.
+ *      0 - Not used
+ *      1 - SPI mode
+ *      2 - Internal loopback
+ *      3 - External DQS
+ *    [3:0] Frequency option
+ *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+ *
+ * option[2] (Effective only if the bit[3:0] in option[0] > 1)
+ *    [31:20]  Reserved
+ *    [19:16] IO voltage
+ *      0 - 3V / 1 - 1.8V
+ *    [15:12] Pin group
+ *      0 - 1st group / 1 - 2nd group
+ *    [11:8] Connection selection
+ *      0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+ *    [7:0] Drive Strength
+ *      0 - Default value
+ * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
+ *              JESD216)
+ *    [31:16] reserved
+ *    [15:12] Sector Erase Command Option, not required here
+ *    [11:8]  Sector Size Option, not required here
+ *    [7:0] Flash Size Option
+ *      0 - 4MB / 1 - 8MB / 2 - 16MB
+ */
+#if defined(FLASH_XIP) && FLASH_XIP
+__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 };
+#endif
+
+#if defined(FLASH_UF2) && FLASH_UF2
+ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
+#endif
+
+void board_init_console(void)
+{
+#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
+    console_config_t cfg;
+
+    /* uart needs to configure pin function before enabling clock, otherwise the level change of
+    uart rx pin when configuring pin function will cause a wrong data to be received.
+    And a uart rx dma request will be generated by default uart fifo dma trigger level. */
+    init_uart_pins((UART_Type *) BOARD_CONSOLE_BASE);
+
+    /* Configure the UART clock to 24MHz */
+    clock_set_source_divider(BOARD_CONSOLE_CLK_NAME, clk_src_osc24m, 1U);
+    clock_add_to_group(BOARD_CONSOLE_CLK_NAME, 0);
+
+    cfg.type = BOARD_CONSOLE_TYPE;
+    cfg.base = (uint32_t)BOARD_CONSOLE_BASE;
+    cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_CLK_NAME);
+    cfg.baudrate = BOARD_CONSOLE_BAUDRATE;
+
+    if (status_success != console_init(&cfg)) {
+        /* failed to  initialize debug console */
+        while (1) {
+        }
+    }
+#else
+    while (1)
+        ;
+#endif
+#endif
+}
+
+void board_print_clock_freq(void)
+{
+    printf("==============================\n");
+    printf(" %s clock summary\n", BOARD_NAME);
+    printf("==============================\n");
+    printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0));
+    printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
+    printf("axi:\t\t %dHz\n", clock_get_frequency(clock_axi));
+    printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb));
+    printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0));
+    printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
+    printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0));
+    printf("==============================\n");
+}
+
+void board_init_uart(UART_Type *ptr)
+{
+    /* configure uart's pin before opening uart's clock */
+    init_uart_pins(ptr);
+    board_init_uart_clock(ptr);
+}
+
+void board_print_banner(void)
+{
+    const uint8_t banner[] = { "\n\
+----------------------------------------------------------------------\n\
+$$\\   $$\\ $$$$$$$\\  $$\\      $$\\ $$\\\n\
+$$ |  $$ |$$  __$$\\ $$$\\    $$$ |\\__|\n\
+$$ |  $$ |$$ |  $$ |$$$$\\  $$$$ |$$\\  $$$$$$$\\  $$$$$$\\   $$$$$$\\\n\
+$$$$$$$$ |$$$$$$$  |$$\\$$\\$$ $$ |$$ |$$  _____|$$  __$$\\ $$  __$$\\\n\
+$$  __$$ |$$  ____/ $$ \\$$$  $$ |$$ |$$ /      $$ |  \\__|$$ /  $$ |\n\
+$$ |  $$ |$$ |      $$ |\\$  /$$ |$$ |$$ |      $$ |      $$ |  $$ |\n\
+$$ |  $$ |$$ |      $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ |      \\$$$$$$  |\n\
+\\__|  \\__|\\__|      \\__|     \\__|\\__| \\_______|\\__|       \\______/\n\
+----------------------------------------------------------------------\n"};
+#ifdef SDK_VERSION_STRING
+    printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
+#endif
+    printf("%s", banner);
+}
+
+uint8_t board_get_led_pwm_off_level(void)
+{
+    return BOARD_LED_OFF_LEVEL;
+}
+
+uint8_t board_get_led_gpio_off_level(void)
+{
+    return BOARD_LED_OFF_LEVEL;
+}
+
+void board_ungate_mchtmr_at_lp_mode(void)
+{
+    /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
+    sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
+}
+
+void board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+#if BOARD_SHOW_CLOCK
+    board_print_clock_freq();
+#endif
+#if BOARD_SHOW_BANNER
+    board_print_banner();
+#endif
+}
+
+void board_delay_us(uint32_t us)
+{
+    static uint32_t gptmr_freq;
+    gptmr_channel_config_t config;
+
+    if (init_delay_flag == false) {
+        init_delay_flag = true;
+        clock_add_to_group(BOARD_DELAY_TIMER_CLK_NAME, 0);
+        gptmr_freq = clock_get_frequency(BOARD_DELAY_TIMER_CLK_NAME);
+        gptmr_channel_get_default_config(BOARD_DELAY_TIMER, &config);
+        gptmr_channel_config(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH, &config, false);
+    }
+
+    gptmr_channel_config_update_reload(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH, gptmr_freq / 1000000 * us);
+    gptmr_start_counter(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH);
+    while (!gptmr_check_status(BOARD_DELAY_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_DELAY_TIMER_CH))) {
+        __asm("nop");
+    }
+    gptmr_stop_counter(BOARD_DELAY_TIMER, BOARD_DELAY_TIMER_CH);
+    gptmr_clear_status(BOARD_DELAY_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_DELAY_TIMER_CH));
+}
+
+void board_delay_ms(uint32_t ms)
+{
+    board_delay_us(1000 * ms);
+}
+
+void board_timer_isr(void)
+{
+    if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
+        gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
+        timer_cb();
+    }
+}
+SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr);
+
+void board_timer_create(uint32_t ms, board_timer_cb cb)
+{
+    uint32_t gptmr_freq;
+    gptmr_channel_config_t config;
+
+    timer_cb = cb;
+    gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);
+
+    clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
+    gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);
+
+    config.reload = gptmr_freq / 1000 * ms;
+    gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
+    gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
+    intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);
+
+    gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
+}
+
+void board_i2c_bus_clear(I2C_Type *ptr)
+{
+    init_i2c_pins_as_gpio(ptr);
+}
+
+void board_init_i2c(I2C_Type *ptr)
+{
+}
+
+uint32_t board_init_spi_clock(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        /* SPI1 clock configure */
+        clock_add_to_group(clock_spi1, 0);
+        clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); /* 80MHz */
+
+        return clock_get_frequency(clock_spi1);
+    } else if (ptr == HPM_SPI2) {
+        /* SPI3 clock configure */
+        clock_add_to_group(clock_spi2, 0);
+        clock_set_source_divider(clock_spi2, clk_src_pll0_clk0, 5U); /* 80MHz */
+
+        return clock_get_frequency(clock_spi2);
+    } else if (ptr == HPM_SPI3) {
+        /* SPI3 clock configure */
+        clock_add_to_group(clock_spi3, 0);
+        clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */
+
+        return clock_get_frequency(clock_spi3);
+    }
+    return 0;
+}
+
+uint32_t board_init_lin_clock(LIN_Type *ptr)
+{
+    if (ptr == HPM_LIN0) {
+        clock_add_to_group(clock_lin0, 0);
+        clock_set_source_divider(clock_lin0, clk_src_pll0_clk0, 20U); /* 20MHz */
+
+        return clock_get_frequency(clock_lin0);
+    }
+    return 0;
+}
+
+void board_init_gpio_pins(void)
+{
+    init_gpio_pins();
+}
+
+void board_init_spi_pins(SPI_Type *ptr)
+{
+    init_spi_pins(ptr);
+}
+
+void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
+{
+    init_spi_pins_with_gpio_as_cs(ptr);
+    gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
+                                     GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
+}
+
+void board_write_spi_cs(uint32_t pin, uint8_t state)
+{
+    gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
+}
+
+void board_init_led_pins(void)
+{
+    init_led_pins_as_gpio();
+    gpio_set_pin_output_with_initial(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, board_get_led_gpio_off_level());
+    gpio_set_pin_output_with_initial(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, board_get_led_gpio_off_level());
+    gpio_set_pin_output_with_initial(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, board_get_led_gpio_off_level());
+}
+
+void board_led_toggle(void)
+{
+#ifdef BOARD_LED_TOGGLE_RGB
+    static uint8_t i;
+    switch (i) {
+    case 1:
+        gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+        gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_ON_LEVEL);
+        gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+        break;
+
+    case 2:
+        gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+        gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+        gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_ON_LEVEL);
+        break;
+
+    case 0:
+    default:
+        gpio_write_pin(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, BOARD_R_GPIO_PIN, BOARD_LED_ON_LEVEL);
+        gpio_write_pin(BOARD_G_GPIO_CTRL, BOARD_G_GPIO_INDEX, BOARD_G_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+        gpio_write_pin(BOARD_B_GPIO_CTRL, BOARD_B_GPIO_INDEX, BOARD_B_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+        break;
+    }
+    i++;
+    i = i % 3;
+#else
+    gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+#endif
+}
+
+void board_led_write(uint8_t state)
+{
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+void board_init_usb_pins(void)
+{
+    /* set pull-up for USBx ID pin */
+    init_usb_pins();
+
+    /* configure USBx ID pin as input function */
+    gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
+}
+
+uint8_t board_get_usb_id_status(void)
+{
+    return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN);
+}
+
+void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level)
+{
+}
+
+void board_init_pmp(void)
+{
+    uint32_t start_addr;
+    uint32_t end_addr;
+    uint32_t length;
+    pmp_entry_t pmp_entry[16];
+    uint8_t index = 0;
+
+    /* Init noncachable memory */
+    extern uint32_t __noncacheable_start__[];
+    extern uint32_t __noncacheable_end__[];
+    start_addr = (uint32_t)__noncacheable_start__;
+    end_addr = (uint32_t)__noncacheable_end__;
+    length = end_addr - start_addr;
+    if (length > 0) {
+        /* Ensure the address and the length are power of 2 aligned */
+        assert((length & (length - 1U)) == 0U);
+        assert((start_addr & (length - 1U)) == 0U);
+        pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
+        pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
+        pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
+        pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
+        index++;
+    }
+
+    /* Init share memory */
+    extern uint32_t __share_mem_start__[];
+    extern uint32_t __share_mem_end__[];
+    start_addr = (uint32_t)__share_mem_start__;
+    end_addr = (uint32_t)__share_mem_end__;
+    length = end_addr - start_addr;
+    if (length > 0) {
+        /* Ensure the address and the length are power of 2 aligned */
+        assert((length & (length - 1U)) == 0U);
+        assert((start_addr & (length - 1U)) == 0U);
+        pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
+        pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
+        pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
+        pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
+        index++;
+    }
+
+    pmp_config(&pmp_entry[0], index);
+}
+
+void board_init_clock(void)
+{
+    uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
+    if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
+        /* Configure the External OSC ramp-up time: ~9ms */
+        pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
+
+        /* Select clock setting preset1 */
+        sysctl_clock_set_preset(HPM_SYSCTL, 2);
+    }
+    /* Add most Clocks to group 0 */
+    /* not open uart clock in this API, uart should configure pin function before opening clock */
+    clock_add_to_group(clock_cpu0, 0);
+    clock_add_to_group(clock_ahbp, 0);
+    clock_add_to_group(clock_axic, 0);
+    clock_add_to_group(clock_axis, 0);
+
+    clock_add_to_group(clock_mchtmr0, 0);
+    clock_add_to_group(clock_xpi0, 0);
+    clock_add_to_group(clock_gptmr0, 0);
+    clock_add_to_group(clock_gptmr1, 0);
+    clock_add_to_group(clock_gptmr2, 0);
+    clock_add_to_group(clock_gptmr3, 0);
+    clock_add_to_group(clock_i2c0, 0);
+    clock_add_to_group(clock_i2c1, 0);
+    clock_add_to_group(clock_i2c2, 0);
+    clock_add_to_group(clock_i2c3, 0);
+    clock_add_to_group(clock_lin0, 0);
+    clock_add_to_group(clock_lin1, 0);
+    clock_add_to_group(clock_lin2, 0);
+    clock_add_to_group(clock_lin3, 0);
+    clock_add_to_group(clock_spi0, 0);
+    clock_add_to_group(clock_spi1, 0);
+    clock_add_to_group(clock_spi2, 0);
+    clock_add_to_group(clock_spi3, 0);
+    clock_add_to_group(clock_can0, 0);
+    clock_add_to_group(clock_can1, 0);
+    clock_add_to_group(clock_can2, 0);
+    clock_add_to_group(clock_can3, 0);
+    clock_add_to_group(clock_ptpc, 0);
+    clock_add_to_group(clock_ref0, 0);
+    clock_add_to_group(clock_ref1, 0);
+    clock_add_to_group(clock_watchdog0, 0);
+    clock_add_to_group(clock_sdp, 0);
+    clock_add_to_group(clock_xdma, 0);
+    clock_add_to_group(clock_ram0, 0);
+    clock_add_to_group(clock_usb0, 0);
+    clock_add_to_group(clock_kman, 0);
+    clock_add_to_group(clock_gpio, 0);
+    clock_add_to_group(clock_mbx0, 0);
+    clock_add_to_group(clock_hdma, 0);
+    clock_add_to_group(clock_rng, 0);
+    clock_add_to_group(clock_mot0, 0);
+    clock_add_to_group(clock_mot1, 0);
+    clock_add_to_group(clock_mot2, 0);
+    clock_add_to_group(clock_mot3, 0);
+    clock_add_to_group(clock_acmp, 0);
+    clock_add_to_group(clock_msyn, 0);
+    clock_add_to_group(clock_lmm0, 0);
+    clock_add_to_group(clock_lmm1, 0);
+
+    clock_add_to_group(clock_adc0, 0);
+    clock_add_to_group(clock_adc1, 0);
+    clock_add_to_group(clock_adc2, 0);
+
+    clock_add_to_group(clock_dac0, 0);
+    clock_add_to_group(clock_dac1, 0);
+
+    clock_add_to_group(clock_tsns, 0);
+    clock_add_to_group(clock_crc0, 0);
+    clock_add_to_group(clock_sdm0, 0);
+
+    /* Connect Group0 to CPU0 */
+    clock_connect_group_to_cpu(0, 0);
+
+    /* Add the CPU1 clock to Group1 */
+    clock_add_to_group(clock_mchtmr1, 1);
+
+    /* Connect Group1 to CPU1 */
+    clock_connect_group_to_cpu(1, 1);
+
+    /* Bump up DCDC voltage to 1275mv */
+    pcfg_dcdc_set_voltage(HPM_PCFG, 1275);
+
+    /* Configure CPU to 600MHz, AXI/AHB to 200MHz */
+    sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clk_src_pll1_clk0, 1, 3, 3);
+    /* Connect CAN2/CAN3 to pll0clk0*/
+    clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1);
+    clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1);
+
+    /* Configure PLL1_CLK0 Post Divider to 1 */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0);
+    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000);
+    clock_update_core_clock();
+
+    /* Configure AHB to 200MHz */
+    clock_set_source_divider(clock_ahb, clk_src_pll1_clk1, 2);
+
+    /* Configure mchtmr to 24MHz */
+    clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
+    clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);
+}
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, 0);
+        clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr0);
+    }
+    else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, 0);
+        clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr1);
+    }
+    else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, 0);
+        clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr2);
+    }
+    else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, 0);
+        clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr3);
+    }
+    else {
+        /* Invalid instance */
+    }
+}
+
+uint32_t board_init_adc12_clock(ADC16_Type *ptr)
+{
+    uint32_t freq = 0;
+    switch ((uint32_t)ptr) {
+    case HPM_ADC0_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc0);
+        break;
+    case HPM_ADC1_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc1, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc1);
+        break;
+    case HPM_ADC2_BASE:
+        /* Configure the ADC clock to 200MHz */
+        clock_set_adc_source(clock_adc2, clk_adc_src_ana0);
+        clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U);
+        freq = clock_get_frequency(clock_adc2);
+        break;
+    default:
+        /* Invalid ADC instance */
+        break;
+    }
+
+    return freq;
+}
+
+uint32_t board_init_adc16_clock(ADC16_Type *ptr)
+{
+    return 0;
+}
+
+uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_DAC0) {
+        if (clk_src_ahb == true) {
+            /* Configure the DAC clock to 133MHz */
+            clock_set_dac_source(clock_dac0, clk_dac_src_ahb0);
+        } else {
+            /* Configure the DAC clock to 166MHz */
+            clock_set_dac_source(clock_dac0, clk_dac_src_ana3);
+            clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2);
+        }
+
+        freq = clock_get_frequency(clock_dac0);
+    }
+
+    return freq;
+}
+
+void board_init_can(MCAN_Type *ptr)
+{
+    init_can_pins(ptr);
+}
+
+uint32_t board_init_can_clock(MCAN_Type *ptr)
+{
+    uint32_t freq = 0;
+    if (ptr == HPM_MCAN0) {
+        /* Set the CAN0 peripheral clock to 8MHz */
+        clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5);
+        freq = clock_get_frequency(clock_can0);
+    } else if (ptr == HPM_MCAN1) {
+        /* Set the CAN1 peripheral clock to 8MHz */
+        clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5);
+        freq = clock_get_frequency(clock_can1);
+    } else if (ptr == HPM_MCAN2) {
+        /* Set the CAN2 peripheral clock to 8MHz */
+        clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 5);
+        freq = clock_get_frequency(clock_can2);
+    } else if (ptr == HPM_MCAN3) {
+        /* Set the CAN2 peripheral clock to 8MHz */
+        clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 5);
+        freq = clock_get_frequency(clock_can3);
+    } else {
+        /* Invalid CAN instance */
+    }
+    return freq;
+}
+
+void board_init_adc16_pins(void)
+{
+    init_adc_pins();
+}
+
+void board_init_rgb_pwm_pins(void)
+{
+    init_led_pins_as_pwm();
+}
+
+void board_disable_output_rgb_led(uint8_t color)
+{
+    switch (color) {
+    case BOARD_RGB_RED:
+        pwm_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
+        break;
+    case BOARD_RGB_GREEN:
+        pwm_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
+        break;
+    case BOARD_RGB_BLUE:
+        pwm_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
+        break;
+    default:
+        while (1) {
+            ;
+        }
+    }
+}
+
+void board_enable_output_rgb_led(uint8_t color)
+{
+    switch (color) {
+    case BOARD_RGB_RED:
+        pwm_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT);
+        break;
+    case BOARD_RGB_GREEN:
+        pwm_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT);
+        break;
+    case BOARD_RGB_BLUE:
+        pwm_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT);
+        break;
+    default:
+        while (1) {
+            ;
+        }
+    }
+}
+void board_init_dac_pins(DAC_Type *ptr)
+{
+    init_dac_pins(ptr);
+}
+
+uint32_t board_init_uart_clock(UART_Type *ptr)
+{
+    uint32_t freq = 0U;
+    if (ptr == HPM_UART0) {
+        clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 6);
+        clock_add_to_group(clock_uart0, 0);
+        freq = clock_get_frequency(clock_uart0);
+    } else if (ptr == HPM_UART1) {
+        clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 6);
+        clock_add_to_group(clock_uart1, 0);
+        freq = clock_get_frequency(clock_uart1);
+    } else if (ptr == HPM_UART2) {
+        clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 6);
+        clock_add_to_group(clock_uart2, 0);
+        freq = clock_get_frequency(clock_uart2);
+    } else if (ptr == HPM_UART6) {
+        clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 6);
+        clock_add_to_group(clock_uart6, 0);
+        freq = clock_get_frequency(clock_uart6);
+    } else {
+        /* Not supported */
+    }
+    return freq;
+}

bsp/hpmicro/hpm6200evk/board/board.h

@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _HPM_BOARD_H
+#define _HPM_BOARD_H
+#include <stdio.h>
+#include "hpm_common.h"
+#include "hpm_clock_drv.h"
+#include "hpm_soc.h"
+#include "hpm_soc_feature.h"
+#include "pinmux.h"
+#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
+#include "hpm_debug_console.h"
+#endif
+
+#define BOARD_NAME "hpm6200evk"
+#define BOARD_UF2_SIGNATURE (0x0A4D5048UL)
+
+#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE
+
+/* dma section */
+#define BOARD_APP_XDMA HPM_XDMA
+#define BOARD_APP_HDMA HPM_HDMA
+#define BOARD_APP_XDMA_IRQ IRQn_XDMA
+#define BOARD_APP_HDMA_IRQ IRQn_HDMA
+#define BOARD_APP_DMAMUX HPM_DMAMUX
+
+/* uart section */
+#ifndef BOARD_RUNNING_CORE
+#define BOARD_RUNNING_CORE HPM_CORE0
+#endif
+#ifndef BOARD_APP_UART_BASE
+#define BOARD_APP_UART_BASE HPM_UART0
+#define BOARD_APP_UART_IRQ  IRQn_UART0
+#else
+#ifndef BOARD_APP_UART_IRQ
+#warning no IRQ specified for applicaiton uart
+#endif
+#endif
+
+#define BOARD_APP_UART_BAUDRATE (115200UL)
+#define BOARD_APP_UART_CLK_NAME clock_uart0
+#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX
+#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX
+
+#ifndef BOARD_CONSOLE_TYPE
+#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
+#endif
+
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
+#ifndef BOARD_CONSOLE_BASE
+#if BOARD_RUNNING_CORE == HPM_CORE0
+#define BOARD_CONSOLE_BASE HPM_UART0
+#define BOARD_CONSOLE_CLK_NAME clock_uart0
+#else
+#define BOARD_CONSOLE_BASE HPM_UART2
+#define BOARD_CONSOLE_CLK_NAME clock_uart2
+#endif
+#endif
+#define BOARD_CONSOLE_BAUDRATE (115200UL)
+#endif
+
+#define BOARD_FREEMASTER_UART_BASE HPM_UART0
+#define BOARD_FREEMASTER_UART_IRQ IRQn_UART0
+#define BOARD_FREEMASTER_UART_CLK_NAME clock_uart0
+
+/* sdm section */
+#define BOARD_SDM HPM_SDM
+#define BOARD_SDM_IRQ IRQn_SDFM
+#define BOARD_SDM_CHANNEL 3
+#define BOARD_SDM_TRGM                     HPM_TRGM3
+#define BOARD_SDM_TRGM_GPTMR               HPM_GPTMR3
+#define BOARD_SDM_TRGM_GPTMR_CH            2
+#define BOARD_SDM_TRGM_INPUT_SRC           HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2
+#define BOARD_SDM_TRGM_OUTPUT_DST          HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15
+
+/* lin section */
+#define BOARD_LIN             HPM_LIN0
+#define BOARD_LIN_CLK_NAME    clock_lin0
+#define BOARD_LIN_IRQ         IRQn_LIN0
+#define BOARD_LIN_BAUDRATE    (19200U)
+
+/* nor flash section */
+#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL)
+#define BOARD_FLASH_SIZE (16 * SIZE_1MB)
+
+/* i2c section */
+#define BOARD_APP_I2C_BASE HPM_I2C0
+#define BOARD_APP_I2C_IRQ IRQn_I2C0
+#define BOARD_APP_I2C_CLK_NAME clock_i2c0
+#define BOARD_APP_I2C_DMA HPM_HDMA
+#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX
+#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0
+#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
+
+/* ACMP desction */
+#define BOARD_ACMP HPM_ACMP
+#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1
+#define BOARD_ACMP_IRQ IRQn_ACMP_1
+#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */
+#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */
+
+/* dma section */
+#define BOARD_APP_XDMA HPM_XDMA
+#define BOARD_APP_HDMA HPM_HDMA
+#define BOARD_APP_XDMA_IRQ IRQn_XDMA
+#define BOARD_APP_HDMA_IRQ IRQn_HDMA
+#define BOARD_APP_DMAMUX HPM_DMAMUX
+
+/* gptmr section */
+#define BOARD_GPTMR HPM_GPTMR2
+#define BOARD_GPTMR_IRQ IRQn_GPTMR2
+#define BOARD_GPTMR_CHANNEL 0
+#define BOARD_GPTMR_PWM HPM_GPTMR2
+#define BOARD_GPTMR_PWM_CHANNEL 0
+#define BOARD_GPTMR_CLK_NAME clock_gptmr2
+
+
+#define BOARD_LED_GPIO_CTRL BOARD_G_GPIO_CTRL
+#define BOARD_LED_GPIO_INDEX BOARD_G_GPIO_INDEX
+#define BOARD_LED_GPIO_PIN BOARD_G_GPIO_PIN
+
+#define BOARD_LED_OFF_LEVEL 0
+#define BOARD_LED_ON_LEVEL !BOARD_LED_OFF_LEVEL
+#define BOARD_LED_TOGGLE_RGB 1
+
+#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ
+#define BOARD_APP_GPIO_PIN 2
+
+/* pinmux section */
+#define USING_GPIO0_FOR_GPIOZ
+#ifndef USING_GPIO0_FOR_GPIOZ
+#define BOARD_APP_GPIO_CTRL HPM_BGPIO
+#define BOARD_APP_GPIO_IRQ IRQn_BGPIO
+#else
+#define BOARD_APP_GPIO_CTRL HPM_GPIO0
+#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_Z
+#endif
+
+/* gpiom section */
+#define BOARD_APP_GPIOM_BASE            HPM_GPIOM
+#define BOARD_APP_GPIOM_USING_CTRL      HPM_FGPIO
+#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast
+
+/* spi section */
+#define BOARD_APP_SPI_BASE              HPM_SPI1
+#define BOARD_APP_SPI_CLK_NAME          clock_spi1
+#define BOARD_APP_SPI_IRQ               IRQn_SPI1
+#define BOARD_APP_SPI_SCLK_FREQ         (20000000UL)
+#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U)
+#define BOARD_APP_SPI_DATA_LEN_IN_BITS  (8U)
+#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX
+#define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
+#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX
+#define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1
+#define BOARD_SPI_CS_GPIO_CTRL           HPM_GPIO0
+#define BOARD_SPI_CS_PIN                 IOC_PAD_PB02
+#define BOARD_SPI_CS_ACTIVE_LEVEL        (0U)
+
+/* Flash section */
+#define BOARD_APP_XPI_NOR_XPI_BASE            (HPM_XPI0)
+#define BOARD_APP_XPI_NOR_CFG_OPT_HDR         (0xfcf90001U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000005U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)
+
+/* ADC section */
+#define BOARD_APP_ADC16_NAME "ADC0"
+#define BOARD_APP_ADC16_BASE HPM_ADC0
+#define BOARD_APP_ADC16_IRQn IRQn_ADC0
+#define BOARD_APP_ADC16_CH_1                     (1U)
+#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES     (1024U)
+#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES     (192U)
+#define BOARD_APP_ADC_PREEMPT_TRIG_LEN           (1U)
+#define BOARD_APP_ADC_SINGLE_CONV_CNT            (6)
+#define BOARD_APP_ADC_TRIG_PWMT0                 HPM_PWM0
+#define BOARD_APP_ADC_TRIG_PWMT1                 HPM_PWM1
+#define BOARD_APP_ADC_TRIG_TRGM0                 HPM_TRGM0
+#define BOARD_APP_ADC_TRIG_TRGM1                 HPM_TRGM1
+#define BOARD_APP_ADC_TRIG_PWM_SYNC              HPM_SYNT
+
+/* DAC section */
+#define BOARD_DAC_BASE       HPM_DAC0
+#define BOARD_DAC_IRQn       IRQn_DAC0
+#define BOARD_DAC_CLOCK_NAME clock_dac0
+
+/* CAN section */
+#define BOARD_APP_CAN_BASE                       HPM_MCAN0
+#define BOARD_APP_CAN_IRQn                       IRQn_CAN0
+
+/*
+ * timer for board delay
+ */
+#define BOARD_DELAY_TIMER (HPM_GPTMR3)
+#define BOARD_DELAY_TIMER_CH 0
+#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3)
+
+#define BOARD_CALLBACK_TIMER (HPM_GPTMR3)
+#define BOARD_CALLBACK_TIMER_CH 1
+#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3
+#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3)
+
+/* USB section */
+#define BOARD_USB0_ID_PORT       (HPM_GPIO0)
+#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC)
+#define BOARD_USB0_ID_GPIO_PIN   (23)
+
+/*BLDC pwm*/
+
+/*PWM define*/
+#define BOARD_BLDCPWM                     HPM_PWM0
+#define BOARD_BLDC_UH_PWM_OUTPIN         (0U)
+#define BOARD_BLDC_UL_PWM_OUTPIN         (1U)
+#define BOARD_BLDC_VH_PWM_OUTPIN         (2U)
+#define BOARD_BLDC_VL_PWM_OUTPIN         (3U)
+#define BOARD_BLDC_WH_PWM_OUTPIN         (4U)
+#define BOARD_BLDC_WL_PWM_OUTPIN         (5U)
+#define BOARD_BLDCPWM_TRGM                HPM_TRGM0
+#define BOARD_BLDCAPP_PWM_IRQ             IRQn_PWM0
+#define BOARD_BLDCPWM_CMP_INDEX_0         (0U)
+#define BOARD_BLDCPWM_CMP_INDEX_1         (1U)
+#define BOARD_BLDCPWM_CMP_INDEX_2         (2U)
+#define BOARD_BLDCPWM_CMP_INDEX_3         (3U)
+#define BOARD_BLDCPWM_CMP_INDEX_4         (4U)
+#define BOARD_BLDCPWM_CMP_INDEX_5         (5U)
+#define BOARD_BLDCPWM_CMP_TRIG_CMP        (15U)
+
+/*HALL define*/
+
+#define BOARD_BLDC_HALL_BASE                 HPM_HALL0
+#define BOARD_BLDC_HALL_TRGM                 HPM_TRGM0
+#define BOARD_BLDC_HALL_IRQ                  IRQn_HALL0
+#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC      HPM_TRGM0_INPUT_SRC_TRGM0_P8
+#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC      HPM_TRGM0_INPUT_SRC_TRGM0_P7
+#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC      HPM_TRGM0_INPUT_SRC_TRGM0_P6
+#define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV        (1000U)
+
+
+
+/*QEI*/
+
+#define BOARD_BLDC_QEI_BASE              HPM_QEI0
+#define BOARD_BLDC_QEI_IRQ               IRQn_QEI0
+#define BOARD_BLDC_QEI_TRGM              HPM_TRGM0
+#define BOARD_BLDC_QEI_TRGM_QEI_A_SRC    HPM_TRGM0_INPUT_SRC_TRGM0_P6
+#define BOARD_BLDC_QEI_TRGM_QEI_B_SRC    HPM_TRGM0_INPUT_SRC_TRGM0_P7
+#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV     (16U)
+#define BOARD_BLDC_QEI_CLOCK_SOURCE      clock_mot0
+#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV       (4000U)
+
+/*Timer define*/
+
+#define BOARD_BLDC_TMR_1MS                       HPM_GPTMR2
+#define BOARD_BLDC_TMR_CH                        0
+#define BOARD_BLDC_TMR_CMP                       0
+#define BOARD_BLDC_TMR_IRQ                       IRQn_GPTMR2
+#define BOARD_BLDC_TMR_RELOAD                    (100000U)
+
+/*adc*/
+#define BOARD_BLDC_ADC_MODULE                  ADCX_MODULE_ADC16
+#define BOARD_BLDC_ADC_U_BASE                  HPM_ADC0
+#define BOARD_BLDC_ADC_V_BASE                  HPM_ADC1
+#define BOARD_BLDC_ADC_W_BASE                  HPM_ADC2
+#define BOARD_BLDC_ADC_TRIG_FLAG               adc16_event_trig_complete
+
+#define BOARD_BLDC_ADC_CH_U                    (11U)
+#define BOARD_BLDC_ADC_CH_V                    (9U)
+#define BOARD_BLDC_ADC_CH_W                    (4U)
+#define BOARD_BLDC_ADC_IRQn                    IRQn_ADC0
+#define BOARD_BLDC_ADC_SEQ_DMA_SIZE_IN_4BYTES  (40U)
+#define BOARD_BLDC_ADC_TRG                    ADC16_CONFIG_TRG0A
+#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN        (1U)
+#define BOARD_BLDC_PWM_TRIG_CMP_INDEX          (8U)
+#define BOARD_BLDC_TRIGMUX_IN_NUM              HPM_TRGM0_INPUT_SRC_PWM0_CH8REF
+#define BOARD_BLDC_TRG_NUM                     TRGM_TRGOCFG_ADCX_PTRGI0A
+
+/*PLA*/
+#define BOARD_PLA_COUNTER   HPM_PLA0
+#define BOARD_PLA_PWM_BASE  HPM_PWM0
+#define BOARD_PLA_PWM_CLOCK_NAME clock_mot0
+#define BOARD_PLA_TRGM                HPM_TRGM0
+#define BOARD_PLA_PWM_TRG                       (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF)
+#define BOARD_PLA_IN_TRG_NUM                    (TRGM_TRGOCFG_PLA_IN0)
+#define BOARD_PLA_OUT_TRG                       (HPM_TRGM0_INPUT_SRC_PLA0_OUT0)
+#define BOARD_PLA_IO_TRG_NUM                    (TRGM_TRGOCFG_TRGM_OUT5)
+#define BOARD_PLA_PWM_CMP                       (8U)
+#define BOARD_PLA_PWM_CHN                       (8U)
+
+/* APP PWM */
+#define BOARD_APP_PWM HPM_PWM0
+#define BOARD_APP_PWM_CLOCK_NAME clock_mot0
+#define BOARD_APP_PWM_OUT1 0
+#define BOARD_APP_PWM_OUT2 1
+#define BOARD_APP_TRGM HPM_TRGM0
+#define BOARD_APP_PWM_IRQ IRQn_PWM0
+
+/* APP HRPWM */
+#define BOARD_APP_HRPWM HPM_PWM1
+#define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1
+#define BOARD_APP_HRPWM_OUT1 0
+#define BOARD_APP_HRPWM_OUT2 2
+#define BOARD_APP_HRPWM_TRGM HPM_TRGM1
+
+#define BOARD_CPU_FREQ (480000000UL)
+
+/* LED */
+#define BOARD_R_GPIO_CTRL HPM_GPIO0
+#define BOARD_R_GPIO_INDEX GPIO_DI_GPIOA
+#define BOARD_R_GPIO_PIN 27
+#define BOARD_G_GPIO_CTRL HPM_GPIO0
+#define BOARD_G_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_G_GPIO_PIN 1
+#define BOARD_B_GPIO_CTRL HPM_GPIO0
+#define BOARD_B_GPIO_INDEX GPIO_DI_GPIOB
+#define BOARD_B_GPIO_PIN 19
+
+/* RGB LED Section */
+#define BOARD_RED_PWM_IRQ IRQn_PWM3
+#define BOARD_RED_PWM HPM_PWM3
+#define BOARD_RED_PWM_OUT 7
+#define BOARD_RED_PWM_CMP 8
+#define BOARD_RED_PWM_CMP_INITIAL_ZERO true
+#define BOARD_RED_PWM_CLOCK_NAME clock_mot3
+
+#define BOARD_GREEN_PWM_IRQ IRQn_PWM1
+#define BOARD_GREEN_PWM HPM_PWM1
+#define BOARD_GREEN_PWM_OUT 1
+#define BOARD_GREEN_PWM_CMP 8
+#define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true
+#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1
+
+#define BOARD_BLUE_PWM_IRQ IRQn_PWM0
+#define BOARD_BLUE_PWM HPM_PWM0
+#define BOARD_BLUE_PWM_OUT 7
+#define BOARD_BLUE_PWM_CMP 8
+#define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true
+#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0
+
+#define BOARD_RGB_RED 0
+#define BOARD_RGB_GREEN (BOARD_RGB_RED + 1)
+#define BOARD_RGB_BLUE  (BOARD_RGB_RED + 2)
+
+#ifndef BOARD_SHOW_CLOCK
+#define BOARD_SHOW_CLOCK 1
+#endif
+#ifndef BOARD_SHOW_BANNER
+#define BOARD_SHOW_BANNER 1
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+typedef void (*board_timer_cb)(void);
+
+void board_init(void);
+void board_init_console(void);
+
+void board_init_uart(UART_Type *ptr);
+void board_init_i2c(I2C_Type *ptr);
+
+void board_init_can(MCAN_Type *ptr);
+
+void board_init_gpio_pins(void);
+void board_init_spi_pins(SPI_Type *ptr);
+void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
+void board_write_spi_cs(uint32_t pin, uint8_t state);
+uint8_t board_get_led_gpio_off_level(void);
+uint8_t board_get_led_pwm_off_level(void);
+void board_init_led_pins(void);
+void board_disable_output_rgb_led(uint8_t color);
+void board_enable_output_rgb_led(uint8_t color);
+void board_init_rgb_pwm_pins(void);
+
+void board_led_write(uint8_t state);
+void board_led_toggle(void);
+
+/* Initialize SoC overall clocks */
+void board_init_clock(void);
+
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
+
+uint32_t board_init_spi_clock(SPI_Type *ptr);
+
+uint32_t board_init_lin_clock(LIN_Type *ptr);
+
+uint32_t board_init_adc16_clock(ADC16_Type *ptr);
+
+uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb);
+
+void board_init_adc16_pins(void);
+
+void board_init_dac_pins(DAC_Type *ptr);
+
+uint32_t board_init_can_clock(MCAN_Type *ptr);
+
+void board_init_usb_pins(void);
+void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
+uint8_t board_get_usb_id_status(void);
+
+
+/*
+ * @brief Initialize PMP and PMA for but not limited to the following purposes:
+ *      -- non-cacheable memory initialization
+ */
+void board_init_pmp(void);
+
+void board_delay_us(uint32_t us);
+void board_delay_ms(uint32_t ms);
+
+void board_timer_create(uint32_t ms, board_timer_cb cb);
+void board_ungate_mchtmr_at_lp_mode(void);
+
+/* Initialize the UART clock */
+uint32_t board_init_uart_clock(UART_Type *ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _HPM_BOARD_H */

bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/boards/hpm6200evk.cfg

@@ -0,0 +1,33 @@
+# Copyright 2023 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
+
+proc init_clock {} {
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+    echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+    init_clock
+}
+
+$_TARGET0 configure -event gdb-attach {
+    reset halt
+}

bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg

@@ -0,0 +1,11 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 8000
+adapter srst delay 500
+
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft2232.cfg

@@ -0,0 +1,15 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0208 0x020b
+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
+

bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/ft232.cfg

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6014
+
+ftdi_layout_init 0x0018 0x001b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/jlink.cfg

@@ -0,0 +1,11 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/jlink.cfg]
+
+transport select jtag
+reset_config srst_only

bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+reset_config srst_only
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x010b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800

bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-dual-core.cfg → bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-dual-core.cfg

@@ -3,7 +3,7 @@
 #
 
 
-set _CHIP hpm6750
+set _CHIP hpm6280
 set _CPUTAPID 0x1000563D
 jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
 
@@ -28,7 +28,7 @@ proc dmi_write_memory {addr value} {
 }
 
 proc dmi_read_memory {addr} {
-    set sbcs [expr 0x100000 | [dmi_read 0x38]]
+    set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
     dmi_write 0x38 ${sbcs}
     dmi_write 0x39 ${addr}
     set value [dmi_read 0x3C]
@@ -37,7 +37,7 @@ proc dmi_read_memory {addr} {
 
 proc release_core1 {} {
     # set start point for core1
-    dmi_write_memory 0xF4002C08 0x20016284
+    dmi_write_memory 0xF4002C08 0x20012588
 
     # set boot flag for core1
     dmi_write_memory 0xF4002C0C 0xC1BEF1A9
@@ -46,16 +46,16 @@ proc release_core1 {} {
     dmi_write_memory 0xF4002C00 0x1000
 }
 
-$_TARGET0 configure -event examine-end {
-    release_core1
-}
-
 set _TARGET1 $_CHIP.cpu1
 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
 
+$_TARGET1 configure -event examine-start {
+    release_core1
+}
+
 $_TARGET1 configure -event reset-deassert-pre {
-    $::_TARGET1 arp_poll
+    $::_TARGET0 arp_poll
     release_core1
 }
 

bsp/hpmicro/libraries/hpm_sdk/boards/openocd/soc/hpm6750-single-core.cfg → bsp/hpmicro/hpm6200evk/board/debug_scripts/openocd/soc/hpm6280-single-core.cfg

@@ -1,7 +1,7 @@
 # Copyright 2021 hpmicro
 # SPDX-License-Identifier: BSD-3-Clause
 
-set _CHIP hpm6750
+set _CHIP hpm6280
 set _CPUTAPID 0x1000563D
 jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
 

bsp/hpmicro/hpm6200evk/board/fal_cfg.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern const struct fal_flash_dev stm32f2_onchip_flash;
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 8*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        15*1024*1024, 1*1024*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* RT_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */

bsp/hpmicro/hpm6200evk/board/fal_flash_port.c

@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2022-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-03-09   hpmicro     First implementation
+ * 2022-08-01   hpmicro     Fixed random crashing during kvdb_init
+ * 2022-08-03   hpmicro     Improved erase speed
+ * 2023-01-31   hpmicro     Fix random crashing issue if the global interrupt is always enabled
+ *
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_FAL
+#include "fal.h"
+#include "hpm_romapi.h"
+#include "board.h"
+#include "hpm_l1c_drv.h"
+
+
+#define FAL_ENTER_CRITICAL() do {\
+        disable_global_irq(CSR_MSTATUS_MIE_MASK);\
+    }while(0)
+
+#define FAL_EXIT_CRITICAL() do {\
+        enable_global_irq(CSR_MSTATUS_MIE_MASK);\
+    }while(0)
+
+#define FAL_RAMFUNC __attribute__((section(".isr_vector")))
+
+
+/***************************************************************************************************
+ *      FAL Porting Guide
+ *
+ *      1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH
+ *         must be placed at RAM or ROM code
+ *      2. During FLASH erase/program, it is recommended to disable the interrupt, or place the
+ *         interrupt related codes to RAM
+ *
+ ***************************************************************************************************/
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static xpi_nor_config_t s_flashcfg;
+
+/**
+ * @brief FAL Flash device context
+ */
+struct fal_flash_dev nor_flash0 =
+    {
+            .name = NOR_FLASH_DEV_NAME,
+            /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */
+            .addr = NOR_FLASH_MEM_BASE,
+            .len = 8 * 1024 * 1024,
+            .blk_size = 4096,
+            .ops = { .init = init, .read = read, .write = write, .erase = erase },
+            .write_gran = 1
+    };
+
+/**
+ * @brief FAL initialization
+ *        This function probes the FLASH using the ROM API
+ */
+FAL_RAMFUNC static int init(void)
+{
+    int ret = RT_EOK;
+    xpi_nor_config_option_t cfg_option;
+    cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR;
+    cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0;
+    cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1;
+
+    FAL_ENTER_CRITICAL();
+    hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option);
+    FAL_EXIT_CRITICAL();
+    if (status != status_success)
+    {
+        ret = -RT_ERROR;
+    }
+    else
+    {
+        s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U;
+        /* update the flash chip information */
+        uint32_t sector_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+        uint32_t flash_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size);
+        nor_flash0.blk_size = sector_size;
+        nor_flash0.len = flash_size;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief FAL read function
+ *        Read data from FLASH
+ * @param offset FLASH offset
+ * @param buf Buffer to hold data read by this API
+ * @param size Size of data to be read
+ * @return actual read bytes
+ */
+FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size)
+{
+    uint32_t flash_addr = nor_flash0.addr + offset;
+    uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr);
+    uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size);
+    uint32_t aligned_size = aligned_end - aligned_start;
+    rt_base_t level = rt_hw_interrupt_disable();
+    l1c_dc_invalidate(aligned_start, aligned_size);
+    rt_hw_interrupt_enable(level);
+
+    (void) rt_memcpy(buf, (void*) flash_addr, size);
+
+    return size;
+}
+
+/**
+ * @brief Write unaligned data to the page
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size)
+{
+    hpm_stat_t status;
+
+    FAL_ENTER_CRITICAL();
+    status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size);
+    FAL_EXIT_CRITICAL();
+
+    if (status != status_success)
+    {
+        return -RT_ERROR;
+        rt_kprintf("write failed, status=%d\n", status);
+    }
+
+    return size;
+}
+
+/**
+ * @brief FAL write function
+ *        Write data to specified FLASH address
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size)
+{
+    uint32_t *src = NULL;
+    uint32_t buf_32[64];
+    uint32_t write_size;
+    size_t remaining_size = size;
+    int ret = (int)size;
+
+    uint32_t page_size;
+    rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size);
+    uint32_t offset_in_page = offset % page_size;
+    if (offset_in_page != 0)
+    {
+        uint32_t write_size_in_page = page_size - offset_in_page;
+        uint32_t write_page_size = MIN(write_size_in_page, size);
+        (void) rt_memcpy(buf_32, buf, write_page_size);
+        write_size = write_unaligned_page_data(offset, buf_32, write_page_size);
+        if (write_size < 0)
+        {
+            ret = -RT_ERROR;
+            goto write_quit;
+        }
+
+        remaining_size -= write_page_size;
+        offset += write_page_size;
+        buf += write_page_size;
+    }
+
+    while (remaining_size > 0)
+    {
+        write_size = MIN(remaining_size, sizeof(buf_32));
+        rt_memcpy(buf_32, buf, write_size);
+        src = &buf_32[0];
+
+        FAL_ENTER_CRITICAL();
+        hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src,
+                offset, write_size);
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            rt_kprintf("write failed, status=%d\n", status);
+            break;
+        }
+
+        remaining_size -= write_size;
+        buf += write_size;
+        offset += write_size;
+    }
+
+write_quit:
+    return ret;
+}
+
+/**
+ * @brief FAL erase function
+ *        Erase specified FLASH region
+ * @param offset the start FLASH address to be erased
+ * @param size size of the region to be erased
+ * @ret RT_EOK Erase operation is successful
+ * @retval -RT_ERROR Erase operation failed
+ */
+FAL_RAMFUNC static int erase(long offset, size_t size)
+{
+    uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U);
+    hpm_stat_t status;
+    int ret = (int)size;
+
+    uint32_t block_size;
+    uint32_t sector_size;
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size);
+    uint32_t erase_unit;
+    while (aligned_size > 0)
+    {
+        FAL_ENTER_CRITICAL();
+        if ((offset % block_size == 0) && (aligned_size >= block_size))
+        {
+            erase_unit = block_size;
+            status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        else
+        {
+            erase_unit = sector_size;
+            status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        offset += erase_unit;
+        aligned_size -= erase_unit;
+    }
+
+    return ret;
+}
+#endif /* RT_USING_FAL */

bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld

@@ -0,0 +1,285 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 144K;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x4000;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = 64K
+    AXI_SRAM  (wx) : ORIGIN = 0x01090000, LENGTH = 176K
+    SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > ILM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > ILM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
+
+    .heap(NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > AXI_SRAM
+
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
+    } > DLM
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+    __share_mem_start__ = ORIGIN(SHARE_RAM);
+    __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM);
+
+}

bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld

@@ -0,0 +1,244 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x10000;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 96K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x90000, LENGTH = NONCACHEABLE_SIZE
+    AXI_SRAM  (wx) : ORIGIN = 0x01084000, LENGTH = 224K
+    SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+}
+
+SECTIONS
+{
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > ILM
+
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > ILM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > AXI_SRAM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > ILM
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .sh_mem (NOLOAD) : {
+        KEEP(*(.sh_mem))
+    } > SHARE_RAM
+    __share_mem_start__ = ORIGIN(SHARE_RAM);
+    __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM);
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+     .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE (__rt_rvstack = .);
+    } > DLM
+
+    .heap (NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > DLM
+}

bsp/hpmicro/hpm6200evk/board/pinmux.c

@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2023 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*
+ * Note:
+ *   PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
+ *  besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
+ *  expected SoC function can be enabled on these IOs.
+ *
+ */
+#include "board.h"
+
+void init_uart_pins(UART_Type *ptr)
+{
+    if (ptr == HPM_UART0) {
+        HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
+        HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
+        /* PY port IO needs to configure PIOC */
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06;
+    } else if (ptr == HPM_UART1) {
+        HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD;
+        HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD;
+    } else if (ptr == HPM_UART2) {
+        HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD;
+        HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD;
+    } else if (ptr == HPM_PUART) {
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART_RXD;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART_TXD;
+    } else if (ptr == HPM_UART6) {
+        HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_UART6_RXD;
+        HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART6_TXD;
+    }
+}
+
+void init_i2c_pins_as_gpio(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+        /* I2C0 */
+        HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_GPIO_B_22;
+        HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23;
+    } else {
+        while (1) {
+        }
+    }
+}
+
+void init_i2c_pins(I2C_Type *ptr)
+{
+    if (ptr == HPM_I2C0) {
+        HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_I2C0_SCL
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_I2C0_SDA
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PB23].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    } else if (ptr == HPM_I2C3) {
+        HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA
+                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+        HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+    } else {
+        while (1) {
+        }
+    }
+}
+
+void init_sdm_pins(void)
+{
+    /* channel 3 */
+    HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_SDM0_CLK_3;
+    HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_SDM0_DAT_3;
+}
+
+void init_gpio_pins(void)
+{
+    /* configure pad setting: pull enable and pull up, schmitt trigger enable */
+    /* enable schmitt trigger to eliminate jitter of pin used as button */
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
+
+    /* Button */
+#ifdef USING_GPIO0_FOR_GPIOZ
+    HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02;
+    HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl;
+    /* PZ port IO needs to configure BIOC as well */
+    HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02;
+#endif
+}
+
+void init_spi_pins(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SPI1_CSN;
+        HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO;
+        HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    } else if (ptr == HPM_SPI2) {
+        HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN;
+        HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO;
+        HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    }
+}
+
+void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
+{
+    if (ptr == HPM_SPI1) {
+        HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_GPIO_B_02;
+        HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO;
+        HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    } else if (ptr == HPM_SPI2) {
+        HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_GPIO_C_22;
+        HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO;
+        HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI;
+        HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);;
+    }
+}
+
+void init_pins(void)
+{
+    init_uart_pins(BOARD_CONSOLE_BASE);
+}
+
+void init_gptmr_pins(GPTMR_Type *ptr)
+{
+    if (ptr == HPM_GPTMR2) {
+        HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0;
+        HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0;
+    }
+}
+
+void init_hall_trgm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06;
+    HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07;
+    HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_TRGM0_P_08;
+}
+
+void init_qei_trgm_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_TRGM0_P_06;
+    HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_TRGM0_P_07;
+}
+
+void init_butn_pins(void)
+{
+    /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */
+    /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */
+}
+
+void init_acmp_pins(void)
+{
+    /* configure to CMP1_INN5 function */
+    HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+    /* configure to ACMP_COMP_1 function */
+    HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_ACMP_COMP_1;
+}
+
+void init_pwm_pins(PWM_Type *ptr)
+{
+    if (ptr == HPM_PWM0) {
+        HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_PWM0_P_5;
+        HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_PWM0_P_3;
+        HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_PWM0_P_1;
+        HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_PWM0_P_4;
+        HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_PWM0_P_2;
+        HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_PWM0_P_0;
+    }
+}
+
+void init_hrpwm_pins(PWM_Type *ptr)
+{
+    if (ptr == HPM_PWM1) {
+        HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_PWM1_P_0;
+        HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_PWM1_P_2;
+    }
+}
+
+void init_adc_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* ADC_BUS:ADC0.INA1 */
+    HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* ADC_IW: ADC0.INA12/ADC1.INA8/ADC2.INA4 */
+    HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* ADC_IV: ADC0.INA13/ADC1.INA9/ADC2.INA5 */
+    HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* ADC_IU: ADC0.INA11/ADC1.INA7.ADC2.INA3 */
+}
+
+void init_adc_bldc_pins(void)
+{
+   HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+   HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+   HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
+}
+
+void init_usb_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23;
+    HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
+}
+
+void  init_can_pins(MCAN_Type *ptr)
+{
+    if (ptr == HPM_MCAN0) {
+        HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+
+        HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = 0x10;
+        HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = 0x810;
+        HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = 0x810;
+    }
+    if (ptr == HPM_MCAN3) {
+        HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN3_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN3_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        HPM_IOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_CAN3_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+
+        HPM_IOC->PAD[IOC_PAD_PZ03].PAD_CTL = 0x10;
+        HPM_IOC->PAD[IOC_PAD_PZ04].PAD_CTL = 0x810;
+        HPM_IOC->PAD[IOC_PAD_PZ05].PAD_CTL = 0x810;
+        /* PZ port IO needs to configure BIOC as well */
+        HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03;
+        HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04;
+        HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05;
+    }
+}
+
+void init_clk_obs_pins(void)
+{
+    /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */
+}
+
+void init_led_pins_as_gpio(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_GPIO_B_19;
+    HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_GPIO_B_01;
+    HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_GPIO_A_27;
+}
+
+void init_dac_pins(DAC_Type *ptr)
+{
+    if (ptr == HPM_DAC0) {
+        HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* DAC0.OUT */
+    } else if (ptr == HPM_DAC1) {
+        HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;  /* DAC1.OUT */
+    }
+}
+
+void init_trgmux_pins(uint32_t pin)
+{
+    /* all trgmux pin ALT_SELECT fixed to 16*/
+    HPM_IOC->PAD[pin].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17);
+}
+
+void init_pla_pins(void)
+{
+    HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_TRGM0_P_05;
+}
+
+void init_lin_pins(LIN_Type *ptr)
+{
+    /** enable open drain and pull up */
+    uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1);
+    if (ptr == HPM_LIN0) {
+        HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_LIN0_TXD;
+        HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl;
+        HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_LIN0_RXD;
+        HPM_IOC->PAD[IOC_PAD_PA11].PAD_CTL = pad_ctl;
+        HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_LIN0_TREN;
+        HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl;
+    } else if (ptr == HPM_LIN2) {
+        HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_LIN2_RXD;
+        HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl;
+        HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_LIN2_TXD;
+        HPM_IOC->PAD[IOC_PAD_PA06].PAD_CTL = pad_ctl;
+        /* missing TREN pin */
+    }
+}
+
+void init_led_pins_as_pwm(void)
+{
+    /* Blue */
+    HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PWM0_P_7;
+    /* Green */
+    HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_PWM1_P_1;
+    /* Red */
+    HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM3_P_07;
+}

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/pinmux.h → bsp/hpmicro/hpm6200evk/board/pinmux.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2022 hpmicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -7,16 +7,12 @@
 
 #ifndef HPM_PINMUX_H
 #define HPM_PINMUX_H
-#include "hpm_soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 void init_uart_pins(UART_Type *ptr);
-void init_lcd_pins(LCDC_Type *ptr);
 void init_i2c_pins(I2C_Type *ptr);
-void init_cap_pins(void);
-void init_sdram_pins(void);
 void init_gpio_pins(void);
 void init_spi_pins(SPI_Type *ptr);
 void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
@@ -24,30 +20,23 @@ void init_pins(void);
 void init_gptmr_pins(GPTMR_Type *ptr);
 void init_hall_trgm_pins(void);
 void init_qei_trgm_pins(void);
-void init_i2s_pins(I2S_Type *ptr);
-void init_dao_pins(void);
-void init_pdm_pins(void);
-void init_vad_pins(void);
-void init_cam_pins(CAM_Type *ptr);
-void init_fpga_power_pins(void);
 void init_butn_pins(void);
 void init_acmp_pins(void);
-void init_enet_pins(ENET_Type *ptr);
 void init_pwm_pins(PWM_Type *ptr);
+void init_hrpwm_pins(PWM_Type *ptr);
 void init_adc_pins(void);
-void init_usb_pins(USB_Type *ptr);
-void init_can_pins(CAN_Type *ptr);
-void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8);
-void init_adc12_pins(void);
-void init_adc16_pins(void);
+void init_dac_pins(DAC_Type *ptr);
+void init_usb_pins(void);
+void init_can_pins(MCAN_Type *ptr);
 void init_adc_bldc_pins(void);
-
+void init_rgb_pwm_pins(void);
 void init_i2c_pins_as_gpio(I2C_Type *ptr);
-
-void init_beep_pwm_pins(void);
-void init_led_pins_as_pwm(void);
 void init_led_pins_as_gpio(void);
+void init_led_pins_as_pwm(void);
 void init_trgmux_pins(uint32_t pin);
+void init_pla_pins(void);
+void init_lin_pins(LIN_Type *ptr);
+void init_sdm_pins(void);
 #ifdef __cplusplus
 }
 #endif

bsp/hpmicro/hpm6200evk/board/rtt_board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_mchtmr_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_manager.h"
+
+void os_tick_config(void);
+
+extern int rt_hw_uart_init(void);
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_manager_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+   gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+
+void BOARD_LED_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+
+    enable_mchtmr_irq();
+}
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_interrupt_enter();
+    rt_tick_increase();
+    rt_interrupt_leave();
+}
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    clock_cpu_delay_us(us);
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_HOT &= ~(1UL << 31);
+    HPM_PPOR->RESET_COLD |= (1UL << 31);
+
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);

bsp/hpmicro/hpm6200evk/board/rtt_board.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <drv_gpio.h>
+
+/* gpio section */
+#define APP_LED0_PIN_NUM GET_PIN(B, 19)
+#define APP_LED_ON (1)
+#define APP_LED_OFF (0)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can0"
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */

bsp/hpmicro/hpm6200evk/rtconfig.h

@@ -0,0 +1,252 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50001
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers Config */
+
+#define SOC_HPM6000
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_UART0_RX_DMA_CHANNEL 0
+#define BSP_UART0_TX_DMA_CHANNEL 1
+
+#endif

bsp/hpmicro/hpm6200evk/rtconfig.py

@@ -0,0 +1,108 @@
+# Copyright 2021-2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+CHIP_NAME='HPM6280'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+# Fallback toolchain info
+FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
+FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
+FALLBACK_TOOLCHAIN_VER='2022-04-12'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+if RTT_EXEC_PATH != None:
+    folders = RTT_EXEC_PATH.split(os.sep)
+    # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
+    if 'arm_gcc' in folders and 'platform' in folders:
+        RTT_EXEC_PATH = ''
+        for path in folders:
+            if path != 'platform':
+                RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
+            else:
+                break
+        RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
+    # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
+    if 'platform' in folders:
+        os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    ARCH_ABI = ' -mcmodel=medlow '
+    CFLAGS = ARCH_ABI  + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = CFLAGS +  ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    CFLAGS = CFLAGS + ' -std=gnu11'

bsp/hpmicro/hpm6750evk/startup/HPM6360/SConscript → bsp/hpmicro/hpm6200evk/startup/HPM6280/SConscript

@@ -12,6 +12,7 @@ src = Split('''
 
 if rtconfig.PLATFORM == 'gcc':
     src += [os.path.join('toolchains', 'gcc', 'start.S')]
+    src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
 
 CPPPATH = [cwd]
 CPPDEFINES=['D45', rtconfig.CHIP_NAME]

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/startup.c → bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 - 2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  *
  */
@@ -43,11 +43,19 @@ __attribute__((weak)) void c_startup(void)
 
     extern uint8_t __etext[];
     extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __tbss_start__[], __tbss_end__[];
+    extern uint8_t __tdata_start__[], __tdata_end__[];
     extern uint8_t __data_start__[], __data_end__[];
     extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
     extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
     extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
 
+    /* tbss section */
+    size = __tbss_end__ - __tbss_start__;
+    for (i = 0; i < size; i++) {
+        *(__tbss_start__ + i) = 0;
+    }
+
     /* bss section */
     size = __bss_end__ - __bss_start__;
     for (i = 0; i < size; i++) {
@@ -60,22 +68,28 @@ __attribute__((weak)) void c_startup(void)
         *(__noncacheable_bss_start__ + i) = 0;
     }
 
+    /* tdata section LMA: etext */
+    size = __tdata_end__ - __tdata_start__;
+    for (i = 0; i < size; i++) {
+        *(__tdata_start__ + i) = *(__etext + i);
+    }
+
     /* data section LMA: etext */
     size = __data_end__ - __data_start__;
     for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + i);
+        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
     }
 
     /* ramfunc section LMA: etext + data length */
     size = __ramfunc_end__ - __ramfunc_start__;
     for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
     }
 
     /* noncacheable init section LMA: etext + data length + ramfunc length */
     size = __noncacheable_init_end__ - __noncacheable_init_start__;
     for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
     }
 }
 

bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/port_gcc.S

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "cpuport.h"
+
+    .globl rt_hw_do_after_save_above
+    .type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+    csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, trap_entry
+    jalr    t2
+
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret

bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S → bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -16,14 +16,9 @@ _start:
     .option push
     .option norelax
     la gp, __global_pointer$
+    la tp, __thread_pointer
     .option pop
 
-#ifdef INIT_EXT_RAM_FOR_DATA
-    la t0, _stack_in_dlm
-    mv sp, t0
-    call _init_ext_ram
-#endif
-
     /* Initialize stack pointer */
     la t0, _stack
     mv sp, t0
@@ -44,7 +39,6 @@ _start:
 #endif
     /* Disable Vector mode */
     csrci CSR_MMISC_CTL, 2
-
     /* Initialize trap_entry base */
     la t0, SW_handler
     csrw mtvec, t0

bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/vectors.S

@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+.section .vector_table, "a"
+.global __vector_table
+.align 9
+
+__vector_table:
+    .weak default_isr_trap
+    .set default_isr_trap, SW_handler
+    .long default_isr_trap
+    IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
+    IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
+    IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
+    IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
+    IRQ_HANDLER 5 /* GPIO0_X IRQ handler */
+    IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */
+    IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */
+    IRQ_HANDLER 8 /* GPIO1_A IRQ handler */
+    IRQ_HANDLER 9 /* GPIO1_B IRQ handler */
+    IRQ_HANDLER 10 /* GPIO1_C IRQ handler */
+    IRQ_HANDLER 11 /* GPIO1_D IRQ handler */
+    IRQ_HANDLER 12 /* GPIO1_X IRQ handler */
+    IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */
+    IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */
+    IRQ_HANDLER 15 /* ADC0 IRQ handler */
+    IRQ_HANDLER 16 /* ADC1 IRQ handler */
+    IRQ_HANDLER 17 /* ADC2 IRQ handler */
+    IRQ_HANDLER 18 /* SDFM IRQ handler */
+    IRQ_HANDLER 19 /* DAC0 IRQ handler */
+    IRQ_HANDLER 20 /* DAC1 IRQ handler */
+    IRQ_HANDLER 21 /* ACMP[0] IRQ handler */
+    IRQ_HANDLER 22 /* ACMP[1] IRQ handler */
+    IRQ_HANDLER 23 /* ACMP[2] IRQ handler */
+    IRQ_HANDLER 24 /* ACMP[3] IRQ handler */
+    IRQ_HANDLER 25 /* SPI0 IRQ handler */
+    IRQ_HANDLER 26 /* SPI1 IRQ handler */
+    IRQ_HANDLER 27 /* SPI2 IRQ handler */
+    IRQ_HANDLER 28 /* SPI3 IRQ handler */
+    IRQ_HANDLER 29 /* UART0 IRQ handler */
+    IRQ_HANDLER 30 /* UART1 IRQ handler */
+    IRQ_HANDLER 31 /* UART2 IRQ handler */
+    IRQ_HANDLER 32 /* UART3 IRQ handler */
+    IRQ_HANDLER 33 /* UART4 IRQ handler */
+    IRQ_HANDLER 34 /* UART5 IRQ handler */
+    IRQ_HANDLER 35 /* UART6 IRQ handler */
+    IRQ_HANDLER 36 /* UART7 IRQ handler */
+    IRQ_HANDLER 37 /* CAN0 IRQ handler */
+    IRQ_HANDLER 38 /* CAN1 IRQ handler */
+    IRQ_HANDLER 39 /* CAN2 IRQ handler */
+    IRQ_HANDLER 40 /* CAN3 IRQ handler */
+    IRQ_HANDLER 41 /* PTPC IRQ handler */
+    IRQ_HANDLER 42 /* WDG0 IRQ handler */
+    IRQ_HANDLER 43 /* WDG1 IRQ handler */
+    IRQ_HANDLER 44 /* TSNS IRQ handler */
+    IRQ_HANDLER 45 /* MBX0A IRQ handler */
+    IRQ_HANDLER 46 /* MBX0B IRQ handler */
+    IRQ_HANDLER 47 /* MBX1A IRQ handler */
+    IRQ_HANDLER 48 /* MBX1B IRQ handler */
+    IRQ_HANDLER 49 /* GPTMR0 IRQ handler */
+    IRQ_HANDLER 50 /* GPTMR1 IRQ handler */
+    IRQ_HANDLER 51 /* GPTMR2 IRQ handler */
+    IRQ_HANDLER 52 /* GPTMR3 IRQ handler */
+    IRQ_HANDLER 53 /* I2C0 IRQ handler */
+    IRQ_HANDLER 54 /* I2C1 IRQ handler */
+    IRQ_HANDLER 55 /* I2C2 IRQ handler */
+    IRQ_HANDLER 56 /* I2C3 IRQ handler */
+    IRQ_HANDLER 57 /* PWM0 IRQ handler */
+    IRQ_HANDLER 58 /* HALL0 IRQ handler */
+    IRQ_HANDLER 59 /* QEI0 IRQ handler */
+    IRQ_HANDLER 60 /* PWM1 IRQ handler */
+    IRQ_HANDLER 61 /* HALL1 IRQ handler */
+    IRQ_HANDLER 62 /* QEI1 IRQ handler */
+    IRQ_HANDLER 63 /* PWM2 IRQ handler */
+    IRQ_HANDLER 64 /* HALL2 IRQ handler */
+    IRQ_HANDLER 65 /* QEI2 IRQ handler */
+    IRQ_HANDLER 66 /* PWM3 IRQ handler */
+    IRQ_HANDLER 67 /* HALL3 IRQ handler */
+    IRQ_HANDLER 68 /* QEI3 IRQ handler */
+    IRQ_HANDLER 69 /* SDP IRQ handler */
+    IRQ_HANDLER 70 /* XPI0 IRQ handler */
+    IRQ_HANDLER 71 /* XDMA IRQ handler */
+    IRQ_HANDLER 72 /* HDMA IRQ handler */
+    IRQ_HANDLER 73 /* RNG IRQ handler */
+    IRQ_HANDLER 74 /* USB0 IRQ handler */
+    IRQ_HANDLER 75 /* PSEC IRQ handler */
+    IRQ_HANDLER 76 /* PGPIO IRQ handler */
+    IRQ_HANDLER 77 /* PWDG IRQ handler */
+    IRQ_HANDLER 78 /* PTMR IRQ handler */
+    IRQ_HANDLER 79 /* PUART IRQ handler */
+    IRQ_HANDLER 80 /* FUSE IRQ handler */
+    IRQ_HANDLER 81 /* SECMON IRQ handler */
+    IRQ_HANDLER 82 /* RTC IRQ handler */
+    IRQ_HANDLER 83 /* BUTN IRQ handler */
+    IRQ_HANDLER 84 /* BGPIO IRQ handler */
+    IRQ_HANDLER 85 /* BVIO IRQ handler */
+    IRQ_HANDLER 86 /* BROWNOUT IRQ handler */
+    IRQ_HANDLER 87 /* SYSCTL IRQ handler */
+    IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */
+    IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */
+    IRQ_HANDLER 90 /* LIN0 IRQ handler */
+    IRQ_HANDLER 91 /* LIN1 IRQ handler */
+    IRQ_HANDLER 92 /* LIN2 IRQ handler */
+    IRQ_HANDLER 93 /* LIN3 IRQ handler */

bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c → bsp/hpmicro/hpm6200evk/startup/HPM6280/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 - 2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -36,12 +36,16 @@
 #define IRQ_COP                 12
 #define IRQ_HOST                13
 
+#ifdef DEBUG
+#define RT_EXCEPTION_TRACE rt_kprintf
+#else
+#define RT_EXCEPTION_TRACE(...)
+#endif
+
 typedef void (*isr_func_t)(void);
 
 static volatile rt_hw_stack_frame_t *s_stack_frame;
 
-static void rt_show_stack_frame(void);
-
 __attribute((weak)) void mchtmr_isr(void)
 {
 }
@@ -54,141 +58,167 @@ __attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1,
 {
 }
 
+void rt_show_stack_frame(void)
+{
+    RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n");
+    RT_EXCEPTION_TRACE("ra      : 0x%08x\r\n", s_stack_frame->ra);
+    RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus
+    RT_EXCEPTION_TRACE("t0      : 0x%08x\r\n", s_stack_frame->t0);
+    RT_EXCEPTION_TRACE("t1      : 0x%08x\r\n", s_stack_frame->t1);
+    RT_EXCEPTION_TRACE("t2      : 0x%08x\r\n", s_stack_frame->t2);
+    RT_EXCEPTION_TRACE("a0      : 0x%08x\r\n", s_stack_frame->a0);
+    RT_EXCEPTION_TRACE("a1      : 0x%08x\r\n", s_stack_frame->a1);
+    RT_EXCEPTION_TRACE("a2      : 0x%08x\r\n", s_stack_frame->a2);
+    RT_EXCEPTION_TRACE("a3      : 0x%08x\r\n", s_stack_frame->a3);
+    RT_EXCEPTION_TRACE("a4      : 0x%08x\r\n", s_stack_frame->a4);
+    RT_EXCEPTION_TRACE("a5      : 0x%08x\r\n", s_stack_frame->a5);
+#ifndef __riscv_32e
+    RT_EXCEPTION_TRACE("a6      : 0x%08x\r\n", s_stack_frame->a6);
+    RT_EXCEPTION_TRACE("a7      : 0x%08x\r\n", s_stack_frame->a7);
+    RT_EXCEPTION_TRACE("t3      : 0x%08x\r\n", s_stack_frame->t3);
+    RT_EXCEPTION_TRACE("t4      : 0x%08x\r\n", s_stack_frame->t4);
+    RT_EXCEPTION_TRACE("t5      : 0x%08x\r\n", s_stack_frame->t5);
+    RT_EXCEPTION_TRACE("t6      : 0x%08x\r\n", s_stack_frame->t6);
+#endif
+}
+
 uint32_t exception_handler(uint32_t cause, uint32_t epc)
 {
     /* Unhandled Trap */
     uint32_t mdcause = read_csr(CSR_MDCAUSE);
     uint32_t mtval = read_csr(CSR_MTVAL);
+    rt_uint32_t mscratch = read_csr(0x340);
+
+    s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
+    rt_show_stack_frame();
+
     switch (cause)
     {
     case MCAUSE_INSTR_ADDR_MISALIGNED:
-        rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
         break;
     case MCAUSE_INSTR_ACCESS_FAULT:
-        rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
+        RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
         switch (mdcause & 0x07)
         {
         case 1:
-            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
             break;
         case 3:
-            rt_kprintf("mdcause: BUS error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
             break;
         case 4:
-            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
             break;
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     case MCAUSE_ILLEGAL_INSTR:
-        rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
         switch (mdcause & 0x07)
         {
         case 0:
-            rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
+            RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
             break;
         case 1:
-            rt_kprintf("mdcause: FP disabled exception \r\n");
+            RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: ACE disabled exception \r\n");
+            RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n");
             break;
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     case MCAUSE_BREAKPOINT:
-        rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
         break;
     case MCAUSE_LOAD_ADDR_MISALIGNED:
-        rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
         break;
     case MCAUSE_LOAD_ACCESS_FAULT:
-        rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
+        RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
         switch (mdcause & 0x07)
         {
         case 1:
-            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
             break;
         case 3:
-            rt_kprintf("mdcause: BUS error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
             break;
         case 4:
-            rt_kprintf("mdcause: Misaligned access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
             break;
         case 5:
-            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
             break;
         case 6:
-            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
             break;
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
-        rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc);
+        RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc);
         break;
     case MCAUSE_STORE_AMO_ACCESS_FAULT:
-        rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc);
+        RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc);
         switch (mdcause & 0x07)
         {
         case 1:
-            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
             break;
         case 3:
-            rt_kprintf("mdcause: BUS error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
             break;
         case 4:
-            rt_kprintf("mdcause: Misaligned access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
             break;
         case 5:
-            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
             break;
         case 6:
-            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
             break;
         case 7:
-            rt_kprintf("mdcause: PMA NAMO exception \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n");
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     default:
-        rt_kprintf("Unknown exception happened, cause=%d\n", cause);
+        RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause);
         break;
     }
 
-    rt_show_stack_frame();
-    while (1)
-    {
+    rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra);
+    while(1) {
     }
 }
 
-void trap_entry(rt_hw_stack_frame_t *stack_frame);
+void trap_entry(void);
 
-void trap_entry(rt_hw_stack_frame_t *stack_frame)
+void trap_entry(void)
 {
     uint32_t mcause = read_csr(CSR_MCAUSE);
     uint32_t mepc = read_csr(CSR_MEPC);
     uint32_t mstatus = read_csr(CSR_MSTATUS);
 
-    s_stack_frame = stack_frame;
-
 #if SUPPORT_PFT_ARCH
     uint32_t mxstatus = read_csr(CSR_MXSTATUS);
 #endif
@@ -272,25 +302,3 @@ void trap_entry(rt_hw_stack_frame_t *stack_frame)
     write_fcsr(fcsr);
 #endif
 }
-
-static void rt_show_stack_frame(void)
-{
-    rt_kprintf("Stack frame:\r\n----------------------------------------\r\n");
-    rt_kprintf("ra      : 0x%08x\r\n", s_stack_frame->ra);
-    rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS));
-    rt_kprintf("t0      : 0x%08x\r\n", s_stack_frame->t0);
-    rt_kprintf("t1      : 0x%08x\r\n", s_stack_frame->t1);
-    rt_kprintf("t2      : 0x%08x\r\n", s_stack_frame->t2);
-    rt_kprintf("a0      : 0x%08x\r\n", s_stack_frame->a0);
-    rt_kprintf("a1      : 0x%08x\r\n", s_stack_frame->a1);
-    rt_kprintf("a2      : 0x%08x\r\n", s_stack_frame->a2);
-    rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
-    rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
-    rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
-    rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
-    rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
-    rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
-    rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
-    rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
-    rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
-}

bsp/hpmicro/hpm6200evk/startup/SConscript

@@ -0,0 +1,13 @@
+# for module compiling
+import os
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+
+objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
+ASFLAGS = ' -I' + cwd
+
+Return('objs')

bsp/hpmicro/hpm6300evk/.config

@@ -0,0 +1,1026 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# CONFIG_RT_USING_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_RT_USING_HW_ATOMIC is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+CONFIG_RT_USING_LEGACY=y
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+# CONFIG_RT_USING_KTIME is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HPM6000=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_SDXC is not set
+# CONFIG_BSP_USING_GPTMR is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_FEMC is not set
+# CONFIG_INIT_EXT_RAM_FOR_DATA is not set
+# CONFIG_BSP_USING_XPI_FLASH is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_USB is not set
+# CONFIG_BSP_USING_WDG is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_ADC is not set

bsp/hpmicro/hpm6300evk/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/hpmicro/hpm6300evk/README.md

@@ -0,0 +1,116 @@
+# HPMicro HPM6300EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides brief introduction of the BSP (board support package) for the HPM6300EVK development board.
+
+The document consists of the following parts:
+
+- HPM6300EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM6300EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| Ethernet                 | √           | Supported by RT-Thread Industry IO    |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6300EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6300evk)

bsp/hpmicro/hpm6300evk/README_zh.md

@@ -0,0 +1,115 @@
+# 先楫 HPM6300EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM6300EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM6300EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+ HPM6300EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           | 由RT-Thread Industry IO扩展板提供支持    |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6300EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6300evk)

bsp/hpmicro/hpm6300evk/SConscript

@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hpmicro/hpm6300evk/SConstruct

@@ -0,0 +1,75 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hpm_library = 'hpm_sdk'
+rtconfig.BSP_LIBRARY_TYPE = hpm_library
+
+# include soc
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
+
+# include components
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6750evkmini/SConscript → bsp/hpmicro/hpm6300evk/applications/SConscript

@@ -9,6 +9,6 @@ src = Glob('*.c')
 CPPDEFINES=[]
 CPPPATH = [cwd]
 
-group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
 
 Return('group')

bsp/hpmicro/hpm6300evk/applications/main.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+#include <drv_gpio.h>
+
+void thread_entry(void *arg);
+
+
+int main(void)
+{
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+
+void thread_entry(void *arg)
+{
+    rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while(1){
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON);
+        rt_thread_mdelay(500);
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}

bsp/hpmicro/hpm6300evk/board/Kconfig

@@ -0,0 +1,256 @@
+menu "Hardware Drivers Config"
+
+config SOC_HPM6000
+    bool
+    select SOC_SERIES_HPM6000
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN if BSP_USING_GPIO
+        default n
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART0
+                bool "Enable UART0 (Debugger)"
+                default y
+                if BSP_USING_UART0
+                    config BSP_UART0_RX_USING_DMA
+                        bool "Enable UART0 RX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_TX_USING_DMA
+                        bool "Enable UART0 TX DMA"
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART0_RX_DMA_CHANNEL
+                        int "Set UART0 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART0_TX_DMA_CHANNEL
+                        int "Set UART0 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART0_RX_BUFSIZE
+                        int "Set UART0 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART0_TX_BUFSIZE
+                        int "Set UART0 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+                menuconfig BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+                if BSP_USING_UART2
+                    config BSP_UART2_RX_USING_DMA
+                        bool "Enable UART2 RX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_TX_USING_DMA
+                        bool "Enable UART2 TX DMA"
+                        depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_RX_DMA_CHANNEL
+                        int "Set UART2 RX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default 0
+
+                    config BSP_UART2_TX_DMA_CHANNEL
+                        int "Set UART2 TX DMA CHANNEL"
+                        range 0 7
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default 1
+
+                    config BSP_UART2_RX_BUFSIZE
+                        int "Set UART2 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 128
+
+                    config BSP_UART2_TX_BUFSIZE
+                        int "Set UART2 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+        endif
+
+
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI if BSP_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                    default n
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                    default n
+            config BSP_USING_SPI3
+                bool "Enable SPI3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_RTC
+       bool "Enable RTC"
+       default n
+
+    menuconfig BSP_USING_ETH
+       bool "Enable Ethernet"
+       default n
+
+       select RT_USING_ETH
+       if BSP_USING_ETH
+       		choice
+		prompt "ETH"
+	    	config BSP_USING_ETH0
+	        bool "Enable ETH0"
+	   	endchoice
+       endif
+
+    menuconfig BSP_USING_SDXC
+        bool "Enable SDXC"
+        default n
+        select RT_USING_SDIO if BSP_USING_SDXC
+        if BSP_USING_SDXC
+            config BSP_USING_SDXC0
+                bool "Enable SDXC0"
+                    default n
+        endif
+
+    menuconfig BSP_USING_GPTMR
+	   	bool "Enable GPTMR"
+	   	default n
+	   	select RT_USING_HWTIMER if BSP_USING_GPTMR
+	   	if BSP_USING_GPTMR
+			config BSP_USING_GPTMR0
+	   			bool "Enable GPTMR0"
+	   			default n
+	   		config BSP_USING_GPTMR1
+	   			bool "Enable GPTMR1"
+	   			default n
+	   		config BSP_USING_GPTMR2
+	   			bool "Enable GPTMR2"
+	   			default n
+	   		config BSP_USING_GPTMR3
+	   			bool "Enable GPTMR3"
+	   			default n
+        endif
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        default n
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                    default y
+
+            config BSP_USING_I2C3
+                bool "Enable I2C3"
+                    default n
+        endif
+
+    menuconfig BSP_USING_FEMC
+       bool "Enable DRAM"
+       default y
+    menuconfig INIT_EXT_RAM_FOR_DATA
+        bool "INIT_EXT_RAM_FOR_DATA"
+        default y
+
+
+    menuconfig BSP_USING_XPI_FLASH
+    	bool "Enable XPI FLASH"
+	default n
+    	select PKG_USING_FAL if BSP_USING_XPI_FLASH
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+	default n
+
+    menuconfig BSP_USING_USB
+       bool "Enable USB"
+       default n
+       if BSP_USING_USB
+       		config BSP_USING_USB_DEVICE
+                bool "Enable USB Device"
+                    default n
+            config BSP_USING_USB_HOST
+                bool "Enable USB HOST"
+                    default n
+       endif
+
+
+     menuconfig BSP_USING_WDG
+     	bool "Enable Watchdog"
+     	default n
+     	select RT_USING_WDT if BSP_USING_WDG
+     	if BSP_USING_WDG
+     		config BSP_USING_WDG0
+     			bool "Enable WDG0"
+     			default n
+     		config BSP_USING_WDG1
+     			bool "Enable WDG1"
+     			default n
+     	endif
+
+     menuconfig BSP_USING_CAN
+     	bool "Enable CAN"
+     	default n
+     	select RT_USING_CAN if BSP_USING_CAN
+     	if BSP_USING_CAN
+     		config BSP_USING_CAN0
+     			bool "Enable CAN0"
+     			default n
+     		config BSP_USING_CAN1
+     			bool "Enable CAN1"
+     			default n
+     endif
+
+     menuconfig BSP_USING_ADC
+     	bool "Enable ADC"
+     	default n
+     	select RT_USING_ADC if BSP_USING_ADC
+     	if BSP_USING_ADC
+            menuconfig BSP_USING_ADC16
+            bool "Enable ADC16"
+            default y
+            if BSP_USING_ADC16
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default n
+                config BSP_USING_ADC1
+                    bool "Enable ADC1"
+                    default y
+                config BSP_USING_ADC2
+                    bool "Enable ADC2"
+                    default n
+            endif
+        endif
+endmenu
+
+
+
+endmenu

bsp/hpmicro/hpm6300evk/board/SConscript

@@ -0,0 +1,19 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    fal_flash_port.c
+    eth_phy_port.c
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM6360']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.c → bsp/hpmicro/hpm6300evk/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */
@@ -10,8 +10,7 @@
 #include "hpm_lcdc_drv.h"
 #include "hpm_i2c_drv.h"
 #include "hpm_gpio_drv.h"
-#include "hpm_debug_console.h"
-#include "hpm_dram_drv.h"
+#include "hpm_femc_drv.h"
 #include "pinmux.h"
 #include "hpm_pmp_drv.h"
 #include "assert.h"
@@ -21,9 +20,13 @@
 #include "hpm_pwm_drv.h"
 #include "hpm_trgm_drv.h"
 #include "hpm_pllctlv2_drv.h"
+#include "hpm_enet_drv.h"
 #include "hpm_pcfg_drv.h"
 
+#include "hpm_debug_console.h"
+
 static board_timer_cb timer_cb;
+ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag;
 
 /**
  * @brief FLASH configuration option definitions:
@@ -88,7 +91,7 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU
 
 void board_init_console(void)
 {
-#if console_type_uart == BOARD_CONSOLE_TYPE
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
     console_config_t cfg;
 
     /* Configure the UART clock to 24MHz */
@@ -107,8 +110,7 @@ void board_init_console(void)
         }
     }
 #else
-    while (1) {
-    }
+    while(1);
 #endif
 }
 
@@ -123,7 +125,7 @@ void board_print_clock_freq(void)
     printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
     printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
     printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
-    printf("dram:\t\t %luHz\n", clock_get_frequency(clock_dram));
+    printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
     printf("==============================\n");
 }
 
@@ -179,13 +181,13 @@ void board_init_sdram_pins(void)
     init_sdram_pins();
 }
 
-uint32_t board_init_dram_clock(void)
+uint32_t board_init_femc_clock(void)
 {
-    clock_add_to_group(clock_dram, 0);
-    /* Configure the SDRAM to 133MHz */
-    clock_set_source_divider(clock_dram, clk_src_pll0_clk1, 2U);
+    clock_add_to_group(clock_femc, 0);
+    /* Configure the SDRAM to 166MHz */
+    clock_set_source_divider(clock_femc, clk_src_pll0_clk1, 2U);
 
-    return clock_get_frequency(clock_dram);
+    return clock_get_frequency(clock_femc);
 }
 
 void board_delay_us(uint32_t us)
@@ -257,18 +259,6 @@ void board_init_spi_pins(SPI_Type *ptr)
     init_spi_pins(ptr);
 }
 
-void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
-{
-    init_spi_pins_with_gpio_as_cs(ptr);
-    gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
-                                    GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
-}
-
-void board_write_spi_cs(uint32_t pin, uint8_t state)
-{
-    gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
-}
-
 void board_init_led_pins(void)
 {
     init_led_pins();
@@ -338,6 +328,7 @@ void board_init_pmp(void)
 void board_init_clock(void)
 {
     uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
+    hpm_core_clock = cpu0_freq;
     if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
         /* Configure the External OSC ramp-up time: ~9ms */
         pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U);
@@ -352,17 +343,13 @@ void board_init_clock(void)
     clock_add_to_group(clock_axis, 0);
 
     clock_add_to_group(clock_mchtmr0, 0);
-    clock_add_to_group(clock_dram, 0);
+    clock_add_to_group(clock_femc, 0);
     clock_add_to_group(clock_xpi0, 0);
     clock_add_to_group(clock_xpi1, 0);
     clock_add_to_group(clock_gptmr0, 0);
     clock_add_to_group(clock_gptmr1, 0);
     clock_add_to_group(clock_gptmr2, 0);
     clock_add_to_group(clock_gptmr3, 0);
-    clock_add_to_group(clock_uart0, 0);
-    clock_add_to_group(clock_uart1, 0);
-    clock_add_to_group(clock_uart2, 0);
-    clock_add_to_group(clock_uart3, 0);
     clock_add_to_group(clock_i2c0, 0);
     clock_add_to_group(clock_i2c1, 0);
     clock_add_to_group(clock_i2c2, 0);
@@ -410,13 +397,25 @@ void board_init_clock(void)
 
     /* Connect Group0 to CPU0 */
     clock_connect_group_to_cpu(0, 0);
-    /* Configure CPU0 to 480MHz */
+    /*
+     * Configure CPU0 to 480MHz
+     *
+     *  NOTE: The PLL2 is disabled by default, and it will be enabled automatically if
+     *        it is required by any nodes.
+     *  Here the PLl2 clock is enabled after switching CPU clock source to it
+     */
     clock_set_source_divider(clock_cpu0, clk_src_pll1_clk0, 1);
+    /* Configure PLL1_CLK0 Post Divider to 1.2 */
+    pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1);
+    /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency  =- 576MHz / 1.2 = 480MHz */
+    pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000);
 
     clock_update_core_clock();
+
+    clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 46); /* config clock_aud1 for 44100*n sample rate */
 }
 
-uint32_t board_init_adc12_clock(ADC16_Type *ptr)
+uint32_t board_init_adc16_clock(ADC16_Type *ptr)
 {
     uint32_t freq = 0;
     switch ((uint32_t) ptr) {
@@ -461,10 +460,6 @@ uint32_t board_init_i2s_clock(I2S_Type *ptr)
     return 0;
 }
 
-uint32_t board_init_adc16_clock(ADC16_Type *ptr)
-{
-    return 0;
-}
 
 uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
 {
@@ -472,7 +467,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
 
     if (ptr == HPM_DAC) {
         if (clk_src_ahb == true) {
-            /* Configure the DAC clock to 133MHz */
+            /* Configure the DAC clock to 160MHz */
             clock_set_dac_source(clock_dac0, clk_dac_src_ahb);
         } else {
             /* Configure the DAC clock to 166MHz */
@@ -508,29 +503,57 @@ uint32_t board_init_can_clock(CAN_Type *ptr)
     return freq;
 }
 
-#ifdef INIT_EXT_RAM_FOR_DATA
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
+{
+    uint32_t freq = 0;
+
+    if (ptr == HPM_GPTMR0) {
+        clock_add_to_group(clock_gptmr0, 0);
+        clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr0);
+    }
+    else if (ptr == HPM_GPTMR1) {
+        clock_add_to_group(clock_gptmr1, 0);
+        clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr1);
+    }
+    else if (ptr == HPM_GPTMR2) {
+        clock_add_to_group(clock_gptmr2, 0);
+        clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr2);
+    }
+    else if (ptr == HPM_GPTMR3) {
+        clock_add_to_group(clock_gptmr3, 0);
+        clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4);
+        freq = clock_get_frequency(clock_gptmr3);
+    }
+    else {
+        /* Invalid instance */
+    }
+}
+
 /*
  * this function will be called during startup to initialize external memory for data use
  */
 void _init_ext_ram(void)
 {
-    uint32_t dram_clk_in_hz;
+    uint32_t femc_clk_in_hz;
     board_init_sdram_pins();
-    dram_clk_in_hz = board_init_dram_clock();
+    femc_clk_in_hz = board_init_femc_clock();
 
-    dram_config_t config = {0};
-    dram_sdram_config_t sdram_config = {0};
+    femc_config_t config = {0};
+    femc_sdram_config_t sdram_config = {0};
 
-    dram_default_config(HPM_DRAM, &config);
-    config.dqs = DRAM_DQS_INTERNAL;
-    dram_init(HPM_DRAM, &config);
+    femc_default_config(HPM_FEMC, &config);
+    config.dqs = FEMC_DQS_INTERNAL;
+    femc_init(HPM_FEMC, &config);
 
-    sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4;
+    sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
     sdram_config.prescaler = 0x3;
     sdram_config.burst_len_in_byte = 8;
     sdram_config.auto_refresh_count_in_one_burst = 1;
-    sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS;
-    sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3;
+    sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
+    sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
 
     sdram_config.precharge_to_act_in_ns = 18;   /* Trp */
     sdram_config.act_to_rw_in_ns = 18;          /* Trcd */
@@ -543,7 +566,7 @@ void _init_ext_ram(void)
     sdram_config.refresh_to_refresh_in_ns = 66;     /* Trfc/Trc */
     sdram_config.act_to_act_in_ns = 12;             /* Trrd */
     sdram_config.idle_timeout_in_ns = 6;
-    sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED;
+    sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
 
     sdram_config.cs = BOARD_SDRAM_CS;
     sdram_config.base_address = BOARD_SDRAM_ADDRESS;
@@ -554,13 +577,14 @@ void _init_ext_ram(void)
     sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
     sdram_config.delay_cell_value = 29;
 
-    dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config);
+    femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
 }
-#endif
+
 
 void board_init_sd_pins(SDXC_Type *ptr)
 {
     init_sdxc_pins(ptr, false);
+    init_sdxc_card_detection_pin(ptr);
 }
 
 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq)
@@ -612,6 +636,11 @@ void board_sd_switch_pins_to_1v8(SDXC_Type *ptr)
     /* This feature is not supported */
 }
 
+void board_sd_power_switch(SDXC_Type *ptr, bool on_off)
+{
+    /* This feature is not supported */
+}
+
 bool board_sd_detect_card(SDXC_Type *ptr)
 {
     return sdxc_is_card_inserted(ptr);
@@ -643,6 +672,9 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
     } else {
         return status_invalid_argument;
     }
+
+    enet_rmii_enable_clock(ptr, internal);
+
     return status_success;
 }
 
@@ -658,6 +690,11 @@ hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
     return status_success;
 }
 
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
+{
+    return status_success;
+}
+
 void board_init_dac_pins(DAC_Type *ptr)
 {
    init_dac_pins(ptr);
@@ -668,15 +705,45 @@ uint32_t board_init_uart_clock(UART_Type *ptr)
     uint32_t freq = 0U;
     if (ptr == HPM_UART0) {
         clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
+        clock_add_to_group(clock_uart0, 0);
         freq = clock_get_frequency(clock_uart0);
     } else if (ptr == HPM_UART1) {
         clock_set_source_divider(clock_uart1, clk_src_osc24m, 1);
+        clock_add_to_group(clock_uart1, 0);
         freq = clock_get_frequency(clock_uart1);
     } else if (ptr == HPM_UART2) {
         clock_set_source_divider(clock_uart2, clk_src_osc24m, 1);
+        clock_add_to_group(clock_uart2, 0);
         freq = clock_get_frequency(clock_uart2);
     } else {
         /* Not supported */
     }
     return freq;
 }
+
+uint8_t board_enet_get_dma_pbl(ENET_Type *ptr)
+{
+    return enet_pbl_16;
+}
+
+hpm_stat_t board_enet_enable_irq(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        intc_m_enable_irq(IRQn_ENET0);
+    } else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}
+
+hpm_stat_t board_enet_disable_irq(ENET_Type *ptr)
+{
+    if (ptr == HPM_ENET0) {
+        intc_m_disable_irq(IRQn_ENET0);
+    }  else {
+        return status_invalid_argument;
+    }
+
+    return status_success;
+}

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/board.h → bsp/hpmicro/hpm6300evk/board/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -41,10 +41,10 @@
 #define BOARD_APP_UART_CLK_NAME clock_uart0
 
 #ifndef BOARD_CONSOLE_TYPE
-#define BOARD_CONSOLE_TYPE console_type_uart
+#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
 #endif
 
-#if console_type_uart == BOARD_CONSOLE_TYPE
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_BASE
 #if BOARD_RUNNING_CORE == HPM_CORE0
 #define BOARD_CONSOLE_BASE HPM_UART0
@@ -80,8 +80,8 @@
 /* sdram section */
 #define BOARD_SDRAM_ADDRESS  (0x40000000UL)
 #define BOARD_SDRAM_SIZE     (32*SIZE_1MB)
-#define BOARD_SDRAM_CS       DRAM_SDRAM_CS0
-#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS
+#define BOARD_SDRAM_CS       FEMC_SDRAM_CS0
+#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS
 #define BOARD_SDRAM_REFRESH_COUNT (8192UL)
 #define BOARD_SDRAM_REFRESH_IN_MS (64UL)
 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL)
@@ -149,22 +149,18 @@
 #define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX
 #define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1
-#define BOARD_SPI_CS_GPIO_CTRL           HPM_GPIO0
-#define BOARD_SPI_CS_PIN                 IOC_PAD_PC18
-#define BOARD_SPI_CS_ACTIVE_LEVEL        (0U)
+
 
 /* Flash section */
 #define BOARD_APP_XPI_NOR_XPI_BASE            (HPM_XPI0)
 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR         (0xfcf90001U)
-#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000005U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000007U)
 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)
 
 /* i2s section */
 #define BOARD_APP_I2S_BASE HPM_I2S0
 #define BOARD_APP_I2S_DATA_LINE      (2U)
 #define BOARD_APP_I2S_CLK_NAME clock_i2s0
-#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0
-#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0
 
 /* enet section */
 #define BOARD_ENET_RMII                 HPM_ENET0
@@ -174,12 +170,30 @@
 #define BOARD_ENET_RMII                 HPM_ENET0
 #define BOARD_ENET_RMII_INT_REF_CLK     (1U)
 #define BOARD_ENET_RMII_PTP_CLOCK       (clock_ptp0)
+#define BOARD_ENET0_INF             (0U)  /* 0: RMII, 1: RGMII */
+#define BOARD_ENET0_INT_REF_CLK     (0U)
+#define BOARD_ENET0_PHY_RST_TIME    (30)
+
+
+#if BOARD_ENET0_INF
+#define BOARD_ENET0_TX_DLY          (0U)
+#define BOARD_ENET0_RX_DLY          (0U)
+#endif
+
+#if __USE_ENET_PTP
+#define BOARD_ENET0_PTP_CLOCK       (clock_ptp0)
+#endif
+
 
 /* ADC section */
 #define BOARD_APP_ADC16_NAME "ADC0"
 #define BOARD_APP_ADC16_BASE HPM_ADC0
 #define BOARD_APP_ADC16_IRQn IRQn_ADC0
-#define BOARD_APP_ADC16_CH_1                     (13U)
+#define BOARD_APP_ADC16_CH                       (13U)
+#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES     (1024U)
+#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES     (192U)
+#define BOARD_APP_ADC_PREEMPT_TRIG_LEN           (1U)
+#define BOARD_APP_ADC_SINGLE_CONV_CNT            (6)
 #define BOARD_APP_ADC_TRIG_PWMT0                 HPM_PWM0
 #define BOARD_APP_ADC_TRIG_PWMT1                 HPM_PWM1
 #define BOARD_APP_ADC_TRIG_TRGM0                 HPM_TRGM0
@@ -208,15 +222,10 @@
 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3)
 
 /* SDXC section */
-#define BOARD_APP_SDCARD_SDXC_BASE                  (HPM_SDXC0)
-#define BOARD_APP_SDCARD_SUPPORT_1V8                (0)
-#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION     (1)
-#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO  (0)
-#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO
-#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO        NULL
-#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX  0
-#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX   0
-#endif
+#define BOARD_APP_SDCARD_SDXC_BASE            (HPM_SDXC0)
+#define BOARD_APP_SDCARD_CDN_GPIO_CTRL        (HPM_GPIO0)
+#define BOARD_APP_SDCARD_CDN_GPIO_PIN         (15UL)
+#define BOARD_APP_SDCARD_SUPPORT_1V8          (0)
 
 /* USB section */
 #define BOARD_USB0_ID_PORT       (HPM_GPIO0)
@@ -328,13 +337,11 @@ void board_init_i2c(I2C_Type *ptr);
 
 void board_init_can(CAN_Type *ptr);
 
-uint32_t board_init_dram_clock(void);
+uint32_t board_init_femc_clock(void);
 
 void board_init_sdram_pins(void);
 void board_init_gpio_pins(void);
 void board_init_spi_pins(SPI_Type *ptr);
-void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
-void board_write_spi_cs(uint32_t pin, uint8_t state);
 void board_init_led_pins(void);
 
 void board_led_write(uint8_t state);
@@ -354,7 +361,7 @@ void board_init_adc16_pins(void);
 void board_init_dac_pins(DAC_Type *ptr);
 
 uint32_t board_init_can_clock(CAN_Type *ptr);
-
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
 uint32_t board_init_i2s_clock(I2S_Type *ptr);
 uint32_t board_init_pdm_clock(void);
 uint32_t board_init_dao_clock(void);
@@ -363,15 +370,19 @@ void board_init_sd_pins(SDXC_Type *ptr);
 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq);
 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr);
 bool board_sd_detect_card(SDXC_Type *ptr);
+void board_sd_power_switch(SDXC_Type *ptr, bool on_off);
 
 void board_init_usb_pins(void);
 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
 uint8_t board_get_usb_id_status(void);
 
+uint8_t    board_enet_get_dma_pbl(ENET_Type *ptr);
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
 hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);
-
+hpm_stat_t board_enet_enable_irq(ENET_Type *ptr);
+hpm_stat_t board_enet_disable_irq(ENET_Type *ptr);
 /*
  * @brief Initialize PMP and PMA for but not limited to the following purposes:
  *      -- non-cacheable memory initialization

bsp/hpmicro/hpm6300evk/board/debug_scripts/openocd/soc/hpm6360-csr.cfg

@@ -0,0 +1,50 @@
+riscv expose_csrs 262
+riscv expose_csrs 800
+riscv expose_csrs 1984
+riscv expose_csrs 1985
+riscv expose_csrs 1986
+riscv expose_csrs 1987
+riscv expose_csrs 1988
+riscv expose_csrs 1989
+riscv expose_csrs 1990
+riscv expose_csrs 1991
+riscv expose_csrs 1992
+riscv expose_csrs 1993
+riscv expose_csrs 1994
+riscv expose_csrs 1995
+riscv expose_csrs 1996
+riscv expose_csrs 1997
+riscv expose_csrs 1998
+riscv expose_csrs 1999
+riscv expose_csrs 2000
+riscv expose_csrs 2001
+riscv expose_csrs 2002
+riscv expose_csrs 2003
+riscv expose_csrs 2004
+riscv expose_csrs 2005
+riscv expose_csrs 2015
+riscv expose_csrs 2016
+riscv expose_csrs 2017
+riscv expose_csrs 2048
+riscv expose_csrs 2049
+riscv expose_csrs 2057
+riscv expose_csrs 2059
+riscv expose_csrs 2060
+riscv expose_csrs 2500
+riscv expose_csrs 2501
+riscv expose_csrs 2505
+riscv expose_csrs 2509
+riscv expose_csrs 2511
+riscv expose_csrs 2513
+riscv expose_csrs 2514
+riscv expose_csrs 2515
+riscv expose_csrs 2516
+riscv expose_csrs 2528
+riscv expose_csrs 2531
+riscv expose_csrs 2532
+riscv expose_csrs 2533
+riscv expose_csrs 2534
+riscv expose_csrs 4032
+riscv expose_csrs 4033
+riscv expose_csrs 4034
+riscv expose_csrs 4035

bsp/hpmicro/hpm6300evk/board/eth_phy_port.c

@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2021 - 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-01-11   hpmicro     First version
+ */
+
+#include "rtthread.h"
+
+#ifdef RT_USING_PHY
+#include <rtdevice.h>
+#include <rtdbg.h>
+#include "hpm_enet_drv.h"
+#include "eth_phy_port.h"
+#include "hpm_soc.h"
+#include "netif/ethernetif.h"
+#include "board.h"
+
+typedef struct
+{
+    char *mdio_name;
+    ENET_Type *instance;
+    struct eth_device *eth_dev;
+    phy_device_t *phy_dev;
+    struct rt_mdio_bus *mdio_bus;
+} eth_phy_handle_t;
+
+typedef struct
+{
+    uint8_t phy_handle_cnt;
+    eth_phy_handle_t **phy_handle;
+} eth_phy_monitor_handle_t;
+
+#ifdef BSP_USING_ETH0
+extern struct eth_device eth0_dev;
+static struct rt_mdio_bus mdio0_bus;
+static phy_device_t phy0_dev;
+static uint8_t phy0_reg_list[]= {PHY0_REG_LIST};
+
+static eth_phy_handle_t eth0_phy_handle =
+{
+    .instance  = HPM_ENET0,
+    .eth_dev   = &eth0_dev,
+    .phy_dev   = &phy0_dev,
+    .mdio_name = "MDIO0",
+    .mdio_bus  = &mdio0_bus,
+};
+#endif
+
+#ifdef BSP_USING_ETH1
+extern struct eth_device eth1_dev;
+static struct rt_mdio_bus mdio1_bus;
+static phy_device_t phy1_dev;
+static uint8_t phy1_reg_list[]= {PHY1_REG_LIST};
+
+static eth_phy_handle_t eth1_phy_handle =
+{
+    .instance     = HPM_ENET1,
+    .eth_dev      = &eth1_dev,
+    .phy_dev      = &phy1_dev,
+    .mdio_name    = "MDIO1",
+    .mdio_bus     = &mdio1_bus,
+};
+#endif
+
+static eth_phy_handle_t *s_gphys[] =
+{
+#ifdef BSP_USING_ETH0
+&eth0_phy_handle,
+#endif
+
+#ifdef BSP_USING_ETH1
+&eth1_phy_handle
+#endif
+};
+
+static uint8_t *s_gphy_reg_list[] =
+{
+#ifdef BSP_USING_ETH0
+phy0_reg_list,
+#endif
+
+#ifdef BSP_USING_ETH1
+phy1_reg_list,
+#endif
+};
+
+eth_phy_monitor_handle_t phy_monitor_handle =
+{
+    .phy_handle_cnt = ARRAY_SIZE(s_gphys),
+    .phy_handle     = s_gphys
+};
+
+static struct rt_phy_ops phy_ops;
+
+static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz)
+{
+    return PHY_STATUS_OK;
+}
+
+static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg);
+
+    return size;
+}
+
+static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+{
+    enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg,  *(uint16_t *)data);
+
+    return size;
+}
+
+static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status)
+{
+    uint16_t reg_status;
+
+    reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_BASIC_STATUS_REG_IDX]);
+
+    #if PHY_AUTO_NEGO
+        reg_status &= PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK;
+        *status = reg_status ? RT_TRUE : RT_FALSE;
+
+    #else
+        reg_status &= PHY_LINKED_STATUS_MASK;
+        *status = reg_status ? RT_TRUE : RT_FALSE;
+    #endif
+
+    return PHY_STATUS_OK;
+}
+
+static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex)
+{
+    uint16_t reg_status;
+
+    reg_status = enet_read_phy(phy->bus->hw_obj, phy->addr, phy->reg_list[PHY_STATUS_REG_IDX]);
+
+    *speed = PHY_STATUS_SPEED_100M(reg_status) ? PHY_SPEED_100M : PHY_SPEED_10M;
+    *duplex = PHY_STATUS_FULL_DUPLEX(reg_status) ? PHY_FULL_DUPLEX: PHY_HALF_DUPLEX;
+
+    return PHY_STATUS_OK;
+}
+
+static void phy_poll_status(void *parameter)
+{
+    int ret;
+    phy_info_t phy_info;
+    rt_bool_t status;
+    rt_device_t dev;
+    rt_phy_msg_t msg;
+    rt_uint32_t speed, duplex;
+    phy_device_t *phy_dev;
+    struct eth_device* eth_dev;
+    char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"};
+    enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps};
+
+    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter;
+
+    for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++)
+    {
+        eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev;
+        phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev;
+
+        phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status);
+
+        if (status)
+        {
+            phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex);
+
+            ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t));
+            if (ret != 0)
+            {
+                memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t));
+            }
+        }
+
+        if (phy_dev->phy_link != status)
+        {
+            phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN;
+            eth_device_linkchange(eth_dev, status);
+            LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n");
+            if (status == PHY_LINK_UP)
+            {
+                LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]);
+                LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex");
+                enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]);
+                enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex);
+            }
+        }
+    }
+}
+
+static void phy_detection(void *parameter)
+{
+    uint8_t detected_count = 0;
+    struct rt_phy_msg msg = {0, 0};
+    phy_device_t *phy_dev = (phy_device_t *)parameter;
+    rt_uint32_t i;
+
+    msg.reg = phy_dev->phy.reg_list[PHY_ID1_REG_IDX];
+    phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, phy_dev->phy.addr, PHY_MDIO_CSR_CLK_FREQ);
+
+    while(phy_dev->phy.addr == 0xffff)
+    {
+        /* Search a PHY */
+        for (i = 0; i <= 0x1f; i++)
+        {
+            ((rt_phy_t *)(phy_dev->phy.parent.user_data))->addr = i;
+            phy_dev->phy.parent.read(&(phy_dev->phy.parent), 0, &msg, 1);
+
+            if (msg.value == PHY_ID1)
+            {
+                phy_dev->phy.addr = i;
+                LOG_D("Found a PHY device[address:0x%02x].\n", phy_dev->phy.addr);
+                return;
+            }
+        }
+
+        phy_dev->phy.addr = 0xffff;
+        detected_count++;
+        rt_thread_mdelay(1000);
+
+        if (detected_count > 3)
+        {
+            LOG_E("No any PHY device is detected! Please check your hardware!\n");
+            return;
+        }
+    }
+}
+
+static void phy_monitor_thread_entry(void *args)
+{
+    rt_timer_t phy_status_timer;
+
+    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)args;
+
+    for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++)
+    {
+        LOG_D("Detect a PHY%d\n", i);
+        phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev);
+    }
+
+    phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER);
+
+    if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK)
+    {
+        LOG_E("Failed to start link change detection timer\n");
+    }
+}
+
+int phy_device_register(void)
+{
+    rt_err_t err = RT_ERROR;
+    rt_thread_t thread_phy_monitor;
+
+    /* Set ops for PHY */
+    phy_ops.init = phy_init;
+    phy_ops.get_link_status = phy_get_link_status;
+    phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex;
+
+    for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++)
+    {
+        /* Set PHY address */
+        s_gphys[i]->phy_dev->phy.addr = 0xffff;
+
+        /* Set MIDO bus */
+        s_gphys[i]->mdio_bus->hw_obj     = s_gphys[i]->instance;
+        s_gphys[i]->mdio_bus->name       = s_gphys[i]->mdio_name;
+        s_gphys[i]->mdio_bus->ops->read  = phy_read;
+        s_gphys[i]->mdio_bus->ops->write = phy_write;
+        s_gphys[i]->phy_dev->phy.bus     = s_gphys[i]->mdio_bus;
+        s_gphys[i]->phy_dev->phy.ops     = &phy_ops;
+
+        /* Set PHY register list */
+        s_gphys[i]->phy_dev->phy.reg_list = s_gphy_reg_list[i];
+
+        rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, PHY_NAME);
+    }
+
+    /* Start PHY monitor */
+    thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 1024, RT_THREAD_PRIORITY_MAX - 2, 2);
+
+    if (thread_phy_monitor != RT_NULL)
+    {
+        rt_thread_startup(thread_phy_monitor);
+    }
+    else
+    {
+        err = RT_ERROR;
+    }
+
+    return err;
+}
+INIT_PREV_EXPORT(phy_device_register);
+#endif /* RT_USING_PHY */

bsp/hpmicro/hpm6300evk/board/eth_phy_port.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef ETH_PHY_PORT_H
+#define ETH_PHY_PORT_H
+
+#include "hpm_ioc_regs.h"
+#include <rtdevice.h>
+
+#ifndef PHY_AUTO_NEGO
+#define PHY_AUTO_NEGO  (1U)
+#endif
+
+#ifndef PHY_MDIO_CSR_CLK_FREQ
+#define PHY_MDIO_CSR_CLK_FREQ (200000000U)
+#endif
+
+enum phy_link_status
+{
+   PHY_LINK_DOWN = 0U,
+   PHY_LINK_UP
+};
+
+typedef struct {
+    rt_uint32_t phy_speed;
+    rt_uint32_t phy_duplex;
+} phy_info_t;
+
+typedef struct {
+    rt_uint32_t phy_link;
+    rt_phy_t phy;
+    phy_info_t phy_info;
+} phy_device_t;
+
+/** @note PHY: RTL8201 */
+
+#define PHY_NAME    ("RTL8201")
+#define PHY_ID1     (0x1CU)
+
+/* The PHY basic control register */
+#define PHY_BASIC_CONTROL_REG       (0x00U)
+#define PHY_RESET_MASK              (1U << 15)
+#define PHY_AUTO_NEGOTIATION_MASK   (1U << 12)
+
+/* The PHY basic status register */
+#define PHY_BASIC_STATUS_REG        (0x01U)
+#define PHY_LINKED_STATUS_MASK      (1U << 2)
+#define PHY_AUTONEGO_COMPLETE_MASK  (1U << 5)
+
+/* The PHY ID one register */
+#define PHY_ID1_REG                 (0x02U)
+
+/* The PHY ID two register */
+#define PHY_ID2_REG                 (0x03U)
+
+/* The PHY auto-negotiate advertise register */
+#define PHY_AUTONEG_ADVERTISE_REG   (0x04U)
+
+/*  The PHY status register. */
+#define PHY_STATUS_REG              (0x00U)
+#define PHY_10M_MASK                (1 << 13)
+#define PHY_100M_MASK               (1 << 13)
+#define PHY_FULL_DUPLEX_MASK        (1 << 8)
+#define PHY_STATUS_SPEED_10M(SR)    ((SR) & PHY_100M_MASK) ? 0: 1
+#define PHY_STATUS_SPEED_100M(SR)   ((SR) & PHY_100M_MASK)
+#define PHY_STATUS_FULL_DUPLEX(SR)  ((SR) & PHY_FULL_DUPLEX_MASK)
+
+/* PHY0 register list */
+#define PHY0_REG_LIST  PHY_BASIC_CONTROL_REG,\
+                       PHY_BASIC_STATUS_REG,\
+                       PHY_ID1_REG,\
+                       PHY_ID2_REG,\
+                       PHY_AUTONEG_ADVERTISE_REG,\
+                       PHY_STATUS_REG
+
+/* PHY0 register index */
+#define PHY_BASIC_STATUS_REG_IDX (1U)
+#define PHY_ID1_REG_IDX          (2U)
+#define PHY_STATUS_REG_IDX       (5U)
+
+#endif

bsp/hpmicro/hpm6300evk/board/fal_cfg.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 8*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        15*1024*1024, 1*1024*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* RT_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */

bsp/hpmicro/hpm6300evk/board/fal_flash_port.c

@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2022-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2022-03-09   hpmicro     First implementation
+ * 2022-08-01   hpmicro     Fixed random crashing during kvdb_init
+ * 2022-08-03   hpmicro     Improved erase speed
+ * 2023-01-31   hpmicro     Fix random crashing issue if the global interrupt is always enabled
+ *
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_FAL
+#include "fal.h"
+#include "hpm_romapi.h"
+#include "board.h"
+#include "hpm_l1c_drv.h"
+
+
+#define FAL_ENTER_CRITICAL() do {\
+        disable_global_irq(CSR_MSTATUS_MIE_MASK);\
+    }while(0)
+
+#define FAL_EXIT_CRITICAL() do {\
+        enable_global_irq(CSR_MSTATUS_MIE_MASK);\
+    }while(0)
+
+#define FAL_RAMFUNC __attribute__((section(".isr_vector")))
+
+
+/***************************************************************************************************
+ *      FAL Porting Guide
+ *
+ *      1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH
+ *         must be placed at RAM or ROM code
+ *      2. During FLASH erase/program, it is recommended to disable the interrupt, or place the
+ *         interrupt related codes to RAM
+ *
+ ***************************************************************************************************/
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static xpi_nor_config_t s_flashcfg;
+
+/**
+ * @brief FAL Flash device context
+ */
+struct fal_flash_dev nor_flash0 =
+    {
+            .name = NOR_FLASH_DEV_NAME,
+            /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */
+            .addr = NOR_FLASH_MEM_BASE,
+            .len = 8 * 1024 * 1024,
+            .blk_size = 4096,
+            .ops = { .init = init, .read = read, .write = write, .erase = erase },
+            .write_gran = 1
+    };
+
+/**
+ * @brief FAL initialization
+ *        This function probes the FLASH using the ROM API
+ */
+FAL_RAMFUNC static int init(void)
+{
+    int ret = RT_EOK;
+    xpi_nor_config_option_t cfg_option;
+    cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR;
+    cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0;
+    cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1;
+
+    FAL_ENTER_CRITICAL();
+    hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option);
+    FAL_EXIT_CRITICAL();
+    if (status != status_success)
+    {
+        ret = -RT_ERROR;
+    }
+    else
+    {
+        s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U;
+        /* update the flash chip information */
+        uint32_t sector_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+        uint32_t flash_size;
+        rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size);
+        nor_flash0.blk_size = sector_size;
+        nor_flash0.len = flash_size;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief FAL read function
+ *        Read data from FLASH
+ * @param offset FLASH offset
+ * @param buf Buffer to hold data read by this API
+ * @param size Size of data to be read
+ * @return actual read bytes
+ */
+FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size)
+{
+    uint32_t flash_addr = nor_flash0.addr + offset;
+    uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr);
+    uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size);
+    uint32_t aligned_size = aligned_end - aligned_start;
+    rt_base_t level = rt_hw_interrupt_disable();
+    l1c_dc_invalidate(aligned_start, aligned_size);
+    rt_hw_interrupt_enable(level);
+
+    (void) rt_memcpy(buf, (void*) flash_addr, size);
+
+    return size;
+}
+
+/**
+ * @brief Write unaligned data to the page
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size)
+{
+    hpm_stat_t status;
+
+    FAL_ENTER_CRITICAL();
+    status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size);
+    FAL_EXIT_CRITICAL();
+
+    if (status != status_success)
+    {
+        return -RT_ERROR;
+        rt_kprintf("write failed, status=%d\n", status);
+    }
+
+    return size;
+}
+
+/**
+ * @brief FAL write function
+ *        Write data to specified FLASH address
+ * @param offset FLASH offset
+ * @param buf Data buffer
+ * @param size Size of data to be written
+ * @return actual size of written data or error code
+ */
+FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size)
+{
+    uint32_t *src = NULL;
+    uint32_t buf_32[64];
+    uint32_t write_size;
+    size_t remaining_size = size;
+    int ret = (int)size;
+
+    uint32_t page_size;
+    rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size);
+    uint32_t offset_in_page = offset % page_size;
+    if (offset_in_page != 0)
+    {
+        uint32_t write_size_in_page = page_size - offset_in_page;
+        uint32_t write_page_size = MIN(write_size_in_page, size);
+        (void) rt_memcpy(buf_32, buf, write_page_size);
+        write_size = write_unaligned_page_data(offset, buf_32, write_page_size);
+        if (write_size < 0)
+        {
+            ret = -RT_ERROR;
+            goto write_quit;
+        }
+
+        remaining_size -= write_page_size;
+        offset += write_page_size;
+        buf += write_page_size;
+    }
+
+    while (remaining_size > 0)
+    {
+        write_size = MIN(remaining_size, sizeof(buf_32));
+        rt_memcpy(buf_32, buf, write_size);
+        src = &buf_32[0];
+
+        FAL_ENTER_CRITICAL();
+        hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src,
+                offset, write_size);
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            rt_kprintf("write failed, status=%d\n", status);
+            break;
+        }
+
+        remaining_size -= write_size;
+        buf += write_size;
+        offset += write_size;
+    }
+
+write_quit:
+    return ret;
+}
+
+/**
+ * @brief FAL erase function
+ *        Erase specified FLASH region
+ * @param offset the start FLASH address to be erased
+ * @param size size of the region to be erased
+ * @ret RT_EOK Erase operation is successful
+ * @retval -RT_ERROR Erase operation failed
+ */
+FAL_RAMFUNC static int erase(long offset, size_t size)
+{
+    uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U);
+    hpm_stat_t status;
+    int ret = (int)size;
+
+    uint32_t block_size;
+    uint32_t sector_size;
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, &sector_size);
+    (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size);
+    uint32_t erase_unit;
+    while (aligned_size > 0)
+    {
+        FAL_ENTER_CRITICAL();
+        if ((offset % block_size == 0) && (aligned_size >= block_size))
+        {
+            erase_unit = block_size;
+            status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        else
+        {
+            erase_unit = sector_size;
+            status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset);
+        }
+        FAL_EXIT_CRITICAL();
+
+        if (status != status_success)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        offset += erase_unit;
+        aligned_size -= erase_unit;
+    }
+
+    return ret;
+}
+#endif /* RT_USING_FAL */

bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld

@@ -0,0 +1,304 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 384K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > AXI_SRAM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > AXI_SRAM
+    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
+
+    .heap(NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > AXI_SRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
+    } > AXI_SRAM
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+    .sdram (NOLOAD) : {
+        . = ALIGN(8);
+        __sdram_start__ = .;
+        . += SDRAM_SIZE;
+        __sdram_end__ = .;
+    } > SDRAM
+}

bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld

@@ -0,0 +1,297 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
+}
+
+__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
+__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000;
+__app_load_addr__ = ORIGIN(XPI0) + 0x3000;
+__boot_header_length__ = __boot_header_end__ - __boot_header_start__;
+__app_offset__ = __app_load_addr__ - __boot_header_load_addr__;
+
+SECTIONS
+{
+    .nor_cfg_option __nor_cfg_option_load_addr__ : {
+        KEEP(*(.nor_cfg_option))
+    } > XPI0
+
+    .boot_header __boot_header_load_addr__ : {
+        __boot_header_start__ = .;
+        KEEP(*(.boot_header))
+        KEEP(*(.fw_info_table))
+        KEEP(*(.dc_info))
+        __boot_header_end__ = .;
+    } > XPI0
+
+    .start __app_load_addr__ : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > XPI0
+
+    __vector_load_addr__ = ADDR(.start) + SIZEOF(.start);
+    .vectors : AT(__vector_load_addr__) {
+        . = ALIGN(8);
+        __vector_ram_start__ = .;
+        KEEP(*(.vector_table))
+        KEEP(*(.isr_vector))
+
+        . = ALIGN(8);
+        __vector_ram_end__ = .;
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __ramfunc_start__ = .;
+        *(.fast)
+
+        /* RT-Thread Core Start */
+        KEEP(*context_gcc.o(.text* .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
+        KEEP(*irq.o (.text .text* .rodata .rodata*))
+        KEEP(*clock.o (.text .text* .rodata .rodata*))
+        KEEP(*kservice.o (.text .text* .rodata .rodata*))
+        KEEP(*scheduler.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
+        KEEP(*idle.o (.text .text* .rodata .rodata*))
+        KEEP(*ipc.o (.text .text* .rodata .rodata*))
+        KEEP(*thread.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*timer.o (.text .text* .rodata .rodata*))
+        KEEP(*mem.o (.text .text* .rodata .rodata*))
+        KEEP(*mempool.o (.text .text* .rodata .rodata*))
+        /* RT-Thread Core End */
+        
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+
+        . = ALIGN(8);
+        __ramfunc_end__ = .;
+    } > AXI_SRAM
+
+    .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+    } > XPI0
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > XPI0
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > AXI_SRAM
+    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+
+    .heap(NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+    } > SDRAM
+
+    .framebuffer (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.framebuffer))
+        . = ALIGN(8);
+    } > SDRAM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        . = ALIGN(8);
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
+    } > AXI_SRAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+}

bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld

@@ -0,0 +1,259 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 64K;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 64K;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 448K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x10F0000, LENGTH = NONCACHEABLE_SIZE
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
+}
+
+SECTIONS
+{
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > AXI_SRAM
+
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > AXI_SRAM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > DLM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > AXI_SRAM
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+     .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE (__rt_rvstack = .);
+    } > DLM
+
+    .framebuffer (NOLOAD) : {
+        KEEP(*(.framebuffer))
+    } > AXI_SRAM
+
+    .heap (NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > AXI_SRAM
+
+    .sdram (NOLOAD) : {
+        . = ALIGN(8);
+        __sdram_start__ = .;
+        . += SDRAM_SIZE;
+        __sdram_end__ = .;
+    } > SDRAM
+}

bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld

@@ -0,0 +1,252 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 128K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 128K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
+}
+
+SECTIONS
+{
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > AXI_SRAM
+
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > AXI_SRAM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > AXI_SRAM
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+     .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE (__rt_rvstack = .);
+    } > AXI_SRAM
+
+    .framebuffer (NOLOAD) : {
+        KEEP(*(.framebuffer))
+    } > SDRAM
+
+    .heap (NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > SDRAM
+}

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.c → bsp/hpmicro/hpm6300evk/board/pinmux.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -28,6 +28,9 @@ void init_uart_pins(UART_Type *ptr)
     } else if (ptr == HPM_UART2) {
         HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD;
         HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD;
+    } else if (ptr == HPM_PUART) {
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD;
     }
 }
 
@@ -135,16 +138,6 @@ void init_spi_pins(SPI_Type *ptr)
     }
 }
 
-void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
-{
-    if (ptr == HPM_SPI3) {
-        HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18;
-        HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI;
-        HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO;
-        HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
-    }
-}
-
 void init_pins(void)
 {
     init_uart_pins(BOARD_CONSOLE_BASE);
@@ -174,8 +167,8 @@ void init_qei_trgm_pins(void)
 
 void init_butn_pins(void)
 {
-    /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */
-    /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */
+    // HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN;
+    // HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN;
 }
 
 void init_acmp_pins(void)
@@ -248,6 +241,23 @@ void init_can_pins(CAN_Type *ptr)
     }
 }
 
+void init_sdxc_power_pin(SDXC_Type *ptr)
+{
+
+}
+
+void init_sdxc_vsel_pin(SDXC_Type *ptr)
+{
+
+}
+
+void init_sdxc_card_detection_pin(SDXC_Type *ptr)
+{
+     /* SDXC0.CD */
+    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+}
+
 void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
 {
     uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
@@ -262,10 +272,6 @@ void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
     HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl;
     HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl;
 
-    /* SDXC0.CD */
-    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = func_ctl;
-    HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl;
-
     /* SDXC0.DATA0 */
     HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl;
     HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl;

bsp/hpmicro/libraries/hpm_sdk/boards/hpm6300evk/pinmux.h → bsp/hpmicro/hpm6300evk/board/pinmux.h

@@ -1,5 +1,5 @@
 /*
- *Copyright (c) 2022 hpmicro
+ *Copyright (c) 2022-2023 HPMicro
  *
  *SPDX-License-Identifier: BSD-3-Clause
  *
@@ -16,7 +16,6 @@ void init_i2c_pins(I2C_Type *ptr);
 void init_sdram_pins(void);
 void init_gpio_pins(void);
 void init_spi_pins(SPI_Type *ptr);
-void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
 void init_pins(void);
 void init_gptmr_pins(GPTMR_Type *ptr);
 void init_hall_trgm_pins(void);
@@ -29,6 +28,9 @@ void init_adc_pins(void);
 void init_dac_pins(DAC_Type *ptr);
 void init_usb_pins(void);
 void init_can_pins(CAN_Type *ptr);
+void init_sdxc_power_pin(SDXC_Type *ptr);
+void init_sdxc_vsel_pin(SDXC_Type *ptr);
+void init_sdxc_card_detection_pin(SDXC_Type *ptr);
 void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8);
 void init_adc_bldc_pins(void);
 void init_rgb_pwm_pins(void);

bsp/hpmicro/hpm6300evk/board/rtt_board.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021-2022 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_mchtmr_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_manager.h"
+
+void os_tick_config(void);
+
+extern int rt_hw_uart_init(void);
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_manager_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+   gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+
+void BOARD_LED_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+
+    enable_mchtmr_irq();
+}
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_interrupt_enter();
+    rt_tick_increase();
+    rt_interrupt_leave();
+}
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    clock_cpu_delay_us(us);
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_HOT &= ~(1UL << 31);
+    HPM_PPOR->RESET_COLD |= (1UL << 31);
+
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);

bsp/hpmicro/hpm6300evk/board/rtt_board.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <drv_gpio.h>
+
+/* gpio section */
+#define APP_LED0_PIN_NUM GET_PIN(A, 7)
+#define APP_LED_ON (0)
+#define APP_LED_OFF (1)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can0"
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */

bsp/hpmicro/hpm6300evk/rtconfig.h

@@ -0,0 +1,242 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50001
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_LEGACY
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers Config */
+
+#define SOC_HPM6000
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART0
+
+#endif

bsp/hpmicro/hpm6300evk/rtconfig.py

@@ -0,0 +1,108 @@
+# Copyright 2021-2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+CHIP_NAME='HPM6360'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+# Fallback toolchain info
+FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
+FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
+FALLBACK_TOOLCHAIN_VER='2022-04-12'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+if RTT_EXEC_PATH != None:
+    folders = RTT_EXEC_PATH.split(os.sep)
+    # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
+    if 'arm_gcc' in folders and 'platform' in folders:
+        RTT_EXEC_PATH = ''
+        for path in folders:
+            if path != 'platform':
+                RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
+            else:
+                break
+        RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
+    # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
+    if 'platform' in folders:
+        os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    ARCH_ABI = ' -mcmodel=medlow '
+    CFLAGS = ARCH_ABI  + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = CFLAGS +  ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    CFLAGS = CFLAGS + ' -std=gnu11'

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/SConscript → bsp/hpmicro/hpm6300evk/startup/HPM6360/SConscript

@@ -12,6 +12,7 @@ src = Split('''
 
 if rtconfig.PLATFORM == 'gcc':
     src += [os.path.join('toolchains', 'gcc', 'start.S')]
+    src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
 
 CPPPATH = [cwd]
 CPPDEFINES=['D45', rtconfig.CHIP_NAME]

bsp/hpmicro/hpm6750evk/startup/HPM6360/startup.c → bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 - 2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  *
  */
@@ -43,11 +43,19 @@ __attribute__((weak)) void c_startup(void)
 
     extern uint8_t __etext[];
     extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __tbss_start__[], __tbss_end__[];
+    extern uint8_t __tdata_start__[], __tdata_end__[];
     extern uint8_t __data_start__[], __data_end__[];
     extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
     extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
     extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
 
+    /* tbss section */
+    size = __tbss_end__ - __tbss_start__;
+    for (i = 0; i < size; i++) {
+        *(__tbss_start__ + i) = 0;
+    }
+
     /* bss section */
     size = __bss_end__ - __bss_start__;
     for (i = 0; i < size; i++) {
@@ -60,22 +68,28 @@ __attribute__((weak)) void c_startup(void)
         *(__noncacheable_bss_start__ + i) = 0;
     }
 
+    /* tdata section LMA: etext */
+    size = __tdata_end__ - __tdata_start__;
+    for (i = 0; i < size; i++) {
+        *(__tdata_start__ + i) = *(__etext + i);
+    }
+
     /* data section LMA: etext */
     size = __data_end__ - __data_start__;
     for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + i);
+        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
     }
 
     /* ramfunc section LMA: etext + data length */
     size = __ramfunc_end__ - __ramfunc_start__;
     for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
     }
 
     /* noncacheable init section LMA: etext + data length + ramfunc length */
     size = __noncacheable_init_end__ - __noncacheable_init_start__;
     for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
     }
 }
 

bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "cpuport.h"
+
+    .globl rt_hw_do_after_save_above
+    .type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+    csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, trap_entry
+    jalr    t2
+
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S → bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -16,6 +16,7 @@ _start:
     .option push
     .option norelax
     la gp, __global_pointer$
+    la tp, __thread_pointer
     .option pop
 
 #ifdef INIT_EXT_RAM_FOR_DATA
@@ -44,7 +45,6 @@ _start:
 #endif
     /* Disable Vector mode */
     csrci CSR_MMISC_CTL, 2
-
     /* Initialize trap_entry base */
     la t0, SW_handler
     csrw mtvec, t0

bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S → bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/vectors.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *

bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c → bsp/hpmicro/hpm6300evk/startup/HPM6360/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 - 2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -36,12 +36,16 @@
 #define IRQ_COP                 12
 #define IRQ_HOST                13
 
+#ifdef DEBUG
+#define RT_EXCEPTION_TRACE rt_kprintf
+#else
+#define RT_EXCEPTION_TRACE(...)
+#endif
+
 typedef void (*isr_func_t)(void);
 
 static volatile rt_hw_stack_frame_t *s_stack_frame;
 
-static void rt_show_stack_frame(void);
-
 __attribute((weak)) void mchtmr_isr(void)
 {
 }
@@ -54,141 +58,167 @@ __attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1,
 {
 }
 
+void rt_show_stack_frame(void)
+{
+    RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n");
+    RT_EXCEPTION_TRACE("ra      : 0x%08x\r\n", s_stack_frame->ra);
+    RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus
+    RT_EXCEPTION_TRACE("t0      : 0x%08x\r\n", s_stack_frame->t0);
+    RT_EXCEPTION_TRACE("t1      : 0x%08x\r\n", s_stack_frame->t1);
+    RT_EXCEPTION_TRACE("t2      : 0x%08x\r\n", s_stack_frame->t2);
+    RT_EXCEPTION_TRACE("a0      : 0x%08x\r\n", s_stack_frame->a0);
+    RT_EXCEPTION_TRACE("a1      : 0x%08x\r\n", s_stack_frame->a1);
+    RT_EXCEPTION_TRACE("a2      : 0x%08x\r\n", s_stack_frame->a2);
+    RT_EXCEPTION_TRACE("a3      : 0x%08x\r\n", s_stack_frame->a3);
+    RT_EXCEPTION_TRACE("a4      : 0x%08x\r\n", s_stack_frame->a4);
+    RT_EXCEPTION_TRACE("a5      : 0x%08x\r\n", s_stack_frame->a5);
+#ifndef __riscv_32e
+    RT_EXCEPTION_TRACE("a6      : 0x%08x\r\n", s_stack_frame->a6);
+    RT_EXCEPTION_TRACE("a7      : 0x%08x\r\n", s_stack_frame->a7);
+    RT_EXCEPTION_TRACE("t3      : 0x%08x\r\n", s_stack_frame->t3);
+    RT_EXCEPTION_TRACE("t4      : 0x%08x\r\n", s_stack_frame->t4);
+    RT_EXCEPTION_TRACE("t5      : 0x%08x\r\n", s_stack_frame->t5);
+    RT_EXCEPTION_TRACE("t6      : 0x%08x\r\n", s_stack_frame->t6);
+#endif
+}
+
 uint32_t exception_handler(uint32_t cause, uint32_t epc)
 {
     /* Unhandled Trap */
     uint32_t mdcause = read_csr(CSR_MDCAUSE);
     uint32_t mtval = read_csr(CSR_MTVAL);
+    rt_uint32_t mscratch = read_csr(0x340);
+
+    s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
+    rt_show_stack_frame();
+
     switch (cause)
     {
     case MCAUSE_INSTR_ADDR_MISALIGNED:
-        rt_kprintf("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval);
         break;
     case MCAUSE_INSTR_ACCESS_FAULT:
-        rt_kprintf("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
+        RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc);
         switch (mdcause & 0x07)
         {
         case 1:
-            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
             break;
         case 3:
-            rt_kprintf("mdcause: BUS error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
             break;
         case 4:
-            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
             break;
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     case MCAUSE_ILLEGAL_INSTR:
-        rt_kprintf("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval);
         switch (mdcause & 0x07)
         {
         case 0:
-            rt_kprintf("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
+            RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n");
             break;
         case 1:
-            rt_kprintf("mdcause: FP disabled exception \r\n");
+            RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: ACE disabled exception \r\n");
+            RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n");
             break;
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     case MCAUSE_BREAKPOINT:
-        rt_kprintf("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval);
         break;
     case MCAUSE_LOAD_ADDR_MISALIGNED:
-        rt_kprintf("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
+        RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval);
         break;
     case MCAUSE_LOAD_ACCESS_FAULT:
-        rt_kprintf("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
+        RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause);
         switch (mdcause & 0x07)
         {
         case 1:
-            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
             break;
         case 3:
-            rt_kprintf("mdcause: BUS error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
             break;
         case 4:
-            rt_kprintf("mdcause: Misaligned access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
             break;
         case 5:
-            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
             break;
         case 6:
-            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
             break;
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     case MCAUSE_STORE_AMO_ADDR_MISALIGNED:
-        rt_kprintf("exception: store amo address was misaligned, epc=%08x\n", epc);
+        RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc);
         break;
     case MCAUSE_STORE_AMO_ACCESS_FAULT:
-        rt_kprintf("exception: store amo access fault happened, epc=%08x\n", epc);
+        RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc);
         switch (mdcause & 0x07)
         {
         case 1:
-            rt_kprintf("mdcause: ECC/Parity error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n");
             break;
         case 2:
-            rt_kprintf("mdcause: PMP instruction access violation \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n");
             break;
         case 3:
-            rt_kprintf("mdcause: BUS error\r\n");
+            RT_EXCEPTION_TRACE("mdcause: BUS error\r\n");
             break;
         case 4:
-            rt_kprintf("mdcause: Misaligned access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n");
             break;
         case 5:
-            rt_kprintf("mdcause: PMP empty hole access \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n");
             break;
         case 6:
-            rt_kprintf("mdcause: PMA attribute inconsistency\r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n");
             break;
         case 7:
-            rt_kprintf("mdcause: PMA NAMO exception \r\n");
+            RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n");
         default:
-            rt_kprintf("mdcause: reserved \r\n");
+            RT_EXCEPTION_TRACE("mdcause: reserved \r\n");
             break;
         }
         break;
     default:
-        rt_kprintf("Unknown exception happened, cause=%d\n", cause);
+        RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause);
         break;
     }
 
-    rt_show_stack_frame();
-    while (1)
-    {
+    rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra);
+    while(1) {
     }
 }
 
-void trap_entry(rt_hw_stack_frame_t *stack_frame);
+void trap_entry(void);
 
-void trap_entry(rt_hw_stack_frame_t *stack_frame)
+void trap_entry(void)
 {
     uint32_t mcause = read_csr(CSR_MCAUSE);
     uint32_t mepc = read_csr(CSR_MEPC);
     uint32_t mstatus = read_csr(CSR_MSTATUS);
 
-    s_stack_frame = stack_frame;
-
 #if SUPPORT_PFT_ARCH
     uint32_t mxstatus = read_csr(CSR_MXSTATUS);
 #endif
@@ -272,25 +302,3 @@ void trap_entry(rt_hw_stack_frame_t *stack_frame)
     write_fcsr(fcsr);
 #endif
 }
-
-static void rt_show_stack_frame(void)
-{
-    rt_kprintf("Stack frame:\r\n----------------------------------------\r\n");
-    rt_kprintf("ra      : 0x%08x\r\n", s_stack_frame->ra);
-    rt_kprintf("mstatus : 0x%08x\r\n", read_csr(CSR_MSTATUS));
-    rt_kprintf("t0      : 0x%08x\r\n", s_stack_frame->t0);
-    rt_kprintf("t1      : 0x%08x\r\n", s_stack_frame->t1);
-    rt_kprintf("t2      : 0x%08x\r\n", s_stack_frame->t2);
-    rt_kprintf("a0      : 0x%08x\r\n", s_stack_frame->a0);
-    rt_kprintf("a1      : 0x%08x\r\n", s_stack_frame->a1);
-    rt_kprintf("a2      : 0x%08x\r\n", s_stack_frame->a2);
-    rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
-    rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
-    rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
-    rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
-    rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
-    rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
-    rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
-    rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
-    rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
-}

bsp/hpmicro/hpm6300evk/startup/SConscript

@@ -0,0 +1,13 @@
+# for module compiling
+import os
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+
+objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
+ASFLAGS = ' -I' + cwd
+
+Return('objs')

bsp/hpmicro/hpm6750evk/.config

@@ -8,6 +8,7 @@
 #
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
@@ -32,7 +33,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
 # CONFIG_RT_KPRINTF_USING_LONGLONG is not set
-# CONFIG_RT_DEBUG is not set
+# CONFIG_RT_USING_DEBUG is not set
 
 #
 # Inter-Thread communication
@@ -42,12 +43,12 @@ CONFIG_RT_USING_MUTEX=y
 CONFIG_RT_USING_EVENT=y
 CONFIG_RT_USING_MAILBOX=y
 CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
 # CONFIG_RT_USING_SIGNALS is not set
 
 #
 # Memory Management
 #
-CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
@@ -71,10 +72,10 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-CONFIG_RT_VER_NUM=0x50000
+CONFIG_RT_VER_NUM=0x50001
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 # CONFIG_RT_USING_CACHE is not set
-CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_RT_USING_HW_ATOMIC is not set
 # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 # CONFIG_RT_USING_CPU_FFS is not set
@@ -102,6 +103,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
 # CONFIG_RT_USING_DFS is not set
 # CONFIG_RT_USING_FAL is not set
 
@@ -159,7 +164,19 @@ CONFIG_RT_USING_RTC=y
 #
 # C/C++ and POSIX layer
 #
-CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 
 #
 # POSIX (Portable Operating System Interface) layer
@@ -198,9 +215,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
 # CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
 # CONFIG_RT_USING_ADT is not set
 # CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_VBUS is not set
+# CONFIG_RT_USING_KTIME is not set
 
 #
 # RT-Thread Utestcases
@@ -225,7 +244,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
 # CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_LIBMODBUS is not set
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
 
@@ -243,6 +261,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
 # CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@@ -350,7 +373,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # LVGL: powerful and easy-to-use embedded GUI library
 #
 # CONFIG_PKG_USING_LVGL is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
 
@@ -425,6 +447,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_HASH_MATCH is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
 # CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set
 
 #
 # system packages
@@ -461,6 +484,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
@@ -496,6 +521,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_QPC is not set
 # CONFIG_PKG_USING_AGILE_UPGRADE is not set
 # CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
 
 #
 # peripheral libraries and drivers
@@ -560,6 +588,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_BALANCE is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
 # CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
 # CONFIG_PKG_USING_MAX17048 is not set
@@ -580,6 +609,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_FT5426 is not set
 # CONFIG_PKG_USING_FT6236 is not set
 # CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ESP_IDF is not set
@@ -592,7 +622,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_LKDGUI is not set
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_WM_LIBRARIES is not set
 
 #
 # Kendryte SDK
@@ -650,14 +679,18 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
-# CONFIG_PKG_USING_BL_MCU_SDK is not set
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
 # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
 # CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
 # CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
 
 #
 # AI packages
@@ -676,7 +709,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # Signal Processing and Control Algorithm Packages
 #
 # CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+# CONFIG_PKG_USING_CMSIS_DSP is not set
 
 #
 # miscellaneous packages
@@ -723,7 +760,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
-# CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
 # CONFIG_PKG_USING_HELLO is not set
@@ -748,8 +784,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_RTDUINO is not set
 
 #
-# Projects
+# Projects and Demos
 #
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
 # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
 # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
 # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
@@ -896,14 +933,21 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Display
 #
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
-# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
 # CONFIG_PKG_USING_SEEED_TM1637 is not set
 
 #
 # Timing
 #
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
 
 #
 # Data Processing
@@ -937,7 +981,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 
 #
 # Signal IO
@@ -970,16 +1013,17 @@ CONFIG_BSP_USING_UART0=y
 # CONFIG_BSP_USING_UART13 is not set
 # CONFIG_BSP_USING_UART14 is not set
 # CONFIG_BSP_USING_SPI is not set
-CONFIG_BSP_USING_RTC=y
+# CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_ETH is not set
 # CONFIG_BSP_USING_SDXC is not set
 # CONFIG_BSP_USING_TOUCH is not set
 # CONFIG_BSP_USING_LCD is not set
 # CONFIG_BSP_USING_LVGL is not set
+# CONFIG_BSP_USING_PDMA is not set
 # CONFIG_BSP_USING_GPTMR is not set
 # CONFIG_BSP_USING_I2C is not set
-CONFIG_BSP_USING_DRAM=y
-CONFIG_INIT_EXT_RAM_FOR_DATA=y
+# CONFIG_BSP_USING_FEMC is not set
+# CONFIG_INIT_EXT_RAM_FOR_DATA is not set
 # CONFIG_BSP_USING_XPI_FLASH is not set
 # CONFIG_BSP_USING_PWM is not set
 # CONFIG_BSP_USING_DAO is not set
@@ -988,3 +1032,4 @@ CONFIG_INIT_EXT_RAM_FOR_DATA=y
 # CONFIG_BSP_USING_USB is not set
 # CONFIG_BSP_USING_WDG is not set
 # CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_ADC is not set

bsp/hpmicro/hpm6750evk/README.md

@@ -0,0 +1,116 @@
+# HPMicro HPM6750EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provide brief introduction of the BSP (board support package) for the HPM6750EVK development board.
+
+The document consists of the following parts:
+
+- HPM6750EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM6750EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Display, Audio, motor control, etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| Ethernet                 | √           |  Dual Ethernet Ports                  |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6750EVKMINI RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6750evk)

bsp/hpmicro/hpm6750evk/README_zh.md

@@ -0,0 +1,115 @@
+# 先楫 HPM6750EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM6750EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM6750EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+HPM6750EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于显示、音频和电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           | 双以太网端口                           |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6750EVKMINI RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6750evk)

bsp/hpmicro/hpm6750evk/board/Kconfig

@@ -5,7 +5,6 @@ config SOC_HPM6000
     select SOC_SERIES_HPM6000
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
-    select RT_USING_HW_ATOMIC
     default y
 
 menu "On-chip Peripheral Drivers"
@@ -247,6 +246,11 @@ menu "On-chip Peripheral Drivers"
         bool "Enable LVGL"
         default n
         select PKG_USING_LVGL if BSP_USING_LVGL
+        select BSP_USING_PDMA if BSP_USING_LVGL
+
+    menuconfig BSP_USING_PDMA
+        bool "Enable PDMA Driver"
+        default n
 
     menuconfig BSP_USING_GPTMR
         bool "Enable GPTMR"
@@ -286,7 +290,7 @@ menu "On-chip Peripheral Drivers"
                     default y
         endif
 
-    menuconfig BSP_USING_DRAM
+    menuconfig BSP_USING_FEMC
        bool "Enable DRAM"
        default y
     menuconfig INIT_EXT_RAM_FOR_DATA
@@ -373,6 +377,36 @@ menu "On-chip Peripheral Drivers"
                 bool "Enable CAN3"
                 default n
      endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC if BSP_USING_ADC
+        if BSP_USING_ADC
+            menuconfig BSP_USING_ADC12
+            bool "Enable ADC12"
+            default n
+                if BSP_USING_ADC12
+                    config BSP_USING_ADC0
+                        bool "Enable ADC0"
+                        default n
+                    config BSP_USING_ADC1
+                        bool "Enable ADC1"
+                        default n
+                    config BSP_USING_ADC2
+                        bool "Enable ADC2"
+                        default n
+                endif
+            menuconfig BSP_USING_ADC16
+            bool "Enable ADC16"
+            default n
+                if BSP_USING_ADC16
+                    config BSP_USING_ADC3
+                        bool "Enable ADC3"
+                        default n
+                endif
+        endif
+
 endmenu
 
 

bsp/hpmicro/hpm6750evk/board/SConscript

@@ -10,7 +10,6 @@ src = Split("""
     eth_phy_port.c
     fal_flash_port.c
     hpm_sgtl5000.c
-    trap_gcc.S
 """)
 
 CPPPATH = [cwd]

bsp/hpmicro/hpm6750evk/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */
@@ -11,7 +11,7 @@
 #include "hpm_i2c_drv.h"
 #include "hpm_gpio_drv.h"
 #include "hpm_debug_console.h"
-#include "hpm_dram_drv.h"
+#include "hpm_femc_drv.h"
 #include "pinmux.h"
 #include "hpm_pmp_drv.h"
 #include "assert.h"
@@ -21,6 +21,8 @@
 #include "hpm_pwm_drv.h"
 #include "hpm_trgm_drv.h"
 #include "hpm_pllctl_drv.h"
+#include "hpm_enet_drv.h"
+#include "hpm_pcfg_drv.h"
 
 static board_timer_cb timer_cb;
 
@@ -87,7 +89,7 @@ ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATU
 
 void board_init_console(void)
 {
-#if BOARD_CONSOLE_TYPE == console_type_uart
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
     console_config_t cfg;
 
     /* Configure the UART clock to 24MHz */
@@ -115,28 +117,29 @@ void board_print_clock_freq(void)
     printf("==============================\n");
     printf(" %s clock summary\n", BOARD_NAME);
     printf("==============================\n");
-    printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0));
-    printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1));
-    printf("axi0:\t\t %dHz\n", clock_get_frequency(clock_axi0));
-    printf("axi1:\t\t %dHz\n", clock_get_frequency(clock_axi1));
-    printf("axi2:\t\t %dHz\n", clock_get_frequency(clock_axi2));
-    printf("ahb:\t\t %dHz\n", clock_get_frequency(clock_ahb));
-    printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0));
-    printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1));
-    printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0));
-    printf("xpi1:\t\t %dHz\n", clock_get_frequency(clock_xpi1));
-    printf("dram:\t\t %dHz\n", clock_get_frequency(clock_dram));
-    printf("display:\t %dHz\n", clock_get_frequency(clock_display));
-    printf("cam0:\t\t %dHz\n", clock_get_frequency(clock_camera0));
-    printf("cam1:\t\t %dHz\n", clock_get_frequency(clock_camera1));
-    printf("jpeg:\t\t %dHz\n", clock_get_frequency(clock_jpeg));
-    printf("pdma:\t\t %dHz\n", clock_get_frequency(clock_pdma));
+    printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0));
+    printf("cpu1:\t\t %luHz\n", clock_get_frequency(clock_cpu1));
+    printf("axi0:\t\t %luHz\n", clock_get_frequency(clock_axi0));
+    printf("axi1:\t\t %luHz\n", clock_get_frequency(clock_axi1));
+    printf("axi2:\t\t %luHz\n", clock_get_frequency(clock_axi2));
+    printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb));
+    printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0));
+    printf("mchtmr1:\t %luHz\n", clock_get_frequency(clock_mchtmr1));
+    printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0));
+    printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1));
+    printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
+    printf("display:\t %luHz\n", clock_get_frequency(clock_display));
+    printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0));
+    printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1));
+    printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg));
+    printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma));
     printf("==============================\n");
 }
 
 void board_init_uart(UART_Type *ptr)
 {
     init_uart_pins(ptr);
+    board_init_uart_clock(ptr);
 }
 
 void board_init_ahb(void)
@@ -198,12 +201,12 @@ void board_init_sdram_pins(void)
     init_sdram_pins();
 }
 
-uint32_t board_init_dram_clock(void)
+uint32_t board_init_femc_clock(void)
 {
-    clock_set_source_divider(clock_dram, clk_src_pll2_clk0, 2U); /* 166Mhz */
-    /* clock_set_source_divider(clock_dram, clk_src_pll1_clk1, 2U); [> 200Mhz <] */
+    clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */
+    /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */
 
-    return clock_get_frequency(clock_dram);
+    return clock_get_frequency(clock_femc);
 }
 
 void board_power_cycle_lcd(void)
@@ -233,6 +236,28 @@ void board_init_lcd(void)
     board_power_cycle_lcd();
 }
 
+void board_panel_para_to_lcdc(lcdc_config_t *config)
+{
+    const uint16_t panel_timing_para[] = BOARD_PANEL_TIMING_PARA;
+
+    config->resolution_x = BOARD_LCD_WIDTH;
+    config->resolution_y = BOARD_LCD_HEIGHT;
+
+    config->hsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSPW_INDEX];
+    config->hsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HBP_INDEX];
+    config->hsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HFP_INDEX];
+
+    config->vsync.pulse_width = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSPW_INDEX];
+    config->vsync.back_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VBP_INDEX];
+    config->vsync.front_porch_pulse = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VFP_INDEX];
+
+    config->control.invert_hsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_HSSP_INDEX];
+    config->control.invert_vsync = panel_timing_para[BOARD_PANEL_TIMEING_PARA_VSSP_INDEX];
+    config->control.invert_href = panel_timing_para[BOARD_PANEL_TIMEING_PARA_DESP_INDEX];
+    config->control.invert_pixel_data = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PDSP_INDEX];
+    config->control.invert_pixel_clock = panel_timing_para[BOARD_PANEL_TIMEING_PARA_PCSP_INDEX];
+}
+
 void board_delay_ms(uint32_t ms)
 {
     clock_cpu_delay_ms(ms);
@@ -325,22 +350,52 @@ void board_init_i2c(I2C_Type *ptr)
 
 uint32_t board_init_uart_clock(UART_Type *ptr)
 {
-    uint32_t freq = 0U;
+    uint32_t freq = 0;
+    clock_name_t clock_name = clock_uart0;
+    bool need_init_clock = true;
     if (ptr == HPM_UART0) {
-        clock_set_source_divider(clock_uart0, clk_src_osc24m, 1);
-        freq = clock_get_frequency(clock_uart0);
+        clock_name = clock_uart0;
+    } else if (ptr == HPM_UART1) {
+        clock_name = clock_uart1;
+    } else if (ptr == HPM_UART2) {
+        clock_name = clock_uart2;
+    } else if (ptr == HPM_UART3) {
+        clock_name = clock_uart3;
+    } else if (ptr == HPM_UART4) {
+        clock_name = clock_uart4;
+    } else if (ptr == HPM_UART5) {
+        clock_name = clock_uart5;
     } else if (ptr == HPM_UART6) {
-        clock_set_source_divider(clock_uart6, clk_src_osc24m, 1);
-        freq = clock_get_frequency(clock_uart6);
+        clock_name = clock_uart6;
+    } else if (ptr == HPM_UART7) {
+        clock_name = clock_uart7;
+    } else if (ptr == HPM_UART8) {
+        clock_name = clock_uart8;
+    } else if (ptr == HPM_UART9) {
+        clock_name = clock_uart9;
+    } else if (ptr == HPM_UART10) {
+        clock_name = clock_uart10;
+    } else if (ptr == HPM_UART11) {
+        clock_name = clock_uart11;
+    } else if (ptr == HPM_UART12) {
+        clock_name = clock_uart12;
     } else if (ptr == HPM_UART13) {
-        clock_set_source_divider(clock_uart13, clk_src_osc24m, 1);
-        freq = clock_get_frequency(clock_uart13);
+        clock_name = clock_uart13;
     } else if (ptr == HPM_UART14) {
-        clock_set_source_divider(clock_uart14, clk_src_osc24m, 1);
-        freq = clock_get_frequency(clock_uart14);
+        clock_name = clock_uart14;
+    } else if (ptr == HPM_UART15) {
+        clock_name = clock_uart15;
     } else {
-        /* Not supported */
+        /* Unsupported instance */
+        need_init_clock = false;
+    }
+
+    if (need_init_clock) {
+        clock_set_source_divider(clock_name, clk_src_osc24m, 1);
+        clock_add_to_group(clock_name, 0);
+        freq = clock_get_frequency(clock_name);
     }
+
     return freq;
 }
 
@@ -482,7 +537,7 @@ void board_init_clock(void)
     clock_add_to_group(clock_axi1, 0);
     clock_add_to_group(clock_axi2, 0);
     clock_add_to_group(clock_ahb, 0);
-    clock_add_to_group(clock_dram, 0);
+    clock_add_to_group(clock_femc, 0);
     clock_add_to_group(clock_xpi0, 0);
     clock_add_to_group(clock_xpi1, 0);
     clock_add_to_group(clock_gptmr0, 0);
@@ -494,10 +549,6 @@ void board_init_clock(void)
     clock_add_to_group(clock_gptmr6, 0);
     clock_add_to_group(clock_gptmr7, 0);
     clock_add_to_group(clock_uart0, 0);
-    clock_add_to_group(clock_uart1, 0);
-    clock_add_to_group(clock_uart2, 0);
-    clock_add_to_group(clock_uart3, 0);
-    clock_add_to_group(clock_uart13, 0);
     clock_add_to_group(clock_i2c0, 0);
     clock_add_to_group(clock_i2c1, 0);
     clock_add_to_group(clock_i2c2, 0);
@@ -543,6 +594,7 @@ void board_init_clock(void)
     clock_add_to_group(clock_msyn, 0);
     clock_add_to_group(clock_lmm0, 0);
     clock_add_to_group(clock_lmm1, 0);
+    clock_add_to_group(clock_pdm, 0);
 
     clock_add_to_group(clock_adc0, 0);
     clock_add_to_group(clock_adc1, 0);
@@ -553,23 +605,30 @@ void board_init_clock(void)
     clock_add_to_group(clock_i2s1, 0);
     clock_add_to_group(clock_i2s2, 0);
     clock_add_to_group(clock_i2s3, 0);
+    /* Connect Group0 to CPU0 */
+    clock_connect_group_to_cpu(0, 0);
 
     /* Add the CPU1 clock to Group1 */
     clock_add_to_group(clock_mchtmr1, 1);
     clock_add_to_group(clock_mbx1, 1);
+    /* Connect Group1 to CPU1 */
+    clock_connect_group_to_cpu(1, 1);
 
-    /* Connect Group0 to CPU0 */
-    clock_connect_group_to_cpu(0, 0);
+    /* Bump up DCDC voltage to 1200mv */
+    pcfg_dcdc_set_voltage(HPM_PCFG, 1200);
 
     if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) {
         printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ);
-        while(1);
+        while (1) {
+        }
     }
 
     clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
     clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);
     /* Connect Group1 to CPU1 */
     clock_connect_group_to_cpu(1, 1);
+
+    clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 54); /* config clock_aud1 for 44100*n sample rate */
 }
 
 uint32_t board_init_cam_clock(CAM_Type *ptr)
@@ -760,23 +819,24 @@ uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
  */
 void _init_ext_ram(void)
 {
-    uint32_t dram_clk_in_hz;
+    uint32_t femc_clk_in_hz;
+    clock_add_to_group(clock_femc, 0);
     board_init_sdram_pins();
-    dram_clk_in_hz = board_init_dram_clock();
+    femc_clk_in_hz = board_init_femc_clock();
 
-    dram_config_t config = {0};
-    dram_sdram_config_t sdram_config = {0};
+    femc_config_t config = {0};
+    femc_sdram_config_t sdram_config = {0};
 
-    dram_default_config(HPM_DRAM, &config);
-    config.dqs = DRAM_DQS_INTERNAL;
-    dram_init(HPM_DRAM, &config);
+    femc_default_config(HPM_FEMC, &config);
+    config.dqs = FEMC_DQS_INTERNAL;
+    femc_init(HPM_FEMC, &config);
 
-    sdram_config.bank_num = DRAM_SDRAM_BANK_NUM_4;
+    sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
     sdram_config.prescaler = 0x3;
     sdram_config.burst_len_in_byte = 8;
     sdram_config.auto_refresh_count_in_one_burst = 1;
-    sdram_config.col_addr_bits = DRAM_SDRAM_COLUMN_ADDR_9_BITS;
-    sdram_config.cas_latency = DRAM_SDRAM_CAS_LATENCY_3;
+    sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
+    sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
 
     sdram_config.precharge_to_act_in_ns = 18;   /* Trp */
     sdram_config.act_to_rw_in_ns = 18;          /* Trcd */
@@ -789,7 +849,7 @@ void _init_ext_ram(void)
     sdram_config.refresh_to_refresh_in_ns = 66;     /* Trfc/Trc */
     sdram_config.act_to_act_in_ns = 12;             /* Trrd */
     sdram_config.idle_timeout_in_ns = 6;
-    sdram_config.cs_mux_pin = DRAM_IO_MUX_NOT_USED;
+    sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
 
     sdram_config.cs = BOARD_SDRAM_CS;
     sdram_config.base_address = BOARD_SDRAM_ADDRESS;
@@ -800,13 +860,19 @@ void _init_ext_ram(void)
     sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
     sdram_config.delay_cell_value = 29;
 
-    dram_config_sdram(HPM_DRAM, dram_clk_in_hz, &sdram_config);
+    femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
 }
 
 
 void board_init_sd_pins(SDXC_Type *ptr)
 {
     init_sdxc_pins(ptr, false);
+    init_sdxc_card_detection_pin(ptr);
+}
+
+void board_sd_power_switch(SDXC_Type *ptr, bool on_off)
+{
+    /* This feature is not supported on current board */
 }
 
 
@@ -818,6 +884,7 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq)
             break;
         }
         clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1;
+        sdxc_enable_inverse_clock(ptr, false);
         sdxc_enable_sd_clock(ptr, false);
         /* Configure the clock below 400KHz for the identification state */
         if (freq <= 400000UL) {
@@ -843,6 +910,7 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq)
         else {
             clock_set_source_divider(sdxc_clk, clk_src_osc24m, 1);
         }
+        sdxc_enable_inverse_clock(ptr, true);
         sdxc_enable_sd_clock(ptr, true);
         actual_freq = clock_get_frequency(sdxc_clk);
     } while (false);
@@ -1012,11 +1080,11 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
 {
     if (ptr == HPM_ENET0) {
         gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 0);
-        board_delay_ms(1);
+        board_delay_ms(BOARD_ENET0_PHY_RST_TIME);
         gpio_write_pin(BOARD_ENET0_RST_GPIO, BOARD_ENET0_RST_GPIO_INDEX, BOARD_ENET0_RST_GPIO_PIN, 1);
     } else if (ptr == HPM_ENET1) {
         gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 0);
-        board_delay_ms(1);
+        board_delay_ms(BOARD_ENET1_PHY_RST_TIME);
         gpio_write_pin(BOARD_ENET1_RST_GPIO, BOARD_ENET1_RST_GPIO_INDEX, BOARD_ENET1_RST_GPIO_PIN, 1);
     } else {
         return status_invalid_argument;
@@ -1024,3 +1092,8 @@ hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
 
     return status_success;
 }
+
+uint8_t board_enet_get_dma_pbl(ENET_Type *ptr)
+{
+    return enet_pbl_32;
+}

bsp/hpmicro/hpm6750evk/board/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -13,6 +13,7 @@
 #include "hpm_soc.h"
 #include "hpm_soc_feature.h"
 #include "pinmux.h"
+#include "hpm_lcdc_drv.h"
 
 #define BOARD_NAME "hpm6750evk"
 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL)
@@ -50,10 +51,10 @@
 #define BOARD_APP_UART_CLK_NAME clock_uart0
 
 #ifndef BOARD_CONSOLE_TYPE
-#define BOARD_CONSOLE_TYPE console_type_uart
+#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
 #endif
 
-#if BOARD_CONSOLE_TYPE == console_type_uart
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_BASE
 #if BOARD_RUNNING_CORE == HPM_CORE0
 #define BOARD_CONSOLE_BASE HPM_UART0
@@ -74,8 +75,8 @@
 /* sdram section */
 #define BOARD_SDRAM_ADDRESS  (0x40000000UL)
 #define BOARD_SDRAM_SIZE     (32*SIZE_1MB)
-#define BOARD_SDRAM_CS       DRAM_SDRAM_CS0
-#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS
+#define BOARD_SDRAM_CS       FEMC_SDRAM_CS0
+#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS
 #define BOARD_SDRAM_REFRESH_COUNT (8192UL)
 #define BOARD_SDRAM_REFRESH_IN_MS (64UL)
 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL)
@@ -201,11 +202,58 @@
 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)
 
 /* lcd section */
+
+/*
+ * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP}
+ *
+ * HSPW: Horizontal Synchronization Pulse width
+ * HBP: Horizontal Back Porch
+ * HFP: Horizontal Front Porch
+ * VSPW: Vertical Synchronization Pulse width
+ * VBP: Vertical Back Porch
+ * VFP: Vertical Front Porch
+ * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active
+ * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active
+ * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active
+ * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active
+ * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active
+ */
+#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0
+#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1
+#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2
+#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3
+#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4
+#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5
+#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6
+#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7
+#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8
+#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9
+#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10
+
+#if defined(PANEL_TM070RDH13)
+
 #ifndef BOARD_LCD_WIDTH
-#define BOARD_LCD_WIDTH (800)
+#define BOARD_LCD_WIDTH 800
 #endif
 #ifndef BOARD_LCD_HEIGHT
-#define BOARD_LCD_HEIGHT (480)
+#define BOARD_LCD_HEIGHT 480
+#endif
+#ifndef BOARD_PANEL_TIMING_PARA
+#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0}
+#endif
+
+#else
+
+#ifndef BOARD_LCD_WIDTH
+#define BOARD_LCD_WIDTH 800
+#endif
+#ifndef BOARD_LCD_HEIGHT
+#define BOARD_LCD_HEIGHT 480
+#endif
+#ifndef BOARD_PANEL_TIMING_PARA
+#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0}
+#endif
+
 #endif
 
 /* pdma section */
@@ -222,19 +270,33 @@
 #define BOARD_ENET0_RST_GPIO       HPM_GPIO0
 #define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF
 #define BOARD_ENET0_RST_GPIO_PIN   (0U)
-#define BOARD_ENET0_INF            enet_inf_rgmii
-#define BOARD_ENET0                HPM_ENET0
-#define BOARD_ENET0_TX_DLY         (0U)
-#define BOARD_ENET0_RX_DLY         (21U)
-#define BOARD_ENET0_PTP_CLOCK      (clock_ptp0)
+#define BOARD_ENET0_INF             (1U)  /* 0: RMII, 1: RGMII */
+#define BOARD_ENET0_INT_REF_CLK     (0U)
+#define BOARD_ENET0_PHY_RST_TIME    (30)
+#if BOARD_ENET0_INF
+#define BOARD_ENET0_TX_DLY          (0U)
+#define BOARD_ENET0_RX_DLY          (21U)
+#endif
+#if __USE_ENET_PTP
+#define BOARD_ENET0_PTP_CLOCK       (clock_ptp0)
+#endif
 
 #define BOARD_ENET1_RST_GPIO        HPM_GPIO0
 #define BOARD_ENET1_RST_GPIO_INDEX  GPIO_DO_GPIOE
 #define BOARD_ENET1_RST_GPIO_PIN    (26U)
-#define BOARD_ENET1_INF             enet_inf_rmii
-#define BOARD_ENET1                 HPM_ENET1
+
+#define BOARD_ENET1_INF             (0U)  /* 0: RMII, 1: RGMII */
 #define BOARD_ENET1_INT_REF_CLK     (1U)
+#define BOARD_ENET1_PHY_RST_TIME    (30)
+
+#if BOARD_ENET1_INF
+#define BOARD_ENET1_TX_DLY          (0U)
+#define BOARD_ENET1_RX_DLY          (0U)
+#endif
+
+#if __USE_ENET_PTP
 #define BOARD_ENET1_PTP_CLOCK       (clock_ptp1)
+#endif
 
 /* ADC section */
 #define BOARD_APP_ADC12_NAME "ADC0"
@@ -429,10 +491,10 @@ void board_init_console(void);
 void board_init_uart(UART_Type *ptr);
 void board_init_i2c(I2C_Type *ptr);
 void board_init_lcd(void);
-
+void board_panel_para_to_lcdc(lcdc_config_t *config);
 void board_init_can(CAN_Type *ptr);
 
-uint32_t board_init_dram_clock(void);
+uint32_t board_init_femc_clock(void);
 
 void board_init_sdram_pins(void);
 void board_init_gpio_pins(void);
@@ -478,6 +540,7 @@ void board_init_sd_pins(SDXC_Type *ptr);
 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq);
 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr);
 bool board_sd_detect_card(SDXC_Type *ptr);
+void board_sd_power_switch(SDXC_Type *ptr, bool on_off);
 
 void board_init_adc12_pins(void);
 void board_init_adc16_pins(void);
@@ -485,8 +548,10 @@ void board_init_adc16_pins(void);
 void board_init_usb_pins(void);
 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
 
+uint8_t    board_enet_get_dma_pbl(ENET_Type *ptr);
 hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
 
 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-csr.cfg

@@ -1 +1,50 @@
-riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534
+riscv expose_csrs 262=scounteren
+riscv expose_csrs 800=mcountinhibit
+riscv expose_csrs 1984=milmb
+riscv expose_csrs 1985=mdlmb
+riscv expose_csrs 1986=mecc_code
+riscv expose_csrs 1987=mnvec
+riscv expose_csrs 1988=mxstatus
+riscv expose_csrs 1989=mpft_ctl
+riscv expose_csrs 1990=mhsp_ctl
+riscv expose_csrs 1991=msp_bound
+riscv expose_csrs 1992=msp_base
+riscv expose_csrs 1993=mdcause
+riscv expose_csrs 1994=mcache_ctl
+riscv expose_csrs 1995=mcctlbeginaddr
+riscv expose_csrs 1996=mcctlcommand
+riscv expose_csrs 1997=mcctldata
+riscv expose_csrs 1998=mcounterwen
+riscv expose_csrs 1999=mcounterinten
+riscv expose_csrs 2000=mmisc_ctl
+riscv expose_csrs 2001=mcountermask_m
+riscv expose_csrs 2002=mcountermask_s
+riscv expose_csrs 2003=mcountermask_u
+riscv expose_csrs 2004=mcounterovf
+riscv expose_csrs 2005=mslideleg
+riscv expose_csrs 2015=mclk_ctl
+riscv expose_csrs 2016=dexc2dbg
+riscv expose_csrs 2017=ddcause
+riscv expose_csrs 2048=uitb
+riscv expose_csrs 2049=ucode
+riscv expose_csrs 2057=udcause
+riscv expose_csrs 2059=ucctlbeginaddr
+riscv expose_csrs 2060=ucctlcommand
+riscv expose_csrs 2500=slie
+riscv expose_csrs 2501=slip
+riscv expose_csrs 2505=sdcause
+riscv expose_csrs 2509=scctldata
+riscv expose_csrs 2511=scounterinten
+riscv expose_csrs 2513=scountermask_m
+riscv expose_csrs 2514=scountermask_s
+riscv expose_csrs 2515=scountermask_u
+riscv expose_csrs 2516=scounterovf
+riscv expose_csrs 2528=scountinhibit
+riscv expose_csrs 2531=shpmevent3
+riscv expose_csrs 2532=shpmevent4
+riscv expose_csrs 2533=shpmevent5
+riscv expose_csrs 2534=shpmevent6
+riscv expose_csrs 4032=micm_cfg
+riscv expose_csrs 4033=mdcm_cfg
+riscv expose_csrs 4034=mmsc_cfg
+riscv expose_csrs 4035=mmsc_cfg2

bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg

@@ -1,5 +1,7 @@
 # Copyright 2021 hpmicro
 # SPDX-License-Identifier: BSD-3-Clause
+#
+
 
 set _CHIP hpm6750
 set _CPUTAPID 0x1000563D
@@ -12,27 +14,48 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are
 
 targets $_TARGET0
 
-set _TARGET1 $_CHIP.cpu1
-target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+proc dmi_write {reg value} {
+    $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc dmi_read {reg} {
+    set v [$::_TARGET0 riscv dmi_read ${reg}]
+    return ${v}
+}
+proc dmi_write_memory {addr value} {
+    dmi_write 0x39 ${addr}
+    dmi_write 0x3C ${value}
+}
+
+proc dmi_read_memory {addr} {
+    set sbcs [expr 0x100000 | [dmi_read 0x38]]
+    dmi_write 0x38 ${sbcs}
+    dmi_write 0x39 ${addr}
+    set value [dmi_read 0x3C]
+    return ${value}
+}
 
 proc release_core1 {} {
     # set start point for core1
-    $::_TARGET0 riscv dmi_write 0x39 0xF4002C08
-    $::_TARGET0 riscv dmi_write 0x3C 0x20016284
+    dmi_write_memory 0xF4002C08 0x20016284
 
     # set boot flag for core1
-    $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C
-    $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9
+    dmi_write_memory 0xF4002C0C 0xC1BEF1A9
 
     # release core1
-    $::_TARGET0 riscv dmi_write 0x39 0xF4002C00
-    $::_TARGET0 riscv dmi_write 0x3C 0x1000
+    dmi_write_memory 0xF4002C00 0x1000
+}
+
+$_TARGET0 configure -event examine-end {
+    release_core1
 }
 
-$_TARGET1 configure -event reset-deassert-pre release_core1
-$_TARGET1 configure -event examine-start release_core1
-$_TARGET1 configure -event examine-end {
-    $::_TARGET1 arp_examine
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+$_TARGET1 configure -event reset-deassert-pre {
+    $::_TARGET1 arp_poll
+    release_core1
 }
 
-$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0

bsp/hpmicro/hpm6750evk/board/eth_phy_port.c

@@ -101,14 +101,14 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr
     return PHY_STATUS_OK;
 }
 
-static rt_ssize_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
 {
     *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg);
 
     return size;
 }
 
-static rt_ssize_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
 {
     enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg,  *(uint16_t *)data);
 
@@ -170,13 +170,14 @@ static void phy_poll_status(void *parameter)
 {
     int ret;
     phy_info_t phy_info;
-    rt_uint32_t status;
+    rt_bool_t status;
     rt_device_t dev;
     rt_phy_msg_t msg;
     rt_uint32_t speed, duplex;
     phy_device_t *phy_dev;
     struct eth_device* eth_dev;
     char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"};
+    enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps};
 
     eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter;
 
@@ -207,6 +208,8 @@ static void phy_poll_status(void *parameter)
             {
                 LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]);
                 LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex");
+                enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]);
+                enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex);
             }
         }
     }
@@ -272,7 +275,7 @@ static void phy_monitor_thread_entry(void *args)
 
 int phy_device_register(void)
 {
-    rt_err_t err = -RT_ERROR;
+    rt_err_t err = RT_ERROR;
     rt_thread_t thread_phy_monitor;
 
     /* Set ops for PHY */
@@ -308,7 +311,7 @@ int phy_device_register(void)
     }
     else
     {
-        err = -RT_ERROR;
+        err = RT_ERROR;
     }
 
     return err;

bsp/hpmicro/hpm6750evk/board/eth_phy_port.h

@@ -156,6 +156,3 @@ typedef struct {
 #endif
 #endif
 
-
-
-

bsp/hpmicro/hpm6750evk/board/fal_cfg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -32,7 +32,8 @@ extern struct fal_flash_dev nor_flash0;
 {                                                                                    \
     {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
     {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
-    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 9*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 8*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        15*1024*1024, 1*1024*1024,    0}, \
 }
 #endif /* FAL_PART_HAS_TABLE_CFG */
 #endif /* RT_USING_FAL */

bsp/hpmicro/hpm6750evk/board/fal_flash_port.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
@@ -20,18 +20,19 @@
 
 #if defined(FLASH_XIP) && (FLASH_XIP == 1)
 
+static rt_base_t s_interrupt_level;
 #define FAL_ENTER_CRITICAL() do {\
         rt_enter_critical();\
-        disable_irq_from_intc();\
         fencei();\
-    }while(0)
+        s_interrupt_level = rt_hw_interrupt_disable();\
+    } while(0)
 
 #define FAL_EXIT_CRITICAL() do {\
         ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\
         fencei();\
         rt_exit_critical();\
-        enable_irq_from_intc();\
-    }while(0)
+        rt_hw_interrupt_enable(s_interrupt_level);\
+    } while(0)
 
 #define FAL_RAMFUNC __attribute__((section(".isr_vector")))
 

bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld

@@ -1,24 +1,26 @@
 /*
- * Copyright 2021 - 2022 hpmicro
+ * Copyright 2021-2023 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 ENTRY(_start)
 
 STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
-HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K;
 FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K;
 SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
-NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
 
 MEMORY
 {
     XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
     ILM (wx) : ORIGIN = 0, LENGTH = 256K
     DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
-    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
-    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
-    SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
 }
 
 __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
@@ -57,29 +59,33 @@ SECTIONS
         __vector_ram_end__ = .;
     } > AXI_SRAM
 
-    .fast : AT(etext + __data_end__ - __data_start__) {
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
         . = ALIGN(8);
         __ramfunc_start__ = .;
         *(.fast)
 
         /* RT-Thread Core Start */
         KEEP(*context_gcc.o(.text* .rodata*))
-        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
-        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
         KEEP(*irq.o (.text .text* .rodata .rodata*))
         KEEP(*clock.o (.text .text* .rodata .rodata*))
         KEEP(*kservice.o (.text .text* .rodata .rodata*))
         KEEP(*scheduler.o (.text .text* .rodata .rodata*))
-        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
         KEEP(*idle.o (.text .text* .rodata .rodata*))
         KEEP(*ipc.o (.text .text* .rodata .rodata*))
         KEEP(*thread.o (.text .text* .rodata .rodata*))
-		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
         KEEP(*timer.o (.text .text* .rodata .rodata*))
         KEEP(*mem.o (.text .text* .rodata .rodata*))
         KEEP(*mempool.o (.text .text* .rodata .rodata*))
         /* RT-Thread Core End */
 
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+
         . = ALIGN(8);
         __ramfunc_end__ = .;
     } > AXI_SRAM
@@ -145,7 +151,46 @@ SECTIONS
     PROVIDE (_etext = .);
     PROVIDE (etext = .);
 
-    .data : AT(etext) {
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -153,8 +198,6 @@ SECTIONS
         *(.data*)
         *(.sdata)
         *(.sdata*)
-        *(.tdata)
-        *(.tdata*)
 
         KEEP(*(.jcr))
         KEEP(*(.dynamic))
@@ -181,10 +224,12 @@ SECTIONS
         PROVIDE(__finit_array_end = .);
 
         . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
         KEEP(*crtbegin*.o(.ctors))
         KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
         KEEP(*(SORT(.ctors.*)))
         KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
 
         . = ALIGN(8);
         KEEP(*crtbegin*.o(.dtors))
@@ -196,61 +241,64 @@ SECTIONS
         PROVIDE (__edata = .);
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
-    } > SDRAM
-    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
-
-    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
-        . = ALIGN(8);
-        __noncacheable_init_start__ = .;
-        KEEP(*(.noncacheable.init))
-        __noncacheable_init_end__ = .;
-        KEEP(*(.noncacheable))
-        __noncacheable_bss_start__ = .;
-        KEEP(*(.noncacheable.bss))
-        __noncacheable_bss_end__ = .;
-        . = ALIGN(8);
-    } > SDRAM_NONCACHEABLE
-
-    .bss : {
-        . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.tbss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.tcommon*)
-        *(.dynsbss*)
-        *(COMMON)
-        . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
     } > AXI_SRAM
+    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
 
-    .heap : {
+    .heap(NOLOAD) : {
         . = ALIGN(8);
         __heap_start__ = .;
         . += HEAP_SIZE;
         __heap_end__ = .;
-    } > SDRAM
+    } > AXI_SRAM
 
     .framebuffer (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.framebuffer))
         . = ALIGN(8);
-    } > SDRAM
+    } > AXI_SRAM
 
-    .stack : {
+    .stack(NOLOAD) : {
         . = ALIGN(8);
         __stack_base__ = .;
         . += STACK_SIZE;
         . = ALIGN(8);
         PROVIDE (_stack = .);
-        PROVIDE( __rt_rvstack = . );
         PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
     } > AXI_SRAM
 
-    __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE);
-    __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE);
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+    .sdram (NOLOAD) : {
+        . = ALIGN(8);
+        __sdram_start__ = .;
+        . += SDRAM_SIZE;
+        __sdram_end__ = .;
+    } > SDRAM
 }

bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld

@@ -1,24 +1,26 @@
 /*
- * Copyright 2021 - 2022 hpmicro
+ * Copyright 2021-2023 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 ENTRY(_start)
 
 STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
-HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K;
 FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K;
 SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
-NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M;
 
 MEMORY
 {
     XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
     ILM (wx) : ORIGIN = 0, LENGTH = 256K
     DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
-    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE
     SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
-    AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
 }
 
 __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
@@ -57,34 +59,59 @@ SECTIONS
         __vector_ram_end__ = .;
     } > AXI_SRAM
 
-    .fast : AT(etext + __data_end__ - __data_start__) {
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
         . = ALIGN(8);
         __ramfunc_start__ = .;
         *(.fast)
 
         /* RT-Thread Core Start */
         KEEP(*context_gcc.o(.text* .rodata*))
-        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
-        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
         KEEP(*irq.o (.text .text* .rodata .rodata*))
         KEEP(*clock.o (.text .text* .rodata .rodata*))
         KEEP(*kservice.o (.text .text* .rodata .rodata*))
         KEEP(*scheduler.o (.text .text* .rodata .rodata*))
-        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
         KEEP(*idle.o (.text .text* .rodata .rodata*))
         KEEP(*ipc.o (.text .text* .rodata .rodata*))
         KEEP(*thread.o (.text .text* .rodata .rodata*))
-		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
         KEEP(*timer.o (.text .text* .rodata .rodata*))
         KEEP(*mem.o (.text .text* .rodata .rodata*))
         KEEP(*mempool.o (.text .text* .rodata .rodata*))
-        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
         /* RT-Thread Core End */
 
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
+        KEEP(*api_lib*.o (.text .text* .rodata .rodata*))
+        KEEP(*api_msg*.o (.text .text* .rodata .rodata*))
+        KEEP(*if_api*.o (.text .text* .rodata .rodata*))
+        KEEP(*netbuf*.o (.text .text* .rodata .rodata*))
+        KEEP(*netdb*.o (.text .text* .rodata .rodata*))
+        KEEP(*netifapi*.o (.text .text* .rodata .rodata*))
+        KEEP(*sockets*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcpip*.o (.text .text* .rodata .rodata*))
+        KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*))
+        KEEP(*ip*.o (.text .text* .rodata .rodata*))
+        KEEP(*memp*.o (.text .text* .rodata .rodata*))
+        KEEP(*netif*.o (.text .text* .rodata .rodata*))
+        KEEP(*pbuf*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcp_in*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcp_out*.o (.text .text* .rodata .rodata*))
+        KEEP(*tcp*.o (.text .text* .rodata .rodata*))
+        KEEP(*ethernet*.o (.text .text* .rodata .rodata*))
+        KEEP(*ethernetif*.o (.text .text* .rodata .rodata*))
+
         . = ALIGN(8);
         __ramfunc_end__ = .;
     } > AXI_SRAM
 
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+    
     .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : {
         . = ALIGN(8);
         *(.text)
@@ -146,7 +173,42 @@ SECTIONS
     PROVIDE (_etext = .);
     PROVIDE (etext = .);
 
-    .data : AT(etext) {
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: the .tbss and .tdata section should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -154,8 +216,6 @@ SECTIONS
         *(.data*)
         *(.sdata)
         *(.sdata*)
-        *(.tdata)
-        *(.tdata*)
 
         KEEP(*(.jcr))
         KEEP(*(.dynamic))
@@ -182,10 +242,12 @@ SECTIONS
         PROVIDE(__finit_array_end = .);
 
         . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
         KEEP(*crtbegin*.o(.ctors))
         KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
         KEEP(*(SORT(.ctors.*)))
         KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
 
         . = ALIGN(8);
         KEEP(*crtbegin*.o(.dtors))
@@ -197,60 +259,64 @@ SECTIONS
         PROVIDE (__edata = .);
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
-    } > SDRAM
-    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
-
-    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
-        . = ALIGN(8);
-        __noncacheable_init_start__ = .;
-        KEEP(*(.noncacheable.init))
-        __noncacheable_init_end__ = .;
-        KEEP(*(.noncacheable))
-        __noncacheable_bss_start__ = .;
-        KEEP(*(.noncacheable.bss))
-        __noncacheable_bss_end__ = .;
-        . = ALIGN(8);
-    } > AXI_SRAM_NONCACHEABLE
-
-    .bss : {
-        . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.tbss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.tcommon*)
-        *(.dynsbss*)
-        *(COMMON)
-        . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
     } > AXI_SRAM
+    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
 
-    .heap : {
+    .heap(NOLOAD) : {
         . = ALIGN(8);
         __heap_start__ = .;
         . += HEAP_SIZE;
         __heap_end__ = .;
-    } > SDRAM
+    } > AXI_SRAM
 
     .framebuffer (NOLOAD) : {
         . = ALIGN(8);
         KEEP(*(.framebuffer))
         . = ALIGN(8);
-    } > SDRAM
+    } > AXI_SRAM
 
-    .stack : {
+    .stack(NOLOAD) : {
         . = ALIGN(8);
         __stack_base__ = .;
         . += STACK_SIZE;
         . = ALIGN(8);
         PROVIDE (_stack = .);
         PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
     } > AXI_SRAM
 
-    __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE);
-    __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE);
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+    .sdram (NOLOAD) : {
+        . = ALIGN(8);
+        __sdram_start__ = .;
+        . += SDRAM_SIZE;
+        __sdram_end__ = .;
+    } > SDRAM
 }

bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld → bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021 - 2022 hpmicro
+ * Copyright 2021-2023 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
@@ -9,16 +9,18 @@ STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
 HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
 FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M;
 SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
-NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 1M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
 
 MEMORY
 {
     XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE
     ILM (wx) : ORIGIN = 0, LENGTH = 256K
     DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
-    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K
-    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
-    AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01100000, LENGTH = NONCACHEABLE_SIZE
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
 }
 
 __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400;
@@ -57,29 +59,32 @@ SECTIONS
         __vector_ram_end__ = .;
     } > AXI_SRAM
 
-    .fast : AT(etext + __data_end__ - __data_start__) {
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
         . = ALIGN(8);
         __ramfunc_start__ = .;
         *(.fast)
 
         /* RT-Thread Core Start */
         KEEP(*context_gcc.o(.text* .rodata*))
-        KEEP(*cpuport.o (.text .text* .rodata .rodata*))
-        KEEP(*trap_entry.o (.text .text* .rodata .rodata*))
+        KEEP(*port*.o (.text .text* .rodata .rodata*))
+        KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*))
+        KEEP(*trap_common.o (.text .text* .rodata .rodata*))
         KEEP(*irq.o (.text .text* .rodata .rodata*))
         KEEP(*clock.o (.text .text* .rodata .rodata*))
         KEEP(*kservice.o (.text .text* .rodata .rodata*))
         KEEP(*scheduler.o (.text .text* .rodata .rodata*))
-        KEEP(*trap.o (.text .text* .rodata .rodata*))
+        KEEP(*trap*.o (.text .text* .rodata .rodata*))
         KEEP(*idle.o (.text .text* .rodata .rodata*))
         KEEP(*ipc.o (.text .text* .rodata .rodata*))
         KEEP(*thread.o (.text .text* .rodata .rodata*))
-		KEEP(*object.o (.text .text* .rodata .rodata*))
+        KEEP(*object.o (.text .text* .rodata .rodata*))
         KEEP(*timer.o (.text .text* .rodata .rodata*))
         KEEP(*mem.o (.text .text* .rodata .rodata*))
         KEEP(*mempool.o (.text .text* .rodata .rodata*))
-        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
         /* RT-Thread Core End */
+        
+        /* HPMicro Driver Wrapper */
+        KEEP(*drv_*.o (.text .text* .rodata .rodata*))
 
         . = ALIGN(8);
         __ramfunc_end__ = .;
@@ -146,7 +151,45 @@ SECTIONS
     PROVIDE (_etext = .);
     PROVIDE (etext = .);
 
-    .data : AT(etext) {
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -154,8 +197,6 @@ SECTIONS
         *(.data*)
         *(.sdata)
         *(.sdata*)
-        *(.tdata)
-        *(.tdata*)
 
         KEEP(*(.jcr))
         KEEP(*(.dynamic))
@@ -182,10 +223,12 @@ SECTIONS
         PROVIDE(__finit_array_end = .);
 
         . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
         KEEP(*crtbegin*.o(.ctors))
         KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
         KEEP(*(SORT(.ctors.*)))
         KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
 
         . = ALIGN(8);
         KEEP(*crtbegin*.o(.dtors))
@@ -197,39 +240,36 @@ SECTIONS
         PROVIDE (__edata = .);
         PROVIDE (_edata = .);
         PROVIDE (edata = .);
-    } > SDRAM
-    __fw_size__ = __data_end__ - __data_start__ + etext - __app_load_addr__;
+    } > AXI_SRAM
+    __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__;
 
-    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
         . = ALIGN(8);
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
         __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
         KEEP(*(.noncacheable))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
         __noncacheable_bss_end__ = .;
         . = ALIGN(8);
-    } > AXI_SRAM_NONCACHEABLE
+    } > NONCACHEABLE_RAM
+
+    .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
 
-    .bss : {
-        . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.tbss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.tcommon*)
-        *(.dynsbss*)
-        *(COMMON)
-        . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
-    } > AXI_SRAM
 
-    .heap : {
+    .heap(NOLOAD) : {
         . = ALIGN(8);
         __heap_start__ = .;
         . += HEAP_SIZE;
@@ -242,15 +282,16 @@ SECTIONS
         . = ALIGN(8);
     } > SDRAM
 
-    .stack : {
+    .stack(NOLOAD) : {
         . = ALIGN(8);
         __stack_base__ = .;
         . += STACK_SIZE;
         . = ALIGN(8);
         PROVIDE (_stack = .);
         PROVIDE (_stack_in_dlm = .);
+        PROVIDE( __rt_rvstack = . );
     } > AXI_SRAM
 
-    __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE);
-    __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE);
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
 }

bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld

@@ -1,30 +1,33 @@
 /*
- * Copyright 2021 - 2022 hpmicro
+ * Copyright 2021-2023 HPMicro
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 ENTRY(_start)
 
 STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
-HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 1M;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K;
 SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
-NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K;
 
 MEMORY
 {
     ILM (wx) : ORIGIN = 0, LENGTH = 256K
     DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
-    /* It's alias address of core0 ILM+DLM, but accessing via system bus */
-    CORE0_LM_SLV (wx) : ORIGIN = 0x1000000, LENGTH = 512K
-    /* It's alias address of core1 ILM+DLM, but accessing via system bus */
-    CORE1_LM_SLV (wx) : ORIGIN = 0x1180000, LENGTH = 512K
-    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
-    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
-    NONCACHEABLE (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
 }
 
 SECTIONS
 {
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > AXI_SRAM
+
     .vectors : {
         . = ALIGN(8);
         KEEP(*(.isr_vector))
@@ -32,11 +35,6 @@ SECTIONS
         . = ALIGN(8);
     } > AXI_SRAM
 
-    .start : {
-        . = ALIGN(8);
-        KEEP(*(.start))
-    } > AXI_SRAM
-
     .text : {
         . = ALIGN(8);
         *(.text)
@@ -98,8 +96,46 @@ SECTIONS
         KEEP(*(.rel*))
     } > AXI_SRAM
 
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
 
-    .data : AT(etext) {
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > DLM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > DLM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > DLM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
         . = ALIGN(8);
         __data_start__ = .;
         __global_pointer$ = . + 0x800;
@@ -107,15 +143,13 @@ SECTIONS
         *(.data*)
         *(.sdata)
         *(.sdata*)
-        *(.tdata)
-        *(.tdata*)
 
         KEEP(*(.jcr))
         KEEP(*(.dynamic))
         KEEP(*(.got*))
         KEEP(*(.got))
-        KEEP(*(.gcc_execpt_table))
-        KEEP(*(.gcc_execpt_table.*))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
 
         . = ALIGN(8);
         PROVIDE(__preinit_array_start = .);
@@ -135,10 +169,12 @@ SECTIONS
         PROVIDE(__finit_array_end = .);
 
         . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
         KEEP(*crtbegin*.o(.ctors))
         KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
         KEEP(*(SORT(.ctors.*)))
         KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
 
         . = ALIGN(8);
         KEEP(*crtbegin*.o(.dtors))
@@ -153,62 +189,71 @@ SECTIONS
         PROVIDE (edata = .);
     } > DLM
 
-    .fast : AT(etext + __data_end__ - __data_start__) {
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
         . = ALIGN(8);
         PROVIDE(__ramfunc_start__ = .);
         *(.fast)
         . = ALIGN(8);
         PROVIDE(__ramfunc_end__ = .);
     } > AXI_SRAM
-    
-    .noncacheable : AT(etext + __data_end__ - __data_start__ + __ramfunc_end__ - __ramfunc_start__){
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
         . = ALIGN(8);
         __noncacheable_init_start__ = .;
         KEEP(*(.noncacheable.init))
         __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
         KEEP(*(.noncacheable))
         __noncacheable_bss_start__ = .;
         KEEP(*(.noncacheable.bss))
         __noncacheable_bss_end__ = .;
         . = ALIGN(8);
-    } > NONCACHEABLE
-    __noncacheable_start__ = ORIGIN(NONCACHEABLE);
-    __noncacheable_end__ = ORIGIN(NONCACHEABLE) + LENGTH(NONCACHEABLE);
+    } > NONCACHEABLE_RAM
 
-    .bss : {
-        . = ALIGN(8);
-        __bss_start__ = .;
-        *(.bss)
-        *(.bss*)
-        *(.tbss*)
-        *(.sbss*)
-        *(.scommon)
-        *(.scommon*)
-        *(.tcommon*)
-        *(.dynsbss*)
-        *(COMMON)
-        . = ALIGN(8);
-        _end = .;
-        __bss_end__ = .;
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+     .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
     } > DLM
 
-    .stack : {
+    .stack(NOLOAD) : {
         . = ALIGN(8);
         __stack_base__ = .;
         . += STACK_SIZE;
         PROVIDE (_stack = .);
         PROVIDE (_stack_in_dlm = .);
+        PROVIDE (__rt_rvstack = .);
     } > DLM
 
     .framebuffer (NOLOAD) : {
         KEEP(*(.framebuffer))
-    } > SDRAM
+    } > AXI_SRAM
 
-    .heap : {
+    .heap (NOLOAD) : {
         . = ALIGN(8);
         __heap_start__ = .;
         . += HEAP_SIZE;
         __heap_end__ = .;
 
+    } > AXI_SRAM
+
+    .sdram (NOLOAD) : {
+        . = ALIGN(8);
+        __sdram_start__ = .;
+        . += SDRAM_SIZE;
+        __sdram_end__ = .;
     } > SDRAM
 }

bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld

@@ -0,0 +1,252 @@
+/*
+ * Copyright 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ENTRY(_start)
+
+STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000;
+HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K;
+SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M;
+NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M;
+
+MEMORY
+{
+    ILM (wx) : ORIGIN = 0, LENGTH = 256K
+    DLM (w) : ORIGIN = 0x80000, LENGTH = 256K
+    AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K
+    NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE
+    SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE
+    AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k
+    APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k
+}
+
+SECTIONS
+{
+    .start : {
+        . = ALIGN(8);
+        KEEP(*(.start))
+    } > AXI_SRAM
+
+    .vectors : {
+        . = ALIGN(8);
+        KEEP(*(.isr_vector))
+        KEEP(*(.vector_table))
+        . = ALIGN(8);
+    } > AXI_SRAM
+
+    .text : {
+        . = ALIGN(8);
+        *(.text)
+        *(.text*)
+        *(.rodata)
+        *(.rodata*)
+        *(.srodata)
+        *(.srodata*)
+
+        *(.hash)
+        *(.dyn*)
+        *(.gnu*)
+        *(.pl*)
+        *(FalPartTable)
+
+        KEEP(*(.eh_frame))
+        *(.eh_frame*)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+        . = ALIGN(8);
+
+        /*********************************************
+         *
+         *      RT-Thread related sections - Start
+         *
+        *********************************************/
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* RT-Thread related sections - end */
+
+        PROVIDE (__etext = .);
+        PROVIDE (_etext = .);
+        PROVIDE (etext = .);
+    } > AXI_SRAM
+
+    .rel : {
+        KEEP(*(.rel*))
+    } > AXI_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .bss(NOLOAD) : {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss*)
+        *(.scommon)
+        *(.scommon*)
+        *(.dynsbss*)
+        *(COMMON)
+        . = ALIGN(8);
+        _end = .;
+        __bss_end__ = .;
+    } > AXI_SRAM
+
+    /* Note: .tbss and .tdata should be adjacent */
+    .tbss(NOLOAD) : {
+        . = ALIGN(8);
+        __tbss_start__ = .;
+        *(.tbss*)
+        *(.tcommon*)
+        _end = .;
+        __tbss_end__ = .;
+    } > AXI_SRAM
+
+    .tdata : AT(etext) {
+        . = ALIGN(8);
+        __tdata_start__ = .;
+        __thread_pointer = .;
+        *(.tdata)
+        *(.tdata*)
+        . = ALIGN(8);
+        __tdata_end__ = .;
+    } > AXI_SRAM
+
+    .data : AT(etext + __tdata_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        __data_start__ = .;
+        __global_pointer$ = . + 0x800;
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+        KEEP(*(.jcr))
+        KEEP(*(.dynamic))
+        KEEP(*(.got*))
+        KEEP(*(.got))
+        KEEP(*(.gcc_except_table))
+        KEEP(*(.gcc_except_table.*))
+
+        . = ALIGN(8);
+        PROVIDE(__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE(__preinit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__init_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__init_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__finit_array_start = .);
+        KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*)))
+        KEEP(*(.finit_array))
+        PROVIDE(__finit_array_end = .);
+
+        . = ALIGN(8);
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*crtbegin*.o(.ctors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors))
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(8);
+        KEEP(*crtbegin*.o(.dtors))
+        KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors))
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+
+        . = ALIGN(8);
+        __data_end__ = .;
+        PROVIDE (__edata = .);
+        PROVIDE (_edata = .);
+        PROVIDE (edata = .);
+    } > AXI_SRAM
+
+    .fast : AT(etext + __data_end__ - __tdata_start__) {
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_start__ = .);
+        *(.fast)
+        . = ALIGN(8);
+        PROVIDE(__ramfunc_end__ = .);
+    } > AXI_SRAM
+
+    .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) {
+        . = ALIGN(8);
+        __noncacheable_init_start__ = .;
+        KEEP(*(.noncacheable.init))
+        __noncacheable_init_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    .noncacheable.bss (NOLOAD) : {
+        . = ALIGN(8);
+        KEEP(*(.noncacheable))
+        __noncacheable_bss_start__ = .;
+        KEEP(*(.noncacheable.bss))
+        __noncacheable_bss_end__ = .;
+        . = ALIGN(8);
+    } > NONCACHEABLE_RAM
+
+    __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM);
+    __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM);
+
+     .ahb_sram (NOLOAD) : {
+        KEEP(*(.ahb_sram))
+    } > AHB_SRAM
+
+    .apb_sram (NOLOAD) : {
+        KEEP(*(.backup_sram))
+    } > APB_SRAM
+
+    .fast_ram (NOLOAD) : {
+        KEEP(*(.fast_ram))
+    } > DLM
+
+    .stack(NOLOAD) : {
+        . = ALIGN(8);
+        __stack_base__ = .;
+        . += STACK_SIZE;
+        PROVIDE (_stack = .);
+        PROVIDE (_stack_in_dlm = .);
+        PROVIDE (__rt_rvstack = .);
+    } > AXI_SRAM
+
+    .framebuffer (NOLOAD) : {
+        KEEP(*(.framebuffer))
+    } > SDRAM
+
+    .heap (NOLOAD) : {
+        . = ALIGN(8);
+        __heap_start__ = .;
+        . += HEAP_SIZE;
+        __heap_end__ = .;
+
+    } > SDRAM
+}

bsp/hpmicro/hpm6750evk/board/pinmux.c

@@ -1,10 +1,18 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
  *
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */
 
+/*
+ * Note:
+ *   PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
+ *  besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
+ *  expected SoC function can be enabled on these IOs.
+ *
+ */
+
 #include "board.h"
 
 void init_uart_pins(UART_Type *ptr)
@@ -12,14 +20,16 @@ void init_uart_pins(UART_Type *ptr)
     if (ptr == HPM_UART0) {
         HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
         HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
-        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
-        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
+        /* PY port IO needs to configure PIOC as well */
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
     } else if (ptr == HPM_UART2) {
         HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD;
         HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD;
     } else if (ptr == HPM_UART13) {
         HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD;
         HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD;
+        /* PZ port IO needs to configure BIOC as well */
         HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08;
         HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09;
     }
@@ -83,11 +93,13 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr)
     if (ptr == HPM_I2C0) {
         /* I2C0 */
         HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11;
-        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
         HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10;
+        /* PZ port IO needs to configure BIOC as well */
+        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
         HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3;
     } else {
-        while(1);
+        while (1) {
+        }
     }
 }
 
@@ -98,12 +110,14 @@ void init_i2c_pins(I2C_Type *ptr)
                                             | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
         HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA
                                             | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        /* PZ port IO needs to configure BIOC as well */
         HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
         HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3;
         HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
         HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
     } else {
-        while(1);
+        while (1) {
+        }
     }
 }
 
@@ -239,16 +253,18 @@ void init_i2s_pins(I2S_Type *ptr)
 void init_dao_pins(void)
 {
     HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P;
-    HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08;
     HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N;
+    /* PY port IO needs to configure PIOC */
+    HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08;
     HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09;
 }
 
 void init_pdm_pins(void)
 {
     HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK;
-    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10;
     HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0;
+    /* PY port IO needs to configure PIOC */
+    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10;
     HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11;
 }
 
@@ -260,10 +276,10 @@ void init_vad_pins(void)
 
 void init_cam_pins(void)
 {
-#ifdef CAMREA_RESET_PWDN_CONFIGURABLE
-    HPM_IOC->PAD[IOC_PAD_PX08].FUNC_CTL = IOC_PX08_FUNC_CTL_GPIO_X_08;
-    HPM_IOC->PAD[IOC_PAD_PX09].FUNC_CTL = IOC_PX09_FUNC_CTL_GPIO_X_09;
-#endif
+    /* configure rst pin function */
+    HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05;
+    /* PY port IO needs to configure PIOC */
+    HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05;
 
     HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK;
     HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK;
@@ -401,9 +417,9 @@ void init_can_pins(CAN_Type *ptr)
     }
 }
 
-void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8)
+void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
 {
-    uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);;
+    uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
     uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17);
     uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) |
                        IOC_PAD_PAD_CTL_PS_SET(1);
@@ -435,10 +451,27 @@ void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8)
         HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
         HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl;
         HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN;
-
     }
 }
 
+void init_sdxc_power_pin(SDXC_Type *ptr)
+{
+    /* Not supported by current board */
+}
+void init_sdxc_vsel_pin(SDXC_Type *ptr)
+{
+    /* Not suppored by current board */
+}
+
+void init_sdxc_card_detection_pin(SDXC_Type *ptr)
+{
+    /* CDN */
+    HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
+    HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) |
+                       IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN;
+}
+
 void init_clk_obs_pins(void)
 {
     HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0;