[bsp][stm32] fix bug in dma config && clean up the dma config code

bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
  */
 
 #ifndef __DMA_CONFIG_H__
@@ -13,30 +14,24 @@
 
 #include <rtthread.h>
 
-/* dma1 channel1  */
-
-/* dma1 channel1 */
-
-/* dma1 channel2-3 DMA2 channel1-2 */
-#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL)
-#define USART1_DMA_RX_IRQHandler          DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
-#define USART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define USART1_RX_DMA_INSTANCE            DMA1_Channel3
-#define USART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+/* DMA1 channel1  */
 
+/* DMA1 channel2-3 DMA2 channel1-2 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel3
+#define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
 #endif
-/* dma1 channel2-3 DMA2 channel1-2 */
-
-/* dma1 channel4-7 DMA2 channel3-5 */
-#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
-#define USART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
-#define USART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define USART2_RX_DMA_INSTANCE            DMA1_Channel5
-#define USART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMA2_Ch3_5_IRQn
-
+/* DMA1 channel2-3 DMA2 channel1-2 */
+
+/* DMA1 channel4-7 DMA2 channel3-5 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMA2_Ch3_5_IRQn
 #endif
-/* dma1 channel4-7 DMA2 channel3-5 */
-
-
+/* DMA1 channel4-7 DMA2 channel3-5 */
 
 #endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h

@@ -28,9 +28,9 @@
 #ifndef UART1_DMA_CONFIG
 #define UART1_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART1_RX_DMA_INSTANCE,                         \
-        .dma_rcc = USART1_RX_DMA_RCC,                               \
-        .dma_irq = USART1_RX_DMA_IRQ,                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */
@@ -50,9 +50,9 @@
 #ifndef UART2_DMA_CONFIG
 #define UART2_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART2_RX_DMA_INSTANCE,                         \
-        .dma_rcc = USART2_RX_DMA_RCC,                               \
-        .dma_irq = USART2_RX_DMA_IRQ,                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
     }
 #endif /* UART2_DMA_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */

bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-01-02     SummerGift   first version
+ * 2019-01-08     SummerGift   clean up the code
  */
 
 #ifndef __DMA_CONFIG_H__
@@ -15,7 +16,7 @@
 
 /* DMA1 channel1 */
 /* DMA1 channel2 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
 #define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
 #define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
@@ -23,21 +24,20 @@
 #endif
 
 /* DMA1 channel3 */
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
 #define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
 #define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
 #define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
-
-#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL)
-#define USART3_DMA_RX_IRQHandler          DMA1_Channel3_IRQHandler
-#define USART3_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define USART3_RX_DMA_INSTANCE            DMA1_Channel3
-#define USART3_RX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
 #endif
 
 /* DMA1 channel4 */
-#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL)
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
 #define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
 #define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
@@ -45,32 +45,31 @@
 #endif
 
 /* DMA1 channel5 */
-#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL)
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
 #define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
 #define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
 #define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
 
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL)
-#define USART1_DMA_RX_IRQHandler          DMA1_Channel5_IRQHandler
-#define USART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
-#define USART1_RX_DMA_INSTANCE           DMA1_Channel5
-#define USART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
 #endif
 
 /* DMA1 channel6 */
-#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
-#define USART2_DMA_RX_IRQHandler          DMA1_Channel6_IRQHandler
-#define USART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
-#define USART2_RX_DMA_INSTANCE            DMA1_Channel6
-#define USART2_RX_DMA_IRQ                 DMA1_Channel6_IRQn
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
 #endif
 
-
 /* DMA1 channel7 */
 
 /* DMA2 channel1 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
 #define SPI3_DMA_RX_IRQHandler          DMA2_Channel1_IRQHandler
 #define SPI3_RX_DMA_RCC                 RCC_AHBENR_DMA2EN
 #define SPI3_RX_DMA_INSTANCE            DMA2_Channel1
@@ -78,12 +77,11 @@
 #endif
 
 /* DMA2 channel2 */
-#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
 #define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
 #define SPI3_TX_DMA_RCC                 RCC_AHBENR_DMA2EN
 #define SPI3_TX_DMA_INSTANCE            DMA2_Channel2
 #define SPI3_TX_DMA_IRQ                 DMA2_Channel2_IRQn
-/* DMA1 channel4 */
 #endif
 
 /* DMA2 channel3 */

bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h

@@ -30,9 +30,9 @@
 #ifndef UART1_DMA_CONFIG
 #define UART1_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART1_RX_DMA_INSTANCE,                         \
-        .dma_rcc = USART1_RX_DMA_RCC,                               \
-        .dma_irq = USART1_RX_DMA_IRQ,                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */
@@ -52,9 +52,9 @@
 #ifndef UART2_DMA_CONFIG
 #define UART2_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART2_RX_DMA_INSTANCE,                         \
-        .dma_rcc = USART2_RX_DMA_RCC,                               \
-        .dma_irq = USART2_RX_DMA_IRQ,                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
     }
 #endif /* UART2_DMA_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
@@ -74,9 +74,9 @@
 #ifndef UART3_DMA_CONFIG
 #define UART3_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART3_RX_DMA_INSTANCE,                         \
-        .dma_rcc = USART3_RX_DMA_RCC,                               \
-        .dma_irq = USART3_RX_DMA_IRQ,                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
     }
 #endif /* UART3_DMA_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
@@ -96,9 +96,9 @@
 #ifndef UART4_DMA_CONFIG
 #define UART4_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART4_RX_DMA_INSTANCE,                         \
-        .dma_rcc = USART4_RX_DMA_RCC,                               \
-        .dma_irq = USART4_RX_DMA_IRQ,                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
     }
 #endif /* UART4_DMA_CONFIG */
 #endif /* BSP_UART4_RX_USING_DMA */

bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h

@@ -5,7 +5,8 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-01-02     zylx         first version
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
  */
 
 #ifndef __DMA_CONFIG_H__
@@ -13,255 +14,196 @@
 
 #include <rtthread.h>
 
-/* dma1 stream0 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
-
-#define SPI3_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
-#define SPI3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_RX_DMA_INSTANCE            DMA1_Stream0
-#define SPI3_RX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_RX_DMA_IRQ                 DMA1_Stream0_IRQn
-
-#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL)
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
 #define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
 #define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART5_RX_DMA_INSTANCE            DMA1_Stream0
 #define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
-
 #endif
-/* dma1 stream0 */
 
-/* dma1 stream1 */
-#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL)
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
 #define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
 #define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART3_RX_DMA_INSTANCE            DMA1_Stream1
 #define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
-
 #endif
-/* dma1 stream1 */
-
-/* dma1 stream2 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
-
-#define SPI3_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
-#define SPI3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_RX_DMA_INSTANCE            DMA1_Stream2
-#define SPI3_RX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_RX_DMA_IRQ                 DMA1_Stream2_IRQn
 
-#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL)
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
 #define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
 #define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART4_RX_DMA_INSTANCE            DMA1_Stream2
 #define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
-
 #endif
-/* dma1 stream2 */
-
-/* dma1 stream3 */
-#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL)
-
-#define SPI2_DMA_RX_IRQHandler          DMA1_Stream3_IRQHandler
-#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI2_RX_DMA_INSTANCE            DMA1_Stream3
-#define SPI2_RX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI2_RX_DMA_IRQ                 DMA1_Stream3_IRQn
 
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
 #endif
-/* dma1 stream3 */
-
-/* dma1 stream4 */
-#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL)
-
-#define SPI2_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
-#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI2_TX_DMA_INSTANCE            DMA1_Stream4
-#define SPI2_TX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI2_TX_DMA_IRQ                 DMA1_Stream4_IRQn
 
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
 #endif
-/* dma1 stream4 */
-
-/* dma1 stream5 */
-#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
 
-#define SPI3_DMA_TX_IRQHandler          DMA1_Stream5_IRQHandler
-#define SPI3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_TX_DMA_INSTANCE            DMA1_Stream5
-#define SPI3_TX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_TX_DMA_IRQ                 DMA1_Stream5_IRQn
-
-#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
 #define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
 #define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART2_RX_DMA_INSTANCE            DMA1_Stream5
 #define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
-
 #endif
-/* dma1 stream5 */
-
-/* dma1 stream6 */
-/* dma1 stream6 */
 
-/* dma1 stream7 */
-#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
-
-#define SPI3_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
-#define SPI3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_TX_DMA_INSTANCE            DMA1_Stream7
-#define SPI3_TX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+/* DMA1 stream6 */
 
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
 #endif
-/* dma1 stream7 */
-
-/* dma2 stream0 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
-
-#define SPI1_DMA_RX_IRQHandler          DMA2_Stream0_IRQHandler
-#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_RX_DMA_INSTANCE            DMA2_Stream0
-#define SPI1_RX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_RX_DMA_IRQ                 DMA2_Stream0_IRQn
-
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL)
-
-#define SPI4_DMA_TX_IRQHandler          DMA2_Stream0_IRQHandler
-#define SPI4_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE            DMA2_Stream0
-#define SPI4_TX_DMA_CHANNEL             DMA_CHANNEL_4
-#define SPI4_TX_DMA_IRQ                 DMA2_Stream0_IRQn
 
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
-/* dma2 stream0 */
-
-/* dma2 stream1 */
-#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL)
-
-#define SPI4_DMA_TX_IRQHandler          DMA2_Stream1_IRQHandler
-#define SPI4_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE            DMA2_Stream1
-#define SPI4_TX_DMA_CHANNEL             DMA_CHANNEL_4
-#define SPI4_TX_DMA_IRQ                 DMA2_Stream1_IRQn
 
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
 #endif
-/* dma2 stream1 */
-
-/* dma2 stream2 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
-
-#define SPI1_DMA_RX_IRQHandler          DMA2_Stream2_IRQHandler
-#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_RX_DMA_INSTANCE            DMA2_Stream2
-#define SPI1_RX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_RX_DMA_IRQ                 DMA2_Stream2_IRQn
-
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL)
-
-#define USART1_DMA_RX_IRQHandler          DMA2_Stream2_IRQHandler
-#define USART1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define USART1_RX_DMA_INSTANCE            DMA2_Stream2
-#define USART1_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define USART1_RX_DMA_IRQ                 DMA2_Stream2_IRQn
 
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
+#define USART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define USART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define USART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define USART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define USART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
 #endif
-/* dma2 stream2 */
-
-/* dma2 stream3 */
-#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL)
-
-#define SPI5_DMA_RX_IRQHandler          DMA2_Stream3_IRQHandler
-#define SPI5_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE            DMA2_Stream3
-#define SPI5_RX_DMA_CHANNEL             DMA_CHANNEL_2
-#define SPI5_RX_DMA_IRQ                 DMA2_Stream3_IRQn
-
-#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
-
-#define SPI1_DMA_TX_IRQHandler          DMA2_Stream3_IRQHandler
-#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_TX_DMA_INSTANCE            DMA2_Stream3
-#define SPI1_TX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_TX_DMA_IRQ                 DMA2_Stream3_IRQn
-
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL)
-
-#define SPI4_DMA_TX_IRQHandler          DMA2_Stream3_IRQHandler
-#define SPI4_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE            DMA2_Stream3
-#define SPI4_TX_DMA_CHANNEL             DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                 DMA2_Stream3_IRQn
 
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
 #endif
-/* dma2 stream3 */
-
-/* dma2 stream4 */
-#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL)
-
-#define SPI5_DMA_TX_IRQHandler          DMA2_Stream4_IRQHandler
-#define SPI5_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_TX_DMA_INSTANCE            DMA2_Stream4
-#define SPI5_TX_DMA_CHANNEL             DMA_CHANNEL_2
-#define SPI5_TX_DMA_IRQ                 DMA2_Stream4_IRQn
-
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL)
-
-#define SPI4_DMA_TX_IRQHandler          DMA2_Stream4_IRQHandler
-#define SPI4_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE            DMA2_Stream4
-#define SPI4_TX_DMA_CHANNEL             DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                 DMA2_Stream4_IRQn
 
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
 #endif
-/* dma2 stream4 */
-
-/* dma2 stream5 */
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
-
-#define SPI1_DMA_TX_IRQHandler          DMA2_Stream5_IRQHandler
-#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_TX_DMA_INSTANCE            DMA2_Stream5
-#define SPI1_TX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_TX_DMA_IRQ                 DMA2_Stream5_IRQn
-
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL)
-
-#define USART1_DMA_RX_IRQHandler          DMA2_Stream5_IRQHandler
-#define USART1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define USART1_RX_DMA_INSTANCE            DMA2_Stream5
-#define USART1_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define USART1_RX_DMA_IRQ                 DMA2_Stream5_IRQn
-
-#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL)
-
-#define SPI5_DMA_RX_IRQHandler          DMA2_Stream5_IRQHandler
-#define SPI5_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE            DMA2_Stream5
-#define SPI5_RX_DMA_CHANNEL             DMA_CHANNEL_7
-#define SPI5_RX_DMA_IRQ                 DMA2_Stream5_IRQn
 
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
+#define USART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define USART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define USART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define USART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define USART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
 #endif
 
-/* dma2 stream5 */
-
-/* dma2 stream6 */
-#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL)
-
-#define SPI5_DMA_TX_IRQHandler          DMA2_Stream6_IRQHandler
-#define SPI5_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_TX_DMA_INSTANCE            DMA2_Stream6
-#define SPI5_TX_DMA_CHANNEL             DMA_CHANNEL_7
-#define SPI5_TX_DMA_IRQ                 DMA2_Stream6_IRQn
-
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
 #endif
-/* dma2 stream6 */
 
-/* dma2 stream7 */
-/* dma2 stream7 */
+/* DMA2 stream7 */
+
 
 #endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h

@@ -5,7 +5,8 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-01-02     zylx         first version
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
  */
 
 #ifndef __DMA_CONFIG_H__
@@ -13,273 +14,208 @@
 
 #include <rtthread.h>
 
-/* dma1 stream0 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
-
-#define SPI3_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
-#define SPI3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_RX_DMA_INSTANCE            DMA1_Stream0
-#define SPI3_RX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_RX_DMA_IRQ                 DMA1_Stream0_IRQn
-
-#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL)
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
 #define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
 #define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART5_RX_DMA_INSTANCE            DMA1_Stream0
 #define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
-
 #endif
-/* dma1 stream0 */
 
-/* dma1 stream1 */
-#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL)
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
 #define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
 #define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART3_RX_DMA_INSTANCE            DMA1_Stream1
 #define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
-
 #endif
-/* dma1 stream1 */
 
-/* dma1 stream2 */
-#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
-
-#define SPI3_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
-#define SPI3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_RX_DMA_INSTANCE            DMA1_Stream2
-#define SPI3_RX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_RX_DMA_IRQ                 DMA1_Stream2_IRQn
-
-#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL)
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
 #define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
 #define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART4_RX_DMA_INSTANCE            DMA1_Stream2
 #define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
-
 #endif
-/* dma1 stream2 */
-
-/* dma1 stream3 */
-#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL)
-
-#define SPI2_DMA_RX_IRQHandler          DMA1_Stream3_IRQHandler
-#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI2_RX_DMA_INSTANCE            DMA1_Stream3
-#define SPI2_RX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI2_RX_DMA_IRQ                 DMA1_Stream3_IRQn
 
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
 #endif
-/* dma1 stream3 */
-
-/* dma1 stream4 */
-#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL)
-
-#define SPI2_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
-#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI2_TX_DMA_INSTANCE            DMA1_Stream4
-#define SPI2_TX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI2_TX_DMA_IRQ                 DMA1_Stream4_IRQn
 
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
 #endif
-/* dma1 stream4 */
-
-/* dma1 stream5 */
-#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
 
-#define SPI3_DMA_TX_IRQHandler          DMA1_Stream5_IRQHandler
-#define SPI3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_TX_DMA_INSTANCE            DMA1_Stream5
-#define SPI3_TX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_TX_DMA_IRQ                 DMA1_Stream5_IRQn
 
-#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
 #define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
 #define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define UART2_RX_DMA_INSTANCE            DMA1_Stream5
 #define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
 #define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
-
 #endif
-/* dma1 stream5 */
 
-/* dma1 stream6 */
-/* dma1 stream6 */
-
-/* dma1 stream7 */
-#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
-
-#define SPI3_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
-#define SPI3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
-#define SPI3_TX_DMA_INSTANCE            DMA1_Stream7
-#define SPI3_TX_DMA_CHANNEL             DMA_CHANNEL_0
-#define SPI3_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+/* DMA1 stream6 */
 
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
 #endif
-/* dma1 stream7 */
-
-/* dma2 stream0 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
-
-#define SPI1_DMA_RX_IRQHandler          DMA2_Stream0_IRQHandler
-#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_RX_DMA_INSTANCE            DMA2_Stream0
-#define SPI1_RX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_RX_DMA_IRQ                 DMA2_Stream0_IRQn
-
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL)
-
-#define SPI4_DMA_RX_IRQHandler          DMA2_Stream0_IRQHandler
-#define SPI4_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE            DMA2_Stream0
-#define SPI4_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define SPI4_RX_DMA_IRQ                 DMA2_Stream0_IRQn
 
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
-/* dma2 stream0 */
-
-/* dma2 stream1 */
-#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL)
-
-#define SPI4_DMA_TX_IRQHandler          DMA2_Stream1_IRQHandler
-#define SPI4_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE            DMA2_Stream1
-#define SPI4_TX_DMA_CHANNEL             DMA_CHANNEL_4
-#define SPI4_TX_DMA_IRQ                 DMA2_Stream1_IRQn
 
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
 #endif
-/* dma2 stream1 */
-
-/* dma2 stream2 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
-
-#define SPI1_DMA_RX_IRQHandler          DMA2_Stream2_IRQHandler
-#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_RX_DMA_INSTANCE            DMA2_Stream2
-#define SPI1_RX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_RX_DMA_IRQ                 DMA2_Stream2_IRQn
-
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL)
-
-#define USART1_DMA_RX_IRQHandler          DMA2_Stream2_IRQHandler
-#define USART1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define USART1_RX_DMA_INSTANCE            DMA2_Stream2
-#define USART1_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define USART1_RX_DMA_IRQ                 DMA2_Stream2_IRQn
-
-#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL)
-
-#define QSPI_DMA_IRQHandler          DMA2_Stream2_IRQHandler
-#define QSPI_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define QSPI_DMA_INSTANCE            DMA2_Stream2
-#define QSPI_DMA_CHANNEL             DMA_CHANNEL_11
-#define QSPI_DMA_IRQ                 DMA2_Stream2_IRQn
 
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
+#define USART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define USART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define USART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define USART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define USART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
 #endif
-/* dma2 stream2 */
-
-/* dma2 stream3 */
-#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL)
-
-#define SPI5_DMA_RX_IRQHandler          DMA2_Stream3_IRQHandler
-#define SPI5_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE            DMA2_Stream3
-#define SPI5_RX_DMA_CHANNEL             DMA_CHANNEL_2
-#define SPI5_RX_DMA_IRQ                 DMA2_Stream3_IRQn
-
-#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
-
-#define SPI1_DMA_TX_IRQHandler          DMA2_Stream3_IRQHandler
-#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_TX_DMA_INSTANCE            DMA2_Stream3
-#define SPI1_TX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_TX_DMA_IRQ                 DMA2_Stream3_IRQn
-
-#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_CHANNEL)
-
-#define SPI4_DMA_RX_IRQHandler          DMA2_Stream3_IRQHandler
-#define SPI4_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_RX_DMA_INSTANCE            DMA2_Stream3
-#define SPI4_RX_DMA_CHANNEL             DMA_CHANNEL_5
-#define SPI4_RX_DMA_IRQ                 DMA2_Stream3_IRQn
 
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
 #endif
-/* dma2 stream3 */
-
-/* dma2 stream4 */
-#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL)
-
-#define SPI5_DMA_TX_IRQHandler          DMA2_Stream4_IRQHandler
-#define SPI5_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_TX_DMA_INSTANCE            DMA2_Stream4
-#define SPI5_TX_DMA_CHANNEL             DMA_CHANNEL_2
-#define SPI5_TX_DMA_IRQ                 DMA2_Stream4_IRQn
-
-#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_CHANNEL)
-
-#define SPI4_DMA_TX_IRQHandler          DMA2_Stream4_IRQHandler
-#define SPI4_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI4_TX_DMA_INSTANCE            DMA2_Stream4
-#define SPI4_TX_DMA_CHANNEL             DMA_CHANNEL_5
-#define SPI4_TX_DMA_IRQ                 DMA2_Stream4_IRQn
 
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
 #endif
-/* dma2 stream4 */
-
-/* dma2 stream5 */
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
-
-#define SPI1_DMA_TX_IRQHandler          DMA2_Stream5_IRQHandler
-#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI1_TX_DMA_INSTANCE            DMA2_Stream5
-#define SPI1_TX_DMA_CHANNEL             DMA_CHANNEL_3
-#define SPI1_TX_DMA_IRQ                 DMA2_Stream5_IRQn
-
-#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_CHANNEL)
-
-#define USART1_DMA_RX_IRQHandler          DMA2_Stream5_IRQHandler
-#define USART1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define USART1_RX_DMA_INSTANCE            DMA2_Stream5
-#define USART1_RX_DMA_CHANNEL             DMA_CHANNEL_4
-#define USART1_RX_DMA_IRQ                 DMA2_Stream5_IRQn
-
-#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_CHANNEL)
-
-#define SPI5_DMA_RX_IRQHandler          DMA2_Stream5_IRQHandler
-#define SPI5_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_RX_DMA_INSTANCE            DMA2_Stream5
-#define SPI5_RX_DMA_CHANNEL             DMA_CHANNEL_7
-#define SPI5_RX_DMA_IRQ                 DMA2_Stream5_IRQn
 
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
+#define USART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define USART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define USART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define USART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define USART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
 #endif
 
-/* dma2 stream5 */
-
-/* dma2 stream6 */
-#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_CHANNEL)
-
-#define SPI5_DMA_TX_IRQHandler          DMA2_Stream6_IRQHandler
-#define SPI5_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define SPI5_TX_DMA_INSTANCE            DMA2_Stream6
-#define SPI5_TX_DMA_CHANNEL             DMA_CHANNEL_7
-#define SPI5_TX_DMA_IRQ                 DMA2_Stream6_IRQn
-
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
 #endif
-/* dma2 stream6 */
-
-/* dma2 stream7 */
-#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL)
-
-#define QSPI_DMA_IRQHandler          DMA2_Stream7_IRQHandler
-#define QSPI_DMA_RCC                 RCC_AHB1ENR_DMA2EN
-#define QSPI_DMA_INSTANCE            DMA2_Stream7
-#define QSPI_DMA_CHANNEL             DMA_CHANNEL_3
-#define QSPI_DMA_IRQ                 DMA2_Stream7_IRQn
 
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
 #endif
 
-/* dma2 stream7 */
-
 #endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h

@@ -5,7 +5,8 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-01-05     zylx         first version
+ * 2019-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
  */
 
 #ifndef __DMA_CONFIG_H__
@@ -13,161 +14,114 @@
 
 #include <rtthread.h>
 
-/* dma1 channel1 */
-
-
-
-/* dma1 channel1 */
-
-/* dma1 channel2 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_REQUEST)
+/* DMA1 channel1 */
 
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
 #define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
 #define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
 #define SPI1_RX_DMA_REQUEST             DMA_REQUEST_1
 #define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
-
 #endif
-/* dma1 channel2 */
-
-/* dma1 channel3 */
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_REQUEST)
 
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
 #define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
 #define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
 #define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
 #define SPI1_TX_DMA_REQUEST             DMA_REQUEST_1
 #define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
-
 #endif
-/* dma1 channel3 */
-
-/* dma1 channel4 */
-#if defined(BSP_UART1_TX_USING_DMA) && !defined(USART1_TX_DMA_REQUEST)
-
-#define USART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
-#define USART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
-#define USART1_TX_DMA_INSTANCE           DMA1_Channel4
-#define USART1_TX_DMA_REQUEST            DMA_REQUEST_2
-#define USART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
 
+/* DMA1 channel4 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
 #endif
-/* dma1 channel4 */
-
-/* dma1 channel5 */
-#if defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_REQUEST)
-
-#define USART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
-#define USART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
-#define USART1_RX_DMA_INSTANCE           DMA1_Channel5
-#define USART1_RX_DMA_REQUEST            DMA_REQUEST_2
-#define USART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
-
-#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL)
 
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
 #define QSPI_DMA_IRQHandler             DMA1_Channel5_IRQHandler
 #define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA1EN
 #define QSPI_DMA_INSTANCE               DMA1_Channel5
-#define QSPI_DMA_CHANNEL                DMA_REQUEST_5
+#define QSPI_DMA_REQUEST                DMA_REQUEST_5
 #define QSPI_DMA_IRQ                    DMA1_Channel5_IRQn
-
 #endif
-/* dma1 channel5 */
-
-/* dma1 channel6 */
-/* dma1 channel6 */
-
-/* dma1 channel7 */
-
-
 
-/* dma1 channel7 */
+/* DMA1 channel6 */
 
-/* dma2 channel1 */
-#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_REQUEST)
+/* DMA1 channel7 */
 
+/* DMA2 channel1 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
 #define UART5_DMA_TX_IRQHandler         DMA2_Channel1_IRQHandler
 #define UART5_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
 #define UART5_TX_DMA_INSTANCE           DMA2_Channel1
 #define UART5_TX_DMA_REQUEST            DMA_REQUEST_2
 #define UART5_TX_DMA_IRQ                DMA2_Channel1_IRQn
-
 #endif
-/* dma2 channel1 */
-
-/* dma2 channel2 */
-#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_REQUEST)
 
+/* DMA2 channel2 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
 #define UART5_DMA_RX_IRQHandler         DMA2_Channel2_IRQHandler
 #define UART5_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
 #define UART5_RX_DMA_INSTANCE           DMA2_Channel2
 #define UART5_RX_DMA_REQUEST            DMA_REQUEST_2
 #define UART5_RX_DMA_IRQ                DMA2_Channel2_IRQn
-
 #endif
-/* dma2 channel2 */
-
-/* dma2 channel3 */
-#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_REQUEST)
 
+/* DMA2 channel3 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
 #define SPI1_DMA_RX_IRQHandler          DMA2_Channel3_IRQHandler
 #define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
 #define SPI1_RX_DMA_INSTANCE            DMA2_Channel3
 #define SPI1_RX_DMA_REQUEST             DMA_REQUEST_4
 #define SPI1_RX_DMA_IRQ                 DMA2_Channel3_IRQn
-
 #endif
-/* dma2 channel3 */
-
-/* dma2 channel4 */
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_REQUEST)
 
+/* DMA2 channel4 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
 #define SPI1_DMA_TX_IRQHandler          DMA2_Channel4_IRQHandler
 #define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
 #define SPI1_TX_DMA_INSTANCE            DMA2_Channel4
 #define SPI1_TX_DMA_REQUEST             DMA_REQUEST_4
 #define SPI1_TX_DMA_IRQ                 DMA2_Channel4_IRQn
-
 #endif
-/* dma2 channel4 */
-
-/* dma2 channel5 */
 
+/* DMA2 channel5 */
 
-
-/* dma2 channel5 */
-
-/* dma2 channel6 */
-#if defined(BSP_UART1_TX_USING_DMA) && !defined(USART1_TX_DMA_REQUEST)
-
-#define USART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
-#define USART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
-#define USART1_TX_DMA_INSTANCE           DMA2_Channel6
-#define USART1_TX_DMA_REQUEST            DMA_REQUEST_2
-#define USART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
-
+/* DMA2 channel6 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Channel6
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
 #endif
-/* dma2 channel6 */
-
-/* dma2 channel7 */
-#if defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_REQUEST)
-
-#define USART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
-#define USART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
-#define USART1_RX_DMA_INSTANCE           DMA2_Channel7
-#define USART1_RX_DMA_REQUEST            DMA_REQUEST_2
-#define USART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
-
-#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_CHANNEL)
 
+/* DMA2 channel7 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Channel7
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
 #define QSPI_DMA_IRQHandler             DMA2_Channel7_IRQHandler
 #define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA2EN
 #define QSPI_DMA_INSTANCE               DMA2_Channel7
-#define QSPI_DMA_CHANNEL                DMA_REQUEST_3
+#define QSPI_DMA_REQUEST                DMA_REQUEST_3
 #define QSPI_DMA_IRQ                    DMA2_Channel7_IRQn
-
 #endif
-/* dma2 channel7 */
 
 #endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h

@@ -30,7 +30,7 @@
 #define QSPI_DMA_CONFIG                                        \
     {                                                          \
         .Instance = QSPI_DMA_INSTANCE,                         \
-        .Init.Request = QSPI_DMA_CHANNEL,                      \
+        .Init.Request = QSPI_DMA_REQUEST,                      \
         .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
         .Init.PeriphInc = DMA_PINC_DISABLE,                    \
         .Init.MemInc = DMA_MINC_ENABLE,                        \

bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h

@@ -5,7 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-11-06     SummerGift   change to new framework
+ * 2018-11-06     SummerGift   first version
  */
 
 #ifndef __UART_CONFIG_H__
@@ -28,10 +28,10 @@
 #ifndef UART1_DMA_CONFIG
 #define UART1_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART1_RX_DMA_INSTANCE,                          \
-        .request = USART1_RX_DMA_REQUEST,                            \
-        .dma_rcc = USART1_RX_DMA_RCC,                                \
-        .dma_irq = USART1_RX_DMA_IRQ,                                \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_CONFIG */
 #endif /* BSP_UART1_RX_USING_DMA */  
@@ -51,10 +51,10 @@
 #ifndef UART2_DMA_CONFIG
 #define UART2_DMA_CONFIG                                            \
     {                                                               \
-        .Instance = USART2_RX_DMA_INSTANCE,                          \
-        .request = USART2_RX_DMA_REQUEST,                            \
-        .dma_rcc = USART2_RX_DMA_RCC,                                \
-        .dma_irq = USART2_RX_DMA_IRQ,                                \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
     }
 #endif /* UART2_DMA_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */