adapt to rv64ilp32 toolchain

bsp/qemu-virt64-riscv/Kconfig

@@ -59,3 +59,7 @@ config ARCH_USING_NEW_CTX_SWITCH
 config __STACKSIZE__
     int "stack size for interrupt"
     default 4096
+
+config RT_USING_RV64ILP32
+    bool "Use RV64ILP32 toolchain"
+    default n

bsp/qemu-virt64-riscv/README_ZH.md

@@ -4,7 +4,7 @@
 
 ## 1. 简介
 
-RISC-V是一种开放和免费的指令集体系结构(ISA)。本工程是在QEMU的RISCV64 VIRT版本上进行的一份移植。
+RISC-V是一种开放和免费的指令集体系结构(ISA)。本工程是在QEMU的RISCV64 VIRT版本上进行的一份移植。本工程支持玄铁团队联合中科院软件所共同推出的全球首款rv64ilp32产品级开源工具链。
 
 ## 2. 编译说明
 
@@ -133,8 +133,59 @@ msh />
 | PLIC | 支持 | - |
 | CLIC | 支持 | - |
 
-## 5. 联系人信息
+## 5.如何使用rv64ilp32工具链
+
+1. 工具链地址：https://github.com/ruyisdk/riscv-gnu-toolchain-rv64ilp32/tags
+
+2. 使用方法：
+
+   - 配置工具链路径
+
+   - 修改ABI参数为：-mabi=ilp32d
+
+   - 使用menuconfig使能下述选项:
+
+     ```shell
+     RT_USING_RV64ILP32
+     ```
+
+   - 使用menuconfig失能下述选项:
+
+     ```shell
+     RT_USING_POSIX_PIPE
+     RT_USING_POSIX_FS
+     RT_USING_DFS
+     ```
+
+3.  使用传统64位工具链与使用新32位工具链编译相同工程的固件大小对比：
+
+   传统64位工具链固件大小：
+
+   ```bash
+   Memory region         Used Size  Region Size  %age Used
+               SRAM:      225856 B        16 MB      1.35%
+   riscv64-unknown-elf-objcopy -O binary rtthread.elf rtthread.bin
+   riscv64-unknown-elf-size rtthread.elf
+      text    data     bss     dec     hex filename
+    150907    3664   71268  225839   3722f rtthread.elf
+   ```
+
+   新32位工具链固件大小：
+
+   ```bash
+   Memory region         Used Size  Region Size  %age Used
+               SRAM:      209376 B        16 MB      1.25%
+   riscv64-unknown-elf-objcopy -O binary rtthread.elf rtthread.bin
+   riscv64-unknown-elf-size rtthread.elf
+      text    data     bss     dec     hex filename
+    138739    1356   69276  209371   331db rtthread.elf
+   ```
+
+## 6. 联系人信息
 
 维护人：[bernard][1]
 
 [1]: https://github.com/BernardXiong
+
+
+

bsp/qemu-virt64-riscv/qemu-rv64ilp32-nographic.sh

@@ -0,0 +1 @@
+/home/rv/opt-ilp32/bin/qemu-system-riscv64ilp32  -cpu rv64 -M virt -m 256M -nographic -kernel rtthread.elf

libcpu/risc-v/virt64/context_gcc.S

@@ -16,13 +16,13 @@
 #include "stackframe.h"
 
 .macro PUSH_8 reg
-    addi    sp, sp, -8
+    addi    sp, sp, -REGBYTES
     STORE   \reg, (sp)
 .endm
 
 .macro POP_8 reg
     LOAD    \reg, (sp)
-    addi    sp, sp, 8
+    addi    sp, sp, REGBYTES
 .endm
 
 .macro RESERVE_CONTEXT
@@ -44,11 +44,11 @@
     li      s10, (SSTATUS_SPP)
     or      s11, s11, s10
     PUSH_8  s11
-    addi    sp, sp, -8
+    addi    sp, sp, -REGBYTES
 .endm
 
 .macro RESTORE_CONTEXT
-    addi    sp, sp, 8
+    addi    sp, sp, REGBYTES
     POP_8   s11
     csrw    sstatus, s11
     POP_8   s11

libcpu/risc-v/virt64/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,6 +16,7 @@
 #include "stack.h"
 #include <sbi.h>
 #include <encoding.h>
+#include "regtypes.h"
 
 #define K_SSTATUS_DEFAULT (SSTATUS_SPP | SSTATUS_SPIE | SSTATUS_SUM | SSTATUS_FS)
 
@@ -35,7 +36,7 @@ volatile rt_ubase_t rt_interrupt_to_thread = 0;
  */
 volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
 
-void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus)
+void *_rt_hw_stack_init(rt_uintreg_t *sp, rt_uintreg_t ra, rt_uintreg_t sstatus)
 {
     (*--sp) = 0;                                /* tp */
     (*--sp) = ra;                               /* ra */
@@ -80,17 +81,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
                              rt_uint8_t *stack_addr,
                              void *texit)
 {
-    rt_ubase_t *sp = (rt_ubase_t *)stack_addr;
+    rt_uintreg_t *sp = (rt_uintreg_t *)stack_addr;
     // we use a strict alignment requirement for Q extension
-    sp = (rt_ubase_t *)RT_ALIGN_DOWN((rt_ubase_t)sp, 16);
+    sp = (rt_uintreg_t *)RT_ALIGN_DOWN((rt_uintreg_t)sp, 16);
 
-    (*--sp) = (rt_ubase_t)tentry;
-    (*--sp) = (rt_ubase_t)parameter;
-    (*--sp) = (rt_ubase_t)texit;
+    (*--sp) = (rt_uintreg_t)tentry;
+    (*--sp) = (rt_uintreg_t)parameter;
+    (*--sp) = (rt_uintreg_t)texit;
 
     /* compatible to RESTORE_CONTEXT */
     extern void _rt_thread_entry(void);
-    return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_ubase_t)_rt_thread_entry, K_SSTATUS_DEFAULT);
+    return (rt_uint8_t *)_rt_hw_stack_init(sp, (rt_uintreg_t)_rt_thread_entry, K_SSTATUS_DEFAULT);
 }
 
 /*

libcpu/risc-v/virt64/cpuport.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,6 +17,8 @@
 #ifdef ARCH_CPU_64BIT
 #define STORE                   sd
 #define LOAD                    ld
+#define FSTORE                  fsd
+#define FLOAD                   fld
 #define REGBYTES                8
 #else
 // error here, not portable

libcpu/risc-v/virt64/cpuport_gcc.S

@@ -14,11 +14,11 @@
 
 START_POINT(_rt_thread_entry)
     LOAD    ra, (sp)    /* thread exit */
-    addi    sp, sp, 8
+    addi    sp, sp, REGBYTES
     LOAD    a0, (sp)    /* parameter */
-    addi    sp, sp, 8
+    addi    sp, sp, REGBYTES
     LOAD    t0, (sp)    /* tentry */
-    addi    sp, sp, 8
+    addi    sp, sp, REGBYTES
     mv      s1, ra
     jalr    t0
     jalr    s1

libcpu/risc-v/virt64/ext_context.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,38 +28,38 @@
  */
 
 #ifdef ENABLE_FPU
-#define FPU_CTX_F0_OFF   0   /* offsetof(fpu_context_t, fpustatus.f[0])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F1_OFF   8   /* offsetof(fpu_context_t, fpustatus.f[1])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F2_OFF   16  /* offsetof(fpu_context_t, fpustatus.f[2])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F3_OFF   24  /* offsetof(fpu_context_t, fpustatus.f[3])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F4_OFF   32  /* offsetof(fpu_context_t, fpustatus.f[4])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F5_OFF   40  /* offsetof(fpu_context_t, fpustatus.f[5])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F6_OFF   48  /* offsetof(fpu_context_t, fpustatus.f[6])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F7_OFF   56  /* offsetof(fpu_context_t, fpustatus.f[7])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F8_OFF   64  /* offsetof(fpu_context_t, fpustatus.f[8])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F9_OFF   72  /* offsetof(fpu_context_t, fpustatus.f[9])  - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F10_OFF  80  /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F11_OFF  88  /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F12_OFF  96  /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F13_OFF  104 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F14_OFF  112 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F15_OFF  120 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F16_OFF  128 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F17_OFF  136 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F18_OFF  144 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F19_OFF  152 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F20_OFF  160 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F21_OFF  168 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F22_OFF  176 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F23_OFF  184 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F24_OFF  192 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F25_OFF  200 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F26_OFF  208 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F27_OFF  216 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F28_OFF  224 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F29_OFF  232 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F30_OFF  240 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
-#define FPU_CTX_F31_OFF  248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F0_OFF  REGBYTES * 0  /* offsetof(fpu_context_t, fpustatus.f[0])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F1_OFF  REGBYTES * 1  /* offsetof(fpu_context_t, fpustatus.f[1])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F2_OFF  REGBYTES * 2  /* offsetof(fpu_context_t, fpustatus.f[2])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F3_OFF  REGBYTES * 3  /* offsetof(fpu_context_t, fpustatus.f[3])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F4_OFF  REGBYTES * 4  /* offsetof(fpu_context_t, fpustatus.f[4])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F5_OFF  REGBYTES * 5  /* offsetof(fpu_context_t, fpustatus.f[5])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F6_OFF  REGBYTES * 6  /* offsetof(fpu_context_t, fpustatus.f[6])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F7_OFF  REGBYTES * 7  /* offsetof(fpu_context_t, fpustatus.f[7])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F8_OFF  REGBYTES * 8  /* offsetof(fpu_context_t, fpustatus.f[8])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F9_OFF  REGBYTES * 9  /* offsetof(fpu_context_t, fpustatus.f[9])  - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F10_OFF REGBYTES * 10 /* offsetof(fpu_context_t, fpustatus.f[10]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F11_OFF REGBYTES * 11 /* offsetof(fpu_context_t, fpustatus.f[11]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F12_OFF REGBYTES * 12 /* offsetof(fpu_context_t, fpustatus.f[12]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F13_OFF REGBYTES * 13 /* offsetof(fpu_context_t, fpustatus.f[13]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F14_OFF REGBYTES * 14 /* offsetof(fpu_context_t, fpustatus.f[14]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F15_OFF REGBYTES * 15 /* offsetof(fpu_context_t, fpustatus.f[15]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F16_OFF REGBYTES * 16 /* offsetof(fpu_context_t, fpustatus.f[16]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F17_OFF REGBYTES * 17 /* offsetof(fpu_context_t, fpustatus.f[17]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F18_OFF REGBYTES * 18 /* offsetof(fpu_context_t, fpustatus.f[18]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F19_OFF REGBYTES * 19 /* offsetof(fpu_context_t, fpustatus.f[19]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F20_OFF REGBYTES * 20 /* offsetof(fpu_context_t, fpustatus.f[20]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F21_OFF REGBYTES * 21 /* offsetof(fpu_context_t, fpustatus.f[21]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F22_OFF REGBYTES * 22 /* offsetof(fpu_context_t, fpustatus.f[22]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F23_OFF REGBYTES * 23 /* offsetof(fpu_context_t, fpustatus.f[23]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F24_OFF REGBYTES * 24 /* offsetof(fpu_context_t, fpustatus.f[24]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F25_OFF REGBYTES * 25 /* offsetof(fpu_context_t, fpustatus.f[25]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F26_OFF REGBYTES * 26 /* offsetof(fpu_context_t, fpustatus.f[26]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F27_OFF REGBYTES * 27 /* offsetof(fpu_context_t, fpustatus.f[27]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F28_OFF REGBYTES * 28 /* offsetof(fpu_context_t, fpustatus.f[28]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F29_OFF REGBYTES * 29 /* offsetof(fpu_context_t, fpustatus.f[29]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F30_OFF REGBYTES * 30 /* offsetof(fpu_context_t, fpustatus.f[30]) - offsetof(fpu_context_t, fpustatus.f[0]) */
+#define FPU_CTX_F31_OFF REGBYTES * 31 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
 #endif /* ENABLE_FPU */
 
 /**
@@ -84,9 +84,9 @@
 
 /**
  * @brief save vector extension hardware state
- * 
+ *
  * @param dst register storing bottom of storage block
- * 
+ *
  */
 .macro SAVE_VECTOR, dst
     mv      t1, \dst
@@ -117,9 +117,9 @@
 
 /**
  * @brief restore vector extension hardware states
- * 
+ *
  * @param dst register storing bottom of storage block
- * 
+ *
  */
 .macro RESTORE_VECTOR, dst
     // restore vector registers first since it will modify vector states
@@ -152,4 +152,4 @@
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __EXT_CONTEXT_H__ */
+#endif /* __EXT_CONTEXT_H__ */

libcpu/risc-v/virt64/interrupt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,6 +15,7 @@
 
 #include <rthw.h>
 #include "stack.h"
+#include "regtypes.h"
 
 enum
 {
@@ -41,6 +42,6 @@ int rt_hw_plic_irq_disable(int irq_number);
 void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int vector);
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
-void handle_trap(rt_size_t xcause, rt_size_t xtval, rt_size_t xepc, struct rt_hw_stack_frame *sp);
+void handle_trap(rt_uintreg_t xcause, rt_uintreg_t xtval, rt_uintreg_t xepc, struct rt_hw_stack_frame *sp);
 
 #endif

libcpu/risc-v/virt64/regtypes.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-07-15     WangShun     The first version
+ */
+
+#ifndef REGTYPES_H__
+#define REGTYPES_H__
+#include <rtconfig.h>
+#if defined(RT_USING_RV64ILP32)
+typedef unsigned long long rt_uintreg_t;
+#else
+typedef unsigned long rt_uintreg_t;
+#endif
+#endif /* REGTYPES_H__ */

libcpu/risc-v/virt64/riscv.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,9 +12,15 @@
 #define __RISCV_H__
 
 #include <encoding.h>
+#include <rtconfig.h>
 
+#if defined(RT_USING_RV64ILP32)
+#define __SIZE(bit) (1ULL << (bit))
+#define __MASK(bit) (__SIZE(bit) - 1ULL)
+#else
 #define __SIZE(bit) (1UL << (bit))
 #define __MASK(bit) (__SIZE(bit) - 1UL)
+#endif /* RT_USING_RV64ILP32 */
 #define __UMASK(bit) (~(__MASK(bit)))
 #define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
 #define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))

libcpu/risc-v/virt64/stackframe.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -85,38 +85,38 @@
 
     li  t0, SSTATUS_FS
     csrs sstatus, t0
-    fsd f0,  FPU_CTX_F0_OFF(t1)
-    fsd f1,  FPU_CTX_F1_OFF(t1)
-    fsd f2,  FPU_CTX_F2_OFF(t1)
-    fsd f3,  FPU_CTX_F3_OFF(t1)
-    fsd f4,  FPU_CTX_F4_OFF(t1)
-    fsd f5,  FPU_CTX_F5_OFF(t1)
-    fsd f6,  FPU_CTX_F6_OFF(t1)
-    fsd f7,  FPU_CTX_F7_OFF(t1)
-    fsd f8,  FPU_CTX_F8_OFF(t1)
-    fsd f9,  FPU_CTX_F9_OFF(t1)
-    fsd f10, FPU_CTX_F10_OFF(t1)
-    fsd f11, FPU_CTX_F11_OFF(t1)
-    fsd f12, FPU_CTX_F12_OFF(t1)
-    fsd f13, FPU_CTX_F13_OFF(t1)
-    fsd f14, FPU_CTX_F14_OFF(t1)
-    fsd f15, FPU_CTX_F15_OFF(t1)
-    fsd f16, FPU_CTX_F16_OFF(t1)
-    fsd f17, FPU_CTX_F17_OFF(t1)
-    fsd f18, FPU_CTX_F18_OFF(t1)
-    fsd f19, FPU_CTX_F19_OFF(t1)
-    fsd f20, FPU_CTX_F20_OFF(t1)
-    fsd f21, FPU_CTX_F21_OFF(t1)
-    fsd f22, FPU_CTX_F22_OFF(t1)
-    fsd f23, FPU_CTX_F23_OFF(t1)
-    fsd f24, FPU_CTX_F24_OFF(t1)
-    fsd f25, FPU_CTX_F25_OFF(t1)
-    fsd f26, FPU_CTX_F26_OFF(t1)
-    fsd f27, FPU_CTX_F27_OFF(t1)
-    fsd f28, FPU_CTX_F28_OFF(t1)
-    fsd f29, FPU_CTX_F29_OFF(t1)
-    fsd f30, FPU_CTX_F30_OFF(t1)
-    fsd f31, FPU_CTX_F31_OFF(t1)
+    FSTORE f0,  FPU_CTX_F0_OFF(t1)
+    FSTORE f1,  FPU_CTX_F1_OFF(t1)
+    FSTORE f2,  FPU_CTX_F2_OFF(t1)
+    FSTORE f3,  FPU_CTX_F3_OFF(t1)
+    FSTORE f4,  FPU_CTX_F4_OFF(t1)
+    FSTORE f5,  FPU_CTX_F5_OFF(t1)
+    FSTORE f6,  FPU_CTX_F6_OFF(t1)
+    FSTORE f7,  FPU_CTX_F7_OFF(t1)
+    FSTORE f8,  FPU_CTX_F8_OFF(t1)
+    FSTORE f9,  FPU_CTX_F9_OFF(t1)
+    FSTORE f10, FPU_CTX_F10_OFF(t1)
+    FSTORE f11, FPU_CTX_F11_OFF(t1)
+    FSTORE f12, FPU_CTX_F12_OFF(t1)
+    FSTORE f13, FPU_CTX_F13_OFF(t1)
+    FSTORE f14, FPU_CTX_F14_OFF(t1)
+    FSTORE f15, FPU_CTX_F15_OFF(t1)
+    FSTORE f16, FPU_CTX_F16_OFF(t1)
+    FSTORE f17, FPU_CTX_F17_OFF(t1)
+    FSTORE f18, FPU_CTX_F18_OFF(t1)
+    FSTORE f19, FPU_CTX_F19_OFF(t1)
+    FSTORE f20, FPU_CTX_F20_OFF(t1)
+    FSTORE f21, FPU_CTX_F21_OFF(t1)
+    FSTORE f22, FPU_CTX_F22_OFF(t1)
+    FSTORE f23, FPU_CTX_F23_OFF(t1)
+    FSTORE f24, FPU_CTX_F24_OFF(t1)
+    FSTORE f25, FPU_CTX_F25_OFF(t1)
+    FSTORE f26, FPU_CTX_F26_OFF(t1)
+    FSTORE f27, FPU_CTX_F27_OFF(t1)
+    FSTORE f28, FPU_CTX_F28_OFF(t1)
+    FSTORE f29, FPU_CTX_F29_OFF(t1)
+    FSTORE f30, FPU_CTX_F30_OFF(t1)
+    FSTORE f31, FPU_CTX_F31_OFF(t1)
 
     /* clr FS domain */
     csrc sstatus, t0
@@ -166,38 +166,38 @@
 
     li  t0, SSTATUS_FS
     csrs sstatus, t0
-    fld f0,  FPU_CTX_F0_OFF(t2)
-    fld f1,  FPU_CTX_F1_OFF(t2)
-    fld f2,  FPU_CTX_F2_OFF(t2)
-    fld f3,  FPU_CTX_F3_OFF(t2)
-    fld f4,  FPU_CTX_F4_OFF(t2)
-    fld f5,  FPU_CTX_F5_OFF(t2)
-    fld f6,  FPU_CTX_F6_OFF(t2)
-    fld f7,  FPU_CTX_F7_OFF(t2)
-    fld f8,  FPU_CTX_F8_OFF(t2)
-    fld f9,  FPU_CTX_F9_OFF(t2)
-    fld f10, FPU_CTX_F10_OFF(t2)
-    fld f11, FPU_CTX_F11_OFF(t2)
-    fld f12, FPU_CTX_F12_OFF(t2)
-    fld f13, FPU_CTX_F13_OFF(t2)
-    fld f14, FPU_CTX_F14_OFF(t2)
-    fld f15, FPU_CTX_F15_OFF(t2)
-    fld f16, FPU_CTX_F16_OFF(t2)
-    fld f17, FPU_CTX_F17_OFF(t2)
-    fld f18, FPU_CTX_F18_OFF(t2)
-    fld f19, FPU_CTX_F19_OFF(t2)
-    fld f20, FPU_CTX_F20_OFF(t2)
-    fld f21, FPU_CTX_F21_OFF(t2)
-    fld f22, FPU_CTX_F22_OFF(t2)
-    fld f23, FPU_CTX_F23_OFF(t2)
-    fld f24, FPU_CTX_F24_OFF(t2)
-    fld f25, FPU_CTX_F25_OFF(t2)
-    fld f26, FPU_CTX_F26_OFF(t2)
-    fld f27, FPU_CTX_F27_OFF(t2)
-    fld f28, FPU_CTX_F28_OFF(t2)
-    fld f29, FPU_CTX_F29_OFF(t2)
-    fld f30, FPU_CTX_F30_OFF(t2)
-    fld f31, FPU_CTX_F31_OFF(t2)
+    FLOAD f0,  FPU_CTX_F0_OFF(t2)
+    FLOAD f1,  FPU_CTX_F1_OFF(t2)
+    FLOAD f2,  FPU_CTX_F2_OFF(t2)
+    FLOAD f3,  FPU_CTX_F3_OFF(t2)
+    FLOAD f4,  FPU_CTX_F4_OFF(t2)
+    FLOAD f5,  FPU_CTX_F5_OFF(t2)
+    FLOAD f6,  FPU_CTX_F6_OFF(t2)
+    FLOAD f7,  FPU_CTX_F7_OFF(t2)
+    FLOAD f8,  FPU_CTX_F8_OFF(t2)
+    FLOAD f9,  FPU_CTX_F9_OFF(t2)
+    FLOAD f10, FPU_CTX_F10_OFF(t2)
+    FLOAD f11, FPU_CTX_F11_OFF(t2)
+    FLOAD f12, FPU_CTX_F12_OFF(t2)
+    FLOAD f13, FPU_CTX_F13_OFF(t2)
+    FLOAD f14, FPU_CTX_F14_OFF(t2)
+    FLOAD f15, FPU_CTX_F15_OFF(t2)
+    FLOAD f16, FPU_CTX_F16_OFF(t2)
+    FLOAD f17, FPU_CTX_F17_OFF(t2)
+    FLOAD f18, FPU_CTX_F18_OFF(t2)
+    FLOAD f19, FPU_CTX_F19_OFF(t2)
+    FLOAD f20, FPU_CTX_F20_OFF(t2)
+    FLOAD f21, FPU_CTX_F21_OFF(t2)
+    FLOAD f22, FPU_CTX_F22_OFF(t2)
+    FLOAD f23, FPU_CTX_F23_OFF(t2)
+    FLOAD f24, FPU_CTX_F24_OFF(t2)
+    FLOAD f25, FPU_CTX_F25_OFF(t2)
+    FLOAD f26, FPU_CTX_F26_OFF(t2)
+    FLOAD f27, FPU_CTX_F27_OFF(t2)
+    FLOAD f28, FPU_CTX_F28_OFF(t2)
+    FLOAD f29, FPU_CTX_F29_OFF(t2)
+    FLOAD f30, FPU_CTX_F30_OFF(t2)
+    FLOAD f31, FPU_CTX_F31_OFF(t2)
 
     /* clr FS domain */
     csrc sstatus, t0

libcpu/risc-v/virt64/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -61,7 +61,7 @@ void dump_regs(struct rt_hw_stack_frame *regs)
     rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode");
     rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SUM) ? "Permit to Access User Page" : "Not Permit to Access User Page");
     rt_kprintf("\t%s\n", (regs->sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page");
-    rt_size_t satp_v = read_csr(satp);
+    rt_uintreg_t satp_v = read_csr(satp);
     rt_kprintf("satp = 0x%p\n", satp_v);
     rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n", __MASKVALUE(satp_v, __MASK(44)) << PAGE_OFFSET_BIT);
     rt_kprintf("\tCurrent ASID = 0x%p\n", __MASKVALUE(satp_v >> 44, __MASK(16)) << PAGE_OFFSET_BIT);
@@ -291,10 +291,10 @@ static void handle_nested_trap_panic(
 #define PAGE_FAULT (id == EP_LOAD_PAGE_FAULT || id == EP_STORE_PAGE_FAULT)
 
 /* Trap entry */
-void handle_trap(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw_stack_frame *sp)
+void handle_trap(rt_uintreg_t scause, rt_uintreg_t stval, rt_uintreg_t sepc, struct rt_hw_stack_frame *sp)
 {
     ENTER_TRAP;
-    rt_size_t id = __MASKVALUE(scause, __MASK(63UL));
+    rt_uintreg_t id = __MASKVALUE(scause, __MASK(63UL));
     const char *msg;
 
     /* supervisor external interrupt */
@@ -316,7 +316,7 @@ void handle_trap(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw
     {
         // trap cannot nested when handling another trap / interrupt
         CHECK_NESTED_PANIC(scause, stval, sepc, sp);
-        rt_size_t id = __MASKVALUE(scause, __MASK(63UL));
+        rt_uintreg_t id = __MASKVALUE(scause, __MASK(63UL));
         const char *msg;
 
         if (scause >> 63)