[bsp]添加ch32v307需要的库文件 (#6329)

* add ch32v307 lib

* fix scons

bsp/wch/risc-v/Libraries/Kconfig

@@ -5,6 +5,11 @@ config SOC_RISCV_SERIES_CH32V103
     bool
     select ARCH_RISCV
     select SOC_RISCV_FAMILY_CH32
+	
+config SOC_RISCV_SERIES_CH32V307
+    bool
+    select ARCH_RISCV
+    select SOC_RISCV_FAMILY_CH32
 
 config SOC_FAMILY_CH56X
     bool

bsp/wch/risc-v/Libraries/ch32_drivers/SConscript

@@ -9,7 +9,7 @@ src = Split("""
 """)
 
 
-if  GetDepend('SOC_RISCV_SERIES_CH32V103'):
+if  GetDepend('SOC_RISCV_FAMILY_CH32'):
 
     if GetDepend('RT_USING_PIN'):
         src += ['drv_gpio.c']

bsp/wch/risc-v/Libraries/ch32v30x_libraries/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/SConscript

@@ -0,0 +1,79 @@
+#-*- encoding: utf-8 -*-
+
+import os
+from building import * 
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#---------------------------------------------------------------------------------
+# Package configuration
+#---------------------------------------------------------------------------------
+PKGNAME = "bmsis"
+VERSION = "v1.0.0"
+DEPENDS = [""]
+#DEPENDS = ["PKG_USING_RW007"]
+
+#---------------------------------------------------------------------------------
+# Compile the configuration 
+#
+# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
+# 
+# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
+# LOCAL_CCFLAGS: Local compilation parameter 
+# LOCAL_ASFLAGS: Local assembly parameters
+# 
+# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH 
+#          is empty # no pass!!!
+# CCFLAGS: Global compilation parameter 
+# ASFLAGS: Global assembly parameters
+#
+# CPPDEFINES: Global macro definition
+# LOCAL_CPPDEFINES: Local macro definition 
+# 
+# LIBS: Specify the static library that need to be linked
+# LIBPATH: Specify the search directory for the library file (.lib/.a)
+#
+# LINKFLAGS: Link options
+#---------------------------------------------------------------------------------
+SOURCES          = Glob("./source/*.c")
+SOURCES          += Glob("./source/startup_ch32v30x.S")
+
+LOCAL_CPPPATH    = [] 
+LOCAL_CCFLAGS    = "" 
+LOCAL_ASFLAGS    = ""
+
+CPPPATH          = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')] 
+CCFLAGS          = "" 
+ASFLAGS          = ""
+
+CPPDEFINES       = []
+LOCAL_CPPDEFINES = []
+
+LIBS             = [] 
+LIBPATH          = [] 
+
+LINKFLAGS        = "" 
+
+SOURCES_IGNORE   = []
+CPPPATH_IGNORE   = []
+
+#---------------------------------------------------------------------------------
+# Main target
+#---------------------------------------------------------------------------------
+objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS, 
+                   CPPPATH          = CPPPATH, 
+                   CCFLAGS          = CCFLAGS, 
+                   ASFLAGS          = ASFLAGS, 
+                   LOCAL_CPPPATH    = LOCAL_CPPPATH, 
+                   LOCAL_CCFLAGS    = LOCAL_CCFLAGS, 
+                   LOCAL_ASFLAGS    = LOCAL_ASFLAGS, 
+                   CPPDEFINES       = CPPDEFINES, 
+                   LOCAL_CPPDEFINES = LOCAL_CPPDEFINES, 
+                   LIBS             = LIBS, 
+                   LIBPATH          = LIBPATH,
+                   LINKFLAGS        = LINKFLAGS)  
+
+Return("objs") 
+#---------------------------------------------------------------------------------
+# End
+#---------------------------------------------------------------------------------

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/include/ch32v30x_conf.h

@@ -0,0 +1,43 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_conf.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Library configuration file.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_CONF_H
+#define __CH32V30x_CONF_H
+
+#include "ch32v30x_adc.h"
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_can.h"
+#include "ch32v30x_crc.h"
+#include "ch32v30x_dac.h"
+#include "ch32v30x_dbgmcu.h"
+#include "ch32v30x_dma.h"
+#include "ch32v30x_exti.h"
+#include "ch32v30x_flash.h"
+#include "ch32v30x_fsmc.h"
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_i2c.h"
+#include "ch32v30x_iwdg.h"
+#include "ch32v30x_pwr.h"
+#include "ch32v30x_rcc.h"
+#include "ch32v30x_rtc.h"
+#include "ch32v30x_sdio.h"
+#include "ch32v30x_spi.h"
+#include "ch32v30x_tim.h"
+#include "ch32v30x_usart.h"
+#include "ch32v30x_wwdg.h"
+#include "ch32v30x_it.h"
+#include "ch32v30x_misc.h"
+
+
+#endif /* __CH32V30x_CONF_H */
+
+
+	
+	
+	

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/include/ch32v30x_it.h

@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains the headers of the interrupt handlers.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_IT_H
+#define __CH32V30x_IT_H
+
+#include "debug.h"
+
+#define GET_INT_SP()   asm("csrrw sp,mscratch,sp")
+#define FREE_INT_SP()  asm("csrrw sp,mscratch,sp")
+
+#endif /* __CH32V30x_IT_H */
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/include/core_riscv.h

@@ -0,0 +1,383 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Header File for CH32V30x
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CORE_RISCV_H__
+#define __CORE_RISCV_H__
+
+/* IO definitions */
+#ifdef __cplusplus
+  #define     __I     volatile                /* defines 'read only' permissions */
+#else
+  #define     __I     volatile const          /* defines 'read only' permissions */
+#endif
+#define     __O     volatile                  /* defines 'write only' permissions */
+#define     __IO    volatile                  /* defines 'read / write' permissions */
+
+/* Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef __I uint64_t vuc64;  /* Read Only */
+typedef __I uint32_t vuc32;  /* Read Only */
+typedef __I uint16_t vuc16;  /* Read Only */
+typedef __I uint8_t vuc8;   /* Read Only */
+
+typedef const uint64_t uc64;  /* Read Only */
+typedef const uint32_t uc32;  /* Read Only */
+typedef const uint16_t uc16;  /* Read Only */
+typedef const uint8_t uc8;   /* Read Only */
+
+typedef __I int64_t vsc64;  /* Read Only */
+typedef __I int32_t vsc32;  /* Read Only */
+typedef __I int16_t vsc16;  /* Read Only */
+typedef __I int8_t vsc8;   /* Read Only */
+
+typedef const int64_t sc64;  /* Read Only */
+typedef const int32_t sc32;  /* Read Only */
+typedef const int16_t sc16;  /* Read Only */
+typedef const int8_t sc8;   /* Read Only */
+
+typedef __IO uint64_t  vu64;
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef uint64_t  u64;
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef __IO int64_t  vs64;
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef int64_t  s64;
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+#define   RV_STATIC_INLINE  static  inline
+
+/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
+typedef struct{
+  __I  uint32_t ISR[8];
+  __I  uint32_t IPR[8];
+  __IO uint32_t ITHRESDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t CFGR;
+  __I  uint32_t GISR;
+  uint8_t VTFIDR[4];
+  uint8_t RESERVED0[12];
+  __IO uint32_t VTFADDR[4];
+  uint8_t RESERVED1[0x90];
+  __O  uint32_t IENR[8];
+  uint8_t RESERVED2[0x60];
+  __O  uint32_t IRER[8];
+  uint8_t RESERVED3[0x60];
+  __O  uint32_t IPSR[8];
+  uint8_t RESERVED4[0x60];
+  __O  uint32_t IPRR[8];
+  uint8_t RESERVED5[0x60];
+  __IO uint32_t IACTR[8];
+  uint8_t RESERVED6[0xE0];
+  __IO uint8_t IPRIOR[256];
+  uint8_t RESERVED7[0x810];
+  __IO uint32_t SCTLR;
+}PFIC_Type;
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+    __IO u32 CTLR;
+    __IO u32 SR;
+    __IO u64 CNT;
+    __IO u64 CMP;
+}SysTick_Type;
+
+
+#define PFIC            ((PFIC_Type *) 0xE000E000 )
+#define NVIC            PFIC
+#define NVIC_KEY1       ((uint32_t)0xFA050000)
+#define	NVIC_KEY2				((uint32_t)0xBCAF0000)
+#define	NVIC_KEY3				((uint32_t)0xBEEF0000)
+
+#define SysTick         ((SysTick_Type *) 0xE000F000)
+
+/*********************************************************************
+ * @fn      __enable_irq
+ *
+ * @brief   Enable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __enable_irq()
+{
+  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
+}
+
+/*********************************************************************
+ * @fn      __disable_irq
+ *
+ * @brief   Disable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __disable_irq()
+{
+  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
+}
+
+/*********************************************************************
+ * @fn      __NOP
+ *
+ * @brief   nop
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __NOP()
+{
+  __asm volatile ("nop");
+}
+
+/*********************************************************************
+ * @fn      NVIC_EnableIRQ
+ *
+ * @brief   Enable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_DisableIRQ
+ *
+ * @brief   Disable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetStatusIRQ
+ *
+ * @brief   Get Interrupt Enable State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Enable
+ *          0 - Interrupt Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetPendingIRQ
+ *
+ * @brief   Get Interrupt Pending State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Pending Enable
+ *          0 - Interrupt Pending Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPendingIRQ
+ *
+ * @brief   Set Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_ClearPendingIRQ
+ *
+ * @brief   Clear Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetActive
+ *
+ * @brief   Get Interrupt Active State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Active
+ *          0 - Interrupt No Active
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPriority
+ *
+ * @brief   Set Interrupt Priority
+ *
+ * @param   IRQn - Interrupt Numbers
+ *          priority -
+ *              bit7 - pre-emption priority
+ *              bit6~bit4 - subpriority
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
+{
+  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
+}
+
+/*********************************************************************
+ * @fn      __WFI
+ *
+ * @brief   Wait for Interrupt
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
+{
+  NVIC->SCTLR &= ~(1<<3);	// wfi
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      __WFE
+ *
+ * @brief   Wait for Events
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
+{
+  uint32_t t;
+
+  t = NVIC->SCTLR;
+  NVIC->SCTLR |= (1<<3)|(1<<5);		// (wfi->wfe)+(__sev)
+  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
+  asm volatile ("wfi");
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      SetVTFIRQ
+ *
+ * @brief   Set VTF Interrupt
+ *
+ * @param   add - VTF interrupt service function base address.
+ *          IRQn -Interrupt Numbers
+ *          num - VTF Interrupt Numbers
+ *          NewState - DISABLE or ENABLE
+ * @return  None
+ */
+RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
+  if(num > 3)  return ;
+
+  if (NewState != DISABLE)
+  {
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
+  }
+  else{
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
+  }
+}
+
+/*********************************************************************
+ * @fn      NVIC_SystemReset
+ *
+ * @brief   Initiate a system reset request
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SystemReset(void)
+{
+  NVIC->CFGR = NVIC_KEY3|(1<<7);
+}
+
+
+/* Core_Exported_Functions */  
+extern uint32_t __get_FFLAGS(void);
+extern void __set_FFLAGS(uint32_t value);
+extern uint32_t __get_FRM(void);
+extern void __set_FRM(uint32_t value);
+extern uint32_t __get_FCSR(void);
+extern void __set_FCSR(uint32_t value);
+extern uint32_t __get_MSTATUS(void);
+extern void __set_MSTATUS(uint32_t value);
+extern uint32_t __get_MISA(void);
+extern void __set_MISA(uint32_t value);
+extern uint32_t __get_MIE(void);
+extern void __set_MIE(uint32_t value);
+extern uint32_t __get_MTVEC(void);
+extern void __set_MTVEC(uint32_t value);
+extern uint32_t __get_MSCRATCH(void);
+extern void __set_MSCRATCH(uint32_t value);
+extern uint32_t __get_MEPC(void);
+extern void __set_MEPC(uint32_t value);
+extern uint32_t __get_MCAUSE(void);
+extern void __set_MCAUSE(uint32_t value);
+extern uint32_t __get_MTVAL(void);
+extern void __set_MTVAL(uint32_t value);
+extern uint32_t __get_MIP(void);
+extern void __set_MIP(uint32_t value);
+extern uint32_t __get_MCYCLE(void);
+extern void __set_MCYCLE(uint32_t value);
+extern uint32_t __get_MCYCLEH(void);
+extern void __set_MCYCLEH(uint32_t value);
+extern uint32_t __get_MINSTRET(void);
+extern void __set_MINSTRET(uint32_t value);
+extern uint32_t __get_MINSTRETH(void);
+extern void __set_MINSTRETH(uint32_t value);
+extern uint32_t __get_MVENDORID(void);
+extern uint32_t __get_MARCHID(void);
+extern uint32_t __get_MIMPID(void);
+extern uint32_t __get_MHARTID(void);
+extern uint32_t __get_SP(void);
+
+
+#endif
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/include/debug.h

@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#include "stdio.h"
+#include "ch32v30x.h"
+
+/* UART Printf Definition */
+#define DEBUG_UART1    1
+#define DEBUG_UART2    2
+#define DEBUG_UART3    3
+
+/* DEBUG UATR Definition */
+#define DEBUG   DEBUG_UART1
+//#define DEBUG   DEBUG_UART2
+//#define DEBUG   DEBUG_UART3
+
+
+void Delay_Init(void);
+void Delay_Us (uint32_t n);
+void Delay_Ms (uint32_t n);
+void USART_Printf_Init(uint32_t baudrate);
+
+#endif 
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/include/system_ch32v30x.h

@@ -0,0 +1,30 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Header File.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V30x_H 
+#define __SYSTEM_CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V30x_SYSTEM_H */
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/ch32v30x_it.c

@@ -0,0 +1,55 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Main Interrupt Service Routines.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_it.h"
+#include "board.h"
+#include <rtthread.h>
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+	GET_INT_SP();
+    rt_interrupt_enter();
+    rt_kprintf(" NMI Handler\r\n");
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    rt_kprintf(" hardfult\r\n");
+    rt_kprintf("mepc:%08x\r\n",__get_MEPC());
+    rt_kprintf("mcause:%08x\r\n",__get_MCAUSE());
+    rt_kprintf("mtval:%08x\r\n",__get_MTVAL());
+    while(1);
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/core_riscv.c

@@ -0,0 +1,554 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Source File
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/*********************************************************************
+ * @fn      __get_FFLAGS
+ *
+ * @brief   Return the Floating-Point Accrued Exceptions
+ *
+ * @return  fflags value
+ */
+uint32_t __get_FFLAGS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FFLAGS
+ *
+ * @brief   Set the Floating-Point Accrued Exceptions
+ *
+ * @param   value  - set FFLAGS value
+ *
+ * @return  none
+ */
+void __set_FFLAGS(uint32_t value)
+{
+  __ASM volatile ("csrw fflags, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_FRM
+ *
+ * @brief   Return the Floating-Point Dynamic Rounding Mode
+ *
+ * @return  frm value
+ */
+uint32_t __get_FRM(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "frm" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FRM
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set frm value
+ *
+ * @return  none
+ */
+void __set_FRM(uint32_t value)
+{
+  __ASM volatile ("csrw frm, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_FCSR
+ *
+ * @brief   Return the Floating-Point Control and Status Register
+ *
+ * @return  fcsr value
+ */
+uint32_t __get_FCSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FCSR
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set fcsr value
+ *
+ * @return  none
+ */
+void __set_FCSR(uint32_t value)
+{
+  __ASM volatile ("csrw fcsr, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MSTATUS
+ *
+ * @brief   Return the Machine Status Register
+ *
+ * @return  mstatus value
+ */
+uint32_t __get_MSTATUS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MSTATUS
+ *
+ * @brief   Set the Machine Status Register
+ *
+ * @param   value  - set mstatus value
+ *
+ * @return  none
+ */
+void __set_MSTATUS(uint32_t value)
+{
+  __ASM volatile ("csrw mstatus, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MISA
+ *
+ * @brief   Return the Machine ISA Register
+ *
+ * @return  misa value
+ */
+uint32_t __get_MISA(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "misa" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set misa value
+ *
+ * @return  none
+ */
+void __set_MISA(uint32_t value)
+{
+  __ASM volatile ("csrw misa, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MIE
+ *
+ * @brief   Return the Machine Interrupt Enable Register
+ *
+ * @return  mie value
+ */
+uint32_t __get_MIE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mie" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set mie value
+ *
+ * @return  none
+ */
+void __set_MIE(uint32_t value)
+{
+  __ASM volatile ("csrw mie, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Trap-Vector Base-Address Register
+ *
+ * @return  mtvec value
+ */
+uint32_t __get_MTVEC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Trap-Vector Base-Address Register
+ *
+ * @param   value  - set mtvec value
+ *
+ * @return  none
+ */
+void __set_MTVEC(uint32_t value)
+{
+  __ASM volatile ("csrw mtvec, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Seratch Register
+ *
+ * @return  mscratch value
+ */
+uint32_t __get_MSCRATCH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Seratch Register
+ *
+ * @param   value  - set mscratch value
+ *
+ * @return  none
+ */
+void __set_MSCRATCH(uint32_t value)
+{
+  __ASM volatile ("csrw mscratch, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MEPC
+ *
+ * @brief   Return the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+uint32_t __get_MEPC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+void __set_MEPC(uint32_t value)
+{
+  __ASM volatile ("csrw mepc, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCAUSE
+ *
+ * @brief   Return the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MCAUSE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+void __set_MCAUSE(uint32_t value)
+{
+  __ASM volatile ("csrw mcause, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVAL
+ *
+ * @brief   Return the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+uint32_t __get_MTVAL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVAL
+ *
+ * @brief   Set the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+void __set_MTVAL(uint32_t value)
+{
+  __ASM volatile ("csrw mtval, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MIP
+ *
+ * @brief   Return the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+uint32_t __get_MIP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mip" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MIP
+ *
+ * @brief   Set the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+void __set_MIP(uint32_t value)
+{
+  __ASM volatile ("csrw mip, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLE
+ *
+ * @brief   Return Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+uint32_t __get_MCYCLE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLE
+ *
+ * @brief   Set Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+void __set_MCYCLE(uint32_t value)
+{
+  __ASM volatile ("csrw mcycle, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLEH
+ *
+ * @brief   Return Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+uint32_t __get_MCYCLEH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLEH
+ *
+ * @brief   Set Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+void __set_MCYCLEH(uint32_t value)
+{
+  __ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRET
+ *
+ * @brief   Return Lower 32 bits of Instructions-retired counter
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MINSTRET(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRET
+ *
+ * @brief   Set Lower 32 bits of Instructions-retired counter
+ *
+ * @return  minstret value
+ */
+void __set_MINSTRET(uint32_t value)
+{
+  __ASM volatile ("csrw minstret, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRETH
+ *
+ * @brief   Return Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+uint32_t __get_MINSTRETH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRETH
+ *
+ * @brief   Set Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+void __set_MINSTRETH(uint32_t value)
+{
+  __ASM volatile ("csrw minstreth, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MVENDORID
+ *
+ * @brief   Return Vendor ID Register
+ *
+ * @return  mvendorid value
+ */
+uint32_t __get_MVENDORID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MARCHID
+ *
+ * @brief   Return Machine Architecture ID Register
+ *
+ * @return  marchid value
+ */
+uint32_t __get_MARCHID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MIMPID
+ *
+ * @brief   Return Machine Implementation ID Register
+ *
+ * @return  mimpid value
+ */
+uint32_t __get_MIMPID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MHARTID
+ *
+ * @brief   Return Hart ID Register
+ *
+ * @return  mhartid value
+ */
+uint32_t __get_MHARTID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_SP
+ *
+ * @brief   Return SP Register
+ *
+ * @return  SP value
+ */
+uint32_t __get_SP(void)
+{
+  uint32_t result;
+
+  asm volatile ( "mv %0," "sp" : "=r"(result) : );
+  return (result);
+}
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/debug.c

@@ -0,0 +1,193 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "debug.h"
+
+static uint8_t  p_us = 0;
+static uint16_t p_ms = 0;
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */
+void Delay_Init(void)
+{
+    p_us = SystemCoreClock / 8000000;
+    p_ms = (uint16_t)p_us * 1000;
+}
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_us;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->SR &= ~(1 << 0);
+    i = (uint32_t)n * p_ms;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1 << 4) | (1 << 5) | (1 << 0);
+
+    while((SysTick->SR & (1 << 0)) != (1 << 0))
+        ;
+    SysTick->CTLR &= ~(1 << 0);
+}
+
+/*********************************************************************
+ * @fn      USART_Printf_Init
+ *
+ * @brief   Initializes the USARTx peripheral.
+ *
+ * @param   baudrate - USART communication baud rate.
+ *
+ * @return  None
+ */
+void USART_Printf_Init(uint32_t baudrate)
+{
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+
+#if(DEBUG == DEBUG_UART1)
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART2)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART3)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#endif
+
+    USART_InitStructure.USART_BaudRate = baudrate;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+#if(DEBUG == DEBUG_UART1)
+    USART_Init(USART1, &USART_InitStructure);
+    USART_Cmd(USART1, ENABLE);
+
+#elif(DEBUG == DEBUG_UART2)
+    USART_Init(USART2, &USART_InitStructure);
+    USART_Cmd(USART2, ENABLE);
+
+#elif(DEBUG == DEBUG_UART3)
+    USART_Init(USART3, &USART_InitStructure);
+    USART_Cmd(USART3, ENABLE);
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      _write
+ *
+ * @brief   Support Printf Function
+ *
+ * @param   *buf - UART send Data.
+ *          size - Data length
+ *
+ * @return  size: Data length
+ */
+__attribute__((used)) int _write(int fd, char *buf, int size)
+{
+    int i;
+
+    for(i = 0; i < size; i++)
+    {
+#if(DEBUG == DEBUG_UART1)
+        while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+        USART_SendData(USART1, *buf++);
+#elif(DEBUG == DEBUG_UART2)
+        while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
+        USART_SendData(USART2, *buf++);
+#elif(DEBUG == DEBUG_UART3)
+        while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
+        USART_SendData(USART3, *buf++);
+#endif
+    }
+
+    return size;
+}
+
+/*********************************************************************
+ * @fn      _sbrk
+ *
+ * @brief   Change the spatial position of data segment.
+ *
+ * @return  size: Data length
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+    extern char _end[];
+    extern char _heap_end[];
+    static char *curbrk = _end;
+
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+    curbrk += incr;
+    return curbrk - incr;
+}
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/startup_ch32v30x.S

@@ -0,0 +1,387 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : startup_ch32v30x.s
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x vector table for eclipse toolchain.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00100073
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .word   TIM8_BRK_IRQHandler        /* TIM8 Break */
+    .word   TIM8_UP_IRQHandler         /* TIM8 Update */
+    .word   TIM8_TRG_COM_IRQHandler    /* TIM8 Trigger and Commutation */
+    .word   TIM8_CC_IRQHandler         /* TIM8 Capture Compare */
+    .word   RNG_IRQHandler             /* RNG */
+    .word   FSMC_IRQHandler            /* FSMC */
+    .word   SDIO_IRQHandler            /* SDIO */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   SPI3_IRQHandler            /* SPI3 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   UART5_IRQHandler           /* UART5 */
+    .word   TIM6_IRQHandler            /* TIM6 */
+    .word   TIM7_IRQHandler            /* TIM7 */
+    .word   DMA2_Channel1_IRQHandler   /* DMA2 Channel 1 */
+    .word   DMA2_Channel2_IRQHandler   /* DMA2 Channel 2 */
+    .word   DMA2_Channel3_IRQHandler   /* DMA2 Channel 3 */
+    .word   DMA2_Channel4_IRQHandler   /* DMA2 Channel 4 */
+    .word   DMA2_Channel5_IRQHandler   /* DMA2 Channel 5 */
+    .word   ETH_IRQHandler             /* ETH */
+    .word   ETH_WKUP_IRQHandler        /* ETH WakeUp */
+    .word   CAN2_TX_IRQHandler         /* CAN2 TX */
+    .word   CAN2_RX0_IRQHandler        /* CAN2 RX0 */
+    .word   CAN2_RX1_IRQHandler        /* CAN2 RX1 */
+    .word   CAN2_SCE_IRQHandler        /* CAN2 SCE */
+    .word   OTG_FS_IRQHandler          /* OTGFS */
+    .word   USBHSWakeup_IRQHandler     /* USBHS Wakeup */
+    .word   USBHS_IRQHandler           /* USBHS */
+    .word   DVP_IRQHandler             /* DVP */
+    .word   UART6_IRQHandler           /* UART6 */
+    .word   UART7_IRQHandler           /* UART7 */
+    .word   UART8_IRQHandler           /* UART8 */
+    .word   TIM9_BRK_IRQHandler        /* TIM9 Break */
+    .word   TIM9_UP_IRQHandler         /* TIM9 Update */
+    .word   TIM9_TRG_COM_IRQHandler    /* TIM9 Trigger and Commutation */
+    .word   TIM9_CC_IRQHandler         /* TIM9 Capture Compare */
+    .word   TIM10_BRK_IRQHandler       /* TIM10 Break */
+    .word   TIM10_UP_IRQHandler        /* TIM10 Update */
+    .word   TIM10_TRG_COM_IRQHandler   /* TIM10 Trigger and Commutation */
+    .word   TIM10_CC_IRQHandler        /* TIM10 Capture Compare */
+    .word   DMA2_Channel6_IRQHandler   /* DMA2 Channel 6 */
+    .word   DMA2_Channel7_IRQHandler   /* DMA2 Channel 7 */
+    .word   DMA2_Channel8_IRQHandler   /* DMA2 Channel 8 */
+    .word   DMA2_Channel9_IRQHandler   /* DMA2 Channel 9 */
+    .word   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
+    .word   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
+
+    .option rvc;
+
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   TIM8_BRK_IRQHandler        /* TIM8 Break */
+    .weak   TIM8_UP_IRQHandler         /* TIM8 Update */
+    .weak   TIM8_TRG_COM_IRQHandler    /* TIM8 Trigger and Commutation */
+    .weak   TIM8_CC_IRQHandler         /* TIM8 Capture Compare */
+    .weak   RNG_IRQHandler             /* RNG */
+    .weak   FSMC_IRQHandler            /* FSMC */
+    .weak   SDIO_IRQHandler            /* SDIO */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   SPI3_IRQHandler            /* SPI3 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   UART5_IRQHandler           /* UART5 */
+    .weak   TIM6_IRQHandler            /* TIM6 */
+    .weak   TIM7_IRQHandler            /* TIM7 */
+    .weak   DMA2_Channel1_IRQHandler   /* DMA2 Channel 1 */
+    .weak   DMA2_Channel2_IRQHandler   /* DMA2 Channel 2 */
+    .weak   DMA2_Channel3_IRQHandler   /* DMA2 Channel 3 */
+    .weak   DMA2_Channel4_IRQHandler   /* DMA2 Channel 4 */
+    .weak   DMA2_Channel5_IRQHandler   /* DMA2 Channel 5 */
+    .weak   ETH_IRQHandler             /* ETH */
+    .weak   ETH_WKUP_IRQHandler        /* ETH WakeUp */
+    .weak   CAN2_TX_IRQHandler         /* CAN2 TX */
+    .weak   CAN2_RX0_IRQHandler        /* CAN2 RX0 */
+    .weak   CAN2_RX1_IRQHandler        /* CAN2 RX1 */
+    .weak   CAN2_SCE_IRQHandler        /* CAN2 SCE */
+    .weak   OTG_FS_IRQHandler          /* OTGFS */
+    .weak   USBHSWakeup_IRQHandler     /* USBHS Wakeup */
+    .weak   USBHS_IRQHandler           /* USBHS */
+    .weak   DVP_IRQHandler             /* DVP */
+    .weak   UART6_IRQHandler           /* UART6 */
+    .weak   UART7_IRQHandler           /* UART7 */
+    .weak   UART8_IRQHandler           /* UART8 */
+    .weak   TIM9_BRK_IRQHandler        /* TIM9 Break */
+    .weak   TIM9_UP_IRQHandler         /* TIM9 Update */
+    .weak   TIM9_TRG_COM_IRQHandler    /* TIM9 Trigger and Commutation */
+    .weak   TIM9_CC_IRQHandler         /* TIM9 Capture Compare */
+    .weak   TIM10_BRK_IRQHandler       /* TIM10 Break */
+    .weak   TIM10_UP_IRQHandler        /* TIM10 Update */
+    .weak   TIM10_TRG_COM_IRQHandler   /* TIM10 Trigger and Commutation */
+    .weak   TIM10_CC_IRQHandler        /* TIM10 Capture Compare */
+    .weak   DMA2_Channel6_IRQHandler   /* DMA2 Channel 6 */
+    .weak   DMA2_Channel7_IRQHandler   /* DMA2 Channel 7 */
+    .weak   DMA2_Channel8_IRQHandler   /* DMA2 Channel 8 */
+    .weak   DMA2_Channel9_IRQHandler   /* DMA2 Channel 9 */
+    .weak   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
+    .weak   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
+
+NMI_Handler:  1:  j 1b
+HardFault_Handler:  1:  j 1b
+Ecall_M_Mode_Handler:  1:  j 1b
+Ecall_U_Mode_Handler:  1:  j 1b
+Break_Point_Handler:  1:  j 1b
+SysTick_Handler:  1:  j 1b
+SW_handler:  1:  j 1b
+WWDG_IRQHandler:  1:  j 1b
+PVD_IRQHandler:  1:  j 1b
+TAMPER_IRQHandler:  1:  j 1b
+RTC_IRQHandler:  1:  j 1b
+FLASH_IRQHandler:  1:  j 1b
+RCC_IRQHandler:  1:  j 1b
+EXTI0_IRQHandler:  1:  j 1b
+EXTI1_IRQHandler:  1:  j 1b
+EXTI2_IRQHandler:  1:  j 1b
+EXTI3_IRQHandler:  1:  j 1b
+EXTI4_IRQHandler:  1:  j 1b
+DMA1_Channel1_IRQHandler:  1:  j 1b
+DMA1_Channel2_IRQHandler:  1:  j 1b
+DMA1_Channel3_IRQHandler:  1:  j 1b
+DMA1_Channel4_IRQHandler:  1:  j 1b
+DMA1_Channel5_IRQHandler:  1:  j 1b
+DMA1_Channel6_IRQHandler:  1:  j 1b
+DMA1_Channel7_IRQHandler:  1:  j 1b
+ADC1_2_IRQHandler:  1:  j 1b
+USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
+USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
+CAN1_RX1_IRQHandler:  1:  j 1b
+CAN1_SCE_IRQHandler:  1:  j 1b
+EXTI9_5_IRQHandler:  1:  j 1b
+TIM1_BRK_IRQHandler:  1:  j 1b
+TIM1_UP_IRQHandler:  1:  j 1b
+TIM1_TRG_COM_IRQHandler:  1:  j 1b
+TIM1_CC_IRQHandler:  1:  j 1b
+TIM2_IRQHandler:  1:  j 1b
+TIM3_IRQHandler:  1:  j 1b
+TIM4_IRQHandler:  1:  j 1b
+I2C1_EV_IRQHandler:  1:  j 1b
+I2C1_ER_IRQHandler:  1:  j 1b
+I2C2_EV_IRQHandler:  1:  j 1b
+I2C2_ER_IRQHandler:  1:  j 1b
+SPI1_IRQHandler:  1:  j 1b
+SPI2_IRQHandler:  1:  j 1b
+USART1_IRQHandler:  1:  j 1b
+USART2_IRQHandler:  1:  j 1b
+USART3_IRQHandler:  1:  j 1b
+EXTI15_10_IRQHandler:  1:  j 1b
+RTCAlarm_IRQHandler:  1:  j 1b
+USBWakeUp_IRQHandler:  1:  j 1b
+TIM8_BRK_IRQHandler:  1:  j 1b
+TIM8_UP_IRQHandler:  1:  j 1b
+TIM8_TRG_COM_IRQHandler:  1:  j 1b
+TIM8_CC_IRQHandler:  1:  j 1b
+RNG_IRQHandler:  1:  j 1b
+FSMC_IRQHandler:  1:  j 1b
+SDIO_IRQHandler:  1:  j 1b
+TIM5_IRQHandler:  1:  j 1b
+SPI3_IRQHandler:  1:  j 1b
+UART4_IRQHandler:  1:  j 1b
+UART5_IRQHandler:  1:  j 1b
+TIM6_IRQHandler:  1:  j 1b
+TIM7_IRQHandler:  1:  j 1b
+DMA2_Channel1_IRQHandler:  1:  j 1b
+DMA2_Channel2_IRQHandler:  1:  j 1b
+DMA2_Channel3_IRQHandler:  1:  j 1b
+DMA2_Channel4_IRQHandler:  1:  j 1b
+DMA2_Channel5_IRQHandler:  1:  j 1b
+ETH_IRQHandler:  1:  j 1b
+ETH_WKUP_IRQHandler:  1:  j 1b
+CAN2_TX_IRQHandler:  1:  j 1b
+CAN2_RX0_IRQHandler:  1:  j 1b
+CAN2_RX1_IRQHandler:  1:  j 1b
+CAN2_SCE_IRQHandler:  1:  j 1b
+OTG_FS_IRQHandler:  1:  j 1b
+USBHSWakeup_IRQHandler:  1:  j 1b
+USBHS_IRQHandler:  1:  j 1b
+DVP_IRQHandler:  1:  j 1b
+UART6_IRQHandler:  1:  j 1b
+UART7_IRQHandler:  1:  j 1b
+UART8_IRQHandler:  1:  j 1b
+TIM9_BRK_IRQHandler:  1:  j 1b
+TIM9_UP_IRQHandler:  1:  j 1b
+TIM9_TRG_COM_IRQHandler:  1:  j 1b
+TIM9_CC_IRQHandler:  1:  j 1b
+TIM10_BRK_IRQHandler:  1:  j 1b
+TIM10_UP_IRQHandler:  1:  j 1b
+TIM10_TRG_COM_IRQHandler:  1:  j 1b
+TIM10_CC_IRQHandler:  1:  j 1b
+DMA2_Channel6_IRQHandler:  1:  j 1b
+DMA2_Channel7_IRQHandler:  1:  j 1b
+DMA2_Channel8_IRQHandler:  1:  j 1b
+DMA2_Channel9_IRQHandler:  1:  j 1b
+DMA2_Channel10_IRQHandler:  1:  j 1b
+DMA2_Channel11_IRQHandler:  1:  j 1b
+
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+    csrw mepc, t0
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+	/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+	/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+    li t0, 0x1f
+    csrw 0xbc0, t0
+
+    /* Enable hardware stack */
+    li t0,0x1
+	csrw 0x804, t0
+
+
+    /* Enable floating point and interrupt */
+   	li t0, 0x7800
+   	csrs mstatus, t0
+
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, entry
+	csrw mepc, t0
+	mret
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/system_ch32v30x.c

@@ -0,0 +1,776 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Source File.
+*                      For HSE = 8Mhz
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+/* #define SYSCLK_FREQ_24MHz  24000000  */ 
+//#define SYSCLK_FREQ_48MHz  48000000
+/* #define SYSCLK_FREQ_56MHz  56000000  */  
+//#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+//#define SYSCLK_FREQ_120MHz  120000000
+#define SYSCLK_FREQ_144MHz  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+
+#elif defined SYSCLK_FREQ_96MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
+
+#else /* HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#elif defined SYSCLK_FREQ_120MHz
+  static void SetSysClockTo120(void);
+#elif defined SYSCLK_FREQ_144MHz
+  static void SetSysClockTo144(void);
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+
+#ifdef CH32V30x_D8C
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+#endif 
+
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+
+#ifdef CH32V30x_D8C
+  RCC->CTLR &= (uint32_t)0xEBFFFFFF;
+  RCC->INTR = 0x00FF0000;
+  RCC->CFGR2 = 0x00000000;
+#else
+  RCC->INTR = 0x009F0000;   
+#endif   
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+	
+  tmp = RCC->CFGR0 & RCC_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08: 
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC; 
+      pllmull = ( pllmull >> 18) + 2;
+	  
+#ifdef CH32V30x_D8
+          if(pllmull == 17) pllmull = 18;
+#else
+          if(pllmull == 2) pllmull = 18;
+          if(pllmull == 15){
+              pllmull = 13;  /* *6.5 */
+              Pll_6_5 = 1;
+          }
+          if(pllmull == 16) pllmull = 15;
+          if(pllmull == 17) pllmull = 16;
+#endif
+	  
+      if (pllsource == 0x00)
+      {
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {    
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+ 
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;  
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+  SetSysClockTo96();
+#elif defined SYSCLK_FREQ_120MHz
+  SetSysClockTo120();
+#elif defined SYSCLK_FREQ_144MHz
+  SetSysClockTo144();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+	*/ 
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
+#endif
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+		
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {	
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+		/* 
+		 * If HSE fails to start-up, the application will have wrong clock 
+     * configuration. User can add here some code to deal with this error 
+		 */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo96
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo120
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo144
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#endif

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/SConscript

@@ -0,0 +1,78 @@
+#-*- encoding: utf-8 -*-
+
+import os
+from building import * 
+Import('RTT_ROOT')
+Import('rtconfig')
+
+#---------------------------------------------------------------------------------
+# Package configuration
+#---------------------------------------------------------------------------------
+PKGNAME = "ch32v307_hal"
+VERSION = "v1.0.0"
+DEPENDS = [""]
+
+#---------------------------------------------------------------------------------
+# Compile the configuration 
+#
+# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
+# 
+# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
+# LOCAL_CCFLAGS: Local compilation parameter 
+# LOCAL_ASFLAGS: Local assembly parameters
+# 
+# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH 
+#          is empty # no pass!!!
+# CCFLAGS: Global compilation parameter 
+# ASFLAGS: Global assembly parameters
+#
+# CPPDEFINES: Global macro definition
+# LOCAL_CPPDEFINES: Local macro definition 
+# 
+# LIBS: Specify the static library that need to be linked
+# LIBPATH: Specify the search directory for the library file (.lib/.a)
+#
+# LINKFLAGS: Link options
+#---------------------------------------------------------------------------------
+CWD              = GetCurrentDir()
+SOURCES          = Glob("./source/*.c")
+
+LOCAL_CPPPATH    = [] 
+LOCAL_CCFLAGS    = "" 
+LOCAL_ASFLAGS    = ""
+
+CPPPATH          = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')] 
+CCFLAGS          = "" 
+ASFLAGS          = ""
+
+CPPDEFINES       = []
+LOCAL_CPPDEFINES = []
+
+LIBS             = [] 
+LIBPATH          = []
+
+LINKFLAGS        = "" 
+
+SOURCES_IGNORE   = []
+CPPPATH_IGNORE   = []
+
+#---------------------------------------------------------------------------------
+# Main target
+#---------------------------------------------------------------------------------
+objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS, 
+                   CPPPATH          = CPPPATH, 
+                   CCFLAGS          = CCFLAGS, 
+                   ASFLAGS          = ASFLAGS, 
+                   LOCAL_CPPPATH    = LOCAL_CPPPATH, 
+                   LOCAL_CCFLAGS    = LOCAL_CCFLAGS, 
+                   LOCAL_ASFLAGS    = LOCAL_ASFLAGS, 
+                   CPPDEFINES       = CPPDEFINES, 
+                   LOCAL_CPPDEFINES = LOCAL_CPPDEFINES,
+                   LIBS             = LIBS, 
+                   LIBPATH          = LIBPATH, 
+                   LINKFLAGS        = LINKFLAGS)  
+
+Return("objs") 
+#---------------------------------------------------------------------------------
+# End
+#---------------------------------------------------------------------------------

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x.h

@@ -0,0 +1,5242 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer Header File.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/   
+#ifndef __CH32V30x_H
+#define __CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+//#define CH32V30x_D8              /* CH32V303x */
+#define CH32V30x_D8C             /* CH32V307x-CH32V305x */
+  
+#define __MPU_PRESENT             0 /* Other CH32 devices does not provide an MPU */
+#define __Vendor_SysTickConfig    0 /* Set to 1 if different SysTick Config is used */	 
+	 
+#define HSE_VALUE    ((uint32_t)8000000) /* Value of the External oscillator in Hz */
+
+/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x1000) /* Time out for HSE start up */
+
+#define HSI_VALUE    ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+
+/* Interrupt Number Definition, according to the selected device */	 
+typedef enum IRQn
+{
+ /******  RISC-V Processor Exceptions Numbers *******************************************************/
+  NonMaskableInt_IRQn         = 2,       /* 2 Non Maskable Interrupt                             */
+  EXC_IRQn                    = 3,       /* 3 Exception Interrupt                                */
+  Ecall_M_Mode_IRQn           = 5,       /* 5 Ecall M Mode Interrupt                             */
+  Ecall_U_Mode_IRQn           = 8,       /* 8 Ecall U Mode Interrupt                             */
+  Break_Point_IRQn            = 9,       /* 9 Break Point Interrupt                              */
+  SysTicK_IRQn                = 12,      /* 12 System timer Interrupt                            */
+  Software_IRQn               = 14,      /* 14 software Interrupt                                */
+
+ /******  RISC-V specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 16,      /* Window WatchDog Interrupt                            */
+  PVD_IRQn                    = 17,      /* PVD through EXTI Line detection Interrupt            */
+  TAMPER_IRQn                 = 18,      /* Tamper Interrupt                                     */
+  RTC_IRQn                    = 19,      /* RTC global Interrupt                                 */
+  FLASH_IRQn                  = 20,      /* FLASH global Interrupt                               */
+  RCC_IRQn                    = 21,      /* RCC global Interrupt                                 */
+  EXTI0_IRQn                  = 22,      /* EXTI Line0 Interrupt                                 */
+  EXTI1_IRQn                  = 23,      /* EXTI Line1 Interrupt                                 */
+  EXTI2_IRQn                  = 24,      /* EXTI Line2 Interrupt                                 */
+  EXTI3_IRQn                  = 25,      /* EXTI Line3 Interrupt                                 */
+  EXTI4_IRQn                  = 26,      /* EXTI Line4 Interrupt                                 */
+  DMA1_Channel1_IRQn          = 27,      /* DMA1 Channel 1 global Interrupt                      */
+  DMA1_Channel2_IRQn          = 28,      /* DMA1 Channel 2 global Interrupt                      */
+  DMA1_Channel3_IRQn          = 29,      /* DMA1 Channel 3 global Interrupt                      */
+  DMA1_Channel4_IRQn          = 30,      /* DMA1 Channel 4 global Interrupt                      */
+  DMA1_Channel5_IRQn          = 31,      /* DMA1 Channel 5 global Interrupt                      */
+  DMA1_Channel6_IRQn          = 32,      /* DMA1 Channel 6 global Interrupt                      */
+  DMA1_Channel7_IRQn          = 33,      /* DMA1 Channel 7 global Interrupt                      */
+  ADC_IRQn                    = 34,      /* ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 35,      /* USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 36,      /* USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 37,      /* CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 38,      /* CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 39,      /* External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 40,      /* TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 41,      /* TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 42,      /* TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 43,      /* TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 44,      /* TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 45,      /* TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 46,      /* TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 47,      /* I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 48,      /* I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 49,      /* I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 50,      /* I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 51,      /* SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 52,      /* SPI2 global Interrupt                                */
+  USART1_IRQn                 = 53,      /* USART1 global Interrupt                              */
+  USART2_IRQn                 = 54,      /* USART2 global Interrupt                              */
+  USART3_IRQn                 = 55,      /* USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 56,      /* External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 57,      /* RTC Alarm through EXTI Line Interrupt                */
+
+#ifdef CH32V30x_D8
+  TIM8_BRK_IRQn               = 59,      /* TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 60,      /* TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 61,      /* TIM8 Trigger and Commutation Interrupt               */
+  TIM8_CC_IRQn                = 62,      /* TIM8 Capture Compare Interrupt                       */
+  RNG_IRQn                    = 63,      /* RNG global Interrupt                                 */
+  FSMC_IRQn                   = 64,      /* FSMC global Interrupt                                */
+  SDIO_IRQn                   = 65,      /* SDIO global Interrupt                                */
+  TIM5_IRQn                   = 66,      /* TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 67,      /* SPI3 global Interrupt                                */
+  UART4_IRQn                  = 68,      /* UART4 global Interrupt                               */
+  UART5_IRQn                  = 69,      /* UART5 global Interrupt                               */
+  TIM6_IRQn                   = 70,      /* TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 71,      /* TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 72,      /* DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 73,      /* DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 74,      /* DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_IRQn          = 75,      /* DMA2 Channel 4 global Interrupt                      */
+  DMA2_Channel5_IRQn          = 76,      /* DMA2 Channel 5 global Interrupt                      */
+  OTG_FS_IRQn                 = 83,      /* OTGFS global Interrupt                               */
+  UART6_IRQn                  = 87,      /* UART6 global Interrupt                               */
+  UART7_IRQn                  = 88,      /* UART7 global Interrupt                               */
+  UART8_IRQn                  = 89,      /* UART8 global Interrupt                               */
+  TIM9_BRK_IRQn               = 90,      /* TIM9 Break Interrupt                                 */
+  TIM9_UP_IRQn                = 91,      /* TIM9 Update Interrupt                                */
+  TIM9_TRG_COM_IRQn           = 92,      /* TIM9 Trigger and Commutation Interrupt               */
+  TIM9_CC_IRQn                = 93,      /* TIM9 Capture Compare Interrupt                       */
+  TIM10_BRK_IRQn              = 94,      /* TIM10 Break Interrupt                                */
+  TIM10_UP_IRQn               = 95,      /* TIM10 Update Interrupt                               */
+  TIM10_TRG_COM_IRQn          = 96,      /* TIM10 Trigger and Commutation Interrupt              */
+  TIM10_CC_IRQn               = 97,      /* TIM10 Capture Compare Interrupt                      */
+  DMA2_Channel6_IRQn          = 98,      /* DMA2 Channel 6 global Interrupt                      */
+  DMA2_Channel7_IRQn          = 99,      /* DMA2 Channel 7 global Interrupt                      */
+  DMA2_Channel8_IRQn          = 100,     /* DMA2 Channel 8 global Interrupt                      */
+  DMA2_Channel9_IRQn          = 101,     /* DMA2 Channel 9 global Interrupt                      */
+  DMA2_Channel10_IRQn         = 102,     /* DMA2 Channel 10 global Interrupt                     */
+  DMA2_Channel11_IRQn         = 103,     /* DMA2 Channel 11 global Interrupt                     */
+
+#endif
+
+#ifdef CH32V30x_D8C
+  USBWakeUp_IRQn              = 58,      /* USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_IRQn               = 59,      /* TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 60,      /* TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 61,      /* TIM8 Trigger and Commutation Interrupt               */
+  TIM8_CC_IRQn                = 62,      /* TIM8 Capture Compare Interrupt                       */
+  RNG_IRQn                    = 63,      /* RNG global Interrupt                                 */
+  FSMC_IRQn                   = 64,      /* FSMC global Interrupt                                */
+  SDIO_IRQn                   = 65,      /* SDIO global Interrupt                                */
+  TIM5_IRQn                   = 66,      /* TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 67,      /* SPI3 global Interrupt                                */
+  UART4_IRQn                  = 68,      /* UART4 global Interrupt                               */
+  UART5_IRQn                  = 69,      /* UART5 global Interrupt                               */
+  TIM6_IRQn                   = 70,      /* TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 71,      /* TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 72,      /* DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 73,      /* DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 74,      /* DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_IRQn          = 75,      /* DMA2 Channel 4 global Interrupt                      */
+  DMA2_Channel5_IRQn          = 76,      /* DMA2 Channel 5 global Interrupt                      */
+  ETH_IRQn                    = 77,      /* ETH global Interrupt                                 */
+  ETH_WKUP_IRQn               = 78,      /* ETH WakeUp Interrupt                                 */
+  CAN2_TX_IRQn                = 79,      /* CAN2 TX Interrupts                                   */
+  CAN2_RX0_IRQn               = 80,      /* CAN2 RX0 Interrupts                                  */
+  CAN2_RX1_IRQn               = 81,      /* CAN2 RX1 Interrupt                                   */
+  CAN2_SCE_IRQn               = 82,      /* CAN2 SCE Interrupt                                   */
+  OTG_FS_IRQn                 = 83,      /* OTGFS global Interrupt                               */
+  USBHSWakeup_IRQn            = 84,      /* USBHS WakeUp Interrupt                               */
+  USBHS_IRQn                  = 85,      /* USBHS global Interrupt                               */
+  DVP_IRQn                    = 86,      /* DVP global Interrupt                                 */
+  UART6_IRQn                  = 87,      /* UART6 global Interrupt                               */
+  UART7_IRQn                  = 88,      /* UART7 global Interrupt                               */
+  UART8_IRQn                  = 89,      /* UART8 global Interrupt                               */
+  TIM9_BRK_IRQn               = 90,      /* TIM9 Break Interrupt                                 */
+  TIM9_UP_IRQn                = 91,      /* TIM9 Update Interrupt                                */
+  TIM9_TRG_COM_IRQn           = 92,      /* TIM9 Trigger and Commutation Interrupt               */
+  TIM9_CC_IRQn                = 93,      /* TIM9 Capture Compare Interrupt                       */
+  TIM10_BRK_IRQn              = 94,      /* TIM10 Break Interrupt                                */
+  TIM10_UP_IRQn               = 95,      /* TIM10 Update Interrupt                               */
+  TIM10_TRG_COM_IRQn          = 96,      /* TIM10 Trigger and Commutation Interrupt              */
+  TIM10_CC_IRQn               = 97,      /* TIM10 Capture Compare Interrupt                      */
+  DMA2_Channel6_IRQn          = 98,      /* DMA2 Channel 6 global Interrupt                      */
+  DMA2_Channel7_IRQn          = 99,      /* DMA2 Channel 7 global Interrupt                      */
+  DMA2_Channel8_IRQn          = 100,     /* DMA2 Channel 8 global Interrupt                      */
+  DMA2_Channel9_IRQn          = 101,     /* DMA2 Channel 9 global Interrupt                      */
+  DMA2_Channel10_IRQn         = 102,     /* DMA2 Channel 10 global Interrupt                     */
+  DMA2_Channel11_IRQn         = 103,     /* DMA2 Channel 11 global Interrupt                     */
+
+#endif
+} IRQn_Type;
+
+#define HardFault_IRQn   EXC_IRQn
+#define ADC1_2_IRQn      ADC_IRQn
+
+
+#include <stdint.h>
+#include "core_riscv.h"
+#include "system_ch32v30x.h"
+
+
+/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSI_Value            HSI_VALUE 
+#define HSE_Value            HSE_VALUE
+#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
+
+/* Analog to Digital Converter */
+typedef struct
+{
+  __IO uint32_t STATR;
+  __IO uint32_t CTLR1;
+  __IO uint32_t CTLR2;
+  __IO uint32_t SAMPTR1;
+  __IO uint32_t SAMPTR2;
+  __IO uint32_t IOFR1;
+  __IO uint32_t IOFR2;
+  __IO uint32_t IOFR3;
+  __IO uint32_t IOFR4;
+  __IO uint32_t WDHTR;
+  __IO uint32_t WDLTR;
+  __IO uint32_t RSQR1;
+  __IO uint32_t RSQR2;
+  __IO uint32_t RSQR3;
+  __IO uint32_t ISQR;
+  __IO uint32_t IDATAR1;
+  __IO uint32_t IDATAR2;
+  __IO uint32_t IDATAR3;
+  __IO uint32_t IDATAR4;
+  __IO uint32_t RDATAR;
+} ADC_TypeDef;
+
+/* Backup Registers */
+typedef struct
+{
+  uint32_t  RESERVED0;
+  __IO uint16_t DATAR1;
+  uint16_t  RESERVED1;
+  __IO uint16_t DATAR2;
+  uint16_t  RESERVED2;
+  __IO uint16_t DATAR3;
+  uint16_t  RESERVED3;
+  __IO uint16_t DATAR4;
+  uint16_t  RESERVED4;
+  __IO uint16_t DATAR5;
+  uint16_t  RESERVED5;
+  __IO uint16_t DATAR6;
+  uint16_t  RESERVED6;
+  __IO uint16_t DATAR7;
+  uint16_t  RESERVED7;
+  __IO uint16_t DATAR8;
+  uint16_t  RESERVED8;
+  __IO uint16_t DATAR9;
+  uint16_t  RESERVED9;
+  __IO uint16_t DATAR10;
+  uint16_t  RESERVED10; 
+  __IO uint16_t OCTLR;
+  uint16_t  RESERVED11;
+  __IO uint16_t TPCTLR;
+  uint16_t  RESERVED12;
+  __IO uint16_t TPCSR;
+  uint16_t  RESERVED13[5];
+  __IO uint16_t DATAR11;
+  uint16_t  RESERVED14;
+  __IO uint16_t DATAR12;
+  uint16_t  RESERVED15;
+  __IO uint16_t DATAR13;
+  uint16_t  RESERVED16;
+  __IO uint16_t DATAR14;
+  uint16_t  RESERVED17;
+  __IO uint16_t DATAR15;
+  uint16_t  RESERVED18;
+  __IO uint16_t DATAR16;
+  uint16_t  RESERVED19;
+  __IO uint16_t DATAR17;
+  uint16_t  RESERVED20;
+  __IO uint16_t DATAR18;
+  uint16_t  RESERVED21;
+  __IO uint16_t DATAR19;
+  uint16_t  RESERVED22;
+  __IO uint16_t DATAR20;
+  uint16_t  RESERVED23;
+  __IO uint16_t DATAR21;
+  uint16_t  RESERVED24;
+  __IO uint16_t DATAR22;
+  uint16_t  RESERVED25;
+  __IO uint16_t DATAR23;
+  uint16_t  RESERVED26;
+  __IO uint16_t DATAR24;
+  uint16_t  RESERVED27;
+  __IO uint16_t DATAR25;
+  uint16_t  RESERVED28;
+  __IO uint16_t DATAR26;
+  uint16_t  RESERVED29;
+  __IO uint16_t DATAR27;
+  uint16_t  RESERVED30;
+  __IO uint16_t DATAR28;
+  uint16_t  RESERVED31;
+  __IO uint16_t DATAR29;
+  uint16_t  RESERVED32;
+  __IO uint16_t DATAR30;
+  uint16_t  RESERVED33; 
+  __IO uint16_t DATAR31;
+  uint16_t  RESERVED34;
+  __IO uint16_t DATAR32;
+  uint16_t  RESERVED35;
+  __IO uint16_t DATAR33;
+  uint16_t  RESERVED36;
+  __IO uint16_t DATAR34;
+  uint16_t  RESERVED37;
+  __IO uint16_t DATAR35;
+  uint16_t  RESERVED38;
+  __IO uint16_t DATAR36;
+  uint16_t  RESERVED39;
+  __IO uint16_t DATAR37;
+  uint16_t  RESERVED40;
+  __IO uint16_t DATAR38;
+  uint16_t  RESERVED41;
+  __IO uint16_t DATAR39;
+  uint16_t  RESERVED42;
+  __IO uint16_t DATAR40;
+  uint16_t  RESERVED43;
+  __IO uint16_t DATAR41;
+  uint16_t  RESERVED44;
+  __IO uint16_t DATAR42;
+  uint16_t  RESERVED45;    
+} BKP_TypeDef;
+
+/* Controller Area Network TxMailBox */
+typedef struct
+{
+  __IO uint32_t TXMIR;
+  __IO uint32_t TXMDTR;
+  __IO uint32_t TXMDLR;
+  __IO uint32_t TXMDHR;
+} CAN_TxMailBox_TypeDef;
+
+/* Controller Area Network FIFOMailBox */ 
+typedef struct
+{
+  __IO uint32_t RXMIR;
+  __IO uint32_t RXMDTR;
+  __IO uint32_t RXMDLR;
+  __IO uint32_t RXMDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/* Controller Area Network FilterRegister */  
+typedef struct
+{
+  __IO uint32_t FR1;
+  __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/* Controller Area Network */  
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t STATR;
+  __IO uint32_t TSTATR;
+  __IO uint32_t RFIFO0;
+  __IO uint32_t RFIFO1;
+  __IO uint32_t INTENR;
+  __IO uint32_t ERRSR;
+  __IO uint32_t BTIMR;
+  uint32_t  RESERVED0[88];
+  CAN_TxMailBox_TypeDef sTxMailBox[3];
+  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+  uint32_t  RESERVED1[12];
+  __IO uint32_t FCTLR;
+  __IO uint32_t FMCFGR;
+  uint32_t  RESERVED2;
+  __IO uint32_t FSCFGR;
+  uint32_t  RESERVED3;
+  __IO uint32_t FAFIFOR;
+  uint32_t  RESERVED4;
+  __IO uint32_t FWR;
+  uint32_t  RESERVED5[8];
+  CAN_FilterRegister_TypeDef sFilterRegister[28];
+} CAN_TypeDef;
+
+/* CRC Calculation Unit */
+typedef struct
+{
+  __IO uint32_t DATAR;
+  __IO uint8_t  IDATAR;
+  uint8_t   RESERVED0;
+  uint16_t  RESERVED1;
+  __IO uint32_t CTLR;
+} CRC_TypeDef;
+
+/* Digital to Analog Converter */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t SWTR;
+  __IO uint32_t R12BDHR1;
+  __IO uint32_t L12BDHR1;
+  __IO uint32_t R8BDHR1;
+  __IO uint32_t R12BDHR2;
+  __IO uint32_t L12BDHR2;
+  __IO uint32_t R8BDHR2;
+  __IO uint32_t RD12BDHR;
+  __IO uint32_t LD12BDHR;
+  __IO uint32_t RD8BDHR;
+  __IO uint32_t DOR1;
+  __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/* DMA Channel Controller */
+typedef struct
+{
+  __IO uint32_t CFGR;
+  __IO uint32_t CNTR;
+  __IO uint32_t PADDR;
+  __IO uint32_t MADDR;
+} DMA_Channel_TypeDef;
+
+/* DMA Controller */
+typedef struct
+{
+  __IO uint32_t INTFR;
+  __IO uint32_t INTFCR;
+} DMA_TypeDef;
+
+/* External Interrupt/Event Controller */
+typedef struct
+{
+  __IO uint32_t INTENR; 
+  __IO uint32_t EVENR;   
+  __IO uint32_t RTENR;   
+  __IO uint32_t FTENR;   
+  __IO uint32_t SWIEVR;  
+  __IO uint32_t INTFR;   
+} EXTI_TypeDef;
+
+/* FLASH Registers */
+typedef struct
+{
+  __IO uint32_t ACTLR;
+  __IO uint32_t KEYR;
+  __IO uint32_t OBKEYR;
+  __IO uint32_t STATR;
+  __IO uint32_t CTLR;
+  __IO uint32_t ADDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t OBR;
+  __IO uint32_t WPR;
+  __IO uint32_t MODEKEYR;
+} FLASH_TypeDef;
+
+/* Option Bytes Registers */  
+typedef struct
+{
+  __IO uint16_t RDPR;
+  __IO uint16_t USER;
+  __IO uint16_t Data0;
+  __IO uint16_t Data1;
+  __IO uint16_t WRPR0;
+  __IO uint16_t WRPR1;
+  __IO uint16_t WRPR2;
+  __IO uint16_t WRPR3;
+} OB_TypeDef;
+
+/* FSMC Bank1 Registers */ 
+typedef struct
+{
+  __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/* FSMC Bank1E Registers */ 
+typedef struct
+{
+  __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/* FSMC Bank2 Registers */ 
+typedef struct
+{
+  __IO uint32_t PCR2;
+  __IO uint32_t SR2;
+  __IO uint32_t PMEM2;
+  __IO uint32_t PATT2;
+  uint32_t  RESERVED0;
+  __IO uint32_t ECCR2;
+} FSMC_Bank2_TypeDef;
+
+/* General Purpose I/O */
+typedef struct
+{
+  __IO uint32_t CFGLR;
+  __IO uint32_t CFGHR;
+  __IO uint32_t INDR;
+  __IO uint32_t OUTDR;
+  __IO uint32_t BSHR;
+  __IO uint32_t BCR;
+  __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/* Alternate Function I/O */
+typedef struct
+{
+  __IO uint32_t ECR;
+  __IO uint32_t PCFR1;
+  __IO uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  __IO uint32_t PCFR2;  
+} AFIO_TypeDef;
+
+/* Inter Integrated Circuit Interface */
+typedef struct
+{
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t OADDR1;
+  uint16_t  RESERVED2;
+  __IO uint16_t OADDR2;
+  uint16_t  RESERVED3;
+  __IO uint16_t DATAR;
+  uint16_t  RESERVED4;
+  __IO uint16_t STAR1;
+  uint16_t  RESERVED5;
+  __IO uint16_t STAR2;
+  uint16_t  RESERVED6;
+  __IO uint16_t CKCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t RTR;
+  uint16_t  RESERVED8;
+} I2C_TypeDef;
+
+/* Independent WatchDog */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t PSCR;
+  __IO uint32_t RLDR;
+  __IO uint32_t STATR;
+} IWDG_TypeDef;
+
+/* Power Control */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/* Reset and Clock Control */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t CFGR0;
+  __IO uint32_t INTR;
+  __IO uint32_t APB2PRSTR;
+  __IO uint32_t APB1PRSTR;
+  __IO uint32_t AHBPCENR;
+  __IO uint32_t APB2PCENR;
+  __IO uint32_t APB1PCENR;
+  __IO uint32_t BDCTLR;
+  __IO uint32_t RSTSCKR;
+
+  __IO uint32_t AHBRSTR;
+  __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/* Real-Time Clock */
+typedef struct
+{
+  __IO uint16_t CTLRH;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLRL;
+  uint16_t  RESERVED1;
+  __IO uint16_t PSCRH;
+  uint16_t  RESERVED2;
+  __IO uint16_t PSCRL;
+  uint16_t  RESERVED3;
+  __IO uint16_t DIVH;
+  uint16_t  RESERVED4;
+  __IO uint16_t DIVL;
+  uint16_t  RESERVED5;
+  __IO uint16_t CNTH;
+  uint16_t  RESERVED6;
+  __IO uint16_t CNTL;
+  uint16_t  RESERVED7;
+  __IO uint16_t ALRMH;
+  uint16_t  RESERVED8;
+  __IO uint16_t ALRML;
+  uint16_t  RESERVED9;
+} RTC_TypeDef;
+
+/* SDIO Registers */ 
+typedef struct
+{
+  __IO uint32_t POWER;
+  __IO uint32_t CLKCR;
+  __IO uint32_t ARG;
+  __IO uint32_t CMD;
+  __I uint32_t RESPCMD;
+  __I uint32_t RESP1;
+  __I uint32_t RESP2;
+  __I uint32_t RESP3;
+  __I uint32_t RESP4;
+  __IO uint32_t DTIMER;
+  __IO uint32_t DLEN;
+  __IO uint32_t DCTRL;
+  __I uint32_t DCOUNT;
+  __I uint32_t STA;
+  __IO uint32_t ICR;
+  __IO uint32_t MASK;
+  uint32_t  RESERVED0[2];
+  __I uint32_t FIFOCNT;
+  uint32_t  RESERVED1[13];
+  __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/* Serial Peripheral Interface */
+typedef struct
+{
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t STATR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DATAR;
+  uint16_t  RESERVED3;
+  __IO uint16_t CRCR;
+  uint16_t  RESERVED4;
+  __IO uint16_t RCRCR;
+  uint16_t  RESERVED5;
+  __IO uint16_t TCRCR;
+  uint16_t  RESERVED6;
+  __IO uint16_t I2SCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t I2SPR;
+  uint16_t  RESERVED8;
+  __IO uint16_t HSCR;
+  uint16_t  RESERVED9;
+} SPI_TypeDef;
+
+/* TIM */
+typedef struct
+{
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SMCFGR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DMAINTENR;
+  uint16_t  RESERVED3;
+  __IO uint16_t INTFR;
+  uint16_t  RESERVED4;
+  __IO uint16_t SWEVGR;
+  uint16_t  RESERVED5;
+  __IO uint16_t CHCTLR1;
+  uint16_t  RESERVED6;
+  __IO uint16_t CHCTLR2;
+  uint16_t  RESERVED7;
+  __IO uint16_t CCER;
+  uint16_t  RESERVED8;
+  __IO uint16_t CNT;
+  uint16_t  RESERVED9;
+  __IO uint16_t PSC;
+  uint16_t  RESERVED10;
+  __IO uint16_t ATRLR;
+  uint16_t  RESERVED11;
+  __IO uint16_t RPTCR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CH1CVR;
+  uint16_t  RESERVED13;
+  __IO uint16_t CH2CVR;
+  uint16_t  RESERVED14;
+  __IO uint16_t CH3CVR;
+  uint16_t  RESERVED15;
+  __IO uint16_t CH4CVR;
+  uint16_t  RESERVED16;
+  __IO uint16_t BDTR;
+  uint16_t  RESERVED17;
+  __IO uint16_t DMACFGR;
+  uint16_t  RESERVED18;
+  __IO uint16_t DMAADR;
+  uint16_t  RESERVED19;
+} TIM_TypeDef;
+
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+typedef struct
+{
+  __IO uint16_t STATR;
+  uint16_t  RESERVED0;
+  __IO uint16_t DATAR;
+  uint16_t  RESERVED1;
+  __IO uint16_t BRR;
+  uint16_t  RESERVED2;
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED3;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED4;
+  __IO uint16_t CTLR3;
+  uint16_t  RESERVED5;
+  __IO uint16_t GPR;
+  uint16_t  RESERVED6;
+} USART_TypeDef;
+
+/* Window WatchDog */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t CFGR;
+  __IO uint32_t STATR;
+} WWDG_TypeDef;
+
+/* Enhanced Registers */
+typedef struct
+{
+  __IO uint32_t EXTEN_CTR;
+} EXTEN_TypeDef;
+
+/* OPA Registers */
+typedef struct
+{
+  __IO uint32_t CR;
+} OPA_TypeDef;
+
+/* RNG Registers */
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t SR;
+  __IO uint32_t DR;
+} RNG_TypeDef;
+
+/* DVP Registers */
+typedef struct
+{
+  __IO uint8_t CR0;
+  __IO uint8_t CR1;
+  __IO uint8_t IER;
+  __IO uint8_t Reserved0;        
+  __IO uint16_t ROW_NUM;
+  __IO uint16_t COL_NUM;
+  __IO uint32_t DMA_BUF0;
+  __IO uint32_t DMA_BUF1;
+  __IO uint8_t IFR;
+  __IO uint8_t STATUS;
+  __IO uint16_t Reserved1;            
+  __IO uint16_t ROW_CNT;
+  __IO uint16_t Reserved2;           
+  __IO uint16_t HOFFCNT;
+  __IO uint16_t VST;
+  __IO uint16_t CAPCNT;
+  __IO uint16_t VLINE;
+  __IO uint32_t DR;
+} DVP_TypeDef;
+
+/* USBHS Registers */
+typedef struct
+{
+  __IO uint8_t  CONTROL;
+  __IO uint8_t  HOST_CTRL;
+  __IO uint8_t  INT_EN;
+  __IO uint8_t  DEV_AD;
+  __IO uint16_t FRAME_NO;
+  __IO uint8_t  SUSPEND;
+  __IO uint8_t  RESERVED0;
+  __IO uint8_t  SPEED_TYPE;
+  __IO uint8_t  MIS_ST;
+  __IO uint8_t  INT_FG;
+  __IO uint8_t  INT_ST;
+  __IO uint16_t RX_LEN;
+  __IO uint16_t RESERVED1;
+  __IO uint32_t ENDP_CONFIG;
+  __IO uint32_t ENDP_TYPE;
+  __IO uint32_t BUF_MODE;
+  __IO uint32_t UEP0_DMA;               
+  __IO uint32_t UEP1_RX_DMA;       
+  __IO uint32_t UEP2_RX_DMA;       
+  __IO uint32_t UEP3_RX_DMA;       
+  __IO uint32_t UEP4_RX_DMA;       
+  __IO uint32_t UEP5_RX_DMA;       
+  __IO uint32_t UEP6_RX_DMA;       
+  __IO uint32_t UEP7_RX_DMA;       
+  __IO uint32_t UEP8_RX_DMA;      
+  __IO uint32_t UEP9_RX_DMA;       
+  __IO uint32_t UEP10_RX_DMA;      
+  __IO uint32_t UEP11_RX_DMA;      
+  __IO uint32_t UEP12_RX_DMA;      
+  __IO uint32_t UEP13_RX_DMA;      
+  __IO uint32_t UEP14_RX_DMA;      
+  __IO uint32_t UEP15_RX_DMA;      
+  __IO uint32_t UEP1_TX_DMA;       
+  __IO uint32_t UEP2_TX_DMA;       
+  __IO uint32_t UEP3_TX_DMA;       
+  __IO uint32_t UEP4_TX_DMA;       
+  __IO uint32_t UEP5_TX_DMA;      
+  __IO uint32_t UEP6_TX_DMA;      
+  __IO uint32_t UEP7_TX_DMA;       
+  __IO uint32_t UEP8_TX_DMA;      
+  __IO uint32_t UEP9_TX_DMA;       
+  __IO uint32_t UEP10_TX_DMA;      
+  __IO uint32_t UEP11_TX_DMA;      
+  __IO uint32_t UEP12_TX_DMA;    
+  __IO uint32_t UEP13_TX_DMA;      
+  __IO uint32_t UEP14_TX_DMA;     
+  __IO uint32_t UEP15_TX_DMA;      
+  __IO uint16_t UEP0_MAX_LEN;
+  __IO uint16_t RESERVED2;
+  __IO uint16_t UEP1_MAX_LEN;
+  __IO uint16_t RESERVED3;
+  __IO uint16_t UEP2_MAX_LEN;
+  __IO uint16_t RESERVED4;
+  __IO uint16_t UEP3_MAX_LEN;
+  __IO uint16_t RESERVED5;
+  __IO uint16_t UEP4_MAX_LEN;
+  __IO uint16_t RESERVED6;
+  __IO uint16_t UEP5_MAX_LEN;
+  __IO uint16_t RESERVED7;
+  __IO uint16_t UEP6_MAX_LEN;
+  __IO uint16_t RESERVED8;
+  __IO uint16_t UEP7_MAX_LEN;
+  __IO uint16_t RESERVED9;
+  __IO uint16_t UEP8_MAX_LEN;
+  __IO uint16_t RESERVED10;
+  __IO uint16_t UEP9_MAX_LEN;
+  __IO uint16_t RESERVED11;
+  __IO uint16_t UEP10_MAX_LEN;
+  __IO uint16_t RESERVED12;
+  __IO uint16_t UEP11_MAX_LEN;
+  __IO uint16_t RESERVED13;
+  __IO uint16_t UEP12_MAX_LEN;
+  __IO uint16_t RESERVED14;
+  __IO uint16_t UEP13_MAX_LEN;
+  __IO uint16_t RESERVED15;
+  __IO uint16_t UEP14_MAX_LEN;
+  __IO uint16_t RESERVED16;
+  __IO uint16_t UEP15_MAX_LEN;
+  __IO uint16_t RESERVED17;
+  __IO uint16_t UEP0_TX_LEN;
+  __IO uint8_t  UEP0_TX_CTRL;
+  __IO uint8_t  UEP0_RX_CTRL;
+  __IO uint16_t UEP1_TX_LEN;
+  __IO uint8_t  UEP1_TX_CTRL;
+  __IO uint8_t  UEP1_RX_CTRL;
+  __IO uint16_t UEP2_TX_LEN;
+  __IO uint8_t  UEP2_TX_CTRL;
+  __IO uint8_t  UEP2_RX_CTRL;
+  __IO uint16_t UEP3_TX_LEN;
+  __IO uint8_t  UEP3_TX_CTRL;
+  __IO uint8_t  UEP3_RX_CTRL;
+  __IO uint16_t UEP4_TX_LEN;
+  __IO uint8_t  UEP4_TX_CTRL;
+  __IO uint8_t  UEP4_RX_CTRL;
+  __IO uint16_t UEP5_TX_LEN;
+  __IO uint8_t  UEP5_TX_CTRL;
+  __IO uint8_t  UEP5_RX_CTRL;
+  __IO uint16_t UEP6_TX_LEN;
+  __IO uint8_t  UEP6_TX_CTRL;
+  __IO uint8_t  UEP6_RX_CTRL;
+  __IO uint16_t UEP7_TX_LEN;
+  __IO uint8_t  UEP7_TX_CTRL;
+  __IO uint8_t  UEP7_RX_CTRL;
+  __IO uint16_t UEP8_TX_LEN;
+  __IO uint8_t  UEP8_TX_CTRL;
+  __IO uint8_t  UEP8_RX_CTRL;
+  __IO uint16_t UEP9_TX_LEN;
+  __IO uint8_t  UEP9_TX_CTRL;
+  __IO uint8_t  UEP9_RX_CTRL;
+  __IO uint16_t UEP10_TX_LEN;
+  __IO uint8_t  UEP10_TX_CTRL;
+  __IO uint8_t  UEP10_RX_CTRL;
+  __IO uint16_t UEP11_TX_LEN;
+  __IO uint8_t  UEP11_TX_CTRL;
+  __IO uint8_t  UEP11_RX_CTRL;
+  __IO uint16_t UEP12_TX_LEN;
+  __IO uint8_t  UEP12_TX_CTRL;
+  __IO uint8_t  UEP12_RX_CTRL;
+  __IO uint16_t UEP13_TX_LEN;
+  __IO uint8_t  UEP13_TX_CTRL;
+  __IO uint8_t  UEP13_RX_CTRL;
+  __IO uint16_t UEP14_TX_LEN;
+  __IO uint8_t  UEP14_TX_CTRL;
+  __IO uint8_t  UEP14_RX_CTRL;
+  __IO uint16_t UEP15_TX_LEN;
+  __IO uint8_t  UEP15_TX_CTRL;
+  __IO uint8_t  UEP15_RX_CTRL;
+} USBHSD_TypeDef;
+
+typedef struct  __attribute__((packed))
+{
+    __IO uint8_t  CONTROL;
+    __IO uint8_t  HOST_CTRL;
+    __IO uint8_t  INT_EN;
+    __IO uint8_t  DEV_AD;
+    __IO uint16_t FRAME_NO;
+    __IO uint8_t  SUSPEND;
+    __IO uint8_t  RESERVED0;
+    __IO uint8_t  SPEED_TYPE;
+    __IO uint8_t  MIS_ST;
+    __IO uint8_t  INT_FG;
+    __IO uint8_t  INT_ST;
+    __IO uint16_t RX_LEN;
+    __IO uint16_t RESERVED1;
+    __IO uint32_t HOST_EP_CONFIG;
+    __IO uint32_t HOST_EP_TYPE;
+    __IO uint32_t RESERVED2;
+    __IO uint32_t RESERVED3;
+    __IO uint32_t RESERVED4;
+    __IO uint32_t HOST_RX_DMA;
+    __IO uint32_t RESERVED5;
+    __IO uint32_t RESERVED6;
+    __IO uint32_t RESERVED7;
+    __IO uint32_t RESERVED8;
+    __IO uint32_t RESERVED9;
+    __IO uint32_t RESERVED10;
+    __IO uint32_t RESERVED11;
+    __IO uint32_t RESERVED12;
+    __IO uint32_t RESERVED13;
+    __IO uint32_t RESERVED14;
+    __IO uint32_t RESERVED15;
+    __IO uint32_t RESERVED16;
+    __IO uint32_t RESERVED17;
+    __IO uint32_t RESERVED18;
+    __IO uint32_t RESERVED19;
+    __IO uint32_t HOST_TX_DMA;
+    __IO uint32_t RESERVED20;
+    __IO uint32_t RESERVED21;
+    __IO uint32_t RESERVED22;
+    __IO uint32_t RESERVED23;
+    __IO uint32_t RESERVED24;
+    __IO uint32_t RESERVED25;
+    __IO uint32_t RESERVED26;
+    __IO uint32_t RESERVED27;
+    __IO uint32_t RESERVED28;
+    __IO uint32_t RESERVED29;
+    __IO uint32_t RESERVED30;
+    __IO uint32_t RESERVED31;
+    __IO uint32_t RESERVED32;
+    __IO uint32_t RESERVED33;
+    __IO uint16_t HOST_RX_MAX_LEN;
+    __IO uint16_t RESERVED34;
+    __IO uint32_t RESERVED35;
+    __IO uint32_t RESERVED36;
+    __IO uint32_t RESERVED37;
+    __IO uint32_t RESERVED38;
+    __IO uint32_t RESERVED39;
+    __IO uint32_t RESERVED40;
+    __IO uint32_t RESERVED41;
+    __IO uint32_t RESERVED42;
+    __IO uint32_t RESERVED43;
+    __IO uint32_t RESERVED44;
+    __IO uint32_t RESERVED45;
+    __IO uint32_t RESERVED46;
+    __IO uint32_t RESERVED47;
+    __IO uint32_t RESERVED48;
+    __IO uint32_t RESERVED49;
+    __IO uint8_t  HOST_EP_PID;
+    __IO uint8_t  RESERVED50;
+    __IO uint8_t  RESERVED51;
+    __IO uint8_t  HOST_RX_CTRL;
+    __IO uint16_t HOST_TX_LEN;
+    __IO uint8_t  HOST_TX_CTRL;
+    __IO uint8_t  RESERVED52;
+    __IO uint16_t HOST_SPLIT_DATA;
+} USBHSH_TypeDef;
+
+
+/* USBOTG_FS Registers */
+typedef struct
+{
+   __IO uint8_t  BASE_CTRL;
+   __IO uint8_t  UDEV_CTRL;
+   __IO uint8_t  INT_EN;
+   __IO uint8_t  DEV_ADDR;
+   __IO uint8_t  Reserve0;
+   __IO uint8_t  MIS_ST;
+   __IO uint8_t  INT_FG;
+   __IO uint8_t  INT_ST;
+   __IO uint16_t RX_LEN;
+   __IO uint16_t Reserve1;
+   __IO uint8_t  UEP4_1_MOD;
+   __IO uint8_t  UEP2_3_MOD;
+   __IO uint8_t  UEP5_6_MOD;
+   __IO uint8_t  UEP7_MOD;
+   __IO uint32_t UEP0_DMA;
+   __IO uint32_t UEP1_DMA;
+   __IO uint32_t UEP2_DMA;
+   __IO uint32_t UEP3_DMA;
+   __IO uint32_t UEP4_DMA;
+   __IO uint32_t UEP5_DMA;
+   __IO uint32_t UEP6_DMA;
+   __IO uint32_t UEP7_DMA;
+   __IO uint16_t UEP0_TX_LEN;
+   __IO uint8_t  UEP0_TX_CTRL;
+   __IO uint8_t  UEP0_RX_CTRL;
+   __IO uint16_t UEP1_TX_LEN;
+   __IO uint8_t  UEP1_TX_CTRL;
+   __IO uint8_t  UEP1_RX_CTRL;
+   __IO uint16_t UEP2_TX_LEN;
+   __IO uint8_t  UEP2_TX_CTRL;
+   __IO uint8_t  UEP2_RX_CTRL;
+   __IO uint16_t UEP3_TX_LEN;
+   __IO uint8_t  UEP3_TX_CTRL;
+   __IO uint8_t  UEP3_RX_CTRL;
+   __IO uint16_t UEP4_TX_LEN;
+   __IO uint8_t  UEP4_TX_CTRL;
+   __IO uint8_t  UEP4_RX_CTRL;
+   __IO uint16_t UEP5_TX_LEN;
+   __IO uint8_t  UEP5_TX_CTRL;
+   __IO uint8_t  UEP5_RX_CTRL;
+   __IO uint16_t UEP6_TX_LEN;
+   __IO uint8_t  UEP6_TX_CTRL;
+   __IO uint8_t  UEP6_RX_CTRL;
+   __IO uint16_t UEP7_TX_LEN;
+   __IO uint8_t  UEP7_TX_CTRL;
+   __IO uint8_t  UEP7_RX_CTRL;
+   __IO uint32_t Reserve2;
+   __IO uint32_t OTG_CR;
+   __IO uint32_t OTG_SR;
+}USBOTG_FS_TypeDef;
+
+typedef struct  __attribute__((packed))
+{
+   __IO uint8_t   BASE_CTRL;
+   __IO uint8_t   HOST_CTRL;
+   __IO uint8_t   INT_EN;
+   __IO uint8_t   DEV_ADDR;
+   __IO uint8_t   Reserve0;
+   __IO uint8_t   MIS_ST;
+   __IO uint8_t   INT_FG;
+   __IO uint8_t   INT_ST;
+   __IO uint16_t  RX_LEN;
+   __IO uint16_t  Reserve1;
+   __IO uint8_t   Reserve2;
+   __IO uint8_t   HOST_EP_MOD;
+   __IO uint16_t  Reserve3;
+   __IO uint32_t  Reserve4;
+   __IO uint32_t  Reserve5;
+   __IO uint32_t  HOST_RX_DMA;
+   __IO uint32_t  HOST_TX_DMA;
+   __IO uint32_t  Reserve6;
+   __IO uint32_t  Reserve7;
+   __IO uint32_t  Reserve8;
+   __IO uint32_t  Reserve9;
+   __IO uint32_t  Reserve10;
+   __IO uint16_t  Reserve11;
+   __IO uint16_t  HOST_SETUP;
+   __IO uint8_t   HOST_EP_PID;
+   __IO uint8_t   Reserve12;
+   __IO uint8_t   Reserve13;
+   __IO uint8_t   HOST_RX_CTRL;
+   __IO uint16_t  HOST_TX_LEN;
+   __IO uint8_t   HOST_TX_CTRL;
+   __IO uint8_t   Reserve14;
+   __IO uint32_t  Reserve15;
+   __IO uint32_t  Reserve16;
+   __IO uint32_t  Reserve17;
+   __IO uint32_t  Reserve18;
+   __IO uint32_t  Reserve19;
+   __IO uint32_t  OTG_CR;
+   __IO uint32_t  OTG_SR;
+}USBOTGH_FS_TypeDef;
+
+/* Ethernet MAC */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;
+       uint32_t RESERVED0[2];
+  __IO uint32_t MACRWUFFR;
+  __IO uint32_t MACPMTCSR;
+       uint32_t RESERVED1[2];
+  __IO uint32_t MACSR;
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+       uint32_t RESERVED2[40];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+       uint32_t RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;
+  __IO uint32_t MMCTGFMSCCR;
+       uint32_t RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+       uint32_t RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+       uint32_t RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+       uint32_t RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+       uint32_t RESERVED8[567];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+       uint32_t RESERVED9[9];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+
+
+/* Peripheral memory map */
+#define FLASH_BASE            ((uint32_t)0x08000000) /* FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /* SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /* FSMC registers base address */
+
+
+#define APB1PERIPH_BASE       (PERIPH_BASE)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define UART6_BASE            (APB1PERIPH_BASE + 0x1800)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x8000)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
+#define DMA2_Channel6_BASE    (AHBPERIPH_BASE + 0x046C)
+#define DMA2_Channel7_BASE    (AHBPERIPH_BASE + 0x0480)
+#define DMA2_Channel8_BASE    (AHBPERIPH_BASE + 0x0490)
+#define DMA2_Channel9_BASE    (AHBPERIPH_BASE + 0x04A0)
+#define DMA2_Channel10_BASE   (AHBPERIPH_BASE + 0x04B0)
+#define DMA2_Channel11_BASE   (AHBPERIPH_BASE + 0x04C0)
+#define DMA2_EXTEN_BASE       (AHBPERIPH_BASE + 0x04D0)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+#define USBHS_BASE            (AHBPERIPH_BASE + 0x3400)
+#define EXTEN_BASE            (AHBPERIPH_BASE + 0x3800)
+#define OPA_BASE              (AHBPERIPH_BASE + 0x3804)
+#define RNG_BASE              (AHBPERIPH_BASE + 0x3C00)
+
+#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+#define USBFS_BASE            ((uint32_t)0x50000000)
+#define DVP_BASE              ((uint32_t)0x50050000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) 
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) 
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) 
+
+#define OB_BASE               ((uint32_t)0x1FFFF800)
+
+/* Peripheral declaration */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define UART6               ((USART_TypeDef *) UART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define BKP                 ((BKP_TypeDef *) BKP_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+
+#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define TKey1               ((ADC_TypeDef *) ADC1_BASE)
+#define TKey2               ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_EXTEN          ((DMA_TypeDef *) DMA2_EXTEN_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_Channel8       ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
+#define DMA2_Channel9       ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE)
+#define DMA2_Channel10      ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE)
+#define DMA2_Channel11      ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define USBHSD              ((USBHSD_TypeDef *) USBHS_BASE)
+#define USBHSH              ((USBHSH_TypeDef *) USBHS_BASE)
+#define USBOTG_FS           ((USBOTG_FS_TypeDef *)USBFS_BASE)
+#define USBOTG_H_FS         ((USBOTGH_FS_TypeDef *)USBFS_BASE)
+#define EXTEN               ((EXTEN_TypeDef *) EXTEN_BASE)
+#define OPA                 ((OPA_TypeDef *) OPA_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)
+
+#define DVP                 ((DVP_TypeDef *) DVP_BASE)
+
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+
+#define OB                  ((OB_TypeDef *) OB_BASE)
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                        Analog to Digital Converter                         */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STATR register  ********************/
+#define  ADC_AWD                        ((uint8_t)0x01)               /* Analog watchdog flag */
+#define  ADC_EOC                        ((uint8_t)0x02)               /* End of conversion */
+#define  ADC_JEOC                       ((uint8_t)0x04)               /* Injected channel end of conversion */
+#define  ADC_JSTRT                      ((uint8_t)0x08)               /* Injected channel Start flag */
+#define  ADC_STRT                       ((uint8_t)0x10)               /* Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CTLR1 register  ********************/
+#define  ADC_AWDCH                      ((uint32_t)0x0000001F)        /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_AWDCH_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_AWDCH_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_AWDCH_2                    ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_AWDCH_3                    ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_AWDCH_4                    ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_EOCIE                      ((uint32_t)0x00000020)        /* Interrupt enable for EOC */
+#define  ADC_AWDIE                      ((uint32_t)0x00000040)        /* Analog Watchdog interrupt enable */
+#define  ADC_JEOCIE                     ((uint32_t)0x00000080)        /* Interrupt enable for injected channels */
+#define  ADC_SCAN                       ((uint32_t)0x00000100)        /* Scan mode */
+#define  ADC_AWDSGL                     ((uint32_t)0x00000200)        /* Enable the watchdog on a single channel in scan mode */
+#define  ADC_JAUTO                      ((uint32_t)0x00000400)        /* Automatic injected group conversion */
+#define  ADC_DISCEN                     ((uint32_t)0x00000800)        /* Discontinuous mode on regular channels */
+#define  ADC_JDISCEN                    ((uint32_t)0x00001000)        /* Discontinuous mode on injected channels */
+
+#define  ADC_DISCNUM                    ((uint32_t)0x0000E000)        /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_DISCNUM_0                  ((uint32_t)0x00002000)        /* Bit 0 */
+#define  ADC_DISCNUM_1                  ((uint32_t)0x00004000)        /* Bit 1 */
+#define  ADC_DISCNUM_2                  ((uint32_t)0x00008000)        /* Bit 2 */
+
+#define  ADC_DUALMOD                    ((uint32_t)0x000F0000)        /* DUALMOD[3:0] bits (Dual mode selection) */
+#define  ADC_DUALMOD_0                  ((uint32_t)0x00010000)        /* Bit 0 */
+#define  ADC_DUALMOD_1                  ((uint32_t)0x00020000)        /* Bit 1 */
+#define  ADC_DUALMOD_2                  ((uint32_t)0x00040000)        /* Bit 2 */
+#define  ADC_DUALMOD_3                  ((uint32_t)0x00080000)        /* Bit 3 */
+
+#define  ADC_JAWDEN                     ((uint32_t)0x00400000)        /* Analog watchdog enable on injected channels */
+#define  ADC_AWDEN                      ((uint32_t)0x00800000)        /* Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CTLR2 register  ********************/
+#define  ADC_ADON                       ((uint32_t)0x00000001)        /* A/D Converter ON / OFF */
+#define  ADC_CONT                       ((uint32_t)0x00000002)        /* Continuous Conversion */
+#define  ADC_CAL                        ((uint32_t)0x00000004)        /* A/D Calibration */
+#define  ADC_RSTCAL                     ((uint32_t)0x00000008)        /* Reset Calibration */
+#define  ADC_DMA                        ((uint32_t)0x00000100)        /* Direct Memory access mode */
+#define  ADC_ALIGN                      ((uint32_t)0x00000800)        /* Data Alignment */
+
+#define  ADC_JEXTSEL                    ((uint32_t)0x00007000)        /* JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_JEXTSEL_0                  ((uint32_t)0x00001000)        /* Bit 0 */
+#define  ADC_JEXTSEL_1                  ((uint32_t)0x00002000)        /* Bit 1 */
+#define  ADC_JEXTSEL_2                  ((uint32_t)0x00004000)        /* Bit 2 */
+
+#define  ADC_JEXTTRIG                   ((uint32_t)0x00008000)        /* External Trigger Conversion mode for injected channels */
+
+#define  ADC_EXTSEL                     ((uint32_t)0x000E0000)        /* EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_EXTSEL_0                   ((uint32_t)0x00020000)        /* Bit 0 */
+#define  ADC_EXTSEL_1                   ((uint32_t)0x00040000)        /* Bit 1 */
+#define  ADC_EXTSEL_2                   ((uint32_t)0x00080000)        /* Bit 2 */
+
+#define  ADC_EXTTRIG                    ((uint32_t)0x00100000)        /* External Trigger Conversion mode for regular channels */
+#define  ADC_JSWSTART                   ((uint32_t)0x00200000)        /* Start Conversion of injected channels */
+#define  ADC_SWSTART                    ((uint32_t)0x00400000)        /* Start Conversion of regular channels */
+#define  ADC_TSVREFE                    ((uint32_t)0x00800000)        /* Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SAMPTR1 register  *******************/
+#define  ADC_SMP10                      ((uint32_t)0x00000007)        /* SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMP10_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SMP10_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SMP10_2                    ((uint32_t)0x00000004)        /* Bit 2 */
+
+#define  ADC_SMP11                      ((uint32_t)0x00000038)        /* SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMP11_0                    ((uint32_t)0x00000008)        /* Bit 0 */
+#define  ADC_SMP11_1                    ((uint32_t)0x00000010)        /* Bit 1 */
+#define  ADC_SMP11_2                    ((uint32_t)0x00000020)        /* Bit 2 */
+
+#define  ADC_SMP12                      ((uint32_t)0x000001C0)        /* SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMP12_0                    ((uint32_t)0x00000040)        /* Bit 0 */
+#define  ADC_SMP12_1                    ((uint32_t)0x00000080)        /* Bit 1 */
+#define  ADC_SMP12_2                    ((uint32_t)0x00000100)        /* Bit 2 */
+
+#define  ADC_SMP13                      ((uint32_t)0x00000E00)        /* SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMP13_0                    ((uint32_t)0x00000200)        /* Bit 0 */
+#define  ADC_SMP13_1                    ((uint32_t)0x00000400)        /* Bit 1 */
+#define  ADC_SMP13_2                    ((uint32_t)0x00000800)        /* Bit 2 */
+
+#define  ADC_SMP14                      ((uint32_t)0x00007000)        /* SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMP14_0                    ((uint32_t)0x00001000)        /* Bit 0 */
+#define  ADC_SMP14_1                    ((uint32_t)0x00002000)        /* Bit 1 */
+#define  ADC_SMP14_2                    ((uint32_t)0x00004000)        /* Bit 2 */
+
+#define  ADC_SMP15                      ((uint32_t)0x00038000)        /* SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMP15_0                    ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SMP15_1                    ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SMP15_2                    ((uint32_t)0x00020000)        /* Bit 2 */
+
+#define  ADC_SMP16                      ((uint32_t)0x001C0000)        /* SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMP16_0                    ((uint32_t)0x00040000)        /* Bit 0 */
+#define  ADC_SMP16_1                    ((uint32_t)0x00080000)        /* Bit 1 */
+#define  ADC_SMP16_2                    ((uint32_t)0x00100000)        /* Bit 2 */
+
+#define  ADC_SMP17                      ((uint32_t)0x00E00000)        /* SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMP17_0                    ((uint32_t)0x00200000)        /* Bit 0 */
+#define  ADC_SMP17_1                    ((uint32_t)0x00400000)        /* Bit 1 */
+#define  ADC_SMP17_2                    ((uint32_t)0x00800000)        /* Bit 2 */
+
+/******************  Bit definition for ADC_SAMPTR2 register  *******************/
+#define  ADC_SMP0                       ((uint32_t)0x00000007)        /* SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMP0_0                     ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SMP0_1                     ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SMP0_2                     ((uint32_t)0x00000004)        /* Bit 2 */
+
+#define  ADC_SMP1                       ((uint32_t)0x00000038)        /* SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMP1_0                     ((uint32_t)0x00000008)        /* Bit 0 */
+#define  ADC_SMP1_1                     ((uint32_t)0x00000010)        /* Bit 1 */
+#define  ADC_SMP1_2                     ((uint32_t)0x00000020)        /* Bit 2 */
+
+#define  ADC_SMP2                       ((uint32_t)0x000001C0)        /* SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMP2_0                     ((uint32_t)0x00000040)        /* Bit 0 */
+#define  ADC_SMP2_1                     ((uint32_t)0x00000080)        /* Bit 1 */
+#define  ADC_SMP2_2                     ((uint32_t)0x00000100)        /* Bit 2 */
+
+#define  ADC_SMP3                       ((uint32_t)0x00000E00)        /* SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMP3_0                     ((uint32_t)0x00000200)        /* Bit 0 */
+#define  ADC_SMP3_1                     ((uint32_t)0x00000400)        /* Bit 1 */
+#define  ADC_SMP3_2                     ((uint32_t)0x00000800)        /* Bit 2 */
+
+#define  ADC_SMP4                       ((uint32_t)0x00007000)        /* SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMP4_0                     ((uint32_t)0x00001000)        /* Bit 0 */
+#define  ADC_SMP4_1                     ((uint32_t)0x00002000)        /* Bit 1 */
+#define  ADC_SMP4_2                     ((uint32_t)0x00004000)        /* Bit 2 */
+
+#define  ADC_SMP5                       ((uint32_t)0x00038000)        /* SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMP5_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SMP5_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SMP5_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+
+#define  ADC_SMP6                       ((uint32_t)0x001C0000)        /* SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMP6_0                     ((uint32_t)0x00040000)        /* Bit 0 */
+#define  ADC_SMP6_1                     ((uint32_t)0x00080000)        /* Bit 1 */
+#define  ADC_SMP6_2                     ((uint32_t)0x00100000)        /* Bit 2 */
+
+#define  ADC_SMP7                       ((uint32_t)0x00E00000)        /* SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMP7_0                     ((uint32_t)0x00200000)        /* Bit 0 */
+#define  ADC_SMP7_1                     ((uint32_t)0x00400000)        /* Bit 1 */
+#define  ADC_SMP7_2                     ((uint32_t)0x00800000)        /* Bit 2 */
+
+#define  ADC_SMP8                       ((uint32_t)0x07000000)        /* SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMP8_0                     ((uint32_t)0x01000000)        /* Bit 0 */
+#define  ADC_SMP8_1                     ((uint32_t)0x02000000)        /* Bit 1 */
+#define  ADC_SMP8_2                     ((uint32_t)0x04000000)        /* Bit 2 */
+
+#define  ADC_SMP9                       ((uint32_t)0x38000000)        /* SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMP9_0                     ((uint32_t)0x08000000)        /* Bit 0 */
+#define  ADC_SMP9_1                     ((uint32_t)0x10000000)        /* Bit 1 */
+#define  ADC_SMP9_2                     ((uint32_t)0x20000000)        /* Bit 2 */
+
+/******************  Bit definition for ADC_IOFR1 register  *******************/
+#define  ADC_JOFFSET1                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_IOFR2 register  *******************/
+#define  ADC_JOFFSET2                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_IOFR3 register  *******************/
+#define  ADC_JOFFSET3                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_IOFR4 register  *******************/
+#define  ADC_JOFFSET4                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WDHTR register  ********************/
+#define  ADC_HT                         ((uint16_t)0x0FFF)            /* Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WDLTR register  ********************/
+#define  ADC_LT                         ((uint16_t)0x0FFF)            /* Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSQR1 register  *******************/
+#define  ADC_SQ13                       ((uint32_t)0x0000001F)        /* SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQ13_0                     ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SQ13_1                     ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SQ13_2                     ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_SQ13_3                     ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_SQ13_4                     ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_SQ14                       ((uint32_t)0x000003E0)        /* SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQ14_0                     ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_SQ14_1                     ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_SQ14_2                     ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_SQ14_3                     ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_SQ14_4                     ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_SQ15                       ((uint32_t)0x00007C00)        /* SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQ15_0                     ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_SQ15_1                     ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_SQ15_2                     ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_SQ15_3                     ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_SQ15_4                     ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_SQ16                       ((uint32_t)0x000F8000)        /* SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQ16_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SQ16_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SQ16_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_SQ16_3                     ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_SQ16_4                     ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_L                          ((uint32_t)0x00F00000)        /* L[3:0] bits (Regular channel sequence length) */
+#define  ADC_L_0                        ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_L_1                        ((uint32_t)0x00200000)        /* Bit 1 */
+#define  ADC_L_2                        ((uint32_t)0x00400000)        /* Bit 2 */
+#define  ADC_L_3                        ((uint32_t)0x00800000)        /* Bit 3 */
+
+/*******************  Bit definition for ADC_RSQR2 register  *******************/
+#define  ADC_SQ7                        ((uint32_t)0x0000001F)        /* SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQ7_0                      ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SQ7_1                      ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SQ7_2                      ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_SQ7_3                      ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_SQ7_4                      ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_SQ8                        ((uint32_t)0x000003E0)        /* SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQ8_0                      ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_SQ8_1                      ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_SQ8_2                      ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_SQ8_3                      ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_SQ8_4                      ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_SQ9                        ((uint32_t)0x00007C00)        /* SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQ9_0                      ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_SQ9_1                      ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_SQ9_2                      ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_SQ9_3                      ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_SQ9_4                      ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_SQ10                       ((uint32_t)0x000F8000)        /* SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQ10_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SQ10_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SQ10_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_SQ10_3                     ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_SQ10_4                     ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_SQ11                       ((uint32_t)0x01F00000)        /* SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQ11_0                     ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_SQ11_1                     ((uint32_t)0x00200000)        /* Bit 1 */
+#define  ADC_SQ11_2                     ((uint32_t)0x00400000)        /* Bit 2 */
+#define  ADC_SQ11_3                     ((uint32_t)0x00800000)        /* Bit 3 */
+#define  ADC_SQ11_4                     ((uint32_t)0x01000000)        /* Bit 4 */
+
+#define  ADC_SQ12                       ((uint32_t)0x3E000000)        /* SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQ12_0                     ((uint32_t)0x02000000)        /* Bit 0 */
+#define  ADC_SQ12_1                     ((uint32_t)0x04000000)        /* Bit 1 */
+#define  ADC_SQ12_2                     ((uint32_t)0x08000000)        /* Bit 2 */
+#define  ADC_SQ12_3                     ((uint32_t)0x10000000)        /* Bit 3 */
+#define  ADC_SQ12_4                     ((uint32_t)0x20000000)        /* Bit 4 */
+
+/*******************  Bit definition for ADC_RSQR3 register  *******************/
+#define  ADC_SQ1                        ((uint32_t)0x0000001F)        /* SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQ1_0                      ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SQ1_1                      ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SQ1_2                      ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_SQ1_3                      ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_SQ1_4                      ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_SQ2                        ((uint32_t)0x000003E0)        /* SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQ2_0                      ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_SQ2_1                      ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_SQ2_2                      ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_SQ2_3                      ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_SQ2_4                      ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_SQ3                        ((uint32_t)0x00007C00)        /* SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQ3_0                      ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_SQ3_1                      ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_SQ3_2                      ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_SQ3_3                      ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_SQ3_4                      ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_SQ4                        ((uint32_t)0x000F8000)        /* SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQ4_0                      ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SQ4_1                      ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SQ4_2                      ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_SQ4_3                      ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_SQ4_4                      ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_SQ5                        ((uint32_t)0x01F00000)        /* SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQ5_0                      ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_SQ5_1                      ((uint32_t)0x00200000)        /* Bit 1 */
+#define  ADC_SQ5_2                      ((uint32_t)0x00400000)        /* Bit 2 */
+#define  ADC_SQ5_3                      ((uint32_t)0x00800000)        /* Bit 3 */
+#define  ADC_SQ5_4                      ((uint32_t)0x01000000)        /* Bit 4 */
+
+#define  ADC_SQ6                        ((uint32_t)0x3E000000)        /* SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQ6_0                      ((uint32_t)0x02000000)        /* Bit 0 */
+#define  ADC_SQ6_1                      ((uint32_t)0x04000000)        /* Bit 1 */
+#define  ADC_SQ6_2                      ((uint32_t)0x08000000)        /* Bit 2 */
+#define  ADC_SQ6_3                      ((uint32_t)0x10000000)        /* Bit 3 */
+#define  ADC_SQ6_4                      ((uint32_t)0x20000000)        /* Bit 4 */
+
+/*******************  Bit definition for ADC_ISQR register  *******************/
+#define  ADC_JSQ1                       ((uint32_t)0x0000001F)        /* JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQ1_0                     ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_JSQ1_1                     ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_JSQ1_2                     ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_JSQ1_3                     ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_JSQ1_4                     ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_JSQ2                       ((uint32_t)0x000003E0)        /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQ2_0                     ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_JSQ2_1                     ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_JSQ2_2                     ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_JSQ2_3                     ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_JSQ2_4                     ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_JSQ3                       ((uint32_t)0x00007C00)        /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQ3_0                     ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_JSQ3_1                     ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_JSQ3_2                     ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_JSQ3_3                     ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_JSQ3_4                     ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_JSQ4                       ((uint32_t)0x000F8000)        /* JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQ4_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_JSQ4_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_JSQ4_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_JSQ4_3                     ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_JSQ4_4                     ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_JL                         ((uint32_t)0x00300000)        /* JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JL_0                       ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_JL_1                       ((uint32_t)0x00200000)        /* Bit 1 */
+
+/*******************  Bit definition for ADC_IDATAR1 register  *******************/
+#define  ADC_IDATAR1_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR2 register  *******************/
+#define  ADC_IDATAR2_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR3 register  *******************/
+#define  ADC_IDATAR3_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR4 register  *******************/
+#define  ADC_IDATAR4_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/********************  Bit definition for ADC_RDATAR register  ********************/
+#define  ADC_RDATAR_DATA                ((uint32_t)0x0000FFFF)        /* Regular data */
+#define  ADC_RDATAR_ADC2DATA            ((uint32_t)0xFFFF0000)        /* ADC2 data */
+
+/******************************************************************************/
+/*                            Backup registers                                */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DATAR1 register  ********************/
+#define  BKP_DATAR1_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR2 register  ********************/
+#define  BKP_DATAR2_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR3 register  ********************/
+#define  BKP_DATAR3_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR4 register  ********************/
+#define  BKP_DATAR4_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR5 register  ********************/
+#define  BKP_DATAR5_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR6 register  ********************/
+#define  BKP_DATAR6_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR7 register  ********************/
+#define  BKP_DATAR7_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR8 register  ********************/
+#define  BKP_DATAR8_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR9 register  ********************/
+#define  BKP_DATAR9_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR10 register  *******************/
+#define  BKP_DATAR10_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR11 register  *******************/
+#define  BKP_DATAR11_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR12 register  *******************/
+#define  BKP_DATAR12_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR13 register  *******************/
+#define  BKP_DATAR13_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR14 register  *******************/
+#define  BKP_DATAR14_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR15 register  *******************/
+#define  BKP_DATAR15_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR16 register  *******************/
+#define  BKP_DATAR16_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR17 register  *******************/
+#define  BKP_DATAR17_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/******************  Bit definition for BKP_DATAR18 register  ********************/
+#define  BKP_DATAR18_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR19 register  *******************/
+#define  BKP_DATAR19_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR20 register  *******************/
+#define  BKP_DATAR20_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR21 register  *******************/
+#define  BKP_DATAR21_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR22 register  *******************/
+#define  BKP_DATAR22_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR23 register  *******************/
+#define  BKP_DATAR23_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR24 register  *******************/
+#define  BKP_DATAR24_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR25 register  *******************/
+#define  BKP_DATAR25_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR26 register  *******************/
+#define  BKP_DATAR26_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR27 register  *******************/
+#define  BKP_DATAR27_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR28 register  *******************/
+#define  BKP_DATAR28_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR29 register  *******************/
+#define  BKP_DATAR29_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR30 register  *******************/
+#define  BKP_DATAR30_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR31 register  *******************/
+#define  BKP_DATAR31_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR32 register  *******************/
+#define  BKP_DATAR32_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR33 register  *******************/
+#define  BKP_DATAR33_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR34 register  *******************/
+#define  BKP_DATAR34_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR35 register  *******************/
+#define  BKP_DATAR35_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR36 register  *******************/
+#define  BKP_DATAR36_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR37 register  *******************/
+#define  BKP_DATAR37_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR38 register  *******************/
+#define  BKP_DATAR38_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR39 register  *******************/
+#define  BKP_DATAR39_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR40 register  *******************/
+#define  BKP_DATAR40_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR41 register  *******************/
+#define  BKP_DATAR41_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR42 register  *******************/
+#define  BKP_DATAR42_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/******************  Bit definition for BKP_OCTLR register  *******************/
+#define  BKP_CAL                                ((uint16_t)0x007F)     /* Calibration value */
+#define  BKP_CCO                                ((uint16_t)0x0080)     /* Calibration Clock Output */
+#define  BKP_ASOE                               ((uint16_t)0x0100)     /* Alarm or Second Output Enable */
+#define  BKP_ASOS                               ((uint16_t)0x0200)     /* Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_TPCTLR register  ********************/
+#define  BKP_TPE                                ((uint8_t)0x01)        /* TAMPER pin enable */
+#define  BKP_TPAL                               ((uint8_t)0x02)        /* TAMPER pin active level */
+
+/*******************  Bit definition for BKP_TPCSR register  ********************/
+#define  BKP_CTE                                ((uint16_t)0x0001)     /* Clear Tamper event */
+#define  BKP_CTI                                ((uint16_t)0x0002)     /* Clear Tamper Interrupt */
+#define  BKP_TPIE                               ((uint16_t)0x0004)     /* TAMPER Pin interrupt enable */
+#define  BKP_TEF                                ((uint16_t)0x0100)     /* Tamper Event Flag */
+#define  BKP_TIF                                ((uint16_t)0x0200)     /* Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                         Controller Area Network                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CAN_CTLR register  ********************/
+#define  CAN_CTLR_INRQ                       ((uint16_t)0x0001)            /* Initialization Request */
+#define  CAN_CTLR_SLEEP                      ((uint16_t)0x0002)            /* Sleep Mode Request */
+#define  CAN_CTLR_TXFP                       ((uint16_t)0x0004)            /* Transmit FIFO Priority */
+#define  CAN_CTLR_RFLM                       ((uint16_t)0x0008)            /* Receive FIFO Locked Mode */
+#define  CAN_CTLR_NART                       ((uint16_t)0x0010)            /* No Automatic Retransmission */
+#define  CAN_CTLR_AWUM                       ((uint16_t)0x0020)            /* Automatic Wakeup Mode */
+#define  CAN_CTLR_ABOM                       ((uint16_t)0x0040)            /* Automatic Bus-Off Management */
+#define  CAN_CTLR_TTCM                       ((uint16_t)0x0080)            /* Time Triggered Communication Mode */
+#define  CAN_CTLR_RESET                      ((uint16_t)0x8000)            /* CAN software master reset */
+
+/*******************  Bit definition for CAN_STATR register  ********************/
+#define  CAN_STATR_INAK                      ((uint16_t)0x0001)            /* Initialization Acknowledge */
+#define  CAN_STATR_SLAK                      ((uint16_t)0x0002)            /* Sleep Acknowledge */
+#define  CAN_STATR_ERRI                      ((uint16_t)0x0004)            /* Error Interrupt */
+#define  CAN_STATR_WKUI                      ((uint16_t)0x0008)            /* Wakeup Interrupt */
+#define  CAN_STATR_SLAKI                     ((uint16_t)0x0010)            /* Sleep Acknowledge Interrupt */
+#define  CAN_STATR_TXM                       ((uint16_t)0x0100)            /* Transmit Mode */
+#define  CAN_STATR_RXM                       ((uint16_t)0x0200)            /* Receive Mode */
+#define  CAN_STATR_SAMP                      ((uint16_t)0x0400)            /* Last Sample Point */
+#define  CAN_STATR_RX                        ((uint16_t)0x0800)            /* CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSTATR register  ********************/
+#define  CAN_TSTATR_RQCP0                    ((uint32_t)0x00000001)        /* Request Completed Mailbox0 */
+#define  CAN_TSTATR_TXOK0                    ((uint32_t)0x00000002)        /* Transmission OK of Mailbox0 */
+#define  CAN_TSTATR_ALST0                    ((uint32_t)0x00000004)        /* Arbitration Lost for Mailbox0 */
+#define  CAN_TSTATR_TERR0                    ((uint32_t)0x00000008)        /* Transmission Error of Mailbox0 */
+#define  CAN_TSTATR_ABRQ0                    ((uint32_t)0x00000080)        /* Abort Request for Mailbox0 */
+#define  CAN_TSTATR_RQCP1                    ((uint32_t)0x00000100)        /* Request Completed Mailbox1 */
+#define  CAN_TSTATR_TXOK1                    ((uint32_t)0x00000200)        /* Transmission OK of Mailbox1 */
+#define  CAN_TSTATR_ALST1                    ((uint32_t)0x00000400)        /* Arbitration Lost for Mailbox1 */
+#define  CAN_TSTATR_TERR1                    ((uint32_t)0x00000800)        /* Transmission Error of Mailbox1 */
+#define  CAN_TSTATR_ABRQ1                    ((uint32_t)0x00008000)        /* Abort Request for Mailbox 1 */
+#define  CAN_TSTATR_RQCP2                    ((uint32_t)0x00010000)        /* Request Completed Mailbox2 */
+#define  CAN_TSTATR_TXOK2                    ((uint32_t)0x00020000)        /* Transmission OK of Mailbox 2 */
+#define  CAN_TSTATR_ALST2                    ((uint32_t)0x00040000)        /* Arbitration Lost for mailbox 2 */
+#define  CAN_TSTATR_TERR2                    ((uint32_t)0x00080000)        /* Transmission Error of Mailbox 2 */
+#define  CAN_TSTATR_ABRQ2                    ((uint32_t)0x00800000)        /* Abort Request for Mailbox 2 */
+#define  CAN_TSTATR_CODE                     ((uint32_t)0x03000000)        /* Mailbox Code */
+
+#define  CAN_TSTATR_TME                      ((uint32_t)0x1C000000)        /* TME[2:0] bits */
+#define  CAN_TSTATR_TME0                     ((uint32_t)0x04000000)        /* Transmit Mailbox 0 Empty */
+#define  CAN_TSTATR_TME1                     ((uint32_t)0x08000000)        /* Transmit Mailbox 1 Empty */
+#define  CAN_TSTATR_TME2                     ((uint32_t)0x10000000)        /* Transmit Mailbox 2 Empty */
+
+#define  CAN_TSTATR_LOW                      ((uint32_t)0xE0000000)        /* LOW[2:0] bits */
+#define  CAN_TSTATR_LOW0                     ((uint32_t)0x20000000)        /* Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSTATR_LOW1                     ((uint32_t)0x40000000)        /* Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSTATR_LOW2                     ((uint32_t)0x80000000)        /* Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RFIFO0 register  *******************/
+#define  CAN_RFIFO0_FMP0                     ((uint8_t)0x03)               /* FIFO 0 Message Pending */
+#define  CAN_RFIFO0_FULL0                    ((uint8_t)0x08)               /* FIFO 0 Full */
+#define  CAN_RFIFO0_FOVR0                    ((uint8_t)0x10)               /* FIFO 0 Overrun */
+#define  CAN_RFIFO0_RFOM0                    ((uint8_t)0x20)               /* Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RFIFO1 register  *******************/
+#define  CAN_RFIFO1_FMP1                     ((uint8_t)0x03)               /* FIFO 1 Message Pending */
+#define  CAN_RFIFO1_FULL1                    ((uint8_t)0x08)               /* FIFO 1 Full */
+#define  CAN_RFIFO1_FOVR1                    ((uint8_t)0x10)               /* FIFO 1 Overrun */
+#define  CAN_RFIFO1_RFOM1                    ((uint8_t)0x20)               /* Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_INTENR register  *******************/
+#define  CAN_INTENR_TMEIE                    ((uint32_t)0x00000001)        /* Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_INTENR_FMPIE0                   ((uint32_t)0x00000002)        /* FIFO Message Pending Interrupt Enable */
+#define  CAN_INTENR_FFIE0                    ((uint32_t)0x00000004)        /* FIFO Full Interrupt Enable */
+#define  CAN_INTENR_FOVIE0                   ((uint32_t)0x00000008)        /* FIFO Overrun Interrupt Enable */
+#define  CAN_INTENR_FMPIE1                   ((uint32_t)0x00000010)        /* FIFO Message Pending Interrupt Enable */
+#define  CAN_INTENR_FFIE1                    ((uint32_t)0x00000020)        /* FIFO Full Interrupt Enable */
+#define  CAN_INTENR_FOVIE1                   ((uint32_t)0x00000040)        /* FIFO Overrun Interrupt Enable */
+#define  CAN_INTENR_EWGIE                    ((uint32_t)0x00000100)        /* Error Warning Interrupt Enable */
+#define  CAN_INTENR_EPVIE                    ((uint32_t)0x00000200)        /* Error Passive Interrupt Enable */
+#define  CAN_INTENR_BOFIE                    ((uint32_t)0x00000400)        /* Bus-Off Interrupt Enable */
+#define  CAN_INTENR_LECIE                    ((uint32_t)0x00000800)        /* Last Error Code Interrupt Enable */
+#define  CAN_INTENR_ERRIE                    ((uint32_t)0x00008000)        /* Error Interrupt Enable */
+#define  CAN_INTENR_WKUIE                    ((uint32_t)0x00010000)        /* Wakeup Interrupt Enable */
+#define  CAN_INTENR_SLKIE                    ((uint32_t)0x00020000)        /* Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ERRSR register  *******************/
+#define  CAN_ERRSR_EWGF                      ((uint32_t)0x00000001)        /* Error Warning Flag */
+#define  CAN_ERRSR_EPVF                      ((uint32_t)0x00000002)        /* Error Passive Flag */
+#define  CAN_ERRSR_BOFF                      ((uint32_t)0x00000004)        /* Bus-Off Flag */
+
+#define  CAN_ERRSR_LEC                       ((uint32_t)0x00000070)        /* LEC[2:0] bits (Last Error Code) */
+#define  CAN_ERRSR_LEC_0                     ((uint32_t)0x00000010)        /* Bit 0 */
+#define  CAN_ERRSR_LEC_1                     ((uint32_t)0x00000020)        /* Bit 1 */
+#define  CAN_ERRSR_LEC_2                     ((uint32_t)0x00000040)        /* Bit 2 */
+
+#define  CAN_ERRSR_TEC                       ((uint32_t)0x00FF0000)        /* Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ERRSR_REC                       ((uint32_t)0xFF000000)        /* Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTIMR register  ********************/
+#define  CAN_BTIMR_BRP                       ((uint32_t)0x000003FF)        /* Baud Rate Prescaler */
+#define  CAN_BTIMR_TS1                       ((uint32_t)0x000F0000)        /* Time Segment 1 */
+#define  CAN_BTIMR_TS2                       ((uint32_t)0x00700000)        /* Time Segment 2 */
+#define  CAN_BTIMR_SJW                       ((uint32_t)0x03000000)        /* Resynchronization Jump Width */
+#define  CAN_BTIMR_LBKM                      ((uint32_t)0x40000000)        /* Loop Back Mode (Debug) */
+#define  CAN_BTIMR_SILM                      ((uint32_t)0x80000000)        /* Silent Mode */
+
+/******************  Bit definition for CAN_TXMI0R register  ********************/
+#define  CAN_TXMI0R_TXRQ                     ((uint32_t)0x00000001)        /* Transmit Mailbox Request */
+#define  CAN_TXMI0R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_TXMI0R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_TXMI0R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended Identifier */
+#define  CAN_TXMI0R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TXMDT0R register  *******************/
+#define  CAN_TXMDT0R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_TXMDT0R_TGT                     ((uint32_t)0x00000100)        /* Transmit Global Time */
+#define  CAN_TXMDT0R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/******************  Bit definition for CAN_TXMDL0R register  *******************/
+#define  CAN_TXMDL0R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_TXMDL0R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_TXMDL0R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_TXMDL0R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/******************  Bit definition for CAN_TXMDH0R register  *******************/
+#define  CAN_TXMDH0R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_TXMDH0R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_TXMDH0R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_TXMDH0R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_TXMI1R register  *******************/
+#define  CAN_TXMI1R_TXRQ                     ((uint32_t)0x00000001)        /* Transmit Mailbox Request */
+#define  CAN_TXMI1R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_TXMI1R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_TXMI1R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended Identifier */
+#define  CAN_TXMI1R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TXMDT1R register  ******************/
+#define  CAN_TXMDT1R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_TXMDT1R_TGT                     ((uint32_t)0x00000100)        /* Transmit Global Time */
+#define  CAN_TXMDT1R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_TXMDL1R register  ******************/
+#define  CAN_TXMDL1R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_TXMDL1R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_TXMDL1R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_TXMDL1R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_TXMDH1R register  ******************/
+#define  CAN_TXMDH1R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_TXMDH1R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_TXMDH1R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_TXMDH1R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_TXMI2R register  *******************/
+#define  CAN_TXMI2R_TXRQ                     ((uint32_t)0x00000001)        /* Transmit Mailbox Request */
+#define  CAN_TXMI2R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_TXMI2R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_TXMI2R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended identifier */
+#define  CAN_TXMI2R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TXMDT2R register  ******************/  
+#define  CAN_TXMDT2R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_TXMDT2R_TGT                     ((uint32_t)0x00000100)        /* Transmit Global Time */
+#define  CAN_TXMDT2R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_TXMDL2R register  ******************/
+#define  CAN_TXMDL2R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_TXMDL2R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_TXMDL2R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_TXMDL2R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_TXMDH2R register  ******************/
+#define  CAN_TXMDH2R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_TXMDH2R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_TXMDH2R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_TXMDH2R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_RXMI0R register  *******************/
+#define  CAN_RXMI0R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_RXMI0R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_RXMI0R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended Identifier */
+#define  CAN_RXMI0R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RXMDT0R register  ******************/
+#define  CAN_RXMDT0R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_RXMDT0R_FMI                     ((uint32_t)0x0000FF00)        /* Filter Match Index */
+#define  CAN_RXMDT0R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_RXMDL0R register  ******************/
+#define  CAN_RXMDL0R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_RXMDL0R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_RXMDL0R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_RXMDL0R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_RXMDH0R register  ******************/
+#define  CAN_RXMDH0R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_RXMDH0R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_RXMDH0R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_RXMDH0R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_RXMI1R register  *******************/
+#define  CAN_RXMI1R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_RXMI1R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_RXMI1R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended identifier */
+#define  CAN_RXMI1R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RXMDT1R register  ******************/
+#define  CAN_RXMDT1R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_RXMDT1R_FMI                     ((uint32_t)0x0000FF00)        /* Filter Match Index */
+#define  CAN_RXMDT1R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_RXMDL1R register  ******************/
+#define  CAN_RXMDL1R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_RXMDL1R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_RXMDL1R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_RXMDL1R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_RXMDH1R register  ******************/
+#define  CAN_RXMDH1R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_RXMDH1R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_RXMDH1R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_RXMDH1R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_FCTLR register  ********************/
+#define  CAN_FCTLR_FINIT                     ((uint8_t)0x01)               /* Filter Init Mode */
+
+/*******************  Bit definition for CAN_FMCFGR register  *******************/
+#define  CAN_FMCFGR_FBM                      ((uint16_t)0x3FFF)            /* Filter Mode */
+#define  CAN_FMCFGR_FBM0                     ((uint16_t)0x0001)            /* Filter Init Mode bit 0 */
+#define  CAN_FMCFGR_FBM1                     ((uint16_t)0x0002)            /* Filter Init Mode bit 1 */
+#define  CAN_FMCFGR_FBM2                     ((uint16_t)0x0004)            /* Filter Init Mode bit 2 */
+#define  CAN_FMCFGR_FBM3                     ((uint16_t)0x0008)            /* Filter Init Mode bit 3 */
+#define  CAN_FMCFGR_FBM4                     ((uint16_t)0x0010)            /* Filter Init Mode bit 4 */
+#define  CAN_FMCFGR_FBM5                     ((uint16_t)0x0020)            /* Filter Init Mode bit 5 */
+#define  CAN_FMCFGR_FBM6                     ((uint16_t)0x0040)            /* Filter Init Mode bit 6 */
+#define  CAN_FMCFGR_FBM7                     ((uint16_t)0x0080)            /* Filter Init Mode bit 7 */
+#define  CAN_FMCFGR_FBM8                     ((uint16_t)0x0100)            /* Filter Init Mode bit 8 */
+#define  CAN_FMCFGR_FBM9                     ((uint16_t)0x0200)            /* Filter Init Mode bit 9 */
+#define  CAN_FMCFGR_FBM10                    ((uint16_t)0x0400)            /* Filter Init Mode bit 10 */
+#define  CAN_FMCFGR_FBM11                    ((uint16_t)0x0800)            /* Filter Init Mode bit 11 */
+#define  CAN_FMCFGR_FBM12                    ((uint16_t)0x1000)            /* Filter Init Mode bit 12 */
+#define  CAN_FMCFGR_FBM13                    ((uint16_t)0x2000)            /* Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FSCFGR register  *******************/
+#define  CAN_FSCFGR_FSC                      ((uint16_t)0x3FFF)            /* Filter Scale Configuration */
+#define  CAN_FSCFGR_FSC0                     ((uint16_t)0x0001)            /* Filter Scale Configuration bit 0 */
+#define  CAN_FSCFGR_FSC1                     ((uint16_t)0x0002)            /* Filter Scale Configuration bit 1 */
+#define  CAN_FSCFGR_FSC2                     ((uint16_t)0x0004)            /* Filter Scale Configuration bit 2 */
+#define  CAN_FSCFGR_FSC3                     ((uint16_t)0x0008)            /* Filter Scale Configuration bit 3 */
+#define  CAN_FSCFGR_FSC4                     ((uint16_t)0x0010)            /* Filter Scale Configuration bit 4 */
+#define  CAN_FSCFGR_FSC5                     ((uint16_t)0x0020)            /* Filter Scale Configuration bit 5 */
+#define  CAN_FSCFGR_FSC6                     ((uint16_t)0x0040)            /* Filter Scale Configuration bit 6 */
+#define  CAN_FSCFGR_FSC7                     ((uint16_t)0x0080)            /* Filter Scale Configuration bit 7 */
+#define  CAN_FSCFGR_FSC8                     ((uint16_t)0x0100)            /* Filter Scale Configuration bit 8 */
+#define  CAN_FSCFGR_FSC9                     ((uint16_t)0x0200)            /* Filter Scale Configuration bit 9 */
+#define  CAN_FSCFGR_FSC10                    ((uint16_t)0x0400)            /* Filter Scale Configuration bit 10 */
+#define  CAN_FSCFGR_FSC11                    ((uint16_t)0x0800)            /* Filter Scale Configuration bit 11 */
+#define  CAN_FSCFGR_FSC12                    ((uint16_t)0x1000)            /* Filter Scale Configuration bit 12 */
+#define  CAN_FSCFGR_FSC13                    ((uint16_t)0x2000)            /* Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FAFIFOR register  *******************/
+#define  CAN_FAFIFOR_FFA                     ((uint16_t)0x3FFF)            /* Filter FIFO Assignment */
+#define  CAN_FAFIFOR_FFA0                    ((uint16_t)0x0001)            /* Filter FIFO Assignment for Filter 0 */
+#define  CAN_FAFIFOR_FFA1                    ((uint16_t)0x0002)            /* Filter FIFO Assignment for Filter 1 */
+#define  CAN_FAFIFOR_FFA2                    ((uint16_t)0x0004)            /* Filter FIFO Assignment for Filter 2 */
+#define  CAN_FAFIFOR_FFA3                    ((uint16_t)0x0008)            /* Filter FIFO Assignment for Filter 3 */
+#define  CAN_FAFIFOR_FFA4                    ((uint16_t)0x0010)            /* Filter FIFO Assignment for Filter 4 */
+#define  CAN_FAFIFOR_FFA5                    ((uint16_t)0x0020)            /* Filter FIFO Assignment for Filter 5 */
+#define  CAN_FAFIFOR_FFA6                    ((uint16_t)0x0040)            /* Filter FIFO Assignment for Filter 6 */
+#define  CAN_FAFIFOR_FFA7                    ((uint16_t)0x0080)            /* Filter FIFO Assignment for Filter 7 */
+#define  CAN_FAFIFOR_FFA8                    ((uint16_t)0x0100)            /* Filter FIFO Assignment for Filter 8 */
+#define  CAN_FAFIFOR_FFA9                    ((uint16_t)0x0200)            /* Filter FIFO Assignment for Filter 9 */
+#define  CAN_FAFIFOR_FFA10                   ((uint16_t)0x0400)            /* Filter FIFO Assignment for Filter 10 */
+#define  CAN_FAFIFOR_FFA11                   ((uint16_t)0x0800)            /* Filter FIFO Assignment for Filter 11 */
+#define  CAN_FAFIFOR_FFA12                   ((uint16_t)0x1000)            /* Filter FIFO Assignment for Filter 12 */
+#define  CAN_FAFIFOR_FFA13                   ((uint16_t)0x2000)            /* Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FWR register  *******************/
+#define  CAN_FWR_FACT                        ((uint16_t)0x3FFF)            /* Filter Active */
+#define  CAN_FWR_FACT0                       ((uint16_t)0x0001)            /* Filter 0 Active */
+#define  CAN_FWR_FACT1                       ((uint16_t)0x0002)            /* Filter 1 Active */
+#define  CAN_FWR_FACT2                       ((uint16_t)0x0004)            /* Filter 2 Active */
+#define  CAN_FWR_FACT3                       ((uint16_t)0x0008)            /* Filter 3 Active */
+#define  CAN_FWR_FACT4                       ((uint16_t)0x0010)            /* Filter 4 Active */
+#define  CAN_FWR_FACT5                       ((uint16_t)0x0020)            /* Filter 5 Active */
+#define  CAN_FWR_FACT6                       ((uint16_t)0x0040)            /* Filter 6 Active */
+#define  CAN_FWR_FACT7                       ((uint16_t)0x0080)            /* Filter 7 Active */
+#define  CAN_FWR_FACT8                       ((uint16_t)0x0100)            /* Filter 8 Active */
+#define  CAN_FWR_FACT9                       ((uint16_t)0x0200)            /* Filter 9 Active */
+#define  CAN_FWR_FACT10                      ((uint16_t)0x0400)            /* Filter 10 Active */
+#define  CAN_FWR_FACT11                      ((uint16_t)0x0800)            /* Filter 11 Active */
+#define  CAN_FWR_FACT12                      ((uint16_t)0x1000)            /* Filter 12 Active */
+#define  CAN_FWR_FACT13                      ((uint16_t)0x2000)            /* Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+
+
+/******************************************************************************/
+/*                          CRC Calculation Unit                              */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DATAR register  *********************/
+#define  CRC_DATAR_DR                           ((uint32_t)0xFFFFFFFF) /* Data register bits */
+
+
+/*******************  Bit definition for CRC_IDATAR register  ********************/
+#define  CRC_IDR_IDATAR                         ((uint8_t)0xFF)        /* General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CTLR register  ********************/
+#define  CRC_CTLR_RESET                         ((uint8_t)0x01)        /* RESET bit */
+
+/******************************************************************************/
+/*                      Digital to Analog Converter                           */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CTLR register  ********************/
+#define  DAC_EN1                          ((uint32_t)0x00000001)        /* DAC channel1 enable */
+#define  DAC_BOFF1                        ((uint32_t)0x00000002)        /* DAC channel1 output buffer disable */
+#define  DAC_TEN1                         ((uint32_t)0x00000004)        /* DAC channel1 Trigger enable */
+
+#define  DAC_TSEL1                        ((uint32_t)0x00000038)        /* TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_TSEL1_0                      ((uint32_t)0x00000008)        /* Bit 0 */
+#define  DAC_TSEL1_1                      ((uint32_t)0x00000010)        /* Bit 1 */
+#define  DAC_TSEL1_2                      ((uint32_t)0x00000020)        /* Bit 2 */
+
+#define  DAC_WAVE1                        ((uint32_t)0x000000C0)        /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_WAVE1_0                      ((uint32_t)0x00000040)        /* Bit 0 */
+#define  DAC_WAVE1_1                      ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define  DAC_MAMP1                        ((uint32_t)0x00000F00)        /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_MAMP1_0                      ((uint32_t)0x00000100)        /* Bit 0 */
+#define  DAC_MAMP1_1                      ((uint32_t)0x00000200)        /* Bit 1 */
+#define  DAC_MAMP1_2                      ((uint32_t)0x00000400)        /* Bit 2 */
+#define  DAC_MAMP1_3                      ((uint32_t)0x00000800)        /* Bit 3 */
+
+#define  DAC_DMAEN1                       ((uint32_t)0x00001000)        /* DAC channel1 DMA enable */
+#define  DAC_EN2                          ((uint32_t)0x00010000)        /* DAC channel2 enable */
+#define  DAC_BOFF2                        ((uint32_t)0x00020000)        /* DAC channel2 output buffer disable */
+#define  DAC_TEN2                         ((uint32_t)0x00040000)        /* DAC channel2 Trigger enable */
+
+#define  DAC_TSEL2                        ((uint32_t)0x00380000)        /* TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_TSEL2_0                      ((uint32_t)0x00080000)        /* Bit 0 */
+#define  DAC_TSEL2_1                      ((uint32_t)0x00100000)        /* Bit 1 */
+#define  DAC_TSEL2_2                      ((uint32_t)0x00200000)        /* Bit 2 */
+
+#define  DAC_WAVE2                        ((uint32_t)0x00C00000)        /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_WAVE2_0                      ((uint32_t)0x00400000)        /* Bit 0 */
+#define  DAC_WAVE2_1                      ((uint32_t)0x00800000)        /* Bit 1 */
+
+#define  DAC_MAMP2                        ((uint32_t)0x0F000000)        /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_MAMP2_0                      ((uint32_t)0x01000000)        /* Bit 0 */
+#define  DAC_MAMP2_1                      ((uint32_t)0x02000000)        /* Bit 1 */
+#define  DAC_MAMP2_2                      ((uint32_t)0x04000000)        /* Bit 2 */
+#define  DAC_MAMP2_3                      ((uint32_t)0x08000000)        /* Bit 3 */
+
+#define  DAC_DMAEN2                       ((uint32_t)0x10000000)        /* DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTR register  ******************/
+#define  DAC_SWTRIG1                      ((uint8_t)0x01)               /* DAC channel1 software trigger */
+#define  DAC_SWTRIG2                      ((uint8_t)0x02)               /* DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_R12BDHR1 register  ******************/
+#define  DAC_DHR12R1                      ((uint16_t)0x0FFF)            /* DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR1 register  ******************/
+#define  DAC_DHR12L1                      ((uint16_t)0xFFF0)            /* DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR1 register  ******************/
+#define  DAC_DHR8R1                       ((uint8_t)0xFF)               /* DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_R12BDHR2 register  ******************/
+#define  DAC_DHR12R2                      ((uint16_t)0x0FFF)            /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR2 register  ******************/
+#define  DAC_DHR12L2                      ((uint16_t)0xFFF0)            /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR2 register  ******************/
+#define  DAC_DHR8R2                       ((uint8_t)0xFF)               /* DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_RD12BDHR register  ******************/
+#define  DAC_RD12BDHR_DACC1DHR            ((uint32_t)0x00000FFF)        /* DAC channel1 12-bit Right aligned data */
+#define  DAC_RD12BDHR_DACC2DHR            ((uint32_t)0x0FFF0000)        /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_LD12BDHR register  ******************/
+#define  DAC_LD12BDHR_DACC1DHR            ((uint32_t)0x0000FFF0)        /* DAC channel1 12-bit Left aligned data */
+#define  DAC_LD12BDHR_DACC2DHR            ((uint32_t)0xFFF00000)        /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_RD8BDHR register  ******************/
+#define  DAC_RD8BDHR_DACC1DHR             ((uint16_t)0x00FF)            /* DAC channel1 8-bit Right aligned data */
+#define  DAC_RD8BDHR_DACC2DHR             ((uint16_t)0xFF00)            /* DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DACC1DOR                     ((uint16_t)0x0FFF)            /* DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DACC2DOR                     ((uint16_t)0x0FFF)            /* DAC channel2 data output */
+
+/******************************************************************************/
+/*                             DMA Controller                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_INTFR register  ********************/
+#define  DMA_GIF1                           ((uint32_t)0x00000001)        /* Channel 1 Global interrupt flag */
+#define  DMA_TCIF1                          ((uint32_t)0x00000002)        /* Channel 1 Transfer Complete flag */
+#define  DMA_HTIF1                          ((uint32_t)0x00000004)        /* Channel 1 Half Transfer flag */
+#define  DMA_TEIF1                          ((uint32_t)0x00000008)        /* Channel 1 Transfer Error flag */
+#define  DMA_GIF2                           ((uint32_t)0x00000010)        /* Channel 2 Global interrupt flag */
+#define  DMA_TCIF2                          ((uint32_t)0x00000020)        /* Channel 2 Transfer Complete flag */
+#define  DMA_HTIF2                          ((uint32_t)0x00000040)        /* Channel 2 Half Transfer flag */
+#define  DMA_TEIF2                          ((uint32_t)0x00000080)        /* Channel 2 Transfer Error flag */
+#define  DMA_GIF3                           ((uint32_t)0x00000100)        /* Channel 3 Global interrupt flag */
+#define  DMA_TCIF3                          ((uint32_t)0x00000200)        /* Channel 3 Transfer Complete flag */
+#define  DMA_HTIF3                          ((uint32_t)0x00000400)        /* Channel 3 Half Transfer flag */
+#define  DMA_TEIF3                          ((uint32_t)0x00000800)        /* Channel 3 Transfer Error flag */
+#define  DMA_GIF4                           ((uint32_t)0x00001000)        /* Channel 4 Global interrupt flag */
+#define  DMA_TCIF4                          ((uint32_t)0x00002000)        /* Channel 4 Transfer Complete flag */
+#define  DMA_HTIF4                          ((uint32_t)0x00004000)        /* Channel 4 Half Transfer flag */
+#define  DMA_TEIF4                          ((uint32_t)0x00008000)        /* Channel 4 Transfer Error flag */
+#define  DMA_GIF5                           ((uint32_t)0x00010000)        /* Channel 5 Global interrupt flag */
+#define  DMA_TCIF5                          ((uint32_t)0x00020000)        /* Channel 5 Transfer Complete flag */
+#define  DMA_HTIF5                          ((uint32_t)0x00040000)        /* Channel 5 Half Transfer flag */
+#define  DMA_TEIF5                          ((uint32_t)0x00080000)        /* Channel 5 Transfer Error flag */
+#define  DMA_GIF6                           ((uint32_t)0x00100000)        /* Channel 6 Global interrupt flag */
+#define  DMA_TCIF6                          ((uint32_t)0x00200000)        /* Channel 6 Transfer Complete flag */
+#define  DMA_HTIF6                          ((uint32_t)0x00400000)        /* Channel 6 Half Transfer flag */
+#define  DMA_TEIF6                          ((uint32_t)0x00800000)        /* Channel 6 Transfer Error flag */
+#define  DMA_GIF7                           ((uint32_t)0x01000000)        /* Channel 7 Global interrupt flag */
+#define  DMA_TCIF7                          ((uint32_t)0x02000000)        /* Channel 7 Transfer Complete flag */
+#define  DMA_HTIF7                          ((uint32_t)0x04000000)        /* Channel 7 Half Transfer flag */
+#define  DMA_TEIF7                          ((uint32_t)0x08000000)        /* Channel 7 Transfer Error flag */
+
+#define  DMA_GIF8                           ((uint32_t)0x00000001)        /* Channel 8 Global interrupt flag */
+#define  DMA_TCIF8                          ((uint32_t)0x00000002)        /* Channel 8 Transfer Complete flag */
+#define  DMA_HTIF8                          ((uint32_t)0x00000004)        /* Channel 8 Half Transfer flag */
+#define  DMA_TEIF8                          ((uint32_t)0x00000008)        /* Channel 8 Transfer Error flag */
+#define  DMA_GIF9                           ((uint32_t)0x00000010)        /* Channel 9 Global interrupt flag */
+#define  DMA_TCIF9                          ((uint32_t)0x00000020)        /* Channel 9 Transfer Complete flag */
+#define  DMA_HTIF9                          ((uint32_t)0x00000040)        /* Channel 9 Half Transfer flag */
+#define  DMA_TEIF9                          ((uint32_t)0x00000080)        /* Channel 9 Transfer Error flag */
+#define  DMA_GIF10                          ((uint32_t)0x00000100)        /* Channel 10 Global interrupt flag */
+#define  DMA_TCIF10                         ((uint32_t)0x00000200)        /* Channel 10 Transfer Complete flag */
+#define  DMA_HTIF10                         ((uint32_t)0x00000400)        /* Channel 10 Half Transfer flag */
+#define  DMA_TEIF10                         ((uint32_t)0x00000800)        /* Channel 10 Transfer Error flag */
+#define  DMA_GIF11                          ((uint32_t)0x00001000)        /* Channel 11 Global interrupt flag */
+#define  DMA_TCIF11                         ((uint32_t)0x00002000)        /* Channel 11 Transfer Complete flag */
+#define  DMA_HTIF11                         ((uint32_t)0x00004000)        /* Channel 11 Half Transfer flag */
+#define  DMA_TEIF11                         ((uint32_t)0x00008000)        /* Channel 11 Transfer Error flag */
+
+/*******************  Bit definition for DMA_INTFCR register  *******************/
+#define  DMA_CGIF1                          ((uint32_t)0x00000001)        /* Channel 1 Global interrupt clear */
+#define  DMA_CTCIF1                         ((uint32_t)0x00000002)        /* Channel 1 Transfer Complete clear */
+#define  DMA_CHTIF1                         ((uint32_t)0x00000004)        /* Channel 1 Half Transfer clear */
+#define  DMA_CTEIF1                         ((uint32_t)0x00000008)        /* Channel 1 Transfer Error clear */
+#define  DMA_CGIF2                          ((uint32_t)0x00000010)        /* Channel 2 Global interrupt clear */
+#define  DMA_CTCIF2                         ((uint32_t)0x00000020)        /* Channel 2 Transfer Complete clear */
+#define  DMA_CHTIF2                         ((uint32_t)0x00000040)        /* Channel 2 Half Transfer clear */
+#define  DMA_CTEIF2                         ((uint32_t)0x00000080)        /* Channel 2 Transfer Error clear */
+#define  DMA_CGIF3                          ((uint32_t)0x00000100)        /* Channel 3 Global interrupt clear */
+#define  DMA_CTCIF3                         ((uint32_t)0x00000200)        /* Channel 3 Transfer Complete clear */
+#define  DMA_CHTIF3                         ((uint32_t)0x00000400)        /* Channel 3 Half Transfer clear */
+#define  DMA_CTEIF3                         ((uint32_t)0x00000800)        /* Channel 3 Transfer Error clear */
+#define  DMA_CGIF4                          ((uint32_t)0x00001000)        /* Channel 4 Global interrupt clear */
+#define  DMA_CTCIF4                         ((uint32_t)0x00002000)        /* Channel 4 Transfer Complete clear */
+#define  DMA_CHTIF4                         ((uint32_t)0x00004000)        /* Channel 4 Half Transfer clear */
+#define  DMA_CTEIF4                         ((uint32_t)0x00008000)        /* Channel 4 Transfer Error clear */
+#define  DMA_CGIF5                          ((uint32_t)0x00010000)        /* Channel 5 Global interrupt clear */
+#define  DMA_CTCIF5                         ((uint32_t)0x00020000)        /* Channel 5 Transfer Complete clear */
+#define  DMA_CHTIF5                         ((uint32_t)0x00040000)        /* Channel 5 Half Transfer clear */
+#define  DMA_CTEIF5                         ((uint32_t)0x00080000)        /* Channel 5 Transfer Error clear */
+#define  DMA_CGIF6                          ((uint32_t)0x00100000)        /* Channel 6 Global interrupt clear */
+#define  DMA_CTCIF6                         ((uint32_t)0x00200000)        /* Channel 6 Transfer Complete clear */
+#define  DMA_CHTIF6                         ((uint32_t)0x00400000)        /* Channel 6 Half Transfer clear */
+#define  DMA_CTEIF6                         ((uint32_t)0x00800000)        /* Channel 6 Transfer Error clear */
+#define  DMA_CGIF7                          ((uint32_t)0x01000000)        /* Channel 7 Global interrupt clear */
+#define  DMA_CTCIF7                         ((uint32_t)0x02000000)        /* Channel 7 Transfer Complete clear */
+#define  DMA_CHTIF7                         ((uint32_t)0x04000000)        /* Channel 7 Half Transfer clear */
+#define  DMA_CTEIF7                         ((uint32_t)0x08000000)        /* Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CFGR1 register  *******************/
+#define  DMA_CFGR1_EN                       ((uint16_t)0x0001)            /* Channel enable*/
+#define  DMA_CFGR1_TCIE                     ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFGR1_HTIE                     ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFGR1_TEIE                     ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFGR1_DIR                      ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFGR1_CIRC                     ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFGR1_PINC                     ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFGR1_MINC                     ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFGR1_PSIZE                    ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFGR1_PSIZE_0                  ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFGR1_PSIZE_1                  ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  DMA_CFGR1_MSIZE                    ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFGR1_MSIZE_0                  ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFGR1_MSIZE_1                  ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  DMA_CFGR1_PL                       ((uint16_t)0x3000)            /* PL[1:0] bits(Channel Priority level) */
+#define  DMA_CFGR1_PL_0                     ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFGR1_PL_1                     ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  DMA_CFGR1_MEM2MEM                  ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR2 register  *******************/
+#define  DMA_CFGR2_EN                       ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFGR2_TCIE                     ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFGR2_HTIE                     ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFGR2_TEIE                     ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFGR2_DIR                      ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFGR2_CIRC                     ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFGR2_PINC                     ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFGR2_MINC                     ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFGR2_PSIZE                    ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFGR2_PSIZE_0                  ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFGR2_PSIZE_1                  ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  DMA_CFGR2_MSIZE                    ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFGR2_MSIZE_0                  ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFGR2_MSIZE_1                  ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  DMA_CFGR2_PL                       ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFGR2_PL_0                     ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFGR2_PL_1                     ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  DMA_CFGR2_MEM2MEM                  ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR3 register  *******************/
+#define  DMA_CFGR3_EN                       ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFGR3_TCIE                     ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFGR3_HTIE                     ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFGR3_TEIE                     ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFGR3_DIR                      ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFGR3_CIRC                     ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFGR3_PINC                     ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFGR3_MINC                     ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFGR3_PSIZE                    ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFGR3_PSIZE_0                  ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFGR3_PSIZE_1                  ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  DMA_CFGR3_MSIZE                    ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFGR3_MSIZE_0                  ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFGR3_MSIZE_1                  ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  DMA_CFGR3_PL                       ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFGR3_PL_0                     ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFGR3_PL_1                     ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  DMA_CFGR3_MEM2MEM                  ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG4 register  *******************/
+#define  DMA_CFG4_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG4_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG4_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG4_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG4_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG4_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG4_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG4_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFG4_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG4_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG4_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG4_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG4_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG4_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG4_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG4_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG4_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG4_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/******************  Bit definition for DMA_CFG5 register  *******************/
+#define  DMA_CFG5_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG5_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG5_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG5_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG5_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG5_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG5_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG5_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+             
+#define  DMA_CFG5_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG5_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG5_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG5_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG5_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG5_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG5_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG5_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG5_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG5_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CFG6 register  *******************/
+#define  DMA_CFG6_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG6_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG6_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG6_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG6_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG6_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG6_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG6_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+             
+#define  DMA_CFG6_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG6_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG6_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG6_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG6_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG6_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG6_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG6_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG6_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG6_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG7 register  *******************/
+#define  DMA_CFG7_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG7_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG7_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG7_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG7_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG7_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG7_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG7_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+             
+#define  DMA_CFG7_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG7_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG7_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG7_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG7_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG7_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG7_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG7_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG7_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG7_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNTR1 register  ******************/
+#define  DMA_CNTR1_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR2 register  ******************/
+#define  DMA_CNTR2_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR3 register  ******************/
+#define  DMA_CNTR3_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR4 register  ******************/
+#define  DMA_CNTR4_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR5 register  ******************/
+#define  DMA_CNTR5_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR6 register  ******************/
+#define  DMA_CNTR6_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR7 register  ******************/
+#define  DMA_CNTR7_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_PADDR1 register  *******************/
+#define  DMA_PADDR1_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR2 register  *******************/
+#define  DMA_PADDR2_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR3 register  *******************/
+#define  DMA_PADDR3_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR4 register  *******************/
+#define  DMA_PADDR4_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR5 register  *******************/
+#define  DMA_PADDR5_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR6 register  *******************/
+#define  DMA_PADDR6_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR7 register  *******************/
+#define  DMA_PADDR7_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_MADDR1 register  *******************/
+#define  DMA_MADDR1_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR2 register  *******************/
+#define  DMA_MADDR2_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR3 register  *******************/
+#define  DMA_MADDR3_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR4 register  *******************/
+#define  DMA_MADDR4_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR5 register  *******************/
+#define  DMA_MADDR5_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR6 register  *******************/
+#define  DMA_MADDR6_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR7 register  *******************/
+#define  DMA_MADDR7_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+
+/******************************************************************************/
+/*                    External Interrupt/Event Controller                     */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_INTENR register  *******************/
+#define  EXTI_INTENR_MR0                        ((uint32_t)0x00000001)        /* Interrupt Mask on line 0 */
+#define  EXTI_INTENR_MR1                        ((uint32_t)0x00000002)        /* Interrupt Mask on line 1 */
+#define  EXTI_INTENR_MR2                        ((uint32_t)0x00000004)        /* Interrupt Mask on line 2 */
+#define  EXTI_INTENR_MR3                        ((uint32_t)0x00000008)        /* Interrupt Mask on line 3 */
+#define  EXTI_INTENR_MR4                        ((uint32_t)0x00000010)        /* Interrupt Mask on line 4 */
+#define  EXTI_INTENR_MR5                        ((uint32_t)0x00000020)        /* Interrupt Mask on line 5 */
+#define  EXTI_INTENR_MR6                        ((uint32_t)0x00000040)        /* Interrupt Mask on line 6 */
+#define  EXTI_INTENR_MR7                        ((uint32_t)0x00000080)        /* Interrupt Mask on line 7 */
+#define  EXTI_INTENR_MR8                        ((uint32_t)0x00000100)        /* Interrupt Mask on line 8 */
+#define  EXTI_INTENR_MR9                        ((uint32_t)0x00000200)        /* Interrupt Mask on line 9 */
+#define  EXTI_INTENR_MR10                       ((uint32_t)0x00000400)        /* Interrupt Mask on line 10 */
+#define  EXTI_INTENR_MR11                       ((uint32_t)0x00000800)        /* Interrupt Mask on line 11 */
+#define  EXTI_INTENR_MR12                       ((uint32_t)0x00001000)        /* Interrupt Mask on line 12 */
+#define  EXTI_INTENR_MR13                       ((uint32_t)0x00002000)        /* Interrupt Mask on line 13 */
+#define  EXTI_INTENR_MR14                       ((uint32_t)0x00004000)        /* Interrupt Mask on line 14 */
+#define  EXTI_INTENR_MR15                       ((uint32_t)0x00008000)        /* Interrupt Mask on line 15 */
+#define  EXTI_INTENR_MR16                       ((uint32_t)0x00010000)        /* Interrupt Mask on line 16 */
+#define  EXTI_INTENR_MR17                       ((uint32_t)0x00020000)        /* Interrupt Mask on line 17 */
+#define  EXTI_INTENR_MR18                       ((uint32_t)0x00040000)        /* Interrupt Mask on line 18 */
+#define  EXTI_INTENR_MR19                       ((uint32_t)0x00080000)        /* Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EVENR register  *******************/
+#define  EXTI_EVENR_MR0                         ((uint32_t)0x00000001)        /* Event Mask on line 0 */
+#define  EXTI_EVENR_MR1                         ((uint32_t)0x00000002)        /* Event Mask on line 1 */
+#define  EXTI_EVENR_MR2                         ((uint32_t)0x00000004)        /* Event Mask on line 2 */
+#define  EXTI_EVENR_MR3                         ((uint32_t)0x00000008)        /* Event Mask on line 3 */
+#define  EXTI_EVENR_MR4                         ((uint32_t)0x00000010)        /* Event Mask on line 4 */
+#define  EXTI_EVENR_MR5                         ((uint32_t)0x00000020)        /* Event Mask on line 5 */
+#define  EXTI_EVENR_MR6                         ((uint32_t)0x00000040)        /* Event Mask on line 6 */
+#define  EXTI_EVENR_MR7                         ((uint32_t)0x00000080)        /* Event Mask on line 7 */
+#define  EXTI_EVENR_MR8                         ((uint32_t)0x00000100)        /* Event Mask on line 8 */
+#define  EXTI_EVENR_MR9                         ((uint32_t)0x00000200)        /* Event Mask on line 9 */
+#define  EXTI_EVENR_MR10                        ((uint32_t)0x00000400)        /* Event Mask on line 10 */
+#define  EXTI_EVENR_MR11                        ((uint32_t)0x00000800)        /* Event Mask on line 11 */
+#define  EXTI_EVENR_MR12                        ((uint32_t)0x00001000)        /* Event Mask on line 12 */
+#define  EXTI_EVENR_MR13                        ((uint32_t)0x00002000)        /* Event Mask on line 13 */
+#define  EXTI_EVENR_MR14                        ((uint32_t)0x00004000)        /* Event Mask on line 14 */
+#define  EXTI_EVENR_MR15                        ((uint32_t)0x00008000)        /* Event Mask on line 15 */
+#define  EXTI_EVENR_MR16                        ((uint32_t)0x00010000)        /* Event Mask on line 16 */
+#define  EXTI_EVENR_MR17                        ((uint32_t)0x00020000)        /* Event Mask on line 17 */
+#define  EXTI_EVENR_MR18                        ((uint32_t)0x00040000)        /* Event Mask on line 18 */
+#define  EXTI_EVENR_MR19                        ((uint32_t)0x00080000)        /* Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTENR register  *******************/
+#define  EXTI_RTENR_TR0                         ((uint32_t)0x00000001)        /* Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTENR_TR1                         ((uint32_t)0x00000002)        /* Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTENR_TR2                         ((uint32_t)0x00000004)        /* Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTENR_TR3                         ((uint32_t)0x00000008)        /* Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTENR_TR4                         ((uint32_t)0x00000010)        /* Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTENR_TR5                         ((uint32_t)0x00000020)        /* Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTENR_TR6                         ((uint32_t)0x00000040)        /* Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTENR_TR7                         ((uint32_t)0x00000080)        /* Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTENR_TR8                         ((uint32_t)0x00000100)        /* Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTENR_TR9                         ((uint32_t)0x00000200)        /* Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTENR_TR10                        ((uint32_t)0x00000400)        /* Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTENR_TR11                        ((uint32_t)0x00000800)        /* Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTENR_TR12                        ((uint32_t)0x00001000)        /* Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTENR_TR13                        ((uint32_t)0x00002000)        /* Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTENR_TR14                        ((uint32_t)0x00004000)        /* Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTENR_TR15                        ((uint32_t)0x00008000)        /* Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTENR_TR16                        ((uint32_t)0x00010000)        /* Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTENR_TR17                        ((uint32_t)0x00020000)        /* Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTENR_TR18                        ((uint32_t)0x00040000)        /* Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTENR_TR19                        ((uint32_t)0x00080000)        /* Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTENR register  *******************/
+#define  EXTI_FTENR_TR0                         ((uint32_t)0x00000001)        /* Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTENR_TR1                         ((uint32_t)0x00000002)        /* Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTENR_TR2                         ((uint32_t)0x00000004)        /* Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTENR_TR3                         ((uint32_t)0x00000008)        /* Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTENR_TR4                         ((uint32_t)0x00000010)        /* Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTENR_TR5                         ((uint32_t)0x00000020)        /* Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTENR_TR6                         ((uint32_t)0x00000040)        /* Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTENR_TR7                         ((uint32_t)0x00000080)        /* Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTENR_TR8                         ((uint32_t)0x00000100)        /* Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTENR_TR9                         ((uint32_t)0x00000200)        /* Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTENR_TR10                        ((uint32_t)0x00000400)        /* Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTENR_TR11                        ((uint32_t)0x00000800)        /* Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTENR_TR12                        ((uint32_t)0x00001000)        /* Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTENR_TR13                        ((uint32_t)0x00002000)        /* Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTENR_TR14                        ((uint32_t)0x00004000)        /* Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTENR_TR15                        ((uint32_t)0x00008000)        /* Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTENR_TR16                        ((uint32_t)0x00010000)        /* Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTENR_TR17                        ((uint32_t)0x00020000)        /* Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTENR_TR18                        ((uint32_t)0x00040000)        /* Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTENR_TR19                        ((uint32_t)0x00080000)        /* Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIEVR register  ******************/
+#define  EXTI_SWIEVR_SWIEVR0                    ((uint32_t)0x00000001)        /* Software Interrupt on line 0 */
+#define  EXTI_SWIEVR_SWIEVR1                    ((uint32_t)0x00000002)        /* Software Interrupt on line 1 */
+#define  EXTI_SWIEVR_SWIEVR2                    ((uint32_t)0x00000004)        /* Software Interrupt on line 2 */
+#define  EXTI_SWIEVR_SWIEVR3                    ((uint32_t)0x00000008)        /* Software Interrupt on line 3 */
+#define  EXTI_SWIEVR_SWIEVR4                    ((uint32_t)0x00000010)        /* Software Interrupt on line 4 */
+#define  EXTI_SWIEVR_SWIEVR5                    ((uint32_t)0x00000020)        /* Software Interrupt on line 5 */
+#define  EXTI_SWIEVR_SWIEVR6                    ((uint32_t)0x00000040)        /* Software Interrupt on line 6 */
+#define  EXTI_SWIEVR_SWIEVR7                    ((uint32_t)0x00000080)        /* Software Interrupt on line 7 */
+#define  EXTI_SWIEVR_SWIEVR8                    ((uint32_t)0x00000100)        /* Software Interrupt on line 8 */
+#define  EXTI_SWIEVR_SWIEVR9                    ((uint32_t)0x00000200)        /* Software Interrupt on line 9 */
+#define  EXTI_SWIEVR_SWIEVR10                   ((uint32_t)0x00000400)        /* Software Interrupt on line 10 */
+#define  EXTI_SWIEVR_SWIEVR11                   ((uint32_t)0x00000800)        /* Software Interrupt on line 11 */
+#define  EXTI_SWIEVR_SWIEVR12                   ((uint32_t)0x00001000)        /* Software Interrupt on line 12 */
+#define  EXTI_SWIEVR_SWIEVR13                   ((uint32_t)0x00002000)        /* Software Interrupt on line 13 */
+#define  EXTI_SWIEVR_SWIEVR14                   ((uint32_t)0x00004000)        /* Software Interrupt on line 14 */
+#define  EXTI_SWIEVR_SWIEVR15                   ((uint32_t)0x00008000)        /* Software Interrupt on line 15 */
+#define  EXTI_SWIEVR_SWIEVR16                   ((uint32_t)0x00010000)        /* Software Interrupt on line 16 */
+#define  EXTI_SWIEVR_SWIEVR17                   ((uint32_t)0x00020000)        /* Software Interrupt on line 17 */
+#define  EXTI_SWIEVR_SWIEVR18                   ((uint32_t)0x00040000)        /* Software Interrupt on line 18 */
+#define  EXTI_SWIEVR_SWIEVR19                   ((uint32_t)0x00080000)        /* Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_INTFR register  ********************/
+#define  EXTI_INTF_INTF0                        ((uint32_t)0x00000001)        /* Pending bit for line 0 */
+#define  EXTI_INTF_INTF1                        ((uint32_t)0x00000002)        /* Pending bit for line 1 */
+#define  EXTI_INTF_INTF2                        ((uint32_t)0x00000004)        /* Pending bit for line 2 */
+#define  EXTI_INTF_INTF3                        ((uint32_t)0x00000008)        /* Pending bit for line 3 */
+#define  EXTI_INTF_INTF4                        ((uint32_t)0x00000010)        /* Pending bit for line 4 */
+#define  EXTI_INTF_INTF5                        ((uint32_t)0x00000020)        /* Pending bit for line 5 */
+#define  EXTI_INTF_INTF6                        ((uint32_t)0x00000040)        /* Pending bit for line 6 */
+#define  EXTI_INTF_INTF7                        ((uint32_t)0x00000080)        /* Pending bit for line 7 */
+#define  EXTI_INTF_INTF8                        ((uint32_t)0x00000100)        /* Pending bit for line 8 */
+#define  EXTI_INTF_INTF9                        ((uint32_t)0x00000200)        /* Pending bit for line 9 */
+#define  EXTI_INTF_INTF10                       ((uint32_t)0x00000400)        /* Pending bit for line 10 */
+#define  EXTI_INTF_INTF11                       ((uint32_t)0x00000800)        /* Pending bit for line 11 */
+#define  EXTI_INTF_INTF12                       ((uint32_t)0x00001000)        /* Pending bit for line 12 */
+#define  EXTI_INTF_INTF13                       ((uint32_t)0x00002000)        /* Pending bit for line 13 */
+#define  EXTI_INTF_INTF14                       ((uint32_t)0x00004000)        /* Pending bit for line 14 */
+#define  EXTI_INTF_INTF15                       ((uint32_t)0x00008000)        /* Pending bit for line 15 */
+#define  EXTI_INTF_INTF16                       ((uint32_t)0x00010000)        /* Pending bit for line 16 */
+#define  EXTI_INTF_INTF17                       ((uint32_t)0x00020000)        /* Pending bit for line 17 */
+#define  EXTI_INTF_INTF18                       ((uint32_t)0x00040000)        /* Pending bit for line 18 */
+#define  EXTI_INTF_INTF19                       ((uint32_t)0x00080000)        /* Pending bit for line 19 */
+
+/******************************************************************************/
+/*                      FLASH and Option Bytes Registers                      */
+/******************************************************************************/
+
+
+/*******************  Bit definition for FLASH_ACTLR register  ******************/
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                      ((uint32_t)0xFFFFFFFF)        /* FPEC Key */
+
+/*****************  Bit definition for FLASH_OBKEYR register  ****************/
+#define  FLASH_OBKEYR_OBKEYR                   ((uint32_t)0xFFFFFFFF)        /* Option Byte Key */
+
+/******************  Bit definition for FLASH_STATR register  *******************/
+#define  FLASH_STATR_BSY                       ((uint8_t)0x01)               /* Busy */
+#define  FLASH_STATR_PGERR                     ((uint8_t)0x04)               /* Programming Error */
+#define  FLASH_STATR_WRPRTERR                  ((uint8_t)0x10)               /* Write Protection Error */
+#define  FLASH_STATR_EOP                       ((uint8_t)0x20)               /* End of operation */
+
+/*******************  Bit definition for FLASH_CTLR register  *******************/
+#define  FLASH_CTLR_PG                         ((uint32_t)0x00000001)        /* Programming */
+#define  FLASH_CTLR_PER                        ((uint32_t)0x00000002)        /* Sector Erase 4K */
+#define  FLASH_CTLR_MER                        ((uint32_t)0x00000004)        /* Mass Erase */
+#define  FLASH_CTLR_OPTPG                      ((uint32_t)0x00000010)        /* Option Byte Programming */
+#define  FLASH_CTLR_OPTER                      ((uint32_t)0x00000020)        /* Option Byte Erase */
+#define  FLASH_CTLR_STRT                       ((uint32_t)0x00000040)        /* Start */
+#define  FLASH_CTLR_LOCK                       ((uint32_t)0x00000080)        /* Lock */
+#define  FLASH_CTLR_OPTWRE                     ((uint32_t)0x00000200)        /* Option Bytes Write Enable */
+#define  FLASH_CTLR_ERRIE                      ((uint32_t)0x00000400)        /* Error Interrupt Enable */
+#define  FLASH_CTLR_EOPIE                      ((uint32_t)0x00001000)        /* End of operation interrupt enable */
+#define  FLASH_CTLR_FAST_LOCK                  ((uint32_t)0x00008000)        /* Fast Lock */
+#define  FLASH_CTLR_PAGE_PG                    ((uint32_t)0x00010000)        /* Page Programming 256Byte */
+#define  FLASH_CTLR_PAGE_ER                    ((uint32_t)0x00020000)        /* Page Erase 256Byte */
+#define  FLASH_CTLR_PAGE_BER32                 ((uint32_t)0x00040000)        /* Block Erase 32K */
+#define  FLASH_CTLR_PAGE_BER64                 ((uint32_t)0x00080000)        /* Block Erase 64K */
+#define  FLASH_CTLR_PG_STRT                    ((uint32_t)0x00200000)        /* Page Programming Start */
+
+/*******************  Bit definition for FLASH_ADDR register  *******************/
+#define  FLASH_ADDR_FAR                        ((uint32_t)0xFFFFFFFF)        /* Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                      ((uint16_t)0x0001)            /* Option Byte Error */
+#define  FLASH_OBR_RDPRT                       ((uint16_t)0x0002)            /* Read protection */
+
+#define  FLASH_OBR_USER                        ((uint16_t)0x03FC)            /* User Option Bytes */
+#define  FLASH_OBR_WDG_SW                      ((uint16_t)0x0004)            /* WDG_SW */
+#define  FLASH_OBR_nRST_STOP                   ((uint16_t)0x0008)            /* nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                  ((uint16_t)0x0010)            /* nRST_STDBY */
+#define  FLASH_OBR_BFB2                        ((uint16_t)0x0020)            /* BFB2 */
+
+/******************  Bit definition for FLASH_WPR register  ******************/
+#define  FLASH_WPR_WRP                         ((uint32_t)0xFFFFFFFF)        /* Write Protect */
+
+/******************  Bit definition for FLASH_RDPR register  *******************/
+#define  FLASH_RDPR_RDPR                       ((uint32_t)0x000000FF)        /* Read protection option byte */
+#define  FLASH_RDPR_nRDPR                      ((uint32_t)0x0000FF00)        /* Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define  FLASH_USER_USER                       ((uint32_t)0x00FF0000)        /* User option byte */
+#define  FLASH_USER_nUSER                      ((uint32_t)0xFF000000)        /* User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define  FLASH_Data0_Data0                     ((uint32_t)0x000000FF)        /* User data storage option byte */
+#define  FLASH_Data0_nData0                    ((uint32_t)0x0000FF00)        /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define  FLASH_Data1_Data1                     ((uint32_t)0x00FF0000)        /* User data storage option byte */
+#define  FLASH_Data1_nData1                    ((uint32_t)0xFF000000)        /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRPR0 register  ******************/
+#define  FLASH_WRPR0_WRPR0                     ((uint32_t)0x000000FF)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR0_nWRPR0                    ((uint32_t)0x0000FF00)        /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR1 register  ******************/
+#define  FLASH_WRPR1_WRPR1                     ((uint32_t)0x00FF0000)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR1_nWRPR1                    ((uint32_t)0xFF000000)        /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR2 register  ******************/
+#define  FLASH_WRPR2_WRPR2                     ((uint32_t)0x000000FF)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR2_nWRPR2                    ((uint32_t)0x0000FF00)        /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR3 register  ******************/
+#define  FLASH_WRPR3_WRPR3                     ((uint32_t)0x00FF0000)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR3_nWRPR3                    ((uint32_t)0xFF000000)        /* Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                General Purpose and Alternate Function I/O                  */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CFGLR register  *******************/
+#define  GPIO_CFGLR_MODE                       ((uint32_t)0x33333333)        /* Port x mode bits */
+
+#define  GPIO_CFGLR_MODE0                      ((uint32_t)0x00000003)        /* MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CFGLR_MODE0_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE0_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE1                      ((uint32_t)0x00000030)        /* MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CFGLR_MODE1_0                    ((uint32_t)0x00000010)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE1_1                    ((uint32_t)0x00000020)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE2                      ((uint32_t)0x00000300)        /* MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CFGLR_MODE2_0                    ((uint32_t)0x00000100)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE2_1                    ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE3                      ((uint32_t)0x00003000)        /* MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CFGLR_MODE3_0                    ((uint32_t)0x00001000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE3_1                    ((uint32_t)0x00002000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE4                      ((uint32_t)0x00030000)        /* MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CFGLR_MODE4_0                    ((uint32_t)0x00010000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE4_1                    ((uint32_t)0x00020000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE5                      ((uint32_t)0x00300000)        /* MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CFGLR_MODE5_0                    ((uint32_t)0x00100000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE5_1                    ((uint32_t)0x00200000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE6                      ((uint32_t)0x03000000)        /* MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CFGLR_MODE6_0                    ((uint32_t)0x01000000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE6_1                    ((uint32_t)0x02000000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE7                      ((uint32_t)0x30000000)        /* MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CFGLR_MODE7_0                    ((uint32_t)0x10000000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE7_1                    ((uint32_t)0x20000000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF                        ((uint32_t)0xCCCCCCCC)        /* Port x configuration bits */
+
+#define  GPIO_CFGLR_CNF0                       ((uint32_t)0x0000000C)        /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CFGLR_CNF0_0                     ((uint32_t)0x00000004)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF0_1                     ((uint32_t)0x00000008)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF1                       ((uint32_t)0x000000C0)        /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CFGLR_CNF1_0                     ((uint32_t)0x00000040)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF1_1                     ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF2                       ((uint32_t)0x00000C00)        /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CFGLR_CNF2_0                     ((uint32_t)0x00000400)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF2_1                     ((uint32_t)0x00000800)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF3                       ((uint32_t)0x0000C000)        /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CFGLR_CNF3_0                     ((uint32_t)0x00004000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF3_1                     ((uint32_t)0x00008000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF4                       ((uint32_t)0x000C0000)        /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CFGLR_CNF4_0                     ((uint32_t)0x00040000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF4_1                     ((uint32_t)0x00080000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF5                       ((uint32_t)0x00C00000)        /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CFGLR_CNF5_0                     ((uint32_t)0x00400000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF5_1                     ((uint32_t)0x00800000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF6                       ((uint32_t)0x0C000000)        /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CFGLR_CNF6_0                     ((uint32_t)0x04000000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF6_1                     ((uint32_t)0x08000000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF7                       ((uint32_t)0xC0000000)        /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CFGLR_CNF7_0                     ((uint32_t)0x40000000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF7_1                     ((uint32_t)0x80000000)        /* Bit 1 */
+
+/*******************  Bit definition for GPIO_CFGHR register  *******************/
+#define  GPIO_CFGHR_MODE                       ((uint32_t)0x33333333)        /* Port x mode bits */
+
+#define  GPIO_CFGHR_MODE8                      ((uint32_t)0x00000003)        /* MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CFGHR_MODE8_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE8_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE9                      ((uint32_t)0x00000030)        /* MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CFGHR_MODE9_0                    ((uint32_t)0x00000010)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE9_1                    ((uint32_t)0x00000020)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE10                     ((uint32_t)0x00000300)        /* MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CFGHR_MODE10_0                   ((uint32_t)0x00000100)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE10_1                   ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE11                     ((uint32_t)0x00003000)        /* MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CFGHR_MODE11_0                   ((uint32_t)0x00001000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE11_1                   ((uint32_t)0x00002000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE12                     ((uint32_t)0x00030000)        /* MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CFGHR_MODE12_0                   ((uint32_t)0x00010000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE12_1                   ((uint32_t)0x00020000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE13                     ((uint32_t)0x00300000)        /* MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CFGHR_MODE13_0                   ((uint32_t)0x00100000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE13_1                   ((uint32_t)0x00200000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE14                     ((uint32_t)0x03000000)        /* MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CFGHR_MODE14_0                   ((uint32_t)0x01000000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE14_1                   ((uint32_t)0x02000000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE15                     ((uint32_t)0x30000000)        /* MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CFGHR_MODE15_0                   ((uint32_t)0x10000000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE15_1                   ((uint32_t)0x20000000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF                        ((uint32_t)0xCCCCCCCC)        /* Port x configuration bits */
+
+#define  GPIO_CFGHR_CNF8                       ((uint32_t)0x0000000C)        /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CFGHR_CNF8_0                     ((uint32_t)0x00000004)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF8_1                     ((uint32_t)0x00000008)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF9                       ((uint32_t)0x000000C0)        /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CFGHR_CNF9_0                     ((uint32_t)0x00000040)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF9_1                     ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF10                      ((uint32_t)0x00000C00)        /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CFGHR_CNF10_0                    ((uint32_t)0x00000400)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF10_1                    ((uint32_t)0x00000800)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF11                      ((uint32_t)0x0000C000)        /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CFGHR_CNF11_0                    ((uint32_t)0x00004000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF11_1                    ((uint32_t)0x00008000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF12                      ((uint32_t)0x000C0000)        /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CFGHR_CNF12_0                    ((uint32_t)0x00040000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF12_1                    ((uint32_t)0x00080000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF13                      ((uint32_t)0x00C00000)        /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CFGHR_CNF13_0                    ((uint32_t)0x00400000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF13_1                    ((uint32_t)0x00800000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF14                      ((uint32_t)0x0C000000)        /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CFGHR_CNF14_0                    ((uint32_t)0x04000000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF14_1                    ((uint32_t)0x08000000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF15                      ((uint32_t)0xC0000000)        /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CFGHR_CNF15_0                    ((uint32_t)0x40000000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF15_1                    ((uint32_t)0x80000000)        /* Bit 1 */
+
+/*******************  Bit definition for GPIO_INDR register  *******************/
+#define GPIO_INDR_IDR0                         ((uint16_t)0x0001)            /* Port input data, bit 0 */
+#define GPIO_INDR_IDR1                         ((uint16_t)0x0002)            /* Port input data, bit 1 */
+#define GPIO_INDR_IDR2                         ((uint16_t)0x0004)            /* Port input data, bit 2 */
+#define GPIO_INDR_IDR3                         ((uint16_t)0x0008)            /* Port input data, bit 3 */
+#define GPIO_INDR_IDR4                         ((uint16_t)0x0010)            /* Port input data, bit 4 */
+#define GPIO_INDR_IDR5                         ((uint16_t)0x0020)            /* Port input data, bit 5 */
+#define GPIO_INDR_IDR6                         ((uint16_t)0x0040)            /* Port input data, bit 6 */
+#define GPIO_INDR_IDR7                         ((uint16_t)0x0080)            /* Port input data, bit 7 */
+#define GPIO_INDR_IDR8                         ((uint16_t)0x0100)            /* Port input data, bit 8 */
+#define GPIO_INDR_IDR9                         ((uint16_t)0x0200)            /* Port input data, bit 9 */
+#define GPIO_INDR_IDR10                        ((uint16_t)0x0400)            /* Port input data, bit 10 */
+#define GPIO_INDR_IDR11                        ((uint16_t)0x0800)            /* Port input data, bit 11 */
+#define GPIO_INDR_IDR12                        ((uint16_t)0x1000)            /* Port input data, bit 12 */
+#define GPIO_INDR_IDR13                        ((uint16_t)0x2000)            /* Port input data, bit 13 */
+#define GPIO_INDR_IDR14                        ((uint16_t)0x4000)            /* Port input data, bit 14 */
+#define GPIO_INDR_IDR15                        ((uint16_t)0x8000)            /* Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_OUTDR register  *******************/
+#define GPIO_OUTDR_ODR0                        ((uint16_t)0x0001)            /* Port output data, bit 0 */
+#define GPIO_OUTDR_ODR1                        ((uint16_t)0x0002)            /* Port output data, bit 1 */
+#define GPIO_OUTDR_ODR2                        ((uint16_t)0x0004)            /* Port output data, bit 2 */
+#define GPIO_OUTDR_ODR3                        ((uint16_t)0x0008)            /* Port output data, bit 3 */
+#define GPIO_OUTDR_ODR4                        ((uint16_t)0x0010)            /* Port output data, bit 4 */
+#define GPIO_OUTDR_ODR5                        ((uint16_t)0x0020)            /* Port output data, bit 5 */
+#define GPIO_OUTDR_ODR6                        ((uint16_t)0x0040)            /* Port output data, bit 6 */
+#define GPIO_OUTDR_ODR7                        ((uint16_t)0x0080)            /* Port output data, bit 7 */
+#define GPIO_OUTDR_ODR8                        ((uint16_t)0x0100)            /* Port output data, bit 8 */
+#define GPIO_OUTDR_ODR9                        ((uint16_t)0x0200)            /* Port output data, bit 9 */
+#define GPIO_OUTDR_ODR10                       ((uint16_t)0x0400)            /* Port output data, bit 10 */
+#define GPIO_OUTDR_ODR11                       ((uint16_t)0x0800)            /* Port output data, bit 11 */
+#define GPIO_OUTDR_ODR12                       ((uint16_t)0x1000)            /* Port output data, bit 12 */
+#define GPIO_OUTDR_ODR13                       ((uint16_t)0x2000)            /* Port output data, bit 13 */
+#define GPIO_OUTDR_ODR14                       ((uint16_t)0x4000)            /* Port output data, bit 14 */
+#define GPIO_OUTDR_ODR15                       ((uint16_t)0x8000)            /* Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSHR register  *******************/
+#define GPIO_BSHR_BS0                          ((uint32_t)0x00000001)        /* Port x Set bit 0 */
+#define GPIO_BSHR_BS1                          ((uint32_t)0x00000002)        /* Port x Set bit 1 */
+#define GPIO_BSHR_BS2                          ((uint32_t)0x00000004)        /* Port x Set bit 2 */
+#define GPIO_BSHR_BS3                          ((uint32_t)0x00000008)        /* Port x Set bit 3 */
+#define GPIO_BSHR_BS4                          ((uint32_t)0x00000010)        /* Port x Set bit 4 */
+#define GPIO_BSHR_BS5                          ((uint32_t)0x00000020)        /* Port x Set bit 5 */
+#define GPIO_BSHR_BS6                          ((uint32_t)0x00000040)        /* Port x Set bit 6 */
+#define GPIO_BSHR_BS7                          ((uint32_t)0x00000080)        /* Port x Set bit 7 */
+#define GPIO_BSHR_BS8                          ((uint32_t)0x00000100)        /* Port x Set bit 8 */
+#define GPIO_BSHR_BS9                          ((uint32_t)0x00000200)        /* Port x Set bit 9 */
+#define GPIO_BSHR_BS10                         ((uint32_t)0x00000400)        /* Port x Set bit 10 */
+#define GPIO_BSHR_BS11                         ((uint32_t)0x00000800)        /* Port x Set bit 11 */
+#define GPIO_BSHR_BS12                         ((uint32_t)0x00001000)        /* Port x Set bit 12 */
+#define GPIO_BSHR_BS13                         ((uint32_t)0x00002000)        /* Port x Set bit 13 */
+#define GPIO_BSHR_BS14                         ((uint32_t)0x00004000)        /* Port x Set bit 14 */
+#define GPIO_BSHR_BS15                         ((uint32_t)0x00008000)        /* Port x Set bit 15 */
+
+#define GPIO_BSHR_BR0                          ((uint32_t)0x00010000)        /* Port x Reset bit 0 */
+#define GPIO_BSHR_BR1                          ((uint32_t)0x00020000)        /* Port x Reset bit 1 */
+#define GPIO_BSHR_BR2                          ((uint32_t)0x00040000)        /* Port x Reset bit 2 */
+#define GPIO_BSHR_BR3                          ((uint32_t)0x00080000)        /* Port x Reset bit 3 */
+#define GPIO_BSHR_BR4                          ((uint32_t)0x00100000)        /* Port x Reset bit 4 */
+#define GPIO_BSHR_BR5                          ((uint32_t)0x00200000)        /* Port x Reset bit 5 */
+#define GPIO_BSHR_BR6                          ((uint32_t)0x00400000)        /* Port x Reset bit 6 */
+#define GPIO_BSHR_BR7                          ((uint32_t)0x00800000)        /* Port x Reset bit 7 */
+#define GPIO_BSHR_BR8                          ((uint32_t)0x01000000)        /* Port x Reset bit 8 */
+#define GPIO_BSHR_BR9                          ((uint32_t)0x02000000)        /* Port x Reset bit 9 */
+#define GPIO_BSHR_BR10                         ((uint32_t)0x04000000)        /* Port x Reset bit 10 */
+#define GPIO_BSHR_BR11                         ((uint32_t)0x08000000)        /* Port x Reset bit 11 */
+#define GPIO_BSHR_BR12                         ((uint32_t)0x10000000)        /* Port x Reset bit 12 */
+#define GPIO_BSHR_BR13                         ((uint32_t)0x20000000)        /* Port x Reset bit 13 */
+#define GPIO_BSHR_BR14                         ((uint32_t)0x40000000)        /* Port x Reset bit 14 */
+#define GPIO_BSHR_BR15                         ((uint32_t)0x80000000)        /* Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BCR register  *******************/
+#define GPIO_BCR_BR0                           ((uint16_t)0x0001)            /* Port x Reset bit 0 */
+#define GPIO_BCR_BR1                           ((uint16_t)0x0002)            /* Port x Reset bit 1 */
+#define GPIO_BCR_BR2                           ((uint16_t)0x0004)            /* Port x Reset bit 2 */
+#define GPIO_BCR_BR3                           ((uint16_t)0x0008)            /* Port x Reset bit 3 */
+#define GPIO_BCR_BR4                           ((uint16_t)0x0010)            /* Port x Reset bit 4 */
+#define GPIO_BCR_BR5                           ((uint16_t)0x0020)            /* Port x Reset bit 5 */
+#define GPIO_BCR_BR6                           ((uint16_t)0x0040)            /* Port x Reset bit 6 */
+#define GPIO_BCR_BR7                           ((uint16_t)0x0080)            /* Port x Reset bit 7 */
+#define GPIO_BCR_BR8                           ((uint16_t)0x0100)            /* Port x Reset bit 8 */
+#define GPIO_BCR_BR9                           ((uint16_t)0x0200)            /* Port x Reset bit 9 */
+#define GPIO_BCR_BR10                          ((uint16_t)0x0400)            /* Port x Reset bit 10 */
+#define GPIO_BCR_BR11                          ((uint16_t)0x0800)            /* Port x Reset bit 11 */
+#define GPIO_BCR_BR12                          ((uint16_t)0x1000)            /* Port x Reset bit 12 */
+#define GPIO_BCR_BR13                          ((uint16_t)0x2000)            /* Port x Reset bit 13 */
+#define GPIO_BCR_BR14                          ((uint16_t)0x4000)            /* Port x Reset bit 14 */
+#define GPIO_BCR_BR15                          ((uint16_t)0x8000)            /* Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCK0                              ((uint32_t)0x00000001)        /* Port x Lock bit 0 */
+#define GPIO_LCK1                              ((uint32_t)0x00000002)        /* Port x Lock bit 1 */
+#define GPIO_LCK2                              ((uint32_t)0x00000004)        /* Port x Lock bit 2 */
+#define GPIO_LCK3                              ((uint32_t)0x00000008)        /* Port x Lock bit 3 */
+#define GPIO_LCK4                              ((uint32_t)0x00000010)        /* Port x Lock bit 4 */
+#define GPIO_LCK5                              ((uint32_t)0x00000020)        /* Port x Lock bit 5 */
+#define GPIO_LCK6                              ((uint32_t)0x00000040)        /* Port x Lock bit 6 */
+#define GPIO_LCK7                              ((uint32_t)0x00000080)        /* Port x Lock bit 7 */
+#define GPIO_LCK8                              ((uint32_t)0x00000100)        /* Port x Lock bit 8 */
+#define GPIO_LCK9                              ((uint32_t)0x00000200)        /* Port x Lock bit 9 */
+#define GPIO_LCK10                             ((uint32_t)0x00000400)        /* Port x Lock bit 10 */
+#define GPIO_LCK11                             ((uint32_t)0x00000800)        /* Port x Lock bit 11 */
+#define GPIO_LCK12                             ((uint32_t)0x00001000)        /* Port x Lock bit 12 */
+#define GPIO_LCK13                             ((uint32_t)0x00002000)        /* Port x Lock bit 13 */
+#define GPIO_LCK14                             ((uint32_t)0x00004000)        /* Port x Lock bit 14 */
+#define GPIO_LCK15                             ((uint32_t)0x00008000)        /* Port x Lock bit 15 */
+#define GPIO_LCKK                              ((uint32_t)0x00010000)        /* Lock key */
+
+
+/******************  Bit definition for AFIO_ECR register  *******************/
+#define AFIO_ECR_PIN                           ((uint8_t)0x0F)               /* PIN[3:0] bits (Pin selection) */
+#define AFIO_ECR_PIN_0                         ((uint8_t)0x01)               /* Bit 0 */
+#define AFIO_ECR_PIN_1                         ((uint8_t)0x02)               /* Bit 1 */
+#define AFIO_ECR_PIN_2                         ((uint8_t)0x04)               /* Bit 2 */
+#define AFIO_ECR_PIN_3                         ((uint8_t)0x08)               /* Bit 3 */
+
+#define AFIO_ECR_PIN_PX0                       ((uint8_t)0x00)               /* Pin 0 selected */
+#define AFIO_ECR_PIN_PX1                       ((uint8_t)0x01)               /* Pin 1 selected */
+#define AFIO_ECR_PIN_PX2                       ((uint8_t)0x02)               /* Pin 2 selected */
+#define AFIO_ECR_PIN_PX3                       ((uint8_t)0x03)               /* Pin 3 selected */
+#define AFIO_ECR_PIN_PX4                       ((uint8_t)0x04)               /* Pin 4 selected */
+#define AFIO_ECR_PIN_PX5                       ((uint8_t)0x05)               /* Pin 5 selected */
+#define AFIO_ECR_PIN_PX6                       ((uint8_t)0x06)               /* Pin 6 selected */
+#define AFIO_ECR_PIN_PX7                       ((uint8_t)0x07)               /* Pin 7 selected */
+#define AFIO_ECR_PIN_PX8                       ((uint8_t)0x08)               /* Pin 8 selected */
+#define AFIO_ECR_PIN_PX9                       ((uint8_t)0x09)               /* Pin 9 selected */
+#define AFIO_ECR_PIN_PX10                      ((uint8_t)0x0A)               /* Pin 10 selected */
+#define AFIO_ECR_PIN_PX11                      ((uint8_t)0x0B)               /* Pin 11 selected */
+#define AFIO_ECR_PIN_PX12                      ((uint8_t)0x0C)               /* Pin 12 selected */
+#define AFIO_ECR_PIN_PX13                      ((uint8_t)0x0D)               /* Pin 13 selected */
+#define AFIO_ECR_PIN_PX14                      ((uint8_t)0x0E)               /* Pin 14 selected */
+#define AFIO_ECR_PIN_PX15                      ((uint8_t)0x0F)               /* Pin 15 selected */
+
+#define AFIO_ECR_PORT                          ((uint8_t)0x70)               /* PORT[2:0] bits (Port selection) */
+#define AFIO_ECR_PORT_0                        ((uint8_t)0x10)               /* Bit 0 */
+#define AFIO_ECR_PORT_1                        ((uint8_t)0x20)               /* Bit 1 */
+#define AFIO_ECR_PORT_2                        ((uint8_t)0x40)               /* Bit 2 */
+
+#define AFIO_ECR_PORT_PA                       ((uint8_t)0x00)               /* Port A selected */
+#define AFIO_ECR_PORT_PB                       ((uint8_t)0x10)               /* Port B selected */
+#define AFIO_ECR_PORT_PC                       ((uint8_t)0x20)               /* Port C selected */
+#define AFIO_ECR_PORT_PD                       ((uint8_t)0x30)               /* Port D selected */
+#define AFIO_ECR_PORT_PE                       ((uint8_t)0x40)               /* Port E selected */
+
+#define AFIO_ECR_EVOE                          ((uint8_t)0x80)               /* Event Output Enable */
+
+/******************  Bit definition for AFIO_PCFR1register  *******************/
+#define AFIO_PCFR1_SPI1_REMAP                  ((uint32_t)0x00000001)        /* SPI1 remapping */
+#define AFIO_PCFR1_I2C1_REMAP                  ((uint32_t)0x00000002)        /* I2C1 remapping */
+#define AFIO_PCFR1_USART1_REMAP                ((uint32_t)0x00000004)        /* USART1 remapping */
+#define AFIO_PCFR1_USART2_REMAP                ((uint32_t)0x00000008)        /* USART2 remapping */
+
+#define AFIO_PCFR1_USART3_REMAP                ((uint32_t)0x00000030)        /* USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_PCFR1_USART3_REMAP_0              ((uint32_t)0x00000010)        /* Bit 0 */
+#define AFIO_PCFR1_USART3_REMAP_1              ((uint32_t)0x00000020)        /* Bit 1 */
+
+#define AFIO_PCFR1_USART3_REMAP_NOREMAP        ((uint32_t)0x00000000)        /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP   ((uint32_t)0x00000010)        /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_FULLREMAP      ((uint32_t)0x00000030)        /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_PCFR1_TIM1_REMAP                  ((uint32_t)0x000000C0)        /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_PCFR1_TIM1_REMAP_0                ((uint32_t)0x00000040)        /* Bit 0 */
+#define AFIO_PCFR1_TIM1_REMAP_1                ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define AFIO_PCFR1_TIM1_REMAP_NOREMAP          ((uint32_t)0x00000000)        /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP     ((uint32_t)0x00000040)        /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP        ((uint32_t)0x000000C0)        /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_PCFR1_TIM2_REMAP                  ((uint32_t)0x00000300)        /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_PCFR1_TIM2_REMAP_0                ((uint32_t)0x00000100)        /* Bit 0 */
+#define AFIO_PCFR1_TIM2_REMAP_1                ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define AFIO_PCFR1_TIM2_REMAP_NOREMAP          ((uint32_t)0x00000000)        /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1    ((uint32_t)0x00000100)        /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2    ((uint32_t)0x00000200)        /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP        ((uint32_t)0x00000300)        /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_PCFR1_TIM3_REMAP                  ((uint32_t)0x00000C00)        /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_PCFR1_TIM3_REMAP_0                ((uint32_t)0x00000400)        /* Bit 0 */
+#define AFIO_PCFR1_TIM3_REMAP_1                ((uint32_t)0x00000800)        /* Bit 1 */
+
+#define AFIO_PCFR1_TIM3_REMAP_NOREMAP          ((uint32_t)0x00000000)        /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP     ((uint32_t)0x00000800)        /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP        ((uint32_t)0x00000C00)        /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_PCFR1_TIM4_REMAP                  ((uint32_t)0x00001000)        /* TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_PCFR1_CAN_REMAP                   ((uint32_t)0x00006000)        /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_PCFR1_CAN_REMAP_0                 ((uint32_t)0x00002000)        /* Bit 0 */
+#define AFIO_PCFR1_CAN_REMAP_1                 ((uint32_t)0x00004000)        /* Bit 1 */
+
+#define AFIO_PCFR1_CAN_REMAP_REMAP1            ((uint32_t)0x00000000)        /* CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP2            ((uint32_t)0x00004000)        /* CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP3            ((uint32_t)0x00006000)        /* CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_PCFR1_PD01_REMAP                  ((uint32_t)0x00008000)        /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCFR1_TIM5CH4_IREMAP              ((uint32_t)0x00010000)        /* TIM5 Channel4 Internal Remap */
+#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP          ((uint32_t)0x00020000)        /* ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC1_ETRGREG_REMAP          ((uint32_t)0x00040000)        /* ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP          ((uint32_t)0x00080000)        /* ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGREG_REMAP          ((uint32_t)0x00100000)        /* ADC 2 External Trigger Regular Conversion remapping */
+
+#define AFIO_PCFR1_SWJ_CFG                     ((uint32_t)0x07000000)        /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_PCFR1_SWJ_CFG_0                   ((uint32_t)0x01000000)        /* Bit 0 */
+#define AFIO_PCFR1_SWJ_CFG_1                   ((uint32_t)0x02000000)        /* Bit 1 */
+#define AFIO_PCFR1_SWJ_CFG_2                   ((uint32_t)0x04000000)        /* Bit 2 */
+
+#define AFIO_PCFR1_SWJ_CFG_RESET               ((uint32_t)0x00000000)        /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_PCFR1_SWJ_CFG_NOJNTRST            ((uint32_t)0x01000000)        /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE         ((uint32_t)0x02000000)        /* JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_PCFR1_SWJ_CFG_DISABLE             ((uint32_t)0x04000000)        /* JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                     ((uint16_t)0x000F)            /* EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                     ((uint16_t)0x00F0)            /* EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                     ((uint16_t)0x0F00)            /* EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                     ((uint16_t)0xF000)            /* EXTI 3 configuration */
+
+#define AFIO_EXTICR1_EXTI0_PA                  ((uint16_t)0x0000)            /* PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                  ((uint16_t)0x0001)            /* PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                  ((uint16_t)0x0002)            /* PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                  ((uint16_t)0x0003)            /* PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                  ((uint16_t)0x0004)            /* PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                  ((uint16_t)0x0005)            /* PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                  ((uint16_t)0x0006)            /* PG[0] pin */
+
+#define AFIO_EXTICR1_EXTI1_PA                  ((uint16_t)0x0000)            /* PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                  ((uint16_t)0x0010)            /* PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                  ((uint16_t)0x0020)            /* PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                  ((uint16_t)0x0030)            /* PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                  ((uint16_t)0x0040)            /* PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                  ((uint16_t)0x0050)            /* PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                  ((uint16_t)0x0060)            /* PG[1] pin */
+ 
+#define AFIO_EXTICR1_EXTI2_PA                  ((uint16_t)0x0000)            /* PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                  ((uint16_t)0x0100)            /* PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                  ((uint16_t)0x0200)            /* PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                  ((uint16_t)0x0300)            /* PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                  ((uint16_t)0x0400)            /* PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                  ((uint16_t)0x0500)            /* PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                  ((uint16_t)0x0600)            /* PG[2] pin */
+
+#define AFIO_EXTICR1_EXTI3_PA                  ((uint16_t)0x0000)            /* PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                  ((uint16_t)0x1000)            /* PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                  ((uint16_t)0x2000)            /* PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                  ((uint16_t)0x3000)            /* PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                  ((uint16_t)0x4000)            /* PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                  ((uint16_t)0x5000)            /* PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                  ((uint16_t)0x6000)            /* PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                     ((uint16_t)0x000F)            /* EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                     ((uint16_t)0x00F0)            /* EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                     ((uint16_t)0x0F00)            /* EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                     ((uint16_t)0xF000)            /* EXTI 7 configuration */
+
+#define AFIO_EXTICR2_EXTI4_PA                  ((uint16_t)0x0000)            /* PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                  ((uint16_t)0x0001)            /* PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                  ((uint16_t)0x0002)            /* PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                  ((uint16_t)0x0003)            /* PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                  ((uint16_t)0x0004)            /* PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                  ((uint16_t)0x0005)            /* PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                  ((uint16_t)0x0006)            /* PG[4] pin */
+
+#define AFIO_EXTICR2_EXTI5_PA                  ((uint16_t)0x0000)            /* PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                  ((uint16_t)0x0010)            /* PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                  ((uint16_t)0x0020)            /* PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                  ((uint16_t)0x0030)            /* PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                  ((uint16_t)0x0040)            /* PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                  ((uint16_t)0x0050)            /* PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                  ((uint16_t)0x0060)            /* PG[5] pin */
+
+#define AFIO_EXTICR2_EXTI6_PA                  ((uint16_t)0x0000)            /* PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                  ((uint16_t)0x0100)            /* PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                  ((uint16_t)0x0200)            /* PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                  ((uint16_t)0x0300)            /* PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                  ((uint16_t)0x0400)            /* PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                  ((uint16_t)0x0500)            /* PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                  ((uint16_t)0x0600)            /* PG[6] pin */
+
+#define AFIO_EXTICR2_EXTI7_PA                  ((uint16_t)0x0000)            /* PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                  ((uint16_t)0x1000)            /* PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                  ((uint16_t)0x2000)            /* PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                  ((uint16_t)0x3000)            /* PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                  ((uint16_t)0x4000)            /* PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                  ((uint16_t)0x5000)            /* PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                  ((uint16_t)0x6000)            /* PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                     ((uint16_t)0x000F)            /* EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                     ((uint16_t)0x00F0)            /* EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                    ((uint16_t)0x0F00)            /* EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                    ((uint16_t)0xF000)            /* EXTI 11 configuration */
+
+#define AFIO_EXTICR3_EXTI8_PA                  ((uint16_t)0x0000)            /* PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                  ((uint16_t)0x0001)            /* PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                  ((uint16_t)0x0002)            /* PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                  ((uint16_t)0x0003)            /* PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                  ((uint16_t)0x0004)            /* PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                  ((uint16_t)0x0005)            /* PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                  ((uint16_t)0x0006)            /* PG[8] pin */
+
+#define AFIO_EXTICR3_EXTI9_PA                  ((uint16_t)0x0000)            /* PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                  ((uint16_t)0x0010)            /* PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                  ((uint16_t)0x0020)            /* PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                  ((uint16_t)0x0030)            /* PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                  ((uint16_t)0x0040)            /* PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                  ((uint16_t)0x0050)            /* PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                  ((uint16_t)0x0060)            /* PG[9] pin */
+ 
+#define AFIO_EXTICR3_EXTI10_PA                 ((uint16_t)0x0000)            /* PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB                 ((uint16_t)0x0100)            /* PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC                 ((uint16_t)0x0200)            /* PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD                 ((uint16_t)0x0300)            /* PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE                 ((uint16_t)0x0400)            /* PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF                 ((uint16_t)0x0500)            /* PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG                 ((uint16_t)0x0600)            /* PG[10] pin */
+
+#define AFIO_EXTICR3_EXTI11_PA                 ((uint16_t)0x0000)            /* PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB                 ((uint16_t)0x1000)            /* PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC                 ((uint16_t)0x2000)            /* PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD                 ((uint16_t)0x3000)            /* PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE                 ((uint16_t)0x4000)            /* PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF                 ((uint16_t)0x5000)            /* PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG                 ((uint16_t)0x6000)            /* PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                    ((uint16_t)0x000F)            /* EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                    ((uint16_t)0x00F0)            /* EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                    ((uint16_t)0x0F00)            /* EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                    ((uint16_t)0xF000)            /* EXTI 15 configuration */
+
+#define AFIO_EXTICR4_EXTI12_PA                 ((uint16_t)0x0000)            /* PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB                 ((uint16_t)0x0001)            /* PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC                 ((uint16_t)0x0002)            /* PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD                 ((uint16_t)0x0003)            /* PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE                 ((uint16_t)0x0004)            /* PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF                 ((uint16_t)0x0005)            /* PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG                 ((uint16_t)0x0006)            /* PG[12] pin */
+
+#define AFIO_EXTICR4_EXTI13_PA                 ((uint16_t)0x0000)            /* PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB                 ((uint16_t)0x0010)            /* PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC                 ((uint16_t)0x0020)            /* PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD                 ((uint16_t)0x0030)            /* PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE                 ((uint16_t)0x0040)            /* PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF                 ((uint16_t)0x0050)            /* PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG                 ((uint16_t)0x0060)            /* PG[13] pin */
+
+#define AFIO_EXTICR4_EXTI14_PA                 ((uint16_t)0x0000)            /* PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB                 ((uint16_t)0x0100)            /* PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC                 ((uint16_t)0x0200)            /* PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD                 ((uint16_t)0x0300)            /* PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE                 ((uint16_t)0x0400)            /* PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF                 ((uint16_t)0x0500)            /* PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG                 ((uint16_t)0x0600)            /* PG[14] pin */
+
+#define AFIO_EXTICR4_EXTI15_PA                 ((uint16_t)0x0000)            /* PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB                 ((uint16_t)0x1000)            /* PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC                 ((uint16_t)0x2000)            /* PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD                 ((uint16_t)0x3000)            /* PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE                 ((uint16_t)0x4000)            /* PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF                 ((uint16_t)0x5000)            /* PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG                 ((uint16_t)0x6000)            /* PG[15] pin */
+
+/******************************************************************************/
+/*                           Independent WATCHDOG                             */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_CTLR register  ********************/
+#define  IWDG_KEY                              ((uint16_t)0xFFFF)            /* Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PSCR register  ********************/
+#define  IWDG_PR                               ((uint8_t)0x07)               /* PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_0                             ((uint8_t)0x01)               /* Bit 0 */
+#define  IWDG_PR_1                             ((uint8_t)0x02)               /* Bit 1 */
+#define  IWDG_PR_2                             ((uint8_t)0x04)               /* Bit 2 */
+
+/*******************  Bit definition for IWDG_RLDR register  *******************/
+#define  IWDG_RL                               ((uint16_t)0x0FFF)            /* Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STATR register  ********************/
+#define  IWDG_PVU                              ((uint8_t)0x01)               /* Watchdog prescaler value update */
+#define  IWDG_RVU                              ((uint8_t)0x02)               /* Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                      Inter-integrated Circuit Interface                    */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTLR1 register  ********************/
+#define  I2C_CTLR1_PE                          ((uint16_t)0x0001)            /* Peripheral Enable */
+#define  I2C_CTLR1_SMBUS                       ((uint16_t)0x0002)            /* SMBus Mode */
+#define  I2C_CTLR1_SMBTYPE                     ((uint16_t)0x0008)            /* SMBus Type */
+#define  I2C_CTLR1_ENARP                       ((uint16_t)0x0010)            /* ARP Enable */
+#define  I2C_CTLR1_ENPEC                       ((uint16_t)0x0020)            /* PEC Enable */
+#define  I2C_CTLR1_ENGC                        ((uint16_t)0x0040)            /* General Call Enable */
+#define  I2C_CTLR1_NOSTRETCH                   ((uint16_t)0x0080)            /* Clock Stretching Disable (Slave mode) */
+#define  I2C_CTLR1_START                       ((uint16_t)0x0100)            /* Start Generation */
+#define  I2C_CTLR1_STOP                        ((uint16_t)0x0200)            /* Stop Generation */
+#define  I2C_CTLR1_ACK                         ((uint16_t)0x0400)            /* Acknowledge Enable */
+#define  I2C_CTLR1_POS                         ((uint16_t)0x0800)            /* Acknowledge/PEC Position (for data reception) */
+#define  I2C_CTLR1_PEC                         ((uint16_t)0x1000)            /* Packet Error Checking */
+#define  I2C_CTLR1_ALERT                       ((uint16_t)0x2000)            /* SMBus Alert */
+#define  I2C_CTLR1_SWRST                       ((uint16_t)0x8000)            /* Software Reset */
+
+/*******************  Bit definition for I2C_CTLR2 register  ********************/
+#define  I2C_CTLR2_FREQ                        ((uint16_t)0x003F)            /* FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CTLR2_FREQ_0                      ((uint16_t)0x0001)            /* Bit 0 */
+#define  I2C_CTLR2_FREQ_1                      ((uint16_t)0x0002)            /* Bit 1 */
+#define  I2C_CTLR2_FREQ_2                      ((uint16_t)0x0004)            /* Bit 2 */
+#define  I2C_CTLR2_FREQ_3                      ((uint16_t)0x0008)            /* Bit 3 */
+#define  I2C_CTLR2_FREQ_4                      ((uint16_t)0x0010)            /* Bit 4 */
+#define  I2C_CTLR2_FREQ_5                      ((uint16_t)0x0020)            /* Bit 5 */
+
+#define  I2C_CTLR2_ITERREN                     ((uint16_t)0x0100)            /* Error Interrupt Enable */
+#define  I2C_CTLR2_ITEVTEN                     ((uint16_t)0x0200)            /* Event Interrupt Enable */
+#define  I2C_CTLR2_ITBUFEN                     ((uint16_t)0x0400)            /* Buffer Interrupt Enable */
+#define  I2C_CTLR2_DMAEN                       ((uint16_t)0x0800)            /* DMA Requests Enable */
+#define  I2C_CTLR2_LAST                        ((uint16_t)0x1000)            /* DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define  I2C_OADDR1_ADD1_7                     ((uint16_t)0x00FE)            /* Interface Address */
+#define  I2C_OADDR1_ADD8_9                     ((uint16_t)0x0300)            /* Interface Address */
+
+#define  I2C_OADDR1_ADD0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  I2C_OADDR1_ADD1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  I2C_OADDR1_ADD2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  I2C_OADDR1_ADD3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  I2C_OADDR1_ADD4                       ((uint16_t)0x0010)            /* Bit 4 */
+#define  I2C_OADDR1_ADD5                       ((uint16_t)0x0020)            /* Bit 5 */
+#define  I2C_OADDR1_ADD6                       ((uint16_t)0x0040)            /* Bit 6 */
+#define  I2C_OADDR1_ADD7                       ((uint16_t)0x0080)            /* Bit 7 */
+#define  I2C_OADDR1_ADD8                       ((uint16_t)0x0100)            /* Bit 8 */
+#define  I2C_OADDR1_ADD9                       ((uint16_t)0x0200)            /* Bit 9 */
+
+#define  I2C_OADDR1_ADDMODE                    ((uint16_t)0x8000)            /* Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define  I2C_OADDR2_ENDUAL                     ((uint8_t)0x01)               /* Dual addressing mode enable */
+#define  I2C_OADDR2_ADD2                       ((uint8_t)0xFE)               /* Interface address */
+
+/********************  Bit definition for I2C_DATAR register  ********************/
+#define  I2C_DR_DATAR                          ((uint8_t)0xFF)               /* 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STAR1 register  ********************/
+#define  I2C_STAR1_SB                          ((uint16_t)0x0001)            /* Start Bit (Master mode) */
+#define  I2C_STAR1_ADDR                        ((uint16_t)0x0002)            /* Address sent (master mode)/matched (slave mode) */
+#define  I2C_STAR1_BTF                         ((uint16_t)0x0004)            /* Byte Transfer Finished */
+#define  I2C_STAR1_ADD10                       ((uint16_t)0x0008)            /* 10-bit header sent (Master mode) */
+#define  I2C_STAR1_STOPF                       ((uint16_t)0x0010)            /* Stop detection (Slave mode) */
+#define  I2C_STAR1_RXNE                        ((uint16_t)0x0040)            /* Data Register not Empty (receivers) */
+#define  I2C_STAR1_TXE                         ((uint16_t)0x0080)            /* Data Register Empty (transmitters) */
+#define  I2C_STAR1_BERR                        ((uint16_t)0x0100)            /* Bus Error */
+#define  I2C_STAR1_ARLO                        ((uint16_t)0x0200)            /* Arbitration Lost (master mode) */
+#define  I2C_STAR1_AF                          ((uint16_t)0x0400)            /* Acknowledge Failure */
+#define  I2C_STAR1_OVR                         ((uint16_t)0x0800)            /* Overrun/Underrun */
+#define  I2C_STAR1_PECERR                      ((uint16_t)0x1000)            /* PEC Error in reception */
+#define  I2C_STAR1_TIMEOUT                     ((uint16_t)0x4000)            /* Timeout or Tlow Error */
+#define  I2C_STAR1_SMBALERT                    ((uint16_t)0x8000)            /* SMBus Alert */
+
+/*******************  Bit definition for I2C_STAR2 register  ********************/
+#define  I2C_STAR2_MSL                         ((uint16_t)0x0001)            /* Master/Slave */
+#define  I2C_STAR2_BUSY                        ((uint16_t)0x0002)            /* Bus Busy */
+#define  I2C_STAR2_TRA                         ((uint16_t)0x0004)            /* Transmitter/Receiver */
+#define  I2C_STAR2_GENCALL                     ((uint16_t)0x0010)            /* General Call Address (Slave mode) */
+#define  I2C_STAR2_SMBDEFAULT                  ((uint16_t)0x0020)            /* SMBus Device Default Address (Slave mode) */
+#define  I2C_STAR2_SMBHOST                     ((uint16_t)0x0040)            /* SMBus Host Header (Slave mode) */
+#define  I2C_STAR2_DUALF                       ((uint16_t)0x0080)            /* Dual Flag (Slave mode) */
+#define  I2C_STAR2_PEC                         ((uint16_t)0xFF00)            /* Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CKCFGR register  ********************/
+#define  I2C_CKCFGR_CCR                        ((uint16_t)0x0FFF)            /* Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CKCFGR_DUTY                       ((uint16_t)0x4000)            /* Fast Mode Duty Cycle */
+#define  I2C_CKCFGR_FS                         ((uint16_t)0x8000)            /* I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_RTR register  *******************/
+#define  I2C_RTR_TRISE                         ((uint8_t)0x3F)               /* Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+
+/******************************************************************************/
+/*                             Power Control                                  */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CTLR register  ********************/
+#define  PWR_CTLR_LPDS                         ((uint16_t)0x0001)     /* Low-Power Deepsleep */
+#define  PWR_CTLR_PDDS                         ((uint16_t)0x0002)     /* Power Down Deepsleep */
+#define  PWR_CTLR_CWUF                         ((uint16_t)0x0004)     /* Clear Wakeup Flag */
+#define  PWR_CTLR_CSBF                         ((uint16_t)0x0008)     /* Clear Standby Flag */
+#define  PWR_CTLR_PVDE                         ((uint16_t)0x0010)     /* Power Voltage Detector Enable */
+
+#define  PWR_CTLR_PLS                          ((uint16_t)0x00E0)     /* PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CTLR_PLS_0                        ((uint16_t)0x0020)     /* Bit 0 */
+#define  PWR_CTLR_PLS_1                        ((uint16_t)0x0040)     /* Bit 1 */
+#define  PWR_CTLR_PLS_2                        ((uint16_t)0x0080)     /* Bit 2 */
+
+#define  PWR_CTLR_PLS_2V2                      ((uint16_t)0x0000)     /* PVD level 2.2V */
+#define  PWR_CTLR_PLS_2V3                      ((uint16_t)0x0020)     /* PVD level 2.3V */
+#define  PWR_CTLR_PLS_2V4                      ((uint16_t)0x0040)     /* PVD level 2.4V */
+#define  PWR_CTLR_PLS_2V5                      ((uint16_t)0x0060)     /* PVD level 2.5V */
+#define  PWR_CTLR_PLS_2V6                      ((uint16_t)0x0080)     /* PVD level 2.6V */
+#define  PWR_CTLR_PLS_2V7                      ((uint16_t)0x00A0)     /* PVD level 2.7V */
+#define  PWR_CTLR_PLS_2V8                      ((uint16_t)0x00C0)     /* PVD level 2.8V */
+#define  PWR_CTLR_PLS_2V9                      ((uint16_t)0x00E0)     /* PVD level 2.9V */
+
+#define  PWR_CTLR_DBP                          ((uint16_t)0x0100)     /* Disable Backup Domain write protection */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                           ((uint16_t)0x0001)     /* Wakeup Flag */
+#define  PWR_CSR_SBF                           ((uint16_t)0x0002)     /* Standby Flag */
+#define  PWR_CSR_PVDO                          ((uint16_t)0x0004)     /* PVD Output */
+#define  PWR_CSR_EWUP                          ((uint16_t)0x0100)     /* Enable WKUP pin */
+
+
+
+/******************************************************************************/
+/*                         Reset and Clock Control                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTLR register  ********************/
+#define  RCC_HSION                       ((uint32_t)0x00000001)        /* Internal High Speed clock enable */
+#define  RCC_HSIRDY                      ((uint32_t)0x00000002)        /* Internal High Speed clock ready flag */
+#define  RCC_HSITRIM                     ((uint32_t)0x000000F8)        /* Internal High Speed clock trimming */
+#define  RCC_HSICAL                      ((uint32_t)0x0000FF00)        /* Internal High Speed clock Calibration */
+#define  RCC_HSEON                       ((uint32_t)0x00010000)        /* External High Speed clock enable */
+#define  RCC_HSERDY                      ((uint32_t)0x00020000)        /* External High Speed clock ready flag */
+#define  RCC_HSEBYP                      ((uint32_t)0x00040000)        /* External High Speed clock Bypass */
+#define  RCC_CSSON                       ((uint32_t)0x00080000)        /* Clock Security System enable */
+#define  RCC_PLLON                       ((uint32_t)0x01000000)        /* PLL enable */
+#define  RCC_PLLRDY                      ((uint32_t)0x02000000)        /* PLL clock ready flag */
+
+
+/*******************  Bit definition for RCC_CFGR0 register  *******************/
+#define  RCC_SW                          ((uint32_t)0x00000003)        /* SW[1:0] bits (System clock Switch) */
+#define  RCC_SW_0                        ((uint32_t)0x00000001)        /* Bit 0 */
+#define  RCC_SW_1                        ((uint32_t)0x00000002)        /* Bit 1 */
+
+#define  RCC_SW_HSI                      ((uint32_t)0x00000000)        /* HSI selected as system clock */
+#define  RCC_SW_HSE                      ((uint32_t)0x00000001)        /* HSE selected as system clock */
+#define  RCC_SW_PLL                      ((uint32_t)0x00000002)        /* PLL selected as system clock */
+
+#define  RCC_SWS                         ((uint32_t)0x0000000C)        /* SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_SWS_0                       ((uint32_t)0x00000004)        /* Bit 0 */
+#define  RCC_SWS_1                       ((uint32_t)0x00000008)        /* Bit 1 */
+
+#define  RCC_SWS_HSI                     ((uint32_t)0x00000000)        /* HSI oscillator used as system clock */
+#define  RCC_SWS_HSE                     ((uint32_t)0x00000004)        /* HSE oscillator used as system clock */
+#define  RCC_SWS_PLL                     ((uint32_t)0x00000008)        /* PLL used as system clock */
+
+#define  RCC_HPRE                        ((uint32_t)0x000000F0)        /* HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_HPRE_0                      ((uint32_t)0x00000010)        /* Bit 0 */
+#define  RCC_HPRE_1                      ((uint32_t)0x00000020)        /* Bit 1 */
+#define  RCC_HPRE_2                      ((uint32_t)0x00000040)        /* Bit 2 */
+#define  RCC_HPRE_3                      ((uint32_t)0x00000080)        /* Bit 3 */
+
+#define  RCC_HPRE_DIV1                   ((uint32_t)0x00000000)        /* SYSCLK not divided */
+#define  RCC_HPRE_DIV2                   ((uint32_t)0x00000080)        /* SYSCLK divided by 2 */
+#define  RCC_HPRE_DIV4                   ((uint32_t)0x00000090)        /* SYSCLK divided by 4 */
+#define  RCC_HPRE_DIV8                   ((uint32_t)0x000000A0)        /* SYSCLK divided by 8 */
+#define  RCC_HPRE_DIV16                  ((uint32_t)0x000000B0)        /* SYSCLK divided by 16 */
+#define  RCC_HPRE_DIV64                  ((uint32_t)0x000000C0)        /* SYSCLK divided by 64 */
+#define  RCC_HPRE_DIV128                 ((uint32_t)0x000000D0)        /* SYSCLK divided by 128 */
+#define  RCC_HPRE_DIV256                 ((uint32_t)0x000000E0)        /* SYSCLK divided by 256 */
+#define  RCC_HPRE_DIV512                 ((uint32_t)0x000000F0)        /* SYSCLK divided by 512 */
+
+#define  RCC_PPRE1                       ((uint32_t)0x00000700)        /* PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_PPRE1_0                     ((uint32_t)0x00000100)        /* Bit 0 */
+#define  RCC_PPRE1_1                     ((uint32_t)0x00000200)        /* Bit 1 */
+#define  RCC_PPRE1_2                     ((uint32_t)0x00000400)        /* Bit 2 */
+
+#define  RCC_PPRE1_DIV1                  ((uint32_t)0x00000000)        /* HCLK not divided */
+#define  RCC_PPRE1_DIV2                  ((uint32_t)0x00000400)        /* HCLK divided by 2 */
+#define  RCC_PPRE1_DIV4                  ((uint32_t)0x00000500)        /* HCLK divided by 4 */
+#define  RCC_PPRE1_DIV8                  ((uint32_t)0x00000600)        /* HCLK divided by 8 */
+#define  RCC_PPRE1_DIV16                 ((uint32_t)0x00000700)        /* HCLK divided by 16 */
+
+#define  RCC_PPRE2                       ((uint32_t)0x00003800)        /* PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_PPRE2_0                     ((uint32_t)0x00000800)        /* Bit 0 */
+#define  RCC_PPRE2_1                     ((uint32_t)0x00001000)        /* Bit 1 */
+#define  RCC_PPRE2_2                     ((uint32_t)0x00002000)        /* Bit 2 */
+
+#define  RCC_PPRE2_DIV1                  ((uint32_t)0x00000000)        /* HCLK not divided */
+#define  RCC_PPRE2_DIV2                  ((uint32_t)0x00002000)        /* HCLK divided by 2 */
+#define  RCC_PPRE2_DIV4                  ((uint32_t)0x00002800)        /* HCLK divided by 4 */
+#define  RCC_PPRE2_DIV8                  ((uint32_t)0x00003000)        /* HCLK divided by 8 */
+#define  RCC_PPRE2_DIV16                 ((uint32_t)0x00003800)        /* HCLK divided by 16 */
+
+#define  RCC_ADCPRE                      ((uint32_t)0x0000C000)        /* ADCPRE[1:0] bits (ADC prescaler) */
+#define  RCC_ADCPRE_0                    ((uint32_t)0x00004000)        /* Bit 0 */
+#define  RCC_ADCPRE_1                    ((uint32_t)0x00008000)        /* Bit 1 */
+
+#define  RCC_ADCPRE_DIV2                 ((uint32_t)0x00000000)        /* PCLK2 divided by 2 */
+#define  RCC_ADCPRE_DIV4                 ((uint32_t)0x00004000)        /* PCLK2 divided by 4 */
+#define  RCC_ADCPRE_DIV6                 ((uint32_t)0x00008000)        /* PCLK2 divided by 6 */
+#define  RCC_ADCPRE_DIV8                 ((uint32_t)0x0000C000)        /* PCLK2 divided by 8 */
+
+#define  RCC_PLLSRC                      ((uint32_t)0x00010000)        /* PLL entry clock source */
+
+#define  RCC_PLLXTPRE                    ((uint32_t)0x00020000)        /* HSE divider for PLL entry */
+
+#define  RCC_PLLMULL                     ((uint32_t)0x003C0000)        /* PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_PLLMULL_0                   ((uint32_t)0x00040000)        /* Bit 0 */
+#define  RCC_PLLMULL_1                   ((uint32_t)0x00080000)        /* Bit 1 */
+#define  RCC_PLLMULL_2                   ((uint32_t)0x00100000)        /* Bit 2 */
+#define  RCC_PLLMULL_3                   ((uint32_t)0x00200000)        /* Bit 3 */
+ 
+#define  RCC_PLLSRC_HSI_Div2             ((uint32_t)0x00000000)        /* HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_PLLSRC_HSE                  ((uint32_t)0x00010000)        /* HSE clock selected as PLL entry clock source */
+ 
+#define  RCC_PLLXTPRE_HSE                ((uint32_t)0x00000000)        /* HSE clock not divided for PLL entry */
+#define  RCC_PLLXTPRE_HSE_Div2           ((uint32_t)0x00020000)        /* HSE clock divided by 2 for PLL entry */
+
+/* for other CH32V30x */
+#define  RCC_PLLMULL2                    ((uint32_t)0x00000000)        /* PLL input clock*2 */
+#define  RCC_PLLMULL3                    ((uint32_t)0x00040000)        /* PLL input clock*3 */
+#define  RCC_PLLMULL4                    ((uint32_t)0x00080000)        /* PLL input clock*4 */
+#define  RCC_PLLMULL5                    ((uint32_t)0x000C0000)        /* PLL input clock*5 */
+#define  RCC_PLLMULL6                    ((uint32_t)0x00100000)        /* PLL input clock*6 */
+#define  RCC_PLLMULL7                    ((uint32_t)0x00140000)        /* PLL input clock*7 */
+#define  RCC_PLLMULL8                    ((uint32_t)0x00180000)        /* PLL input clock*8 */
+#define  RCC_PLLMULL9                    ((uint32_t)0x001C0000)        /* PLL input clock*9 */
+#define  RCC_PLLMULL10                   ((uint32_t)0x00200000)        /* PLL input clock10 */
+#define  RCC_PLLMULL11                   ((uint32_t)0x00240000)        /* PLL input clock*11 */
+#define  RCC_PLLMULL12                   ((uint32_t)0x00280000)        /* PLL input clock*12 */
+#define  RCC_PLLMULL13                   ((uint32_t)0x002C0000)        /* PLL input clock*13 */
+#define  RCC_PLLMULL14                   ((uint32_t)0x00300000)        /* PLL input clock*14 */
+#define  RCC_PLLMULL15                   ((uint32_t)0x00340000)        /* PLL input clock*15 */
+#define  RCC_PLLMULL16                   ((uint32_t)0x00380000)        /* PLL input clock*16 */
+#define  RCC_PLLMULL18                   ((uint32_t)0x003C0000)        /* PLL input clock*18 */
+/* for CH32V307 */
+#define  RCC_PLLMULL18_EXTEN             ((uint32_t)0x00000000)        /* PLL input clock*18 */
+#define  RCC_PLLMULL3_EXTEN              ((uint32_t)0x00040000)        /* PLL input clock*3 */
+#define  RCC_PLLMULL4_EXTEN              ((uint32_t)0x00080000)        /* PLL input clock*4 */
+#define  RCC_PLLMULL5_EXTEN              ((uint32_t)0x000C0000)        /* PLL input clock*5 */
+#define  RCC_PLLMULL6_EXTEN              ((uint32_t)0x00100000)        /* PLL input clock*6 */
+#define  RCC_PLLMULL7_EXTEN              ((uint32_t)0x00140000)        /* PLL input clock*7 */
+#define  RCC_PLLMULL8_EXTEN              ((uint32_t)0x00180000)        /* PLL input clock*8 */
+#define  RCC_PLLMULL9_EXTEN              ((uint32_t)0x001C0000)        /* PLL input clock*9 */
+#define  RCC_PLLMULL10_EXTEN             ((uint32_t)0x00200000)        /* PLL input clock10 */
+#define  RCC_PLLMULL11_EXTEN             ((uint32_t)0x00240000)        /* PLL input clock*11 */
+#define  RCC_PLLMULL12_EXTEN             ((uint32_t)0x00280000)        /* PLL input clock*12 */
+#define  RCC_PLLMULL13_EXTEN             ((uint32_t)0x002C0000)        /* PLL input clock*13 */
+#define  RCC_PLLMULL14_EXTEN             ((uint32_t)0x00300000)        /* PLL input clock*14 */
+#define  RCC_PLLMULL6_5_EXTEN            ((uint32_t)0x00340000)        /* PLL input clock*6.5 */
+#define  RCC_PLLMULL15_EXTEN             ((uint32_t)0x00380000)        /* PLL input clock*15 */
+#define  RCC_PLLMULL16_EXTEN             ((uint32_t)0x003C0000)        /* PLL input clock*16 */
+
+#define  RCC_USBPRE                      ((uint32_t)0x00400000)        /* USB Device prescaler */
+
+#define  RCC_CFGR0_MCO                   ((uint32_t)0x07000000)        /* MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_MCO_0                       ((uint32_t)0x01000000)        /* Bit 0 */
+#define  RCC_MCO_1                       ((uint32_t)0x02000000)        /* Bit 1 */
+#define  RCC_MCO_2                       ((uint32_t)0x04000000)        /* Bit 2 */
+
+#define  RCC_MCO_NOCLOCK                 ((uint32_t)0x00000000)        /* No clock */
+#define  RCC_CFGR0_MCO_SYSCLK            ((uint32_t)0x04000000)        /* System clock selected as MCO source */
+#define  RCC_CFGR0_MCO_HSI               ((uint32_t)0x05000000)        /* HSI clock selected as MCO source */
+#define  RCC_CFGR0_MCO_HSE               ((uint32_t)0x06000000)        /* HSE clock selected as MCO source  */
+#define  RCC_CFGR0_MCO_PLL               ((uint32_t)0x07000000)        /* PLL clock divided by 2 selected as MCO source */
+
+/*******************  Bit definition for RCC_INTR register  ********************/
+#define  RCC_LSIRDYF                     ((uint32_t)0x00000001)        /* LSI Ready Interrupt flag */
+#define  RCC_LSERDYF                     ((uint32_t)0x00000002)        /* LSE Ready Interrupt flag */
+#define  RCC_HSIRDYF                     ((uint32_t)0x00000004)        /* HSI Ready Interrupt flag */
+#define  RCC_HSERDYF                     ((uint32_t)0x00000008)        /* HSE Ready Interrupt flag */
+#define  RCC_PLLRDYF                     ((uint32_t)0x00000010)        /* PLL Ready Interrupt flag */
+#define  RCC_CSSF                        ((uint32_t)0x00000080)        /* Clock Security System Interrupt flag */
+#define  RCC_LSIRDYIE                    ((uint32_t)0x00000100)        /* LSI Ready Interrupt Enable */
+#define  RCC_LSERDYIE                    ((uint32_t)0x00000200)        /* LSE Ready Interrupt Enable */
+#define  RCC_HSIRDYIE                    ((uint32_t)0x00000400)        /* HSI Ready Interrupt Enable */
+#define  RCC_HSERDYIE                    ((uint32_t)0x00000800)        /* HSE Ready Interrupt Enable */
+#define  RCC_PLLRDYIE                    ((uint32_t)0x00001000)        /* PLL Ready Interrupt Enable */
+#define  RCC_LSIRDYC                     ((uint32_t)0x00010000)        /* LSI Ready Interrupt Clear */
+#define  RCC_LSERDYC                     ((uint32_t)0x00020000)        /* LSE Ready Interrupt Clear */
+#define  RCC_HSIRDYC                     ((uint32_t)0x00040000)        /* HSI Ready Interrupt Clear */
+#define  RCC_HSERDYC                     ((uint32_t)0x00080000)        /* HSE Ready Interrupt Clear */
+#define  RCC_PLLRDYC                     ((uint32_t)0x00100000)        /* PLL Ready Interrupt Clear */
+#define  RCC_CSSC                        ((uint32_t)0x00800000)        /* Clock Security System Interrupt Clear */
+
+
+/*****************  Bit definition for RCC_APB2PRSTR register  *****************/
+#define  RCC_AFIORST                     ((uint32_t)0x00000001)        /* Alternate Function I/O reset */
+#define  RCC_IOPARST                     ((uint32_t)0x00000004)        /* I/O port A reset */
+#define  RCC_IOPBRST                     ((uint32_t)0x00000008)        /* I/O port B reset */
+#define  RCC_IOPCRST                     ((uint32_t)0x00000010)        /* I/O port C reset */
+#define  RCC_IOPDRST                     ((uint32_t)0x00000020)        /* I/O port D reset */
+#define  RCC_ADC1RST                     ((uint32_t)0x00000200)        /* ADC 1 interface reset */
+
+
+#define  RCC_ADC2RST                     ((uint32_t)0x00000400)        /* ADC 2 interface reset */
+
+
+#define  RCC_TIM1RST                     ((uint32_t)0x00000800)        /* TIM1 Timer reset */
+#define  RCC_SPI1RST                     ((uint32_t)0x00001000)        /* SPI 1 reset */
+#define  RCC_USART1RST                   ((uint32_t)0x00004000)        /* USART1 reset */
+
+#define  RCC_IOPERST                     ((uint32_t)0x00000040)        /* I/O port E reset */
+
+/*****************  Bit definition for RCC_APB1PRSTR register  *****************/
+#define  RCC_TIM2RST                     ((uint32_t)0x00000001)        /* Timer 2 reset */
+#define  RCC_TIM3RST                     ((uint32_t)0x00000002)        /* Timer 3 reset */
+#define  RCC_WWDGRST                     ((uint32_t)0x00000800)        /* Window Watchdog reset */
+#define  RCC_USART2RST                   ((uint32_t)0x00020000)        /* USART 2 reset */
+#define  RCC_I2C1RST                     ((uint32_t)0x00200000)        /* I2C 1 reset */
+  
+#define  RCC_CAN1RST                     ((uint32_t)0x02000000)        /* CAN1 reset */
+
+
+#define  RCC_BKPRST                      ((uint32_t)0x08000000)        /* Backup interface reset */
+#define  RCC_PWRRST                      ((uint32_t)0x10000000)        /* Power interface reset */
+
+
+#define  RCC_TIM4RST                     ((uint32_t)0x00000004)        /* Timer 4 reset */
+#define  RCC_SPI2RST                     ((uint32_t)0x00004000)        /* SPI 2 reset */
+#define  RCC_USART3RST                   ((uint32_t)0x00040000)        /* USART 3 reset */
+#define  RCC_I2C2RST                     ((uint32_t)0x00400000)        /* I2C 2 reset */
+
+#define  RCC_USBRST                      ((uint32_t)0x00800000)        /* USB Device reset */
+
+/******************  Bit definition for RCC_AHBPCENR register  ******************/
+#define  RCC_DMA1EN                      ((uint16_t)0x0001)            /* DMA1 clock enable */
+#define  RCC_SRAMEN                      ((uint16_t)0x0004)            /* SRAM interface clock enable */
+#define  RCC_FLITFEN                     ((uint16_t)0x0010)            /* FLITF clock enable */
+#define  RCC_CRCEN                       ((uint16_t)0x0040)            /* CRC clock enable */
+#define  RCC_USBHD                       ((uint16_t)0x1000)
+
+/******************  Bit definition for RCC_APB2PCENR register  *****************/
+#define  RCC_AFIOEN                      ((uint32_t)0x00000001)         /* Alternate Function I/O clock enable */
+#define  RCC_IOPAEN                      ((uint32_t)0x00000004)         /* I/O port A clock enable */
+#define  RCC_IOPBEN                      ((uint32_t)0x00000008)         /* I/O port B clock enable */
+#define  RCC_IOPCEN                      ((uint32_t)0x00000010)         /* I/O port C clock enable */
+#define  RCC_IOPDEN                      ((uint32_t)0x00000020)         /* I/O port D clock enable */
+#define  RCC_ADC1EN                      ((uint32_t)0x00000200)         /* ADC 1 interface clock enable */
+
+#define  RCC_ADC2EN                      ((uint32_t)0x00000400)         /* ADC 2 interface clock enable */
+
+
+#define  RCC_TIM1EN                      ((uint32_t)0x00000800)         /* TIM1 Timer clock enable */
+#define  RCC_SPI1EN                      ((uint32_t)0x00001000)         /* SPI 1 clock enable */
+#define  RCC_USART1EN                    ((uint32_t)0x00004000)         /* USART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1PCENR register  ******************/
+#define  RCC_TIM2EN                      ((uint32_t)0x00000001)        /* Timer 2 clock enabled*/
+#define  RCC_TIM3EN                      ((uint32_t)0x00000002)        /* Timer 3 clock enable */
+#define  RCC_WWDGEN                      ((uint32_t)0x00000800)        /* Window Watchdog clock enable */
+#define  RCC_USART2EN                    ((uint32_t)0x00020000)        /* USART 2 clock enable */
+#define  RCC_I2C1EN                      ((uint32_t)0x00200000)        /* I2C 1 clock enable */
+
+#define  RCC_BKPEN                       ((uint32_t)0x08000000)        /* Backup interface clock enable */
+#define  RCC_PWREN                       ((uint32_t)0x10000000)        /* Power interface clock enable */
+
+
+#define  RCC_USBEN                       ((uint32_t)0x00800000)        /* USB Device clock enable */
+
+/*******************  Bit definition for RCC_BDCTLR register  *******************/
+#define  RCC_LSEON                       ((uint32_t)0x00000001)        /* External Low Speed oscillator enable */
+#define  RCC_LSERDY                      ((uint32_t)0x00000002)        /* External Low Speed oscillator Ready */
+#define  RCC_LSEBYP                      ((uint32_t)0x00000004)        /* External Low Speed oscillator Bypass */
+
+#define  RCC_RTCSEL                      ((uint32_t)0x00000300)        /* RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_RTCSEL_0                    ((uint32_t)0x00000100)        /* Bit 0 */
+#define  RCC_RTCSEL_1                    ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define  RCC_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)        /* No clock */
+#define  RCC_RTCSEL_LSE                  ((uint32_t)0x00000100)        /* LSE oscillator clock used as RTC clock */
+#define  RCC_RTCSEL_LSI                  ((uint32_t)0x00000200)        /* LSI oscillator clock used as RTC clock */
+#define  RCC_RTCSEL_HSE                  ((uint32_t)0x00000300)        /* HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_RTCEN                       ((uint32_t)0x00008000)        /* RTC clock enable */
+#define  RCC_BDRST                       ((uint32_t)0x00010000)        /* Backup domain software reset  */
+
+/*******************  Bit definition for RCC_RSTSCKR register  ********************/  
+#define  RCC_LSION                       ((uint32_t)0x00000001)        /* Internal Low Speed oscillator enable */
+#define  RCC_LSIRDY                      ((uint32_t)0x00000002)        /* Internal Low Speed oscillator Ready */
+#define  RCC_RMVF                        ((uint32_t)0x01000000)        /* Remove reset flag */
+#define  RCC_PINRSTF                     ((uint32_t)0x04000000)        /* PIN reset flag */
+#define  RCC_PORRSTF                     ((uint32_t)0x08000000)        /* POR/PDR reset flag */
+#define  RCC_SFTRSTF                     ((uint32_t)0x10000000)        /* Software Reset flag */
+#define  RCC_IWDGRSTF                    ((uint32_t)0x20000000)        /* Independent Watchdog reset flag */
+#define  RCC_WWDGRSTF                    ((uint32_t)0x40000000)        /* Window watchdog reset flag */
+#define  RCC_LPWRRSTF                    ((uint32_t)0x80000000)        /* Low-Power reset flag */
+
+/******************************************************************************/
+/*                                    RNG                                     */
+/******************************************************************************/
+/********************  Bit definition for RNG_CR register  *******************/
+#define  RNG_CR_RNGEN                         ((uint32_t)0x00000004)
+#define  RNG_CR_IE                            ((uint32_t)0x00000008)
+
+/********************  Bit definition for RNG_SR register  *******************/
+#define  RNG_SR_DRDY                          ((uint32_t)0x00000001)
+#define  RNG_SR_CECS                          ((uint32_t)0x00000002)
+#define  RNG_SR_SECS                          ((uint32_t)0x00000004)
+#define  RNG_SR_CEIS                          ((uint32_t)0x00000020)
+#define  RNG_SR_SEIS                          ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/*                             Real-Time Clock                                */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CTLRH register  ********************/
+#define  RTC_CTLRH_SECIE                     ((uint8_t)0x01)               /* Second Interrupt Enable */
+#define  RTC_CTLRH_ALRIE                     ((uint8_t)0x02)               /* Alarm Interrupt Enable */
+#define  RTC_CTLRH_OWIE                      ((uint8_t)0x04)               /* OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CTLRL register  ********************/
+#define  RTC_CTLRL_SECF                      ((uint8_t)0x01)               /* Second Flag */
+#define  RTC_CTLRL_ALRF                      ((uint8_t)0x02)               /* Alarm Flag */
+#define  RTC_CTLRL_OWF                       ((uint8_t)0x04)               /* OverfloW Flag */
+#define  RTC_CTLRL_RSF                       ((uint8_t)0x08)               /* Registers Synchronized Flag */
+#define  RTC_CTLRL_CNF                       ((uint8_t)0x10)               /* Configuration Flag */
+#define  RTC_CTLRL_RTOFF                     ((uint8_t)0x20)               /* RTC operation OFF */
+
+/*******************  Bit definition for RTC_PSCH register  *******************/
+#define  RTC_PSCH_PRL                        ((uint16_t)0x000F)            /* RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define  RTC_PSCL_PRL                        ((uint16_t)0xFFFF)            /* RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /* RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /* RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /* RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /* RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRMH register  *******************/
+#define  RTC_ALRMH_RTC_ALRM                  ((uint16_t)0xFFFF)            /* RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRML register  *******************/
+#define  RTC_ALRML_RTC_ALRM                  ((uint16_t)0xFFFF)            /* RTC Alarm Low */
+
+/******************************************************************************/
+/*                        Serial Peripheral Interface                         */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTLR1 register  ********************/
+#define  SPI_CTLR1_CPHA                      ((uint16_t)0x0001)            /* Clock Phase */
+#define  SPI_CTLR1_CPOL                      ((uint16_t)0x0002)            /* Clock Polarity */
+#define  SPI_CTLR1_MSTR                      ((uint16_t)0x0004)            /* Master Selection */
+
+#define  SPI_CTLR1_BR                        ((uint16_t)0x0038)            /* BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CTLR1_BR_0                      ((uint16_t)0x0008)            /* Bit 0 */
+#define  SPI_CTLR1_BR_1                      ((uint16_t)0x0010)            /* Bit 1 */
+#define  SPI_CTLR1_BR_2                      ((uint16_t)0x0020)            /* Bit 2 */
+
+#define  SPI_CTLR1_SPE                       ((uint16_t)0x0040)            /* SPI Enable */
+#define  SPI_CTLR1_LSBFIRST                  ((uint16_t)0x0080)            /* Frame Format */
+#define  SPI_CTLR1_SSI                       ((uint16_t)0x0100)            /* Internal slave select */
+#define  SPI_CTLR1_SSM                       ((uint16_t)0x0200)            /* Software slave management */
+#define  SPI_CTLR1_RXONLY                    ((uint16_t)0x0400)            /* Receive only */
+#define  SPI_CTLR1_DFF                       ((uint16_t)0x0800)            /* Data Frame Format */
+#define  SPI_CTLR1_CRCNEXT                   ((uint16_t)0x1000)            /* Transmit CRC next */
+#define  SPI_CTLR1_CRCEN                     ((uint16_t)0x2000)            /* Hardware CRC calculation enable */
+#define  SPI_CTLR1_BIDIOE                    ((uint16_t)0x4000)            /* Output enable in bidirectional mode */
+#define  SPI_CTLR1_BIDIMODE                  ((uint16_t)0x8000)            /* Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTLR2 register  ********************/
+#define  SPI_CTLR2_RXDMAEN                   ((uint8_t)0x01)               /* Rx Buffer DMA Enable */
+#define  SPI_CTLR2_TXDMAEN                   ((uint8_t)0x02)               /* Tx Buffer DMA Enable */
+#define  SPI_CTLR2_SSOE                      ((uint8_t)0x04)               /* SS Output Enable */
+#define  SPI_CTLR2_ERRIE                     ((uint8_t)0x20)               /* Error Interrupt Enable */
+#define  SPI_CTLR2_RXNEIE                    ((uint8_t)0x40)               /* RX buffer Not Empty Interrupt Enable */
+#define  SPI_CTLR2_TXEIE                     ((uint8_t)0x80)               /* Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_STATR register  ********************/
+#define  SPI_STATR_RXNE                      ((uint8_t)0x01)               /* Receive buffer Not Empty */
+#define  SPI_STATR_TXE                       ((uint8_t)0x02)               /* Transmit buffer Empty */
+#define  SPI_STATR_CHSIDE                    ((uint8_t)0x04)               /* Channel side */
+#define  SPI_STATR_UDR                       ((uint8_t)0x08)               /* Underrun flag */
+#define  SPI_STATR_CRCERR                    ((uint8_t)0x10)               /* CRC Error flag */
+#define  SPI_STATR_MODF                      ((uint8_t)0x20)               /* Mode fault */
+#define  SPI_STATR_OVR                       ((uint8_t)0x40)               /* Overrun flag */
+#define  SPI_STATR_BSY                       ((uint8_t)0x80)               /* Busy flag */
+
+/********************  Bit definition for SPI_DATAR register  ********************/
+#define  SPI_DATAR_DR                        ((uint16_t)0xFFFF)            /* Data Register */
+
+/*******************  Bit definition for SPI_CRCR register  ******************/
+#define  SPI_CRCR_CRCPOLY                    ((uint16_t)0xFFFF)            /* CRC polynomial register */
+
+/******************  Bit definition for SPI_RCRCR register  ******************/
+#define  SPI_RCRCR_RXCRC                     ((uint16_t)0xFFFF)            /* Rx CRC Register */
+
+/******************  Bit definition for SPI_TCRCR register  ******************/
+#define  SPI_TCRCR_TXCRC                     ((uint16_t)0xFFFF)            /* Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /* Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /* DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /* Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /* Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /* steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /* I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /* Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /* Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /* PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /* I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /* Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /* I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /* I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /* I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /* Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /* Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                    TIM                                     */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CTLR1 register  ********************/
+#define  TIM_CEN                         ((uint16_t)0x0001)            /* Counter enable */
+#define  TIM_UDIS                        ((uint16_t)0x0002)            /* Update disable */
+#define  TIM_URS                         ((uint16_t)0x0004)            /* Update request source */
+#define  TIM_OPM                         ((uint16_t)0x0008)            /* One pulse mode */
+#define  TIM_DIR                         ((uint16_t)0x0010)            /* Direction */
+
+#define  TIM_CMS                         ((uint16_t)0x0060)            /* CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CMS_0                       ((uint16_t)0x0020)            /* Bit 0 */
+#define  TIM_CMS_1                       ((uint16_t)0x0040)            /* Bit 1 */
+
+#define  TIM_ARPE                        ((uint16_t)0x0080)            /* Auto-reload preload enable */
+
+#define  TIM_CTLR1_CKD                   ((uint16_t)0x0300)            /* CKD[1:0] bits (clock division) */
+#define  TIM_CKD_0                       ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_CKD_1                       ((uint16_t)0x0200)            /* Bit 1 */
+
+/*******************  Bit definition for TIM_CTLR2 register  ********************/
+#define  TIM_CCPC                        ((uint16_t)0x0001)            /* Capture/Compare Preloaded Control */
+#define  TIM_CCUS                        ((uint16_t)0x0004)            /* Capture/Compare Control Update Selection */
+#define  TIM_CCDS                        ((uint16_t)0x0008)            /* Capture/Compare DMA Selection */
+
+#define  TIM_MMS                         ((uint16_t)0x0070)            /* MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_MMS_0                       ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_MMS_1                       ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_MMS_2                       ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_TI1S                        ((uint16_t)0x0080)            /* TI1 Selection */
+#define  TIM_OIS1                        ((uint16_t)0x0100)            /* Output Idle state 1 (OC1 output) */
+#define  TIM_OIS1N                       ((uint16_t)0x0200)            /* Output Idle state 1 (OC1N output) */
+#define  TIM_OIS2                        ((uint16_t)0x0400)            /* Output Idle state 2 (OC2 output) */
+#define  TIM_OIS2N                       ((uint16_t)0x0800)            /* Output Idle state 2 (OC2N output) */
+#define  TIM_OIS3                        ((uint16_t)0x1000)            /* Output Idle state 3 (OC3 output) */
+#define  TIM_OIS3N                       ((uint16_t)0x2000)            /* Output Idle state 3 (OC3N output) */
+#define  TIM_OIS4                        ((uint16_t)0x4000)            /* Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCFGR register  *******************/
+#define  TIM_SMS                         ((uint16_t)0x0007)            /* SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMS_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_SMS_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  TIM_SMS_2                       ((uint16_t)0x0004)            /* Bit 2 */
+
+#define  TIM_TS                          ((uint16_t)0x0070)            /* TS[2:0] bits (Trigger selection) */
+#define  TIM_TS_0                        ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_TS_1                        ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_TS_2                        ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_MSM                         ((uint16_t)0x0080)            /* Master/slave mode */
+ 
+#define  TIM_ETF                         ((uint16_t)0x0F00)            /* ETF[3:0] bits (External trigger filter) */
+#define  TIM_ETF_0                       ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_ETF_1                       ((uint16_t)0x0200)            /* Bit 1 */
+#define  TIM_ETF_2                       ((uint16_t)0x0400)            /* Bit 2 */
+#define  TIM_ETF_3                       ((uint16_t)0x0800)            /* Bit 3 */
+
+#define  TIM_ETPS                        ((uint16_t)0x3000)            /* ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_ETPS_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_ETPS_1                      ((uint16_t)0x2000)            /* Bit 1 */
+ 
+#define  TIM_ECE                         ((uint16_t)0x4000)            /* External clock enable */
+#define  TIM_ETP                         ((uint16_t)0x8000)            /* External trigger polarity */
+
+/*******************  Bit definition for TIM_DMAINTENR register  *******************/
+#define  TIM_UIE                         ((uint16_t)0x0001)            /* Update interrupt enable */
+#define  TIM_CC1IE                       ((uint16_t)0x0002)            /* Capture/Compare 1 interrupt enable */
+#define  TIM_CC2IE                       ((uint16_t)0x0004)            /* Capture/Compare 2 interrupt enable */
+#define  TIM_CC3IE                       ((uint16_t)0x0008)            /* Capture/Compare 3 interrupt enable */
+#define  TIM_CC4IE                       ((uint16_t)0x0010)            /* Capture/Compare 4 interrupt enable */
+#define  TIM_COMIE                       ((uint16_t)0x0020)            /* COM interrupt enable */
+#define  TIM_TIE                         ((uint16_t)0x0040)            /* Trigger interrupt enable */
+#define  TIM_BIE                         ((uint16_t)0x0080)            /* Break interrupt enable */
+#define  TIM_UDE                         ((uint16_t)0x0100)            /* Update DMA request enable */
+#define  TIM_CC1DE                       ((uint16_t)0x0200)            /* Capture/Compare 1 DMA request enable */
+#define  TIM_CC2DE                       ((uint16_t)0x0400)            /* Capture/Compare 2 DMA request enable */
+#define  TIM_CC3DE                       ((uint16_t)0x0800)            /* Capture/Compare 3 DMA request enable */
+#define  TIM_CC4DE                       ((uint16_t)0x1000)            /* Capture/Compare 4 DMA request enable */
+#define  TIM_COMDE                       ((uint16_t)0x2000)            /* COM DMA request enable */
+#define  TIM_TDE                         ((uint16_t)0x4000)            /* Trigger DMA request enable */
+
+/********************  Bit definition for TIM_INTFR register  ********************/
+#define  TIM_UIF                         ((uint16_t)0x0001)            /* Update interrupt Flag */
+#define  TIM_CC1IF                       ((uint16_t)0x0002)            /* Capture/Compare 1 interrupt Flag */
+#define  TIM_CC2IF                       ((uint16_t)0x0004)            /* Capture/Compare 2 interrupt Flag */
+#define  TIM_CC3IF                       ((uint16_t)0x0008)            /* Capture/Compare 3 interrupt Flag */
+#define  TIM_CC4IF                       ((uint16_t)0x0010)            /* Capture/Compare 4 interrupt Flag */
+#define  TIM_COMIF                       ((uint16_t)0x0020)            /* COM interrupt Flag */
+#define  TIM_TIF                         ((uint16_t)0x0040)            /* Trigger interrupt Flag */
+#define  TIM_BIF                         ((uint16_t)0x0080)            /* Break interrupt Flag */
+#define  TIM_CC1OF                       ((uint16_t)0x0200)            /* Capture/Compare 1 Overcapture Flag */
+#define  TIM_CC2OF                       ((uint16_t)0x0400)            /* Capture/Compare 2 Overcapture Flag */
+#define  TIM_CC3OF                       ((uint16_t)0x0800)            /* Capture/Compare 3 Overcapture Flag */
+#define  TIM_CC4OF                       ((uint16_t)0x1000)            /* Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_SWEVGR register  ********************/
+#define  TIM_UG                          ((uint8_t)0x01)               /* Update Generation */
+#define  TIM_CC1G                        ((uint8_t)0x02)               /* Capture/Compare 1 Generation */
+#define  TIM_CC2G                        ((uint8_t)0x04)               /* Capture/Compare 2 Generation */
+#define  TIM_CC3G                        ((uint8_t)0x08)               /* Capture/Compare 3 Generation */
+#define  TIM_CC4G                        ((uint8_t)0x10)               /* Capture/Compare 4 Generation */
+#define  TIM_COMG                        ((uint8_t)0x20)               /* Capture/Compare Control Update Generation */
+#define  TIM_TG                          ((uint8_t)0x40)               /* Trigger Generation */
+#define  TIM_BG                          ((uint8_t)0x80)               /* Break Generation */
+
+/******************  Bit definition for TIM_CHCTLR1 register  *******************/
+#define  TIM_CC1S                        ((uint16_t)0x0003)            /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CC1S_0                      ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_CC1S_1                      ((uint16_t)0x0002)            /* Bit 1 */
+
+#define  TIM_OC1FE                       ((uint16_t)0x0004)            /* Output Compare 1 Fast enable */
+#define  TIM_OC1PE                       ((uint16_t)0x0008)            /* Output Compare 1 Preload enable */
+
+#define  TIM_OC1M                        ((uint16_t)0x0070)            /* OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_OC1M_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_OC1M_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_OC1M_2                      ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_OC1CE                       ((uint16_t)0x0080)            /* Output Compare 1Clear Enable */
+
+#define  TIM_CC2S                        ((uint16_t)0x0300)            /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CC2S_0                      ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_CC2S_1                      ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  TIM_OC2FE                       ((uint16_t)0x0400)            /* Output Compare 2 Fast enable */
+#define  TIM_OC2PE                       ((uint16_t)0x0800)            /* Output Compare 2 Preload enable */
+
+#define  TIM_OC2M                        ((uint16_t)0x7000)            /* OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_OC2M_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_OC2M_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_OC2M_2                      ((uint16_t)0x4000)            /* Bit 2 */
+
+#define  TIM_OC2CE                       ((uint16_t)0x8000)            /* Output Compare 2 Clear Enable */
+
+
+#define  TIM_IC1PSC                      ((uint16_t)0x000C)            /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_IC1PSC_0                    ((uint16_t)0x0004)            /* Bit 0 */
+#define  TIM_IC1PSC_1                    ((uint16_t)0x0008)            /* Bit 1 */
+
+#define  TIM_IC1F                        ((uint16_t)0x00F0)            /* IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_IC1F_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_IC1F_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_IC1F_2                      ((uint16_t)0x0040)            /* Bit 2 */
+#define  TIM_IC1F_3                      ((uint16_t)0x0080)            /* Bit 3 */
+
+#define  TIM_IC2PSC                      ((uint16_t)0x0C00)            /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_IC2PSC_0                    ((uint16_t)0x0400)            /* Bit 0 */
+#define  TIM_IC2PSC_1                    ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  TIM_IC2F                        ((uint16_t)0xF000)            /* IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_IC2F_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_IC2F_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_IC2F_2                      ((uint16_t)0x4000)            /* Bit 2 */
+#define  TIM_IC2F_3                      ((uint16_t)0x8000)            /* Bit 3 */
+
+/******************  Bit definition for TIM_CHCTLR2 register  *******************/
+#define  TIM_CC3S                        ((uint16_t)0x0003)            /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CC3S_0                      ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_CC3S_1                      ((uint16_t)0x0002)            /* Bit 1 */
+
+#define  TIM_OC3FE                       ((uint16_t)0x0004)            /* Output Compare 3 Fast enable */
+#define  TIM_OC3PE                       ((uint16_t)0x0008)            /* Output Compare 3 Preload enable */
+
+#define  TIM_OC3M                        ((uint16_t)0x0070)            /* OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_OC3M_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_OC3M_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_OC3M_2                      ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_OC3CE                       ((uint16_t)0x0080)            /* Output Compare 3 Clear Enable */
+
+#define  TIM_CC4S                        ((uint16_t)0x0300)            /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CC4S_0                      ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_CC4S_1                      ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  TIM_OC4FE                       ((uint16_t)0x0400)            /* Output Compare 4 Fast enable */
+#define  TIM_OC4PE                       ((uint16_t)0x0800)            /* Output Compare 4 Preload enable */
+
+#define  TIM_OC4M                        ((uint16_t)0x7000)            /* OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_OC4M_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_OC4M_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_OC4M_2                      ((uint16_t)0x4000)            /* Bit 2 */
+
+#define  TIM_OC4CE                       ((uint16_t)0x8000)            /* Output Compare 4 Clear Enable */
+
+
+#define  TIM_IC3PSC                      ((uint16_t)0x000C)            /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_IC3PSC_0                    ((uint16_t)0x0004)            /* Bit 0 */
+#define  TIM_IC3PSC_1                    ((uint16_t)0x0008)            /* Bit 1 */
+
+#define  TIM_IC3F                        ((uint16_t)0x00F0)            /* IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_IC3F_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_IC3F_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_IC3F_2                      ((uint16_t)0x0040)            /* Bit 2 */
+#define  TIM_IC3F_3                      ((uint16_t)0x0080)            /* Bit 3 */
+
+#define  TIM_IC4PSC                      ((uint16_t)0x0C00)            /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_IC4PSC_0                    ((uint16_t)0x0400)            /* Bit 0 */
+#define  TIM_IC4PSC_1                    ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  TIM_IC4F                        ((uint16_t)0xF000)            /* IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_IC4F_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_IC4F_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_IC4F_2                      ((uint16_t)0x4000)            /* Bit 2 */
+#define  TIM_IC4F_3                      ((uint16_t)0x8000)            /* Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CC1E                        ((uint16_t)0x0001)            /* Capture/Compare 1 output enable */
+#define  TIM_CC1P                        ((uint16_t)0x0002)            /* Capture/Compare 1 output Polarity */
+#define  TIM_CC1NE                       ((uint16_t)0x0004)            /* Capture/Compare 1 Complementary output enable */
+#define  TIM_CC1NP                       ((uint16_t)0x0008)            /* Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CC2E                        ((uint16_t)0x0010)            /* Capture/Compare 2 output enable */
+#define  TIM_CC2P                        ((uint16_t)0x0020)            /* Capture/Compare 2 output Polarity */
+#define  TIM_CC2NE                       ((uint16_t)0x0040)            /* Capture/Compare 2 Complementary output enable */
+#define  TIM_CC2NP                       ((uint16_t)0x0080)            /* Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CC3E                        ((uint16_t)0x0100)            /* Capture/Compare 3 output enable */
+#define  TIM_CC3P                        ((uint16_t)0x0200)            /* Capture/Compare 3 output Polarity */
+#define  TIM_CC3NE                       ((uint16_t)0x0400)            /* Capture/Compare 3 Complementary output enable */
+#define  TIM_CC3NP                       ((uint16_t)0x0800)            /* Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CC4E                        ((uint16_t)0x1000)            /* Capture/Compare 4 output enable */
+#define  TIM_CC4P                        ((uint16_t)0x2000)            /* Capture/Compare 4 output Polarity */
+#define  TIM_CC4NP                       ((uint16_t)0x8000)            /* Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT                         ((uint16_t)0xFFFF)            /* Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC                         ((uint16_t)0xFFFF)            /* Prescaler Value */
+
+/*******************  Bit definition for TIM_ATRLR register  ********************/
+#define  TIM_ARR                         ((uint16_t)0xFFFF)            /* actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RPTCR register  ********************/
+#define  TIM_REP                         ((uint8_t)0xFF)               /* Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CH1CVR register  *******************/
+#define  TIM_CCR1                        ((uint16_t)0xFFFF)            /* Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CH2CVR register  *******************/
+#define  TIM_CCR2                        ((uint16_t)0xFFFF)            /* Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CH3CVR register  *******************/
+#define  TIM_CCR3                        ((uint16_t)0xFFFF)            /* Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CH4CVR register  *******************/
+#define  TIM_CCR4                        ((uint16_t)0xFFFF)            /* Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_DTG                         ((uint16_t)0x00FF)            /* DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_DTG_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_DTG_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  TIM_DTG_2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  TIM_DTG_3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  TIM_DTG_4                       ((uint16_t)0x0010)            /* Bit 4 */
+#define  TIM_DTG_5                       ((uint16_t)0x0020)            /* Bit 5 */
+#define  TIM_DTG_6                       ((uint16_t)0x0040)            /* Bit 6 */
+#define  TIM_DTG_7                       ((uint16_t)0x0080)            /* Bit 7 */
+
+#define  TIM_LOCK                        ((uint16_t)0x0300)            /* LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_LOCK_0                      ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_LOCK_1                      ((uint16_t)0x0200)            /* Bit 1 */
+ 
+#define  TIM_OSSI                        ((uint16_t)0x0400)            /* Off-State Selection for Idle mode */
+#define  TIM_OSSR                        ((uint16_t)0x0800)            /* Off-State Selection for Run mode */
+#define  TIM_BKE                         ((uint16_t)0x1000)            /* Break enable */
+#define  TIM_BKP                         ((uint16_t)0x2000)            /* Break Polarity */
+#define  TIM_AOE                         ((uint16_t)0x4000)            /* Automatic Output enable */
+#define  TIM_MOE                         ((uint16_t)0x8000)            /* Main Output enable */
+
+/*******************  Bit definition for TIM_DMACFGR register  ********************/
+#define  TIM_DBA                         ((uint16_t)0x001F)            /* DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DBA_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_DBA_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  TIM_DBA_2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  TIM_DBA_3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  TIM_DBA_4                       ((uint16_t)0x0010)            /* Bit 4 */
+
+#define  TIM_DBL                         ((uint16_t)0x1F00)            /* DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DBL_0                       ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_DBL_1                       ((uint16_t)0x0200)            /* Bit 1 */
+#define  TIM_DBL_2                       ((uint16_t)0x0400)            /* Bit 2 */
+#define  TIM_DBL_3                       ((uint16_t)0x0800)            /* Bit 3 */
+#define  TIM_DBL_4                       ((uint16_t)0x1000)            /* Bit 4 */
+
+/*******************  Bit definition for TIM_DMAADR register  *******************/
+#define  TIM_DMAR_DMAB                   ((uint16_t)0xFFFF)            /* DMA register for burst accesses */
+
+/******************************************************************************/
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STATR register  *******************/
+#define  USART_STATR_PE                        ((uint16_t)0x0001)            /* Parity Error */
+#define  USART_STATR_FE                        ((uint16_t)0x0002)            /* Framing Error */
+#define  USART_STATR_NE                        ((uint16_t)0x0004)            /* Noise Error Flag */
+#define  USART_STATR_ORE                       ((uint16_t)0x0008)            /* OverRun Error */
+#define  USART_STATR_IDLE                      ((uint16_t)0x0010)            /* IDLE line detected */
+#define  USART_STATR_RXNE                      ((uint16_t)0x0020)            /* Read Data Register Not Empty */
+#define  USART_STATR_TC                        ((uint16_t)0x0040)            /* Transmission Complete */
+#define  USART_STATR_TXE                       ((uint16_t)0x0080)            /* Transmit Data Register Empty */
+#define  USART_STATR_LBD                       ((uint16_t)0x0100)            /* LIN Break Detection Flag */
+#define  USART_STATR_CTS                       ((uint16_t)0x0200)            /* CTS Flag */
+
+/*******************  Bit definition for USART_DATAR register  *******************/
+#define  USART_DATAR_DR                        ((uint16_t)0x01FF)            /* Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction                ((uint16_t)0x000F)            /* Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa                ((uint16_t)0xFFF0)            /* Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTLR1 register  *******************/
+#define  USART_CTLR1_SBK                       ((uint16_t)0x0001)            /* Send Break */
+#define  USART_CTLR1_RWU                       ((uint16_t)0x0002)            /* Receiver wakeup */
+#define  USART_CTLR1_RE                        ((uint16_t)0x0004)            /* Receiver Enable */
+#define  USART_CTLR1_TE                        ((uint16_t)0x0008)            /* Transmitter Enable */
+#define  USART_CTLR1_IDLEIE                    ((uint16_t)0x0010)            /* IDLE Interrupt Enable */
+#define  USART_CTLR1_RXNEIE                    ((uint16_t)0x0020)            /* RXNE Interrupt Enable */
+#define  USART_CTLR1_TCIE                      ((uint16_t)0x0040)            /* Transmission Complete Interrupt Enable */
+#define  USART_CTLR1_TXEIE                     ((uint16_t)0x0080)            /* PE Interrupt Enable */
+#define  USART_CTLR1_PEIE                      ((uint16_t)0x0100)            /* PE Interrupt Enable */
+#define  USART_CTLR1_PS                        ((uint16_t)0x0200)            /* Parity Selection */
+#define  USART_CTLR1_PCE                       ((uint16_t)0x0400)            /* Parity Control Enable */
+#define  USART_CTLR1_WAKE                      ((uint16_t)0x0800)            /* Wakeup method */
+#define  USART_CTLR1_M                         ((uint16_t)0x1000)            /* Word length */
+#define  USART_CTLR1_UE                        ((uint16_t)0x2000)            /* USART Enable */
+#define  USART_CTLR1_OVER8                     ((uint16_t)0x8000)            /* USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CTLR2 register  *******************/
+#define  USART_CTLR2_ADD                       ((uint16_t)0x000F)            /* Address of the USART node */
+#define  USART_CTLR2_LBDL                      ((uint16_t)0x0020)            /* LIN Break Detection Length */
+#define  USART_CTLR2_LBDIE                     ((uint16_t)0x0040)            /* LIN Break Detection Interrupt Enable */
+#define  USART_CTLR2_LBCL                      ((uint16_t)0x0100)            /* Last Bit Clock pulse */
+#define  USART_CTLR2_CPHA                      ((uint16_t)0x0200)            /* Clock Phase */
+#define  USART_CTLR2_CPOL                      ((uint16_t)0x0400)            /* Clock Polarity */
+#define  USART_CTLR2_CLKEN                     ((uint16_t)0x0800)            /* Clock Enable */
+
+#define  USART_CTLR2_STOP                      ((uint16_t)0x3000)            /* STOP[1:0] bits (STOP bits) */
+#define  USART_CTLR2_STOP_0                    ((uint16_t)0x1000)            /* Bit 0 */
+#define  USART_CTLR2_STOP_1                    ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  USART_CTLR2_LINEN                     ((uint16_t)0x4000)            /* LIN mode enable */
+
+/******************  Bit definition for USART_CTLR3 register  *******************/
+#define  USART_CTLR3_EIE                       ((uint16_t)0x0001)            /* Error Interrupt Enable */
+#define  USART_CTLR3_IREN                      ((uint16_t)0x0002)            /* IrDA mode Enable */
+#define  USART_CTLR3_IRLP                      ((uint16_t)0x0004)            /* IrDA Low-Power */
+#define  USART_CTLR3_HDSEL                     ((uint16_t)0x0008)            /* Half-Duplex Selection */
+#define  USART_CTLR3_NACK                      ((uint16_t)0x0010)            /* Smartcard NACK enable */
+#define  USART_CTLR3_SCEN                      ((uint16_t)0x0020)            /* Smartcard mode enable */
+#define  USART_CTLR3_DMAR                      ((uint16_t)0x0040)            /* DMA Enable Receiver */
+#define  USART_CTLR3_DMAT                      ((uint16_t)0x0080)            /* DMA Enable Transmitter */
+#define  USART_CTLR3_RTSE                      ((uint16_t)0x0100)            /* RTS Enable */
+#define  USART_CTLR3_CTSE                      ((uint16_t)0x0200)            /* CTS Enable */
+#define  USART_CTLR3_CTSIE                     ((uint16_t)0x0400)            /* CTS Interrupt Enable */
+#define  USART_CTLR3_ONEBIT                    ((uint16_t)0x0800)            /* One Bit method */
+
+/******************  Bit definition for USART_GPR register  ******************/
+#define  USART_GPR_PSC                         ((uint16_t)0x00FF)            /* PSC[7:0] bits (Prescaler value) */
+#define  USART_GPR_PSC_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  USART_GPR_PSC_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  USART_GPR_PSC_2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  USART_GPR_PSC_3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  USART_GPR_PSC_4                       ((uint16_t)0x0010)            /* Bit 4 */
+#define  USART_GPR_PSC_5                       ((uint16_t)0x0020)            /* Bit 5 */
+#define  USART_GPR_PSC_6                       ((uint16_t)0x0040)            /* Bit 6 */
+#define  USART_GPR_PSC_7                       ((uint16_t)0x0080)            /* Bit 7 */
+
+#define  USART_GPR_GT                          ((uint16_t)0xFF00)            /* Guard time value */
+
+/******************************************************************************/
+/*                            Window WATCHDOG                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTLR register  ********************/
+#define  WWDG_CTLR_T                           ((uint8_t)0x7F)               /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CTLR_T0                          ((uint8_t)0x01)               /* Bit 0 */
+#define  WWDG_CTLR_T1                          ((uint8_t)0x02)               /* Bit 1 */
+#define  WWDG_CTLR_T2                          ((uint8_t)0x04)               /* Bit 2 */
+#define  WWDG_CTLR_T3                          ((uint8_t)0x08)               /* Bit 3 */
+#define  WWDG_CTLR_T4                          ((uint8_t)0x10)               /* Bit 4 */
+#define  WWDG_CTLR_T5                          ((uint8_t)0x20)               /* Bit 5 */
+#define  WWDG_CTLR_T6                          ((uint8_t)0x40)               /* Bit 6 */
+
+#define  WWDG_CTLR_WDGA                        ((uint8_t)0x80)               /* Activation bit */
+
+/*******************  Bit definition for WWDG_CFGR register  *******************/
+#define  WWDG_CFGR_W                           ((uint16_t)0x007F)            /* W[6:0] bits (7-bit window value) */
+#define  WWDG_CFGR_W0                          ((uint16_t)0x0001)            /* Bit 0 */
+#define  WWDG_CFGR_W1                          ((uint16_t)0x0002)            /* Bit 1 */
+#define  WWDG_CFGR_W2                          ((uint16_t)0x0004)            /* Bit 2 */
+#define  WWDG_CFGR_W3                          ((uint16_t)0x0008)            /* Bit 3 */
+#define  WWDG_CFGR_W4                          ((uint16_t)0x0010)            /* Bit 4 */
+#define  WWDG_CFGR_W5                          ((uint16_t)0x0020)            /* Bit 5 */
+#define  WWDG_CFGR_W6                          ((uint16_t)0x0040)            /* Bit 6 */
+
+#define  WWDG_CFGR_WDGTB                       ((uint16_t)0x0180)            /* WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFGR_WDGTB0                      ((uint16_t)0x0080)            /* Bit 0 */
+#define  WWDG_CFGR_WDGTB1                      ((uint16_t)0x0100)            /* Bit 1 */
+
+#define  WWDG_CFGR_EWI                         ((uint16_t)0x0200)            /* Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STATR register  ********************/
+#define  WWDG_STATR_EWIF                       ((uint8_t)0x01)               /* Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                          ENHANCED FUNNCTION                                */
+/******************************************************************************/
+
+/****************************  Enhanced register  *****************************/
+#define  EXTEN_USBD_LS                         ((uint32_t)0x00000001)         /* Bit 0 */
+#define  EXTEN_USBD_PU_EN                      ((uint32_t)0x00000002)         /* Bit 1 */
+#define  EXTEN_ETH_10M_EN                      ((uint32_t)0x00000004)         /* Bit 2 */
+#define  EXTEN_ETH_RGMII_SEL                   ((uint32_t)0x00000008)         /* Bit 3 */
+#define  EXTEN_PLL_HSI_PRE                     ((uint32_t)0x00000010)         /* Bit 4 */
+#define  EXTEN_LOCKUP_EN                       ((uint32_t)0x00000040)         /* Bit 5 */
+#define  EXTEN_LOCKUP_RSTF                     ((uint32_t)0x00000080)         /* Bit 7 */
+
+#define  EXTEN_ULLDO_TRIM                      ((uint32_t)0x00000300)         /* ULLDO_TRIM[1:0] bits */
+#define  EXTEN_ULLDO_TRIM0                     ((uint32_t)0x00000100)         /* Bit 0 */
+#define  EXTEN_ULLDO_TRIM1                     ((uint32_t)0x00000200)         /* Bit 1 */
+
+#define  EXTEN_LDO_TRIM                        ((uint32_t)0x00000C00)         /* LDO_TRIM[1:0] bits */
+#define  EXTEN_LDO_TRIM0                       ((uint32_t)0x00000400)         /* Bit 0 */
+#define  EXTEN_LDO_TRIM1                       ((uint32_t)0x00000800)         /* Bit 1 */
+
+
+/******************************************************************************/
+/*                                  DVP                                       */
+/******************************************************************************/
+
+/*******************  Bit definition for DVP_CR0 register  ********************/
+#define RB_DVP_ENABLE			0x01					// RW, DVP enable
+#define RB_DVP_V_POLAR			0x02					// RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert
+#define	RB_DVP_H_POLAR			0x04					// RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert
+#define	RB_DVP_P_POLAR			0x08					// RW, DVP PCLK polarity control: 1 = invert, 0 = not invert
+#define RB_DVP_MSK_DAT_MOD		0x30					
+#define 	RB_DVP_D8_MOD			0x00				// RW, DVP 8bits data mode
+#define		RB_DVP_D10_MOD			0x10				// RW, DVP 10bits data mode
+#define		RB_DVP_D12_MOD			0x20				// RW, DVP 12bits data mode
+#define	RB_DVP_JPEG				0x40					// RW, DVP JPEG mode
+
+/*******************  Bit definition for DVP_CR1 register  ********************/
+#define RB_DVP_DMA_EN			0x01					// RW, DVP dma enable
+#define RB_DVP_ALL_CLR			0x02					// RW, DVP all clear, high action
+#define	RB_DVP_RCV_CLR			0x04					// RW, DVP receive logic clear, high action
+#define RB_DVP_BUF_TOG			0x08					// RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0
+#define RB_DVP_CM				0x10					// RW, DVP capture mode
+#define	RB_DVP_CROP				0x20					// RW, DVP Crop feature enable
+#define RB_DVP_FCRC				0xC0					// RW, DVP frame capture rate control: 
+#define		DVP_RATE_100P		0x00					//00 = every frame captured (100%) 
+#define		DVP_RATE_50P		0x40					//01 = every alternate frame captured (50%)
+#define		DVP_RATE_25P		0x80					//10 = one frame in four frame captured (25%)
+
+/*******************  Bit definition for DVP_IER register  ********************/
+#define	RB_DVP_IE_STR_FRM		0x01					// RW, DVP frame start interrupt enable
+#define	RB_DVP_IE_ROW_DONE		0x02					// RW, DVP row received done interrupt enable
+#define RB_DVP_IE_FRM_DONE		0x04					// RW, DVP frame received done interrupt enable
+#define	RB_DVP_IE_FIFO_OV		0x08					// RW, DVP receive fifo overflow interrupt enable	
+#define RB_DVP_IE_STP_FRM		0x10					// RW, DVP frame stop interrupt enable				
+
+/*******************  Bit definition for DVP_IFR register  ********************/
+#define RB_DVP_IF_STR_FRM	    0x01				    // RW1, interrupt flag for DVP frame start
+#define RB_DVP_IF_ROW_DONE		0x02				    // RW1, interrupt flag for DVP row receive done
+#define RB_DVP_IF_FRM_DONE		0x04				    // RW1, interrupt flag for DVP frame receive done
+#define RB_DVP_IF_FIFO_OV		0x08				    // RW1, interrupt flag for DVP receive fifo overflow
+#define RB_DVP_IF_STP_FRM		0x10				    // RW1, interrupt flag for DVP frame stop
+
+/*******************  Bit definition for DVP_STATUS register  ********************/
+#define RB_DVP_FIFO_RDY			0x01					// RO, DVP receive fifo ready
+#define RB_DVP_FIFO_FULL		0x02					// RO, DVP receive fifo full
+#define RB_DVP_FIFO_OV			0x04					// RO, DVP receive fifo overflow
+#define RB_DVP_MSK_FIFO_CNT		0x70					// RO, DVP receive fifo count
+
+
+
+#include "ch32v30x_conf.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_adc.h

@@ -0,0 +1,228 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_adc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      ADC firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_ADC_H
+#define __CH32V30x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+/* ADC Init structure definition */
+typedef struct
+{
+  uint32_t ADC_Mode;                      /* Configures the ADC to operate in independent or
+                                             dual mode. 
+                                             This parameter can be a value of @ref ADC_mode */
+
+  FunctionalState ADC_ScanConvMode;       /* Specifies whether the conversion is performed in
+                                             Scan (multichannels) or Single (one channel) mode.
+                                             This parameter can be set to ENABLE or DISABLE */
+
+  FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
+                                             Continuous or Single mode.
+                                             This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ADC_ExternalTrigConv;          /* Defines the external trigger used to start the analog
+                                             to digital conversion of regular channels. This parameter
+                                             can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+  uint32_t ADC_DataAlign;                 /* Specifies whether the ADC data alignment is left or right.
+                                             This parameter can be a value of @ref ADC_data_align */
+
+  uint8_t ADC_NbrOfChannel;               /* Specifies the number of ADC channels that will be converted
+                                               using the sequencer for regular channel group.
+                                               This parameter must range from 1 to 16. */
+
+  uint32_t  ADC_OutputBuffer;             /* Specifies whether the ADC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref ADC_OutputBuffer */
+
+  uint32_t ADC_Pga;                       /* Specifies the PGA gain multiple.
+                                               This parameter can be a value of @ref ADC_Pga */
+}ADC_InitTypeDef;
+
+/* ADC_mode */
+#define ADC_Mode_Independent                        ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                     ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig                ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl             ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl             ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                        ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                          ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                         ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                         ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                          ((uint32_t)0x00090000)
+
+/* ADC_external_trigger_sources_for_regular_channels_conversion */
+#define ADC_ExternalTrigConv_T1_CC1                 ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigConv_T1_CC2                 ((uint32_t)0x00020000) 
+#define ADC_ExternalTrigConv_T2_CC2                 ((uint32_t)0x00060000) 
+#define ADC_ExternalTrigConv_T3_TRGO                ((uint32_t)0x00080000) 
+#define ADC_ExternalTrigConv_T4_CC4                 ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO     ((uint32_t)0x000C0000) 
+
+#define ADC_ExternalTrigConv_T1_CC3                 ((uint32_t)0x00040000) 
+#define ADC_ExternalTrigConv_None                   ((uint32_t)0x000E0000) 
+
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x00020000) 
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x00060000) 
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x00080000)
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x000A0000) 
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x000C0000) 
+
+
+/* ADC_data_align */
+#define ADC_DataAlign_Right                         ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                          ((uint32_t)0x00000800)
+
+/* ADC_channels */
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+
+/*ADC_output_buffer*/
+#define ADC_OutputBuffer_Enable                     ((uint32_t)0x04000000)
+#define ADC_OutputBuffer_Disable                    ((uint32_t)0x00000000)
+
+/*ADC_pga*/
+#define ADC_Pga_1                                   ((uint32_t)0x00000000)
+#define ADC_Pga_4                                   ((uint32_t)0x08000000)
+#define ADC_Pga_16                                  ((uint32_t)0x10000000)
+#define ADC_Pga_64                                  ((uint32_t)0x18000000)
+
+/* ADC_sampling_time */
+#define ADC_SampleTime_1Cycles5                     ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                     ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                    ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                    ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                    ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                    ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                    ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                   ((uint8_t)0x07)
+
+/* ADC_external_trigger_sources_for_injected_channels_conversion */
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00002000) 
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00003000) 
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00004000) 
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00005000) 
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) 
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00000000) 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00001000) 
+#define ADC_ExternalTrigInjecConv_None              ((uint32_t)0x00007000) 
+
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00002000) 
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x00003000) 
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x00004000) 
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x00005000)
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x00006000) 
+
+
+/* ADC_injected_channel_selection */
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+
+/* ADC_analog_watchdog_selection */
+#define ADC_AnalogWatchdog_SingleRegEnable          ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable        ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable   ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable             ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable           ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable     ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                     ((uint32_t)0x00000000)
+
+/* ADC_interrupts_definition */
+#define ADC_IT_EOC                                  ((uint16_t)0x0220)
+#define ADC_IT_AWD                                  ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                 ((uint16_t)0x0480)
+
+/* ADC_flags_definition */
+#define ADC_FLAG_AWD                                ((uint8_t)0x01)
+#define ADC_FLAG_EOC                                ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                               ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                              ((uint8_t)0x08)
+#define ADC_FLAG_STRT                               ((uint8_t)0x10)
+
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+s32 TempSensor_Volt_To_Temper(s32 Value);
+void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+int16_t Get_CalibrationValue(ADC_TypeDef* ADCx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_bkp.h

@@ -0,0 +1,97 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_bkp.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      BKP firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_BKP_H
+#define __CH32V30x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* Tamper_Pin_active_level */
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+
+/* RTC_output_source_to_output_on_the_Tamper_pin */
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+	 
+/* Data_Backup_Register */
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_can.h

@@ -0,0 +1,366 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_can.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      CAN firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_CAN_H
+#define __CH32V30x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* CAN init structure definition */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /* Specifies the length of a time quantum. 
+                               It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /* Specifies the CAN operating mode.
+                               This parameter can be a value of 
+                              @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /* Specifies the maximum number of time quanta 
+                               the CAN hardware is allowed to lengthen or 
+                               shorten a bit to perform resynchronization.
+                               This parameter can be a value of 
+                               @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /* Specifies the number of time quanta in Bit 
+                               Segment 1. This parameter can be a value of 
+                               @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /* Specifies the number of time quanta in Bit 
+                               Segment 2.
+                               This parameter can be a value of 
+                               @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /* Enable or disable the time triggered 
+                               communication mode. This parameter can be set 
+                               either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /* Enable or disable the automatic bus-off 
+                                management. This parameter can be set either 
+                                to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /* Enable or disable the automatic wake-up mode. 
+                                This parameter can be set either to ENABLE or 
+                                DISABLE. */
+
+  FunctionalState CAN_NART;  /* Enable or disable the no-automatic 
+                                retransmission mode. This parameter can be 
+                                set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /* Enable or disable the Receive FIFO Locked mode.
+                                This parameter can be set either to ENABLE 
+                                or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /* Enable or disable the transmit FIFO priority.
+                                This parameter can be set either to ENABLE 
+                                or DISABLE. */
+} CAN_InitTypeDef;
+
+/* CAN filter init structure definition */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /* Specifies the filter identification number (MSBs for a 32-bit
+                                            configuration, first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /* Specifies the filter identification number (LSBs for a 32-bit
+                                            configuration, second one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /* Specifies the filter mask number or identification number,
+                                            according to the mode (MSBs for a 32-bit configuration,
+                                            first one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /* Specifies the filter mask number or identification number,
+                                            according to the mode (LSBs for a 32-bit configuration,
+                                            second one for a 16-bit configuration).
+                                            This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                            This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /* Specifies the filter mode to be initialized.
+                                            This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /* Specifies the filter scale.
+                                            This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
+                                            This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/* CAN Tx message structure definition */
+typedef struct
+{
+  uint32_t StdId;  /* Specifies the standard identifier.
+                      This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /* Specifies the extended identifier.
+                      This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /* Specifies the type of identifier for the message that 
+                      will be transmitted. This parameter can be a value 
+                      of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /* Specifies the type of frame for the message that will 
+                      be transmitted. This parameter can be a value of 
+                      @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /* Specifies the length of the frame that will be 
+                      transmitted. This parameter can be a value between 
+                      0 to 8 */
+
+  uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 
+                       to 0xFF. */
+} CanTxMsg;
+
+/* CAN Rx message structure definition  */
+typedef struct
+{
+  uint32_t StdId;  /* Specifies the standard identifier.
+                      This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /* Specifies the extended identifier.
+                      This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /* Specifies the type of identifier for the message that 
+                      will be received. This parameter can be a value of 
+                      @ref CAN_identifier_type */
+
+  uint8_t RTR;     /* Specifies the type of frame for the received message.
+                      This parameter can be a value of 
+                      @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /* Specifies the length of the frame that will be received.
+                      This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to 
+                      0xFF. */
+
+  uint8_t FMI;     /* Specifies the index of the filter the message stored in 
+                      the mailbox passes through. This parameter can be a 
+                      value between 0 to 0xFF */
+} CanRxMsg;
+
+/* CAN_sleep_constants */
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /* CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /* CAN initialization OK */
+
+/* CAN_Mode */
+#define CAN_Mode_Normal                    ((uint8_t)0x00)  /* normal mode */
+#define CAN_Mode_LoopBack                  ((uint8_t)0x01)  /* loopback mode */
+#define CAN_Mode_Silent                    ((uint8_t)0x02)  /* silent mode */
+#define CAN_Mode_Silent_LoopBack           ((uint8_t)0x03)  /* loopback combined with silent mode */
+
+/* CAN_Operating_Mode */
+#define CAN_OperatingMode_Initialization   ((uint8_t)0x00) /* Initialization mode */
+#define CAN_OperatingMode_Normal           ((uint8_t)0x01) /* Normal mode */
+#define CAN_OperatingMode_Sleep            ((uint8_t)0x02) /* sleep mode */
+
+/* CAN_Mode_Status */
+#define CAN_ModeStatus_Failed              ((uint8_t)0x00)                /* CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success             ((uint8_t)!CAN_ModeStatus_Failed)   /* CAN entering the specific mode Succeed */
+
+/* CAN_synchronisation_jump_width */
+#define CAN_SJW_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_SJW_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_SJW_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_SJW_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_1 */
+#define CAN_BS1_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_BS1_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_BS1_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_BS1_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+#define CAN_BS1_5tq                        ((uint8_t)0x04)  /* 5 time quantum */
+#define CAN_BS1_6tq                        ((uint8_t)0x05)  /* 6 time quantum */
+#define CAN_BS1_7tq                        ((uint8_t)0x06)  /* 7 time quantum */
+#define CAN_BS1_8tq                        ((uint8_t)0x07)  /* 8 time quantum */
+#define CAN_BS1_9tq                        ((uint8_t)0x08)  /* 9 time quantum */
+#define CAN_BS1_10tq                       ((uint8_t)0x09)  /* 10 time quantum */
+#define CAN_BS1_11tq                       ((uint8_t)0x0A)  /* 11 time quantum */
+#define CAN_BS1_12tq                       ((uint8_t)0x0B)  /* 12 time quantum */
+#define CAN_BS1_13tq                       ((uint8_t)0x0C)  /* 13 time quantum */
+#define CAN_BS1_14tq                       ((uint8_t)0x0D)  /* 14 time quantum */
+#define CAN_BS1_15tq                       ((uint8_t)0x0E)  /* 15 time quantum */
+#define CAN_BS1_16tq                       ((uint8_t)0x0F)  /* 16 time quantum */
+
+/* CAN_time_quantum_in_bit_segment_2 */
+#define CAN_BS2_1tq                        ((uint8_t)0x00)  /* 1 time quantum */
+#define CAN_BS2_2tq                        ((uint8_t)0x01)  /* 2 time quantum */
+#define CAN_BS2_3tq                        ((uint8_t)0x02)  /* 3 time quantum */
+#define CAN_BS2_4tq                        ((uint8_t)0x03)  /* 4 time quantum */
+#define CAN_BS2_5tq                        ((uint8_t)0x04)  /* 5 time quantum */
+#define CAN_BS2_6tq                        ((uint8_t)0x05)  /* 6 time quantum */
+#define CAN_BS2_7tq                        ((uint8_t)0x06)  /* 7 time quantum */
+#define CAN_BS2_8tq                        ((uint8_t)0x07)  /* 8 time quantum */
+
+/* CAN_filter_mode */
+#define CAN_FilterMode_IdMask              ((uint8_t)0x00)  /* identifier/mask mode */
+#define CAN_FilterMode_IdList              ((uint8_t)0x01)  /* identifier list mode */
+
+/* CAN_filter_scale */
+#define CAN_FilterScale_16bit              ((uint8_t)0x00) /* Two 16-bit filters */
+#define CAN_FilterScale_32bit              ((uint8_t)0x01) /* One 32-bit filter */
+
+/* CAN_filter_FIFO */
+#define CAN_Filter_FIFO0                   ((uint8_t)0x00)  /* Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1                   ((uint8_t)0x01)  /* Filter FIFO 1 assignment for filter x */
+
+/* CAN_identifier_type */
+#define CAN_Id_Standard                    ((uint32_t)0x00000000)  /* Standard Id */
+#define CAN_Id_Extended                    ((uint32_t)0x00000004)  /* Extended Id */
+
+/* CAN_remote_transmission_request */
+#define CAN_RTR_Data                       ((uint32_t)0x00000000)  /* Data frame */
+#define CAN_RTR_Remote                     ((uint32_t)0x00000002)  /* Remote frame */
+
+/* CAN_transmit_constants */
+#define CAN_TxStatus_Failed                ((uint8_t)0x00)/* CAN transmission failed */
+#define CAN_TxStatus_Ok                    ((uint8_t)0x01) /* CAN transmission succeeded */
+#define CAN_TxStatus_Pending               ((uint8_t)0x02) /* CAN transmission pending */
+#define CAN_TxStatus_NoMailBox             ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
+
+/* CAN_receive_FIFO_number_constants */
+#define CAN_FIFO0                          ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
+#define CAN_FIFO1                          ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
+
+/* CAN_sleep_constants */
+#define CAN_Sleep_Failed                   ((uint8_t)0x00) /* CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok                       ((uint8_t)0x01) /* CAN entered the sleep mode */
+
+/* CAN_wake_up_constants */
+#define CAN_WakeUp_Failed                  ((uint8_t)0x00) /* CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok                      ((uint8_t)0x01) /* CAN leaved the sleep mode */
+ 
+/* CAN_Error_Code_constants */                                                               
+#define CAN_ErrorCode_NoErr                ((uint8_t)0x00) /* No Error */ 
+#define	CAN_ErrorCode_StuffErr             ((uint8_t)0x10) /* Stuff Error */ 
+#define	CAN_ErrorCode_FormErr              ((uint8_t)0x20) /* Form Error */ 
+#define	CAN_ErrorCode_ACKErr               ((uint8_t)0x30) /* Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr      ((uint8_t)0x40) /* Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr       ((uint8_t)0x50) /* Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr               ((uint8_t)0x60) /* CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr       ((uint8_t)0x70) /* Software Set Error */ 
+
+
+/* CAN_flags */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0                     ((uint32_t)0x38000001) /* Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1                     ((uint32_t)0x38000100) /* Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2                     ((uint32_t)0x38010000) /* Request MailBox2 Flag */
+
+/* Receive Flags */ 
+#define CAN_FLAG_FMP0                      ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0                       ((uint32_t)0x32000008) /* FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0                      ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1                      ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1                       ((uint32_t)0x34000008) /* FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1                      ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU                       ((uint32_t)0x31000008) /* Wake up Flag */
+#define CAN_FLAG_SLAK                      ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
+
+/* Error Flags */
+#define CAN_FLAG_EWG                       ((uint32_t)0x10F00001) /* Error Warning Flag   */
+#define CAN_FLAG_EPV                       ((uint32_t)0x10F00002) /* Error Passive Flag   */
+#define CAN_FLAG_BOF                       ((uint32_t)0x10F00004) /* Bus-Off Flag         */
+#define CAN_FLAG_LEC                       ((uint32_t)0x30F00070) /* Last error code Flag */
+
+
+/* CAN_interrupts */
+#define CAN_IT_TME                         ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                        ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                         ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                        ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                        ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                         ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                        ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                         ((uint32_t)0x00010000) /* Wake-up Interrupt*/
+#define CAN_IT_SLK                         ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                         ((uint32_t)0x00000100) /* Error warning Interrupt*/
+#define CAN_IT_EPV                         ((uint32_t)0x00000200) /* Error passive Interrupt*/
+#define CAN_IT_BOF                         ((uint32_t)0x00000400) /* Bus-off Interrupt*/
+#define CAN_IT_LEC                         ((uint32_t)0x00000800) /* Last error code Interrupt*/
+#define CAN_IT_ERR                         ((uint32_t)0x00008000) /* Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0    CAN_IT_TME
+#define CAN_IT_RQCP1    CAN_IT_TME
+#define CAN_IT_RQCP2    CAN_IT_TME
+
+/* CAN_Legacy */
+#define CANINITFAILED               CAN_InitStatus_Failed
+#define CANINITOK                   CAN_InitStatus_Success
+#define CAN_FilterFIFO0             CAN_Filter_FIFO0
+#define CAN_FilterFIFO1             CAN_Filter_FIFO1
+#define CAN_ID_STD                  CAN_Id_Standard           
+#define CAN_ID_EXT                  CAN_Id_Extended
+#define CAN_RTR_DATA                CAN_RTR_Data         
+#define CAN_RTR_REMOTE              CAN_RTR_Remote
+#define CANTXFAILE                  CAN_TxStatus_Failed
+#define CANTXOK                     CAN_TxStatus_Ok
+#define CANTXPENDING                CAN_TxStatus_Pending
+#define CAN_NO_MB                   CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED              CAN_Sleep_Failed
+#define CANSLEEPOK                  CAN_Sleep_Ok
+#define CANWAKEUPFAILED             CAN_WakeUp_Failed        
+#define CANWAKEUPOK                 CAN_WakeUp_Ok        
+
+
+void CAN_DeInit(CAN_TypeDef* CANx); 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_crc.h

@@ -0,0 +1,37 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_crc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      CRC firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_CRC_H
+#define __CH32V30x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+	 
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_dac.h

@@ -0,0 +1,120 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dac.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DAC firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_DAC_H
+#define __CH32V30x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* DAC Init structure definition */
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /* Specifies the external trigger for the selected DAC channel.
+                                                This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /* Specifies whether DAC channel noise waves or triangle waves
+                                                are generated, or whether no wave is generated.
+                                                This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or
+                                                the maximum amplitude triangle generation for the DAC channel. 
+                                                This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /* Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+
+/* DAC_trigger_selection */
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                     has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                     only in High-density devices*/
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */
+
+/* DAC_wave_generation */
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+
+
+/* DAC_lfsrunmask_triangleamplitude */
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */
+
+/* DAC_output_buffer */
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+
+/* DAC_Channel_selection */
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+																 
+/* DAC_data_alignment */
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+
+/* DAC_wave_generation */
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_dbgmcu.h

@@ -0,0 +1,35 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dbgmcu.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DBGMCU firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_DBGMCU_H
+#define __CH32V30x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_dma.h

@@ -0,0 +1,268 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dma.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DMA firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/  
+#ifndef __CH32V30x_DMA_H
+#define __CH32V30x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+ 
+/* DMA Init structure definition */
+typedef struct
+{
+  uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
+
+  uint32_t DMA_MemoryBaseAddr;     /* Specifies the memory base address for DMAy Channelx. */
+
+  uint32_t DMA_DIR;                /* Specifies if the peripheral is the source or destination.
+                                      This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /* Specifies the buffer size, in data unit, of the specified Channel. 
+                                      The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                      or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /* Specifies whether the Peripheral address register is incremented or not.
+                                      This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /* Specifies whether the memory address register is incremented or not.
+                                      This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /* Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /* Specifies the operation mode of the DMAy Channelx.
+                                      This parameter can be a value of @ref DMA_circular_normal_mode.
+                                      @note: The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Channel */
+
+  uint32_t DMA_Priority;           /* Specifies the software priority for the DMAy Channelx.
+                                      This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_M2M;                /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                                      This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* DMA_data_transfer_direction */
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_incremented_mode */
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+											
+/* DMA_memory_incremented_mode */
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+										
+/* DMA_peripheral_data_size */
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+
+/* DMA_memory_data_size */
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+
+/* DMA_circular_normal_mode */
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+
+/* DMA_priority_level */
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+/* DMA_memory_to_memory */
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+
+/* DMA_interrupts_definition */
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+#define DMA2_IT_GL6                        ((uint32_t)0x10100000)
+#define DMA2_IT_TC6                        ((uint32_t)0x10200000)
+#define DMA2_IT_HT6                        ((uint32_t)0x10400000)
+#define DMA2_IT_TE6                        ((uint32_t)0x10800000)
+#define DMA2_IT_GL7                        ((uint32_t)0x11000000)
+#define DMA2_IT_TC7                        ((uint32_t)0x12000000)
+#define DMA2_IT_HT7                        ((uint32_t)0x14000000)
+#define DMA2_IT_TE7                        ((uint32_t)0x18000000)
+
+#define DMA2_IT_GL8                        ((uint32_t)0x20000001)
+#define DMA2_IT_TC8                        ((uint32_t)0x20000002)
+#define DMA2_IT_HT8                        ((uint32_t)0x20000004)
+#define DMA2_IT_TE8                        ((uint32_t)0x20000008)
+#define DMA2_IT_GL9                        ((uint32_t)0x20000010)
+#define DMA2_IT_TC9                        ((uint32_t)0x20000020)
+#define DMA2_IT_HT9                        ((uint32_t)0x20000040)
+#define DMA2_IT_TE9                        ((uint32_t)0x20000080)
+#define DMA2_IT_GL10                       ((uint32_t)0x20000100)
+#define DMA2_IT_TC10                       ((uint32_t)0x20000200)
+#define DMA2_IT_HT10                       ((uint32_t)0x20000400)
+#define DMA2_IT_TE10                       ((uint32_t)0x20000800)
+#define DMA2_IT_GL11                       ((uint32_t)0x20001000)
+#define DMA2_IT_TC11                       ((uint32_t)0x20002000)
+#define DMA2_IT_HT11                       ((uint32_t)0x20004000)
+#define DMA2_IT_TE11                       ((uint32_t)0x20008000)
+
+/* DMA_flags_definition */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+#define DMA2_FLAG_GL6                      ((uint32_t)0x10100000)
+#define DMA2_FLAG_TC6                      ((uint32_t)0x10200000)
+#define DMA2_FLAG_HT6                      ((uint32_t)0x10400000)
+#define DMA2_FLAG_TE6                      ((uint32_t)0x10800000)
+#define DMA2_FLAG_GL7                      ((uint32_t)0x11000000)
+#define DMA2_FLAG_TC7                      ((uint32_t)0x12000000)
+#define DMA2_FLAG_HT7                      ((uint32_t)0x14000000)
+#define DMA2_FLAG_TE7                      ((uint32_t)0x18000000)
+
+#define DMA2_FLAG_GL8                      ((uint32_t)0x20000001)
+#define DMA2_FLAG_TC8                      ((uint32_t)0x20000002)
+#define DMA2_FLAG_HT8                      ((uint32_t)0x20000004)
+#define DMA2_FLAG_TE8                      ((uint32_t)0x20000008)
+#define DMA2_FLAG_GL9                      ((uint32_t)0x20000010)
+#define DMA2_FLAG_TC9                      ((uint32_t)0x20000020)
+#define DMA2_FLAG_HT9                      ((uint32_t)0x20000040)
+#define DMA2_FLAG_TE9                      ((uint32_t)0x20000080)
+#define DMA2_FLAG_GL10                     ((uint32_t)0x20000100)
+#define DMA2_FLAG_TC10                     ((uint32_t)0x20000200)
+#define DMA2_FLAG_HT10                     ((uint32_t)0x20000400)
+#define DMA2_FLAG_TE10                     ((uint32_t)0x20000800)
+#define DMA2_FLAG_GL11                     ((uint32_t)0x20001000)
+#define DMA2_FLAG_TC11                     ((uint32_t)0x20002000)
+#define DMA2_FLAG_HT11                     ((uint32_t)0x20004000)
+#define DMA2_FLAG_TE11                     ((uint32_t)0x20008000)
+
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_dvp.h

@@ -0,0 +1,67 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dvp.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      DVP firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_DVP_H
+#define __CH32V30x_DVP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* DVP Data Mode */
+typedef enum
+{
+ Video_Mode = 0,
+ JPEG_Mode,
+}DVP_Data_ModeTypeDef;
+
+
+/* DVP DMA */
+typedef enum
+{
+ DVP_DMA_Disable = 0,
+ DVP_DMA_Enable,
+}DVP_DMATypeDef;
+
+/* DVP FLAG and FIFO Reset */
+typedef enum
+{
+ DVP_FLAG_FIFO_RESET_Disable = 0,
+ DVP_FLAG_FIFO_RESET_Enable,
+}DVP_FLAG_FIFO_RESETTypeDef;
+
+/* DVP RX Reset */
+typedef enum
+{
+ DVP_RX_RESET_Disable = 0,
+ DVP_RX_RESET_Enable,
+}DVP_RX_RESETTypeDef;
+
+
+
+void DVP_INTCfg( uint8_t s,  uint8_t i );
+void DVP_Mode( uint8_t s,  DVP_Data_ModeTypeDef i);
+void DVP_Cfg( DVP_DMATypeDef s,  DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_eth.h

@@ -0,0 +1,1331 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_eth.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the
+*                      ETH firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_ETH_H
+#define __CH32V30x_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+#define PHY_10BASE_T_LINKED   1
+#define PHY_10BASE_T_NOT_LINKED   0
+
+#define DMA_TPS_Mask      ((uint32_t)0x00700000) 	
+#define DMA_RPS_Mask      ((uint32_t)0x000E0000) 	
+
+/* ETH Init structure definition */
+typedef struct {
+    uint32_t             ETH_AutoNegotiation;             /* Selects or not the AutoNegotiation mode for the external PHY
+                                                             The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                             and the mode (half/full-duplex).
+                                                             This parameter can be a value of @ref ETH_AutoNegotiation */
+
+    uint32_t             ETH_Watchdog;                    /* Selects or not the Watchdog timer
+                                                             When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                             When disabled, the MAC can receive up to 16384 bytes.
+                                                             This parameter can be a value of @ref ETH_watchdog */
+
+    uint32_t             ETH_Jabber;                      /* Selects or not Jabber timer
+                                                             When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                             When disabled, the MAC can send up to 16384 bytes.
+                                                             This parameter can be a value of @ref ETH_Jabber */
+
+    uint32_t             ETH_InterFrameGap;               /* Selects the minimum IFG between frames during transmission
+                                                             This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+    uint32_t             ETH_CarrierSense;                /* Selects or not the Carrier Sense
+                                                             This parameter can be a value of @ref ETH_Carrier_Sense */
+
+    uint32_t             ETH_Speed;                       /* Sets the Ethernet speed: 10/100 Mbps
+                                                             This parameter can be a value of @ref ETH_Speed */
+
+    uint32_t             ETH_ReceiveOwn;                  /* Selects or not the ReceiveOwn
+                                                             ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                             in Half-Duplex mode
+                                                             This parameter can be a value of @ref ETH_Receive_Own */
+
+    uint32_t             ETH_LoopbackMode;                /* Selects or not the internal MAC MII Loopback mode
+                                                             This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+    uint32_t             ETH_Mode;                        /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                             This parameter can be a value of @ref ETH_Duplex_Mode */
+
+    uint32_t             ETH_ChecksumOffload;             /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                             This parameter can be a value of @ref ETH_Checksum_Offload */
+
+    uint32_t             ETH_RetryTransmission;           /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                             when a colision occurs (Half-Duplex mode)
+                                                             This parameter can be a value of @ref ETH_Retry_Transmission */
+
+    uint32_t             ETH_AutomaticPadCRCStrip;        /* Selects or not the Automatic MAC Pad/CRC Stripping
+                                                             This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+    uint32_t             ETH_BackOffLimit;                /* Selects the BackOff limit value
+                                                             This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+    uint32_t             ETH_DeferralCheck;               /* Selects or not the deferral check function (Half-Duplex mode)
+                                                             This parameter can be a value of @ref ETH_Deferral_Check */
+
+    uint32_t             ETH_ReceiveAll;                  /* Selects or not all frames reception by the MAC (No fitering)
+                                                             This parameter can be a value of @ref ETH_Receive_All */
+
+    uint32_t             ETH_SourceAddrFilter;            /* Selects the Source Address Filter mode
+                                                             This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+    uint32_t             ETH_PassControlFrames;           /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+                                                             This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+    uint32_t             ETH_BroadcastFramesReception;    /* Selects or not the reception of Broadcast Frames
+                                                             This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+    uint32_t             ETH_DestinationAddrFilter;       /* Sets the destination filter mode for both unicast and multicast frames
+                                                             This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+    uint32_t             ETH_PromiscuousMode;             /* Selects or not the Promiscuous Mode
+                                                             This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+    uint32_t             ETH_MulticastFramesFilter;       /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                             This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+    uint32_t             ETH_UnicastFramesFilter;         /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                             This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+    uint32_t             ETH_HashTableHigh;               /* This field holds the higher 32 bits of Hash table.  */
+
+    uint32_t             ETH_HashTableLow;                /* This field holds the lower 32 bits of Hash table.  */
+
+    uint32_t             ETH_PauseTime;                   /* This field holds the value to be used in the Pause Time field in the
+                                                             transmit control frame */
+
+    uint32_t             ETH_ZeroQuantaPause;             /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
+                                                             This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+    uint32_t             ETH_PauseLowThreshold;           /* This field configures the threshold of the PAUSE to be checked for
+                                                             automatic retransmission of PAUSE Frame
+                                                             This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+                                                           
+    uint32_t             ETH_UnicastPauseFrameDetect;     /* Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                             unicast address and unique multicast address)
+                                                             This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+    uint32_t             ETH_ReceiveFlowControl;          /* Enables or disables the MAC to decode the received Pause frame and
+                                                             disable its transmitter for a specified time (Pause Time)
+                                                             This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+    uint32_t             ETH_TransmitFlowControl;         /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                             or the MAC back-pressure operation (Half-Duplex mode)
+                                                             This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+    uint32_t             ETH_VLANTagComparison;           /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                             comparison and filtering
+                                                             This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+    uint32_t             ETH_VLANTagIdentifier;           /* Holds the VLAN tag identifier for receive frames */
+
+    uint32_t             ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
+                                                             This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 
+
+    uint32_t             ETH_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
+                                                             This parameter can be a value of @ref ETH_Receive_Store_Forward */ 
+
+    uint32_t             ETH_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
+                                                             This parameter can be a value of @ref ETH_Flush_Received_Frame */ 
+
+    uint32_t             ETH_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
+                                                             This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 
+
+    uint32_t             ETH_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
+                                                             This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+    uint32_t             ETH_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
+                                                             This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+    uint32_t             ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                             and length less than 64 bytes) including pad-bytes and CRC)
+                                                             This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+    uint32_t             ETH_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
+                                                             This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+    uint32_t             ETH_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                             frame of Transmit data even before obtaining the status for the first frame.
+                                                             This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+    uint32_t             ETH_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
+                                                             This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+    uint32_t             ETH_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
+                                                             This parameter can be a value of @ref ETH_Fixed_Burst */
+                       
+    uint32_t             ETH_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+                                                             This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 
+
+    uint32_t             ETH_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+                                                             This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */                                                   
+
+    uint32_t             ETH_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
+
+    uint32_t             ETH_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
+                                                             This parameter can be a value of @ref ETH_DMA_Arbitration */  
+}ETH_InitTypeDef;
+
+
+
+/* ETH delay.Just for Ethernet */
+#define _eth_delay_    ETH_Delay       /* Default _eth_delay_ function with less precise timing */
+
+/* definition for Ethernet frame */
+#define ETH_MAX_PACKET_SIZE    1520    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               14    /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                   4    /* Ethernet CRC */
+#define ETH_EXTRA                 2    /* Extra bytes in some cases */
+#define VLAN_TAG                  4    /* optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD          46    /* Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD        1500    /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD    9000    /* Jumbo frame payload size */
+
+/* ETH DMA structure definition */
+typedef struct
+{
+  uint32_t   Status;                /* Status */
+  uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
+  uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
+  uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
+} ETH_DMADESCTypeDef;
+
+/**
+   DMA Tx Desciptor
+  -----------------------------------------------------------------------------------------------
+  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                         Buffer1 Address [31:0]                                         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 |                   Buffer2 Address [31:0] / Next Desciptor Address [31:0]               |
+  ------------------------------------------------------------------------------------------------
+*/
+
+
+/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/
+#define ETH_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /* OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATxDesc_IC                      ((uint32_t)0x40000000)  /* Interrupt on Completion */
+#define ETH_DMATxDesc_LS                      ((uint32_t)0x20000000)  /* Last Segment */
+#define ETH_DMATxDesc_FS                      ((uint32_t)0x10000000)  /* First Segment */
+#define ETH_DMATxDesc_DC                      ((uint32_t)0x08000000)  /* Disable CRC */
+#define ETH_DMATxDesc_DP                      ((uint32_t)0x04000000)  /* Disable Padding */
+#define ETH_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /* Transmit Time Stamp Enable */
+#define ETH_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /* Checksum Insertion Control: 4 cases */
+#define ETH_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /* Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /* IPV4 header Checksum Insertion */
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /* TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATxDesc_TER                     ((uint32_t)0x00200000)  /* Transmit End of Ring */
+#define ETH_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /* Second Address Chained */
+#define ETH_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /* Tx Time Stamp Status */
+#define ETH_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /* IP Header Error */
+#define ETH_DMATxDesc_ES                      ((uint32_t)0x00008000)  /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATxDesc_JT                      ((uint32_t)0x00004000)  /* Jabber Timeout */
+#define ETH_DMATxDesc_FF                      ((uint32_t)0x00002000)  /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /* Payload Checksum Error */
+#define ETH_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /* Loss of Carrier: carrier lost during tramsmission */
+#define ETH_DMATxDesc_NC                      ((uint32_t)0x00000400)  /* No Carrier: no carrier signal from the tranceiver */
+#define ETH_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /* Late Collision: transmission aborted due to collision */
+#define ETH_DMATxDesc_EC                      ((uint32_t)0x00000100)  /* Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATxDesc_VF                      ((uint32_t)0x00000080)  /* VLAN Frame */
+#define ETH_DMATxDesc_CC                      ((uint32_t)0x00000078)  /* Collision Count */
+#define ETH_DMATxDesc_ED                      ((uint32_t)0x00000004)  /* Excessive Deferral */
+#define ETH_DMATxDesc_UF                      ((uint32_t)0x00000002)  /* Underflow Error: late data arrival from the memory */
+#define ETH_DMATxDesc_DB                      ((uint32_t)0x00000001)  /* Deferred Bit */
+
+/* Field definition of TDES1 register */
+#define ETH_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /* Transmit Buffer2 Size */
+#define ETH_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /* Transmit Buffer1 Size */
+
+/* Field definition of TDES2 register */
+#define ETH_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+/* Field definition of TDES3 register */
+#define ETH_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+/**
+  DMA Rx Desciptor
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES0 | OWN(31) |                                             Status [30:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                       Buffer1 Address [31:0]                                                 |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 |                          Buffer2 Address [31:0] / Next Desciptor Address [31:0]                              |
+  ----------------------------------------------------------------------------------------------------------------------
+*/
+
+/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */
+#define ETH_DMARxDesc_OWN         ((uint32_t)0x80000000)  /* OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARxDesc_AFM         ((uint32_t)0x40000000)  /* DA Filter Fail for the rx frame  */
+#define ETH_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /* Receive descriptor frame length  */
+#define ETH_DMARxDesc_ES          ((uint32_t)0x00008000)  /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARxDesc_DE          ((uint32_t)0x00004000)  /* Desciptor error: no more descriptors for receive frame  */
+#define ETH_DMARxDesc_SAF         ((uint32_t)0x00002000)  /* SA Filter Fail for the received frame */
+#define ETH_DMARxDesc_LE          ((uint32_t)0x00001000)  /* Frame size not matching with length field */
+#define ETH_DMARxDesc_OE          ((uint32_t)0x00000800)  /* Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /* VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARxDesc_FS          ((uint32_t)0x00000200)  /* First descriptor of the frame  */
+#define ETH_DMARxDesc_LS          ((uint32_t)0x00000100)  /* Last descriptor of the frame  */
+#define ETH_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /* IPC Checksum Error: Rx Ipv4 header checksum error   */
+#define ETH_DMARxDesc_LC          ((uint32_t)0x00000040)  /* Late collision occurred during reception   */
+#define ETH_DMARxDesc_FT          ((uint32_t)0x00000020)  /* Frame type - Ethernet, otherwise 802.3    */
+#define ETH_DMARxDesc_RWT         ((uint32_t)0x00000010)  /* Receive Watchdog Timeout: watchdog timer expired during reception    */
+#define ETH_DMARxDesc_RE          ((uint32_t)0x00000008)  /* Receive error: error reported by MII interface  */
+#define ETH_DMARxDesc_DBE         ((uint32_t)0x00000004)  /* Dribble bit error: frame contains non int multiple of 8 bits  */
+#define ETH_DMARxDesc_CE          ((uint32_t)0x00000002)  /* CRC error */
+#define ETH_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/* Bit or field definition of RDES1 register */
+#define ETH_DMARxDesc_DIC   ((uint32_t)0x80000000)  /* Disable Interrupt on Completion */
+#define ETH_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /* Receive Buffer2 Size */
+#define ETH_DMARxDesc_RER   ((uint32_t)0x00008000)  /* Receive End of Ring */
+#define ETH_DMARxDesc_RCH   ((uint32_t)0x00004000)  /* Second Address Chained */
+#define ETH_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /* Receive Buffer1 Size */
+
+/* Field definition of RDES2 register */
+#define ETH_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /* Buffer1 Address Pointer */
+
+/* Field definition of RDES3 register */
+#define ETH_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /* Buffer2 Address Pointer */
+
+/* Timeout threshold of Reading or writing PHY registers */
+#define PHY_READ_TO                     ((uint32_t)0x004FFFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0004FFFF)
+
+/* Delay time after reset PHY */
+#define PHY_ResetDelay                  ((uint32_t)0x000FFFFF) 
+
+/* Delay time after configure PHY */
+#define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)
+
+/* PHY basic register */
+#define PHY_BCR                          0          /*PHY tranceiver Basic Control Register */
+#define PHY_BSR                          1          /*PHY tranceiver Basic Status Register */
+#define PHY_BMCR                         PHY_BCR
+#define PHY_BMSR                         PHY_BSR
+
+/* Bit or field definition for PHY basic control register */
+#define PHY_Reset                       ((uint16_t)0x8000)      /* PHY Reset */
+#define PHY_Loopback                    ((uint16_t)0x4000)      /* Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)      /* Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)      /* Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)      /* Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)      /* Set the half-duplex mode at 10 Mb/s */
+#define PHY_AutoNegotiation             ((uint16_t)0x1000)      /* Enable auto-negotiation function */
+#define PHY_Restart_AutoNegotiation     ((uint16_t)0x0200)      /* Restart auto-negotiation function */
+#define PHY_Powerdown                   ((uint16_t)0x0800)      /* Select the power down mode */
+#define PHY_Isolate                     ((uint16_t)0x0400)      /* Isolate PHY from MII */
+
+/* Bit or field definition for PHY basic status register */
+#define PHY_AutoNego_Complete           ((uint16_t)0x0020)      /* Auto-Negotioation process completed */
+#define PHY_Linked_Status               ((uint16_t)0x0004)      /* Valid link established */
+#define PHY_Jabber_detection            ((uint16_t)0x0002)      /* Jabber condition detected */
+#define PHY_RMII_Mode                   ((uint16_t)0x0020)      /* RMII */
+
+
+/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */
+#define ETH_Internal_Pull_Up_Res_Enable     ((uint32_t)0x00100000)
+#define ETH_Internal_Pull_Up_Res_Disable    ((uint32_t)0x00000000)
+
+/* MAC autoNegotiation enable or disable */
+#define ETH_AutoNegotiation_Enable     ((uint32_t)0x00000001)
+#define ETH_AutoNegotiation_Disable    ((uint32_t)0x00000000)
+
+/* MAC watchdog enable or disable */
+#define ETH_Watchdog_Enable       ((uint32_t)0x00000000)
+#define ETH_Watchdog_Disable      ((uint32_t)0x00800000)
+
+/* Bit description - MAC jabber enable or disable */
+#define ETH_Jabber_Enable    ((uint32_t)0x00000000)
+#define ETH_Jabber_Disable   ((uint32_t)0x00400000)
+
+/* Value of minimum IFG between frames during transmission */
+#define ETH_InterFrameGap_96Bit   ((uint32_t)0x00000000)  /* minimum IFG between frames during transmission is 96Bit */
+#define ETH_InterFrameGap_88Bit   ((uint32_t)0x00020000)  /* minimum IFG between frames during transmission is 88Bit */
+#define ETH_InterFrameGap_80Bit   ((uint32_t)0x00040000)  /* minimum IFG between frames during transmission is 80Bit */
+#define ETH_InterFrameGap_72Bit   ((uint32_t)0x00060000)  /* minimum IFG between frames during transmission is 72Bit */
+#define ETH_InterFrameGap_64Bit   ((uint32_t)0x00080000)  /* minimum IFG between frames during transmission is 64Bit */
+#define ETH_InterFrameGap_56Bit   ((uint32_t)0x000A0000)  /* minimum IFG between frames during transmission is 56Bit */
+#define ETH_InterFrameGap_48Bit   ((uint32_t)0x000C0000)  /* minimum IFG between frames during transmission is 48Bit */
+#define ETH_InterFrameGap_40Bit   ((uint32_t)0x000E0000)  /* minimum IFG between frames during transmission is 40Bit */
+
+/* MAC carrier sense enable or disable */
+#define ETH_CarrierSense_Enable   ((uint32_t)0x00000000)
+#define ETH_CarrierSense_Disable  ((uint32_t)0x00010000)
+
+/* MAC speed */
+#define ETH_Speed_10M        ((uint32_t)0x00000000)
+#define ETH_Speed_100M       ((uint32_t)0x00004000)
+#define ETH_Speed_1000M      ((uint32_t)0x00008000)
+
+/* MAC receive own enable or disable */
+#define ETH_ReceiveOwn_Enable     ((uint32_t)0x00000000)
+#define ETH_ReceiveOwn_Disable    ((uint32_t)0x00002000)
+
+/* MAC Loopback mode enable or disable */
+#define ETH_LoopbackMode_Enable        ((uint32_t)0x00001000)
+#define ETH_LoopbackMode_Disable       ((uint32_t)0x00000000)
+
+/* MAC fullDuplex or halfDuplex */
+#define ETH_Mode_FullDuplex       ((uint32_t)0x00000800)
+#define ETH_Mode_HalfDuplex       ((uint32_t)0x00000000)
+
+/* MAC offload checksum enable or disable */
+#define ETH_ChecksumOffload_Enable     ((uint32_t)0x00000400)
+#define ETH_ChecksumOffload_Disable    ((uint32_t)0x00000000)
+
+/* MAC transmission retry enable or disable */
+#define ETH_RetryTransmission_Enable   ((uint32_t)0x00000000)
+#define ETH_RetryTransmission_Disable  ((uint32_t)0x00000200)
+
+/* MAC automatic pad CRC strip enable or disable */
+#define ETH_AutomaticPadCRCStrip_Enable     ((uint32_t)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable    ((uint32_t)0x00000000)
+
+/* MAC backoff limitation */
+#define ETH_BackOffLimit_10  ((uint32_t)0x00000000)
+#define ETH_BackOffLimit_8   ((uint32_t)0x00000020)
+#define ETH_BackOffLimit_4   ((uint32_t)0x00000040)
+#define ETH_BackOffLimit_1   ((uint32_t)0x00000060)
+
+/* MAC deferral check enable or disable */
+#define ETH_DeferralCheck_Enable       ((uint32_t)0x00000010)
+#define ETH_DeferralCheck_Disable      ((uint32_t)0x00000000)
+
+/* Bit description  : MAC receive all frame enable or disable */
+#define ETH_ReceiveAll_Enable     ((uint32_t)0x80000000)
+#define ETH_ReceiveAll_Disable    ((uint32_t)0x00000000)
+
+/* MAC backoff limitation */
+#define ETH_SourceAddrFilter_Normal_Enable       ((uint32_t)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable      ((uint32_t)0x00000300)
+#define ETH_SourceAddrFilter_Disable             ((uint32_t)0x00000000)
+
+/* MAC Pass control frames */
+#define ETH_PassControlFrames_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
+#define ETH_PassControlFrames_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+
+/* MAC broadcast frames reception */
+#define ETH_BroadcastFramesReception_Enable      ((uint32_t)0x00000000)
+#define ETH_BroadcastFramesReception_Disable     ((uint32_t)0x00000020)
+
+/* MAC destination address filter */
+#define ETH_DestinationAddrFilter_Normal    ((uint32_t)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse   ((uint32_t)0x00000008)
+
+/* MAC Promiscuous mode enable or disable */
+#define ETH_PromiscuousMode_Enable     ((uint32_t)0x00000001)
+#define ETH_PromiscuousMode_Disable    ((uint32_t)0x00000000)
+
+/* MAC multicast frames filter */
+#define ETH_MulticastFramesFilter_PerfectHashTable    ((uint32_t)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable           ((uint32_t)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect             ((uint32_t)0x00000000)
+#define ETH_MulticastFramesFilter_None                ((uint32_t)0x00000010)
+
+/* MAC unicast frames filter */
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable        ((uint32_t)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect          ((uint32_t)0x00000000)
+
+/* Bit description  : MAC zero quanta pause */
+#define ETH_ZeroQuantaPause_Enable     ((uint32_t)0x00000000)
+#define ETH_ZeroQuantaPause_Disable    ((uint32_t)0x00000080)
+
+/* Field description  : MAC pause low threshold */
+#define ETH_PauseLowThreshold_Minus4        ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */
+#define ETH_PauseLowThreshold_Minus28       ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */
+#define ETH_PauseLowThreshold_Minus144      ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */
+#define ETH_PauseLowThreshold_Minus256      ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */
+
+/* MAC unicast pause frame detect enable or disable*/
+#define ETH_UnicastPauseFrameDetect_Enable  ((uint32_t)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
+
+/* MAC receive flow control frame enable or disable */
+#define ETH_ReceiveFlowControl_Enable       ((uint32_t)0x00000004)
+#define ETH_ReceiveFlowControl_Disable      ((uint32_t)0x00000000)
+
+/* MAC transmit flow control enable or disable */
+#define ETH_TransmitFlowControl_Enable      ((uint32_t)0x00000002)
+#define ETH_TransmitFlowControl_Disable     ((uint32_t)0x00000000)
+
+/* MAC VLAN tag comparison */
+#define ETH_VLANTagComparison_12Bit    ((uint32_t)0x00010000)
+#define ETH_VLANTagComparison_16Bit    ((uint32_t)0x00000000)
+
+/* MAC flag */
+#define ETH_MAC_FLAG_TST     ((uint32_t)0x00000200)  /* Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT    ((uint32_t)0x00000040)  /* MMC transmit flag  */
+#define ETH_MAC_FLAG_MMCR    ((uint32_t)0x00000020)  /* MMC receive flag */
+#define ETH_MAC_FLAG_MMC     ((uint32_t)0x00000010)  /* MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT     ((uint32_t)0x00000008)  /* PMT flag (on MAC) */
+
+/* MAC interrupt */
+#define ETH_MAC_IT_TST       ((uint32_t)0x00000200)  /* Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT      ((uint32_t)0x00000040)  /* MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR      ((uint32_t)0x00000020)  /* MMC receive interrupt */
+#define ETH_MAC_IT_MMC       ((uint32_t)0x00000010)  /* MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT       ((uint32_t)0x00000008)  /* PMT interrupt (on MAC) */
+
+/* MAC address */
+#define ETH_MAC_Address0     ((uint32_t)0x00000000)
+#define ETH_MAC_Address1     ((uint32_t)0x00000008)
+#define ETH_MAC_Address2     ((uint32_t)0x00000010)
+#define ETH_MAC_Address3     ((uint32_t)0x00000018)
+
+/* MAC address filter select */
+#define ETH_MAC_AddressFilter_SA       ((uint32_t)0x00000000)
+#define ETH_MAC_AddressFilter_DA       ((uint32_t)0x00000008)
+
+/* MAC address mask */
+#define ETH_MAC_AddressMask_Byte6      ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte5      ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_AddressMask_Byte4      ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_AddressMask_Byte3      ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_AddressMask_Byte2      ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte1      ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          MAC Descriptor Register                                                                                                                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/* DMA descriptor segment */
+#define ETH_DMATxDesc_LastSegment      ((uint32_t)0x40000000)  /* Last Segment */
+#define ETH_DMATxDesc_FirstSegment     ((uint32_t)0x20000000)  /* First Segment */
+
+/* DMA descriptor checksum setting */
+#define ETH_DMATxDesc_ChecksumByPass             ((uint32_t)0x00000000)   /* Checksum engine bypass */
+#define ETH_DMATxDesc_ChecksumIPV4Header         ((uint32_t)0x00400000)   /* IPv4 header checksum insertion  */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment  ((uint32_t)0x00800000)   /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull     ((uint32_t)0x00C00000)   /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+
+/* DMA RX & TX buffer */
+#define ETH_DMARxDesc_Buffer1     ((uint32_t)0x00000000)  /* DMA Rx Desc Buffer1 */
+#define ETH_DMARxDesc_Buffer2     ((uint32_t)0x00000001)  /* DMA Rx Desc Buffer2 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          ETH DMA Register                                                                                                                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/* DMA drop TCPIP checksum error frame enable or disable */
+#define ETH_DropTCPIPChecksumErrorFrame_Enable   ((uint32_t)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable  ((uint32_t)0x04000000)
+
+/* DMA receive store forward enable or disable */
+#define ETH_ReceiveStoreForward_Enable      ((uint32_t)0x02000000)
+#define ETH_ReceiveStoreForward_Disable     ((uint32_t)0x00000000)
+
+/* DMA flush received frame enable or disable */
+#define ETH_FlushReceivedFrame_Enable       ((uint32_t)0x00000000)
+#define ETH_FlushReceivedFrame_Disable      ((uint32_t)0x01000000)
+
+/* DMA transmit store forward enable or disable */
+#define ETH_TransmitStoreForward_Enable     ((uint32_t)0x00200000)
+#define ETH_TransmitStoreForward_Disable    ((uint32_t)0x00000000)
+
+/* DMA transmit threshold control */
+#define ETH_TransmitThresholdControl_64Bytes     ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TransmitThresholdControl_128Bytes    ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TransmitThresholdControl_192Bytes    ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TransmitThresholdControl_256Bytes    ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TransmitThresholdControl_40Bytes     ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TransmitThresholdControl_32Bytes     ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TransmitThresholdControl_24Bytes     ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TransmitThresholdControl_16Bytes     ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+
+/* DMA forward error frames */
+#define ETH_ForwardErrorFrames_Enable       ((uint32_t)0x00000080)
+#define ETH_ForwardErrorFrames_Disable      ((uint32_t)0x00000000)
+
+/* DMA forward undersized good frames enable or disable */
+#define ETH_ForwardUndersizedGoodFrames_Enable   ((uint32_t)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable  ((uint32_t)0x00000000)     
+
+/* DMA receive threshold control */
+#define ETH_ReceiveThresholdControl_64Bytes      ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_ReceiveThresholdControl_32Bytes      ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_ReceiveThresholdControl_96Bytes      ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_ReceiveThresholdControl_128Bytes     ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+
+/* DMA second frame operate enable or disable */
+#define ETH_SecondFrameOperate_Enable       ((uint32_t)0x00000004)
+#define ETH_SecondFrameOperate_Disable      ((uint32_t)0x00000000)  
+
+/* Address aligned beats enable or disable */
+#define ETH_AddressAlignedBeats_Enable      ((uint32_t)0x02000000)
+#define ETH_AddressAlignedBeats_Disable     ((uint32_t)0x00000000) 
+
+/* DMA Fixed burst enable or disable */
+#define ETH_FixedBurst_Enable     ((uint32_t)0x00010000)
+#define ETH_FixedBurst_Disable    ((uint32_t)0x00000000) 
+
+
+/* RX DMA burst length */
+#define ETH_RxDMABurstLength_1Beat          ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RxDMABurstLength_2Beat          ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RxDMABurstLength_4Beat          ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_8Beat          ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_16Beat         ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_32Beat         ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+
+ 
+/* TX DMA burst length */
+#define ETH_TxDMABurstLength_1Beat          ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TxDMABurstLength_2Beat          ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TxDMABurstLength_4Beat          ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_8Beat          ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_16Beat         ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_32Beat         ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+
+/* DMA arbitration_round robin */
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1   ((uint32_t)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1   ((uint32_t)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1   ((uint32_t)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1   ((uint32_t)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx             ((uint32_t)0x00000002)
+
+/* DMA interrupt FALG */
+#define ETH_DMA_FLAG_TST               ((uint32_t)0x20000000)  /* Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT               ((uint32_t)0x10000000)  /* PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC               ((uint32_t)0x08000000)  /* MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_ReadWriteError    ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_AccessError       ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS               ((uint32_t)0x00010000)  /* Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS               ((uint32_t)0x00008000)  /* Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER                ((uint32_t)0x00004000)  /* Early receive flag */
+#define ETH_DMA_FLAG_FBE               ((uint32_t)0x00002000)  /* Fatal bus error flag */
+#define ETH_DMA_FLAG_ET                ((uint32_t)0x00000400)  /* Early transmit flag */
+#define ETH_DMA_FLAG_RWT               ((uint32_t)0x00000200)  /* Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS               ((uint32_t)0x00000100)  /* Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU               ((uint32_t)0x00000080)  /* Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R                 ((uint32_t)0x00000040)  /* Receive flag */
+#define ETH_DMA_FLAG_TU                ((uint32_t)0x00000020)  /* Underflow flag */
+#define ETH_DMA_FLAG_RO                ((uint32_t)0x00000010)  /* Overflow flag */
+#define ETH_DMA_FLAG_TJT               ((uint32_t)0x00000008)  /* Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU               ((uint32_t)0x00000004)  /* Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS               ((uint32_t)0x00000002)  /* Transmit process stopped flag */
+#define ETH_DMA_FLAG_T                 ((uint32_t)0x00000001)  /* Transmit flag */
+
+/* DMA interrupt */
+#define ETH_DMA_IT_PHYLINK   ((uint32_t)0x80000000)  /* Internal PHY link status change interrupt */
+#define ETH_DMA_IT_TST       ((uint32_t)0x20000000)  /* Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT       ((uint32_t)0x10000000)  /* PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC       ((uint32_t)0x08000000)  /* MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS       ((uint32_t)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMA_IT_AIS       ((uint32_t)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMA_IT_ER        ((uint32_t)0x00004000)  /* Early receive interrupt */
+#define ETH_DMA_IT_FBE       ((uint32_t)0x00002000)  /* Fatal bus error interrupt */
+#define ETH_DMA_IT_ET        ((uint32_t)0x00000400)  /* Early transmit interrupt */
+#define ETH_DMA_IT_RWT       ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS       ((uint32_t)0x00000100)  /* Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU       ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R         ((uint32_t)0x00000040)  /* Receive interrupt */
+#define ETH_DMA_IT_TU        ((uint32_t)0x00000020)  /* Underflow interrupt */
+#define ETH_DMA_IT_RO        ((uint32_t)0x00000010)  /* Overflow interrupt */
+#define ETH_DMA_IT_TJT       ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU       ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS       ((uint32_t)0x00000002)  /* Transmit process stopped interrupt */
+#define ETH_DMA_IT_T         ((uint32_t)0x00000001)  /* Transmit interrupt */
+
+/* DMA transmit process */
+#define ETH_DMA_TransmitProcess_Stopped     ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TransmitProcess_Fetching    ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */
+#define ETH_DMA_TransmitProcess_Waiting     ((uint32_t)0x00200000)  /* Running - waiting for status */
+#define ETH_DMA_TransmitProcess_Reading     ((uint32_t)0x00300000)  /* Running - reading the data from host memory */
+#define ETH_DMA_TransmitProcess_Suspended   ((uint32_t)0x00600000)  /* Suspended - Tx Desciptor unavailabe */
+#define ETH_DMA_TransmitProcess_Closing     ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */
+
+/* DMA receive Process */
+#define ETH_DMA_ReceiveProcess_Stopped      ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_ReceiveProcess_Fetching     ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */
+#define ETH_DMA_ReceiveProcess_Waiting      ((uint32_t)0x00060000)  /* Running - waiting for packet */
+#define ETH_DMA_ReceiveProcess_Suspended    ((uint32_t)0x00080000)  /* Suspended - Rx Desciptor unavailable */
+#define ETH_DMA_ReceiveProcess_Closing      ((uint32_t)0x000A0000)  /* Running - closing descriptor */
+#define ETH_DMA_ReceiveProcess_Queuing      ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+
+/* DMA overflow */
+#define ETH_DMA_Overflow_RxFIFOCounter      ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */
+
+
+/*********************************************************************************
+*                            Ethernet PMT defines
+**********************************************************************************/
+
+/* PMT flag */
+#define ETH_PMT_FLAG_WUFFRPR      ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Poniter Reset */
+#define ETH_PMT_FLAG_WUFR         ((uint32_t)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR          ((uint32_t)0x00000020)  /* Magic Packet Received */
+
+/*********************************************************************************
+*                            Ethernet MMC defines
+**********************************************************************************/
+
+/* MMC TX interrupt flag */
+#define ETH_MMC_IT_TGF       ((uint32_t)0x00200000)  /* When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC    ((uint32_t)0x00008000)  /* When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC     ((uint32_t)0x00004000)  /* When Tx good single col counter reaches half the maximum value */
+
+/* MMC RX interrupt flag */
+#define ETH_MMC_IT_RGUF      ((uint32_t)0x10020000)  /* When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE      ((uint32_t)0x10000040)  /* When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE      ((uint32_t)0x10000020)  /* When Rx crc error counter reaches half the maximum value */
+
+
+/* MMC description */
+#define ETH_MMCCR            ((uint32_t)0x00000100)  /* MMC CR register */
+#define ETH_MMCRIR           ((uint32_t)0x00000104)  /* MMC RIR register */
+#define ETH_MMCTIR           ((uint32_t)0x00000108)  /* MMC TIR register */
+#define ETH_MMCRIMR          ((uint32_t)0x0000010C)  /* MMC RIMR register */
+#define ETH_MMCTIMR          ((uint32_t)0x00000110)  /* MMC TIMR register */
+#define ETH_MMCTGFSCCR       ((uint32_t)0x0000014C)  /* MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR      ((uint32_t)0x00000150)  /* MMC TGFMSCCR register */
+#define ETH_MMCTGFCR         ((uint32_t)0x00000168)  /* MMC TGFCR register */
+#define ETH_MMCRFCECR        ((uint32_t)0x00000194)  /* MMC RFCECR register */
+#define ETH_MMCRFAECR        ((uint32_t)0x00000198)  /* MMC RFAECR register */
+#define ETH_MMCRGUFCR        ((uint32_t)0x000001C4)  /* MMC RGUFCR register */
+
+
+/*********************************************************************************
+*                            Ethernet PTP defines
+**********************************************************************************/
+
+/* PTP fine update method or coarse Update method */
+#define ETH_PTP_FineUpdate        ((uint32_t)0x00000001)  /* Fine Update method */
+#define ETH_PTP_CoarseUpdate      ((uint32_t)0x00000000)  /* Coarse Update method */
+
+
+/* PTP time stamp control */
+#define ETH_PTP_FLAG_TSARU        ((uint32_t)0x00000020)  /* Addend Register Update */
+#define ETH_PTP_FLAG_TSITE        ((uint32_t)0x00000010)  /* Time Stamp Interrupt Trigger */
+#define ETH_PTP_FLAG_TSSTU        ((uint32_t)0x00000008)  /* Time Stamp Update */
+#define ETH_PTP_FLAG_TSSTI        ((uint32_t)0x00000004)  /* Time Stamp Initialize */
+
+/* PTP positive/negative time value */
+#define ETH_PTP_PositiveTime      ((uint32_t)0x00000000)  /* Positive time value */
+#define ETH_PTP_NegativeTime      ((uint32_t)0x80000000)  /* Negative time value */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                PTP Register                                                                                                                           */
+/*                                                                            */
+/******************************************************************************/
+#define ETH_PTPTSCR     ((uint32_t)0x00000700)  /* PTP TSCR register */
+#define ETH_PTPSSIR     ((uint32_t)0x00000704)  /* PTP SSIR register */
+#define ETH_PTPTSHR     ((uint32_t)0x00000708)  /* PTP TSHR register */
+#define ETH_PTPTSLR     ((uint32_t)0x0000070C)  /* PTP TSLR register */
+#define ETH_PTPTSHUR    ((uint32_t)0x00000710)  /* PTP TSHUR register */
+#define ETH_PTPTSLUR    ((uint32_t)0x00000714)  /* PTP TSLUR register */
+#define ETH_PTPTSAR     ((uint32_t)0x00000718)  /* PTP TSAR register */
+#define ETH_PTPTTHR     ((uint32_t)0x0000071C)  /* PTP TTHR register */
+#define ETH_PTPTTLR     ((uint32_t)0x00000720)  /* PTP TTLR register */
+
+#define ETH_DMASR_TSTS       ((unsigned int)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((unsigned int)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((unsigned int)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((unsigned int)0x03800000)  /* Error bits status */
+  #define ETH_DMASR_EBS_DescAccess      ((unsigned int)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+  #define ETH_DMASR_EBS_ReadTransf      ((unsigned int)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+  #define ETH_DMASR_EBS_DataTransfTx    ((unsigned int)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((unsigned int)0x00700000)  /* Transmit process state */
+  #define ETH_DMASR_TPS_Stopped         ((unsigned int)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+  #define ETH_DMASR_TPS_Fetching        ((unsigned int)0x00100000)  /* Running - fetching the Tx descriptor */
+  #define ETH_DMASR_TPS_Waiting         ((unsigned int)0x00200000)  /* Running - waiting for status */
+  #define ETH_DMASR_TPS_Reading         ((unsigned int)0x00300000)  /* Running - reading the data from host memory */
+  #define ETH_DMASR_TPS_Suspended       ((unsigned int)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+  #define ETH_DMASR_TPS_Closing         ((unsigned int)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((unsigned int)0x000E0000)  /* Receive process state */
+  #define ETH_DMASR_RPS_Stopped         ((unsigned int)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+  #define ETH_DMASR_RPS_Fetching        ((unsigned int)0x00020000)  /* Running - fetching the Rx descriptor */
+  #define ETH_DMASR_RPS_Waiting         ((unsigned int)0x00060000)  /* Running - waiting for packet */
+  #define ETH_DMASR_RPS_Suspended       ((unsigned int)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+  #define ETH_DMASR_RPS_Closing         ((unsigned int)0x000A0000)  /* Running - closing descriptor */
+  #define ETH_DMASR_RPS_Queuing         ((unsigned int)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((unsigned int)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((unsigned int)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((unsigned int)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((unsigned int)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((unsigned int)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((unsigned int)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((unsigned int)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((unsigned int)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((unsigned int)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((unsigned int)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((unsigned int)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((unsigned int)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((unsigned int)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((unsigned int)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((unsigned int)0x00000001)  /* Transmit status */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          ETH MAC Register                                                                                                                               */
+/*                                                                            */
+/******************************************************************************/
+#define ETH_MACCR_WD      ((unsigned int)0x00800000)  /* Watchdog disable */
+#define ETH_MACCR_JD      ((unsigned int)0x00400000)  /* Jabber disable */
+#define ETH_MACCR_IFG     ((unsigned int)0x000E0000)  /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit     ((unsigned int)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */
+   #define ETH_MACCR_IFG_88Bit     ((unsigned int)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */
+   #define ETH_MACCR_IFG_80Bit     ((unsigned int)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */
+   #define ETH_MACCR_IFG_72Bit     ((unsigned int)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */
+   #define ETH_MACCR_IFG_64Bit     ((unsigned int)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */
+   #define ETH_MACCR_IFG_56Bit     ((unsigned int)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */
+   #define ETH_MACCR_IFG_48Bit     ((unsigned int)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */
+   #define ETH_MACCR_IFG_40Bit     ((unsigned int)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD     ((unsigned int)0x00010000)  /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES     ((unsigned int)0x00004000)  /* Fast ethernet speed */
+#define ETH_MACCR_ROD     ((unsigned int)0x00002000)  /* Receive own disable */
+#define ETH_MACCR_LM      ((unsigned int)0x00001000)  /* loopback mode */
+#define ETH_MACCR_DM      ((unsigned int)0x00000800)  /* Duplex mode */
+#define ETH_MACCR_IPCO    ((unsigned int)0x00000400)  /* IP Checksum offload */
+#define ETH_MACCR_RD      ((unsigned int)0x00000200)  /* Retry disable */
+#define ETH_MACCR_APCS    ((unsigned int)0x00000080)  /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL      ((unsigned int)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */
+   #define ETH_MACCR_BL_10    ((unsigned int)0x00000000)  /* k = min (n, 10) */
+   #define ETH_MACCR_BL_8     ((unsigned int)0x00000020)  /* k = min (n, 8) */
+   #define ETH_MACCR_BL_4     ((unsigned int)0x00000040)  /* k = min (n, 4) */
+   #define ETH_MACCR_BL_1     ((unsigned int)0x00000060)  /* k = min (n, 1) */
+#define ETH_MACCR_DC      ((unsigned int)0x00000010)  /* Defferal check */
+#define ETH_MACCR_TE      ((unsigned int)0x00000008)  /* Transmitter enable */
+#define ETH_MACCR_RE      ((unsigned int)0x00000004)  /* Receiver enable */
+
+#define ETH_MACFFR_RA     ((unsigned int)0x80000000)  /* Receive all */
+#define ETH_MACFFR_HPF    ((unsigned int)0x00000400)  /* Hash or perfect filter */
+#define ETH_MACFFR_SAF    ((unsigned int)0x00000200)  /* Source address filter enable */
+#define ETH_MACFFR_SAIF   ((unsigned int)0x00000100)  /* SA inverse filtering */
+#define ETH_MACFFR_PCF    ((unsigned int)0x000000C0)  /* Pass control frames: 3 cases */
+   #define ETH_MACFFR_PCF_BlockAll                ((unsigned int)0x00000040)  /* MAC filters all control frames from reaching the application */
+   #define ETH_MACFFR_PCF_ForwardAll              ((unsigned int)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
+   #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD    ((unsigned int)0x00000020)  /* Broadcast frame disable */
+#define ETH_MACFFR_PAM    ((unsigned int)0x00000010)  /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF   ((unsigned int)0x00000008)  /* DA Inverse filtering */
+#define ETH_MACFFR_HM     ((unsigned int)0x00000004)  /* Hash multicast */
+#define ETH_MACFFR_HU     ((unsigned int)0x00000002)  /* Hash unicast */
+#define ETH_MACFFR_PM     ((unsigned int)0x00000001)  /* Promiscuous mode */
+
+#define ETH_MACHTHR_HTH   ((unsigned int)0xFFFFFFFF)  /* Hash table high */
+#define ETH_MACHTLR_HTL   ((unsigned int)0xFFFFFFFF)  /* Hash table low */
+
+#define ETH_MACMIIAR_PA   ((unsigned int)0x0000F800)  /* Physical layer address */
+#define ETH_MACMIIAR_MR   ((unsigned int)0x000007C0)  /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR   ((unsigned int)0x0000001C)  /* CR clock range: 6 cases */
+   #define ETH_MACMIIAR_CR_Div42   ((unsigned int)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
+   #define ETH_MACMIIAR_CR_Div16   ((unsigned int)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+   #define ETH_MACMIIAR_CR_Div26   ((unsigned int)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW   ((unsigned int)0x00000002)  /* MII write */
+#define ETH_MACMIIAR_MB   ((unsigned int)0x00000001)  /* MII busy */
+#define ETH_MACMIIDR_MD   ((unsigned int)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+#define ETH_MACFCR_PT     ((unsigned int)0xFFFF0000)  /* Pause time */
+#define ETH_MACFCR_ZQPD   ((unsigned int)0x00000080)  /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT    ((unsigned int)0x00000030)  /* Pause low threshold: 4 cases */
+   #define ETH_MACFCR_PLT_Minus4   ((unsigned int)0x00000000)  /* Pause time minus 4 slot times */
+   #define ETH_MACFCR_PLT_Minus28  ((unsigned int)0x00000010)  /* Pause time minus 28 slot times */
+   #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020)  /* Pause time minus 144 slot times */
+   #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030)  /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD   ((unsigned int)0x00000008)  /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE   ((unsigned int)0x00000004)  /* Receive flow control enable */
+#define ETH_MACFCR_TFCE   ((unsigned int)0x00000002)  /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001)  /* Flow control busy/backpressure activate */
+
+#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000)  /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */
+
+#define ETH_MACRWUFFR_D   ((unsigned int)0xFFFFFFFF)  /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+
+/*
+Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+                           RSVD - Filter1 Command - RSVD - Filter0 Command
+Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU     ((unsigned int)0x00000200)  /* Global Unicast */
+#define ETH_MACPMTCSR_WFR    ((unsigned int)0x00000040)  /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR    ((unsigned int)0x00000020)  /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE    ((unsigned int)0x00000004)  /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE    ((unsigned int)0x00000002)  /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD     ((unsigned int)0x00000001)  /* Power Down */
+
+#define ETH_MACSR_TSTS      ((unsigned int)0x00000200)  /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS     ((unsigned int)0x00000040)  /* MMC transmit status */
+#define ETH_MACSR_MMMCRS    ((unsigned int)0x00000020)  /* MMC receive status */
+#define ETH_MACSR_MMCS      ((unsigned int)0x00000010)  /* MMC status */
+#define ETH_MACSR_PMTS      ((unsigned int)0x00000008)  /* PMT status */
+
+#define ETH_MACIMR_TSTIM     ((unsigned int)0x00000200)  /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM     ((unsigned int)0x00000008)  /* PMT interrupt mask */
+
+#define ETH_MACA0HR_MACA0H   ((unsigned int)0x0000FFFF)  /* MAC address0 high */
+
+#define ETH_MACA0LR_MACA0L   ((unsigned int)0xFFFFFFFF)  /* MAC address0 low */
+
+#define ETH_MACA1HR_AE       ((unsigned int)0x80000000)  /* Address enable */
+#define ETH_MACA1HR_SA       ((unsigned int)0x40000000)  /* Source address */
+#define ETH_MACA1HR_MBC      ((unsigned int)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+   #define ETH_MACA1HR_MBC_HBits15_8    ((unsigned int)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+   #define ETH_MACA1HR_MBC_HBits7_0     ((unsigned int)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+   #define ETH_MACA1HR_MBC_LBits31_24   ((unsigned int)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+   #define ETH_MACA1HR_MBC_LBits23_16   ((unsigned int)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+   #define ETH_MACA1HR_MBC_LBits15_8    ((unsigned int)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+   #define ETH_MACA1HR_MBC_LBits7_0     ((unsigned int)0x01000000)  /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H   ((unsigned int)0x0000FFFF)  /* MAC address1 high */
+
+#define ETH_MACA1LR_MACA1L   ((unsigned int)0xFFFFFFFF)  /* MAC address1 low */
+
+#define ETH_MACA2HR_AE       ((unsigned int)0x80000000)  /* Address enable */
+#define ETH_MACA2HR_SA       ((unsigned int)0x40000000)  /* Source address */
+#define ETH_MACA2HR_MBC      ((unsigned int)0x3F000000)  /* Mask byte control */
+   #define ETH_MACA2HR_MBC_HBits15_8    ((unsigned int)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+   #define ETH_MACA2HR_MBC_HBits7_0     ((unsigned int)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+   #define ETH_MACA2HR_MBC_LBits31_24   ((unsigned int)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+   #define ETH_MACA2HR_MBC_LBits23_16   ((unsigned int)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+   #define ETH_MACA2HR_MBC_LBits15_8    ((unsigned int)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+   #define ETH_MACA2HR_MBC_LBits7_0     ((unsigned int)0x01000000)  /* Mask MAC Address low reg bits [70] */
+
+#define ETH_MACA2HR_MACA2H   ((unsigned int)0x0000FFFF)  /* MAC address1 high */
+#define ETH_MACA2LR_MACA2L   ((unsigned int)0xFFFFFFFF)  /* MAC address2 low */
+
+#define ETH_MACA3HR_AE       ((unsigned int)0x80000000)  /* Address enable */
+#define ETH_MACA3HR_SA       ((unsigned int)0x40000000)  /* Source address */
+#define ETH_MACA3HR_MBC      ((unsigned int)0x3F000000)  /* Mask byte control */
+   #define ETH_MACA3HR_MBC_HBits15_8    ((unsigned int)0x20000000)  /* Mask MAC Address high reg bits [15:8] */
+   #define ETH_MACA3HR_MBC_HBits7_0     ((unsigned int)0x10000000)  /* Mask MAC Address high reg bits [7:0] */
+   #define ETH_MACA3HR_MBC_LBits31_24   ((unsigned int)0x08000000)  /* Mask MAC Address low reg bits [31:24] */
+   #define ETH_MACA3HR_MBC_LBits23_16   ((unsigned int)0x04000000)  /* Mask MAC Address low reg bits [23:16] */
+   #define ETH_MACA3HR_MBC_LBits15_8    ((unsigned int)0x02000000)  /* Mask MAC Address low reg bits [15:8] */
+   #define ETH_MACA3HR_MBC_LBits7_0     ((unsigned int)0x01000000)  /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H   ((unsigned int)0x0000FFFF)  /* MAC address3 high */
+#define ETH_MACA3LR_MACA3L   ((unsigned int)0xFFFFFFFF)  /* MAC address3 low */
+
+/******************************************************************************/
+/*
+/*                          ETH MMC Register
+/*
+/******************************************************************************/
+#define ETH_MMCCR_MCFHP      ((unsigned int)0x00000020)  /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP        ((unsigned int)0x00000010)  /* MMC counter preset */
+#define ETH_MMCCR_MCF        ((unsigned int)0x00000008)  /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR        ((unsigned int)0x00000004)  /* Reset on Read */
+#define ETH_MMCCR_CSR        ((unsigned int)0x00000002)  /* Counter Stop Rollover */
+#define ETH_MMCCR_CR         ((unsigned int)0x00000001)  /* Counters Reset */
+
+#define ETH_MMCRIR_RGUFS     ((unsigned int)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES     ((unsigned int)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES     ((unsigned int)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */
+
+#define ETH_MMCTIR_TGFS      ((unsigned int)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS   ((unsigned int)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS    ((unsigned int)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */
+
+#define ETH_MMCRIMR_RGUFM    ((unsigned int)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM    ((unsigned int)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM    ((unsigned int)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+#define ETH_MMCTIMR_TGFM     ((unsigned int)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM  ((unsigned int)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM   ((unsigned int)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+#define ETH_MMCTGFSCCR_TGFSCC     ((unsigned int)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((unsigned int)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+#define ETH_MMCTGFCR_TGFC    ((unsigned int)0xFFFFFFFF)  /* Number of good frames transmitted. */
+
+#define ETH_MMCRFCECR_RFCEC  ((unsigned int)0xFFFFFFFF)  /* Number of frames received with CRC error. */
+
+#define ETH_MMCRFAECR_RFAEC  ((unsigned int)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */
+
+#define ETH_MMCRGUFCR_RGUFC  ((unsigned int)0xFFFFFFFF)  /* Number of good unicast frames received. */
+
+
+/******************************************************************************/
+/*
+/*                          ETH Precise Clock Protocol Register
+/*
+/******************************************************************************/
+#define ETH_PTPTSCR_TSCNT       ((unsigned int)0x00030000)  /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME     ((unsigned int)0x00008000)  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME      ((unsigned int)0x00004000)  /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE   ((unsigned int)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE   ((unsigned int)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE  ((unsigned int)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E  ((unsigned int)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR       ((unsigned int)0x00000200)  /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE     ((unsigned int)0x00000100)  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU    ((unsigned int)0x00000020)  /* Addend register update */
+#define ETH_PTPTSCR_TSITE    ((unsigned int)0x00000010)  /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU    ((unsigned int)0x00000008)  /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI    ((unsigned int)0x00000004)  /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU    ((unsigned int)0x00000002)  /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE      ((unsigned int)0x00000001)  /* Time stamp enable */
+
+#define ETH_PTPSSIR_STSSI    ((unsigned int)0x000000FF)  /* System time Sub-second increment value */
+
+#define ETH_PTPTSHR_STS      ((unsigned int)0xFFFFFFFF)  /* System Time second */
+
+#define ETH_PTPTSLR_STPNS    ((unsigned int)0x80000000)  /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS     ((unsigned int)0x7FFFFFFF)  /* System Time sub-seconds */
+
+#define ETH_PTPTSHUR_TSUS    ((unsigned int)0xFFFFFFFF)  /* Time stamp update seconds */
+
+#define ETH_PTPTSLUR_TSUPNS  ((unsigned int)0x80000000)  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS   ((unsigned int)0x7FFFFFFF)  /* Time stamp update sub-seconds */
+
+#define ETH_PTPTSAR_TSA      ((unsigned int)0xFFFFFFFF)  /* Time stamp addend */
+
+#define ETH_PTPTTHR_TTSH     ((unsigned int)0xFFFFFFFF)  /* Target time stamp high */
+
+#define ETH_PTPTTLR_TTSL     ((unsigned int)0xFFFFFFFF)  /* Target time stamp low */
+
+#define ETH_PTPTSSR_TSTTR    ((unsigned int)0x00000020)  /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO     ((unsigned int)0x00000010)  /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*
+/*                       ETH DMA Register
+/*
+/******************************************************************************/
+#define ETH_DMABMR_AAB       ((unsigned int)0x02000000)  /* Address-Aligned beats */
+#define ETH_DMABMR_FPM        ((unsigned int)0x01000000)  /* 4xPBL mode */
+#define ETH_DMABMR_USP       ((unsigned int)0x00800000)  /* Use separate PBL */
+#define ETH_DMABMR_RDP       ((unsigned int)0x007E0000)  /* RxDMA PBL */
+   #define ETH_DMABMR_RDP_1Beat    ((unsigned int)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+   #define ETH_DMABMR_RDP_2Beat    ((unsigned int)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+   #define ETH_DMABMR_RDP_4Beat    ((unsigned int)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+   #define ETH_DMABMR_RDP_8Beat    ((unsigned int)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+   #define ETH_DMABMR_RDP_16Beat   ((unsigned int)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+   #define ETH_DMABMR_RDP_32Beat   ((unsigned int)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+   #define ETH_DMABMR_RDP_4xPBL_4Beat   ((unsigned int)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+   #define ETH_DMABMR_RDP_4xPBL_8Beat   ((unsigned int)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+   #define ETH_DMABMR_RDP_4xPBL_16Beat  ((unsigned int)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+   #define ETH_DMABMR_RDP_4xPBL_32Beat  ((unsigned int)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+   #define ETH_DMABMR_RDP_4xPBL_64Beat  ((unsigned int)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+   #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB        ((unsigned int)0x00010000)  /* Fixed Burst */
+#define ETH_DMABMR_RTPR      ((unsigned int)0x0000C000)  /* Rx Tx priority ratio */
+   #define ETH_DMABMR_RTPR_1_1     ((unsigned int)0x00000000)  /* Rx Tx priority ratio */
+   #define ETH_DMABMR_RTPR_2_1     ((unsigned int)0x00004000)  /* Rx Tx priority ratio */
+   #define ETH_DMABMR_RTPR_3_1     ((unsigned int)0x00008000)  /* Rx Tx priority ratio */
+   #define ETH_DMABMR_RTPR_4_1     ((unsigned int)0x0000C000)  /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL    ((unsigned int)0x00003F00)  /* Programmable burst length */
+   #define ETH_DMABMR_PBL_1Beat    ((unsigned int)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+   #define ETH_DMABMR_PBL_2Beat    ((unsigned int)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+   #define ETH_DMABMR_PBL_4Beat    ((unsigned int)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+   #define ETH_DMABMR_PBL_8Beat    ((unsigned int)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+   #define ETH_DMABMR_PBL_16Beat   ((unsigned int)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+   #define ETH_DMABMR_PBL_32Beat   ((unsigned int)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+   #define ETH_DMABMR_PBL_4xPBL_4Beat   ((unsigned int)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+   #define ETH_DMABMR_PBL_4xPBL_8Beat   ((unsigned int)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+   #define ETH_DMABMR_PBL_4xPBL_16Beat  ((unsigned int)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+   #define ETH_DMABMR_PBL_4xPBL_32Beat  ((unsigned int)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+   #define ETH_DMABMR_PBL_4xPBL_64Beat  ((unsigned int)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+   #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE       ((unsigned int)0x00000080)  /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL       ((unsigned int)0x0000007C)  /* Descriptor Skip Length */
+#define ETH_DMABMR_DA        ((unsigned int)0x00000002)  /* DMA arbitration scheme */
+#define ETH_DMABMR_SR        ((unsigned int)0x00000001)  /* Software reset */
+
+#define ETH_DMATPDR_TPD      ((unsigned int)0xFFFFFFFF)  /* Transmit poll demand */
+
+#define ETH_DMARPDR_RPD      ((unsigned int)0xFFFFFFFF)  /* Receive poll demand  */
+
+#define ETH_DMARDLAR_SRL     ((unsigned int)0xFFFFFFFF)  /* Start of receive list */
+
+#define ETH_DMATDLAR_STL     ((unsigned int)0xFFFFFFFF)  /* Start of transmit list */
+
+#define ETH_DMASR_TSTS       ((unsigned int)0x20000000)  /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS       ((unsigned int)0x10000000)  /* PMT status */
+#define ETH_DMASR_MMCS       ((unsigned int)0x08000000)  /* MMC status */
+#define ETH_DMASR_EBS        ((unsigned int)0x03800000)  /* Error bits status */
+   #define ETH_DMASR_EBS_DescAccess      ((unsigned int)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */
+   #define ETH_DMASR_EBS_ReadTransf      ((unsigned int)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */
+   #define ETH_DMASR_EBS_DataTransfTx    ((unsigned int)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS         ((unsigned int)0x00700000)  /* Transmit process state */
+   #define ETH_DMASR_TPS_Stopped         ((unsigned int)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */
+   #define ETH_DMASR_TPS_Fetching        ((unsigned int)0x00100000)  /* Running - fetching the Tx descriptor */
+   #define ETH_DMASR_TPS_Waiting         ((unsigned int)0x00200000)  /* Running - waiting for status */
+   #define ETH_DMASR_TPS_Reading         ((unsigned int)0x00300000)  /* Running - reading the data from host memory */
+   #define ETH_DMASR_TPS_Suspended       ((unsigned int)0x00600000)  /* Suspended - Tx Descriptor unavailabe */
+   #define ETH_DMASR_TPS_Closing         ((unsigned int)0x00700000)  /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS         ((unsigned int)0x000E0000)  /* Receive process state */
+   #define ETH_DMASR_RPS_Stopped         ((unsigned int)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */
+   #define ETH_DMASR_RPS_Fetching        ((unsigned int)0x00020000)  /* Running - fetching the Rx descriptor */
+   #define ETH_DMASR_RPS_Waiting         ((unsigned int)0x00060000)  /* Running - waiting for packet */
+   #define ETH_DMASR_RPS_Suspended       ((unsigned int)0x00080000)  /* Suspended - Rx Descriptor unavailable */
+   #define ETH_DMASR_RPS_Closing         ((unsigned int)0x000A0000)  /* Running - closing descriptor */
+   #define ETH_DMASR_RPS_Queuing         ((unsigned int)0x000E0000)  /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS        ((unsigned int)0x00010000)  /* Normal interrupt summary */
+#define ETH_DMASR_AIS        ((unsigned int)0x00008000)  /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS        ((unsigned int)0x00004000)  /* Early receive status */
+#define ETH_DMASR_FBES       ((unsigned int)0x00002000)  /* Fatal bus error status */
+#define ETH_DMASR_ETS        ((unsigned int)0x00000400)  /* Early transmit status */
+#define ETH_DMASR_RWTS       ((unsigned int)0x00000200)  /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS       ((unsigned int)0x00000100)  /* Receive process stopped status */
+#define ETH_DMASR_RBUS       ((unsigned int)0x00000080)  /* Receive buffer unavailable status */
+#define ETH_DMASR_RS         ((unsigned int)0x00000040)  /* Receive status */
+#define ETH_DMASR_TUS        ((unsigned int)0x00000020)  /* Transmit underflow status */
+#define ETH_DMASR_ROS        ((unsigned int)0x00000010)  /* Receive overflow status */
+#define ETH_DMASR_TJTS       ((unsigned int)0x00000008)  /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS       ((unsigned int)0x00000004)  /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS       ((unsigned int)0x00000002)  /* Transmit process stopped status */
+#define ETH_DMASR_TS         ((unsigned int)0x00000001)  /* Transmit status */
+
+#define ETH_DMAOMR_DTCEFD    ((unsigned int)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF       ((unsigned int)0x02000000)  /* Receive store and forward */
+#define ETH_DMAOMR_DFRF      ((unsigned int)0x01000000)  /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF       ((unsigned int)0x00200000)  /* Transmit store and forward */
+#define ETH_DMAOMR_FTF       ((unsigned int)0x00100000)  /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC       ((unsigned int)0x0001C000)  /* Transmit threshold control */
+   #define ETH_DMAOMR_TTC_64Bytes       ((unsigned int)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+   #define ETH_DMAOMR_TTC_128Bytes      ((unsigned int)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+   #define ETH_DMAOMR_TTC_192Bytes      ((unsigned int)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+   #define ETH_DMAOMR_TTC_256Bytes      ((unsigned int)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+   #define ETH_DMAOMR_TTC_40Bytes       ((unsigned int)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+   #define ETH_DMAOMR_TTC_32Bytes       ((unsigned int)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+   #define ETH_DMAOMR_TTC_24Bytes       ((unsigned int)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+   #define ETH_DMAOMR_TTC_16Bytes       ((unsigned int)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST        ((unsigned int)0x00002000)  /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF       ((unsigned int)0x00000080)  /* Forward error frames */
+#define ETH_DMAOMR_FUGF      ((unsigned int)0x00000040)  /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC       ((unsigned int)0x00000018)  /* receive threshold control */
+   #define ETH_DMAOMR_RTC_64Bytes       ((unsigned int)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */
+   #define ETH_DMAOMR_RTC_32Bytes       ((unsigned int)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */
+   #define ETH_DMAOMR_RTC_96Bytes       ((unsigned int)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */
+   #define ETH_DMAOMR_RTC_128Bytes      ((unsigned int)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF       ((unsigned int)0x00000004)  /* operate on second frame */
+#define ETH_DMAOMR_SR        ((unsigned int)0x00000002)  /* Start/stop receive */
+
+#define ETH_DMAIER_NISE      ((unsigned int)0x00010000)  /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE      ((unsigned int)0x00008000)  /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE      ((unsigned int)0x00004000)  /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE     ((unsigned int)0x00002000)  /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE      ((unsigned int)0x00000400)  /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE     ((unsigned int)0x00000200)  /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE     ((unsigned int)0x00000100)  /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE     ((unsigned int)0x00000080)  /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE       ((unsigned int)0x00000040)  /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE      ((unsigned int)0x00000020)  /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE      ((unsigned int)0x00000010)  /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE     ((unsigned int)0x00000008)  /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE     ((unsigned int)0x00000004)  /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE     ((unsigned int)0x00000002)  /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE       ((unsigned int)0x00000001)  /* Transmit interrupt enable */
+
+#define ETH_DMAMFBOCR_OFOC   ((unsigned int)0x10000000)  /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA    ((unsigned int)0x0FFE0000)  /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC   ((unsigned int)0x00010000)  /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC    ((unsigned int)0x0000FFFF)  /* Number of frames missed by the controller */
+
+#define ETH_DMACHTDR_HTDAP   ((unsigned int)0xFFFFFFFF)  /* Host transmit descriptor address pointer */
+#define ETH_DMACHRDR_HRDAP   ((unsigned int)0xFFFFFFFF)  /* Host receive descriptor address pointer */
+#define ETH_DMACHTBAR_HTBAP  ((unsigned int)0xFFFFFFFF)  /* Host transmit buffer address pointer */
+#define ETH_DMACHRBAR_HRBAP  ((unsigned int)0xFFFFFFFF)  /* Host receive buffer address pointer */
+
+
+#define ETH_MAC_ADDR_HBASE   (ETH_MAC_BASE + 0x40)   /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK    ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK    ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK   ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK   ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH      8
+
+/* ETHERNET Missed frames counter Shift */
+#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT        3
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16
+
+/* ETHERNET errors */
+#define  ETH_ERROR              ((uint32_t)0)
+#define  ETH_SUCCESS            ((uint32_t)1)
+
+
+void ETH_DeInit(void);
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+FlagStatus ETH_GetlinkStaus (void);
+void  ETH_Start(void);
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength);
+void delay_clk (uint32_t nCount);
+void printf_dmasr (void);
+void print_dmasr_tbus(void);
+void print_dmasr_rps(void);
+void print_dmasr_tps(void);
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt);
+uint32_t ETH_GetRxPktSize(void);
+void ETH_DropRxPkt(void);
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg);
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue);
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState);
+
+void ETH_MACTransmissionCmd(FunctionalState NewState);
+void ETH_MACReceptionCmd(FunctionalState NewState);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);  
+void ETH_BackPressureActivationCmd(FunctionalState NewState); 
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);  
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr);
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr);
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
+
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
+
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
+uint32_t ETH_GetTransmitProcessState(void);
+uint32_t ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState NewState);
+void ETH_DMAReceptionCmd(FunctionalState NewState);
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
+uint32_t ETH_GetCurrentTxDescStartAddress(void);
+uint32_t ETH_GetCurrentRxDescStartAddress(void);
+uint32_t ETH_GetCurrentTxBufferAddress(void);
+uint32_t ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
+void ETH_PowerDownCmd(FunctionalState NewState);
+
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
+
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab);
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab);
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+void ETH_EnablePTPTimeStampAddend(void);
+void ETH_EnablePTPTimeStampInterruptTrigger(void);
+void ETH_EnablePTPTimeStampUpdate(void);
+void ETH_InitializePTPTimeStamp(void);
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
+void ETH_PTPTimeStampCmd(FunctionalState NewState);
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampAddend(uint32_t Value);
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);
+void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_exti.h

@@ -0,0 +1,90 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_exti.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      EXTI firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_EXTI_H
+#define __CH32V30x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* EXTI mode enumeration */
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+/* EXTI Trigger enumeration */
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+/* EXTI Init Structure definition */
+typedef struct
+{
+  uint32_t EXTI_Line;               /* Specifies the EXTI lines to be enabled or disabled.
+                                       This parameter can be any combination of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /* Specifies the mode for the EXTI lines.
+                                       This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
+                                       This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /* Specifies the new state of the selected EXTI lines.
+                                       This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+
+/* EXTI_Lines */
+#define EXTI_Line0       ((uint32_t)0x00001)  /* External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /* External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /* External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /* External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /* External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /* External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /* External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /* External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /* External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /* External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /* External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /* External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /* External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /* External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /* External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /* External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /* External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /* External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /* External interrupt line 18 Connected to the USBD/USBFS OTG
+                                                 Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)  /* External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20      ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_flash.h

@@ -0,0 +1,143 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_flash.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the FLASH  
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_FLASH_H
+#define __CH32V30x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* FLASH Status */
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PG,
+  FLASH_ERROR_WRP,
+  FLASH_COMPLETE,
+  FLASH_TIMEOUT
+}FLASH_Status;
+
+
+/* Write Protect */
+#define FLASH_WRProt_Sectors0        ((uint32_t)0x00000001) /* Write protection of setor 0  */
+#define FLASH_WRProt_Sectors1        ((uint32_t)0x00000002) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors2        ((uint32_t)0x00000004) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors3        ((uint32_t)0x00000008) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors4        ((uint32_t)0x00000010) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors5        ((uint32_t)0x00000020) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors6        ((uint32_t)0x00000040) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors7        ((uint32_t)0x00000080) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors8        ((uint32_t)0x00000100) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors9        ((uint32_t)0x00000200) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors10       ((uint32_t)0x00000400) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors11       ((uint32_t)0x00000800) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors12       ((uint32_t)0x00001000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors13       ((uint32_t)0x00002000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors14       ((uint32_t)0x00004000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors15       ((uint32_t)0x00008000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors16       ((uint32_t)0x00010000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors17       ((uint32_t)0x00020000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors18       ((uint32_t)0x00040000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors19       ((uint32_t)0x00080000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors20       ((uint32_t)0x00100000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors21       ((uint32_t)0x00200000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors22       ((uint32_t)0x00400000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors23       ((uint32_t)0x00800000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors24       ((uint32_t)0x01000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors25       ((uint32_t)0x02000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors26       ((uint32_t)0x04000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors27       ((uint32_t)0x08000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors28       ((uint32_t)0x10000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors29       ((uint32_t)0x20000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors30       ((uint32_t)0x40000000) /* Write protection of setor 0 */
+#define FLASH_WRProt_Sectors31to127  ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllSectors      ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
+
+/* Option_Bytes_IWatchdog */
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /* Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /* Hardware IWDG selected */
+
+/* Option_Bytes_nRST_STOP */
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+
+/* Option_Bytes_nRST_STDBY  */
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+
+/* FLASH_Interrupts */	
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /* FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /* End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR           FLASH_IT_ERROR          /* FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP             FLASH_IT_EOP            /* End of FLASH BANK1 Operation Interrupt source */
+
+/* FLASH_Flags */	
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /* FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY                 FLASH_FLAG_BSY       /* FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP                 FLASH_FLAG_EOP       /* FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR               FLASH_FLAG_PGERR     /* FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR            FLASH_FLAG_WRPRTERR  /* FLASH BANK1 Write protected error flag */
+
+/* FLASH_Enhance_CLK */
+#define FLASH_Enhance_SYSTEM_HALF      ((uint32_t)0x00000000)   /* FLASH Enhance Clock = SYSTEM */
+#define FLASH_Enhance_SYSTEM           ((uint32_t)0x02000000)   /* Enhance_CLK = SYSTEM/2 */ 
+ 
+ 
+/*Functions used for all devices*/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+void FLASH_Unlock_Fast(void);
+void FLASH_Lock_Fast(void);
+void FLASH_ErasePage_Fast(uint32_t Page_Address);
+void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
+void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address);
+void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf);
+void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState);
+
+/* New function used for all devices */
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_fsmc.h

@@ -0,0 +1,287 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_fsmc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the FSMC
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_FSMC_H
+#define __CH32V30x_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#include "ch32v30x.h"
+
+
+/* FSMC Init structure definition */
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /* Defines the number of HCLK cycles to configure
+                                           the duration of the address setup time.
+                                           This parameter can be a value between 0 and 0xF.
+                                           @note: It is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /* Defines the number of HCLK cycles to configure
+                                           the duration of the address hold time.
+                                           This parameter can be a value between 0 and 0xF.
+                                           @note: It is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /* Defines the number of HCLK cycles to configure
+                                           the duration of the data setup time.
+                                           This parameter can be a value between 0 and 0xFF.
+                                           @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /* Defines the number of HCLK cycles to configure
+                                           the duration of the bus turnaround.
+                                           This parameter can be a value between 0 and 0xF.
+                                           @note: It is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                           This parameter can be a value between 1 and 0xF.
+                                           @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /* Defines the number of memory clock cycles to issue
+                                           to the memory before getting the first data.
+                                           The value of this parameter depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /* Specifies the asynchronous access mode.
+                                            This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+
+typedef struct
+{
+  uint32_t FSMC_Bank;                /* Specifies the NOR/SRAM memory bank that will be used.
+                                        This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /* Specifies whether the address and data values are
+                                        multiplexed on the databus or not.
+                                        This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /* Specifies the type of external memory attached to
+                                        the corresponding memory bank.
+                                        This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /* Specifies the external memory device width.
+                                        This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /* Enables or disables the burst access mode for Flash memory,
+                                        valid only with synchronous burst Flash memories.
+                                        This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+                                       
+  uint32_t FSMC_AsynchronousWait;    /* Enables or disables wait signal during asynchronous transfers,
+                                        valid only with asynchronous Flash memories.
+                                        This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+  uint32_t FSMC_WaitSignalPolarity;  /* Specifies the wait signal polarity, valid only when accessing
+                                        the Flash memory in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /* Enables or disables the Wrapped burst access mode for Flash
+                                        memory, valid only when accessing Flash memories in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /* Specifies if the wait signal is asserted by the memory one
+                                        clock cycle before the wait state or during the wait state,
+                                        valid only when accessing memories in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /* Enables or disables the write operation in the selected bank by the FSMC.
+                                        This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /* Enables or disables the wait-state insertion via wait
+                                        signal, valid for Flash memory access in burst mode.
+                                        This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /* Enables or disables the extended mode.
+                                        This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /* Enables or disables the write burst operation.
+                                        This parameter can be a value of @ref FSMC_Write_Burst */
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the  ExtendedMode is not used*/
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /* Timing Parameters for write access if the  ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+
+typedef struct
+{
+  uint32_t FSMC_SetupTime;      /* Defines the number of HCLK cycles to setup address before
+                                   the command assertion for NAND-Flash read or write access
+                                   to common/Attribute or I/O memory space (depending on
+                                   the memory space timing to be configured).
+                                   This parameter can be a value between 0 and 0xFF.*/
+
+  uint32_t FSMC_WaitSetupTime;  /* Defines the minimum number of HCLK cycles to assert the
+                                   command for NAND-Flash read or write access to
+                                   common/Attribute or I/O memory space (depending on the
+                                   memory space timing to be configured).
+                                   This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HoldSetupTime;  /* Defines the number of HCLK clock cycles to hold address
+                                   (and data for write access) after the command deassertion
+                                   for NAND-Flash read or write access to common/Attribute
+                                   or I/O memory space (depending on the memory space timing
+                                   to be configured).
+                                   This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HiZSetupTime;   /* Defines the number of HCLK clock cycles during which the
+                                   databus is kept in HiZ after the start of a NAND-Flash
+                                   write access to common/Attribute or I/O memory space (depending
+                                   on the memory space timing to be configured).
+                                   This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+
+typedef struct
+{
+  uint32_t FSMC_Bank;             /* Specifies the NAND memory bank that will be used.
+                                     This parameter can be a value of @ref FSMC_NAND_Bank */
+
+  uint32_t FSMC_Waitfeature;      /* Enables or disables the Wait feature for the NAND Memory Bank.
+                                     This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_MemoryDataWidth;  /* Specifies the external memory device width.
+                                     This parameter can be any value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_ECC;              /* Enables or disables the ECC computation.
+                                     This parameter can be any value of @ref FSMC_ECC */
+
+  uint32_t FSMC_ECCPageSize;      /* Defines the page size for the extended ECC.
+                                     This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+  uint32_t FSMC_TCLRSetupTime;    /* Defines the number of HCLK cycles to configure the
+                                     delay between CLE low and RE low.
+                                     This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;     /* Defines the number of HCLK cycles to configure the
+                                     delay between ALE low and RE low.
+                                     This parameter can be a number between 0x0 and 0xFF */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /* FSMC Common Space Timing */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+
+/* FSMC_NORSRAM_Bank */
+#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
+
+/* FSMC_NAND_Bank */
+#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
+
+/* FSMC_Data_Address_Bus_Multiplexing */
+#define FSMC_DataAddressMux_Disable                     ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                      ((uint32_t)0x00000002)
+
+/* FSMC_Memory_Type */
+#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
+
+/* FSMC_Data_Width */
+#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
+
+/* FSMC_Burst_Access_Mode */
+#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
+
+/* FSMC_AsynchronousWait */
+#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
+
+/* FSMC_Wait_Signal_Polarity */
+#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
+
+/* FSMC_Wrap_Mode */
+#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
+
+/* FSMC_Wait_Timing */
+#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
+
+/* FSMC_Write_Operation */
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+
+/* FSMC_Wait_Signal */
+#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
+
+/* FSMC_Extended_Mode */
+#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
+
+/* FSMC_Write_Burst */
+#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
+
+/* FSMC_Access_Mode */
+#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
+
+/* FSMC_Wait_feature */
+#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
+
+/* FSMC_ECC */
+#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
+
+/* FSMC_ECC_Page_Size */
+#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
+
+/* FSMC_Interrupt_sources */
+#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
+#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
+
+/* FSMC_Flags */
+#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
+
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_gpio.h

@@ -0,0 +1,197 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_gpio.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      GPIO firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_GPIO_H
+#define __CH32V30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+                                 
+/* Output Maximum frequency selection */
+typedef enum
+{ 
+  GPIO_Speed_10MHz = 1,
+  GPIO_Speed_2MHz, 
+  GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+/* Configuration Mode enumeration */
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IPD = 0x28,
+  GPIO_Mode_IPU = 0x48,
+  GPIO_Mode_Out_OD = 0x14,
+  GPIO_Mode_Out_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+/* GPIO Init structure definition */
+typedef struct
+{
+  uint16_t GPIO_Pin;             /* Specifies the GPIO pins to be configured.
+                                    This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOSpeed_TypeDef GPIO_Speed;  /* Specifies the speed for the selected pins.
+                                    This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOMode_TypeDef GPIO_Mode;    /* Specifies the operating mode for the selected pins.
+                                    This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+	Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0                  ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                  ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                  ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                  ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                  ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                  ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                  ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                  ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                  ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                  ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                 ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                 ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                 ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                 ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                 ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                 ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All                ((uint16_t)0xFFFF)  /* All pins selected */
+
+/* GPIO_Remap_define */
+/* PCFR1 */
+#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /* USART1 Alternate Function mapping low bit */
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /* PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /* LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /* ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /* ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /* Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /* CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_MII_RMII_SEL     ((uint32_t)0x00200080)  /* MII or RMII selection */
+#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3             ((uint32_t)0x00201000)  /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+                                                               to TIM2 Internal Trigger 1 for calibration
+                                                               (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+/* PCFR2 */
+#define GPIO_Remap_TIM8             ((uint32_t)0x80000004)  /* TIM8 Alternate Function mapping */
+#define GPIO_PartialRemap_TIM9      ((uint32_t)0x80130008)  /* TIM9 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM9         ((uint32_t)0x80130010)  /* TIM9 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM10     ((uint32_t)0x80150020)  /* TIM10 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM10        ((uint32_t)0x80150040)  /* TIM10 Full Alternate Function mapping */
+#define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /* FSMC_NADV Alternate Function mapping */
+#define GPIO_PartialRemap_USART4    ((uint32_t)0x80300001)  /* USART4 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART4       ((uint32_t)0x80300002)  /* USART4 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART5    ((uint32_t)0x80320004)  /* USART5 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART5       ((uint32_t)0x80320008)  /* USART5 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART6    ((uint32_t)0x80340010)  /* USART6 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART6       ((uint32_t)0x80340020)  /* USART6 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART7    ((uint32_t)0x80360040)  /* USART7 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART7       ((uint32_t)0x80360080)  /* USART7 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART8    ((uint32_t)0x80380100)  /* USART8 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART8       ((uint32_t)0x80380200)  /* USART8 Full Alternate Function mapping */
+#define GPIO_Remap_USART1_HighBit   ((uint32_t)0x80200400)  /* USART1 Alternate Function mapping high bit */
+
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA        ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB        ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC        ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD        ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE        ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF        ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG        ((uint8_t)0x06)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0             ((uint8_t)0x00)
+#define GPIO_PinSource1             ((uint8_t)0x01)
+#define GPIO_PinSource2             ((uint8_t)0x02)
+#define GPIO_PinSource3             ((uint8_t)0x03)
+#define GPIO_PinSource4             ((uint8_t)0x04)
+#define GPIO_PinSource5             ((uint8_t)0x05)
+#define GPIO_PinSource6             ((uint8_t)0x06)
+#define GPIO_PinSource7             ((uint8_t)0x07)
+#define GPIO_PinSource8             ((uint8_t)0x08)
+#define GPIO_PinSource9             ((uint8_t)0x09)
+#define GPIO_PinSource10            ((uint8_t)0x0A)
+#define GPIO_PinSource11            ((uint8_t)0x0B)
+#define GPIO_PinSource12            ((uint8_t)0x0C)
+#define GPIO_PinSource13            ((uint8_t)0x0D)
+#define GPIO_PinSource14            ((uint8_t)0x0E)
+#define GPIO_PinSource15            ((uint8_t)0x0F)
+
+/* Ethernet_Media_Interface */
+#define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)
+
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_i2c.h

@@ -0,0 +1,211 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_i2c.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      I2C firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_I2C_H
+#define __CH32V30x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* I2C Init structure definition  */
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /* Specifies the clock frequency.
+                                       This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /* Specifies the I2C mode.
+                                       This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /* Specifies the I2C fast mode duty cycle.
+                                       This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /* Specifies the first device own address.
+                                       This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /* Enables or disables the acknowledgement.
+                                       This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
+                                       This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* I2C_mode */
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+
+/* I2C_duty_cycle_in_fast_mode */
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
+
+/* I2C_acknowledgement */
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+
+/* I2C_transfer_direction */
+#define I2C_Direction_Transmitter       ((uint8_t)0x00)
+#define I2C_Direction_Receiver          ((uint8_t)0x01)
+
+/* I2C_acknowledged_address */
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+
+/* I2C_registers */
+#define I2C_Register_CTLR1              ((uint8_t)0x00)
+#define I2C_Register_CTLR2              ((uint8_t)0x04)
+#define I2C_Register_OADDR1             ((uint8_t)0x08)
+#define I2C_Register_OADDR2             ((uint8_t)0x0C)
+#define I2C_Register_DATAR              ((uint8_t)0x10)
+#define I2C_Register_STAR1              ((uint8_t)0x14)
+#define I2C_Register_STAR2              ((uint8_t)0x18)
+#define I2C_Register_CKCFGR             ((uint8_t)0x1C)
+#define I2C_Register_RTR                ((uint8_t)0x20)
+
+/* I2C_SMBus_alert_pin_level */
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+
+/* I2C_PEC_position */
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+
+/* I2C_NACK_position */
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+/* SR2 register flags  */
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/* SR1 register flags */
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+
+/****************I2C Master Events (Events grouped in order of communication)********************/
+
+#define I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                ((uint32_t)0x00070080)  /* TRA, BUSY, MSL, TXE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/******************I2C Slave Events (Events grouped in order of communication)******************/
+
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002)  /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082)  /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+#define I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+
+/****************************************************************************************
+*                         I2C State Monitoring Functions                     
+****************************************************************************************/
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_iwdg.h

@@ -0,0 +1,56 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_iwdg.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the  
+*                      IWDG firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_IWDG_H
+#define __CH32V30x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* IWDG_WriteAccess */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+
+/* IWDG_prescaler */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+
+/* IWDG_Flag */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_misc.h

@@ -0,0 +1,46 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_misc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      miscellaneous firmware library functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/   
+#ifndef __CH32V30X_MISC_H
+#define __CH32V30X_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* NVIC Init Structure definition */	 
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;
+  uint8_t NVIC_IRQChannelPreemptionPriority;
+  uint8_t NVIC_IRQChannelSubPriority;
+  FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+ 
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0           ((uint32_t)0x00)
+#define NVIC_PriorityGroup_1           ((uint32_t)0x01)
+#define NVIC_PriorityGroup_2           ((uint32_t)0x02)
+#define NVIC_PriorityGroup_3           ((uint32_t)0x03)
+#define NVIC_PriorityGroup_4           ((uint32_t)0x04)
+
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_opa.h

@@ -0,0 +1,75 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_opa.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      OPA firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_OPA_H
+#define __CH32V30x_OPA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+#define OPA_PSEL_OFFSET 3
+#define OPA_NSEL_OFFSET 2
+#define OPA_MODE_OFFSET 1
+
+
+/* OPA member enumeration */
+typedef enum
+{
+   OPA1=0,
+   OPA2,
+   OPA3,
+   OPA4
+}OPA_Num_TypeDef;
+
+/* OPA PSEL enumeration */
+typedef enum
+{
+   CHP0=0,
+   CHP1
+}OPA_PSEL_TypeDef;
+
+/* OPA NSEL enumeration */
+typedef enum
+{
+   CHN0=0,
+   CHN1
+}OPA_NSEL_TypeDef;
+
+/* OPA Mode enumeration */
+typedef enum
+{
+   OUT_IO_ADC=0,
+   OUT_IO
+}OPA_Mode_TypeDef;
+
+/* OPA Init Structure definition */
+typedef struct
+{
+  OPA_Num_TypeDef   OPA_NUM;      /* Specifies the members of OPA */
+  OPA_PSEL_TypeDef  PSEL;         /* Specifies the positive channel of OPA */
+  OPA_NSEL_TypeDef  NSEL;         /* Specifies the negative channel of OPA */
+  OPA_Mode_TypeDef  Mode;         /* Specifies the mode of OPA */
+}OPA_InitTypeDef;
+
+
+void OPA_DeInit(void);
+void OPA_Init(OPA_InitTypeDef* OPA_InitStruct);
+void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct);
+void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_pwr.h

@@ -0,0 +1,64 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_pwr.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the PWR  
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_PWR_H
+#define __CH32V30x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* PVD_detection_level  */
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+	 
+/* Regulator_state_is_STOP_mode */
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+
+/* STOP_mode_entry */
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+ 
+/* PWR_Flag */
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+void PWR_EnterSTANDBYMode_RAM(void);
+void PWR_EnterSTANDBYMode_RAM_LV(void);
+void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
+void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_rcc.h

@@ -0,0 +1,456 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rcc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RCC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_RCC_H
+#define __CH32V30x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* RCC_Exported_Types */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;  /* returns SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;    /* returns HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;   /* returns PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;   /* returns PCLK2 clock frequency expressed in Hz */
+  uint32_t ADCCLK_Frequency;  /* returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* HSE_configuration */
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+
+#ifdef CH32V30x_D8
+#define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+#define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+
+#else
+#define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
+
+#endif
+
+/* PLL_multiplication_factor */
+#ifdef CH32V30x_D8
+#define RCC_PLLMul_2                     ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                     ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                     ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                     ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                     ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                     ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                    ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                    ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                    ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                    ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                    ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                    ((uint32_t)0x00380000)
+#define RCC_PLLMul_18                    ((uint32_t)0x003C0000)
+
+#else
+#define RCC_PLLMul_18_EXTEN              ((uint32_t)0x00000000)
+#define RCC_PLLMul_3_EXTEN               ((uint32_t)0x00040000)
+#define RCC_PLLMul_4_EXTEN               ((uint32_t)0x00080000)
+#define RCC_PLLMul_5_EXTEN               ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6_EXTEN               ((uint32_t)0x00100000)
+#define RCC_PLLMul_7_EXTEN               ((uint32_t)0x00140000)
+#define RCC_PLLMul_8_EXTEN               ((uint32_t)0x00180000)
+#define RCC_PLLMul_9_EXTEN               ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10_EXTEN              ((uint32_t)0x00200000)
+#define RCC_PLLMul_11_EXTEN              ((uint32_t)0x00240000)
+#define RCC_PLLMul_12_EXTEN              ((uint32_t)0x00280000)
+#define RCC_PLLMul_13_EXTEN              ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14_EXTEN              ((uint32_t)0x00300000)
+#define RCC_PLLMul_6_5_EXTEN             ((uint32_t)0x00340000)
+#define RCC_PLLMul_15_EXTEN              ((uint32_t)0x00380000)
+#define RCC_PLLMul_16_EXTEN              ((uint32_t)0x003C0000)
+
+#endif
+
+/* PREDIV1_division_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PREDIV1_Div1                 ((uint32_t)0x00000000)
+#define RCC_PREDIV1_Div2                 ((uint32_t)0x00000001)
+#define RCC_PREDIV1_Div3                 ((uint32_t)0x00000002)
+#define RCC_PREDIV1_Div4                 ((uint32_t)0x00000003)
+#define RCC_PREDIV1_Div5                 ((uint32_t)0x00000004)
+#define RCC_PREDIV1_Div6                 ((uint32_t)0x00000005)
+#define RCC_PREDIV1_Div7                 ((uint32_t)0x00000006)
+#define RCC_PREDIV1_Div8                 ((uint32_t)0x00000007)
+#define RCC_PREDIV1_Div9                 ((uint32_t)0x00000008)
+#define RCC_PREDIV1_Div10                ((uint32_t)0x00000009)
+#define RCC_PREDIV1_Div11                ((uint32_t)0x0000000A)
+#define RCC_PREDIV1_Div12                ((uint32_t)0x0000000B)
+#define RCC_PREDIV1_Div13                ((uint32_t)0x0000000C)
+#define RCC_PREDIV1_Div14                ((uint32_t)0x0000000D)
+#define RCC_PREDIV1_Div15                ((uint32_t)0x0000000E)
+#define RCC_PREDIV1_Div16                ((uint32_t)0x0000000F)
+
+#endif
+
+/* PREDIV1_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_PREDIV1_Source_HSE           ((uint32_t)0x00000000)
+#define RCC_PREDIV1_Source_PLL2          ((uint32_t)0x00010000)
+
+#endif
+
+/* PREDIV2_division_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PREDIV2_Div1                 ((uint32_t)0x00000000)
+#define RCC_PREDIV2_Div2                 ((uint32_t)0x00000010)
+#define RCC_PREDIV2_Div3                 ((uint32_t)0x00000020)
+#define RCC_PREDIV2_Div4                 ((uint32_t)0x00000030)
+#define RCC_PREDIV2_Div5                 ((uint32_t)0x00000040)
+#define RCC_PREDIV2_Div6                 ((uint32_t)0x00000050)
+#define RCC_PREDIV2_Div7                 ((uint32_t)0x00000060)
+#define RCC_PREDIV2_Div8                 ((uint32_t)0x00000070)
+#define RCC_PREDIV2_Div9                 ((uint32_t)0x00000080)
+#define RCC_PREDIV2_Div10                ((uint32_t)0x00000090)
+#define RCC_PREDIV2_Div11                ((uint32_t)0x000000A0)
+#define RCC_PREDIV2_Div12                ((uint32_t)0x000000B0)
+#define RCC_PREDIV2_Div13                ((uint32_t)0x000000C0)
+#define RCC_PREDIV2_Div14                ((uint32_t)0x000000D0)
+#define RCC_PREDIV2_Div15                ((uint32_t)0x000000E0)
+#define RCC_PREDIV2_Div16                ((uint32_t)0x000000F0)
+
+#endif
+
+/* PLL2_multiplication_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PLL2Mul_2_5                  ((uint32_t)0x00000000)
+#define RCC_PLL2Mul_12_5                 ((uint32_t)0x00000100)
+#define RCC_PLL2Mul_4                    ((uint32_t)0x00000200)
+#define RCC_PLL2Mul_5                    ((uint32_t)0x00000300)
+#define RCC_PLL2Mul_6                    ((uint32_t)0x00000400)
+#define RCC_PLL2Mul_7                    ((uint32_t)0x00000500)
+#define RCC_PLL2Mul_8                    ((uint32_t)0x00000600)
+#define RCC_PLL2Mul_9                    ((uint32_t)0x00000700)
+#define RCC_PLL2Mul_10                   ((uint32_t)0x00000800)
+#define RCC_PLL2Mul_11                   ((uint32_t)0x00000900)
+#define RCC_PLL2Mul_12                   ((uint32_t)0x00000A00)
+#define RCC_PLL2Mul_13                   ((uint32_t)0x00000B00)
+#define RCC_PLL2Mul_14                   ((uint32_t)0x00000C00)
+#define RCC_PLL2Mul_15                   ((uint32_t)0x00000D00)
+#define RCC_PLL2Mul_16                   ((uint32_t)0x00000E00)
+#define RCC_PLL2Mul_20                   ((uint32_t)0x00000F00)
+
+#endif
+
+/* PLL3_multiplication_factor */
+#ifdef CH32V30x_D8C
+#define RCC_PLL3Mul_2_5                  ((uint32_t)0x00000000)
+#define RCC_PLL3Mul_12_5                 ((uint32_t)0x00001000)
+#define RCC_PLL3Mul_4                    ((uint32_t)0x00002000)
+#define RCC_PLL3Mul_5                    ((uint32_t)0x00003000)
+#define RCC_PLL3Mul_6                    ((uint32_t)0x00004000)
+#define RCC_PLL3Mul_7                    ((uint32_t)0x00005000)
+#define RCC_PLL3Mul_8                    ((uint32_t)0x00006000)
+#define RCC_PLL3Mul_9                    ((uint32_t)0x00007000)
+#define RCC_PLL3Mul_10                   ((uint32_t)0x00008000)
+#define RCC_PLL3Mul_11                   ((uint32_t)0x00009000)
+#define RCC_PLL3Mul_12                   ((uint32_t)0x0000A000)
+#define RCC_PLL3Mul_13                   ((uint32_t)0x0000B000)
+#define RCC_PLL3Mul_14                   ((uint32_t)0x0000C000)
+#define RCC_PLL3Mul_15                   ((uint32_t)0x0000D000)
+#define RCC_PLL3Mul_16                   ((uint32_t)0x0000E000)
+#define RCC_PLL3Mul_20                   ((uint32_t)0x0000F000)
+
+#endif
+
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+
+/* APB1_APB2_clock_source */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+#ifdef CH32V30x_D8C
+#define RCC_IT_PLL2RDY                   ((uint8_t)0x20)
+#define RCC_IT_PLL3RDY                   ((uint8_t)0x40)
+
+#endif
+
+/* USB_OTG_FS_clock_source */
+#define RCC_OTGFSCLKSource_PLLCLK_Div1   ((uint8_t)0x00)
+#define RCC_OTGFSCLKSource_PLLCLK_Div2   ((uint8_t)0x01)
+#define RCC_OTGFSCLKSource_PLLCLK_Div3   ((uint8_t)0x02)
+
+/* I2S2_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_I2S2CLKSource_SYSCLK         ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_PLL3_VCO       ((uint8_t)0x01)
+
+#endif
+
+/* I2S3_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_I2S3CLKSource_SYSCLK         ((uint8_t)0x00)
+#define RCC_I2S3CLKSource_PLL3_VCO       ((uint8_t)0x01)
+
+#endif
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+
+/* LSE_configuration */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+
+/* RTC_clock_source */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_RNG                ((uint32_t)0x00000200)
+#define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
+#define RCC_AHBPeriph_USBHS              ((uint32_t)0x00000800)
+#define RCC_AHBPeriph_OTG_FS             ((uint32_t)0x00001000)
+#define RCC_AHBPeriph_DVP                ((uint32_t)0x00002000)
+#define RCC_AHBPeriph_ETH_MAC            ((uint32_t)0x00004000)
+#define RCC_AHBPeriph_ETH_MAC_Tx         ((uint32_t)0x00008000)
+#define RCC_AHBPeriph_ETH_MAC_Rx         ((uint32_t)0x00010000)
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_UART6             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_UART7             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_UART8             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+
+#ifdef CH32V30x_D8C
+#define RCC_MCO_PLL2CLK                  ((uint8_t)0x08)
+#define RCC_MCO_PLL3CLK_Div2             ((uint8_t)0x09)
+#define RCC_MCO_XT1                      ((uint8_t)0x0A)
+#define RCC_MCO_PLL3CLK                  ((uint8_t)0x0B)
+
+#endif
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+#ifdef CH32V30x_D8C
+#define RCC_FLAG_PLL2RDY                 ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY                 ((uint8_t)0x3D)
+
+#endif
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8      ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK           ((uint32_t)0x00000004)
+
+/* RNG_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_RNGCLKSource_SYSCLK          ((uint32_t)0x00)
+#define RCC_RNGCLKSource_PLL3_VCO        ((uint32_t)0x01)
+
+#endif
+
+/* ETH1G_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_ETH1GCLKSource_PLL2_VCO      ((uint32_t)0x00)
+#define RCC_ETH1GCLKSource_PLL3_VCO      ((uint32_t)0x01)
+#define RCC_ETH1GCLKSource_PB1_IN        ((uint32_t)0x02)
+
+#endif
+
+/* USBFS_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_USBPLL_Div1                  ((uint32_t)0x00)
+#define RCC_USBPLL_Div2                  ((uint32_t)0x01)
+#define RCC_USBPLL_Div3                  ((uint32_t)0x02)
+#define RCC_USBPLL_Div4                  ((uint32_t)0x03)
+#define RCC_USBPLL_Div5                  ((uint32_t)0x04)
+#define RCC_USBPLL_Div6                  ((uint32_t)0x05)
+#define RCC_USBPLL_Div7                  ((uint32_t)0x06)
+#define RCC_USBPLL_Div8                  ((uint32_t)0x07)
+
+#endif
+
+/* USBHSPLL_clock_source */
+#ifdef CH32V30x_D8C
+#define RCC_HSBHSPLLCLKSource_HSE        ((uint32_t)0x00)
+#define RCC_HSBHSPLLCLKSource_HSI        ((uint32_t)0x01)
+
+#endif
+
+/* USBHSPLLCKREF_clock_select */
+#ifdef CH32V30x_D8C
+#define RCC_USBHSPLLCKREFCLK_3M          ((uint32_t)0x00)
+#define RCC_USBHSPLLCKREFCLK_4M          ((uint32_t)0x01)
+#define RCC_USBHSPLLCKREFCLK_8M          ((uint32_t)0x02)
+#define RCC_USBHSPLLCKREFCLK_5M          ((uint32_t)0x03)
+
+#endif
+
+/* OTGUSBCLK48M_clock_source */
+#define RCC_USBCLK48MCLKSource_PLLCLK    ((uint32_t)0x00)
+#define RCC_USBCLK48MCLKSource_USBPHY    ((uint32_t)0x01)
+
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+void RCC_ADCCLKADJcmd(FunctionalState NewState);
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
+
+#ifdef CH32V30x_D8C
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+void RCC_PLL2Cmd(FunctionalState NewState);
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+void RCC_PLL3Cmd(FunctionalState NewState);
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
+void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
+void RCC_ETH1G_125Mcmd(FunctionalState NewState);
+void RCC_USBHSConfig(uint32_t RCC_USBHS);
+void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
+void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
+void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_rng.h

@@ -0,0 +1,41 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rng.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the
+*                      RNG firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_RNG_H
+#define __CH32V30x_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#include "ch32v30x.h"
+
+ /* RNG_flags_definition*/
+#define RNG_FLAG_DRDY               ((uint8_t)0x0001) /* Data ready */
+#define RNG_FLAG_CECS               ((uint8_t)0x0002) /* Clock error current status */
+#define RNG_FLAG_SECS               ((uint8_t)0x0004) /* Seed error current status */
+
+/* RNG_interrupts_definition */
+#define RNG_IT_CEI                  ((uint8_t)0x20) /* Clock error interrupt */
+#define RNG_IT_SEI                  ((uint8_t)0x40) /* Seed error interrupt */
+
+
+void RNG_Cmd(FunctionalState NewState);
+uint32_t RNG_GetRandomNumber(void);
+void RNG_ITConfig(FunctionalState NewState);
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
+void RNG_ClearFlag(uint8_t RNG_FLAG);
+ITStatus RNG_GetITStatus(uint8_t RNG_IT);
+void RNG_ClearITPendingBit(uint8_t RNG_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_rtc.h

@@ -0,0 +1,54 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rtc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the RTC  
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_RTC_H
+#define __CH32V30x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+/* RTC_interrupts_define */
+#define RTC_IT_OW            ((uint16_t)0x0004)  /* Overflow interrupt */
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /* Alarm interrupt */
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /* Second interrupt */
+
+/* RTC_interrupts_flags */
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /* Registers Synchronized flag */
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /* Overflow flag */
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /* Alarm flag */
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /* Second flag */
+	 
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_sdio.h

@@ -0,0 +1,254 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_sdio.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the SDIO
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_SDIO_H
+#define __CH32V30x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* SDIO Init structure definition */
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /* Specifies the clock transition on which the bit capture is made.
+                                         This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /* Specifies whether the SDIO Clock divider bypass is
+                                         enabled or disabled.
+                                         This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /* Specifies whether SDIO Clock output is enabled or
+                                         disabled when the bus is idle.
+                                         This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /* Specifies the SDIO bus width.
+                                         This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /* Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                         This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /* Specifies the clock frequency of the SDIO controller.
+                                         This parameter can be a value between 0x00 and 0xFF. */
+                                           
+} SDIO_InitTypeDef;
+
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /* Specifies the SDIO command argument which is sent
+                              to a card as part of a command message. If a command
+                              contains an argument, it must be loaded into this register
+                              before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /* Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /* Specifies the SDIO response type.
+                              This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                              This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /* Specifies whether SDIO Command path state machine (CPSM)
+                              is enabled or disabled.
+                              This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /* Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /* Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /* Specifies the data block size for block transfer.
+                                   This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /* Specifies the data transfer direction, whether the transfer
+                                   is a read or write.
+                                   This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /* Specifies whether data transfer is in stream or block mode.
+                                   This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /* Specifies whether SDIO Data path state machine (DPSM)
+                                   is enabled or disabled.
+                                   This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+
+/* SDIO_Clock_Edge */
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+
+/* SDIO_Clock_Bypass */
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+
+/* SDIO_Clock_Power_Save */
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+
+/* SDIO_Bus_Wide */
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+
+/* SDIO_Hardware_Flow_Control */
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+
+/* SDIO_Power_State */
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+
+/* SDIO_Interrupt_sources */
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+
+/* SDIO_Response_Type */
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+
+/* SDIO_Wait_Interrupt_State */
+#define SDIO_Wait_No                        ((uint32_t)0x00000000)
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100)
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200)
+
+/* SDIO_CPSM_State */
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+
+/* SDIO_Response_Registers */
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+
+/* SDIO_Data_Block_Size */
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+
+/* SDIO_Transfer_Direction */
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+
+/* SDIO_Transfer_Type */
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+
+/* SDIO_DPSM_State */
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+
+/* SDIO_Flags */
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+
+/* SDIO_Read_Wait_Mode */
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000000)
+
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_spi.h

@@ -0,0 +1,229 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_spi.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the  
+*                      SPI firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_SPI_H
+#define __CH32V30x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* SPI Init structure definition */
+typedef struct
+{
+  uint16_t SPI_Direction;           /* Specifies the SPI unidirectional or bidirectional data mode.
+                                       This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /* Specifies the SPI operating mode.
+                                       This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /* Specifies the SPI data size.
+                                       This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /* Specifies the serial clock steady state.
+                                       This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /* Specifies the clock active edge for the bit capture.
+                                       This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /* Specifies whether the NSS signal is managed by
+                                       hardware (NSS pin) or by software using the SSI bit.
+                                       This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /* Specifies the Baud Rate prescaler value which will be
+                                       used to configure the transmit and receive SCK clock.
+                                       This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                       @note The communication clock is derived from the master
+                                             clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /* Specifies whether data transfers start from MSB or LSB bit.
+                                       This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /* Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/* I2S Init structure definition */
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /* Specifies the I2S operating mode.
+                                This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /* Specifies the standard used for the I2S communication.
+                                This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /* Specifies the data format for the I2S communication.
+                                This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /* Specifies whether the I2S MCLK output is enabled or not.
+                                This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /* Specifies the frequency selected for the I2S communication.
+                                This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /* Specifies the idle state of the I2S clock.
+                                This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* SPI_data_direction */  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+
+/* SPI_mode */
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+
+/* SPI_data_size */
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+
+/* SPI_Clock_Polarity */
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+
+/* SPI_Clock_Phase */
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+
+/* SPI_Slave_Select_management */
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+
+/* SPI_BaudRate_Prescaler */
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+
+/* SPI_MSB_LSB_transmission */
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+
+/* I2S_Mode */
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+
+/* I2S_Standard */
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+
+/* I2S_Data_Format */
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+
+/* I2S_MCLK_Output */
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+
+/* I2S_Audio_Frequency */
+#define I2S_AudioFreq_192k              ((uint32_t)192000)
+#define I2S_AudioFreq_96k               ((uint32_t)96000)
+#define I2S_AudioFreq_48k               ((uint32_t)48000)
+#define I2S_AudioFreq_44k               ((uint32_t)44100)
+#define I2S_AudioFreq_32k               ((uint32_t)32000)
+#define I2S_AudioFreq_22k               ((uint32_t)22050)
+#define I2S_AudioFreq_16k               ((uint32_t)16000)
+#define I2S_AudioFreq_11k               ((uint32_t)11025)
+#define I2S_AudioFreq_8k                ((uint32_t)8000)
+#define I2S_AudioFreq_Default           ((uint32_t)2)
+
+/* I2S_Clock_Polarity */
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+
+/* SPI_I2S_DMA_transfer_requests */
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+
+/* SPI_NSS_internal_software_management */
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+
+/* SPI_CRC_Transmit_Receive */
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+
+/* SPI_direction_transmit_receive */
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+
+/* SPI_I2S_interrupts_definition */
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+
+/* SPI_I2S_flags_definition */
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_tim.h

@@ -0,0 +1,515 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_tim.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the  
+*                      TIM firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_TIM_H
+#define __CH32V30x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* TIM Time Base Init structure definition */
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /* Specifies the prescaler value used to divide the TIM clock.
+                                     This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /* Specifies the counter mode.
+                                     This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint16_t TIM_Period;            /* Specifies the period value to be loaded into the active
+                                     Auto-Reload Register at the next update event.
+                                     This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /* Specifies the clock division.
+                                    This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /* Specifies the repetition counter value. Each time the RCR downcounter
+                                     reaches zero, an update event is generated and counting restarts
+                                     from the RCR value (N).
+                                     This means in PWM mode that (N+1) corresponds to:
+                                        - the number of PWM periods in edge-aligned mode
+                                        - the number of half PWM period in center-aligned mode
+                                     This parameter must be a number between 0x00 and 0xFF. 
+                                     @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;       
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+  uint16_t TIM_OCMode;        /* Specifies the TIM mode.
+                                 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /* Specifies the TIM Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_state */
+
+  uint16_t TIM_OutputNState;  /* Specifies the TIM complementary Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_Pulse;         /* Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                 This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_OCPolarity;    /* Specifies the output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /* Specifies the complementary output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCIdleState;   /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCNIdleState;  /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+  uint16_t TIM_Channel;      /* Specifies the TIM channel.
+                                This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /* Specifies the active edge of the input signal.
+                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /* Specifies the input.
+                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /* Specifies the Input Capture Prescaler.
+                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /* Specifies the input capture filter.
+                                This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+  uint16_t TIM_OSSRState;        /* Specifies the Off-State selection used in Run mode.
+                                    This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /* Specifies the Off-State used in Idle state.
+                                    This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /* Specifies the LOCK level parameters.
+                                    This parameter can be a value of @ref Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /* Specifies the delay time between the switching-off and the
+                                    switching-on of the outputs.
+                                    This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /* Specifies whether the TIM Break input is enabled or not. 
+                                    This parameter can be a value of @ref Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /* Specifies the TIM Break Input pin polarity.
+                                    This parameter can be a value of @ref Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /* Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                    This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* TIM_Output_Compare_and_PWM_modes */
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+
+/* TIM_One_Pulse_Mode */
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+
+/* TIM_Channel */
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+/* TIM_Clock_Division_CKD */
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+
+/* TIM_Counter_Mode */
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+
+/* TIM_Output_Compare_Polarity */
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+
+/* TIM_Output_Compare_N_Polarity */  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+
+/* TIM_Output_Compare_state */
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+
+/* TIM_Output_Compare_N_state */
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+
+/* TIM_Capture_Compare_state */
+#define TIM_CCx_Enable                     ((uint16_t)0x0001)
+#define TIM_CCx_Disable                    ((uint16_t)0x0000)
+
+/* TIM_Capture_Compare_N_state */
+#define TIM_CCxN_Enable                    ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                   ((uint16_t)0x0000)
+
+/* Break_Input_enable_disable */
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+
+/* Break_Polarity */
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+
+/* TIM_AOE_Bit_Set_Reset */
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+
+/* Lock_level */
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+
+/* OSSI_Off_State_Selection_for_Idle_mode_state */
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+
+/* OSSR_Off_State_Selection_for_Run_mode_state */
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Idle_State */
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_N_Idle_State */
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+
+/* TIM_Input_Capture_Polarity */
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+                                     
+/* TIM_Input_Capture_Selection */
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                 connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be
+                                                                 connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+
+/* TIM_Input_Capture_Prescaler */
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /* Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /* Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /* Capture performed once every 8 events. */
+
+/* TIM_interrupt_sources */
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+
+/* TIM_DMA_Base_address */
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+
+/* TIM_DMA_Burst_Length */
+#define TIM_DMABurstLength_1Transfer       ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers      ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers      ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers      ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers      ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers      ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers      ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers      ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers      ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers     ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers     ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers     ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers     ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers     ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers     ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers     ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers     ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers     ((uint16_t)0x1100)
+
+/* TIM_DMA_sources */
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+
+/* TIM_External_Trigger_Prescaler */
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+
+/* TIM_Internal_Trigger_Selection */
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+
+/* TIM_TIx_External_Clock_Source */
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/* TIM_External_Trigger_Polarity */
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+
+/* TIM_Prescaler_Reload_Mode */
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+
+/* TIM_Forced_Action */
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+
+/* TIM_Encoder_Mode */
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+
+/* TIM_Event_Source */
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+
+/* TIM_Update_Source */
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow
+                                                                 or the setting of UG bit, or an update generation
+                                                                 through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
+
+/* TIM_Output_Compare_Preload_State */
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Fast_State */
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Clear_State */
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+
+/* TIM_Trigger_Output_Source */
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+
+/* TIM_Slave_Mode */
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+
+/* TIM_Master_Slave_Mode */
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+
+/* TIM_Flags */
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+
+/* TIM_Legacy */
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_usart.h

@@ -0,0 +1,195 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_usart.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      USART firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_USART_H
+#define __CH32V30x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+ 
+
+/* USART Init Structure definition */  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /* This member configures the USART communication baud rate.
+                                         The baud rate is computed using the following formula:
+                                          - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                          - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+  uint16_t USART_WordLength;          /* Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /* Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /* Specifies the parity mode.
+                                         This parameter can be a value of @ref USART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /* Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /* Specifies whether the USART clock is enabled or disabled.
+                             This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /* Specifies the steady state value of the serial clock.
+                             This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /* Specifies the clock transition on which the bit capture is made.
+                             This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
+                             data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                             This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* USART_Word_Length */ 
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+/* USART_Stop_Bits */  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+
+/* USART_Parity */  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+
+/* USART_Mode */ 
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+#define USART_IT_ORE                          USART_IT_ORE_ER
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b       ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b       ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/include/ch32v30x_wwdg.h

@@ -0,0 +1,42 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_wwdg.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the WWDG 
+*                      firmware library.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_WWDG_H
+#define __CH32V30x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+
+/* WWDG_Prescaler */  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+
+  
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_adc.c

@@ -0,0 +1,1180 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_adc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the ADC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_adc.h"
+#include "ch32v30x_rcc.h"
+
+/* ADC DISCNUM mask */
+#define CTLR1_DISCNUM_Reset              ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CTLR1_DISCEN_Set                 ((uint32_t)0x00000800)
+#define CTLR1_DISCEN_Reset               ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CTLR1_JAUTO_Set                  ((uint32_t)0x00000400)
+#define CTLR1_JAUTO_Reset                ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CTLR1_JDISCEN_Set                ((uint32_t)0x00001000)
+#define CTLR1_JDISCEN_Reset              ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CTLR1_AWDCH_Reset                ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTLR1_AWDMode_Reset              ((uint32_t)0xFF3FFDFF)
+
+/* CTLR1 register Mask */
+#define CTLR1_CLEAR_Mask                 ((uint32_t)0xE0F0FEFF)
+
+/* ADC ADON mask */
+#define CTLR2_ADON_Set                   ((uint32_t)0x00000001)
+#define CTLR2_ADON_Reset                 ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTLR2_DMA_Set                    ((uint32_t)0x00000100)
+#define CTLR2_DMA_Reset                  ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CTLR2_RSTCAL_Set                 ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTLR2_CAL_Set                    ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CTLR2_SWSTART_Set                ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CTLR2_EXTTRIG_Set                ((uint32_t)0x00100000)
+#define CTLR2_EXTTRIG_Reset              ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTLR2_EXTTRIG_SWSTART_Set        ((uint32_t)0x00500000)
+#define CTLR2_EXTTRIG_SWSTART_Reset      ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CTLR2_JEXTSEL_Reset              ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CTLR2_JEXTTRIG_Set               ((uint32_t)0x00008000)
+#define CTLR2_JEXTTRIG_Reset             ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CTLR2_JSWSTART_Set               ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTLR2_JEXTTRIG_JSWSTART_Set      ((uint32_t)0x00208000)
+#define CTLR2_JEXTTRIG_JSWSTART_Reset    ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTLR2_TSVREFE_Set                ((uint32_t)0x00800000)
+#define CTLR2_TSVREFE_Reset              ((uint32_t)0xFF7FFFFF)
+
+/* CTLR2 register Mask */
+#define CTLR2_CLEAR_Mask                 ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define RSQR3_SQ_Set                     ((uint32_t)0x0000001F)
+#define RSQR2_SQ_Set                     ((uint32_t)0x0000001F)
+#define RSQR1_SQ_Set                     ((uint32_t)0x0000001F)
+
+/* RSQR1 register Mask */
+#define RSQR1_CLEAR_Mask                 ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define ISQR_JSQ_Set                     ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define ISQR_JL_Set                      ((uint32_t)0x00300000)
+#define ISQR_JL_Reset                    ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SAMPTR1_SMP_Set                  ((uint32_t)0x00000007)
+#define SAMPTR2_SMP_Set                  ((uint32_t)0x00000007)
+
+/* ADC IDATARx registers offset */
+#define IDATAR_Offset                    ((uint8_t)0x28)
+
+/* ADC1 RDATAR register base address */
+#define RDATAR_ADDRESS                   ((uint32_t)0x4001244C)
+
+/*********************************************************************
+ * @fn      ADC_DeInit
+ *
+ * @brief   Deinitializes the ADCx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  none
+ */
+void ADC_DeInit(ADC_TypeDef *ADCx)
+{
+    if(ADCx == ADC1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+    }
+    else if(ADCx == ADC2)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_Init
+ *
+ * @brief   Initializes the ADCx peripheral according to the specified
+ *        parameters in the ADC_InitStruct.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_InitStruct - pointer to an ADC_InitTypeDef structure that
+ *        contains the configuration information for the specified ADC
+ *        peripheral.
+ *
+ * @return  none
+ */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
+{
+    uint32_t tmpreg1 = 0;
+    uint8_t  tmpreg2 = 0;
+
+    tmpreg1 = ADCx->CTLR1;
+    tmpreg1 &= CTLR1_CLEAR_Mask;
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer |
+                          (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+    ADCx->CTLR1 = tmpreg1;
+
+    tmpreg1 = ADCx->CTLR2;
+    tmpreg1 &= CTLR2_CLEAR_Mask;
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+                          ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+    ADCx->CTLR2 = tmpreg1;
+
+    tmpreg1 = ADCx->RSQR1;
+    tmpreg1 &= RSQR1_CLEAR_Mask;
+    tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+    tmpreg1 |= (uint32_t)tmpreg2 << 20;
+    ADCx->RSQR1 = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_StructInit
+ *
+ * @brief   Fills each ADC_InitStruct member with its default value.
+ *
+ * @param   ADC_InitStruct - pointer to an ADC_InitTypeDef structure that
+ *        contains the configuration information for the specified ADC
+ *        peripheral.
+ *
+ * @return  none
+ */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
+{
+    ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+    ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+    ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+    ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+    ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+    ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/*********************************************************************
+ * @fn      ADC_Cmd
+ *
+ * @brief   Enables or disables the specified ADC peripheral.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_ADON_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_ADON_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_DMACmd
+ *
+ * @brief   Enables or disables the specified ADC DMA request.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_DMA_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_DMA_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ITConfig
+ *
+ * @brief   Enables or disables the specified ADC interrupts.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt sources to be enabled or disabled.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+    uint8_t itmask = 0;
+
+    itmask = (uint8_t)ADC_IT;
+
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= itmask;
+    }
+    else
+    {
+        ADCx->CTLR1 &= (~(uint32_t)itmask);
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ResetCalibration
+ *
+ * @brief   Resets the selected ADC calibration registers.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  none
+ */
+void ADC_ResetCalibration(ADC_TypeDef *ADCx)
+{
+    ADCx->CTLR2 |= CTLR2_RSTCAL_Set;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetResetCalibrationStatus
+ *
+ * @brief   Gets the selected ADC reset calibration registers status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_StartCalibration
+ *
+ * @brief   Starts the selected ADC calibration process.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  None
+ */
+void ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+    ADCx->CTLR2 |= CTLR2_CAL_Set;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetCalibrationStatus
+ *
+ * @brief   Gets the selected ADC calibration status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_SoftwareStartConvCmd
+ *
+ * @brief   Enables or disables the selected ADC software start conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetSoftwareStartConvStatus
+ *
+ * @brief   Gets the selected ADC Software start conversion Status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_DiscModeChannelCountConfig
+ *
+ * @brief   Configures the discontinuous mode for the selected ADC regular
+ *        group channel.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          Number - specifies the discontinuous mode regular channel
+ *            count value(1-8).
+ *
+ * @return  None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->CTLR1;
+    tmpreg1 &= CTLR1_DISCNUM_Reset;
+    tmpreg2 = Number - 1;
+    tmpreg1 |= tmpreg2 << 13;
+    ADCx->CTLR1 = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_DiscModeCmd
+ *
+ * @brief   Enables or disables the discontinuous mode on regular group
+ *        channel for the specified ADC.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_DISCEN_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_DISCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_RegularChannelConfig
+ *
+ * @brief   Configures for the selected ADC regular channel its corresponding
+ *        rank in the sequencer and its sample time.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *          Rank - The rank in the regular group sequencer.
+ *            This parameter must be between 1 to 16.
+ *          ADC_SampleTime - The sample time value to be set for the selected channel.
+ *            ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles.
+ *            ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles.
+ *            ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles.
+ *            ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles.
+ *            ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles.
+ *            ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles.
+ *            ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles.
+ *            ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles.
+ *
+ * @return  None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+    if(ADC_Channel > ADC_Channel_9)
+    {
+        tmpreg1 = ADCx->SAMPTR1;
+        tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR1 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->SAMPTR2;
+        tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel);
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR2 = tmpreg1;
+    }
+
+    if(Rank < 7)
+    {
+        tmpreg1 = ADCx->RSQR3;
+        tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR3 = tmpreg1;
+    }
+    else if(Rank < 13)
+    {
+        tmpreg1 = ADCx->RSQR2;
+        tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR2 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->RSQR1;
+        tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR1 = tmpreg1;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigConvCmd
+ *
+ * @brief   Enables or disables the ADCx conversion through external trigger.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_EXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetConversionValue
+ *
+ * @brief   Returns the last ADCx conversion result data for regular channel.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  ADCx->RDATAR - The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
+{
+    return (uint16_t)ADCx->RDATAR;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetDualModeConversionValue
+ *
+ * @brief   Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ *
+ * @return  RDATAR_ADDRESS - The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+    return (*(__IO uint32_t *)RDATAR_ADDRESS);
+}
+
+/*********************************************************************
+ * @fn      ADC_AutoInjectedConvCmd
+ *
+ * @brief   Enables or disables the selected ADC automatic injected group
+ *        conversion after regular one.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_JAUTO_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_JAUTO_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedDiscModeCmd
+ *
+ * @brief   Enables or disables the discontinuous mode for injected group
+ *        channel for the specified ADC.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_JDISCEN_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_JDISCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigInjectedConvConfig
+ *
+ * @brief   Configures the ADCx external trigger for injected channels conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_ExternalTrigInjecConv - specifies the ADC trigger to start
+ *        injected conversion.
+ *            ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected.
+ *            ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected.
+ *            ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected.
+ *            ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt
+ *        line 15 event selected.
+ *            ADC_ExternalTrigInjecConv_None: Injected conversion started
+ *        by software and not by external trigger.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR2;
+    tmpreg &= CTLR2_JEXTSEL_Reset;
+    tmpreg |= ADC_ExternalTrigInjecConv;
+    ADCx->CTLR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigInjectedConvCmd
+ *
+ * @brief   Enables or disables the ADCx injected channels conversion through
+ *        external trigger.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_SoftwareStartInjectedConvCmd
+ *
+ * @brief   Enables or disables the selected ADC start of the injected
+ *        channels conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetSoftwareStartInjectedConvCmdStatus
+ *
+ * @brief   Gets the selected ADC Software start injected conversion Status.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedChannelConfig
+ *
+ * @brief   Configures for the selected ADC injected channel its corresponding
+ *        rank in the sequencer and its sample time.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *          Rank - The rank in the regular group sequencer.
+ *            This parameter must be between 1 to 4.
+ *          ADC_SampleTime - The sample time value to be set for the selected channel.
+ *            ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles.
+ *            ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles.
+ *            ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles.
+ *            ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles.
+ *            ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles.
+ *            ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles.
+ *            ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles.
+ *            ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles.
+ *
+ * @return  None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+
+    if(ADC_Channel > ADC_Channel_9)
+    {
+        tmpreg1 = ADCx->SAMPTR1;
+        tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR1 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->SAMPTR2;
+        tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel);
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR2 = tmpreg1;
+    }
+
+    tmpreg1 = ADCx->ISQR;
+    tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20;
+    tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    tmpreg1 &= ~tmpreg2;
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    tmpreg1 |= tmpreg2;
+    ADCx->ISQR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedSequencerLengthConfig
+ *
+ * @brief   Configures the sequencer length for injected channels.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          Length - The sequencer length.
+ *            This parameter must be a number between 1 to 4.
+ *
+ * @return  None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->ISQR;
+    tmpreg1 &= ISQR_JL_Reset;
+    tmpreg2 = Length - 1;
+    tmpreg1 |= tmpreg2 << 20;
+    ADCx->ISQR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_SetInjectedOffset
+ *
+ * @brief   Set the injected channels conversion value offset.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_InjectedChannel: the ADC injected channel to set its offset.
+ *            ADC_InjectedChannel_1 - Injected Channel1 selected.
+ *            ADC_InjectedChannel_2 - Injected Channel2 selected.
+ *            ADC_InjectedChannel_3 - Injected Channel3 selected.
+ *            ADC_InjectedChannel_4 - Injected Channel4 selected.
+ *          Offset - the offset value for the selected ADC injected channel.
+ *            This parameter must be a 12bit value.
+ *
+ * @return  None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel;
+
+    *(__IO uint32_t *)tmp = (uint32_t)Offset;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetInjectedConversionValue
+ *
+ * @brief   Returns the ADC injected channel conversion result.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_InjectedChannel - the ADC injected channel to set its offset.
+ *            ADC_InjectedChannel_1 - Injected Channel1 selected.
+ *            ADC_InjectedChannel_2 - Injected Channel2 selected.
+ *            ADC_InjectedChannel_3 - Injected Channel3 selected.
+ *            ADC_InjectedChannel_4 - Injected Channel4 selected.
+ *
+ * @return  tmp - The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel + IDATAR_Offset;
+
+    return (uint16_t)(*(__IO uint32_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogCmd
+ *
+ * @brief   Enables or disables the analog watchdog on single/all regular
+ *        or injected channels.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_AnalogWatchdog - the ADC analog watchdog configuration.
+ *            ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a
+ *        single regular channel.
+ *            ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a
+ *        single injected channel.
+ *            ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog
+ *        on a single regular or injected channel.
+ *            ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on  all
+ *        regular channel.
+ *            ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on  all
+ *        injected channel.
+ *            ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on
+ *        all regular and injected channels.
+ *            ADC_AnalogWatchdog_None - No channel guarded by the analog
+ *        watchdog.
+ *
+ * @return  none
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR1;
+    tmpreg &= CTLR1_AWDMode_Reset;
+    tmpreg |= ADC_AnalogWatchdog;
+    ADCx->CTLR1 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogThresholdsConfig
+ *
+ * @brief   Configures the high and low thresholds of the analog watchdog.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          HighThreshold - the ADC analog watchdog High threshold value.
+ *            This parameter must be a 12bit value.
+ *          LowThreshold - the ADC analog watchdog Low threshold value.
+ *            This parameter must be a 12bit value.
+ *
+ * @return  none
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+    ADCx->WDHTR = HighThreshold;
+    ADCx->WDLTR = LowThreshold;
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogSingleChannelConfig
+ *
+ * @brief   Configures the analog watchdog guarded single channel.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *
+ * @return  None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR1;
+    tmpreg &= CTLR1_AWDCH_Reset;
+    tmpreg |= ADC_Channel;
+    ADCx->CTLR1 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_TempSensorVrefintCmd
+ *
+ * @brief   Enables or disables the temperature sensor and Vrefint channel.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADC1->CTLR2 |= CTLR2_TSVREFE_Set;
+    }
+    else
+    {
+        ADC1->CTLR2 &= CTLR2_TSVREFE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified ADC flag is set or not.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_FLAG - specifies the flag to check.
+ *            ADC_FLAG_AWD - Analog watchdog flag.
+ *            ADC_FLAG_EOC - End of conversion flag.
+ *            ADC_FLAG_JEOC - End of injected group conversion flag.
+ *            ADC_FLAG_JSTRT - Start of injected group conversion flag.
+ *            ADC_FLAG_STRT - Start of regular group conversion flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_ClearFlag
+ *
+ * @brief   Clears the ADCx's pending flags.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_FLAG - specifies the flag to clear.
+ *            ADC_FLAG_AWD - Analog watchdog flag.
+ *            ADC_FLAG_EOC - End of conversion flag.
+ *            ADC_FLAG_JEOC - End of injected group conversion flag.
+ *            ADC_FLAG_JSTRT - Start of injected group conversion flag.
+ *            ADC_FLAG_STRT - Start of regular group conversion flag.
+ *
+ * @return  none
+ */
+void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
+{
+    ADCx->STATR = ~(uint32_t)ADC_FLAG;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetITStatus
+ *
+ * @brief   Checks whether the specified ADC interrupt has occurred or not.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt source to check.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t itmask = 0, enablestatus = 0;
+
+    itmask = ADC_IT >> 8;
+    enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT);
+
+    if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_ClearITPendingBit
+ *
+ * @brief   Clears the ADCx's interrupt pending bits.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt pending bit to clear.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *
+ * @return  none
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT)
+{
+    uint8_t itmask = 0;
+
+    itmask = (uint8_t)(ADC_IT >> 8);
+    ADCx->STATR = ~(uint32_t)itmask;
+}
+
+/*********************************************************************
+ * @fn      TempSensor_Volt_To_Temper
+ *
+ * @brief   Internal Temperature Sensor Voltage to temperature.
+ *
+ * @param   Value - Voltage Value(mv).
+ *
+ * @return  Temper - Temperature Value.
+ */
+s32 TempSensor_Volt_To_Temper(s32 Value)
+{
+    s32 Temper, Refer_Volt, Refer_Temper;
+    s32 k = 43;
+
+    Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF);
+    Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF);
+
+    Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k;
+
+    return Temper;
+}
+
+/*********************************************************************
+ * @fn      ADC_BufferCmd
+ *
+ * @brief   Enables or disables the ADCx buffer.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= (1 << 26);
+    }
+    else
+    {
+        ADCx->CTLR1 &= ~(1 << 26);
+    }
+}
+
+/*********************************************************************
+ * @fn      Get_CalibrationValue
+ *
+ * @brief   Get ADCx Calibration Value.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *
+ * @return  CalibrationValue
+ */
+int16_t Get_CalibrationValue(ADC_TypeDef *ADCx)
+{
+    __IO uint8_t  i, j;
+    uint16_t      buf[10];
+    __IO uint16_t t;
+
+    for(i = 0; i < 10; i++)
+    {
+        ADC_ResetCalibration(ADCx);
+        while(ADC_GetResetCalibrationStatus(ADCx))
+            ;
+        ADC_StartCalibration(ADCx);
+        while(ADC_GetCalibrationStatus(ADCx))
+            ;
+        buf[i] = ADCx->RDATAR;
+    }
+
+    for(i = 0; i < 10; i++)
+    {
+        for(j = 0; j < 9; j++)
+        {
+            if(buf[j] > buf[j + 1])
+            {
+                t = buf[j];
+                buf[j] = buf[j + 1];
+                buf[j + 1] = t;
+            }
+        }
+    }
+
+    t = 0;
+    for(i = 0; i < 6; i++)
+    {
+        t += buf[i + 2];
+    }
+
+    t = (t / 6) + ((t % 6) / 3);
+
+    return (int16_t)(2048 - (int16_t)t);
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_bkp.c

@@ -0,0 +1,242 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_bkp.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the BKP firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_rcc.h"
+
+/* BKP registers bit mask */
+
+/* OCTLR register bit mask */
+#define OCTLR_CAL_MASK    ((uint16_t)0xFF80)
+#define OCTLR_MASK        ((uint16_t)0xFC7F)
+
+/*********************************************************************
+ * @fn      BKP_DeInit
+ *
+ * @brief   Deinitializes the BKP peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinLevelConfig
+ *
+ * @brief   Configures the Tamper Pin active level.
+ *
+ * @param   BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ *            BKP_TamperPinLevel_High - Tamper pin active on high level.
+ *            BKP_TamperPinLevel_Low - Tamper pin active on low level.
+ *
+ * @return  none
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+    if(BKP_TamperPinLevel)
+    {
+        BKP->TPCTLR |= (1 << 1);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 1);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinCmd
+ *
+ * @brief   Enables or disables the Tamper Pin activation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCTLR |= (1 << 0);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ITConfig
+ *
+ * @brief   Enables or disables the Tamper Pin Interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCSR |= (1 << 2);
+    }
+    else
+    {
+        BKP->TPCSR &= ~(1 << 2);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_RTCOutputConfig
+ *
+ * @brief   Select the RTC output source to output on the Tamper pin.
+ *
+ * @param   BKP_RTCOutputSource - specifies the RTC output source.
+ *            BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
+ *            BKP_RTCOutputSource_CalibClock - output the RTC clock with
+ *        frequency divided by 64 on the Tamper pin.
+ *            BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
+ *        on the Tamper pin.
+ *            BKP_RTCOutputSource_Second - output the RTC Second pulse
+ *        signal on the Tamper pin.
+ *
+ * @return  none
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_MASK;
+    tmpreg |= BKP_RTCOutputSource;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_SetRTCCalibrationValue
+ *
+ * @brief   Sets RTC Clock Calibration value.
+ *
+ * @param   CalibrationValue - specifies the RTC Clock Calibration value.
+ *            This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_CAL_MASK;
+    tmpreg |= CalibrationValue;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_WriteBackupRegister
+ *
+ * @brief   Writes user data to the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *          Data - data to write.
+ *
+ * @return  none
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      BKP_ReadBackupRegister
+ *
+ * @brief   Reads data from the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *            This parameter can be BKP_DRx where x=[1, 42].
+ *
+ * @return  none
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      BKP_GetFlagStatus
+ *
+ * @brief   Checks whether the Tamper Pin Event flag is set or not.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+    if(BKP->TPCSR & (1 << 8))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearFlag
+ *
+ * @brief   Clears Tamper Pin Event pending flag.
+ *
+ * @return  none
+ */
+void BKP_ClearFlag(void)
+{
+    BKP->TPCSR |= BKP_CTE;
+}
+
+/*********************************************************************
+ * @fn      BKP_GetITStatus
+ *
+ * @brief   Checks whether the Tamper Pin Interrupt has occurred or not.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus BKP_GetITStatus(void)
+{
+    if(BKP->TPCSR & (1 << 9))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearITPendingBit
+ *
+ * @brief   Clears Tamper Pin Interrupt pending bit.
+ *
+ * @return  none
+ */
+void BKP_ClearITPendingBit(void)
+{
+    BKP->TPCSR |= BKP_CTI;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_can.c

@@ -0,0 +1,1207 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_can.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the CAN firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_can.h"
+#include "ch32v30x_rcc.h"
+
+/* CAN CTLR Register bits */
+#define CTLR_DBF            ((uint32_t)0x00010000)
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ         ((uint32_t)0x00000001)
+
+/* CAN FCTLR Register bits */
+#define FCTLR_FINIT         ((uint32_t)0x00000001)
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT        ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT        ((uint32_t)0x0000FFFF)
+
+/* Flags in TSTATR register */
+#define CAN_FLAGS_TSTATR    ((uint32_t)0x08000000)
+/* Flags in RFIFO1 register */
+#define CAN_FLAGS_RFIFO1    ((uint32_t)0x04000000)
+/* Flags in RFIFO0 register */
+#define CAN_FLAGS_RFIFO0    ((uint32_t)0x02000000)
+/* Flags in STATR register */
+#define CAN_FLAGS_STATR     ((uint32_t)0x01000000)
+/* Flags in ERRSR register */
+#define CAN_FLAGS_ERRSR     ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0     ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1     ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2     ((uint8_t)0x02)
+
+#define CAN_MODE_MASK       ((uint32_t)0x00000003)
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/*********************************************************************
+ * @fn      CAN_DeInit
+ *
+ * @brief   Deinitializes the CAN peripheral registers to their default reset
+ *        values.
+ *
+ * @param   CANx - where x can be 1 or 2 to select the CAN peripheral.
+ *
+ * @return  none
+ */
+void CAN_DeInit(CAN_TypeDef *CANx)
+{
+    if(CANx == CAN1)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+    }
+    else
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_Init
+ *
+ * @brief   Initializes the CAN peripheral according to the specified
+ *        parameters in the CAN_InitStruct.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_InitStruct - pointer to a CAN_InitTypeDef structure that
+ *        contains the configuration information for the CAN peripheral.
+ *
+ * @return  InitStatus - CAN InitStatus state.
+ *             CAN_InitStatus_Failed.
+ *             CAN_InitStatus_Success.
+ */
+uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct)
+{
+    uint8_t  InitStatus = CAN_InitStatus_Failed;
+    uint32_t wait_ack = 0x00000000;
+
+    CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP);
+    CANx->CTLR |= CAN_CTLR_INRQ;
+
+    while(((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT))
+    {
+        wait_ack++;
+    }
+
+    if((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK)
+    {
+        InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+        if(CAN_InitStruct->CAN_TTCM == ENABLE)
+        {
+            CANx->CTLR |= CAN_CTLR_TTCM;
+        }
+        else
+        {
+            CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM;
+        }
+
+        if(CAN_InitStruct->CAN_ABOM == ENABLE)
+        {
+            CANx->CTLR |= CAN_CTLR_ABOM;
+        }
+        else
+        {
+            CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM;
+        }
+
+        if(CAN_InitStruct->CAN_AWUM == ENABLE)
+        {
+            CANx->CTLR |= CAN_CTLR_AWUM;
+        }
+        else
+        {
+            CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM;
+        }
+
+        if(CAN_InitStruct->CAN_NART == ENABLE)
+        {
+            CANx->CTLR |= CAN_CTLR_NART;
+        }
+        else
+        {
+            CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART;
+        }
+
+        if(CAN_InitStruct->CAN_RFLM == ENABLE)
+        {
+            CANx->CTLR |= CAN_CTLR_RFLM;
+        }
+        else
+        {
+            CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM;
+        }
+
+        if(CAN_InitStruct->CAN_TXFP == ENABLE)
+        {
+            CANx->CTLR |= CAN_CTLR_TXFP;
+        }
+        else
+        {
+            CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP;
+        }
+
+        CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) |
+                      ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |
+                      ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) |
+                      ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |
+                      ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+        CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ;
+        wait_ack = 0;
+
+        while(((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT))
+        {
+            wait_ack++;
+        }
+
+        if((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK)
+        {
+            InitStatus = CAN_InitStatus_Failed;
+        }
+        else
+        {
+            InitStatus = CAN_InitStatus_Success;
+        }
+    }
+
+    return InitStatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_FilterInit
+ *
+ * @brief   Initializes the CAN peripheral according to the specified
+ *        parameters in the CAN_FilterInitStruct.
+ *
+ * @param   CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef
+ *        structure that contains the configuration information.
+ *
+ * @return  none
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct)
+{
+    uint32_t filter_number_bit_pos = 0;
+
+    filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+    CAN1->FCTLR |= FCTLR_FINIT;
+    CAN1->FWR &= ~(uint32_t)filter_number_bit_pos;
+
+    if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+    {
+        CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos;
+
+        CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+            ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+            (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+        CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+            ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+            (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+    }
+
+    if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+    {
+        CAN1->FSCFGR |= filter_number_bit_pos;
+
+        CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+            ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+            (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+        CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+            ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+            (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+    }
+
+    if(CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+    {
+        CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos;
+    }
+    else
+    {
+        CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos;
+    }
+
+    if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+    {
+        CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos;
+    }
+
+    if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+    {
+        CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos;
+    }
+
+    if(CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+    {
+        CAN1->FWR |= filter_number_bit_pos;
+    }
+
+    CAN1->FCTLR &= ~FCTLR_FINIT;
+}
+
+/*********************************************************************
+ * @fn      CAN_StructInit
+ *
+ * @brief   Fills each CAN_InitStruct member with its default value.
+ *
+ * @param   CAN_InitStruct - pointer to a CAN_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct)
+{
+    CAN_InitStruct->CAN_TTCM = DISABLE;
+    CAN_InitStruct->CAN_ABOM = DISABLE;
+    CAN_InitStruct->CAN_AWUM = DISABLE;
+    CAN_InitStruct->CAN_NART = DISABLE;
+    CAN_InitStruct->CAN_RFLM = DISABLE;
+    CAN_InitStruct->CAN_TXFP = DISABLE;
+    CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+    CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+    CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+    CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+    CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/*********************************************************************
+ * @fn      CAN_SlaveStartBank
+ *
+ * @brief   This function applies only to CH32 Connectivity line devices.
+ *
+ * @param   CAN_BankNumber - Select the start slave bank filter from 1..27.
+ *
+ * @return  none
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+    CAN1->FCTLR |= FCTLR_FINIT;
+    CAN1->FCTLR &= (uint32_t)0xFFFFC0F1;
+    CAN1->FCTLR |= (uint32_t)(CAN_BankNumber) << 8;
+    CAN1->FCTLR &= ~FCTLR_FINIT;
+}
+
+/*********************************************************************
+ * @fn      CAN_DBGFreeze
+ *
+ * @brief   Enables or disables the DBG Freeze for CAN.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        CANx->CTLR |= CTLR_DBF;
+    }
+    else
+    {
+        CANx->CTLR &= ~CTLR_DBF;
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_TTComModeCmd
+ *
+ * @brief   Enables or disabes the CAN Time TriggerOperation communication mode.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        CANx->CTLR |= CAN_CTLR_TTCM;
+
+        CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT);
+        CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT);
+        CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT);
+    }
+    else
+    {
+        CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM);
+
+        CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT);
+        CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT);
+        CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT);
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_Transmit
+ *
+ * @brief   Initiates the transmission of a message.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          TxMessage - pointer to a structure which contains CAN Id, CAN
+ *        DLC and CAN data.
+ *
+ * @return  transmit_mailbox - The number of the mailbox that is used for
+ *        transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage)
+{
+    uint8_t transmit_mailbox = 0;
+
+    if((CANx->TSTATR & CAN_TSTATR_TME0) == CAN_TSTATR_TME0)
+    {
+        transmit_mailbox = 0;
+    }
+    else if((CANx->TSTATR & CAN_TSTATR_TME1) == CAN_TSTATR_TME1)
+    {
+        transmit_mailbox = 1;
+    }
+    else if((CANx->TSTATR & CAN_TSTATR_TME2) == CAN_TSTATR_TME2)
+    {
+        transmit_mailbox = 2;
+    }
+    else
+    {
+        transmit_mailbox = CAN_TxStatus_NoMailBox;
+    }
+
+    if(transmit_mailbox != CAN_TxStatus_NoMailBox)
+    {
+        CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ;
+        if(TxMessage->IDE == CAN_Id_Standard)
+        {
+            CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) |
+                                                         TxMessage->RTR);
+        }
+        else
+        {
+            CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) |
+                                                         TxMessage->IDE |
+                                                         TxMessage->RTR);
+        }
+
+        TxMessage->DLC &= (uint8_t)0x0000000F;
+        CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0;
+        CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC;
+
+        CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) |
+                                                     ((uint32_t)TxMessage->Data[2] << 16) |
+                                                     ((uint32_t)TxMessage->Data[1] << 8) |
+                                                     ((uint32_t)TxMessage->Data[0]));
+        CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) |
+                                                     ((uint32_t)TxMessage->Data[6] << 16) |
+                                                     ((uint32_t)TxMessage->Data[5] << 8) |
+                                                     ((uint32_t)TxMessage->Data[4]));
+        CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ;
+    }
+
+    return transmit_mailbox;
+}
+
+/*********************************************************************
+ * @fn      CAN_TransmitStatus
+ *
+ * @brief   Checks the transmission of a message.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          TransmitMailbox - the number of the mailbox that is used for
+ *        transmission.
+ *
+ * @return  state -
+ *            CAN_TxStatus_Ok.
+ *            CAN_TxStatus_Failed.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox)
+{
+    uint32_t state = 0;
+
+    switch(TransmitMailbox)
+    {
+        case(CAN_TXMAILBOX_0):
+            state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0);
+            break;
+
+        case(CAN_TXMAILBOX_1):
+            state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1);
+            break;
+
+        case(CAN_TXMAILBOX_2):
+            state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2);
+            break;
+
+        default:
+            state = CAN_TxStatus_Failed;
+            break;
+    }
+
+    switch(state)
+    {
+        case(0x0):
+            state = CAN_TxStatus_Pending;
+            break;
+
+        case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0):
+            state = CAN_TxStatus_Failed;
+            break;
+
+        case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1):
+            state = CAN_TxStatus_Failed;
+            break;
+
+        case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2):
+            state = CAN_TxStatus_Failed;
+            break;
+
+        case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0):
+            state = CAN_TxStatus_Ok;
+            break;
+
+        case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1):
+            state = CAN_TxStatus_Ok;
+            break;
+
+        case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2):
+            state = CAN_TxStatus_Ok;
+            break;
+
+        default:
+            state = CAN_TxStatus_Failed;
+            break;
+    }
+
+    return (uint8_t)state;
+}
+
+/*********************************************************************
+ * @fn      CAN_CancelTransmit
+ *
+ * @brief   Cancels a transmit request.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          Mailbox -  Mailbox number.
+ *            CAN_TXMAILBOX_0.
+ *            CAN_TXMAILBOX_1.
+ *            CAN_TXMAILBOX_2.
+ *
+ * @return  none
+ */
+void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox)
+{
+    switch(Mailbox)
+    {
+        case(CAN_TXMAILBOX_0):
+            CANx->TSTATR |= CAN_TSTATR_ABRQ0;
+            break;
+
+        case(CAN_TXMAILBOX_1):
+            CANx->TSTATR |= CAN_TSTATR_ABRQ1;
+            break;
+
+        case(CAN_TXMAILBOX_2):
+            CANx->TSTATR |= CAN_TSTATR_ABRQ2;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_Receive
+ *
+ * @brief   Receives a message.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          FIFONumber - Receive FIFO number.
+ *            CAN_FIFO0.
+ *            CAN_FIFO1.
+ *          RxMessage -  pointer to a structure receive message which contains
+ *        CAN Id, CAN DLC, CAN datas and FMI number.
+ *
+ * @return  none
+ */
+void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage)
+{
+    RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR;
+
+    if(RxMessage->IDE == CAN_Id_Standard)
+    {
+        RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21);
+    }
+    else
+    {
+        RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3);
+    }
+
+    RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR;
+    RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR;
+    RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8);
+    RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR;
+    RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8);
+    RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16);
+    RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24);
+    RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR;
+    RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8);
+    RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16);
+    RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24);
+
+    if(FIFONumber == CAN_FIFO0)
+    {
+        CANx->RFIFO0 |= CAN_RFIFO0_RFOM0;
+    }
+    else
+    {
+        CANx->RFIFO1 |= CAN_RFIFO1_RFOM1;
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_FIFORelease
+ *
+ * @brief   Releases the specified FIFO.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          FIFONumber - Receive FIFO number.
+ *            CAN_FIFO0.
+ *            CAN_FIFO1.
+ *
+ * @return  none
+ */
+void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber)
+{
+    if(FIFONumber == CAN_FIFO0)
+    {
+        CANx->RFIFO0 |= CAN_RFIFO0_RFOM0;
+    }
+    else
+    {
+        CANx->RFIFO1 |= CAN_RFIFO1_RFOM1;
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_MessagePending
+ *
+ * @brief   Returns the number of pending messages.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          FIFONumber - Receive FIFO number.
+ *            CAN_FIFO0.
+ *            CAN_FIFO1.
+ *
+ * @return  message_pending: which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber)
+{
+    uint8_t message_pending = 0;
+
+    if(FIFONumber == CAN_FIFO0)
+    {
+        message_pending = (uint8_t)(CANx->RFIFO0 & (uint32_t)0x03);
+    }
+    else if(FIFONumber == CAN_FIFO1)
+    {
+        message_pending = (uint8_t)(CANx->RFIFO1 & (uint32_t)0x03);
+    }
+    else
+    {
+        message_pending = 0;
+    }
+
+    return message_pending;
+}
+
+/*********************************************************************
+ * @fn      CAN_OperatingModeRequest
+ *
+ * @brief   Select the CAN Operation mode.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_OperatingMode - CAN Operating Mode.
+ *            CAN_OperatingMode_Initialization.
+ *            CAN_OperatingMode_Normal.
+ *            CAN_OperatingMode_Sleep.
+ *
+ * @return  status -
+ *          CAN_ModeStatus_Failed - CAN failed entering the specific mode.
+ *          CAN_ModeStatus_Success - CAN Succeed entering the specific mode.
+ */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode)
+{
+    uint8_t  status = CAN_ModeStatus_Failed;
+    uint32_t timeout = INAK_TIMEOUT;
+
+    if(CAN_OperatingMode == CAN_OperatingMode_Initialization)
+    {
+        CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ);
+
+        while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0))
+        {
+            timeout--;
+        }
+        if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK)
+        {
+            status = CAN_ModeStatus_Failed;
+        }
+        else
+        {
+            status = CAN_ModeStatus_Success;
+        }
+    }
+    else if(CAN_OperatingMode == CAN_OperatingMode_Normal)
+    {
+        CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP | CAN_CTLR_INRQ));
+
+        while(((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout != 0))
+        {
+            timeout--;
+        }
+        if((CANx->STATR & CAN_MODE_MASK) != 0)
+        {
+            status = CAN_ModeStatus_Failed;
+        }
+        else
+        {
+            status = CAN_ModeStatus_Success;
+        }
+    }
+    else if(CAN_OperatingMode == CAN_OperatingMode_Sleep)
+    {
+        CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP);
+
+        while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout != 0))
+        {
+            timeout--;
+        }
+        if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK)
+        {
+            status = CAN_ModeStatus_Failed;
+        }
+        else
+        {
+            status = CAN_ModeStatus_Success;
+        }
+    }
+    else
+    {
+        status = CAN_ModeStatus_Failed;
+    }
+
+    return (uint8_t)status;
+}
+
+/*********************************************************************
+ * @fn      CAN_Sleep
+ *
+ * @brief   Enters the low power mode.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  sleepstatus -
+ *            CAN_Sleep_Ok.
+ *            CAN_Sleep_Failed.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef *CANx)
+{
+    uint8_t sleepstatus = CAN_Sleep_Failed;
+
+    CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP);
+
+    if((CANx->STATR & (CAN_STATR_SLAK | CAN_STATR_INAK)) == CAN_STATR_SLAK)
+    {
+        sleepstatus = CAN_Sleep_Ok;
+    }
+
+    return (uint8_t)sleepstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_WakeUp
+ *
+ * @brief   Wakes the CAN up.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  wakeupstatus -
+ *            CAN_WakeUp_Ok.
+ *            CAN_WakeUp_Failed.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef *CANx)
+{
+    uint32_t wait_slak = SLAK_TIMEOUT;
+    uint8_t  wakeupstatus = CAN_WakeUp_Failed;
+
+    CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP;
+
+    while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK) && (wait_slak != 0x00))
+    {
+        wait_slak--;
+    }
+    if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK)
+    {
+        wakeupstatus = CAN_WakeUp_Ok;
+    }
+
+    return (uint8_t)wakeupstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_GetLastErrorCode
+ *
+ * @brief   Returns the CANx's last error code (LEC).
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  errorcode - specifies the Error code.
+ *            CAN_ErrorCode_NoErr - No Error.
+ *            CAN_ErrorCode_StuffErr - Stuff Error.
+ *            CAN_ErrorCode_FormErr - Form Error.
+ *            CAN_ErrorCode_ACKErr - Acknowledgment Error.
+ *            CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error.
+ *            CAN_ErrorCode_BitDominantErr - Bit Dominant Error.
+ *            CAN_ErrorCode_CRCErr - CRC Error.
+ *            CAN_ErrorCode_SoftwareSetErr - Software Set Error.
+ */
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx)
+{
+    uint8_t errorcode = 0;
+
+    errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC);
+
+    return errorcode;
+}
+
+/*********************************************************************
+ * @fn      CAN_GetReceiveErrorCounter
+ *
+ * @brief   Returns the CANx Receive Error Counter (REC).
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  counter - CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx)
+{
+    uint8_t counter = 0;
+
+    counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC) >> 24);
+
+    return counter;
+}
+
+/*********************************************************************
+ * @fn      CAN_GetLSBTransmitErrorCounter
+ *
+ * @brief   Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *
+ * @return  counter - LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx)
+{
+    uint8_t counter = 0;
+
+    counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC) >> 16);
+
+    return counter;
+}
+
+/*********************************************************************
+ * @fn      CAN_ITConfig
+ *
+ * @brief   Enables or disables the specified CANx interrupts.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_IT - specifies the CAN interrupt sources to be enabled or disabled.
+ *            CAN_IT_TME.
+ *            CAN_IT_FMP0.
+ *            CAN_IT_FF0.
+ *            CAN_IT_FOV0.
+ *            CAN_IT_FMP1.
+ *            CAN_IT_FF1.
+ *            CAN_IT_FOV1.
+ *            CAN_IT_EWG.
+ *            CAN_IT_EPV.
+ *            CAN_IT_LEC.
+ *            CAN_IT_ERR.
+ *            CAN_IT_WKU.
+ *            CAN_IT_SLK.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  counter - LSB of the 9-bit CAN Transmit Error Counter.
+ */
+void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        CANx->INTENR |= CAN_IT;
+    }
+    else
+    {
+        CANx->INTENR &= ~CAN_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_GetFlagStatus
+ *
+ * @brief   Checks whether the specified CAN flag is set or not.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_FLAG - specifies the flag to check.
+ *            CAN_FLAG_EWG.
+ *            CAN_FLAG_EPV.
+ *            CAN_FLAG_BOF.
+ *            CAN_FLAG_RQCP0.
+ *            CAN_FLAG_RQCP1.
+ *            CAN_FLAG_RQCP2.
+ *            CAN_FLAG_FMP1.
+ *            CAN_FLAG_FF1.
+ *            CAN_FLAG_FOV1.
+ *            CAN_FLAG_FMP0.
+ *            CAN_FLAG_FF0.
+ *            CAN_FLAG_FOV0.
+ *            CAN_FLAG_WKU.
+ *            CAN_FLAG_SLAK.
+ *            CAN_FLAG_LEC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET)
+    {
+        if((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET)
+    {
+        if((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET)
+    {
+        if((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET)
+    {
+        if((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_ClearFlag
+ *
+ * @brief   Clears the CAN's pending flags.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_FLAG - specifies the flag to clear.
+ *            CAN_FLAG_RQCP0.
+ *            CAN_FLAG_RQCP1.
+ *            CAN_FLAG_RQCP2.
+ *            CAN_FLAG_FF1.
+ *            CAN_FLAG_FOV1.
+ *            CAN_FLAG_FF0.
+ *            CAN_FLAG_FOV0.
+ *            CAN_FLAG_WKU.
+ *            CAN_FLAG_SLAK.
+ *            CAN_FLAG_LEC.
+ *
+ * @return  none
+ */
+void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG)
+{
+    uint32_t flagtmp = 0;
+
+    if(CAN_FLAG == CAN_FLAG_LEC)
+    {
+        CANx->ERRSR = (uint32_t)RESET;
+    }
+    else
+    {
+        flagtmp = CAN_FLAG & 0x000FFFFF;
+
+        if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET)
+        {
+            CANx->RFIFO0 = (uint32_t)(flagtmp);
+        }
+        else if((CAN_FLAG & CAN_FLAGS_RFIFO1) != (uint32_t)RESET)
+        {
+            CANx->RFIFO1 = (uint32_t)(flagtmp);
+        }
+        else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET)
+        {
+            CANx->TSTATR = (uint32_t)(flagtmp);
+        }
+        else
+        {
+            CANx->STATR = (uint32_t)(flagtmp);
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      CAN_GetITStatus
+ *
+ * @brief   Checks whether the specified CANx interrupt has occurred or not.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_IT -  specifies the CAN interrupt source to check.
+ *            CAN_IT_TME.
+ *            CAN_IT_FMP0.
+ *            CAN_IT_FF0.
+ *            CAN_IT_FOV0.
+ *            CAN_IT_FMP1.
+ *            CAN_IT_FF1.
+ *            CAN_IT_FOV1.
+ *            CAN_IT_WKU.
+ *            CAN_IT_SLK.
+ *            CAN_IT_EWG.
+ *            CAN_IT_EPV.
+ *            CAN_IT_BOF.
+ *            CAN_IT_LEC.
+ *            CAN_IT_ERR.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT)
+{
+    ITStatus itstatus = RESET;
+
+    if((CANx->INTENR & CAN_IT) != RESET)
+    {
+        switch(CAN_IT)
+        {
+            case CAN_IT_TME:
+                itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2);
+                break;
+
+            case CAN_IT_FMP0:
+                itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0);
+                break;
+
+            case CAN_IT_FF0:
+                itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0);
+                break;
+
+            case CAN_IT_FOV0:
+                itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0);
+                break;
+
+            case CAN_IT_FMP1:
+                itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1);
+                break;
+
+            case CAN_IT_FF1:
+                itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1);
+                break;
+
+            case CAN_IT_FOV1:
+                itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1);
+                break;
+
+            case CAN_IT_WKU:
+                itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI);
+                break;
+
+            case CAN_IT_SLK:
+                itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI);
+                break;
+
+            case CAN_IT_EWG:
+                itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF);
+                break;
+
+            case CAN_IT_EPV:
+                itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF);
+                break;
+
+            case CAN_IT_BOF:
+                itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF);
+                break;
+
+            case CAN_IT_LEC:
+                itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC);
+                break;
+
+            case CAN_IT_ERR:
+                itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI);
+                break;
+
+            default:
+                itstatus = RESET;
+                break;
+        }
+    }
+    else
+    {
+        itstatus = RESET;
+    }
+
+    return itstatus;
+}
+
+/*********************************************************************
+ * @fn      CAN_ClearITPendingBit
+ *
+ * @brief   Clears the CANx's interrupt pending bits.
+ *
+ * @param   CANx - where x can be 1 to select the CAN peripheral.
+ *          CAN_IT - specifies the interrupt pending bit to clear.
+ *            CAN_IT_TME.
+ *            CAN_IT_FF0.
+ *            CAN_IT_FOV0.
+ *            CAN_IT_FF1.
+ *            CAN_IT_FOV1.
+ *            CAN_IT_WKU.
+ *            CAN_IT_SLK.
+ *            CAN_IT_EWG.
+ *            CAN_IT_EPV.
+ *            CAN_IT_BOF.
+ *            CAN_IT_LEC.
+ *            CAN_IT_ERR.
+ *
+ * @return  none
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT)
+{
+    switch(CAN_IT)
+    {
+        case CAN_IT_TME:
+            CANx->TSTATR = CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2;
+            break;
+
+        case CAN_IT_FF0:
+            CANx->RFIFO0 = CAN_RFIFO0_FULL0;
+            break;
+
+        case CAN_IT_FOV0:
+            CANx->RFIFO0 = CAN_RFIFO0_FOVR0;
+            break;
+
+        case CAN_IT_FF1:
+            CANx->RFIFO1 = CAN_RFIFO1_FULL1;
+            break;
+
+        case CAN_IT_FOV1:
+            CANx->RFIFO1 = CAN_RFIFO1_FOVR1;
+            break;
+
+        case CAN_IT_WKU:
+            CANx->STATR = CAN_STATR_WKUI;
+            break;
+
+        case CAN_IT_SLK:
+            CANx->STATR = CAN_STATR_SLAKI;
+            break;
+
+        case CAN_IT_EWG:
+            CANx->STATR = CAN_STATR_ERRI;
+            break;
+
+        case CAN_IT_EPV:
+            CANx->STATR = CAN_STATR_ERRI;
+            break;
+
+        case CAN_IT_BOF:
+            CANx->STATR = CAN_STATR_ERRI;
+            break;
+
+        case CAN_IT_LEC:
+            CANx->ERRSR = RESET;
+            CANx->STATR = CAN_STATR_ERRI;
+            break;
+
+        case CAN_IT_ERR:
+            CANx->ERRSR = RESET;
+            CANx->STATR = CAN_STATR_ERRI;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      CheckITStatus
+ *
+ * @brief   Checks whether the CAN interrupt has occurred or not.
+ *
+ * @param   CAN_Reg - specifies the CAN interrupt register to check
+ *          It_Bit - specifies the interrupt source bit to check.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+    ITStatus pendingbitstatus = RESET;
+
+    if((CAN_Reg & It_Bit) != (uint32_t)RESET)
+    {
+        pendingbitstatus = SET;
+    }
+    else
+    {
+        pendingbitstatus = RESET;
+    }
+
+    return pendingbitstatus;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_crc.c

@@ -0,0 +1,98 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_crc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the CRC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_crc.h"
+
+/*********************************************************************
+ * @fn      CRC_ResetDR
+ *
+ * @brief   Resets the CRC Data register (DR).
+ *
+ * @return  none
+ */
+void CRC_ResetDR(void)
+{
+    CRC->CTLR = CRC_CTLR_RESET;
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given data word(32-bit).
+ *
+ * @param   Data - data word(32-bit) to compute its CRC.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+    CRC->DATAR = Data;
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcBlockCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ *
+ * @param   pBuffer - pointer to the buffer containing the data to be computed.
+ *          BufferLength - length of the buffer to be computed.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    for(index = 0; index < BufferLength; index++)
+    {
+        CRC->DATAR = pBuffer[index];
+    }
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_GetCRC
+ *
+ * @brief   Returns the current CRC value.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_GetCRC(void)
+{
+    return (CRC->IDATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_SetIDRegister
+ *
+ * @brief   Stores a 8-bit data in the Independent Data(ID) register.
+ *
+ * @param   IDValue - 8-bit value to be stored in the ID register.
+ *
+ * @return  none
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+    CRC->IDATAR = IDValue;
+}
+
+/*********************************************************************
+ * @fn      CRC_GetIDRegister
+ *
+ * @brief   Returns the 8-bit data stored in the Independent Data(ID) register.
+ *
+ * @return  8-bit value of the ID register.
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+    return (CRC->IDATAR);
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_dac.c

@@ -0,0 +1,302 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dac.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DAC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+****************************************************************************************/
+#include "ch32v30x_dac.h"
+#include "ch32v30x_rcc.h"
+
+/* CTLR register Mask */
+#define CTLR_CLEAR_MASK    ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTR masks */
+#define DUAL_SWTR_SET      ((uint32_t)0x00000003)
+#define DUAL_SWTR_RESET    ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET     ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET     ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET     ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET         ((uint32_t)0x0000002C)
+
+/*********************************************************************
+ * @fn      DAC_DeInit
+ *
+ * @brief   Deinitializes the DAC peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void DAC_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      DAC_Init
+ *
+ * @brief   Initializes the DAC peripheral according to the specified parameters in
+ *        the DAC_InitStruct.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          DAC_InitStruct - pointer to a DAC_InitTypeDef structure.
+ *
+ * @return  none
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+    tmpreg1 = DAC->CTLR;
+    tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel);
+    tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+               DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+    tmpreg1 |= tmpreg2 << DAC_Channel;
+    DAC->CTLR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      DAC_StructInit
+ *
+ * @brief   Fills each DAC_InitStruct member with its default value.
+ *
+ * @param   DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized.
+ *
+ * @return  none
+ */
+void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
+{
+    DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+    DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+    DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+    DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/*********************************************************************
+ * @fn      DAC_Cmd
+ *
+ * @brief   Enables or disables the specified DAC channel.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTLR |= (DAC_EN1 << DAC_Channel);
+    }
+    else
+    {
+        DAC->CTLR &= ~(DAC_EN1 << DAC_Channel);
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_DMACmd
+ *
+ * @brief   Enables or disables the specified DAC channel DMA request.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel);
+    }
+    else
+    {
+        DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel);
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_SoftwareTriggerCmd
+ *
+ * @brief   Enables or disables the selected DAC channel software trigger.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4);
+    }
+    else
+    {
+        DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4));
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_DualSoftwareTriggerCmd
+ *
+ * @brief   Enables or disables the two DAC channel software trigger.
+ *
+ * @param   NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->SWTR |= DUAL_SWTR_SET;
+    }
+    else
+    {
+        DAC->SWTR &= DUAL_SWTR_RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_WaveGenerationCmd
+ *
+ * @brief   Enables or disables the selected DAC channel wave generation.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *          DAC_Wave - Specifies the wave type to enable or disable.
+ *            DAC_Wave_Noise - noise wave generation
+ *            DAC_Wave_Triangle - triangle wave generation
+ *          NewState - new state of the DAC channel(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DAC->CTLR |= DAC_Wave << DAC_Channel;
+    }
+    else
+    {
+        DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
+    }
+}
+
+/*********************************************************************
+ * @fn      DAC_SetChannel1Data
+ *
+ * @brief   Set the specified data holding register value for DAC channel1.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *          Data - Data to be loaded in the selected data holding register.
+ *
+ * @return  none
+ */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DHR12R1_OFFSET + DAC_Align;
+
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      DAC_SetChannel2Data
+ *
+ * @brief   Set the specified data holding register value for DAC channel2.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *            Data - Data to be loaded in the selected data holding register.
+ *
+ * @return  none
+ */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DHR12R2_OFFSET + DAC_Align;
+
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      DAC_SetDualChannelData
+ *
+ * @brief   Set the specified data holding register value for two DAC.
+ *
+ * @param   DAC_Align - Specifies the data alignment for DAC channel1.
+ *            DAC_Align_8b_R - 8bit right data alignment selected
+ *            DAC_Align_12b_L - 12bit left data alignment selected
+ *            DAC_Align_12b_R - 12bit right data alignment selected
+ *            Data - Data to be loaded in the selected data holding register.
+ *          Data1 - Data for DAC Channel1.
+ *          Data2 - Data for DAC Channel2
+ *
+ * @return  none
+ */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+    uint32_t data = 0, tmp = 0;
+
+    if(DAC_Align == DAC_Align_8b_R)
+    {
+        data = ((uint32_t)Data2 << 8) | Data1;
+    }
+    else
+    {
+        data = ((uint32_t)Data2 << 16) | Data1;
+    }
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DHR12RD_OFFSET + DAC_Align;
+
+    *(__IO uint32_t *)tmp = data;
+}
+
+/*********************************************************************
+ * @fn      DAC_GetDataOutputValue
+ *
+ * @brief   Returns the last data output value of the selected DAC channel.
+ *
+ * @param   DAC_Channel - the selected DAC channel.
+ *            DAC_Channel_1 - DAC Channel1 selected
+ *            DAC_Channel_2 - DAC Channel2 selected
+ *
+ * @return  none
+ */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)DAC_BASE;
+    tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+    return (uint16_t)(*(__IO uint32_t *)tmp);
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_dbgmcu.c

@@ -0,0 +1,36 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dbgmcu.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DBGMCU firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+****************************************************************************************/
+#include "ch32v30x_dbgmcu.h"
+
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/*********************************************************************
+ * @fn      DBGMCU_GetREVID
+ *
+ * @brief   Returns the device revision identifier.
+ *
+ * @return  Revision identifier.
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+    return ((*(uint32_t *)0x1FFFF704) >> 16);
+}
+
+/*********************************************************************
+ * @fn      DBGMCU_GetDEVID
+ *
+ * @brief   Returns the device identifier.
+ *
+ * @return  Device identifier.
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+    return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_dma.c

@@ -0,0 +1,690 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dma.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DMA firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_dma.h"
+#include "ch32v30x_rcc.h"
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask     ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA1_Channel2_IT_Mask     ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA1_Channel3_IT_Mask     ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA1_Channel4_IT_Mask     ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA1_Channel5_IT_Mask     ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA1_Channel6_IT_Mask     ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA1_Channel7_IT_Mask     ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask     ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA2_Channel2_IT_Mask     ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA2_Channel3_IT_Mask     ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA2_Channel4_IT_Mask     ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA2_Channel5_IT_Mask     ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA2_Channel6_IT_Mask     ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA2_Channel7_IT_Mask     ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+#define DMA2_Channel8_IT_Mask     ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
+#define DMA2_Channel9_IT_Mask     ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9))
+#define DMA2_Channel10_IT_Mask    ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10))
+#define DMA2_Channel11_IT_Mask    ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                 ((uint32_t)0x10000000)
+#define DMA2_EXTEN_FLAG_Mask      ((uint32_t)0x20000000)
+
+/* DMA registers Masks */
+#define CFGR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
+
+/*********************************************************************
+ * @fn      DMA_DeInit
+ *
+ * @brief   Deinitializes the DMAy Channelx registers to their default
+ *        reset values.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    DMAy_Channelx->CFGR = 0;
+    DMAy_Channelx->CNTR = 0;
+    DMAy_Channelx->PADDR = 0;
+    DMAy_Channelx->MADDR = 0;
+    if(DMAy_Channelx == DMA1_Channel1)
+    {
+        DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel2)
+    {
+        DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel3)
+    {
+        DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel4)
+    {
+        DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel5)
+    {
+        DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel6)
+    {
+        DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel7)
+    {
+        DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel1)
+    {
+        DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel2)
+    {
+        DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel3)
+    {
+        DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel4)
+    {
+        DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel5)
+    {
+        DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel6)
+    {
+        DMA2->INTFCR |= DMA2_Channel6_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel7)
+    {
+        DMA2->INTFCR |= DMA2_Channel7_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel8)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel9)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel10)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel11)
+    {
+        DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_Init
+ *
+ * @brief   Initializes the DMAy Channelx according to the specified
+ *        parameters in the DMA_InitStruct.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = DMAy_Channelx->CFGR;
+    tmpreg &= CFGR_CLEAR_Mask;
+    tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+              DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+              DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+              DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+    DMAy_Channelx->CFGR = tmpreg;
+    DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
+    DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+    DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*********************************************************************
+ * @fn      DMA_StructInit
+ *
+ * @brief   Fills each DMA_InitStruct member with its default value.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
+{
+    DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+    DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+    DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+    DMA_InitStruct->DMA_BufferSize = 0;
+    DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+    DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+    DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/*********************************************************************
+ * @fn      DMA_Cmd
+ *
+ * @brief   Enables or disables the specified DMAy Channelx.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_ITConfig
+ *
+ * @brief   Enables or disables the specified DMAy Channelx interrupts.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DMA_IT - specifies the DMA interrupts sources to be enabled
+ *        or disabled.
+ *           DMA_IT_TC - Transfer complete interrupt mask
+ *           DMA_IT_HT - Half transfer interrupt mask
+ *           DMA_IT_TE -  Transfer error interrupt mask
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_IT;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= ~DMA_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_SetCurrDataCounter
+ *
+ * @brief   Sets the number of data units in the current DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *          DataNumber - The number of data units in the current DMAy Channelx
+ *        transfer.
+ *
+ * @return  none
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
+{
+    DMAy_Channelx->CNTR = DataNumber;
+}
+
+/*********************************************************************
+ * @fn      DMA_GetCurrDataCounter
+ *
+ * @brief   Returns the number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
+ *
+ * @return  DataNumber - The number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    return ((uint16_t)(DMAy_Channelx->CNTR));
+}
+
+/*********************************************************************
+ * @fn      DMA_GetFlagStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx flag is set or not.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t   tmpreg = 0;
+
+    if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        tmpreg = DMA2_EXTEN->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearFlag
+ *
+ * @brief   Clears the DMAy Channelx's pending flags.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+    if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
+    {
+        DMA2->INTFCR = DMAy_FLAG;
+    }
+    else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        DMA2_EXTEN->INTFCR = DMAy_FLAG;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_FLAG;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_GetITStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx interrupt has
+ *        occurred or not.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_IT_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_IT_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_IT_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_IT_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_IT_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_IT_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+
+    if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        tmpreg = DMA2_EXTEN->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if((tmpreg & DMAy_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearITPendingBit
+ *
+ * @brief   Clears the DMAy Channelx's interrupt pending bits.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *            DMA2_IT_GL6 - DMA2 Channel6 global flag.
+ *            DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
+ *            DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
+ *            DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
+ *            DMA2_IT_GL7 - DMA2 Channel7 global flag.
+ *            DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
+ *            DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
+ *            DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
+ *            DMA2_IT_GL8 - DMA2 Channel8 global flag.
+ *            DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
+ *            DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
+ *            DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
+ *            DMA2_IT_GL9 - DMA2 Channel9 global flag.
+ *            DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
+ *            DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
+ *            DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
+ *            DMA2_IT_GL10 - DMA2 Channel10 global flag.
+ *            DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
+ *            DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
+ *            DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
+ *            DMA2_IT_GL11 - DMA2 Channel11 global flag.
+ *            DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
+ *            DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
+ *            DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+    if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
+    {
+        DMA2->INTFCR = DMAy_IT;
+    }
+    else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
+    {
+        DMA2_EXTEN->INTFCR = DMAy_IT;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_IT;
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_dvp.c

@@ -0,0 +1,133 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_dvp.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the DVP firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_dvp.h"
+
+/*********************************************************************
+ * @fn      DVP_INTCfg
+ *
+ * @brief   DVP interrupt configuration
+ *
+ * @param   s - interrupt enable
+ *             ENABLE
+ *             DISABLE
+ *          i - interrupt type
+ *             RB_DVP_IE_STP_FRM
+ *             RB_DVP_IE_FIFO_OV
+ *             RB_DVP_IE_FRM_DONE
+ *             RB_DVP_IE_ROW_DONE
+ *             RB_DVP_IE_STR_FRM
+ *
+ * @return  none
+ */
+void DVP_INTCfg(uint8_t s, uint8_t i)
+{
+    if(s)
+    {
+        DVP->IER |= i;
+    }
+    else
+    {
+        DVP->IER &= ~i;
+    }
+}
+
+/*********************************************************************
+ * @fn      DVP_Mode
+ *
+ * @brief   DVP mode
+ *
+ * @param   s - data bit width
+ *             RB_DVP_D8_MOD
+ *             RB_DVP_D10_MOD
+ *             RB_DVP_D12_MOD
+ *          i - interrupt type
+ *             Video_Mode
+ *             JPEG_Mode
+ *
+ * @return  none
+ */
+void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i)
+{
+    DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD;
+
+    if(s)
+    {
+        DVP->CR0 |= s;
+    }
+    else
+    {
+        DVP->CR0 &= ~(3 << 4);
+    }
+
+    if(i)
+    {
+        DVP->CR0 |= RB_DVP_JPEG;
+    }
+    else
+    {
+        DVP->CR0 &= ~RB_DVP_JPEG;
+    }
+}
+
+/*********************************************************************
+ * @fn      DVP_Cfg
+ *
+ * @brief   DVP configuration
+ *
+ * @param   s - DMA enable control
+ *            DVP_DMA_Enable
+ *            DVP_DMA_Disable
+ *          i - DVP all clear
+ *            DVP_FLAG_FIFO_RESET_Enable
+ *            DVP_FLAG_FIFO_RESET_Disable
+ *          j - receive reset enable
+ *            DVP_RX_RESET_Enable
+ *            DVP_RX_RESET_Disable
+ *
+ * @return  none
+ */
+void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j)
+{
+    switch(s)
+    {
+        case DVP_DMA_Enable:
+            DVP->CR1 |= RB_DVP_DMA_EN;
+            break;
+        case DVP_DMA_Disable:
+            DVP->CR1 &= ~RB_DVP_DMA_EN;
+            break;
+        default:
+            break;
+    }
+
+    switch(i)
+    {
+        case DVP_RX_RESET_Enable:
+            DVP->CR1 |= RB_DVP_ALL_CLR;
+            break;
+        case DVP_RX_RESET_Disable:
+            DVP->CR1 &= ~RB_DVP_ALL_CLR;
+            break;
+        default:
+            break;
+    }
+
+    switch(j)
+    {
+        case DVP_RX_RESET_Enable:
+            DVP->CR1 |= RB_DVP_RCV_CLR;
+            break;
+        case DVP_RX_RESET_Disable:
+            DVP->CR1 &= ~RB_DVP_RCV_CLR;
+            break;
+        default:
+            break;
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_eth.c

@@ -0,0 +1,2522 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_eth.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the ETH firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_eth.h"
+#include "ch32v30x_rcc.h"
+
+ETH_DMADESCTypeDef *DMATxDescToSet;
+ETH_DMADESCTypeDef *DMARxDescToGet;
+ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
+ETH_DMADESCTypeDef *DMAPTPRxDescToGet;
+
+/*********************************************************************
+ * @fn      ETH_DeInit
+ *
+ * @brief   ETH hardware initialize again.
+ *
+ * @return  none
+ */
+#ifdef CH32V30x_D8C
+void ETH_DeInit(void)
+{
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
+}
+
+#endif
+
+/*********************************************************************
+ * @fn      ETH_StructInit
+ *
+ * @brief   Fills each ETH_InitStruct member with its default value.
+ *
+ * @param   ETH_InitStruct - pointer to a ETH_InitTypeDef structure
+ *        which will be initialized.
+ *
+ * @return  none
+ */
+void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct)
+{
+    /*------------------------   MAC   -----------------------------------*/
+    ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
+    ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
+    ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
+    ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
+    ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
+    ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+    ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
+    ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+    ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+    ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
+    ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
+    ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+    ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
+    ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
+    ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
+    ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
+    ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
+    ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+    ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
+    ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+    ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+    ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+    ETH_InitStruct->ETH_HashTableHigh = 0x0;
+    ETH_InitStruct->ETH_HashTableLow = 0x0;
+    ETH_InitStruct->ETH_PauseTime = 0x0;
+    ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
+    ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
+    ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+    ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
+    ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
+    ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
+    ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
+    /*------------------------   DMA   -----------------------------------*/
+    ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
+    ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+    ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable;
+    ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+    ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
+    ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+    ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+    ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
+    ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
+    ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+    ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
+    ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
+    ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
+    ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
+    ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
+}
+
+/*********************************************************************
+ * @fn      ETH_Start
+ *
+ * @brief   Enables ENET MAC and DMA reception/transmission.
+ *
+ * @return  none
+ */
+void ETH_Start(void)
+{
+    ETH_MACTransmissionCmd(ENABLE);
+    ETH_FlushTransmitFIFO();
+    ETH_MACReceptionCmd(ENABLE);
+    ETH_DMATransmissionCmd(ENABLE);
+    ETH_DMAReceptionCmd(ENABLE);
+}
+
+/*********************************************************************
+ * @fn      ETH_HandleTxPkt
+ *
+ * @brief   Transmits a packet, from application buffer, pointed by ppkt.
+ *
+ * @param   ppkt - pointer to the application's packet buffer to transmit.
+ *          FrameLength - Tx Packet size.
+ *
+ * @return  ETH_ERROR - in case of Tx desc owned by DMA.
+ *          ETH_SUCCESS - for correct transmission.
+ */
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
+{
+    uint32_t offset = 0;
+
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+    {
+        return ETH_ERROR;
+    }
+
+    for(offset = 0; offset < FrameLength; offset++)
+    {
+        (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+    }
+
+    DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+    DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+    DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+
+    if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+    {
+        ETH->DMASR = ETH_DMASR_TBUS;
+        ETH->DMATPDR = 0;
+    }
+
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+    {
+        DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr);
+    }
+    else
+    {
+        if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+        {
+            DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR);
+        }
+        else
+        {
+            DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+        }
+    }
+
+    return ETH_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      ETH_HandleRxPkt
+ *
+ * @brief   Receives a packet and copies it to memory pointed by ppkt.
+ *
+ * @param   ppkt - pointer to the application packet receive buffer.
+ *
+ * @return  ETH_ERROR - if there is error in reception
+ *          framelength - received packet size if packet reception is correct
+ */
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
+{
+    uint32_t offset = 0, framelength = 0;
+
+    if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+    {
+        return ETH_ERROR;
+    }
+
+    if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+    {
+        framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+
+        for(offset = 0; offset < framelength; offset++)
+        {
+            (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
+        }
+    }
+    else
+    {
+        framelength = ETH_ERROR;
+    }
+
+    DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+    if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+    {
+        ETH->DMASR = ETH_DMASR_RBUS;
+        ETH->DMARPDR = 0;
+    }
+
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+    {
+        DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr);
+    }
+    else
+    {
+        if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+        {
+            DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR);
+        }
+        else
+        {
+            DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+        }
+    }
+
+    return (framelength);
+}
+
+/*********************************************************************
+ * @fn      ETH_GetRxPktSize
+ *
+ * @brief   Get the size of received the received packet.
+ *
+ * @return  framelength - received packet size
+ */
+uint32_t ETH_GetRxPktSize(void)
+{
+    uint32_t frameLength = 0;
+    if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+    {
+        frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
+    }
+
+    return frameLength;
+}
+
+/*********************************************************************
+ * @fn      ETH_DropRxPkt
+ *
+ * @brief   Drop a Received packet.
+ *
+ * @return  none
+ */
+void ETH_DropRxPkt(void)
+{
+    DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+    {
+        DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr);
+    }
+    else
+    {
+        if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+        {
+            DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR);
+        }
+        else
+        {
+            DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_ReadPHYRegister
+ *
+ * @brief   Read a PHY register.
+ *
+ * @param   PHYAddress - PHY device address, is the index of one of supported 32 PHY devices.
+ *          PHYReg - PHY register address, is the index of one of the 32 PHY register.
+ *
+ * @return  ETH_ERROR - in case of timeout.
+ *          MAC MIIDR register value - Data read from the selected PHY register.
+ */
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
+{
+    uint32_t      tmpreg = 0;
+    __IO uint32_t timeout = 0;
+
+    tmpreg = ETH->MACMIIAR;
+    tmpreg &= ~MACMIIAR_CR_MASK;
+    tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA);
+    tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR);
+    tmpreg &= ~ETH_MACMIIAR_MW;
+    tmpreg |= ETH_MACMIIAR_MB;
+    ETH->MACMIIAR = tmpreg;
+
+    do
+    {
+        timeout++;
+        tmpreg = ETH->MACMIIAR;
+    } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
+
+    if(timeout == PHY_READ_TO)
+    {
+        return (uint16_t)ETH_ERROR;
+    }
+
+    return (uint16_t)(ETH->MACMIIDR);
+}
+
+/*********************************************************************
+ * @fn      ETH_WritePHYRegister
+ *
+ * @brief   Write to a PHY register.
+ *
+ * @param   PHYAddress - PHY device address, is the index of one of supported 32 PHY devices.
+ *          PHYReg - PHY register address, is the index of one of the 32 PHY register.
+ *          PHYValue - the value to write.
+ *
+ * @return  ETH_ERROR - in case of timeout.
+ *          ETH_SUCCESS - for correct write
+ */
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
+{
+    uint32_t      tmpreg = 0;
+    __IO uint32_t timeout = 0;
+
+    tmpreg = ETH->MACMIIAR;
+    tmpreg &= ~MACMIIAR_CR_MASK;
+    tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA);
+    tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR);
+    tmpreg |= ETH_MACMIIAR_MW;
+    tmpreg |= ETH_MACMIIAR_MB;
+    ETH->MACMIIDR = PHYValue;
+    ETH->MACMIIAR = tmpreg;
+
+    do
+    {
+        timeout++;
+        tmpreg = ETH->MACMIIAR;
+    } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
+
+    if(timeout >= PHY_WRITE_TO)
+    {
+        return ETH_ERROR;
+    }
+
+    return ETH_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      ETH_PHYLoopBackCmd
+ *
+ * @brief   Enables or disables the PHY loopBack mode.
+ *
+ * @param   PHYAddress - PHY device address, is the index of one of supported 32 PHY devices.
+ *          NewState - new state of the PHY loopBack mode.
+ *
+ * @return  ETH_ERROR - in case of bad PHY configuration.
+ *          ETH_SUCCESS - for correct PHY configuration.
+ */
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
+
+    if(NewState != DISABLE)
+    {
+        tmpreg |= PHY_Loopback;
+    }
+    else
+    {
+        tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
+    }
+
+    if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
+    {
+        return ETH_SUCCESS;
+    }
+    else
+    {
+        return ETH_ERROR;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MACTransmissionCmd
+ *
+ * @brief   Enables or disables the MAC transmission.
+ *
+ * @param   NewState - new state of the MAC transmission.
+ *
+ * @return  none
+ */
+void ETH_MACTransmissionCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACCR |= ETH_MACCR_TE;
+    }
+    else
+    {
+        ETH->MACCR &= ~ETH_MACCR_TE;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MACReceptionCmd
+ *
+ * @brief   Enables or disables the MAC reception.
+ *
+ * @param   NewState - new state of the MAC reception.
+ *
+ * @return  none
+ */
+void ETH_MACReceptionCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACCR |= ETH_MACCR_RE;
+    }
+    else
+    {
+        ETH->MACCR &= ~ETH_MACCR_RE;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetFlowControlBusyStatus
+ *
+ * @brief   Enables or disables the MAC reception.
+ *
+ * @return  The new state of flow control busy status bit (SET or RESET).
+ */
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_InitiatePauseControlFrame
+ *
+ * @brief   Initiate a Pause Control Frame (Full-duplex only).
+ *
+ * @return  none
+ */
+void ETH_InitiatePauseControlFrame(void)
+{
+    ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+/*********************************************************************
+ * @fn      ETH_BackPressureActivationCmd
+ *
+ * @brief   Enables or disables the MAC BackPressure operation activation (Half-duplex only).
+ *
+ * @param   NewState - new state of the MAC BackPressure operation activation.
+ *
+ * @return  none
+ */
+void ETH_BackPressureActivationCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+    }
+    else
+    {
+        ETH->MACFCR &= ~ETH_MACFCR_FCBBPA;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetMACFlagStatus
+ *
+ * @brief   Checks whether the specified ETHERNET MAC flag is set or not.
+ *
+ * @param   ETH_MAC_FLAG - specifies the flag to check.
+ *
+ * @return  The new state of ETHERNET MAC flag (SET or RESET).
+ */
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetMACITStatus
+ *
+ * @brief   Checks whether the specified ETHERNET MAC interrupt has occurred or not.
+ *
+ * @param   ETH_MAC_IT - specifies the interrupt source to check.
+ *
+ * @return  The new state of ETHERNET MAC interrupt (SET or RESET).
+ */
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_MACITConfig
+ *
+ * @brief   Enables or disables the specified ETHERNET MAC interrupts.
+ *
+ * @param   ETH_MAC_IT - specifies the interrupt source to check.
+ *          NewState - new state of the specified ETHERNET MAC interrupts.
+ *
+ * @return  none
+ */
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
+    }
+    else
+    {
+        ETH->MACIMR |= ETH_MAC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MACAddressConfig
+ *
+ * @brief   Configures the selected MAC address.
+ *
+ * @param   MacAddr - The MAC addres to configure.
+ *            ETH_MAC_Address0 - MAC Address0
+ *            ETH_MAC_Address1 - MAC Address1
+ *            ETH_MAC_Address2 - MAC Address2
+ *            ETH_MAC_Address3 - MAC Address3
+ *            Addr - Pointer on MAC address buffer data (6 bytes).
+ *
+ * @return  none
+ */
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
+{
+    uint32_t tmpreg;
+
+    tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+    (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
+    tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+
+    (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetMACAddress
+ *
+ * @brief   Get the selected MAC address.
+ *
+ * @param   MacAddr - The MAC address to return.
+ *            ETH_MAC_Address0 - MAC Address0
+ *            ETH_MAC_Address1 - MAC Address1
+ *            ETH_MAC_Address2 - MAC Address2
+ *            ETH_MAC_Address3 - MAC Address3
+ *            Addr - Pointer on MAC address buffer data (6 bytes).
+ *
+ * @return  none
+ */
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
+{
+    uint32_t tmpreg;
+
+    tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr));
+
+    Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
+    Addr[4] = (tmpreg & (uint8_t)0xFF);
+    tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr));
+    Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
+    Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
+    Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF);
+    Addr[0] = (tmpreg & (uint8_t)0xFF);
+}
+
+/*********************************************************************
+ * @fn      ETH_MACAddressPerfectFilterCmd
+ *
+ * @brief   Enables or disables the Address filter module uses the specified.
+ *
+ * @param   MacAddr - The MAC address to return.
+ *            ETH_MAC_Address0 - MAC Address0
+ *            ETH_MAC_Address1 - MAC Address1
+ *            ETH_MAC_Address2 - MAC Address2
+ *            ETH_MAC_Address3 - MAC Address3
+ *            NewState - new state of the specified ETHERNET MAC address use.
+ *
+ * @return  none
+ */
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;
+    }
+    else
+    {
+        (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MACAddressFilterConfig
+ *
+ * @brief   Set the filter type for the specified ETHERNET MAC address.
+ *
+ * @param   MacAddr - specifies the ETHERNET MAC address.
+ *            ETH_MAC_Address0 - MAC Address0
+ *            ETH_MAC_Address1 - MAC Address1
+ *            ETH_MAC_Address2 - MAC Address2
+ *            ETH_MAC_Address3 - MAC Address3
+ *          Filter - specifies the used frame received field for comparaison.
+ *            ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the
+ *        SA fields of the received frame.
+ *            ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the
+ *        DA fields of the received frame.
+ *
+ * @return  none
+ */
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
+{
+    if(Filter != ETH_MAC_AddressFilter_DA)
+    {
+        (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;
+    }
+    else
+    {
+        (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MACAddressMaskBytesFilterConfig
+ *
+ * @brief   Set the filter type for the specified ETHERNET MAC address.
+ *
+ * @param   MacAddr - specifies the ETHERNET MAC address.
+ *            ETH_MAC_Address1 - MAC Address1
+ *            ETH_MAC_Address2 - MAC Address2
+ *            ETH_MAC_Address3 - MAC Address3
+ *          MaskByte - specifies the used address bytes for comparaison
+ *            ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0].
+ *            ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24].
+ *            ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16].
+ *            ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8].
+ *            ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0].
+ *
+ * @return  none
+ */
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
+{
+    (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC);
+    (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescChainInit
+ *
+ * @brief   Initializes the DMA Tx descriptors in chain mode.
+ *
+ * @param   DMATxDescTab - Pointer on the first Tx desc list
+ *          TxBuff - Pointer on the first TxBuffer list
+ *          TxBuffCount - Number of the used Tx desc in the list
+ *
+ * @return  none
+ */
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
+{
+    uint32_t            i = 0;
+    ETH_DMADESCTypeDef *DMATxDesc;
+
+    DMATxDescToSet = DMATxDescTab;
+
+    for(i = 0; i < TxBuffCount; i++)
+    {
+        DMATxDesc = DMATxDescTab + i;
+        DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC;
+        DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]);
+
+        if(i < (TxBuffCount - 1))
+        {
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1);
+        }
+        else
+        {
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab;
+        }
+    }
+
+    ETH->DMATDLAR = (uint32_t)DMATxDescTab;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescRingInit
+ *
+ * @brief   Initializes the DMA Tx descriptors in ring mode.
+ *
+ * @param   DMATxDescTab - Pointer on the first Tx desc list.
+ *            TxBuff1 - Pointer on the first TxBuffer1 list.
+ *            TxBuff2 - Pointer on the first TxBuffer2 list.
+ *            TxBuffCount - Number of the used Tx desc in the list.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
+{
+    uint32_t            i = 0;
+    ETH_DMADESCTypeDef *DMATxDesc;
+
+    DMATxDescToSet = DMATxDescTab;
+
+    for(i = 0; i < TxBuffCount; i++)
+    {
+        DMATxDesc = DMATxDescTab + i;
+        DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]);
+        DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]);
+
+        if(i == (TxBuffCount - 1))
+        {
+            DMATxDesc->Status = ETH_DMATxDesc_TER;
+        }
+    }
+
+    ETH->DMATDLAR = (uint32_t)DMATxDescTab;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMATxDescFlagStatus
+ *
+ * @brief   Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor
+ *          ETH_DMATxDescFlag - specifies the flag to check.
+ *            ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine
+ *            ETH_DMATxDesc_IC - Interrupt on completetion
+ *            ETH_DMATxDesc_LS - Last Segment
+ *            ETH_DMATxDesc_FS - First Segment
+ *            ETH_DMATxDesc_DC - Disable CRC
+ *            ETH_DMATxDesc_DP - Disable Pad
+ *            ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable
+ *            ETH_DMATxDesc_TER - Transmit End of Ring
+ *            ETH_DMATxDesc_TCH - Second Address Chained
+ *            ETH_DMATxDesc_TTSS - Tx Time Stamp Status
+ *            ETH_DMATxDesc_IHE - IP Header Error
+ *            ETH_DMATxDesc_ES - Error summary
+ *            ETH_DMATxDesc_JT - Jabber Timeout
+ *            ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush
+ *            ETH_DMATxDesc_PCE - Payload Checksum Error
+ *            ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission
+ *            ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver
+ *            ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision
+ *            ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions
+ *            ETH_DMATxDesc_VF - VLAN Frame
+ *            ETH_DMATxDesc_CC - Collision Count
+ *            ETH_DMATxDesc_ED - Excessive Deferral
+ *            ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory
+ *            ETH_DMATxDesc_DB - Deferred Bit
+ *
+ * @return  The new state of ETH_DMATxDescFlag (SET or RESET).
+ */
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMATxDescCollisionCount
+ *
+ * @brief   Returns the specified ETHERNET DMA Tx Desc collision count.
+ *
+ * @param   pointer on a DMA Tx descriptor.
+ *
+ * @return  The Transmit descriptor collision counter value.
+ */
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
+{
+    return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
+}
+
+/*********************************************************************
+ * @fn      ETH_SetDMATxDescOwnBit
+ *
+ * @brief   Set the specified DMA Tx Desc Own bit.
+ *
+ * @param   DMATxDesc - Pointer on a Tx desc
+ *
+ * @return  none
+ */
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
+{
+    DMATxDesc->Status |= ETH_DMATxDesc_OWN;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescTransmitITConfig
+ *
+ * @brief   Enables or disables the specified DMA Tx Desc Transmit interrupt.
+ *
+ * @param   Pointer on a Tx desc.
+ *          NewState - new state of the DMA Tx Desc transmit interrupt.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMATxDesc->Status |= ETH_DMATxDesc_IC;
+    }
+    else
+    {
+        DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescFrameSegmentConfig
+ *
+ * @brief   Enables or disables the specified DMA Tx Desc Transmit interrupt.
+ *
+ * @param   PDMATxDesc - Pointer on a Tx desc.
+ *          ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
+{
+    DMATxDesc->Status |= DMATxDesc_FrameSegment;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescChecksumInsertionConfig
+ *
+ * @brief   Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor.
+ *          DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
+{
+    DMATxDesc->Status |= DMATxDesc_Checksum;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescCRCCmd
+ *
+ * @brief   Enables or disables the DMA Tx Desc CRC.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor
+ *          NewState - new state of the specified DMA Tx Desc CRC.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
+    }
+    else
+    {
+        DMATxDesc->Status |= ETH_DMATxDesc_DC;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescEndOfRingCmd
+ *
+ * @brief   Enables or disables the DMA Tx Desc end of ring.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor.
+ *          NewState - new state of the specified DMA Tx Desc end of ring.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMATxDesc->Status |= ETH_DMATxDesc_TER;
+    }
+    else
+    {
+        DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescSecondAddressChainedCmd
+ *
+ * @brief   Enables or disables the DMA Tx Desc second address chained.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor
+ *          NewState - new state of the specified DMA Tx Desc second address chained.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMATxDesc->Status |= ETH_DMATxDesc_TCH;
+    }
+    else
+    {
+        DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescShortFramePaddingCmd
+ *
+ * @brief   Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor.
+ *          NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
+    }
+    else
+    {
+        DMATxDesc->Status |= ETH_DMATxDesc_DP;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescTimeStampCmd
+ *
+ * @brief   Enables or disables the DMA Tx Desc time stamp.
+ *
+ * @param   DMATxDesc - pointer on a DMA Tx descriptor
+ *          NewState - new state of the specified DMA Tx Desc time stamp.
+ *
+ * @return  none
+ */
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
+    }
+    else
+    {
+        DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATxDescBufferSizeConfig
+ *
+ * @brief   Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
+ *
+ * @param   DMATxDesc - Pointer on a Tx desc.
+ *          BufferSize1 - specifies the Tx desc buffer1 size.
+ *          RxBuff2 - Pointer on the first RxBuffer2 list
+ *          BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used).
+ *
+ * @return  none
+ */
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
+{
+    DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
+}
+
+/*********************************************************************
+ * @fn      ETH_DMARxDescChainInit
+ *
+ * @brief   Initializes the DMA Rx descriptors in chain mode.
+ *
+ * @param   DMARxDescTab - Pointer on the first Rx desc list.
+ *          RxBuff - Pointer on the first RxBuffer list.
+ *          RxBuffCount - Number of the used Rx desc in the list.
+ *
+ * @return  none
+ */
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+    uint32_t            i = 0;
+    ETH_DMADESCTypeDef *DMARxDesc;
+
+    DMARxDescToGet = DMARxDescTab;
+
+    for(i = 0; i < RxBuffCount; i++)
+    {
+        DMARxDesc = DMARxDescTab + i;
+        DMARxDesc->Status = ETH_DMARxDesc_OWN;
+        DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
+        DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]);
+
+        if(i < (RxBuffCount - 1))
+        {
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1);
+        }
+        else
+        {
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+        }
+    }
+
+    ETH->DMARDLAR = (uint32_t)DMARxDescTab;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMARxDescRingInit
+ *
+ * @brief   Initializes the DMA Rx descriptors in ring mode.
+ *
+ * @param   DMARxDescTab - Pointer on the first Rx desc list.
+ *            RxBuff1 - Pointer on the first RxBuffer1 list.
+ *            RxBuff2 - Pointer on the first RxBuffer2 list
+ *            RxBuffCount - Number of the used Rx desc in the list.
+ *
+ * @return  none
+ */
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
+{
+    uint32_t            i = 0;
+    ETH_DMADESCTypeDef *DMARxDesc;
+
+    DMARxDescToGet = DMARxDescTab;
+
+    for(i = 0; i < RxBuffCount; i++)
+    {
+        DMARxDesc = DMARxDescTab + i;
+        DMARxDesc->Status = ETH_DMARxDesc_OWN;
+        DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
+        DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]);
+        DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]);
+
+        if(i == (RxBuffCount - 1))
+        {
+            DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+        }
+    }
+
+    ETH->DMARDLAR = (uint32_t)DMARxDescTab;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMARxDescFlagStatus
+ *
+ * @brief   Checks whether the specified ETHERNET Rx Desc flag is set or not.
+ *
+ * @param   DMARxDesc - pointer on a DMA Rx descriptor.
+ *          ETH_DMARxDescFlag - specifies the flag to check.
+ *            ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine
+ *            ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame
+ *            ETH_DMARxDesc_ES - Error summary
+ *            ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame
+ *            ETH_DMARxDesc_SAF - SA Filter Fail for the received frame
+ *            ETH_DMARxDesc_LE - Frame size not matching with length field
+ *            ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow
+ *            ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame
+ *            ETH_DMARxDesc_FS - First descriptor of the frame
+ *            ETH_DMARxDesc_LS - Last descriptor of the frame
+ *            ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
+ *            ETH_DMARxDesc_LC - Late collision occurred during reception
+ *            ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3
+ *            ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception
+ *            ETH_DMARxDesc_RE - Receive error: error reported by MII interface
+ *            ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits
+ *            ETH_DMARxDesc_CE - CRC error
+ *            ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+ *
+ * @return  The new state of ETH_DMARxDescFlag (SET or RESET).
+ */
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_SetDMARxDescOwnBit
+ *
+ * @brief   Set the specified DMA Rx Desc Own bit.
+ *
+ * @param   DMARxDesc - Pointer on a Rx desc
+ *
+ * @return  none
+ */
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
+{
+    DMARxDesc->Status |= ETH_DMARxDesc_OWN;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMARxDescFrameLength
+ *
+ * @brief   Returns the specified DMA Rx Desc frame length.
+ *
+ * @param   DMARxDesc - pointer on a DMA Rx descriptor
+ *
+ * @return  The Rx descriptor received frame length.
+ */
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
+{
+    return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/*********************************************************************
+ * @fn      ETH_DMARxDescReceiveITConfig
+ *
+ * @brief   Enables or disables the specified DMA Rx Desc receive interrupt.
+ *
+ * @param   DMARxDesc - Pointer on a Rx desc
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC);
+    }
+    else
+    {
+        DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMARxDescEndOfRingCmd
+ *
+ * @brief   Enables or disables the DMA Rx Desc end of ring.
+ *
+ * @param   DMARxDesc - pointer on a DMA Rx descriptor.
+ *          NewState - new state of the specified DMA Rx Desc end of ring.
+ *
+ * @return  none
+ */
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+    }
+    else
+    {
+        DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMARxDescSecondAddressChainedCmd
+ *
+ * @brief   Returns the specified ETHERNET DMA Rx Desc buffer size.
+ *
+ * @param   DMARxDesc - pointer on a DMA Rx descriptor.
+ *          NewState - new state of the specified DMA Rx Desc second address chained.
+ *
+ * @return  none
+ */
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
+    }
+    else
+    {
+        DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMARxDescBufferSize
+ *
+ * @brief   Returns the specified ETHERNET DMA Rx Desc buffer size.
+ *
+ * @param   DMARxDesc - pointer on a DMA Rx descriptor.
+ *          DMARxDesc_Buffer - specifies the DMA Rx Desc buffer.
+ *          ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1
+ *          ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2
+ *
+ * @return  The Receive descriptor frame length.
+ */
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
+{
+    if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
+    {
+        return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
+    }
+    else
+    {
+        return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_SoftwareReset
+ *
+ * @brief   Resets all MAC subsystem internal registers and logic.
+ *
+ * @return  none
+ */
+void ETH_SoftwareReset(void)
+{
+    ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetSoftwareResetStatus
+ *
+ * @brief   Checks whether the ETHERNET software reset bit is set or not.
+ *
+ * @return  The new state of DMA Bus Mode register SR bit (SET or RESET).
+ */
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+    if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    printf("ETH->DMABMR is:%08x\n", ETH->DMABMR);
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetlinkStaus
+ *
+ * @brief   Checks whether the internal 10BASE-T PHY is link or not.
+ *
+ * @return  Internal 10BASE-T PHY is link or not.
+ */
+FlagStatus ETH_GetlinkStaus(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->DMASR & 0x80000000) != (uint32_t)RESET)
+    {
+        bitstatus = PHY_10BASE_T_LINKED;
+    }
+    else
+    {
+        bitstatus = PHY_10BASE_T_NOT_LINKED;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMAFlagStatus
+ *
+ * @brief   Checks whether the specified ETHERNET DMA flag is set or not.
+ *
+ * @param   ETH_DMA_FLAG - specifies the flag to check.
+ *            ETH_DMA_FLAG_TST - Time-stamp trigger flag
+ *            ETH_DMA_FLAG_PMT - PMT flag
+ *            ETH_DMA_FLAG_MMC - MMC flag
+ *            ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access
+ *            ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr
+ *            ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA
+ *            ETH_DMA_FLAG_NIS - Normal interrupt summary flag
+ *            ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag
+ *            ETH_DMA_FLAG_ER - Early receive flag
+ *            ETH_DMA_FLAG_FBE - Fatal bus error flag
+ *            ETH_DMA_FLAG_ET - Early transmit flag
+ *            ETH_DMA_FLAG_RWT - Receive watchdog timeout flag
+ *            ETH_DMA_FLAG_RPS - Receive process stopped flag
+ *            ETH_DMA_FLAG_RBU - Receive buffer unavailable flag
+ *            ETH_DMA_FLAG_R - Receive flag
+ *            ETH_DMA_FLAG_TU - Underflow flag
+ *            ETH_DMA_FLAG_RO - Overflow flag
+ *            ETH_DMA_FLAG_TJT - Transmit jabber timeout flag
+ *            ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag
+ *            ETH_DMA_FLAG_TPS - Transmit process stopped flag
+ *            ETH_DMA_FLAG_T - Transmit flag
+ *
+ * @return  Internal 10BASE-T PHY is link or not.
+ */
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMAClearFlag
+ *
+ * @brief   Checks whether the specified ETHERNET DMA interrupt has occured or not.
+ *
+ * @param   ETH_DMA_FLAG - specifies the flag to clear.
+ *            ETH_DMA_FLAG_NIS - Normal interrupt summary flag
+ *            ETH_DMA_FLAG_AIS - Abnormal interrupt summary  flag
+ *            ETH_DMA_FLAG_ER - Early receive flag
+ *            ETH_DMA_FLAG_FBE - Fatal bus error flag
+ *            ETH_DMA_FLAG_ETI - Early transmit flag
+ *            ETH_DMA_FLAG_RWT - Receive watchdog timeout flag
+ *            ETH_DMA_FLAG_RPS - Receive process stopped flag
+ *            ETH_DMA_FLAG_RBU - Receive buffer unavailable flag
+ *            ETH_DMA_FLAG_R - Receive flag
+ *            ETH_DMA_FLAG_TU - Transmit Underflow flag
+ *            ETH_DMA_FLAG_RO - Receive Overflow flag
+ *            ETH_DMA_FLAG_TJT - Transmit jabber timeout flag
+ *            ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag
+ *            ETH_DMA_FLAG_TPS - Transmit process stopped flag
+ *            ETH_DMA_FLAG_T - Transmit flag
+ *
+ * @return  none
+ */
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
+{
+    ETH->DMASR = (uint32_t)ETH_DMA_FLAG;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMAITStatus
+ *
+ * @brief   Checks whether the specified ETHERNET DMA interrupt has occured or not.
+ *
+ * @param   ETH_DMA_IT - specifies the interrupt pending bit to clear.
+ *            ETH_DMA_IT_TST - Time-stamp trigger interrupt
+ *            ETH_DMA_IT_PMT - PMT interrupt
+ *            ETH_DMA_IT_MMC - MMC interrupt
+ *            ETH_DMA_IT_NIS - Normal interrupt summary
+ *            ETH_DMA_IT_AIS - Abnormal interrupt summary
+ *            ETH_DMA_IT_ER  - Early receive interrupt
+ *            ETH_DMA_IT_FBE - Fatal bus error interrupt
+ *            ETH_DMA_IT_ET  - Early transmit interrupt
+ *            ETH_DMA_IT_RWT - Receive watchdog timeout interrupt
+ *            ETH_DMA_IT_RPS - Receive process stopped interrupt
+ *            ETH_DMA_IT_RBU - Receive buffer unavailable interrupt
+ *            ETH_DMA_IT_R - Receive interrupt
+ *            ETH_DMA_IT_TU - Underflow interrupt
+ *            ETH_DMA_IT_RO - Overflow interrupt
+ *            ETH_DMA_IT_TJT - Transmit jabber timeout interrupt
+ *            ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt
+ *            ETH_DMA_IT_TPS - Transmit process stopped interrupt
+ *            ETH_DMA_IT_T - Transmit interrupt
+ *
+ * @return  The new state of ETH_DMA_IT (SET or RESET).
+ */
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMAClearITPendingBit
+ *
+ * @brief   Clears the ETHERNET’s DMA IT pending bit.
+ *
+ * @param   ETH_DMA_IT - specifies the interrupt pending bit to clear.
+ *            ETH_DMA_IT_NIS - Normal interrupt summary
+ *            ETH_DMA_IT_AIS - Abnormal interrupt summary
+ *            ETH_DMA_IT_ER - Early receive interrupt
+ *            ETH_DMA_IT_FBE - Fatal bus error interrupt
+ *            ETH_DMA_IT_ETI - Early transmit interrupt
+ *            ETH_DMA_IT_RWT - Receive watchdog timeout interrupt
+ *            ETH_DMA_IT_RPS - Receive process stopped interrupt
+ *            ETH_DMA_IT_RBU - Receive buffer unavailable interrupt
+ *            ETH_DMA_IT_R - Receive interrupt
+ *            ETH_DMA_IT_TU - Transmit Underflow interrupt
+ *            ETH_DMA_IT_RO - Receive Overflow interrupt
+ *            ETH_DMA_IT_TJT - Transmit jabber timeout interrupt
+ *            ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt
+ *            ETH_DMA_IT_TPS - Transmit process stopped interrupt
+ *            ETH_DMA_IT_T - Transmit interrupt
+ *
+ * @return  none
+ */
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
+{
+    ETH->DMASR = (uint32_t)ETH_DMA_IT;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetTransmitProcessState
+ *
+ * @brief   Returns the ETHERNET DMA Transmit Process State.
+ *
+ * @return  The new ETHERNET DMA Transmit Process State -
+ *            ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued
+ *            ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor
+ *            ETH_DMA_TransmitProcess_Waiting - Running - waiting for status
+ *            ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory
+ *            ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe
+ *            ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor
+ */
+uint32_t ETH_GetTransmitProcessState(void)
+{
+    return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS));
+}
+
+/*********************************************************************
+ * @fn      ETH_GetReceiveProcessState
+ *
+ * @brief   Returns the ETHERNET DMA Receive Process State.
+ *
+ * @return  The new ETHERNET DMA Receive Process State:
+ *            ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued
+ *            ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor
+ *            ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet
+ *            ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable
+ *            ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor
+ *            ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory
+ */
+uint32_t ETH_GetReceiveProcessState(void)
+{
+    return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS));
+}
+
+/*********************************************************************
+ * @fn      ETH_FlushTransmitFIFO
+ *
+ * @brief   Clears the ETHERNET transmit FIFO.
+ *
+ * @return  none
+ */
+void ETH_FlushTransmitFIFO(void)
+{
+    ETH->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetFlushTransmitFIFOStatus
+ *
+ * @brief   Checks whether the ETHERNET transmit FIFO bit is cleared or not.
+ *
+ * @return  The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
+ */
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+    if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMATransmissionCmd
+ *
+ * @brief   Enables or disables the DMA transmission.
+ *
+ * @param   NewState - new state of the DMA transmission.
+ *
+ * @return  none
+ */
+void ETH_DMATransmissionCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->DMAOMR |= ETH_DMAOMR_ST;
+    }
+    else
+    {
+        ETH->DMAOMR &= ~ETH_DMAOMR_ST;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMAReceptionCmd
+ *
+ * @brief   Enables or disables the DMA reception.
+ *
+ * @param   NewState - new state of the DMA reception.
+ *
+ * @return  none
+ */
+void ETH_DMAReceptionCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->DMAOMR |= ETH_DMAOMR_SR;
+    }
+    else
+    {
+        ETH->DMAOMR &= ~ETH_DMAOMR_SR;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_DMAITConfig
+ *
+ * @brief   Enables or disables the specified ETHERNET DMA interrupts.
+ *
+ * @param   ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled.
+ *            ETH_DMA_IT_NIS - Normal interrupt summary
+ *            ETH_DMA_IT_AIS - Abnormal interrupt summary
+ *            ETH_DMA_IT_ER - Early receive interrupt
+ *            ETH_DMA_IT_FBE - Fatal bus error interrupt
+ *            ETH_DMA_IT_ET - Early transmit interrupt
+ *            ETH_DMA_IT_RWT - Receive watchdog timeout interrupt
+ *            ETH_DMA_IT_RPS - Receive process stopped interrupt
+ *            ETH_DMA_IT_RBU - Receive buffer unavailable interrupt
+ *            ETH_DMA_IT_R - Receive interrupt
+ *            ETH_DMA_IT_TU - Underflow interrupt
+ *            ETH_DMA_IT_RO - Overflow interrupt
+ *            ETH_DMA_IT_TJT - Transmit jabber timeout interrupt
+ *            ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt
+ *            ETH_DMA_IT_TPS - Transmit process stopped interrupt
+ *            ETH_DMA_IT_T - Transmit interrupt
+ *            ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter
+ *            ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter
+ *            NewState - new state of the specified ETHERNET DMA interrupts.
+ *
+ * @return  new state of the specified ETHERNET DMA interrupts.
+ */
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->DMAIER |= ETH_DMA_IT;
+    }
+    else
+    {
+        ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetDMAOverflowStatus
+ *
+ * @brief   Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ *
+ * @param   ETH_DMA_Overflow - specifies the DMA overflow flag to check.
+ *            ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter
+ *            ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter
+ *
+ * @return  The new state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetRxOverflowMissedFrameCounter
+ *
+ * @brief   Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
+ *
+ * @return  The value of Rx overflow Missed Frame Counter.
+ */
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
+{
+    return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
+}
+
+/*********************************************************************
+ * @fn      ETH_GetBufferUnavailableMissedFrameCounter
+ *
+ * @brief   Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
+ *
+ * @return  The value of Buffer unavailable Missed Frame Counter.
+ */
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+    return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
+}
+
+/*********************************************************************
+ * @fn      ETH_GetCurrentTxDescStartAddress
+ *
+ * @brief   Get the ETHERNET DMA DMACHTDR register value.
+ *
+ * @return  The value of the current Tx desc start address.
+ */
+uint32_t ETH_GetCurrentTxDescStartAddress(void)
+{
+    return ((uint32_t)(ETH->DMACHTDR));
+}
+
+/*********************************************************************
+ * @fn      ETH_GetCurrentRxDescStartAddress
+ *
+ * @brief   Get the ETHERNET DMA DMACHRDR register value.
+ *
+ * @return  The value of the current Rx desc start address.
+ */
+uint32_t ETH_GetCurrentRxDescStartAddress(void)
+{
+    return ((uint32_t)(ETH->DMACHRDR));
+}
+
+/*********************************************************************
+ * @fn      ETH_GetCurrentTxBufferAddress
+ *
+ * @brief   Get the ETHERNET DMA DMACHTBAR register value.
+ *
+ * @return  The value of the current Tx buffer address.
+ */
+uint32_t ETH_GetCurrentTxBufferAddress(void)
+{
+    return (DMATxDescToSet->Buffer1Addr);
+}
+
+/*********************************************************************
+ * @fn      ETH_GetCurrentRxBufferAddress
+ *
+ * @brief   Get the ETHERNET DMA DMACHRBAR register value.
+ *
+ * @return  The value of the current Rx buffer address.
+ */
+uint32_t ETH_GetCurrentRxBufferAddress(void)
+{
+    return ((uint32_t)(ETH->DMACHRBAR));
+}
+
+/*********************************************************************
+ * @fn      ETH_ResumeDMATransmission
+ *
+ * @brief   Resumes the DMA Transmission by writing to the DmaTxPollDemand register
+ *
+ * @return  none
+ */
+void ETH_ResumeDMATransmission(void)
+{
+    ETH->DMATPDR = 0;
+}
+
+/*********************************************************************
+ * @fn      ETH_ResumeDMAReception
+ *
+ * @brief   Resumes the DMA Transmission by writing to the DmaRxPollDemand register.
+ *
+ * @return  none
+ */
+void ETH_ResumeDMAReception(void)
+{
+    ETH->DMARPDR = 0;
+}
+
+/*********************************************************************
+ * @fn      ETH_ResetWakeUpFrameFilterRegisterPointer
+ *
+ * @brief   Reset Wakeup frame filter register pointer.
+ *
+ * @return  none
+ */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+/*********************************************************************
+ * @fn      ETH_SetWakeUpFrameFilterRegister
+ *
+ * @brief   Populates the remote wakeup frame registers.
+ *
+ * @param   Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
+ *
+ * @return  none
+ */
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
+{
+    uint32_t i = 0;
+
+    for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++)
+    {
+        ETH->MACRWUFFR = Buffer[i];
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GlobalUnicastWakeUpCmd
+ *
+ * @brief   Enables or disables any unicast packet filtered by the MAC address.
+ *
+ * @param   NewState - new state of the MAC Global Unicast Wake-Up.
+ *
+ * @return  none
+ */
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;
+    }
+    else
+    {
+        ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetPMTFlagStatus
+ *
+ * @brief   Checks whether the specified ETHERNET PMT flag is set or not.
+ *
+ * @param   ETH_PMT_FLAG - specifies the flag to check.
+ *
+ * @return  The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_WakeUpFrameDetectionCmd
+ *
+ * @brief   Enables or disables the MAC Wake-Up Frame Detection.
+ *
+ * @param   NewState - new state of the MAC Wake-Up Frame Detection.
+ *
+ * @return  none
+ */
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;
+    }
+    else
+    {
+        ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MagicPacketDetectionCmd
+ *
+ * @brief   Enables or disables the MAC Magic Packet Detection.
+ *
+ * @param   NewState - new state of the MAC Magic Packet Detection.
+ *
+ * @return  none
+ */
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;
+    }
+    else
+    {
+        ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_PowerDownCmd
+ *
+ * @brief   Enables or disables the MAC Power Down.
+ *
+ * @param   NewState - new state of the MAC Power Down.
+ *
+ * @return  none
+ */
+void ETH_PowerDownCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;
+    }
+    else
+    {
+        ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MMCCounterFreezeCmd
+ *
+ * @brief   Enables or disables the MMC Counter Freeze.
+ *
+ * @param   NewState - new state of the MMC Counter Freeze.
+ *
+ * @return  none
+ */
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MMCCR |= ETH_MMCCR_MCF;
+    }
+    else
+    {
+        ETH->MMCCR &= ~ETH_MMCCR_MCF;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MMCResetOnReadCmd
+ *
+ * @brief   Enables or disables the MMC Reset On Read.
+ *
+ * @param   NewState - new state of the MMC Reset On Read.
+ *
+ * @return  none
+ */
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MMCCR |= ETH_MMCCR_ROR;
+    }
+    else
+    {
+        ETH->MMCCR &= ~ETH_MMCCR_ROR;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MMCCounterRolloverCmd
+ *
+ * @brief   Enables or disables the MMC Counter Stop Rollover.
+ *
+ * @param   NewState - new state of the MMC Counter Stop Rollover.
+ *
+ * @return  none
+ */
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->MMCCR &= ~ETH_MMCCR_CSR;
+    }
+    else
+    {
+        ETH->MMCCR |= ETH_MMCCR_CSR;
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_MMCCountersReset
+ *
+ * @brief   Resets the MMC Counters.
+ *
+ * @return  none
+ */
+void ETH_MMCCountersReset(void)
+{
+    ETH->MMCCR |= ETH_MMCCR_CR;
+}
+
+/*********************************************************************
+ * @fn      ETH_MMCITConfig
+ *
+ * @brief   Enables or disables the specified ETHERNET MMC interrupts.
+ *
+ * @param   ETH_MMC_IT - specifies the ETHERNET MMC interrupt.
+ *            ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value.
+ *            ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value.
+ *            ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value.
+ *            ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value.
+ *            ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value.
+ *            ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value.
+ *          NewState - new state of the specified ETHERNET MMC interrupts.
+ *
+ * @return  none
+ */
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
+{
+    if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+    {
+        ETH_MMC_IT &= 0xEFFFFFFF;
+
+        if(NewState != DISABLE)
+        {
+            ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT);
+        }
+        else
+        {
+            ETH->MMCRIMR |= ETH_MMC_IT;
+        }
+    }
+    else
+    {
+        if(NewState != DISABLE)
+        {
+            ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT);
+        }
+        else
+        {
+            ETH->MMCTIMR |= ETH_MMC_IT;
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetMMCITStatus
+ *
+ * @brief   Checks whether the specified ETHERNET MMC IT is set or not.
+ *
+ * @param   ETH_MMC_IT - specifies the ETHERNET MMC interrupt.
+ *            ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value.
+ *            ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value.
+ *            ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value .
+ *            ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value.
+ *            ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value.
+ *            ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value.
+ *
+ * @return  The value of ETHERNET MMC IT (SET or RESET).
+ */
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+    {
+        if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetMMCRegister
+ *
+ * @brief   Get the specified ETHERNET MMC register value.
+ *
+ * @param   ETH_MMCReg - specifies the ETHERNET MMC register.
+ *            ETH_MMCCR - MMC CR register
+ *            ETH_MMCRIR - MMC RIR register
+ *            ETH_MMCTIR - MMC TIR register
+ *            ETH_MMCRIMR - MMC RIMR register
+ *            ETH_MMCTIMR - MMC TIMR register
+ *            ETH_MMCTGFSCCR - MMC TGFSCCR register
+ *            ETH_MMCTGFMSCCR - MMC TGFMSCCR register
+ *            ETH_MMCTGFCR - MMC TGFCR register
+ *            ETH_MMCRFCECR - MMC RFCECR register
+ *            ETH_MMCRFAECR - MMC RFAECR register
+ *            ETH_MMCRGUFCR - MMC RGUFCRregister
+ *
+ * @return  The value of ETHERNET MMC Register value.
+ */
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
+{
+    return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
+}
+
+/*********************************************************************
+ * @fn      ETH_EnablePTPTimeStampAddend
+ *
+ * @brief   Updated the PTP block for fine correction with the Time Stamp Addend register value.
+ *
+ * @return  none
+ */
+void ETH_EnablePTPTimeStampAddend(void)
+{
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;
+}
+
+/*********************************************************************
+ * @fn      ETH_EnablePTPTimeStampInterruptTrigger
+ *
+ * @brief   Enable the PTP Time Stamp interrupt trigger
+ *
+ * @return  none
+ */
+void ETH_EnablePTPTimeStampInterruptTrigger(void)
+{
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;
+}
+
+/*********************************************************************
+ * @fn      ETH_EnablePTPTimeStampUpdate
+ *
+ * @brief   Updated the PTP system time with the Time Stamp Update register value.
+ *
+ * @return  none
+ */
+void ETH_EnablePTPTimeStampUpdate(void)
+{
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;
+}
+
+/*********************************************************************
+ * @fn      ETH_InitializePTPTimeStamp
+ *
+ * @brief   Initialize the PTP Time Stamp.
+ *
+ * @return  none
+ */
+void ETH_InitializePTPTimeStamp(void)
+{
+    ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;
+}
+
+/*********************************************************************
+ * @fn      ETH_PTPUpdateMethodConfig
+ *
+ * @brief   Selects the PTP Update method.
+ *
+ * @param   UpdateMethod - the PTP Update method.
+ *
+ * @return  none
+ */
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
+{
+    if(UpdateMethod != ETH_PTP_CoarseUpdate)
+    {
+        ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
+    }
+    else
+    {
+        ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_PTPTimeStampCmd
+ *
+ * @brief   Enables or disables the PTP time stamp for transmit and receive frames.
+ *
+ * @param   NewState - new state of the PTP time stamp for transmit and receive frames.
+ *
+ * @return  none
+ */
+void ETH_PTPTimeStampCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
+    }
+    else
+    {
+        ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
+    }
+}
+
+/*********************************************************************
+ * @fn      ETH_GetPTPFlagStatus
+ *
+ * @brief   Checks whether the specified ETHERNET PTP flag is set or not.
+ *
+ * @param   The new state of ETHERNET PTP Flag (SET or RESET).
+ *
+ * @return  none
+ */
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ETH_SetPTPSubSecondIncrement
+ *
+ * @brief   Sets the system time Sub-Second Increment value.
+ *
+ * @param   SubSecondValue - specifies the PTP Sub-Second Increment Register value.
+ *
+ * @return  none
+ */
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
+{
+    ETH->PTPSSIR = SubSecondValue;
+}
+
+/*********************************************************************
+ * @fn      ETH_SetPTPTimeStampUpdate
+ *
+ * @brief   Sets the Time Stamp update sign and values.
+ *
+ * @param   Sign - specifies the PTP Time update value sign.
+ *          SecondValue - specifies the PTP Time update second value.
+ *          SubSecondValue - specifies the PTP Time update sub-second value.
+ *
+ * @return  none
+ */
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
+{
+    ETH->PTPTSHUR = SecondValue;
+    ETH->PTPTSLUR = Sign | SubSecondValue;
+}
+
+/*********************************************************************
+ * @fn      ETH_SetPTPTimeStampAddend
+ *
+ * @brief   Sets the Time Stamp Addend value.
+ *
+ * @param   Value - specifies the PTP Time Stamp Addend Register value.
+ *
+ * @return  none
+ */
+void ETH_SetPTPTimeStampAddend(uint32_t Value)
+{
+    /* Set the PTP Time Stamp Addend Register */
+    ETH->PTPTSAR = Value;
+}
+
+/*********************************************************************
+ * @fn      ETH_SetPTPTargetTime
+ *
+ * @brief   Sets the Target Time registers values.
+ *
+ * @param   HighValue - specifies the PTP Target Time High Register value.
+ *          LowValue - specifies the PTP Target Time Low Register value.
+ *
+ * @return  none
+ */
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
+{
+    ETH->PTPTTHR = HighValue;
+    ETH->PTPTTLR = LowValue;
+}
+
+/*********************************************************************
+ * @fn      ETH_GetPTPRegister
+ *
+ * @brief   Get the specified ETHERNET PTP register value.
+ *
+ * @param   ETH_PTPReg - specifies the ETHERNET PTP register.
+ *            ETH_PTPTSCR - Sub-Second Increment Register
+ *            ETH_PTPSSIR - Sub-Second Increment Register
+ *            ETH_PTPTSHR - Time Stamp High Register
+ *            ETH_PTPTSLR - Time Stamp Low Register
+ *            ETH_PTPTSHUR - Time Stamp High Update Register
+ *            ETH_PTPTSLUR - Time Stamp Low Update Register
+ *            ETH_PTPTSAR - Time Stamp Addend Register
+ *            ETH_PTPTTHR - Target Time High Register
+ *            ETH_PTPTTLR - Target Time Low Register
+ *
+ * @return  The value of ETHERNET PTP Register value.
+ */
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
+{
+    return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
+}
+
+/*********************************************************************
+ * @fn      ETH_DMAPTPTxDescChainInit
+ *
+ * @brief   Initializes the DMA Tx descriptors in chain mode with PTP.
+ *
+ * @param   DMATxDescTab - Pointer on the first Tx desc list.
+ *          DMAPTPTxDescTab - Pointer on the first PTP Tx desc list.
+ *          TxBuff - Pointer on the first TxBuffer list.
+ *          TxBuffCount - Number of the used Tx desc in the list.
+ *
+ * @return  none.
+ */
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,
+                               uint8_t *TxBuff, uint32_t TxBuffCount)
+{
+    uint32_t            i = 0;
+    ETH_DMADESCTypeDef *DMATxDesc;
+
+    DMATxDescToSet = DMATxDescTab;
+    DMAPTPTxDescToSet = DMAPTPTxDescTab;
+
+    for(i = 0; i < TxBuffCount; i++)
+    {
+        DMATxDesc = DMATxDescTab + i;
+        DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
+        DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]);
+
+        if(i < (TxBuffCount - 1))
+        {
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1);
+        }
+        else
+        {
+            DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab;
+        }
+
+        (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
+        (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
+    }
+
+    (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab;
+
+    ETH->DMATDLAR = (uint32_t)DMATxDescTab;
+}
+
+/*********************************************************************
+ * @fn      ETH_DMAPTPRxDescChainInit
+ *
+ * @brief   Initializes the DMA Rx descriptors in chain mode.
+ *
+ * @param   DMARxDescTab - Pointer on the first Rx desc list.
+ *          DMAPTPRxDescTab - Pointer on the first PTP Rx desc list.
+ *          RxBuff - Pointer on the first RxBuffer list.
+ *          RxBuffCount - Number of the used Rx desc in the list.
+ *
+ * @return  none.
+ */
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,
+                               uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+    uint32_t            i = 0;
+    ETH_DMADESCTypeDef *DMARxDesc;
+
+    DMARxDescToGet = DMARxDescTab;
+    DMAPTPRxDescToGet = DMAPTPRxDescTab;
+
+    for(i = 0; i < RxBuffCount; i++)
+    {
+        DMARxDesc = DMARxDescTab + i;
+        DMARxDesc->Status = ETH_DMARxDesc_OWN;
+        DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
+        DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]);
+
+        if(i < (RxBuffCount - 1))
+        {
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1);
+        }
+        else
+        {
+            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+        }
+
+        (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
+        (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
+    }
+
+    (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab;
+    ETH->DMARDLAR = (uint32_t)DMARxDescTab;
+}
+
+/*********************************************************************
+ * @fn      ETH_HandlePTPTxPkt
+ *
+ * @brief   Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.
+ *
+ * @param   ppkt - pointer to application packet buffer to transmit.
+ *          FrameLength - Tx Packet size.
+ *          PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values.
+ *
+ * @return  none.
+ */
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
+{
+    uint32_t offset = 0, timeout = 0;
+
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+    {
+        return ETH_ERROR;
+    }
+
+    for(offset = 0; offset < FrameLength; offset++)
+    {
+        (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));
+    }
+
+    DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
+    DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+    DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+
+    if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+    {
+        ETH->DMASR = ETH_DMASR_TBUS;
+        ETH->DMATPDR = 0;
+    }
+
+    do
+    {
+        timeout++;
+    } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+
+    if(timeout == PHY_READ_TO)
+    {
+        return ETH_ERROR;
+    }
+
+    DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
+    *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
+    *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
+
+    if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+    {
+        DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr);
+        if(DMAPTPTxDescToSet->Status != 0)
+        {
+            DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status);
+        }
+        else
+        {
+            DMAPTPTxDescToSet++;
+        }
+    }
+    else
+    {
+        if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+        {
+            DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR);
+            DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR);
+        }
+        else
+        {
+            DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+            DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+        }
+    }
+
+    return ETH_SUCCESS;
+}
+
+/*********************************************************************
+ * @fn      ETH_HandlePTPRxPkt
+ *
+ * @brief   Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.
+ *
+ * @param   ppkt - pointer to application packet receive buffer.
+ *          PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values.
+ *
+ * @return  ETH_ERROR - if there is error in reception.
+ *          framelength - received packet size if packet reception is correct.
+ */
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
+{
+    uint32_t offset = 0, framelength = 0;
+
+    if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+    {
+        return ETH_ERROR;
+    }
+    if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+       ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+    {
+        framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+
+        for(offset = 0; offset < framelength; offset++)
+        {
+            (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));
+        }
+    }
+    else
+    {
+        framelength = ETH_ERROR;
+    }
+
+    if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+    {
+        ETH->DMASR = ETH_DMASR_RBUS;
+        ETH->DMARPDR = 0;
+    }
+
+    *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
+    *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
+    DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
+
+    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+    {
+        DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr);
+        if(DMAPTPRxDescToGet->Status != 0)
+        {
+            DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status);
+        }
+        else
+        {
+            DMAPTPRxDescToGet++;
+        }
+    }
+    else
+    {
+        if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+        {
+            DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR);
+        }
+        else
+        {
+            DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+        }
+    }
+
+    return (framelength);
+}
+
+/*********************************************************************
+ * @fn      RGMII_TXC_Delay
+ *
+ * @brief   Delay time.
+ *
+ * @return  none
+ */
+void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time)
+{
+    if(clock_polarity)
+    {
+        ETH->MACCR |= (uint32_t)(1 << 1);
+    }
+    else
+    {
+        ETH->MACCR &= ~(uint32_t)(1 << 1);
+    }
+    if(delay_time <= 7)
+    {
+        ETH->MACCR |= (uint32_t)(delay_time << 29);
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_exti.c

@@ -0,0 +1,180 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_exti.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the EXTI firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+***************************************************************************************/
+#include "ch32v30x_exti.h"
+
+/* No interrupt selected */
+#define EXTI_LINENONE    ((uint32_t)0x00000)
+
+/*********************************************************************
+ * @fn      EXTI_DeInit
+ *
+ * @brief   Deinitializes the EXTI peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none.
+ */
+void EXTI_DeInit(void)
+{
+    EXTI->INTENR = 0x00000000;
+    EXTI->EVENR = 0x00000000;
+    EXTI->RTENR = 0x00000000;
+    EXTI->FTENR = 0x00000000;
+    EXTI->INTFR = 0x000FFFFF;
+}
+
+/*********************************************************************
+ * @fn      EXTI_Init
+ *
+ * @brief   Initializes the EXTI peripheral according to the specified
+ *        parameters in the EXTI_InitStruct.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    uint32_t tmp = 0;
+
+    tmp = (uint32_t)EXTI_BASE;
+    if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+    {
+        EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
+        if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+        {
+            EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            tmp = (uint32_t)EXTI_BASE;
+            tmp += EXTI_InitStruct->EXTI_Trigger;
+            *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/*********************************************************************
+ * @fn      EXTI_StructInit
+ *
+ * @brief   Fills each EXTI_InitStruct member with its reset value.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+    EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GenerateSWInterrupt
+ *
+ * @brief   Generates a Software interrupt.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none.
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+    EXTI->SWIEVR |= EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetFlagStatus
+ *
+ * @brief   Checks whether the specified EXTI line flag is set or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+    FlagStatus bitstatus = RESET;
+    if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearFlag
+ *
+ * @brief   Clears the EXTI's line pending flags.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetITStatus
+ *
+ * @brief   Checks whether the specified EXTI line is asserted or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = EXTI->INTENR & EXTI_Line;
+    if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearITPendingBit
+ *
+ * @brief   Clears the EXTI's line pending bits.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_flash.c

@@ -0,0 +1,968 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_flash.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the FLASH firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+***************************************************************************************/
+#include "ch32v30x_flash.h"
+
+/* Flash Control Register bits */
+#define CR_PG_Set                  ((uint32_t)0x00000001)
+#define CR_PG_Reset                ((uint32_t)0x00001FFE)
+#define CR_PER_Set                 ((uint32_t)0x00000002)
+#define CR_PER_Reset               ((uint32_t)0x00001FFD)
+#define CR_MER_Set                 ((uint32_t)0x00000004)
+#define CR_MER_Reset               ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set               ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset             ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set               ((uint32_t)0x00000020)
+#define CR_OPTER_Reset             ((uint32_t)0x00001FDF)
+#define CR_STRT_Set                ((uint32_t)0x00000040)
+#define CR_LOCK_Set                ((uint32_t)0x00000080)
+#define CR_FAST_LOCK_Set           ((uint32_t)0x00008000)
+#define CR_PAGE_PG                 ((uint32_t)0x00010000)
+#define CR_PAGE_ER                 ((uint32_t)0x00020000)
+#define CR_BER32                   ((uint32_t)0x00040000)
+#define CR_BER64                   ((uint32_t)0x00080000)
+#define CR_PG_STRT                 ((uint32_t)0x00200000)
+
+/* FLASH Status Register bits */
+#define SR_BSY                     ((uint32_t)0x00000001)
+#define SR_WR_BSY                  ((uint32_t)0x00000002)
+#define SR_WRPRTERR                ((uint32_t)0x00000010)
+#define SR_EOP                     ((uint32_t)0x00000020)
+
+/* FLASH Mask */
+#define RDPRT_Mask                 ((uint32_t)0x00000002)
+#define WRP0_Mask                  ((uint32_t)0x000000FF)
+#define WRP1_Mask                  ((uint32_t)0x0000FF00)
+#define WRP2_Mask                  ((uint32_t)0x00FF0000)
+#define WRP3_Mask                  ((uint32_t)0xFF000000)
+#define OB_USER_BFB2               ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key                    ((uint16_t)0x00A5)
+#define FLASH_KEY1                 ((uint32_t)0x45670123)
+#define FLASH_KEY2                 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS    ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout               ((uint32_t)0x000B0000)
+#define ProgramTimeout             ((uint32_t)0x00005000)
+
+/*********************************************************************
+ * @fn      FLASH_Unlock
+ *
+ * @brief   Unlocks the FLASH Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_Unlock(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UnlockBank1
+ *
+ * @brief   Unlocks the FLASH Bank1 Program Erase Controller.
+ *          equivalent to FLASH_Unlock function.
+ *
+ * @return  none
+ */
+void FLASH_UnlockBank1(void)
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock
+ *
+ * @brief   Locks the FLASH Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_Lock(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_LockBank1
+ *
+ * @brief   Locks the FLASH Bank1 Program Erase Controller.
+ *
+ * @return  none
+ */
+void FLASH_LockBank1(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage
+ *
+ * @brief   Erases a specified FLASH page(page size 4KB).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PER_Set;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_PER_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseAllPages
+ *
+ * @brief   Erases all FLASH pages.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseAllBank1Pages
+ *
+ * @brief   Erases all Bank1 FLASH pages.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseOptionBytes
+ *
+ * @brief   Erases the FLASH option bytes.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+    uint16_t     rdptmp = RDP_Key;
+    uint32_t     Address = 0x1FFFF800;
+    __IO uint8_t i;
+
+    FLASH_Status status = FLASH_COMPLETE;
+    if(FLASH_GetReadOutProtectionStatus() != RESET)
+    {
+        rdptmp = 0x00;
+    }
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            OB->RDPR = (uint16_t)rdptmp;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+
+        /* Write 0xFF */
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Address + 2 * i) = 0x00FF;
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramWord
+ *
+ * @brief   Programs a word at a specified address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+    FLASH_Status  status = FLASH_COMPLETE;
+    __IO uint32_t tmp = 0;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+
+        *(__IO uint16_t *)Address = (uint16_t)Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            tmp = Address + 2;
+            *(__IO uint16_t *)tmp = Data >> 16;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+        else
+        {
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramHalfWord
+ *
+ * @brief   Programs a half word at a specified address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+        *(__IO uint16_t *)Address = Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        FLASH->CTLR &= CR_PG_Reset;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramOptionByteData
+ *
+ * @brief   Programs a half word at a specified Option Byte Data address.
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data - specifies the data to be programmed.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data));
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EnableWriteProtection
+ *
+ * @brief   Write protects the desired sectors
+ *
+ * @param   FLASH_Sectors - specifies the address of the pages to be write protected.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors)
+{
+    uint16_t     WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    FLASH_Sectors = (uint32_t)(~FLASH_Sectors);
+    WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask);
+    WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8);
+    WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16);
+    WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24);
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[4] = WRP0_Data;
+        pbuf[5] = WRP1_Data;
+        pbuf[6] = WRP2_Data;
+        pbuf[7] = WRP3_Data;
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ReadOutProtection
+ *
+ * @brief   Enables or disables the read out protection.
+ *
+ * @param   Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        if(NewState == DISABLE)
+            pbuf[0] = 0x5AA5;
+        else
+            pbuf[0] = 0x00FF;
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UserOptionByteConfig
+ *
+ * @brief   Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY.
+ *
+ * @param   OB_IWDG - Selects the IWDG mode
+ *            OB_IWDG_SW - Software IWDG selected
+ *            OB_IWDG_HW - Hardware IWDG selected
+ *          OB_STOP - Reset event when entering STOP mode.
+ *            OB_STOP_NoRST - No reset generated when entering in STOP
+ *            OB_STOP_RST - Reset generated when entering in STOP
+ *          OB_STDBY - Reset event when entering Standby mode.
+ *            OB_STDBY_NoRST - No reset generated when entering in STANDBY
+ *            OB_STDBY_RST - Reset generated when entering in STANDBY
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    uint32_t     Addr = 0x1FFFF800;
+    __IO uint8_t i;
+    uint16_t     pbuf[8];
+
+    FLASH->OBKEYR = FLASH_KEY1;
+    FLASH->OBKEYR = FLASH_KEY2;
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Read optionbytes */
+        for(i = 0; i < 8; i++)
+        {
+            pbuf[i] = *(uint16_t *)(Addr + 2 * i);
+        }
+
+        /* Erase optionbytes */
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_OPTER_Set;
+
+        /* Write optionbytes */
+        pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+        FLASH->CTLR |= CR_OPTPG_Set;
+        for(i = 0; i < 8; i++)
+        {
+            *(uint16_t *)(Addr + 2 * i) = pbuf[i];
+            while(FLASH->STATR & SR_BSY)
+                ;
+        }
+        FLASH->CTLR &= ~CR_OPTPG_Set;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetUserOptionByte
+ *
+ * @brief   Returns the FLASH User Option Bytes values.
+ *
+ * @return  The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ *        and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+    return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetWriteProtectionOptionByte
+ *
+ * @brief   Returns the FLASH Write Protection Option Bytes Register value.
+ *
+ * @return  The FLASH Write Protection Option Bytes Register value.
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+    return (uint32_t)(FLASH->WPR);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetReadOutProtectionStatus
+ *
+ * @brief   Checks whether the FLASH Read Out Protection Status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ITConfig
+ *
+ * @brief   Enables or disables the specified FLASH interrupts.
+ *
+ * @param   FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled.
+ *            FLASH_IT_ERROR - FLASH Error Interrupt
+ *            FLASH_IT_EOP - FLASH end of operation Interrupt
+ *          NewState - new state of the specified Flash interrupts(ENABLE or DISABLE).
+ *
+ * @return  FLASH Prefetch Buffer Status (SET or RESET).
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        FLASH->CTLR |= FLASH_IT;
+    }
+    else
+    {
+        FLASH->CTLR &= ~(uint32_t)FLASH_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetFlagStatus
+ *
+ * @brief   Checks whether the specified FLASH flag is set or not.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flag to check.
+ *            FLASH_FLAG_BSY - FLASH Busy flag
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *            FLASH_FLAG_OPTERR - FLASH Option Byte error flag
+ *
+ * @return  The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+    {
+        if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ClearFlag
+ *
+ * @brief   Clears the FLASH's pending flags.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flags to clear.
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *
+ * @return  none
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+    FLASH->STATR = FLASH_FLAG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetStatus
+ *
+ * @brief   Returns the FLASH Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetBank1Status
+ *
+ * @brief   Returns the FLASH Bank1 Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastOperation
+ *
+ * @brief   Waits for a Flash operation to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_BUSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastBank1Operation
+ *
+ * @brief   Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Unlock_Fast(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast program mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Lock_Fast
+ *
+ * @brief   Locks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Lock_Fast(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage_Fast
+ *
+ * @brief   Erases a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_ErasePage_Fast(uint32_t Page_Address)
+{
+    Page_Address &= 0xFFFFFF00;
+
+    FLASH->CTLR |= CR_PAGE_ER;
+    FLASH->ADDR = Page_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_PAGE_ER;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseBlock_32K_Fast
+ *
+ * @brief   Erases a specified FLASH Block (1Block = 32KByte).
+ *
+ * @param   Block_Address - The block address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
+{
+    Block_Address &= 0xFFFF8000;
+
+    FLASH->CTLR |= CR_BER32;
+    FLASH->ADDR = Block_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_BER32;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EraseBlock_64K_Fast
+ *
+ * @brief   Erases a specified FLASH Block (1Block = 64KByte).
+ *
+ * @param   Block_Address - The block address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address)
+{
+    Block_Address &= 0xFFFF0000;
+
+    FLASH->CTLR |= CR_BER64;
+    FLASH->ADDR = Block_Address;
+    FLASH->CTLR |= CR_STRT_Set;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_BER64;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramPage_Fast
+ *
+ * @brief   Program a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be programed.
+ *
+ * @return  none
+ */
+void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf)
+{
+    uint8_t size = 64;
+
+    Page_Address &= 0xFFFFFF00;
+
+    FLASH->CTLR |= CR_PAGE_PG;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    while(FLASH->STATR & SR_WR_BSY)
+        ;
+
+    while(size)
+    {
+        *(uint32_t *)Page_Address = *(uint32_t *)pbuf;
+        Page_Address += 4;
+        pbuf += 1;
+        size -= 1;
+        while(FLASH->STATR & SR_WR_BSY)
+            ;
+    }
+
+    FLASH->CTLR |= CR_PG_STRT;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_PAGE_PG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Enhance_Mode
+ *
+ * @brief   Read FLASH Enhance Mode
+ *
+ * @param   FLASH_Enhance_CLK -
+ *            FLASH_Enhance_SYSTEM_HALF - System clock/2
+ *            FLASH_Enhance_SYSTEM - System clock
+ *          Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void FLASH_Enhance_Mode(uint32_t FLASH_Enhance_CLK, FunctionalState NewState)
+{
+    FLASH->CTLR &= ~(1 << 25);
+    FLASH->CTLR |= FLASH_Enhance_CLK;
+
+    if(NewState)
+    {
+        FLASH->CTLR |= (1 << 24);
+    }
+    else
+    {
+        FLASH->CTLR &= ~(1 << 24);
+        FLASH->CTLR |= (1 << 22);
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_fsmc.c

@@ -0,0 +1,501 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_fsmc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the FSMC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_fsmc.h"
+#include "ch32v30x_rcc.h"
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set          ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset        ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set         ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set          ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset        ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set          ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset        ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND    ((uint32_t)0x00000008)
+
+/*********************************************************************
+ * @fn      FSMC_NORSRAMDeInit
+ *
+ * @brief   Deinitializes the FSMC NOR/SRAM Banks registers to their default
+ *        reset values.
+ *
+ * @param   FSMC_Bank-
+ *            FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1.
+ *
+ * @return  none
+ */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+    if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+    {
+        FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
+    }
+    else
+    {
+        FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
+    }
+    FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+    FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
+}
+
+/*********************************************************************
+ * @fn      FSMC_NANDDeInit
+ *
+ * @brief   Deinitializes the FSMC NAND Banks registers to their default
+ *        reset values.
+ *
+ * @param   FSMC_Bank -
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND.
+ *
+ * @return  none
+ */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        FSMC_Bank2->PCR2 = 0x00000018;
+        FSMC_Bank2->SR2 = 0x00000040;
+        FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+        FSMC_Bank2->PATT2 = 0xFCFCFCFC;
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_NORSRAMInit
+ *
+ * @brief   Initializes the FSMC NOR/SRAM Banks according to the specified
+ *        parameters in the FSMC_NORSRAMInitStruct.
+ *
+ * @param   SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef
+ *        structure that contains the configuration information for the FSMC NOR/SRAM
+ *        specified Banks.
+ *
+ * @return  none
+ */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
+{
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+        (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+        FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+        FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+        FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+        FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+        FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+        FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+        FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+        FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+        FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+        FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+        FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+    if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+    {
+        FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+    }
+
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
+        (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+        (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+        (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+        (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+        (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+        (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+        FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+
+    if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+    {
+        FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+            (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) |
+            (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+            (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+            (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+            FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+    }
+    else
+    {
+        FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_NANDInit
+ *
+ * @brief   Initializes the FSMC NAND Banks according to the specified
+ *        parameters in the FSMC_NANDInitStruct.
+ *
+ * @param   FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
+ *        structure that contains the configuration information for the FSMC
+ *        NAND specified Banks.
+ *
+ * @return  none
+ */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
+{
+    uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+    tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+             PCR_MemoryType_NAND |
+             FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+             FSMC_NANDInitStruct->FSMC_ECC |
+             FSMC_NANDInitStruct->FSMC_ECCPageSize |
+             (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) |
+             (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+
+    tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+              (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+              (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
+              (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+    tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+              (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+              (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
+              (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+    if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        FSMC_Bank2->PCR2 = tmppcr;
+        FSMC_Bank2->PMEM2 = tmppmem;
+        FSMC_Bank2->PATT2 = tmppatt;
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_NORSRAMStructInit
+ *
+ * @brief   Fills each FSMC_NORSRAMInitStruct member with its default value.
+ *
+ * @param   FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
+{
+    FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+    FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+    FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+    FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+    FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+    FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+    FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+    FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+    FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+    FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+    FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+    FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+    FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+    FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/*********************************************************************
+ * @fn      FSMC_NANDStructInit
+ *
+ * @brief   Fills each FSMC_NANDInitStruct member with its default value.
+ *
+ * @param   FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
+{
+    FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+    FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+    FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+    FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+    FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+    FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+    FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+    FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+    FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/*********************************************************************
+ * @fn      FSMC_NORSRAMCmd
+ *
+ * @brief   Enables or disables the specified NOR/SRAM Memory Bank.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1
+ *            FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2
+ *            FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3
+ *            FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4
+ *          NewState£ºENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+    }
+    else
+    {
+        FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_NANDCmd
+ *
+ * @brief   Enables or disables the specified NAND Memory Bank.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *            FSMC_Bank3_NAND - FSMC Bank3 NAND
+ *          NewStat - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        if(FSMC_Bank == FSMC_Bank2_NAND)
+        {
+            FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+        }
+    }
+    else
+    {
+        if(FSMC_Bank == FSMC_Bank2_NAND)
+        {
+            FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_NANDECCCmd
+ *
+ * @brief   Enables or disables the FSMC NAND ECC feature.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        if(FSMC_Bank == FSMC_Bank2_NAND)
+        {
+            FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+        }
+    }
+    else
+    {
+        if(FSMC_Bank == FSMC_Bank2_NAND)
+        {
+            FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_GetECC
+ *
+ * @brief   Returns the error correction code register value.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  eccval - The Error Correction Code (ECC) value.
+ */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+    uint32_t eccval = 0x00000000;
+
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        eccval = FSMC_Bank2->ECCR2;
+    }
+
+    return (eccval);
+}
+
+/*********************************************************************
+ * @fn      FSMC_ITConfig
+ *
+ * @brief   Enables or disables the specified FSMC interrupts.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          FSMC_IT - specifies the FSMC interrupt sources to be enabled or disabled.
+ *            FSMC_IT_RisingEdge - Rising edge detection interrupt.
+ *            FSMC_IT_Level - Level edge detection interrupt.
+ *            FSMC_IT_FallingEdge - Falling edge detection interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        if(FSMC_Bank == FSMC_Bank2_NAND)
+        {
+            FSMC_Bank2->SR2 |= FSMC_IT;
+        }
+    }
+    else
+    {
+        if(FSMC_Bank == FSMC_Bank2_NAND)
+        {
+            FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified FSMC flag is set or not.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          FSMC_FLAG - specifies the flag to check.
+ *            FSMC_FLAG_RisingEdge - Rising egde detection Flag.
+ *            FSMC_FLAG_Level - Level detection Flag.
+ *            FSMC_FLAG_FallingEdge - Falling egde detection Flag.
+ *            FSMC_FLAG_FEMPT - Fifo empty Flag.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  FlagStatus - The new state of FSMC_FLAG (SET or RESET).
+ */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t   tmpsr = 0x00000000;
+
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        tmpsr = FSMC_Bank2->SR2;
+    }
+
+    if((tmpsr & FSMC_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FSMC_ClearFlag
+ *
+ * @brief   Clears the FSMC's pending flags.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          FSMC_FLAG - specifies the flag to check.
+ *            FSMC_FLAG_RisingEdge - Rising egde detection Flag.
+ *            FSMC_FLAG_Level - Level detection Flag.
+ *            FSMC_FLAG_FallingEdge - Falling egde detection Flag.
+ *
+ * @return  none
+ */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        FSMC_Bank2->SR2 &= ~FSMC_FLAG;
+    }
+}
+
+/*********************************************************************
+ * @fn      FSMC_GetITStatus
+ *
+ * @brief   Checks whether the specified FSMC interrupt has occurred or not.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          FSMC_IT - specifies the FSMC interrupt source to check.
+ *            FSMC_IT_RisingEdge - Rising edge detection interrupt.
+ *            FSMC_IT_Level - Level edge detection interrupt.
+ *            FSMC_IT_FallingEdge - Falling edge detection interrupt.
+ *
+ * @return  ITStatus - The new state of FSMC_IT (SET or RESET).
+ */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        tmpsr = FSMC_Bank2->SR2;
+    }
+
+    itstatus = tmpsr & FSMC_IT;
+
+    itenable = tmpsr & (FSMC_IT >> 3);
+    if((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FSMC_ClearITPendingBit
+ *
+ * @brief   Clears the FSMC's interrupt pending bits.
+ *
+ * @param   FSMC_Bank - specifies the FSMC Bank to be used
+ *            FSMC_Bank2_NAND - FSMC Bank2 NAND
+ *          FSMC_IT - specifies the FSMC interrupt source to check.
+ *            FSMC_IT_RisingEdge - Rising edge detection interrupt.
+ *            FSMC_IT_Level - Level edge detection interrupt.
+ *            FSMC_IT_FallingEdge - Falling edge detection interrupt.
+ *
+ * @return  none
+ */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+        FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_gpio.c

@@ -0,0 +1,566 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_gpio.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the GPIO firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_rcc.h"
+
+/* MASK */
+#define ECR_PORTPINCONFIG_MASK    ((uint16_t)0xFF80)
+#define LSB_MASK                  ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK      ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK        ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK      ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK       ((uint32_t)0x00100000)
+
+/*********************************************************************
+ * @fn      GPIO_DeInit
+ *
+ * @brief   Deinitializes the GPIOx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+    if(GPIOx == GPIOA)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+    }
+    else if(GPIOx == GPIOB)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+    }
+    else if(GPIOx == GPIOC)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+    }
+    else if(GPIOx == GPIOD)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+    }
+    else if(GPIOx == GPIOE)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_AFIODeInit
+ *
+ * @brief   Deinitializes the Alternate Functions (remap, event control
+ *        and EXTI configuration) registers to their default reset values.
+ *
+ * @return  none
+ */
+void GPIO_AFIODeInit(void)
+{
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      GPIO_Init
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
+ *        contains the configuration information for the specified GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+    uint32_t tmpreg = 0x00, pinmask = 0x00;
+
+    currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+
+    if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+    {
+        currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+    }
+
+    if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+    {
+        tmpreg = GPIOx->CFGLR;
+
+        for(pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = ((uint32_t)0x01) << pinpos;
+            currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+            if(currentpin == pos)
+            {
+                pos = pinpos << 2;
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= (currentmode << pos);
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BCR = (((uint32_t)0x01) << pinpos);
+                }
+                else
+                {
+                    if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                    {
+                        GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
+                    }
+                }
+            }
+        }
+        GPIOx->CFGLR = tmpreg;
+    }
+
+    if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
+    {
+        tmpreg = GPIOx->CFGHR;
+
+        for(pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = (((uint32_t)0x01) << (pinpos + 0x08));
+            currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+
+            if(currentpin == pos)
+            {
+                pos = pinpos << 2;
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= (currentmode << pos);
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                {
+                    GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+            }
+        }
+        GPIOx->CFGHR = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_StructInit
+ *
+ * @brief   Fills each GPIO_InitStruct member with its default
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
+ *      which will be initialized.
+ *
+ * @return  none
+ */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputDataBit
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param    GPIO_Pin - specifies the port bit to read.
+ *             This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+    if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputData
+ *
+ * @brief   Reads the specified GPIO input data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  The output port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint16_t)GPIOx->INDR);
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputDataBit
+ *
+ * @brief   Reads the specified output data port bit.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to read.
+ *            This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+    if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputData
+ *
+ * @brief   Reads the specified GPIO output data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  GPIO output port pin value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint16_t)GPIOx->OUTDR);
+}
+
+/*********************************************************************
+ * @fn      GPIO_SetBits
+ *
+ * @brief   Sets the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    GPIOx->BSHR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ResetBits
+ *
+ * @brief   Clears the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    GPIOx->BCR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_WriteBit
+ *
+ * @brief   Sets or clears the selected data port bit.
+ *
+ * @param   GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ *          BitVal - specifies the value to be written to the selected bit.
+ *            Bit_SetL - to clear the port pin.
+ *            Bit_SetH - to set the port pin.
+ *
+ * @return  none
+ */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+    if(BitVal != Bit_RESET)
+    {
+        GPIOx->BSHR = GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->BCR = GPIO_Pin;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_Write
+ *
+ * @brief   Writes data to the specified GPIO data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          PortVal - specifies the value to be written to the port output data register.
+ *
+ * @return  none
+ */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
+{
+    GPIOx->OUTDR = PortVal;
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinLockConfig
+ *
+ * @brief   Locks GPIO Pins configuration registers.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint32_t tmp = 0x00010000;
+
+    tmp |= GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    GPIOx->LCKR = GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    tmp = GPIOx->LCKR;
+    tmp = GPIOx->LCKR;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputConfig
+ *
+ * @brief   Selects the GPIO pin used as Event output.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source
+ *        for Event output.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ *          GPIO_PinSource - specifies the pin for the Event output.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = AFIO->ECR;
+    tmpreg &= ECR_PORTPINCONFIG_MASK;
+    tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+    tmpreg |= GPIO_PinSource;
+    AFIO->ECR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputCmd
+ *
+ * @brief   Enables or disables the Event Output.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        AFIO->ECR |= (1 << 7);
+    }
+    else
+    {
+        AFIO->ECR &= ~(1 << 7);
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinRemapConfig
+ *
+ * @brief   Changes the mapping of the specified pin.
+ *
+ * @param   GPIO_Remap - selects the pin to remap.
+ *            GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
+ *            GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
+ *            GPIO_Remap_USART1 - USART1 Alternate Function mapping
+ *            GPIO_Remap_USART2 - USART2 Alternate Function mapping
+ *            GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
+ *            GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
+ *            GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
+ *            GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
+ *            GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
+ *            GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap_PD01 - PD01 Alternate Function mapping
+ *            GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ETH - Ethernet remapping
+ *            GPIO_Remap_CAN2 - CAN2 remapping
+ *            GPIO_Remap_MII_RMII_SEL - MII or RMII selection
+ *            GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ *            GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
+ *            GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ *        to TIM2 Internal Trigger 1 for calibration
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
+ *            GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
+ *            GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
+ *            GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
+ *            GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
+ *            GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+    uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {
+        tmpreg = AFIO->PCFR2;
+    }
+    else
+    {
+        tmpreg = AFIO->PCFR1;
+    }
+
+    tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+    tmp = GPIO_Remap & LSB_MASK;
+
+    /* Clear bit */
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {                                                                                                                   /* PCFR2 */
+        if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
+        {
+            tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
+            tmpreg &= ~tmp1;
+        }
+        else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
+        {
+            tmp1 = ((uint32_t)0x03) << tmpmask;
+            tmpreg &= ~tmp1;
+        }
+        else /* [31:0] 1bit */
+        {
+            tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
+        }
+    }
+    else
+    {                                                                                                                   /* PCFR1 */
+        if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
+        {
+            tmpreg &= DBGAFR_SWJCFG_MASK;
+            AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
+        }
+        else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
+        {
+            tmp1 = ((uint32_t)0x03) << tmpmask;
+            tmpreg &= ~tmp1;
+            tmpreg |= ~DBGAFR_SWJCFG_MASK;
+        }
+        else /* [31:0] 1bit */
+        {
+            tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
+            tmpreg |= ~DBGAFR_SWJCFG_MASK;
+        }
+    }
+
+    /* Set bit */
+    if(NewState != DISABLE)
+    {
+        tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
+    }
+
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {
+        AFIO->PCFR2 = tmpreg;
+    }
+    else
+    {
+        AFIO->PCFR1 = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_EXTILineConfig
+ *
+ * @brief   Selects the GPIO pin used as EXTI Line.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ *          GPIO_PinSource - specifies the EXTI line to be configured.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmp = 0x00;
+
+    tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/*********************************************************************
+ * @fn      GPIO_ETH_MediaInterfaceConfig
+ *
+ * @brief   Selects the Ethernet media interface.
+ *
+ * @param   GPIO_ETH_MediaInterface - specifies the Media Interface mode.
+ *            GPIO_ETH_MediaInterface_MII - MII mode
+ *            GPIO_ETH_MediaInterface_RMII - RMII mode
+ *
+ * @return  none
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+    if(GPIO_ETH_MediaInterface)
+    {
+        AFIO->PCFR1 |= (1 << 23);
+    }
+    else
+    {
+        AFIO->PCFR1 &= ~(1 << 23);
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_i2c.c

@@ -0,0 +1,972 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_i2c.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the I2C firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_i2c.h"
+#include "ch32v30x_rcc.h"
+
+/* I2C SPE mask */
+#define CTLR1_PE_Set             ((uint16_t)0x0001)
+#define CTLR1_PE_Reset           ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTLR1_START_Set          ((uint16_t)0x0100)
+#define CTLR1_START_Reset        ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTLR1_STOP_Set           ((uint16_t)0x0200)
+#define CTLR1_STOP_Reset         ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTLR1_ACK_Set            ((uint16_t)0x0400)
+#define CTLR1_ACK_Reset          ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTLR1_ENGC_Set           ((uint16_t)0x0040)
+#define CTLR1_ENGC_Reset         ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTLR1_SWRST_Set          ((uint16_t)0x8000)
+#define CTLR1_SWRST_Reset        ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTLR1_PEC_Set            ((uint16_t)0x1000)
+#define CTLR1_PEC_Reset          ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTLR1_ENPEC_Set          ((uint16_t)0x0020)
+#define CTLR1_ENPEC_Reset        ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTLR1_ENARP_Set          ((uint16_t)0x0010)
+#define CTLR1_ENARP_Reset        ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTLR1_NOSTRETCH_Set      ((uint16_t)0x0080)
+#define CTLR1_NOSTRETCH_Reset    ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTLR1_CLEAR_Mask         ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTLR2_DMAEN_Set          ((uint16_t)0x0800)
+#define CTLR2_DMAEN_Reset        ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTLR2_LAST_Set           ((uint16_t)0x1000)
+#define CTLR2_LAST_Reset         ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTLR2_FREQ_Reset         ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADD0_Set          ((uint16_t)0x0001)
+#define OADDR1_ADD0_Reset        ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_ENDUAL_Set        ((uint16_t)0x0001)
+#define OADDR2_ENDUAL_Reset      ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADD2_Reset        ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CKCFGR_FS_Set            ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CKCFGR_CCR_Set           ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask                ((uint32_t)0x07000000)
+
+/*********************************************************************
+ * @fn      I2C_DeInit
+ *
+ * @brief   Deinitializes the I2Cx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+    if(I2Cx == I2C1)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+    }
+    else
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_Init
+ *
+ * @brief   Initializes the I2Cx peripheral according to the specified
+ *        parameters in the I2C_InitStruct.
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
+ *        contains the configuration information for the specified I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
+{
+    uint16_t tmpreg = 0, freqrange = 0;
+    uint16_t result = 0x04;
+    uint32_t pclk1 = 8000000;
+
+    RCC_ClocksTypeDef rcc_clocks;
+
+    tmpreg = I2Cx->CTLR2;
+    tmpreg &= CTLR2_FREQ_Reset;
+    RCC_GetClocksFreq(&rcc_clocks);
+    pclk1 = rcc_clocks.PCLK1_Frequency;
+    freqrange = (uint16_t)(pclk1 / 1000000);
+    tmpreg |= freqrange;
+    I2Cx->CTLR2 = tmpreg;
+
+    I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    tmpreg = 0;
+
+    if(I2C_InitStruct->I2C_ClockSpeed <= 100000)
+    {
+        result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+
+        if(result < 0x04)
+        {
+            result = 0x04;
+        }
+
+        tmpreg |= result;
+        I2Cx->RTR = freqrange + 1;
+    }
+    else
+    {
+        if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+        {
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+        }
+        else
+        {
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+            result |= I2C_DutyCycle_16_9;
+        }
+
+        if((result & CKCFGR_CCR_Set) == 0)
+        {
+            result |= (uint16_t)0x0001;
+        }
+
+        tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
+        I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+    }
+
+    I2Cx->CKCFGR = tmpreg;
+    I2Cx->CTLR1 |= CTLR1_PE_Set;
+
+    tmpreg = I2Cx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+    I2Cx->CTLR1 = tmpreg;
+
+    I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/*********************************************************************
+ * @fn      I2C_StructInit
+ *
+ * @brief   Fills each I2C_InitStruct member with its default value.
+ *
+ * @param   I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
+{
+    I2C_InitStruct->I2C_ClockSpeed = 5000;
+    I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+    I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+    I2C_InitStruct->I2C_OwnAddress1 = 0;
+    I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+    I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/*********************************************************************
+ * @fn      I2C_Cmd
+ *
+ * @brief   Enables or disables the specified I2C peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_PE_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMACmd
+ *
+ * @brief   Enables or disables the specified I2C DMA requests.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMALastTransferCmd
+ *
+ * @brief   Specifies if the next DMA transfer will be the last one.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= CTLR2_LAST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_LAST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTART
+ *
+ * @brief   Generates I2Cx communication START condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_START_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_START_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTOP
+ *
+ * @brief   Generates I2Cx communication STOP condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_STOP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_STOP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_AcknowledgeConfig
+ *
+ * @brief   Enables or disables the specified I2C acknowledge feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ACK_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_OwnAddress2Config
+ *
+ * @brief   Configures the specified I2C own address2.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the 7bit I2C own address2.
+ *
+ * @return  none
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = I2Cx->OADDR2;
+    tmpreg &= OADDR2_ADD2_Reset;
+    tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+    I2Cx->OADDR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      I2C_DualAddressCmd
+ *
+ * @brief   Enables or disables the specified I2C dual addressing mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
+    }
+    else
+    {
+        I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GeneralCallCmd
+ *
+ * @brief   Enables or disables the specified I2C general call feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENGC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_ITConfig
+ *
+ * @brief   Enables or disables the specified I2C interrupts.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
+ *            I2C_IT_BUF - Buffer interrupt mask.
+ *            I2C_IT_EVT - Event interrupt mask.
+ *            I2C_IT_ERR - Error interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= I2C_IT;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SendData
+ *
+ * @brief   Sends a data byte through the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Data - Byte to be transmitted.
+ *
+ * @return  none
+ */
+void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+    I2Cx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
+{
+    return (uint8_t)I2Cx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      I2C_Send7bitAddress
+ *
+ * @brief   Transmits the address byte to select the slave device.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the slave address which will be transmitted.
+ *          I2C_Direction - specifies whether the I2C device will be a
+ *        Transmitter or a Receiver.
+ *            I2C_Direction_Transmitter - Transmitter mode.
+ *            I2C_Direction_Receiver - Receiver mode.
+ *
+ * @return  none
+ */
+void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+    if(I2C_Direction != I2C_Direction_Transmitter)
+    {
+        Address |= OADDR1_ADD0_Set;
+    }
+    else
+    {
+        Address &= OADDR1_ADD0_Reset;
+    }
+
+    I2Cx->DATAR = Address;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReadRegister
+ *
+ * @brief   Reads the specified I2C register and returns its value.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_Register - specifies the register to read.
+ *            I2C_Register_CTLR1.
+ *            I2C_Register_CTLR2.
+ *            I2C_Register_OADDR1.
+ *            I2C_Register_OADDR2.
+ *            I2C_Register_DATAR.
+ *            I2C_Register_STAR1.
+ *            I2C_Register_STAR2.
+ *            I2C_Register_CKCFGR.
+ *            I2C_Register_RTR.
+ *
+ * @return  none
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)I2Cx;
+    tmp += I2C_Register;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      I2C_SoftwareResetCmd
+ *
+ * @brief   Enables or disables the specified I2C software reset.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_SWRST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_NACKPositionConfig
+ *
+ * @brief   Selects the specified I2C NACK position in master receiver mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_NACKPosition - specifies the NACK position.
+ *            I2C_NACKPosition_Next - indicates that the next byte will be
+ *        the last received byte.
+ *            I2C_NACKPosition_Current - indicates that current byte is the
+ *        last received byte.
+ *
+ * @return  none
+ */
+void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
+{
+    if(I2C_NACKPosition == I2C_NACKPosition_Next)
+    {
+        I2Cx->CTLR1 |= I2C_NACKPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_NACKPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SMBusAlertConfig
+ *
+ * @brief   Drives the SMBusAlert pin high or low for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_SMBusAlert - specifies SMBAlert pin level.
+ *            I2C_SMBusAlert_Low - SMBAlert pin driven low.
+ *            I2C_SMBusAlert_High - SMBAlert pin driven high.
+ *
+ * @return  none
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
+{
+    if(I2C_SMBusAlert == I2C_SMBusAlert_Low)
+    {
+        I2Cx->CTLR1 |= I2C_SMBusAlert_Low;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_SMBusAlert_High;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_TransmitPEC
+ *
+ * @brief   Enables or disables the specified I2C PEC transfer.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_PEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_PECPositionConfig
+ *
+ * @brief   Selects the specified I2C PEC position.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_PECPosition - specifies the PEC position.
+ *            I2C_PECPosition_Next - indicates that the next byte is PEC.
+ *            I2C_PECPosition_Current - indicates that current byte is PEC.
+ *
+ * @return  none
+ */
+void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
+{
+    if(I2C_PECPosition == I2C_PECPosition_Next)
+    {
+        I2Cx->CTLR1 |= I2C_PECPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_PECPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CalculatePEC
+ *
+ * @brief   Enables or disables the PEC value calculation of the transferred bytes.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GetPEC
+ *
+ * @brief   Returns the PEC value for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
+{
+    return ((I2Cx->STAR2) >> 8);
+}
+
+/*********************************************************************
+ * @fn      I2C_ARPCmd
+ *
+ * @brief   Enables or disables the specified I2C ARP.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *            NewState - ENABLE or DISABLE.
+ *
+ * @return  The PEC value.
+ */
+void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENARP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_StretchClockCmd
+ *
+ * @brief   Enables or disables the specified I2C Clock stretching.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState == DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_FastModeDutyCycleConfig
+ *
+ * @brief   Selects the specified I2C fast mode duty cycle.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_DutyCycle - specifies the fast mode duty cycle.
+ *            I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
+ *            I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
+ *
+ * @return  none
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
+{
+    if(I2C_DutyCycle != I2C_DutyCycle_16_9)
+    {
+        I2Cx->CKCFGR &= I2C_DutyCycle_2;
+    }
+    else
+    {
+        I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CheckEvent
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_EVENT: specifies the event to be checked.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
+ *             I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
+ *             I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
+ *             I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
+ *             I2C_EVENT_MASTER_MODE_SELECT - EV5.
+ *             I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
+ *             I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
+ *
+ * @return  none
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
+{
+    uint32_t    lastevent = 0;
+    uint32_t    flag1 = 0, flag2 = 0;
+    ErrorStatus status = ERROR;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+
+    lastevent = (flag1 | flag2) & FLAG_Mask;
+
+    if((lastevent & I2C_EVENT) == I2C_EVENT)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetLastEvent
+ *
+ * @brief   Returns the last I2Cx Event.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+    lastevent = (flag1 | flag2) & FLAG_Mask;
+
+    return lastevent;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetFlagStatus
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to check.
+ *            I2C_FLAG_DUALF - Dual flag (Slave mode).
+ *            I2C_FLAG_SMBHOST - SMBus host header (Slave mode).
+ *            I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode).
+ *            I2C_FLAG_GENCALL - General call header flag (Slave mode).
+ *            I2C_FLAG_TRA - Transmitter/Receiver flag.
+ *            I2C_FLAG_BUSY - Bus busy flag.
+ *            I2C_FLAG_MSL - Master/Slave flag.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *            I2C_FLAG_TXE - Data register empty flag (Transmitter).
+ *            I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
+ *            I2C_FLAG_STOPF - Stop detection flag (Slave mode).
+ *            I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_FLAG_BTF - Byte transfer finished flag.
+ *            I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
+ *        Address matched flag (Slave mode)"ENDA".
+ *            I2C_FLAG_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus    bitstatus = RESET;
+    __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+    i2cxbase = (uint32_t)I2Cx;
+    i2creg = I2C_FLAG >> 28;
+    I2C_FLAG &= FLAG_Mask;
+
+    if(i2creg != 0)
+    {
+        i2cxbase += 0x14;
+    }
+    else
+    {
+        I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+        i2cxbase += 0x18;
+    }
+
+    if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearFlag
+ *
+ * @brief   Clears the I2Cx's pending flags.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to clear.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *
+ * @return  none
+ */
+void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_FLAG & FLAG_Mask;
+    I2Cx->STAR1 = (uint16_t)~flagpos;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetITStatus
+ *
+ * @brief   Checks whether the specified I2C interrupt has occurred or not.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          II2C_IT - specifies the interrupt source to check.
+ *            I2C_IT_SMBALERT - SMBus Alert flag.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_IT_PECERR - PEC error in reception flag.
+ *            I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure flag.
+ *            I2C_IT_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_IT_BERR - Bus error flag.
+ *            I2C_IT_TXE - Data register empty flag (Transmitter).
+ *            I2C_IT_RXNE - Data register not empty (Receiver) flag.
+ *            I2C_IT_STOPF - Stop detection flag (Slave mode).
+ *            I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_IT_BTF - Byte transfer finished flag.
+ *            I2C_IT_ADDR - Address sent flag (Master mode) "ADSL"  Address matched
+ *        flag (Slave mode)"ENDAD".
+ *            I2C_IT_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2));
+    I2C_IT &= FLAG_Mask;
+
+    if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearITPendingBit
+ *
+ * @brief   Clears the I2Cx interrupt pending bits.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the interrupt pending bit to clear.
+ *            I2C_IT_SMBALERT - SMBus Alert interrupt.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error interrupt.
+ *            I2C_IT_PECERR - PEC error in reception  interrupt.
+ *            I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure interrupt.
+ *            I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
+ *            I2C_IT_BERR - Bus error interrupt.
+ *
+ * @return  none
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_IT & FLAG_Mask;
+    I2Cx->STAR1 = (uint16_t)~flagpos;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_iwdg.c

@@ -0,0 +1,120 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_iwdg.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the IWDG firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_iwdg.h"
+
+/* CTLR register bit mask */
+#define CTLR_KEY_Reload    ((uint16_t)0xAAAA)
+#define CTLR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/*********************************************************************
+ * @fn      IWDG_WriteAccessCmd
+ *
+ * @brief   Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
+ *
+ * @param   WDG_WriteAccess - new state of write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
+ *        and IWDG_RLDR registers.
+ *
+ * @return  none
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+    IWDG->CTLR = IWDG_WriteAccess;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetPrescaler
+ *
+ * @brief   Sets IWDG Prescaler value.
+ *
+ * @param   IWDG_Prescaler - specifies the IWDG Prescaler value.
+ *             IWDG_Prescaler_4 - IWDG prescaler set to 4.
+ *             IWDG_Prescaler_8 - IWDG prescaler set to 8.
+ *             IWDG_Prescaler_16 - IWDG prescaler set to 16.
+ *             IWDG_Prescaler_32 - IWDG prescaler set to 32.
+ *             IWDG_Prescaler_64 - IWDG prescaler set to 64.
+ *             IWDG_Prescaler_128 - IWDG prescaler set to 128.
+ *             IWDG_Prescaler_256 - IWDG prescaler set to 256.
+ *
+ * @return  none
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+    IWDG->PSCR = IWDG_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetReload
+ *
+ * @brief   Sets IWDG Reload value.
+ *
+ * @param   Reload - specifies the IWDG Reload value.
+ *            This parameter must be a number between 0 and 0x0FFF.
+ *
+ * @return  none
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+    IWDG->RLDR = Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_ReloadCounter
+ *
+ * @brief   Reloads IWDG counter with value defined in the reload register.
+ *
+ * @return  none
+ */
+void IWDG_ReloadCounter(void)
+{
+    IWDG->CTLR = CTLR_KEY_Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_Enable
+ *
+ * @brief   Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
+ *
+ * @return  none
+ */
+void IWDG_Enable(void)
+{
+    IWDG->CTLR = CTLR_KEY_Enable;
+}
+
+/*********************************************************************
+ * @fn      IWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the specified IWDG flag is set or not.
+ *
+ * @param   IWDG_FLAG - specifies the flag to check.
+ *            IWDG_FLAG_PVU - Prescaler Value Update on going.
+ *            IWDG_FLAG_RVU - Reload Value Update on going.
+ *
+ * @return  none
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_misc.c

@@ -0,0 +1,107 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_misc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the miscellaneous firmware functions .
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x_misc.h"
+
+__IO uint32_t NVIC_Priority_Group = 0;
+
+/*********************************************************************
+ * @fn      NVIC_PriorityGroupConfig
+ *
+ * @brief   Configures the priority grouping - pre-emption priority and subpriority.
+ *
+ * @param   NVIC_PriorityGroup - specifies the priority grouping bits length.
+ *            NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
+ *                                   4 bits for subpriority
+ *            NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
+ *                                   3 bits for subpriority
+ *            NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
+ *                                   2 bits for subpriority
+ *            NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
+ *                                   1 bits for subpriority
+ *            NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
+ *                                   0 bits for subpriority
+ *
+ * @return  none
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+    NVIC_Priority_Group = NVIC_PriorityGroup;
+}
+
+/*********************************************************************
+ * @fn      NVIC_Init
+ *
+ * @brief   Initializes the NVIC peripheral according to the specified parameters in
+ *        the NVIC_InitStruct.
+ *
+ * @param   NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
+ *        configuration information for the specified NVIC peripheral.
+ *
+ * @return  none
+ */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
+{
+    uint8_t tmppre = 0;
+
+    if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
+    {
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
+        {
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
+        }
+        else
+        {
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
+        }
+        else
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
+        }
+        else
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
+    {
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
+    }
+
+    if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+    else
+    {
+        NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_opa.c

@@ -0,0 +1,84 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_opa.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the OPA firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+***************************************************************************************/
+#include "ch32v30x_opa.h"
+
+#define OPA_MASK         ((uint32_t)0x000F)
+#define OPA_Total_NUM    4
+
+/*********************************************************************
+ * @fn      OPA_DeInit
+ *
+ * @brief   Deinitializes the OPA peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none
+ */
+void OPA_DeInit(void)
+{
+    OPA->CR = 0;
+}
+
+/*********************************************************************
+ * @fn      OPA_Init
+ *
+ * @brief   Initializes the OPA peripheral according to the specified
+ *        parameters in the OPA_InitStruct.
+ *
+ * @param   OPA_InitStruct - pointer to a OPA_InitTypeDef structure
+ *
+ * @return  none
+ */
+void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
+{
+    uint32_t tmp = 0;
+    tmp = OPA->CR;
+    tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
+    tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
+    OPA->CR = tmp;
+}
+
+/*********************************************************************
+ * @fn      OPA_StructInit
+ *
+ * @brief   Fills each OPA_StructInit member with its reset value.
+ *
+ * @param   OPA_StructInit - pointer to a OPA_InitTypeDef structure
+ *
+ * @return  none
+ */
+void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
+{
+    OPA_InitStruct->Mode = OUT_IO;
+    OPA_InitStruct->PSEL = CHP0;
+    OPA_InitStruct->NSEL = CHN0;
+    OPA_InitStruct->OPA_NUM = OPA1;
+}
+
+/*********************************************************************
+ * @fn      OPA_Cmd
+ *
+ * @brief   Enables or disables the specified OPA peripheral.
+ *
+ * @param   OPA_NUM - Select OPA
+ *            NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
+{
+    if(NewState == ENABLE)
+    {
+        OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
+    }
+    else
+    {
+        OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
+    }
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_pwr.c

@@ -0,0 +1,321 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_pwr.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the PWR firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+********************************************************************************/
+#include "ch32v30x_pwr.h"
+#include "ch32v30x_rcc.h"
+
+/* PWR registers bit mask */
+/* CTLR register bit mask */
+#define CTLR_DS_MASK     ((uint32_t)0xFFFFFFFC)
+#define CTLR_PLS_MASK    ((uint32_t)0xFFFFFF1F)
+
+/*********************************************************************
+ * @fn      PWR_DeInit
+ *
+ * @brief   Deinitializes the PWR peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none
+ */
+void PWR_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      PWR_BackupAccessCmd
+ *
+ * @brief   Enables or disables access to the RTC and backup registers.
+ *
+ * @param   NewState - new state of the access to the RTC and backup registers,
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CTLR |= (1 << 8);
+    }
+    else
+    {
+        PWR->CTLR &= ~(1 << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_PVDCmd
+ *
+ * @brief   Enables or disables the Power Voltage Detector(PVD).
+ *
+ * @param   NewState - new state of the PVD(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CTLR |= (1 << 4);
+    }
+    else
+    {
+        PWR->CTLR &= ~(1 << 4);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_PVDLevelConfig
+ *
+ * @brief   Configures the voltage threshold detected by the Power Voltage
+ *        Detector(PVD).
+ *
+ * @param   PWR_PVDLevel - specifies the PVD detection level
+ *            PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
+ *            PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
+ *            PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
+ *            PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
+ *            PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
+ *            PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
+ *            PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
+ *            PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
+ *
+ * @return  none
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_PLS_MASK;
+    tmpreg |= PWR_PVDLevel;
+    PWR->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      PWR_WakeUpPinCmd
+ *
+ * @brief   Enables or disables the WakeUp Pin functionality.
+ *
+ * @param   NewState - new state of the WakeUp Pin functionality
+ *        (ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CSR |= (1 << 8);
+    }
+    else
+    {
+        PWR->CSR &= ~(1 << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTOPMode
+ *
+ * @brief   Enters STOP mode.
+ *
+ * @param   PWR_Regulator - specifies the regulator state in STOP mode.
+ *            PWR_Regulator_ON - STOP mode with regulator ON
+ *            PWR_Regulator_LowPower - STOP mode with regulator in low power mode
+ *          PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
+ *            PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
+ *            PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
+ *
+ * @return  none
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_DS_MASK;
+    tmpreg |= PWR_Regulator;
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+    {
+        __WFI();
+    }
+    else
+    {
+        __WFE();
+    }
+
+    NVIC->SCTLR &= ~(1 << 2);
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode
+ *
+ * @brief   Enters STANDBY mode.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+    PWR->CTLR |= PWR_CTLR_CWUF;
+    PWR->CTLR |= PWR_CTLR_PDDS;
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_GetFlagStatus
+ *
+ * @brief   Checks whether the specified PWR flag is set or not.
+ *
+ * @param   PWR_FLAG - specifies the flag to check.
+ *            PWR_FLAG_WU - Wake Up flag
+ *            PWR_FLAG_SB - StandBy flag
+ *            PWR_FLAG_PVDO - PVD Output
+ *
+ * @return  none
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      PWR_ClearFlag
+ *
+ * @brief   Clears the PWR's pending flags.
+ *
+ * @param   PWR_FLAG - specifies the flag to clear.
+ *            PWR_FLAG_WU - Wake Up flag
+ *            PWR_FLAG_SB - StandBy flag
+ *
+ * @return  none
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+    PWR->CTLR |= PWR_FLAG << 2;
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function on.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+    //2K+30K in standby w power.
+    tmpreg |= (0x1 << 16) | (0x1 << 17);
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM_LV
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function and LV mode on.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM_LV(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+    //2K+30K in standby power.
+    tmpreg |= (0x1 << 16) | (0x1 << 17);
+    //2K+30K in standby LV .
+    tmpreg |= (0x1 << 20);
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM_VBAT_EN
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function on (VBAT Enable).
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+    //2K+30K in standby power (VBAT Enable).
+    tmpreg |= (0x1 << 18) | (0x1 << 19);
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
+ *
+ * @brief   Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+
+    tmpreg |= PWR_CTLR_CWUF;
+    tmpreg |= PWR_CTLR_PDDS;
+
+    //2K+30K in standby power (VBAT Enable).
+    tmpreg |= (0x1 << 18) | (0x1 << 19);
+    //2K+30K in standby LV .
+    tmpreg |= (0x1 << 20);
+
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_rcc.c

@@ -0,0 +1,1424 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_rcc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RCC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_rcc.h"
+
+/* RCC registers bit address in the alias region */
+#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
+
+/* BDCTLR Register */
+#define BDCTLR_OFFSET              (RCC_OFFSET + 0x20)
+
+/* RCC registers bit mask */
+
+/* CTLR register bit mask */
+#define CTLR_HSEBYP_Reset          ((uint32_t)0xFFFBFFFF)
+#define CTLR_HSEBYP_Set            ((uint32_t)0x00040000)
+#define CTLR_HSEON_Reset           ((uint32_t)0xFFFEFFFF)
+#define CTLR_HSEON_Set             ((uint32_t)0x00010000)
+#define CTLR_HSITRIM_Mask          ((uint32_t)0xFFFFFF07)
+
+#define CFGR0_PLL_Mask             ((uint32_t)0xFFC0FFFF) /* 103 */
+#define CFGR0_PLL_Mask_1           ((uint32_t)0xFFC2FFFF) /* 107 */
+
+#define CFGR0_PLLMull_Mask         ((uint32_t)0x003C0000)
+#define CFGR0_PLLSRC_Mask          ((uint32_t)0x00010000)
+#define CFGR0_PLLXTPRE_Mask        ((uint32_t)0x00020000)
+#define CFGR0_SWS_Mask             ((uint32_t)0x0000000C)
+#define CFGR0_SW_Mask              ((uint32_t)0xFFFFFFFC)
+#define CFGR0_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
+#define CFGR0_HPRE_Set_Mask        ((uint32_t)0x000000F0)
+#define CFGR0_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
+#define CFGR0_PPRE1_Set_Mask       ((uint32_t)0x00000700)
+#define CFGR0_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
+#define CFGR0_PPRE2_Set_Mask       ((uint32_t)0x00003800)
+#define CFGR0_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
+#define CFGR0_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
+
+/* RSTSCKR register bit mask */
+#define RSTSCKR_RMVF_Set           ((uint32_t)0x01000000)
+
+/* CFGR2 register bit mask */
+#define CFGR2_PREDIV1SRC           ((uint32_t)0x00010000)
+#define CFGR2_PREDIV1              ((uint32_t)0x0000000F)
+#define CFGR2_PREDIV2              ((uint32_t)0x000000F0)
+#define CFGR2_PLL2MUL              ((uint32_t)0x00000F00)
+#define CFGR2_PLL3MUL              ((uint32_t)0x0000F000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                  ((uint8_t)0x1F)
+
+/* INTR register byte 2 (Bits[15:8]) base address */
+#define INTR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
+
+/* INTR register byte 3 (Bits[23:16]) base address */
+#define INTR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
+
+/* CFGR0 register byte 4 (Bits[31:24]) base address */
+#define CFGR0_BYTE4_ADDRESS        ((uint32_t)0x40021007)
+
+/* BDCTLR register base address */
+#define BDCTLR_ADDRESS             (PERIPH_BASE + BDCTLR_OFFSET)
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/*********************************************************************
+ * @fn      RCC_DeInit
+ *
+ * @brief   Resets the RCC clock configuration to the default reset state.
+ *
+ * @return  none
+ */
+void RCC_DeInit(void)
+{
+    RCC->CTLR |= (uint32_t)0x00000001;
+
+#ifdef CH32V30x_D8C
+    RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+#else
+    RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+#endif
+
+    RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+    RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+    RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+
+#ifdef CH32V30x_D8C
+    RCC->CTLR &= (uint32_t)0xEBFFFFFF;
+    RCC->INTR = 0x00FF0000;
+    RCC->CFGR2 = 0x00000000;
+#else
+    RCC->INTR = 0x009F0000;
+#endif
+}
+
+/*********************************************************************
+ * @fn      RCC_HSEConfig
+ *
+ * @brief   Configures the External High Speed oscillator (HSE).
+ *
+ * @param   RCC_HSE -
+ *            RCC_HSE_OFF - HSE oscillator OFF.
+ *            RCC_HSE_ON - HSE oscillator ON.
+ *            RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+    RCC->CTLR &= CTLR_HSEON_Reset;
+    RCC->CTLR &= CTLR_HSEBYP_Reset;
+
+    switch(RCC_HSE)
+    {
+        case RCC_HSE_ON:
+            RCC->CTLR |= CTLR_HSEON_Set;
+            break;
+
+        case RCC_HSE_Bypass:
+            RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_WaitForHSEStartUp
+ *
+ * @brief   Waits for HSE start-up.
+ *
+ * @return  SUCCESS - HSE oscillator is stable and ready to use.
+ *                  ERROR - HSE oscillator not yet ready.
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+    __IO uint32_t StartUpCounter = 0;
+
+    ErrorStatus status = ERROR;
+    FlagStatus  HSEStatus = RESET;
+
+    do
+    {
+        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+        StartUpCounter++;
+    } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+    if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    return (status);
+}
+
+/*********************************************************************
+ * @fn      RCC_AdjustHSICalibrationValue
+ *
+ * @brief   Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ *
+ * @param   HSICalibrationValue - specifies the calibration trimming value.
+ *                    This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CTLR;
+    tmpreg &= CTLR_HSITRIM_Mask;
+    tmpreg |= (uint32_t)HSICalibrationValue << 3;
+    RCC->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSICmd
+ *
+ * @brief   Enables or disables the Internal High Speed oscillator (HSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 0);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLConfig
+ *
+ * @brief   Configures the PLL clock source and multiplication factor.
+ *
+ * @param   RCC_PLLSource - specifies the PLL entry clock source.
+ *            RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *            RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock
+ *        entry.
+ *          RCC_PLLMul - specifies the PLL multiplication factor.
+ *            This parameter can be RCC_PLLMul_x where x:[2,16].
+ *            For CH32V307 -
+ *              RCC_PLLMul_18_EXTEN
+ *              RCC_PLLMul_3_EXTEN
+ *              RCC_PLLMul_4_EXTEN
+ *              RCC_PLLMul_5_EXTEN
+ *              RCC_PLLMul_6_EXTEN
+ *              RCC_PLLMul_7_EXTEN
+ *              RCC_PLLMul_8_EXTEN
+ *              RCC_PLLMul_9_EXTEN
+ *              RCC_PLLMul_10_EXTEN
+ *              RCC_PLLMul_11_EXTEN
+ *              RCC_PLLMul_12_EXTEN
+ *              RCC_PLLMul_13_EXTEN
+ *              RCC_PLLMul_14_EXTEN
+ *              RCC_PLLMul_6_5_EXTEN
+ *              RCC_PLLMul_15_EXTEN
+ *              RCC_PLLMul_16_EXTEN
+ *            For other CH32V30x -
+ *              RCC_PLLMul_2
+ *              RCC_PLLMul_3
+ *              RCC_PLLMul_4
+ *              RCC_PLLMul_5
+ *              RCC_PLLMul_6
+ *              RCC_PLLMul_7
+ *              RCC_PLLMul_8
+ *              RCC_PLLMul_9
+ *              RCC_PLLMul_10
+ *              RCC_PLLMul_11
+ *              RCC_PLLMul_12
+ *              RCC_PLLMul_13
+ *              RCC_PLLMul_14
+ *              RCC_PLLMul_15
+ *              RCC_PLLMul_16
+ *              RCC_PLLMul_18
+ *
+ * @return  none
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+
+    if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14))
+    { /* for other CH32V30x */
+        tmpreg &= CFGR0_PLL_Mask;
+    }
+    else
+    { /* for CH32V307 */
+        tmpreg &= CFGR0_PLL_Mask_1;
+    }
+
+    tmpreg |= RCC_PLLSource | RCC_PLLMul;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLCmd
+ *
+ * @brief   Enables or disables the PLL.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 24);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 24);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_SYSCLKConfig
+ *
+ * @brief   Configures the system clock (SYSCLK).
+ *
+ * @param   RCC_SYSCLKSource - specifies the clock source used as system clock.
+ *            RCC_SYSCLKSource_HSI - HSI selected as system clock.
+ *            RCC_SYSCLKSource_HSE - HSE selected as system clock.
+ *            RCC_SYSCLKSource_PLLCLK - PLL selected as system clock.
+ *
+ * @return  none
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_SW_Mask;
+    tmpreg |= RCC_SYSCLKSource;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetSYSCLKSource
+ *
+ * @brief   Returns the clock source used as system clock.
+ *
+ * @return  0x00 - HSI used as system clock.
+ *          0x04 - HSE used as system clock.
+ *          0x08 - PLL used as system clock.
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+    return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
+}
+
+/*********************************************************************
+ * @fn      RCC_HCLKConfig
+ *
+ * @brief   Configures the AHB clock (HCLK).
+ *
+ * @param   RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
+ *        the system clock (SYSCLK).
+ *            RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
+ *            RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
+ *            RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
+ *            RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
+ *            RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
+ *            RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
+ *            RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
+ *            RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
+ *            RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512.
+ *
+ * @return  none
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_HPRE_Reset_Mask;
+    tmpreg |= RCC_SYSCLK;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK1Config
+ *
+ * @brief   Configures the Low Speed APB clock (PCLK1).
+ *
+ * @param   RCC_HCLK - defines the APB1 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PPRE1_Reset_Mask;
+    tmpreg |= RCC_HCLK;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK2Config
+ *
+ * @brief   Configures the High Speed APB clock (PCLK2).
+ *
+ * @param   RCC_HCLK - defines the APB2 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PPRE2_Reset_Mask;
+    tmpreg |= RCC_HCLK << 3;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_ITConfig
+ *
+ * @brief   Enables or disables the specified RCC interrupts.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt sources to be enabled or disabled.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT;
+    }
+    else
+    {
+        *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKConfig
+ *
+ * @brief   Configures the ADC clock (ADCCLK).
+ *
+ * @param   RCC_PCLK2 - defines the ADC clock divider. This clock is derived from
+ *        the APB2 clock (PCLK2).
+ *          RCC_PCLK2_Div2 - ADC clock = PCLK2/2.
+ *          RCC_PCLK2_Div4 - ADC clock = PCLK2/4.
+ *          RCC_PCLK2_Div6 - ADC clock = PCLK2/6.
+ *          RCC_PCLK2_Div8 - ADC clock = PCLK2/8.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_ADCPRE_Reset_Mask;
+    tmpreg |= RCC_PCLK2;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_LSEConfig
+ *
+ * @brief   Configures the External Low Speed oscillator (LSE).
+ *
+ * @param   RCC_LSE - specifies the new state of the LSE.
+ *            RCC_LSE_OFF - LSE oscillator OFF.
+ *            RCC_LSE_ON - LSE oscillator ON.
+ *            RCC_LSE_Bypass - LSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+    *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF;
+    *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF;
+
+    switch(RCC_LSE)
+    {
+        case RCC_LSE_ON:
+            *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON;
+            break;
+
+        case RCC_LSE_Bypass:
+            *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_LSICmd
+ *
+ * @brief   Enables or disables the Internal Low Speed oscillator (LSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->RSTSCKR |= (1 << 0);
+    }
+    else
+    {
+        RCC->RSTSCKR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKConfig
+ *
+ * @brief   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ *
+ * @param   RCC_RTCCLKSource - specifies the RTC clock source.
+ *            RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
+ *            RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
+ *            RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+    RCC->BDCTLR |= RCC_RTCCLKSource;
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKCmd
+ *
+ * @brief   This function must be used only after the RTC clock was selected
+ *        using the RCC_RTCCLKConfig function.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->BDCTLR |= (1 << 15);
+    }
+    else
+    {
+        RCC->BDCTLR &= ~(1 << 15);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_GetClocksFreq
+ *
+ * @brief   The result of this function could be not correct when using
+ *        fractional value for HSE crystal.
+ *
+ * @param   RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
+ *        the clocks frequencies.
+ *
+ * @return  none
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0;
+
+    tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
+
+    switch(tmp)
+    {
+        case 0x00:
+            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+            break;
+
+        case 0x04:
+            RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+            break;
+
+        case 0x08:
+            pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
+            pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
+
+            pllmull = (pllmull >> 18) + 2;
+
+            if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14))
+            { /* for other CH32V30x */
+                if(pllmull == 17)
+                    pllmull = 18;
+            }
+            else
+            { /* for CH32V307 */
+                if(pllmull == 2)
+                    pllmull = 18;
+                if(pllmull == 15)
+                {
+                    pllmull = 13; /* *6.5 */
+                    Pll_6_5 = 1;
+                }
+                if(pllmull == 16)
+                    pllmull = 15;
+                if(pllmull == 17)
+                    pllmull = 16;
+            }
+
+            if(pllsource == 0x00)
+            {
+                if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE)
+                {
+                    RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+                }
+            }
+            else
+            {
+                if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
+                {
+                    RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+                }
+            }
+
+            if(Pll_6_5 == 1)
+                RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2);
+
+            break;
+
+        default:
+            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+            break;
+    }
+
+    tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
+    tmp = tmp >> 8;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
+    tmp = tmp >> 11;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
+    tmp = tmp >> 14;
+    presc = ADCPrescTable[tmp];
+    RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphClockCmd
+ *
+ * @brief   Enables or disables the AHB peripheral clock.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
+ *            RCC_AHBPeriph_DMA1.
+ *            RCC_AHBPeriph_DMA2.
+ *            RCC_AHBPeriph_SRAM.
+ *            RCC_AHBPeriph_CRC.
+ *            RCC_AHBPeriph_FSMC
+ *            RCC_AHBPeriph_RNG
+ *            RCC_AHBPeriph_SDIO
+ *            RCC_AHBPeriph_USBHS
+ *            RCC_AHBPeriph_OTG_FS
+ *            RCC_AHBPeriph_DVP
+ *            RCC_AHBPeriph_ETH_MAC
+ *            RCC_AHBPeriph_ETH_MAC_Tx
+ *            RCC_AHBPeriph_ETH_MAC_Rx
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->AHBPCENR |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBPCENR &= ~RCC_AHBPeriph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphClockCmd
+ *
+ * @brief   Enables or disables the High Speed APB (APB2) peripheral clock.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *            RCC_APB2Periph_TIM9
+ *            RCC_APB2Periph_TIM10
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB2PCENR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PCENR &= ~RCC_APB2Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphClockCmd
+ *
+ * @brief   Enables or disables the Low Speed APB (APB1) peripheral clock.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_TIM5
+ *            RCC_APB1Periph_TIM6
+ *            RCC_APB1Periph_TIM7
+ *            RCC_APB1Periph_UART6
+ *            RCC_APB1Periph_UART7
+ *            RCC_APB1Periph_UART8
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_SPI3.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_UART4
+ *            RCC_APB1Periph_UART5
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB1PCENR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PCENR &= ~RCC_APB1Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphResetCmd
+ *
+ * @brief   Forces or releases High Speed APB (APB2) peripheral reset.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to reset.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *            RCC_APB2Periph_TIM9
+ *            RCC_APB2Periph_TIM10
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB2PRSTR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PRSTR &= ~RCC_APB2Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphResetCmd
+ *
+ * @brief   Forces or releases Low Speed APB (APB1) peripheral reset.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to reset.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_TIM5
+ *            RCC_APB1Periph_TIM6
+ *            RCC_APB1Periph_TIM7
+ *            RCC_APB1Periph_UART6
+ *            RCC_APB1Periph_UART7
+ *            RCC_APB1Periph_UART8
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_SPI3.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_UART4
+ *            RCC_APB1Periph_UART5
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB1PRSTR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PRSTR &= ~RCC_APB1Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_BackupResetCmd
+ *
+ * @brief   Forces or releases the Backup domain reset.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->BDCTLR |= (1 << 16);
+    }
+    else
+    {
+        RCC->BDCTLR &= ~(1 << 16);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_ClockSecuritySystemCmd
+ *
+ * @brief   Enables or disables the Clock Security System.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 19);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 19);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_MCOConfig
+ *
+ * @brief   Selects the clock source to output on MCO pin.
+ *
+ * @param   RCC_MCO - specifies the clock source to output.
+ *            RCC_MCO_NoClock - No clock selected.
+ *            RCC_MCO_SYSCLK - System clock selected.
+ *            RCC_MCO_HSI - HSI oscillator clock selected.
+ *            RCC_MCO_HSE - HSE oscillator clock selected.
+ *            RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected.
+ *            RCC_MCO_PLL2CLK - PLL2 clock selected
+ *            RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected
+ *            RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected
+ *            RCC_MCO_PLL3CLK - PLL3 clock selected
+ *
+ * @return  none
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+    *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RCC flag is set or not.
+ *
+ * @param   RCC_FLAG - specifies the flag to check.
+ *            RCC_FLAG_HSIRDY - HSI oscillator clock ready.
+ *            RCC_FLAG_HSERDY - HSE oscillator clock ready.
+ *            RCC_FLAG_PLLRDY - PLL clock ready.
+ *            RCC_FLAG_PLL2RDY - PLL2 clock ready.
+ *            RCC_FLAG_PLL3RDY - PLL3 clock ready.
+ *            RCC_FLAG_LSERDY - LSE oscillator clock ready.
+ *            RCC_FLAG_LSIRDY - LSI oscillator clock ready.
+ *            RCC_FLAG_PINRST - Pin reset.
+ *            RCC_FLAG_PORRST - POR/PDR reset.
+ *            RCC_FLAG_SFTRST - Software reset.
+ *            RCC_FLAG_IWDGRST - Independent Watchdog reset.
+ *            RCC_FLAG_WWDGRST - Window Watchdog reset.
+ *            RCC_FLAG_LPWRRST - Low Power reset.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+    uint32_t tmp = 0;
+    uint32_t statusreg = 0;
+
+    FlagStatus bitstatus = RESET;
+    tmp = RCC_FLAG >> 5;
+
+    if(tmp == 1)
+    {
+        statusreg = RCC->CTLR;
+    }
+    else if(tmp == 2)
+    {
+        statusreg = RCC->BDCTLR;
+    }
+    else
+    {
+        statusreg = RCC->RSTSCKR;
+    }
+
+    tmp = RCC_FLAG & FLAG_Mask;
+
+    if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearFlag
+ *
+ * @brief   Clears the RCC reset flags.
+ *
+ * @return  none
+ */
+void RCC_ClearFlag(void)
+{
+    RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetITStatus
+ *
+ * @brief   Checks whether the specified RCC interrupt has occurred or not.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt source to check.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_PLL2RDY - PLL2 ready interrupt.
+ *            RCC_IT_PLL3RDY - PLL3 ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    if((RCC->INTR & RCC_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearITPendingBit
+ *
+ * @brief   Clears the RCC's interrupt pending bits.
+ *
+ * @param   RCC_IT - specifies the interrupt pending bit to clear.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_PLL2RDY - PLL2 ready interrupt.
+ *            RCC_IT_PLL3RDY - PLL3 ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  none
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+    *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/*********************************************************************
+ * @fn      RCC_PREDIV1Config
+ *
+ * @brief   Configures the PREDIV1 division factor.
+ *
+ * @param   RCC_PREDIV1_Source - specifies the PREDIV1 clock source.
+ *            RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock
+ *            RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock
+ *          RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor.
+ *            This parameter can be RCC_PREDIV1_Divx where x[1,16]
+ *
+ * @return  none
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR2;
+    tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+    tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div;
+    RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PREDIV2Config
+ *
+ * @brief   Configures the PREDIV2 division factor.
+ *
+ * @param   RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor.
+ *            This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+ *
+ * @return  none
+ */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR2;
+    tmpreg &= ~CFGR2_PREDIV2;
+    tmpreg |= RCC_PREDIV2_Div;
+    RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL2Config
+ *
+ * @brief   Configures the PLL2 multiplication factor.
+ *
+ * @param   RCC_PLL2Mul - specifies the PLL2 multiplication factor.
+ *            This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ *
+ * @return  none
+ */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR2;
+    tmpreg &= ~CFGR2_PLL2MUL;
+    tmpreg |= RCC_PLL2Mul;
+    RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL2Cmd
+ *
+ * @brief   Enables or disables the PLL2.
+ *
+ * @param   NewState - new state of the PLL2. This parameter can be
+ *        ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 26);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 26);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL3Config
+ *
+ * @brief   Configures the PLL3 multiplication factor.
+ *
+ * @param   RCC_PLL3Mul - specifies the PLL2 multiplication factor.
+ *            This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ *
+ * @return  none
+ */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR2;
+    tmpreg &= ~CFGR2_PLL3MUL;
+    tmpreg |= RCC_PLL3Mul;
+    RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL3Cmd
+ *
+ * @brief   Enables or disables the PLL3.
+ *
+ * @param   NewState - new state of the PLL2. This parameter can be
+ *        ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 28);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 28);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_OTGFSCLKConfig
+ *
+ * @brief   Configures the USB OTG FS clock (OTGFSCLK).
+ *
+ * @param   RCC_OTGFSCLKSource - specifies the USB OTG FS clock source.
+ *            RCC_OTGFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1
+ *        selected as USB OTG FS clock source
+ *            RCC_OTGFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2
+ *        selected as USB OTG FS clock source
+ *            RCC_OTGFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3
+ *        selected as USB OTG FS clock source
+ *
+ * @return  none
+ */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+    RCC->CFGR0 &= ~(3 << 22);
+    RCC->CFGR0 |= RCC_OTGFSCLKSource << 22;
+}
+
+/*********************************************************************
+ * @fn      RCC_I2S2CLKConfig
+ *
+ * @brief   Configures the I2S2 clock source(I2S2CLK).
+ *
+ * @param   RCC_I2S2CLKSource - specifies the I2S2 clock source.
+ *          RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry
+ *          RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry
+ *
+ * @return  none
+ */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+    RCC->CFGR2 &= ~(1 << 17);
+    RCC->CFGR2 |= RCC_I2S2CLKSource << 17;
+}
+
+/*********************************************************************
+ * @fn      RCC_I2S3CLKConfig
+ *
+ * @brief   Configures the I2S3 clock source(I2S2CLK).
+ *
+ * @param   RCC_I2S3CLKSource - specifies the I2S3 clock source.
+ *            RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry
+ *            RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry
+ *
+ * @return  none
+ */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+    RCC->CFGR2 &= ~(1 << 18);
+    RCC->CFGR2 |= RCC_I2S3CLKSource << 18;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphResetCmd
+ *
+ * @brief   Forces or releases AHB peripheral reset.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to reset.
+ *            RCC_AHBPeriph_OTG_FS
+ *            RCC_AHBPeriph_ETH_MAC
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->AHBRSTR |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBRSTR &= ~RCC_AHBPeriph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKADJcmd
+ *
+ * @brief   Enable ADC clock duty cycle adjustment.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKADJcmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->CFGR0 |= (1 << 31);
+    }
+    else
+    {
+        RCC->CFGR0 &= ~(1 << 31);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_RNGCLKConfig
+ *
+ * @brief   Configures the RNG clock source.
+ *
+ * @param   RCC_RNGCLKSource - specifies the RNG clock source.
+ *            RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry
+ *            RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry
+ *
+ * @return  none
+ */
+void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource)
+{
+    RCC->CFGR2 &= ~(1 << 19);
+    RCC->CFGR2 |= RCC_RNGCLKSource << 19;
+}
+
+/*********************************************************************
+ * @fn      RCC_ETH1GCLKConfig
+ *
+ * @brief   Configures the ETH1G clock source.
+ *
+ * @param   RCC_RNGCLKSource - specifies the ETH1G clock source.
+ *            RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry
+ *            RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry
+ *            RCC_ETH1GCLKSource_PB1_IN -  GPIO PB1 input clock selected as ETH1G clock entry
+ *
+ * @return  none
+ */
+void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource)
+{
+    RCC->CFGR2 &= ~(3 << 20);
+    RCC->CFGR2 |= RCC_ETH1GCLKSource << 20;
+}
+
+/*********************************************************************
+ * @fn      RCC_ETH1G_125Mcmd
+ *
+ * @brief   Enable ETH1G 125M.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ETH1G_125Mcmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->CFGR2 |= (1 << 22);
+    }
+    else
+    {
+        RCC->CFGR2 &= ~(1 << 22);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSConfig
+ *
+ * @brief   Configures the USBHS clock.
+ *
+ * @param   RCC_USBHS - defines the USBHS clock divider.
+ *            RCC_USBPLL_Div1 - USBHS clock = USBPLL.
+ *            RCC_USBPLL_Div2 - USBHS clock = USBPLL/2.
+ *            RCC_USBPLL_Div3 - USBHS clock = USBPLL/3.
+ *            RCC_USBPLL_Div4 - USBHS clock = USBPLL/4.
+ *            RCC_USBPLL_Div5 - USBHS clock = USBPLL/5.
+ *            RCC_USBPLL_Div6 - USBHS clock = USBPLL/6.
+ *            RCC_USBPLL_Div7 - USBHS clock = USBPLL/7.
+ *            RCC_USBPLL_Div8 - USBHS clock = USBPLL/8.
+ *
+ * @return  none
+ */
+void RCC_USBHSConfig(uint32_t RCC_USBHS)
+{
+    RCC->CFGR2 &= ~(7 << 24);
+    RCC->CFGR2 |= RCC_USBHS << 24;
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSPLLCLKConfig
+ *
+ * @brief   Configures the USBHSPLL clock source.
+ *
+ * @param   RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source.
+ *            RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry
+ *            RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry
+ *
+ * @return  none
+ */
+void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource)
+{
+    RCC->CFGR2 &= ~(1 << 27);
+    RCC->CFGR2 |= RCC_USBHSPLLCLKSource << 27;
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSPLLCKREFCLKConfig
+ *
+ * @brief   Configures the USBHSPLL reference clock.
+ *
+ * @param   RCC_USBHSPLLCKREFCLKSource - Select reference clock.
+ *            RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz.
+ *            RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz.
+ *            RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz.
+ *            RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz.
+ *
+ * @return  none
+ */
+void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource)
+{
+    RCC->CFGR2 &= ~(3 << 28);
+    RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource << 28;
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSPHYPLLALIVEcmd
+ *
+ * @brief   Enable USBHS PHY control.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->CFGR2 |= (1 << 30);
+    }
+    else
+    {
+        RCC->CFGR2 &= ~(1 << 30);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBCLK48MConfig
+ *
+ * @brief   Configures the USB clock 48MHz source.
+ *
+ * @param   RCC_USBCLK48MSource - specifies the USB clock 48MHz source.
+ *            RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry
+ *            RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry
+ *
+ * @return  none
+ */
+void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource)
+{
+    RCC->CFGR2 &= ~(1 << 31);
+    RCC->CFGR2 |= RCC_USBCLK48MSource << 31;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_rng.c

@@ -0,0 +1,152 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_rng.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RNG firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+********************************************************************************/
+#include "ch32v30x_rng.h"
+#include "ch32v30x_rcc.h"
+
+/*********************************************************************
+ * @fn      RNG_Cmd
+ *
+ * @brief   Enables or disables the RNG peripheral.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RNG_Cmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RNG->CR |= RNG_CR_RNGEN;
+    }
+    else
+    {
+        RNG->CR &= ~RNG_CR_RNGEN;
+    }
+}
+
+/*********************************************************************
+ * @fn      RNG_GetRandomNumber
+ *
+ * @brief   Returns a 32-bit random number.
+ *
+ * @return  32-bit random number.
+ */
+uint32_t RNG_GetRandomNumber(void)
+{
+    return RNG->DR;
+}
+
+/*********************************************************************
+ * @fn      RNG_ITConfig
+ *
+ * @brief   Enables or disables the RNG interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  32-bit random number.
+ */
+void RNG_ITConfig(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RNG->CR |= RNG_CR_IE;
+    }
+    else
+    {
+        RNG->CR &= ~RNG_CR_IE;
+    }
+}
+
+/*********************************************************************
+ * @fn      RNG_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RNG flag is set or not.
+ *
+ * @param   RNG_FLAG - specifies the RNG flag to check.
+ *            RNG_FLAG_DRDY - Data Ready flag.
+ *            RNG_FLAG_CECS - Clock Error Current flag.
+ *            RNG_FLAG_SECS - Seed Error Current flag.
+ *
+ * @return  32-bit random number.
+ */
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RNG_ClearFlag
+ *
+ * @brief   Clears the RNG flags.
+ *
+ * @param   RNG_FLAG - specifies the flag to clear.
+ *            RNG_FLAG_CECS - Clock Error Current flag.
+ *            RNG_FLAG_SECS - Seed Error Current flag.
+ *
+ * @return  32-bit random number.
+ */
+void RNG_ClearFlag(uint8_t RNG_FLAG)
+{
+    RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
+}
+
+/*********************************************************************
+ * @fn      RNG_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RNG interrupt has occurred or not.
+ *
+ * @param   RNG_IT - specifies the RNG interrupt source to check.
+ *            RNG_IT_CEI - Clock Error Interrupt.
+ *            RNG_IT_SEI - Seed Error Interrupt.
+ *
+ * @return  bitstatus£ºSET or RESET.
+ */
+ITStatus RNG_GetITStatus(uint8_t RNG_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    if((RNG->SR & RNG_IT) != (uint8_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RNG_ClearITPendingBit
+ *
+ * @brief   Clears the RNG interrupt pending bit(s).
+ *
+ * @param   RNG_IT - specifies the RNG interrupt pending bit(s) to clear.
+ *            RNG_IT_CEI - Clock Error Interrupt.
+ *            RNG_IT_SEI - Seed Error Interrupt.
+ *
+ * @return  None
+ */
+void RNG_ClearITPendingBit(uint8_t RNG_IT)
+{
+    RNG->SR = (uint8_t)~RNG_IT;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_rtc.c

@@ -0,0 +1,273 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_rtc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RTC firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+********************************************************************************/
+#include "ch32v30x_rtc.h"
+
+/* RTC_Private_Defines */
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
+
+/*********************************************************************
+ * @fn      RTC_ITConfig
+ *
+ * @brief   Enables or disables the specified RTC interrupts.
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
+ *            RTC_IT_OW - Overflow interrupt
+ *            RTC_IT_ALR - Alarm interrupt
+ *            RTC_IT_SEC - Second interrupt
+ *
+ * @return  NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RTC->CTLRH |= RTC_IT;
+    }
+    else
+    {
+        RTC->CTLRH &= (uint16_t)~RTC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_EnterConfigMode
+ *
+ * @brief   Enters the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_EnterConfigMode(void)
+{
+    RTC->CTLRL |= RTC_CTLRL_CNF;
+}
+
+/*********************************************************************
+ * @fn      RTC_ExitConfigMode
+ *
+ * @brief   Exits from the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_ExitConfigMode(void)
+{
+    RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
+}
+
+/*********************************************************************
+ * @fn      RTC_GetCounter
+ *
+ * @brief   Gets the RTC counter value
+ *
+ * @return  RTC counter value
+ */
+uint32_t RTC_GetCounter(void)
+{
+    uint16_t high1 = 0, high2 = 0, low = 0;
+
+    high1 = RTC->CNTH;
+    low = RTC->CNTL;
+    high2 = RTC->CNTH;
+
+    if(high1 != high2)
+    {
+        return (((uint32_t)high2 << 16) | RTC->CNTL);
+    }
+    else
+    {
+        return (((uint32_t)high1 << 16) | low);
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_SetCounter
+ *
+ * @brief   Sets the RTC counter value.
+ *
+ * @param   CounterValue - RTC counter new value.
+ *
+ * @return  RTC counter value
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+    RTC_EnterConfigMode();
+    RTC->CNTH = CounterValue >> 16;
+    RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_SetPrescaler
+ *
+ * @brief   Sets the RTC prescaler value
+ *
+ * @param   PrescalerValue - RTC prescaler new value
+ *
+ * @return  none
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+    RTC_EnterConfigMode();
+    RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+    RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_SetAlarm
+ *
+ * @brief   Sets the RTC alarm value
+ *
+ * @param   AlarmValue - RTC alarm new value
+ *
+ * @return  none
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+    RTC_EnterConfigMode();
+    RTC->ALRMH = AlarmValue >> 16;
+    RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_GetDivider
+ *
+ * @brief   Gets the RTC divider value
+ *
+ * @return  RTC Divider value
+ */
+uint32_t RTC_GetDivider(void)
+{
+    uint32_t tmp = 0x00;
+    tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+    tmp |= RTC->DIVL;
+    return tmp;
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForLastTask
+ *
+ * @brief   Waits until last write operation on RTC registers has finished
+ *
+ * @return  none
+ */
+void RTC_WaitForLastTask(void)
+{
+    while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForSynchro
+ *
+ * @brief   Waits until the RTC registers are synchronized with RTC APB clock
+ *
+ * @return  none
+ */
+void RTC_WaitForSynchro(void)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
+    while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RTC flag is set or not
+ *
+ * @param   RTC_FLAG- specifies the flag to check
+ *            RTC_FLAG_RTOFF - RTC Operation OFF flag
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  none
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearFlag
+ *
+ * @brief   Clears the RTC's pending flags
+ *
+ * @param   RTC_FLAG - specifies the flag to clear
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  none
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_FLAG;
+}
+
+/*********************************************************************
+ * @fn      RTC_GetITStatus
+ *
+ * @brief   Checks whether the specified RTC interrupt has occurred or not
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to check
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  The new state of the RTC_IT (SET or RESET)
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
+    if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearITPendingBit
+ *
+ * @brief   Clears the RTC's interrupt pending bits
+ *
+ * @param   RTC_IT - specifies the interrupt pending bit to clear
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  none
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_IT;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_sdio.c

@@ -0,0 +1,670 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_SDIO.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the SDIO firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_sdio.h"
+#include "ch32v30x_rcc.h"
+
+#define SDIO_OFFSET         (SDIO_BASE - PERIPH_BASE)
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK    ((uint32_t)0xFFFF8100)
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK    ((uint32_t)0xFFFFFFFC)
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK    ((uint32_t)0xFFFFFF08)
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK      ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR      ((uint32_t)(SDIO_BASE + 0x14))
+
+/*********************************************************************
+ * @fn      SDIO_DeInit
+ *
+ * @brief   Deinitializes the SDIO peripheral registers to their default
+ *        reset values.
+ *
+ * @return  RTC counter value
+ */
+void SDIO_DeInit(void)
+{
+    SDIO->POWER = 0x00000000;
+    SDIO->CLKCR = 0x00000000;
+    SDIO->ARG = 0x00000000;
+    SDIO->CMD = 0x00000000;
+    SDIO->DTIMER = 0x00000000;
+    SDIO->DLEN = 0x00000000;
+    SDIO->DCTRL = 0x00000000;
+    SDIO->ICR = 0x00C007FF;
+    SDIO->MASK = 0x00000000;
+}
+
+/*********************************************************************
+ * @fn      SDIO_Init
+ *
+ * @brief   Initializes the SDIO peripheral according to the specified
+ *        parameters in the SDIO_InitStruct.
+ *
+ * @param   SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure
+ *        that contains the configuration information for the SDIO peripheral.
+ *
+ * @return  None
+ */
+void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = SDIO->CLKCR;
+    tmpreg &= CLKCR_CLEAR_MASK;
+    tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
+               SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+               SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
+
+    SDIO->CLKCR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SDIO_StructInit
+ *
+ * @brief   Fills each SDIO_InitStruct member with its default value.
+ *
+ * @param   SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
+{
+    SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+    SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+    SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+    SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+    SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+    SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/*********************************************************************
+ * @fn      SDIO_ClockCmd
+ *
+ * @brief   Enables or disables the SDIO Clock.
+ *
+ * @param   SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->CLKCR |= (1 << 8);
+    else
+        SDIO->CLKCR &= ~(1 << 8);
+}
+
+/*********************************************************************
+ * @fn      SDIO_SetPowerState
+ *
+ * @brief   Sets the power status of the controller.
+ *
+ * @param   SDIO_PowerState - new state of the Power state.
+ *            SDIO_PowerState_OFF
+ *            SDIO_PowerState_ON
+ *
+ * @return  none
+ */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+    SDIO->POWER &= PWR_PWRCTRL_MASK;
+    SDIO->POWER |= SDIO_PowerState;
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetPowerState
+ *
+ * @brief   Gets the power status of the controller.
+ *
+ * @param   CounterValue - RTC counter new value.
+ *
+ * @return  power state -
+ *            0x00 - Power OFF
+ *            0x02 - Power UP
+ *            0x03 - Power ON
+ */
+uint32_t SDIO_GetPowerState(void)
+{
+    return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/*********************************************************************
+ * @fn      SDIO_ITConfig
+ *
+ * @brief   Enables or disables the SDIO interrupts.
+ *
+ * @param   DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled.
+ *            SDIO_IT_CCRCFAIL
+ *            SDIO_IT_DCRCFAIL
+ *            SDIO_IT_CTIMEOUT
+ *            SDIO_IT_DTIMEOUT
+ *            SDIO_IT_TXUNDERR
+ *            SDIO_IT_RXOVERR
+ *            SDIO_IT_CMDREND
+ *            SDIO_IT_CMDSENT
+ *            SDIO_IT_DATAEND
+ *            SDIO_IT_STBITERR
+ *            SDIO_IT_DBCKEND
+ *            SDIO_IT_CMDACT
+ *            SDIO_IT_TXACT
+ *            SDIO_IT_RXACT
+ *            SDIO_IT_TXFIFOHE
+ *            SDIO_IT_RXFIFOHF
+ *            SDIO_IT_TXFIFOF
+ *            SDIO_IT_RXFIFOF
+ *            SDIO_IT_TXFIFOE
+ *            SDIO_IT_RXFIFOE
+ *            SDIO_IT_TXDAVL
+ *            SDIO_IT_RXDAVL
+ *            SDIO_IT_SDIOIT
+ *            SDIO_IT_CEATAEND
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SDIO->MASK |= SDIO_IT;
+    }
+    else
+    {
+        SDIO->MASK &= ~SDIO_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      SDIO_DMACmd
+ *
+ * @brief   Enables or disables the SDIO DMA request.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->DCTRL |= (1 << 3);
+    else
+        SDIO->DCTRL &= ~(1 << 3);
+}
+
+/*********************************************************************
+ * @fn      SDIO_SendCommand
+ *
+ * @brief   Initializes the SDIO Command according to the specified
+ *        parameters in the SDIO_CmdInitStruct and send the command.
+ * @param   SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef
+ *        structure that contains the configuration information for
+ *        ddthe SDIO command.
+ *
+ * @return  none
+ */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+
+    tmpreg = SDIO->CMD;
+    tmpreg &= CMD_CLEAR_MASK;
+    tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+    SDIO->CMD = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SDIO_CmdStructInit
+ *
+ * @brief   Fills each SDIO_CmdInitStruct member with its default value.
+ *
+ * @param   SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+    SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+    SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+    SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+    SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+    SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetCommandResponse
+ *
+ * @brief   Returns command index of last command for which response received.
+ *
+ * @return  Returns the command index of the last command response received.
+ */
+uint8_t SDIO_GetCommandResponse(void)
+{
+    return (uint8_t)(SDIO->RESPCMD);
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetResponse
+ *
+ * @brief   Returns response received from the card for the last command.
+ *
+ * @param   SDIO_RESP - Specifies the SDIO response register.
+ *            SDIO_RESP1 - Response Register 1
+ *            SDIO_RESP2 - Response Register 2
+ *            SDIO_RESP3 - Response Register 3
+ *            SDIO_RESP4 - Response Register 4
+ *
+ * @return  Returns the command index of the last command response received.
+ */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = SDIO_RESP_ADDR + SDIO_RESP;
+
+    return (*(__IO uint32_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      SDIO_DataConfig
+ *
+ * @brief   Initializes the SDIO data path according to the specified
+ *
+ * @param   SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that
+ *        contains the configuration information for the SDIO command.
+ *
+ * @return  none
+ */
+void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+    SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+    tmpreg = SDIO->DCTRL;
+    tmpreg &= DCTRL_CLEAR_MASK;
+    tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+    SDIO->DCTRL = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SDIO_DataStructInit
+ *
+ * @brief   Fills each SDIO_DataInitStruct member with its default value.
+ *
+ * @param   SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  RTC counter value
+ */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
+{
+    SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+    SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+    SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+    SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+    SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+    SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetDataCounter
+ *
+ * @brief   Returns number of remaining data bytes to be transferred.
+ *
+ * @return  Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCounter(void)
+{
+    return SDIO->DCOUNT;
+}
+
+/*********************************************************************
+ * @fn      SDIO_ReadData
+ *
+ * @brief   Read one data word from Rx FIFO.
+ *
+ * @return  Data received
+ */
+uint32_t SDIO_ReadData(void)
+{
+    return SDIO->FIFO;
+}
+
+/*********************************************************************
+ * @fn      SDIO_WriteData
+ *
+ * @brief   Write one data word to Tx FIFO.
+ *
+ * @param   Data - 32-bit data word to write.
+ *
+ * @return  RTC counter value
+ */
+void SDIO_WriteData(uint32_t Data)
+{
+    SDIO->FIFO = Data;
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetFIFOCount
+ *
+ * @brief   Returns the number of words left to be written to or read from FIFO.
+ *
+ * @return  Remaining number of words.
+ */
+uint32_t SDIO_GetFIFOCount(void)
+{
+    return SDIO->FIFOCNT;
+}
+
+/*********************************************************************
+ * @fn      SDIO_StartSDIOReadWait
+ *
+ * @brief   Starts the SD I/O Read Wait operation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->DCTRL |= (1 << 8);
+    else
+        SDIO->DCTRL &= ~(1 << 8);
+}
+
+/*********************************************************************
+ * @fn      SDIO_StopSDIOReadWait
+ *
+ * @brief   Stops the SD I/O Read Wait operation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->DCTRL |= (1 << 9);
+    else
+        SDIO->DCTRL &= ~(1 << 9);
+}
+
+/*********************************************************************
+ * @fn      SDIO_SetSDIOReadWaitMode
+ *
+ * @brief   Sets one of the two options of inserting read wait interval.
+ *
+ * @param   SDIO_ReadWaitMode - SD I/O Read Wait operation mode.
+ *            SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK
+ *            SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2
+ *
+ * @return  none
+ */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+    if(SDIO_ReadWaitMode)
+        SDIO->DCTRL |= (1 << 10);
+    else
+        SDIO->DCTRL &= ~(1 << 10);
+}
+
+/*********************************************************************
+ * @fn      SDIO_SetSDIOOperation
+ *
+ * @brief   Enables or disables the SD I/O Mode Operation.
+ *
+ * @param   NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->DCTRL |= (1 << 11);
+    else
+        SDIO->DCTRL &= ~(1 << 11);
+}
+
+/*********************************************************************
+ * @fn      SDIO_SendSDIOSuspendCmd
+ *
+ * @brief   Enables or disables the SD I/O Mode suspend command sending.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->CMD |= (1 << 11);
+    else
+        SDIO->CMD &= ~(1 << 11);
+}
+
+/*********************************************************************
+ * @fn      SDIO_CommandCompletionCmd
+ *
+ * @brief   Enables or disables the command completion signal.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->CMD |= (1 << 12);
+    else
+        SDIO->CMD &= ~(1 << 12);
+}
+
+/*********************************************************************
+ * @fn      SDIO_CEATAITCmd
+ *
+ * @brief   Enables or disables the CE-ATA interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->CMD |= (1 << 13);
+    else
+        SDIO->CMD &= ~(1 << 13);
+}
+
+/*********************************************************************
+ * @fn      SDIO_SendCEATACmd
+ *
+ * @brief   Sends CE-ATA command (CMD61).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  RTC counter value
+ */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{
+    if(NewState)
+        SDIO->CMD |= (1 << 14);
+    else
+        SDIO->CMD &= ~(1 << 14);
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetFlagStatus
+ *
+ * @brief   Checks whether the specified SDIO flag is set or not.
+ *
+ * @param   SDIO_FLAG - specifies the flag to check.
+ *            SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
+ *            SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
+ *            SDIO_FLAG_CTIMEOUT - Command response timeout
+ *            SDIO_FLAG_DTIMEOUT - Data timeout
+ *            SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
+ *            SDIO_FLAG_RXOVERR - Received FIFO overrun error
+ *            SDIO_FLAG_CMDREND - Command response received (CRC check passed)
+ *            SDIO_FLAG_CMDSENT - Command sent (no response required)
+ *            SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
+ *            SDIO_FLAG_STBITERR - Start bit not detected on all data signals
+ *          in wide bus mode.
+ *            SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
+ *            SDIO_FLAG_CMDACT - Command transfer in progress
+ *            SDIO_FLAG_TXACT - Data transmit in progress
+ *            SDIO_FLAG_RXACT - Data receive in progress
+ *            SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty
+ *            SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full
+ *            SDIO_FLAG_TXFIFOF - Transmit FIFO full
+ *            SDIO_FLAG_RXFIFOF - Receive FIFO full
+ *            SDIO_FLAG_TXFIFOE - Transmit FIFO empty
+ *            SDIO_FLAG_RXFIFOE - Receive FIFO empty
+ *            SDIO_FLAG_TXDAVL - Data available in transmit FIFO
+ *            SDIO_FLAG_RXDAVL - Data available in receive FIFO
+ *            SDIO_FLAG_SDIOIT - SD I/O interrupt received
+ *            SDIO_FLAG_CEATAEND - CE-ATA command completion signal received
+ *          for CMD61
+ *
+ * @return  ITStatus - SET or RESET
+ */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SDIO_ClearFlag
+ *
+ * @brief   Clears the SDIO's pending flags.
+ *
+ * @param   SDIO_FLAG - specifies the flag to clear.
+ *            SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
+ *            SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
+ *            SDIO_FLAG_CTIMEOUT - Command response timeout
+ *            SDIO_FLAG_DTIMEOUT - Data timeout
+ *            SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
+ *            SDIO_FLAG_RXOVERR - Received FIFO overrun error
+ *            SDIO_FLAG_CMDREND - Command response received (CRC check passed)
+ *            SDIO_FLAG_CMDSENT - Command sent (no response required)
+ *            SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
+ *            SDIO_FLAG_STBITERR - Start bit not detected on all data signals
+ *        in wide bus mode
+ *            SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
+ *            SDIO_FLAG_SDIOIT - SD I/O interrupt received
+ *            SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61
+ *
+ * @return  none
+ */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{
+    SDIO->ICR = SDIO_FLAG;
+}
+
+/*********************************************************************
+ * @fn      SDIO_GetITStatus
+ *
+ * @brief   Checks whether the specified SDIO interrupt has occurred or not.
+ *
+ * @param   SDIO_IT: specifies the SDIO interrupt source to check.
+ *            SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
+ *            SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
+ *            SDIO_IT_CTIMEOUT - Command response timeout interrupt
+ *            SDIO_IT_DTIMEOUT - Data timeout interrupt
+ *            SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
+ *            SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
+ *            SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
+ *            SDIO_IT_CMDSENT - Command sent (no response required) interrupt
+ *            SDIO_IT_DATAEND -  Data end (data counter, SDIDCOUNT, is zero) interrupt
+ *            SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
+ *        bus mode interrupt
+ *            SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt
+ *            SDIO_IT_CMDACT - Command transfer in progress interrupt
+ *            SDIO_IT_TXACT - Data transmit in progress interrupt
+ *            SDIO_IT_RXACT - Data receive in progress interrupt
+ *            SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt
+ *            SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt
+ *            SDIO_IT_TXFIFOF - Transmit FIFO full interrupt
+ *            SDIO_IT_RXFIFOF - Receive FIFO full interrupt
+ *            SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt
+ *            SDIO_IT_RXFIFOE - Receive FIFO empty interrupt
+ *            SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt
+ *            SDIO_IT_RXDAVL - Data available in receive FIFO interrupt
+ *            SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
+ *            SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt
+ *
+ * @return  ITStatus£ºSET or RESET
+ */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    if((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SDIO_ClearITPendingBit
+ *
+ * @brief   Clears the SDIO's interrupt pending bits.
+ *
+ * @param   SDIO_IT - specifies the interrupt pending bit to clear.
+ *            SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
+ *            SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
+ *            SDIO_IT_CTIMEOUT - Command response timeout interrupt
+ *            SDIO_IT_DTIMEOUT - Data timeout interrupt
+ *            SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
+ *            SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
+ *            SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
+ *            SDIO_IT_CMDSENT - Command sent (no response required) interrupt
+ *            SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
+ *            SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
+ *        bus mode interrupt
+ *            SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
+ *            SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61
+ *
+ * @return  RTC counter value
+ */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{
+    SDIO->ICR = SDIO_IT;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_spi.c

@@ -0,0 +1,646 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_spi.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the SPI firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x_spi.h"
+#include "ch32v30x_rcc.h"
+
+/* SPI SPE mask */
+#define CTLR1_SPE_Set         ((uint16_t)0x0040)
+#define CTLR1_SPE_Reset       ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set      ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset    ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTLR1_CRCNext_Set     ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTLR1_CRCEN_Set       ((uint16_t)0x2000)
+#define CTLR1_CRCEN_Reset     ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTLR2_SSOE_Set        ((uint16_t)0x0004)
+#define CTLR2_SSOE_Reset      ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTLR1_CLEAR_Mask      ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask    ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select       ((uint16_t)0xF7FF)
+#define I2S_Mode_Select       ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC        ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC        ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK          ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK          ((uint32_t)(0x000000F0))
+
+/*********************************************************************
+ * @fn      SPI_I2S_DeInit
+ *
+ * @brief   Deinitializes the SPIx peripheral registers to their default
+ *        reset values (Affects also the I2Ss).
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+    if(SPIx == SPI1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+    }
+    else if(SPIx == SPI2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+    else
+    {
+        if(SPIx == SPI3)
+        {
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the SPI_InitStruct.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = SPIx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                         SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+                         SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+                         SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+
+    SPIx->CTLR1 = tmpreg;
+    SPIx->I2SCFGR &= SPI_Mode_Select;
+    SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/*********************************************************************
+ * @fn      I2S_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the I2S_InitStruct.
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *        (configured in I2S mode).
+ *          I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral
+ *        configured in I2S mode.
+ * @return  none
+ */
+void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
+{
+    uint16_t          tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+    uint32_t          tmp = 0;
+    RCC_ClocksTypeDef RCC_Clocks;
+    uint32_t          sourceclock = 0;
+
+    SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+    SPIx->I2SPR = 0x0002;
+    tmpreg = SPIx->I2SCFGR;
+
+    if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+    {
+        i2sodd = (uint16_t)0;
+        i2sdiv = (uint16_t)2;
+    }
+    else
+    {
+        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+        {
+            packetlength = 1;
+        }
+        else
+        {
+            packetlength = 2;
+        }
+
+        if(((uint32_t)SPIx) == SPI2_BASE)
+        {
+            tmp = I2S2_CLOCK_SRC;
+        }
+        else
+        {
+            tmp = I2S3_CLOCK_SRC;
+        }
+
+        RCC_GetClocksFreq(&RCC_Clocks);
+
+        sourceclock = RCC_Clocks.SYSCLK_Frequency;
+
+        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+        {
+            tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+        }
+        else
+        {
+            tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+        }
+
+        tmp = tmp / 10;
+        i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+        i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+        i2sodd = (uint16_t)(i2sodd << 8);
+    }
+
+    if((i2sdiv < 2) || (i2sdiv > 0xFF))
+    {
+        i2sdiv = 2;
+        i2sodd = 0;
+    }
+
+    SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+    tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
+                                                      (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
+                                                                                                           (uint16_t)I2S_InitStruct->I2S_CPOL))));
+    SPIx->I2SCFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_StructInit
+ *
+ * @brief   Fills each SPI_InitStruct member with its default value.
+ *
+ * @param   SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
+{
+    SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+    SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+    SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+    SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+    SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/*********************************************************************
+ * @fn      I2S_StructInit
+ *
+ * @brief   Fills each I2S_InitStruct member with its default value.
+ *
+ * @param   I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
+{
+    I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+    I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+    I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+    I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+    I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+    I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/*********************************************************************
+ * @fn      SPI_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR1 |= CTLR1_SPE_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_SPE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2S_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral (in I2S mode).
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+    }
+    else
+    {
+        SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ITConfig
+ *
+ * @brief   Enables or disables the specified SPI/I2S interrupts.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
+ *        enabled or disabled.
+ *            SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
+ *            SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
+ *            SPI_I2S_IT_ERR - Error interrupt mask.
+ *          NewState: ENABLE or DISABLE.
+ * @return  none
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+    uint16_t itpos = 0, itmask = 0;
+
+    itpos = SPI_I2S_IT >> 4;
+    itmask = (uint16_t)1 << (uint16_t)itpos;
+
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= itmask;
+    }
+    else
+    {
+        SPIx->CTLR2 &= (uint16_t)~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_DMACmd
+ *
+ * @brief   Enables or disables the SPIx/I2Sx DMA interface.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
+ *        be enabled or disabled.
+ *            SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
+ *            SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= SPI_I2S_DMAReq;
+    }
+    else
+    {
+        SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_SendData
+ *
+ * @brief   Transmits a Data through the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  none
+ */
+void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
+{
+    SPIx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  SPIx->DATAR - The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
+{
+    return SPIx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      SPI_NSSInternalSoftwareConfig
+ *
+ * @brief   Configures internally by software the NSS pin for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_NSSInternalSoft -
+ *            SPI_NSSInternalSoft_Set - Set NSS pin internally.
+ *            SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
+ *
+ * @return  none
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
+{
+    if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+    {
+        SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_SSOutputCmd
+ *
+ * @brief   Enables or disables the SS output for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx SS output.
+ *
+ * @return  none
+ */
+void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= CTLR2_SSOE_Set;
+    }
+    else
+    {
+        SPIx->CTLR2 &= CTLR2_SSOE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_DataSizeConfig
+ *
+ * @brief   Configures the data size for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_DataSize - specifies the SPI data size.
+ *            SPI_DataSize_16b - Set data frame format to 16bit.
+ *            SPI_DataSize_8b - Set data frame format to 8bit.
+ *
+ * @return  none
+ */
+void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
+{
+    SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
+    SPIx->CTLR1 |= SPI_DataSize;
+}
+
+/*********************************************************************
+ * @fn      SPI_TransmitCRC
+ *
+ * @brief   Transmit the SPIx CRC value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_TransmitCRC(SPI_TypeDef *SPIx)
+{
+    SPIx->CTLR1 |= CTLR1_CRCNext_Set;
+}
+
+/*********************************************************************
+ * @fn      SPI_CalculateCRC
+ *
+ * @brief   Enables or disables the CRC value calculation of the transferred bytes.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx CRC value calculation.
+ *
+ * @return  none
+ */
+void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR1 |= CTLR1_CRCEN_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRC
+ *
+ * @brief   Returns the transmit or the receive CRC register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_CRC - specifies the CRC register to be read.
+ *            SPI_CRC_Tx - Selects Tx CRC register.
+ *            SPI_CRC_Rx - Selects Rx CRC register.
+ *
+ * @return  crcreg: The selected CRC register value.
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
+{
+    uint16_t crcreg = 0;
+
+    if(SPI_CRC != SPI_CRC_Rx)
+    {
+        crcreg = SPIx->TCRCR;
+    }
+    else
+    {
+        crcreg = SPIx->RCRCR;
+    }
+
+    return crcreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRCPolynomial
+ *
+ * @brief   Returns the CRC Polynomial register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  SPIx->CRCR - The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+    return SPIx->CRCR;
+}
+
+/*********************************************************************
+ * @fn      SPI_BiDirectionalLineConfig
+ *
+ * @brief   Selects the data transfer direction in bi-directional mode
+ *      for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_Direction - specifies the data transfer direction in
+ *        bi-directional mode.
+ *            SPI_Direction_Tx - Selects Tx transmission direction.
+ *            SPI_Direction_Rx - Selects Rx receive direction.
+ *
+ * @return  none
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
+{
+    if(SPI_Direction == SPI_Direction_Tx)
+    {
+        SPIx->CTLR1 |= SPI_Direction_Tx;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_Direction_Rx;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetFlagStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S flag is set or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
+ *            SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
+ *            SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
+ *            SPI_I2S_FLAG_BSY - Busy flag.
+ *            SPI_I2S_FLAG_OVR - Overrun flag.
+ *            SPI_FLAG_MODF - Mode Fault flag.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *            I2S_FLAG_UDR - Underrun Error flag.
+ *            I2S_FLAG_CHSIDE - Channel Side flag.
+ *
+ * @return  none
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearFlag
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) flag.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI flag to clear.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *
+ * @return  none
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
+{
+    SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetITStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S interrupt has occurred or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
+ *            SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
+ *            SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
+ *            SPI_I2S_IT_OVR - Overrun interrupt.
+ *            SPI_IT_MODF - Mode Fault interrupt.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *            I2S_IT_UDR - Underrun Error interrupt.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+    itmask = SPI_I2S_IT >> 4;
+    itmask = 0x01 << itmask;
+    enablestatus = (SPIx->CTLR2 & itmask);
+
+    if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearITPendingBit
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *          SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *
+ * @return  none
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
+{
+    uint16_t itpos = 0;
+
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+    SPIx->STATR = (uint16_t)~itpos;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_tim.c

@@ -0,0 +1,2366 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_tim.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the TIM firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_tim.h"
+#include "ch32v30x_rcc.h"
+
+/* TIM registers bit mask */
+#define SMCFGR_ETR_Mask    ((uint16_t)0x00FF)
+#define CHCTLR_Offset      ((uint16_t)0x0018)
+#define CCER_CCE_Set       ((uint16_t)0x0001)
+#define CCER_CCNE_Set      ((uint16_t)0x0004)
+
+static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+
+/*********************************************************************
+ * @fn      TIM_DeInit
+ *
+ * @brief   Deinitializes the TIMx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *
+ * @return  none
+ */
+void TIM_DeInit(TIM_TypeDef *TIMx)
+{
+    if(TIMx == TIM1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+    }
+    else if(TIMx == TIM8)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+    }
+    else if(TIMx == TIM9)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
+    }
+    else if(TIMx == TIM10)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
+    }
+    else if(TIMx == TIM2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+    }
+    else if(TIMx == TIM3)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+    }
+    else if(TIMx == TIM4)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+    }
+    else if(TIMx == TIM5)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+    }
+    else if(TIMx == TIM6)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+    }
+    else if(TIMx == TIM7)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_TimeBaseInit
+ *
+ * @brief   Initializes the TIMx Time Base Unit peripheral according to
+ *        the specified parameters in the TIM_TimeBaseInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef
+ *        structure.
+ *
+ * @return  none
+ */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    uint16_t tmpcr1 = 0;
+
+    tmpcr1 = TIMx->CTLR1;
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) ||
+       (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
+        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+    }
+
+    if((TIMx != TIM6) && (TIMx != TIM7))
+    {
+        tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD));
+        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+    }
+
+    TIMx->CTLR1 = tmpcr1;
+    TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period;
+    TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+    if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+    }
+
+    TIMx->SWEVGR = TIM_PSCReloadMode_Immediate;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1Init
+ *
+ * @brief   Initializes the TIMx Channel1 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E);
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR1;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S));
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P));
+    tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+    tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+    if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP));
+        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE));
+        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N));
+
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR1 = tmpccmrx;
+    TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2Init
+ *
+ * @brief   Initializes the TIMx Channel2 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR1;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S));
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+    if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR1 = tmpccmrx;
+    TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3Init
+ *
+ * @brief   Initializes the TIMx Channel3 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR2;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S));
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+    if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR2 = tmpccmrx;
+    TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4Init
+ *
+ * @brief   Initializes the TIMx Channel4 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR2;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S));
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+    if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR2 = tmpccmrx;
+    TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_ICInit
+ *
+ * @brief   IInitializes the TIM peripheral according to the specified
+ *        parameters in the TIM_ICInitStruct.
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+    {
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+    {
+        TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_PWMIConfig
+ *
+ * @brief   Configures the TIM peripheral according to the specified
+ *        parameters in the TIM_ICInitStruct to measure an external
+ *        PWM signal.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+    uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+
+    if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+    {
+        icoppositepolarity = TIM_ICPolarity_Falling;
+    }
+    else
+    {
+        icoppositepolarity = TIM_ICPolarity_Rising;
+    }
+
+    if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+    {
+        icoppositeselection = TIM_ICSelection_IndirectTI;
+    }
+    else
+    {
+        icoppositeselection = TIM_ICSelection_DirectTI;
+    }
+
+    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_BDTRConfig
+ *
+ * @brief   Configures the: Break feature, dead time, Lock level, the OSSI,
+ *      the OSSR State and the AOE(automatic output enable).
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/*********************************************************************
+ * @fn      TIM_TimeBaseStructInit
+ *
+ * @brief   Fills each TIM_TimeBaseInitStruct member with its default value.
+ *
+ * @param   TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+    TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+    TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+    TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+    TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/*********************************************************************
+ * @fn      TIM_OCStructInit
+ *
+ * @brief   Fills each TIM_OCInitStruct member with its default value.
+ *
+ * @param   TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+    TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+    TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+    TIM_OCInitStruct->TIM_Pulse = 0x0000;
+    TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+    TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/*********************************************************************
+ * @fn      TIM_ICStructInit
+ *
+ * @brief   Fills each TIM_ICInitStruct member with its default value.
+ *
+ * @param   TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+    TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+    TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+    TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+    TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/*********************************************************************
+ * @fn      TIM_BDTRStructInit
+ *
+ * @brief   Fills each TIM_BDTRInitStruct member with its default value.
+ *
+ * @param   TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+    TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+    TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+    TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+    TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+    TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+    TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/*********************************************************************
+ * @fn      TIM_Cmd
+ *
+ * @brief   Enables or disables the specified TIM peripheral.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_CEN;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN));
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_CtrlPWMOutputs
+ *
+ * @brief   Enables or disables the TIM peripheral Main Outputs.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->BDTR |= TIM_MOE;
+    }
+    else
+    {
+        TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE));
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_ITConfig
+ *
+ * @brief   Enables or disables the specified TIM interrupts.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupts sources to be enabled or disabled.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->DMAINTENR |= TIM_IT;
+    }
+    else
+    {
+        TIMx->DMAINTENR &= (uint16_t)~TIM_IT;
+    }
+}
+
+void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
+{
+    TIMx->SWEVGR = TIM_EventSource;
+}
+
+/*********************************************************************
+ * @fn      TIM_DMAConfig
+ *
+ * @brief   Configures the TIMx's DMA interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_DMABase: DMA Base address.
+ *            TIM_DMABase_CR.
+ *            TIM_DMABase_CR2.
+ *            TIM_DMABase_SMCR.
+ *            TIM_DMABase_DIER.
+ *            TIM1_DMABase_SR.
+ *            TIM_DMABase_EGR.
+ *            TIM_DMABase_CCMR1.
+ *            TIM_DMABase_CCMR2.
+ *            TIM_DMABase_CCER.
+ *            TIM_DMABase_CNT.
+ *            TIM_DMABase_PSC.
+ *            TIM_DMABase_CCR1.
+ *            TIM_DMABase_CCR2.
+ *            TIM_DMABase_CCR3.
+ *            TIM_DMABase_CCR4.
+ *            TIM_DMABase_BDTR.
+ *            TIM_DMABase_DCR.
+ *          TIM_DMABurstLength - DMA Burst length.
+ *            TIM_DMABurstLength_1Transfer.
+ *            TIM_DMABurstLength_18Transfers.
+ *
+ * @return  none
+ */
+void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+    TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/*********************************************************************
+ * @fn      TIM_DMACmd
+ *
+ * @brief   Enables or disables the TIMx's DMA Requests.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_DMASource - specifies the DMA Request sources.
+ *            TIM_DMA_Update - TIM update Interrupt source.
+ *            TIM_DMA_CC1 - TIM Capture Compare 1 DMA source.
+ *            TIM_DMA_CC2 - TIM Capture Compare 2 DMA source.
+ *            TIM_DMA_CC3 - TIM Capture Compare 3 DMA source.
+ *            TIM_DMA_CC4 - TIM Capture Compare 4 DMA source.
+ *            TIM_DMA_COM - TIM Commutation DMA source.
+ *            TIM_DMA_Trigger - TIM Trigger DMA source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->DMAINTENR |= TIM_DMASource;
+    }
+    else
+    {
+        TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource;
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_InternalClockConfig
+ *
+ * @brief   Configures the TIMx internal Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *
+ * @return  none
+ */
+void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
+{
+    TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS));
+}
+
+/*********************************************************************
+ * @fn      TIM_ITRxExternalClockConfig
+ *
+ * @brief   Configures the TIMx Internal Trigger as External Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_InputTriggerSource: Trigger source.
+ *            TIM_TS_ITR0 - Internal Trigger 0.
+ *            TIM_TS_ITR1 - Internal Trigger 1.
+ *            TIM_TS_ITR2 - Internal Trigger 2.
+ *            TIM_TS_ITR3 - Internal Trigger 3.
+ *
+ * @return  none
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
+{
+    TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+    TIMx->SMCFGR |= TIM_SlaveMode_External1;
+}
+
+/*********************************************************************
+ * @fn      TIM_TIxExternalClockConfig
+ *
+ * @brief   Configures the TIMx Trigger as External Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_TIxExternalCLKSource - Trigger source.
+ *            TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector.
+ *            TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1.
+ *            TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2.
+ *          TIM_ICPolarity - specifies the TIx Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *             TIM_DMA_COM - TIM Commutation DMA source.
+ *             TIM_DMA_Trigger - TIM Trigger DMA source.
+ *          ICFilter - specifies the filter value.
+ *             This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+    if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+    {
+        TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+    else
+    {
+        TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+
+    TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+    TIMx->SMCFGR |= TIM_SlaveMode_External1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRClockMode1Config
+ *
+ * @brief   Configures the External clock Mode1.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *             This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
+    tmpsmcr |= TIM_SlaveMode_External1;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
+    tmpsmcr |= TIM_TS_ETRF;
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRClockMode2Config
+ *
+ * @brief   Configures the External clock Mode2.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *            This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    TIMx->SMCFGR |= TIM_ECE;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRConfig
+ *
+ * @brief   Configures the TIMx External Trigger (ETR).
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *            This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= SMCFGR_ETR_Mask;
+    tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_PrescalerConfig
+ *
+ * @brief   Configures the TIMx Prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          Prescaler - specifies the Prescaler Register value.
+ *          TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
+ *            TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
+ *            TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event.
+ *            TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately.
+ *
+ * @return  none
+ */
+void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+    TIMx->PSC = Prescaler;
+    TIMx->SWEVGR = TIM_PSCReloadMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_CounterModeConfig
+ *
+ * @brief   Specifies the TIMx Counter Mode to be used.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_CounterMode - specifies the Counter Mode to be used.
+ *            TIM_CounterMode_Up - TIM Up Counting Mode.
+ *            TIM_CounterMode_Down - TIM Down Counting Mode.
+ *            TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1.
+ *            TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2.
+ *            TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3.
+ *
+ * @return  none
+ */
+void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
+{
+    uint16_t tmpcr1 = 0;
+
+    tmpcr1 = TIMx->CTLR1;
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
+    tmpcr1 |= TIM_CounterMode;
+    TIMx->CTLR1 = tmpcr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectInputTrigger
+ *
+ * @brief   Selects the Input Trigger source.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_InputTriggerSource - The Input Trigger source.
+ *            TIM_TS_ITR0 - Internal Trigger 0.
+ *            TIM_TS_ITR1 - Internal Trigger 1.
+ *            TIM_TS_ITR2 - Internal Trigger 2.
+ *            TIM_TS_ITR3 - Internal Trigger 3.
+ *            TIM_TS_TI1F_ED - TI1 Edge Detector.
+ *            TIM_TS_TI1FP1 - Filtered Timer Input 1.
+ *            TIM_TS_TI2FP2 - Filtered Timer Input 2.
+ *            TIM_TS_ETRF - External Trigger input.
+ *
+ * @return  none
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
+{
+    uint16_t tmpsmcr = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
+    tmpsmcr |= TIM_InputTriggerSource;
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_EncoderInterfaceConfig
+ *
+ * @brief   Configures the TIMx Encoder Interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_EncoderMode - specifies the TIMx Encoder Mode.
+ *            TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending
+ *        on TI2FP2 level.
+ *            TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending
+ *        on TI1FP1 level.
+ *            TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and
+ *        TI2FP2 edges depending.
+ *          TIM_IC1Polarity - specifies the IC1 Polarity.
+ *            TIM_ICPolarity_Falling - IC Falling edge.
+ *            TTIM_ICPolarity_Rising - IC Rising edge.
+ *          TIM_IC2Polarity - specifies the IC2 Polarity.
+ *            TIM_ICPolarity_Falling - IC Falling edge.
+ *            TIM_ICPolarity_Rising - IC Rising edge.
+ *
+ * @return  none
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+    uint16_t tmpsmcr = 0;
+    uint16_t tmpccmr1 = 0;
+    uint16_t tmpccer = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
+    tmpsmcr |= TIM_EncoderMode;
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S)));
+    tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0;
+    tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P)));
+    tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+    TIMx->SMCFGR = tmpsmcr;
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC1Config
+ *
+ * @brief   Forces the TIMx output 1 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC1REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC1REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M);
+    tmpccmr1 |= TIM_ForcedAction;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC2Config
+ *
+ * @brief   Forces the TIMx output 2 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC2REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC2REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M);
+    tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC3Config
+ *
+ * @brief   Forces the TIMx output 3 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC3REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC3REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M);
+    tmpccmr2 |= TIM_ForcedAction;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC4Config
+ *
+ * @brief   Forces the TIMx output 4 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC4REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC4REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M);
+    tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ARRPreloadConfig
+ *
+ * @brief   Enables or disables TIMx peripheral Preload register on ARR.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_ARPE;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectCOM
+ *
+ * @brief   Selects the TIM peripheral Commutation event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCUS;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectCCDMA
+ *
+ * @brief   Selects the TIMx peripheral Capture Compare DMA source.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCDS;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_CCPreloadControl
+ *
+ * @brief   DSets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ *        reset values (Affects also the I2Ss).
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCPC;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR1.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE);
+    tmpccmr1 |= TIM_OCPreload;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR2.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE);
+    tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR3.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE);
+    tmpccmr2 |= TIM_OCPreload;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR4.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE);
+    tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 1 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE);
+    tmpccmr1 |= TIM_OCFast;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 2 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE);
+    tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 3 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE);
+    tmpccmr2 |= TIM_OCFast;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 4 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE);
+    tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC1Ref
+ *
+ * @brief   Clears or safeguards the OCREF1 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE);
+    tmpccmr1 |= TIM_OCClear;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC2Ref
+ *
+ * @brief   Clears or safeguards the OCREF2 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE);
+    tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC3Ref
+ *
+ * @brief   Clears or safeguards the OCREF3 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE);
+    tmpccmr2 |= TIM_OCClear;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC4Ref
+ *
+ * @brief   Clears or safeguards the OCREF4 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE);
+    tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1PolarityConfig
+ *
+ * @brief   Configures the TIMx channel 1 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPolarity - specifies the OC1 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P);
+    tmpccer |= TIM_OCPolarity;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1NPolarityConfig
+ *
+ * @brief   Configures the TIMx channel 1 polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC1N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP);
+    tmpccer |= TIM_OCNPolarity;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2PolarityConfig
+ *
+ * @brief   Configures the TIMx channel 2 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPolarity - specifies the OC2 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2NPolarityConfig
+ *
+ * @brief   Configures the TIMx channel 2 polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC1N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP);
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3PolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 3 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OCPolarit - specifies the OC3 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3NPolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 3N polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC2N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP);
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4PolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 4 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OCPolarit - specifies the OC3 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_CCxCmd
+ *
+ * @brief   Enables or disables the TIM Capture Compare Channel x.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *            TIM_Channel_4 - TIM Channel 4.
+ *          TIM_CCx - specifies the TIM Channel CCxE bit new state.
+ *            TIM_CCx_Enable.
+ *            TIM_CCx_Disable.
+ *
+ * @return  none
+ */
+void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+    uint16_t tmp = 0;
+
+    tmp = CCER_CCE_Set << TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp;
+    TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/*********************************************************************
+ * @fn      TIM_CCxNCmd
+ *
+ * @brief   Enables or disables the TIM Capture Compare Channel xN.
+ *
+ * @param   TIMx - where x can be 1 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *          TIM_CCxN - specifies the TIM Channel CCxNE bit new state.
+ *            TIM_CCxN_Enable.
+ *            TIM_CCxN_Disable.
+ *
+ * @return  none
+ */
+void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+    uint16_t tmp = 0;
+
+    tmp = CCER_CCNE_Set << TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp;
+    TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOCxM
+ *
+ * @brief   Selects the TIM Output Compare Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *            TIM_Channel_4 - TIM Channel 4.
+ *          TIM_OCMode - specifies the TIM Output Compare Mode.
+ *            TIM_OCMode_Timing.
+ *            TIM_OCMode_Active.
+ *            TIM_OCMode_Toggle.
+ *            TIM_OCMode_PWM1.
+ *            TIM_OCMode_PWM2.
+ *            TIM_ForcedAction_Active.
+ *            TIM_ForcedAction_InActive.
+ *
+ * @return  none
+ */
+void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+    uint32_t tmp = 0;
+    uint16_t tmp1 = 0;
+
+    tmp = (uint32_t)TIMx;
+    tmp += CHCTLR_Offset;
+    tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp1;
+
+    if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3))
+    {
+        tmp += (TIM_Channel >> 1);
+        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M);
+        *(__IO uint32_t *)tmp |= TIM_OCMode;
+    }
+    else
+    {
+        tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1;
+        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M);
+        *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_UpdateDisableConfig
+ *
+ * @brief   Enables or Disables the TIMx Update event.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_UDIS;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_UpdateRequestConfig
+ *
+ * @brief   Configures the TIMx Update Request Interrupt source.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_UpdateSource - specifies the Update source.
+ *            TIM_UpdateSource_Regular.
+ *            TIM_UpdateSource_Global.
+ *
+ * @return  none
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
+{
+    if(TIM_UpdateSource != TIM_UpdateSource_Global)
+    {
+        TIMx->CTLR1 |= TIM_URS;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectHallSensor
+ *
+ * @brief   Enables or disables the TIMx's Hall sensor interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_TI1S;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOnePulseMode
+ *
+ * @brief   Selects the TIMx's One Pulse Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OPMode - specifies the OPM Mode to be used.
+ *            TIM_OPMode_Single.
+ *            TIM_OPMode_Repetitive.
+ *
+ * @return  none
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
+{
+    TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
+    TIMx->CTLR1 |= TIM_OPMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOutputTrigger
+ *
+ * @brief   Selects the TIMx Trigger Output Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_TRGOSource - specifies the Trigger Output source.
+ *            TIM_TRGOSource_Reset -  The UG bit in the TIM_EGR register is
+ *        used as the trigger output (TRGO).
+ *            TIM_TRGOSource_Enable - The Counter Enable CEN is used as the
+ *        trigger output (TRGO).
+ *            TIM_TRGOSource_Update - The update event is selected as the
+ *        trigger output (TRGO).
+ *            TIM_TRGOSource_OC1 - The trigger output sends a positive pulse
+ *        when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
+ *            TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @return  none
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
+{
+    TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS);
+    TIMx->CTLR2 |= TIM_TRGOSource;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectSlaveMode
+ *
+ * @brief   Selects the TIMx Slave Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_SlaveMode - specifies the Timer Slave Mode.
+ *            TIM_SlaveMode_Reset - Rising edge of the selected trigger
+ *        signal (TRGI) re-initializes.
+ *            TIM_SlaveMode_Gated - The counter clock is enabled when the
+ *        trigger signal (TRGI) is high.
+ *            TIM_SlaveMode_Trigger - The counter starts at a rising edge
+ *        of the trigger TRGI.
+ *            TIM_SlaveMode_External1 - Rising edges of the selected trigger
+ *        (TRGI) clock the counter.
+ *
+ * @return  none
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
+{
+    TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS);
+    TIMx->SMCFGR |= TIM_SlaveMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectMasterSlaveMode
+ *
+ * @brief   Sets or Resets the TIMx Master/Slave Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_MasterSlaveMode - specifies the Timer Master Slave Mode.
+ *            TIM_MasterSlaveMode_Enable - synchronization between the current
+ *        timer and its slaves (through TRGO).
+ *            TIM_MasterSlaveMode_Disable - No action.
+ *
+ * @return  none
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
+{
+    TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM);
+    TIMx->SMCFGR |= TIM_MasterSlaveMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCounter
+ *
+ * @brief   Sets the TIMx Counter Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Counter - specifies the Counter register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter)
+{
+    TIMx->CNT = Counter;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetAutoreload
+ *
+ * @brief   Sets the TIMx Autoreload Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Autoreload - specifies the Autoreload register new value.
+ *
+ * @return  none
+ */
+void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload)
+{
+    TIMx->ATRLR = Autoreload;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare1
+ *
+ * @brief   Sets the TIMx Capture Compare1 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1)
+{
+    TIMx->CH1CVR = Compare1;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare2
+ *
+ * @brief   Sets the TIMx Capture Compare2 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2)
+{
+    TIMx->CH2CVR = Compare2;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare3
+ *
+ * @brief   Sets the TIMx Capture Compare3 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3)
+{
+    TIMx->CH3CVR = Compare3;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare4
+ *
+ * @brief   Sets the TIMx Capture Compare4 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4)
+{
+    TIMx->CH4CVR = Compare4;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC1Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 1 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC);
+    TIMx->CHCTLR1 |= TIM_ICPSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC2Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 2 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC);
+    TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC3Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 3 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC);
+    TIMx->CHCTLR2 |= TIM_ICPSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC4Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 4 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC);
+    TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/*********************************************************************
+ * @fn      TIM_SetClockDivision
+ *
+ * @brief   Sets the TIMx Clock Division value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_CKD - specifies the clock division value.
+ *            TIM_CKD_DIV1 - TDTS = Tck_tim.
+ *            TIM_CKD_DIV2 - TDTS = 2*Tck_tim.
+ *            TIM_CKD_DIV4 - TDTS = 4*Tck_tim.
+ *
+ * @return  none
+ */
+void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
+{
+    TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD);
+    TIMx->CTLR1 |= TIM_CKD;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture1
+ *
+ * @brief   Gets the TIMx Input Capture 1 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH1CVR - Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH1CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture2
+ *
+ * @brief   Gets the TIMx Input Capture 2 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH2CVR - Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH2CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture3
+ *
+ * @brief   Gets the TIMx Input Capture 3 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH3CVR - Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH3CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture4
+ *
+ * @brief   Gets the TIMx Input Capture 4 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH4CVR - Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH4CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCounter
+ *
+ * @brief   Gets the TIMx Counter value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CNT - Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+    return TIMx->CNT;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetPrescaler
+ *
+ * @brief   Gets the TIMx Prescaler value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->PSC - Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+    return TIMx->PSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetFlagStatus
+ *
+ * @brief   Checks whether the specified TIM flag is set or not.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_FLAG - specifies the flag to check.
+ *            TIM_FLAG_Update - TIM update Flag.
+ *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
+ *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
+ *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
+ *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
+ *            TIM_FLAG_COM - TIM Commutation Flag.
+ *            TIM_FLAG_Trigger - TIM Trigger Flag.
+ *            TIM_FLAG_Break - TIM Break Flag.
+ *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
+ *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
+ *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
+ *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
+ *
+ * @return  none
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
+{
+    ITStatus bitstatus = RESET;
+
+    if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearFlag
+ *
+ * @brief   Clears the TIMx's pending flags.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_FLAG - specifies the flag to check.
+ *            TIM_FLAG_Update - TIM update Flag.
+ *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
+ *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
+ *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
+ *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
+ *            TIM_FLAG_COM - TIM Commutation Flag.
+ *            TIM_FLAG_Trigger - TIM Trigger Flag.
+ *            TIM_FLAG_Break - TIM Break Flag.
+ *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
+ *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
+ *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
+ *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
+ *
+ * @return  none
+ */
+void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
+{
+    TIMx->INTFR = (uint16_t)~TIM_FLAG;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetITStatus
+ *
+ * @brief   Checks whether the TIM interrupt has occurred or not.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupt source to check.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *
+ * @return  none
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itstatus = 0x0, itenable = 0x0;
+
+    itstatus = TIMx->INTFR & TIM_IT;
+
+    itenable = TIMx->DMAINTENR & TIM_IT;
+    if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearITPendingBit
+ *
+ * @brief   Clears the TIMx's interrupt pending bits.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupt source to check.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *
+ * @return  none
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
+{
+    TIMx->INTFR = (uint16_t)~TIM_IT;
+}
+
+/*********************************************************************
+ * @fn      TI1_Config
+ *
+ * @brief   Configure the TI1 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E);
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F)));
+    tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) ||
+       (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);
+    }
+
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI2_Config
+ *
+ * @brief   Configure the TI2 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E);
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 4);
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F)));
+    tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+    tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) ||
+       (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E);
+    }
+
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI3_Config
+ *
+ * @brief   Configure the TI3 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E);
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 8);
+    tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F)));
+    tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) ||
+       (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E);
+    }
+
+    TIMx->CHCTLR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI4_Config
+ *
+ * @brief   Configure the TI4 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E);
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 12);
+    tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F)));
+    tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+    tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) ||
+       (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E);
+    }
+
+    TIMx->CHCTLR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_usart.c

@@ -0,0 +1,826 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_usart.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the USART firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_usart.h"
+#include "ch32v30x_rcc.h"
+
+/* USART_Private_Defines */
+#define CTLR1_UE_Set              ((uint16_t)0x2000) /* USART Enable Mask */
+#define CTLR1_UE_Reset            ((uint16_t)0xDFFF) /* USART Disable Mask */
+
+#define CTLR1_WAKE_Mask           ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
+
+#define CTLR1_RWU_Set             ((uint16_t)0x0002) /* USART mute mode Enable Mask */
+#define CTLR1_RWU_Reset           ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
+#define CTLR1_SBK_Set             ((uint16_t)0x0001) /* USART Break Character send Mask */
+#define CTLR1_CLEAR_Mask          ((uint16_t)0xE9F3) /* USART CR1 Mask */
+#define CTLR2_Address_Mask        ((uint16_t)0xFFF0) /* USART address Mask */
+
+#define CTLR2_LINEN_Set           ((uint16_t)0x4000) /* USART LIN Enable Mask */
+#define CTLR2_LINEN_Reset         ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
+
+#define CTLR2_LBDL_Mask           ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
+#define CTLR2_STOP_CLEAR_Mask     ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
+#define CTLR2_CLOCK_CLEAR_Mask    ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
+
+#define CTLR3_SCEN_Set            ((uint16_t)0x0020) /* USART SC Enable Mask */
+#define CTLR3_SCEN_Reset          ((uint16_t)0xFFDF) /* USART SC Disable Mask */
+
+#define CTLR3_NACK_Set            ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
+#define CTLR3_NACK_Reset          ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
+
+#define CTLR3_HDSEL_Set           ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
+#define CTLR3_HDSEL_Reset         ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
+
+#define CTLR3_IRLP_Mask           ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
+#define CTLR3_CLEAR_Mask          ((uint16_t)0xFCFF) /* USART CR3 Mask */
+
+#define CTLR3_IREN_Set            ((uint16_t)0x0002) /* USART IrDA Enable Mask */
+#define CTLR3_IREN_Reset          ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
+#define GPR_LSB_Mask              ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
+#define GPR_MSB_Mask              ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
+#define IT_Mask                   ((uint16_t)0x001F) /* USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTLR1_OVER8_Set           ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
+#define CTLR1_OVER8_Reset         ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTLR3_ONEBITE_Set         ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
+#define CTLR3_ONEBITE_Reset       ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
+
+/*********************************************************************
+ * @fn      USART_DeInit
+ *
+ * @brief   Deinitializes the USARTx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *
+ * @return  none
+ */
+void USART_DeInit(USART_TypeDef *USARTx)
+{
+    if(USARTx == USART1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+    }
+    else if(USARTx == USART2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+    }
+    else if(USARTx == USART3)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+    }
+    else if(USARTx == UART4)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+    }
+    else if(USARTx == UART5)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+    }
+    else if(USARTx == UART6)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE);
+    }
+    else if(USARTx == UART7)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
+    }
+    else if(USARTx == UART8)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_Init
+ *
+ * @brief   Initializes the USARTx peripheral according to the specified
+ *        parameters in the USART_InitStruct.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *          USART_InitStruct - pointer to a USART_InitTypeDef structure
+ *        that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
+{
+    uint32_t          tmpreg = 0x00, apbclock = 0x00;
+    uint32_t          integerdivider = 0x00;
+    uint32_t          fractionaldivider = 0x00;
+    uint32_t          usartxbase = 0;
+    RCC_ClocksTypeDef RCC_ClocksStatus;
+
+    if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+    {
+    }
+
+    usartxbase = (uint32_t)USARTx;
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_STOP_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+    USARTx->CTLR2 = (uint16_t)tmpreg;
+    tmpreg = USARTx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+              USART_InitStruct->USART_Mode;
+    USARTx->CTLR1 = (uint16_t)tmpreg;
+
+    tmpreg = USARTx->CTLR3;
+    tmpreg &= CTLR3_CLEAR_Mask;
+    tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+    USARTx->CTLR3 = (uint16_t)tmpreg;
+
+    RCC_GetClocksFreq(&RCC_ClocksStatus);
+
+    if(usartxbase == USART1_BASE)
+    {
+        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+    }
+    else
+    {
+        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+    }
+
+    if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+    {
+        integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
+    }
+    else
+    {
+        integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
+    }
+    tmpreg = (integerdivider / 100) << 4;
+
+    fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+    if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+    {
+        tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+    }
+    else
+    {
+        tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+    }
+
+    USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_StructInit
+ *
+ * @brief   Fills each USART_InitStruct member with its default value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
+{
+    USART_InitStruct->USART_BaudRate = 9600;
+    USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+    USART_InitStruct->USART_StopBits = USART_StopBits_1;
+    USART_InitStruct->USART_Parity = USART_Parity_No;
+    USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockInit
+ *
+ * @brief   Initializes the USARTx peripheral Clock according to the
+ *        specified parameters in the USART_ClockInitStruct .
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+              USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+    USARTx->CTLR2 = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockStructInit
+ *
+ * @brief   Fills each USART_ClockStructInit member with its default value.
+ *
+ * @param   USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+    USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+    USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+    USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+    USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*********************************************************************
+ * @fn      USART_Cmd
+ *
+ * @brief   Enables or disables the specified USART peripheral.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_UE_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_UE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_ITConfig
+ *
+ * @brief   Enables or disables the specified USART interrupts.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt sources to be enabled or disabled.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Transmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *            USART_IT_ERR - Error interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+    uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+    uint32_t usartxbase = 0x00;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    usartxbase = (uint32_t)USARTx;
+    usartreg = (((uint8_t)USART_IT) >> 0x05);
+    itpos = USART_IT & IT_Mask;
+    itmask = (((uint32_t)0x01) << itpos);
+
+    if(usartreg == 0x01)
+    {
+        usartxbase += 0x0C;
+    }
+    else if(usartreg == 0x02)
+    {
+        usartxbase += 0x10;
+    }
+    else
+    {
+        usartxbase += 0x14;
+    }
+
+    if(NewState != DISABLE)
+    {
+        *(__IO uint32_t *)usartxbase |= itmask;
+    }
+    else
+    {
+        *(__IO uint32_t *)usartxbase &= ~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_DMACmd
+ *
+ * @brief   Enables or disables the USART DMA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_DMAReq - specifies the DMA request.
+ *            USART_DMAReq_Tx - USART DMA transmit request.
+ *            USART_DMAReq_Rx - USART DMA receive request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= USART_DMAReq;
+    }
+    else
+    {
+        USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SetAddress
+ *
+ * @brief   Sets the address of the USART node.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Address - Indicates the address of the USART node.
+ *
+ * @return  none
+ */
+void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
+{
+    USARTx->CTLR2 &= CTLR2_Address_Mask;
+    USARTx->CTLR2 |= USART_Address;
+}
+
+/*********************************************************************
+ * @fn      USART_WakeUpConfig
+ *
+ * @brief   Selects the USART WakeUp method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_WakeUp - specifies the USART wakeup method.
+ *            USART_WakeUp_IdleLine - WakeUp by an idle line detection.
+ *            USART_WakeUp_AddressMark - WakeUp by an address mark.
+ *
+ * @return  none
+ */
+void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
+{
+    USARTx->CTLR1 &= CTLR1_WAKE_Mask;
+    USARTx->CTLR1 |= USART_WakeUp;
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiverWakeUpCmd
+ *
+ * @brief   Determines if the USART is in mute mode or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_RWU_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_RWU_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_LINBreakDetectLengthConfig
+ *
+ * @brief   Sets the USART LIN Break detection length.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_LINBreakDetectLength - specifies the LIN break detection length.
+ *            USART_LINBreakDetectLength_10b - 10-bit break detection.
+ *            USART_LINBreakDetectLength_11b - 11-bit break detection.
+ *
+ * @return  none
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
+{
+    USARTx->CTLR2 &= CTLR2_LBDL_Mask;
+    USARTx->CTLR2 |= USART_LINBreakDetectLength;
+}
+
+/*********************************************************************
+ * @fn      USART_LINCmd
+ *
+ * @brief   Enables or disables the USART LIN mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR2 |= CTLR2_LINEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR2 &= CTLR2_LINEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SendData
+ *
+ * @brief   Transmits single data through the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          Data - the data to transmit.
+ *
+ * @return  none
+ */
+void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
+{
+    USARTx->DATAR = (Data & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
+{
+    return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_SendBreak
+ *
+ * @brief   Transmits break characters.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  none
+ */
+void USART_SendBreak(USART_TypeDef *USARTx)
+{
+    USARTx->CTLR1 |= CTLR1_SBK_Set;
+}
+
+/*********************************************************************
+ * @fn      USART_SetGuardTime
+ *
+ * @brief   Sets the specified USART guard time.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_GuardTime - specifies the guard time.
+ *
+ * @return  none
+ */
+void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
+{
+    USARTx->GPR &= GPR_LSB_Mask;
+    USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/*********************************************************************
+ * @fn      USART_SetPrescaler
+ *
+ * @brief   Sets the system clock prescaler.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Prescaler - specifies the prescaler clock.
+ *
+ * @return  none
+ */
+void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
+{
+    USARTx->GPR &= GPR_MSB_Mask;
+    USARTx->GPR |= USART_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardCmd
+ *
+ * @brief   Enables or disables the USART Smart Card mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_SCEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_SCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardNACKCmd
+ *
+ * @brief   Enables or disables NACK transmission.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_NACK_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_NACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_HalfDuplexCmd
+ *
+ * @brief   Enables or disables the USART Half Duplex communication.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *                  NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_HDSEL_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OverSampling8Cmd
+ *
+ * @brief   Enables or disables the USART's 8x oversampling mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_OVER8_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_OVER8_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OneBitMethodCmd
+ *
+ * @brief   Enables or disables the USART's one bit sampling method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_IrDAConfig
+ *
+ * @brief   Configures the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IrDAMode - specifies the IrDA mode.
+ *            USART_IrDAMode_LowPower.
+ *            USART_IrDAMode_Normal.
+ *
+ * @return  none
+ */
+void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
+{
+    USARTx->CTLR3 &= CTLR3_IRLP_Mask;
+    USARTx->CTLR3 |= USART_IrDAMode;
+}
+
+/*********************************************************************
+ * @fn      USART_IrDACmd
+ *
+ * @brief   Enables or disables the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_IREN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_IREN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_GetFlagStatus
+ *
+ * @brief   Checks whether the specified USART flag is set or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to check.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TXE - Transmit data register empty flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *            USART_FLAG_IDLE - Idle Line detection flag.
+ *            USART_FLAG_ORE - OverRun Error flag.
+ *            USART_FLAG_NE - Noise Error flag.
+ *            USART_FLAG_FE - Framing Error flag.
+ *            USART_FLAG_PE - Parity Error flag.
+ *
+ * @return  none
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(USART_FLAG == USART_FLAG_CTS)
+    {
+    }
+
+    if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearFlag
+ *
+ * @brief   Clears the USARTx's pending flags.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to clear.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *
+ * @return  none
+ */
+void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
+{
+    if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+    {
+    }
+
+    USARTx->STATR = (uint16_t)~USART_FLAG;
+}
+
+/*********************************************************************
+ * @fn      USART_GetITStatus
+ *
+ * @brief   Checks whether the specified USART interrupt has occurred or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt source to check.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Tansmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
+ *            USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
+ *            USART_IT_NE - Noise Error interrupt.
+ *            USART_IT_FE - Framing Error interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *
+ * @return  none
+ */
+ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
+{
+    uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+    ITStatus bitstatus = RESET;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    usartreg = (((uint8_t)USART_IT) >> 0x05);
+    itmask = USART_IT & IT_Mask;
+    itmask = (uint32_t)0x01 << itmask;
+
+    if(usartreg == 0x01)
+    {
+        itmask &= USARTx->CTLR1;
+    }
+    else if(usartreg == 0x02)
+    {
+        itmask &= USARTx->CTLR2;
+    }
+    else
+    {
+        itmask &= USARTx->CTLR3;
+    }
+
+    bitpos = USART_IT >> 0x08;
+    bitpos = (uint32_t)0x01 << bitpos;
+    bitpos &= USARTx->STATR;
+
+    if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearITPendingBit
+ *
+ * @brief   Clears the USARTx's interrupt pending bits.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the interrupt pending bit to clear.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *
+ * @return  none
+ */
+void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
+{
+    uint16_t bitpos = 0x00, itmask = 0x00;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    bitpos = USART_IT >> 0x08;
+    itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+    USARTx->STATR = (uint16_t)~itmask;
+}

bsp/wch/risc-v/Libraries/ch32v30x_libraries/ch32v307_hal/source/ch32v30x_wwdg.c

@@ -0,0 +1,139 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_wwdg.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the WWDG firmware functions.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+**********************************************************************************/
+#include "ch32v30x_wwdg.h"
+#include "ch32v30x_rcc.h"
+
+/* CTLR register bit mask */
+#define CTLR_WDGA_Set      ((uint32_t)0x00000080)
+
+/* CFGR register bit mask */
+#define CFGR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
+#define CFGR_W_Mask        ((uint32_t)0xFFFFFF80)
+#define BIT_Mask           ((uint8_t)0x7F)
+
+/*********************************************************************
+ * @fn      WWDG_DeInit
+ *
+ * @brief   Deinitializes the WWDG peripheral registers to their default reset values
+ *
+ * @return  none
+ */
+void WWDG_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetPrescaler
+ *
+ * @brief   Sets the WWDG Prescaler
+ *
+ * @param   WWDG_Prescaler - specifies the WWDG Prescaler
+ *            WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
+ *            WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
+ *            WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
+ *            WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
+ *
+ * @return  none
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
+    tmpreg |= WWDG_Prescaler;
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetWindowValue
+ *
+ * @brief   Sets the WWDG window value
+ *
+ * @param   WindowValue - specifies the window value to be compared to the
+ *        downcounter,which must be lower than 0x80
+ *
+ * @return  none
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+    __IO uint32_t tmpreg = 0;
+
+    tmpreg = WWDG->CFGR & CFGR_W_Mask;
+
+    tmpreg |= WindowValue & (uint32_t)BIT_Mask;
+
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_EnableIT
+ *
+ * @brief   Enables the WWDG Early Wakeup interrupt(EWI)
+ *
+ * @return  none
+ */
+void WWDG_EnableIT(void)
+{
+    WWDG->CFGR |= (1 << 9);
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetCounter
+ *
+ * @brief   Sets the WWDG counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ *
+ * @return  none
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+    WWDG->CTLR = Counter & BIT_Mask;
+}
+
+/*********************************************************************
+ * @fn      WWDG_Enable
+ *
+ * @brief   Enables WWDG and load the counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ * @return  none
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+    WWDG->CTLR = CTLR_WDGA_Set | Counter;
+}
+
+/*********************************************************************
+ * @fn      WWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the Early Wakeup interrupt flag is set or not
+ *
+ * @return  The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+    return (FlagStatus)(WWDG->STATR);
+}
+
+/*********************************************************************
+ * @fn      WWDG_ClearFlag
+ *
+ * @brief   Clears Early Wakeup interrupt flag
+ *
+ * @return  none
+ */
+void WWDG_ClearFlag(void)
+{
+    WWDG->STATR = (uint32_t)RESET;
+}