update lm3s Libraries

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1118 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/lm3s/Libraries/SConscript

@@ -1,8 +1,9 @@
-Import('env')
 Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
 
 # The set of source files associated with this SConscript file.
-src_local = Split("""
+src = Split("""
 	driverlib/adc.c
 	driverlib/can.c
 	driverlib/comp.c
@@ -28,10 +29,8 @@ src_local = Split("""
 	driverlib/watchdog.c
 """)
 
-path = [RTT_ROOT + '/bsp/lm3s/Libraries/inc', RTT_ROOT + '/bsp/lm3s/Libraries', RTT_ROOT + '/bsp/lm3s/Libraries/driverlib']
+CPPPATH = [RTT_ROOT + '/bsp/lm3s/Libraries/inc', RTT_ROOT + '/bsp/lm3s/Libraries', RTT_ROOT + '/bsp/lm3s/Libraries/driverlib']
 
-env.Append(CPPPATH = path)
+group = DefineGroup('library', src, depend = [''], CPPPATH = CPPPATH)
 
-obj = env.Object(src_local)
-
-Return('obj')
+Return('group')

bsp/lm3s/Libraries/driverlib/adc.c

@@ -2,26 +2,23 @@
 //
 // adc.c - Driver for the ADC.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -52,6 +49,8 @@
 #define ADC_SSCTL               (ADC_O_SSCTL0 - ADC_O_SSMUX0)
 #define ADC_SSFIFO              (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
 #define ADC_SSFSTAT             (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
+#define ADC_SSOP                (ADC_O_SSOP0 - ADC_O_SSMUX0)
+#define ADC_SSDC                (ADC_O_SSDC0 - ADC_O_SSMUX0)
 
 //*****************************************************************************
 //
@@ -97,7 +96,8 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
     //
     // Determine the interrupt to register based on the sequence number.
     //
-    ulInt = INT_ADC0 + ulSequenceNum;
+    ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
+             (INT_ADC1SS0 + ulSequenceNum));
 
     //
     // Register the interrupt handler.
@@ -141,7 +141,8 @@ ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
     //
     // Determine the interrupt to unregister based on the sequence number.
     //
-    ulInt = INT_ADC0 + ulSequenceNum;
+    ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
+             (INT_ADC1SS0 + ulSequenceNum));
 
     //
     // Disable the interrupt.
@@ -235,6 +236,8 @@ unsigned long
 ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
              tBoolean bMasked)
 {
+    unsigned long ulTemp;
+
     //
     // Check the arguments.
     //
@@ -247,12 +250,27 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
     //
     if(bMasked)
     {
-        return(HWREG(ulBase + ADC_O_ISC) & (1 << ulSequenceNum));
+        ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum);
     }
     else
     {
-        return(HWREG(ulBase + ADC_O_RIS) & (1 << ulSequenceNum));
+        ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
+
+        //
+        // If the digital comparator status bit is set, reflect it to the 
+        // appropriate sequence bit.
+        //
+        if(ulTemp & 0x10000)
+        {
+            ulTemp |= 0xF0000;
+            ulTemp &= ~(0x10000 << ulSequenceNum);
+        }
     }
+
+    //
+    // Return the interrupt status
+    //
+    return(ulTemp);
 }
 
 //*****************************************************************************
@@ -386,6 +404,8 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
 //!                         configured with PWMGenIntTrigEnable().
 //! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
 //!                         configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator;
+//!                         configured with PWMGenIntTrigEnable().
 //! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
 //!                           sample sequence to capture repeatedly (so long as
 //!                           there is not a higher priority source active).
@@ -420,6 +440,7 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
            (ulTrigger == ADC_TRIGGER_PWM0) ||
            (ulTrigger == ADC_TRIGGER_PWM1) ||
            (ulTrigger == ADC_TRIGGER_PWM2) ||
+           (ulTrigger == ADC_TRIGGER_PWM3) ||
            (ulTrigger == ADC_TRIGGER_ALWAYS));
     ASSERT(ulPriority < 4);
 
@@ -452,18 +473,29 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
 //! \param ulStep is the step to be configured.
 //! \param ulConfig is the configuration of this step; must be a logical OR of
 //! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
-//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH7).
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15).  For parts
+//! with the digital comparator feature, the follow values may also be OR'd
+//! into the \e ulConfig value to enable the digital comparater feature:
+//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
+//! \b ADC_CTL_CMP7).
 //!
 //! This function will set the configuration of the ADC for one step of a
 //! sample sequence.  The ADC can be configured for single-ended or
 //! differential operation (the \b ADC_CTL_D bit selects differential
 //! operation when set), the channel to be sampled can be chosen (the
-//! \b ADC_CTL_CH0 through \b ADC_CTL_CH7 values), and the internal temperature
-//! sensor can be selected (the \b ADC_CTL_TS bit).  Additionally, this step
-//! can be defined as the last in the sequence (the \b ADC_CTL_END bit) and it
-//! can be configured to cause an interrupt when the step is complete (the
-//! \b ADC_CTL_IE bit).  The configuration is used by the ADC at the
-//! appropriate time when the trigger for this sequence occurs.
+//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
+//! temperature sensor can be selected (the \b ADC_CTL_TS bit).  Additionally,
+//! this step can be defined as the last in the sequence (the \b ADC_CTL_END
+//! bit) and it can be configured to cause an interrupt when the step is
+//! complete (the \b ADC_CTL_IE bit).  If the digital comparators are present
+//! on the device, this step may also be configured send the ADC sample to
+//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
+//! values) by using the \b ADC_CTL_CE bit.  The configuration is used by the
+//! ADC at the appropriate time when the trigger for this sequence occurs.
+//!
+//! \note If the Digitial Comparator is present and enabled using the
+//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
+//! sequence data FIFO.
 //!
 //! The \e ulStep parameter determines the order in which the samples are
 //! captured by the ADC when the trigger occurs.  It can range from zero to
@@ -488,6 +520,8 @@ void
 ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
                          unsigned long ulStep, unsigned long ulConfig)
 {
+    unsigned long ulTemp;
+
     //
     // Check the arugments.
     //
@@ -521,6 +555,37 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
     HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
                                   ~(0x0000000f << ulStep)) |
                                  (((ulConfig & 0xf0) >> 4) << ulStep));
+
+    //
+    // Enable digital comparator if specified in the ulConfig bit-fields.
+    //
+    if(ulConfig & 0x000F0000)
+    {
+        //
+        // Program the comparator for the specified step.
+        //
+        ulTemp = HWREG(ulBase + ADC_SSDC);
+        ulTemp &= ~(0xF << ulStep);
+        ulTemp |= (((ulConfig & 0x00070000) >> 16) << ulStep);
+        HWREG(ulBase + ADC_SSDC) = ulTemp;
+
+        //
+        // Enable the comparator.
+        //
+        ulTemp = HWREG(ulBase + ADC_SSOP);
+        ulTemp |= (1 << ulStep);
+        HWREG(ulBase + ADC_SSOP) = ulTemp;
+    }
+
+    //
+    // Disable digital comparator if not specified.
+    //
+    else
+    {
+        ulTemp = HWREG(ulBase + ADC_SSOP);
+        ulTemp &= ~(1 << ulStep);
+        HWREG(ulBase + ADC_SSOP) = ulTemp;
+    }
 }
 
 //*****************************************************************************
@@ -703,10 +768,16 @@ ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
 //! Causes a processor trigger for a sample sequence.
 //!
 //! \param ulBase is the base address of the ADC module.
-//! \param ulSequenceNum is the sample sequence number.
+//! \param ulSequenceNum is the sample sequence number, with
+//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it.
 //!
 //! This function triggers a processor-initiated sample sequence if the sample
-//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.
+//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR.  If
+//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the
+//! processor-initiated trigger is delayed until a later processor-initiated
+//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL,
+//! allowing multiple ADCs to start from a processor-initiated trigger in a
+//! synchronous manner.
 //!
 //! \return None.
 //
@@ -718,12 +789,13 @@ ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
     // Check the arguments.
     //
     ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
-    ASSERT(ulSequenceNum < 4);
+    ASSERT((ulSequenceNum & 0xf) < 4);
 
     //
     // Generate a processor trigger for this sample sequence.
     //
-    HWREG(ulBase + ADC_O_PSSI) = 1 << ulSequenceNum;
+    HWREG(ulBase + ADC_O_PSSI) = ((ulSequenceNum & 0xffff0000) |
+                                  (1 << (ulSequenceNum & 0xf)));
 }
 
 //*****************************************************************************
@@ -971,6 +1043,425 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
     HWREG(ulBase + ADC_O_SAC) = ulValue;
 }
 
+//*****************************************************************************
+//
+//! Configures an ADC digital comparator.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulConfig is the configuration of the comparator.
+//!
+//! This function will configure a comparator.  The \e ulConfig parameter is
+//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
+//! \b ADC_COMP_INT_xxx values.
+//!
+//! The \b ADC_COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
+//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band.
+//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the low-band.
+//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into low-band only if ADC output has been in the
+//! high-band since the last trigger output.
+//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the mid-band.
+//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the mid-band.
+//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into high-band only if ADC output has been in the
+//! low-band since the last trigger output.
+//!
+//! The \b ADC_COMP_INT_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
+//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band.
+//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the low-band.
+//! - \b ADC_COMP__INT_LOW_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
+//! transitions into low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the mid-band.
+//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the mid-band.
+//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band.
+//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the high-band.
+//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
+//! transitions into high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+                       unsigned long ulConfig)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT(ulComp < 8);
+
+    //
+    // Save the new setting.
+    //
+    HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Defines the ADC digital comparator regions.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulLowRef is the reference point for the low/mid band threshold.
+//! \param ulHighRef is the reference point for the mid/high band threshold.
+//!
+//! The ADC digital comparator operation is based on three ADC value regions:
+//! - \b low-band is defined as any ADC value less than or equal to the
+//! \e ulLowRef value.
+//! - \b mid-band is defined as any ADC value greater than the \e ulLowRef
+//! value but less than or equal to the \e ulHighRef value.
+//! - \b high-band is defined as any ADC value greater than the \e ulHighRef
+//! value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
+                       unsigned long ulLowRef, unsigned long ulHighRef)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT(ulComp < 8);
+    ASSERT((ulLowRef < 1024) && (ulLowRef <= ulHighRef));
+    ASSERT(ulHighRef < 1024);
+
+    //
+    // Save the new region settings.
+    //
+    HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef;
+}
+
+//*****************************************************************************
+//
+//! Resets the current ADC digital comparator conditions.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator.
+//! \param bTrigger is the flag to indicate reset of Trigger conditions.
+//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
+//!
+//! Because the digital comparator uses current and previous ADC values, this
+//! function is provide to allow the comparator to be reset to its initial
+//! value to prevent stale data from being used when a sequence is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
+                   tBoolean bTrigger, tBoolean bInterrupt)
+{
+    unsigned long ulTemp = 0;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT(ulComp < 8);
+
+    //
+    // Set the appropriate bits to reset the trigger and/or interrupt
+    // comparator conditions.
+    //
+    if(bTrigger)
+    {
+        ulTemp |= (1 << (16 + ulComp));
+    }
+    if(bInterrupt)
+    {
+        ulTemp |= (1 << ulComp);
+    }
+
+    HWREG(ulBase + ADC_O_DCRIC) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence comparator interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT(ulSequenceNum < 4);
+
+    //
+    // Disable this sample sequence comparator interrupt.
+    //
+    HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence comparator interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT(ulSequenceNum < 4);
+
+    //
+    // Enable this sample sequence interrupt.
+    //
+    HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator interrupt status.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! This returns the digitial comparator interrupt status bits.  This status
+//! is sequence agnostic.
+//!
+//! \return The current comparator interrupt status.
+//
+//*****************************************************************************
+unsigned long
+ADCComparatorIntStatus(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Return the digitial comparator interrupt status.
+    //
+    return(HWREG(ulBase + ADC_O_DCISC));
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence comparator interrupt source.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulStatus is the bit-mapped interrupts status to clear.
+//!
+//! The specified interrupt status is cleared.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Clear the interrupt.
+    //
+    HWREG(ulBase + ADC_O_DCISC) = ulStatus;
+}
+
+//*****************************************************************************
+//
+//! Selects the ADC reference.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulRef is the reference to use.
+//!
+//! The ADC reference is set as specified by \e ulRef.  It must be one of
+//! \b ADC_REF_INT or \b ADC_REF_EXT_3V, for internal or external reference.
+//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and
+//! no external reference is needed.  If \b ADC_REF_EXT_3V is chosen, then a 3V
+//! reference must be supplied to the AVREF pin.
+//!
+//! \note The ADC reference can only be selected on parts that have an external
+//! reference.  Consult the data sheet for your part to determine if there is
+//! an external reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V));
+
+    //
+    // Set the reference.
+    //
+    HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) |
+                                ulRef;
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting of the ADC reference.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! Returns the value of the ADC reference setting.  The returned value will be
+//! one of \b ADC_REF_INT or \b ADC_REF_EXT_3V.
+//!
+//! \note The value returned by this function is only meaningful if used on a
+//! part that is capable of using an external reference.  Consult the data
+//! sheet for your part to determine if it has an external reference input.
+//!
+//! \return The current setting of the ADC reference.
+//
+//*****************************************************************************
+unsigned long
+ADCReferenceGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Return the value of the reference.
+    //
+    return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF);
+}
+
+//*****************************************************************************
+//
+//! Sets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulPhase is the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//!
+//! This function sets the phase delay between the detection of an ADC trigger
+//! event and the start of the sample sequence.  By selecting a different phase
+//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and
+//! \b ADC_PHASE_180) and having each ADC module sample the same analog input,
+//! it is possible to increase the sampling rate of the analog input (with
+//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1,
+//! N+3, N+5, and so on, coming from the second ADC).  The ADC module has a
+//! single phase delay that is applied to all sample sequences within that
+//! module.
+//!
+//! \note This capability is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+    ASSERT((ulPhase == ADC_PHASE_0) || (ulPhase == ADC_PHASE_22_5) ||
+           (ulPhase == ADC_PHASE_45) || (ulPhase == ADC_PHASE_67_5) ||
+           (ulPhase == ADC_PHASE_90) || (ulPhase == ADC_PHASE_112_5) ||
+           (ulPhase == ADC_PHASE_135) || (ulPhase == ADC_PHASE_157_5) ||
+           (ulPhase == ADC_PHASE_180) || (ulPhase == ADC_PHASE_202_5) ||
+           (ulPhase == ADC_PHASE_225) || (ulPhase == ADC_PHASE_247_5) ||
+           (ulPhase == ADC_PHASE_270) || (ulPhase == ADC_PHASE_292_5) ||
+           (ulPhase == ADC_PHASE_315) || (ulPhase == ADC_PHASE_337_5));
+
+    //
+    // Set the phase delay.
+    //
+    HWREG(ulBase + ADC_O_SPC) = ulPhase;
+}
+
+//*****************************************************************************
+//
+//! Gets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! This function gets the current phase delay between the detection of an ADC
+//! trigger event and the start of the sample sequence.
+//!
+//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//
+//*****************************************************************************
+unsigned long
+ADCPhaseDelayGet(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+    //
+    // Return the phase delay.
+    //
+    return(HWREG(ulBase + ADC_O_SPC));
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.

bsp/lm3s/Libraries/driverlib/adc.h

@@ -2,26 +2,23 @@
 //
 // adc.h - ADC headers for using the ADC driver functions.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -54,6 +51,7 @@ extern "C"
 #define ADC_TRIGGER_PWM0        0x00000006  // PWM0 event
 #define ADC_TRIGGER_PWM1        0x00000007  // PWM1 event
 #define ADC_TRIGGER_PWM2        0x00000008  // PWM2 event
+#define ADC_TRIGGER_PWM3        0x00000009  // PWM3 event
 #define ADC_TRIGGER_ALWAYS      0x0000000F  // Always event
 
 //*****************************************************************************
@@ -82,6 +80,99 @@ extern "C"
 #define ADC_CTL_CH13            0x0000000D  // Input channel 13
 #define ADC_CTL_CH14            0x0000000E  // Input channel 14
 #define ADC_CTL_CH15            0x0000000F  // Input channel 15
+#define ADC_CTL_CMP0            0x00080000  // Select Comparator 0
+#define ADC_CTL_CMP1            0x00090000  // Select Comparator 1
+#define ADC_CTL_CMP2            0x000A0000  // Select Comparator 2
+#define ADC_CTL_CMP3            0x000B0000  // Select Comparator 3
+#define ADC_CTL_CMP4            0x000C0000  // Select Comparator 4
+#define ADC_CTL_CMP5            0x000D0000  // Select Comparator 5
+#define ADC_CTL_CMP6            0x000E0000  // Select Comparator 6
+#define ADC_CTL_CMP7            0x000F0000  // Select Comparator 7
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCComparatorConfigure as part of the
+// ulConfig parameter.
+//
+//*****************************************************************************
+#define ADC_COMP_TRIG_NONE      0x00000000  // Trigger Disabled
+#define ADC_COMP_TRIG_LOW_ALWAYS \
+                                0x00001000  // Trigger Low Always
+#define ADC_COMP_TRIG_LOW_ONCE  0x00001100  // Trigger Low Once
+#define ADC_COMP_TRIG_LOW_HALWAYS \
+                                0x00001200  // Trigger Low Always (Hysteresis)
+#define ADC_COMP_TRIG_LOW_HONCE 0x00001300  // Trigger Low Once (Hysteresis)
+#define ADC_COMP_TRIG_MID_ALWAYS \
+                                0x00001400  // Trigger Mid Always
+#define ADC_COMP_TRIG_MID_ONCE  0x00001500  // Trigger Mid Once
+#define ADC_COMP_TRIG_HIGH_ALWAYS \
+                                0x00001C00  // Trigger High Always
+#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00  // Trigger High Once
+#define ADC_COMP_TRIG_HIGH_HALWAYS \
+                                0x00001E00  // Trigger High Always (Hysteresis)
+#define ADC_COMP_TRIG_HIGH_HONCE \
+                                0x00001F00  // Trigger High Once (Hysteresis)
+
+#define ADC_COMP_INT_NONE       0x00000000  // Interrupt Disabled
+#define ADC_COMP_INT_LOW_ALWAYS \
+                                0x00000010  // Interrupt Low Always
+#define ADC_COMP_INT_LOW_ONCE   0x00000011  // Interrupt Low Once
+#define ADC_COMP_INT_LOW_HALWAYS \
+                                0x00000012  // Interrupt Low Always
+                                            // (Hysteresis)
+#define ADC_COMP_INT_LOW_HONCE  0x00000013  // Interrupt Low Once (Hysteresis)
+#define ADC_COMP_INT_MID_ALWAYS \
+                                0x00000014  // Interrupt Mid Always
+#define ADC_COMP_INT_MID_ONCE   0x00000015  // Interrupt Mid Once
+#define ADC_COMP_INT_HIGH_ALWAYS \
+                                0x0000001C  // Interrupt High Always
+#define ADC_COMP_INT_HIGH_ONCE  0x0000001D  // Interrupt High Once
+#define ADC_COMP_INT_HIGH_HALWAYS \
+                                0x0000001E  // Interrupt High Always
+                                            // (Hysteresis)
+#define ADC_COMP_INT_HIGH_HONCE \
+                                0x0000001F  // Interrupt High Once (Hysteresis)
+
+//*****************************************************************************
+//
+// Values that can be used to modify the sequence number passed to
+// ADCProcessorTrigger in order to get cross-module synchronous processor
+// triggers.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_WAIT        0x08000000  // Wait for the synchronous trigger
+#define ADC_TRIGGER_SIGNAL      0x80000000  // Signal the synchronous trigger
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
+// returned from ADCPhaseDelayGet.
+//
+//*****************************************************************************
+#define ADC_PHASE_0             0x00000000  // 0 degrees
+#define ADC_PHASE_22_5          0x00000001  // 22.5 degrees
+#define ADC_PHASE_45            0x00000002  // 45 degrees
+#define ADC_PHASE_67_5          0x00000003  // 67.5 degrees
+#define ADC_PHASE_90            0x00000004  // 90 degrees
+#define ADC_PHASE_112_5         0x00000005  // 112.5 degrees
+#define ADC_PHASE_135           0x00000006  // 135 degrees
+#define ADC_PHASE_157_5         0x00000007  // 157.5 degrees
+#define ADC_PHASE_180           0x00000008  // 180 degrees
+#define ADC_PHASE_202_5         0x00000009  // 202.5 degrees
+#define ADC_PHASE_225           0x0000000A  // 225 degrees
+#define ADC_PHASE_247_5         0x0000000B  // 247.5 degrees
+#define ADC_PHASE_270           0x0000000C  // 270 degrees
+#define ADC_PHASE_292_5         0x0000000D  // 292.5 degrees
+#define ADC_PHASE_315           0x0000000E  // 315 degrees
+#define ADC_PHASE_337_5         0x0000000F  // 337.5 degrees
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCReferenceSet as the ulRef parameter.
+//
+//*****************************************************************************
+#define ADC_REF_INT             0x00000000  // Internal reference
+#define ADC_REF_EXT_3V          0x00000001  // External 3V reference
 
 //*****************************************************************************
 //
@@ -136,6 +227,24 @@ extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
                                          unsigned long ulCount);
 extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
                                            unsigned long ulFactor);
+extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+                                   unsigned long ulConfig);
+extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
+                                   unsigned long ulLowRef,
+                                   unsigned long ulHighRef);
+extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
+                               tBoolean bTrigger, tBoolean bInterrupt);
+extern void ADCComparatorIntDisable(unsigned long ulBase,
+                                    unsigned long ulSequenceNum);
+extern void ADCComparatorIntEnable(unsigned long ulBase,
+                                   unsigned long ulSequenceNum);
+extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
+extern void ADCComparatorIntClear(unsigned long ulBase,
+                                  unsigned long ulStatus);
+extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
+extern unsigned long ADCReferenceGet(unsigned long ulBase);
+extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
+extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/can.c

@@ -2,26 +2,23 @@
 //
 // can.c - Driver for the CAN module.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -47,34 +44,56 @@
 // identifier.
 //
 //*****************************************************************************
-#define CAN_MAX_11BIT_MSG_ID    (0x7ff)
+#define CAN_MAX_11BIT_MSG_ID    0x7ff
 
 //*****************************************************************************
 //
 // This is used as the loop delay for accessing the CAN controller registers.
 //
 //*****************************************************************************
-#define CAN_RW_DELAY            (5)
+#define CAN_RW_DELAY            5
 
+//*****************************************************************************
 //
-// The maximum CAN bit timing divisor is 13.
+// The maximum CAN bit timing divisor is 19.
 //
-#define CAN_MAX_BIT_DIVISOR     (13)
+//*****************************************************************************
+#define CAN_MAX_BIT_DIVISOR     19
 
+//*****************************************************************************
 //
-// The minimum CAN bit timing divisor is 5.
+// The minimum CAN bit timing divisor is 4.
 //
-#define CAN_MIN_BIT_DIVISOR     (5)
+//*****************************************************************************
+#define CAN_MIN_BIT_DIVISOR     4
 
+//*****************************************************************************
 //
 // The maximum CAN pre-divisor is 1024.
 //
-#define CAN_MAX_PRE_DIVISOR     (1024)
+//*****************************************************************************
+#define CAN_MAX_PRE_DIVISOR     1024
+
+//*****************************************************************************
+//
+// The minimum CAN pre-divisor is 1.
+//
+//*****************************************************************************
+#define CAN_MIN_PRE_DIVISOR     1
 
+//*****************************************************************************
 //
-// The minimum CAN pre-divisor is 1024.
+// Converts a set of CAN bit timing values into the value that needs to be
+// programmed into the CAN_BIT register to achieve those timings.
 //
-#define CAN_MIN_PRE_DIVISOR     (1024)
+//*****************************************************************************
+#define CAN_BIT_VALUE(seg1, seg2, sjw)                                        \
+                                ((((seg1 - 1) << CAN_BIT_TSEG1_S) &           \
+                                  CAN_BIT_TSEG1_M) |                          \
+                                 (((seg2 - 1) << CAN_BIT_TSEG2_S) &           \
+                                  CAN_BIT_TSEG2_M) |                          \
+                                 (((sjw - 1) << CAN_BIT_SJW_S) &              \
+                                  CAN_BIT_SJW_M))
 
 //*****************************************************************************
 //
@@ -84,15 +103,22 @@
 //*****************************************************************************
 static const unsigned short g_usCANBitValues[] =
 {
-    0x1100, // TSEG2 2, TSEG1 2, SJW 1, Divide 5
-    0x1200, // TSEG2 2, TSEG1 3, SJW 1, Divide 6
-    0x2240, // TSEG2 3, TSEG1 3, SJW 2, Divide 7
-    0x2340, // TSEG2 3, TSEG1 4, SJW 2, Divide 8
-    0x3340, // TSEG2 4, TSEG1 4, SJW 2, Divide 9
-    0x3440, // TSEG2 4, TSEG1 5, SJW 2, Divide 10
-    0x3540, // TSEG2 4, TSEG1 6, SJW 2, Divide 11
-    0x3640, // TSEG2 4, TSEG1 7, SJW 2, Divide 12
-    0x3740  // TSEG2 4, TSEG1 8, SJW 2, Divide 13
+    CAN_BIT_VALUE(2, 1, 1),     // 4 clocks/bit
+    CAN_BIT_VALUE(3, 1, 1),     // 5 clocks/bit
+    CAN_BIT_VALUE(3, 2, 2),     // 6 clocks/bit
+    CAN_BIT_VALUE(4, 2, 2),     // 7 clocks/bit
+    CAN_BIT_VALUE(4, 3, 3),     // 8 clocks/bit
+    CAN_BIT_VALUE(5, 3, 3),     // 9 clocks/bit
+    CAN_BIT_VALUE(5, 4, 4),     // 10 clocks/bit
+    CAN_BIT_VALUE(6, 4, 4),     // 11 clocks/bit
+    CAN_BIT_VALUE(6, 5, 4),     // 12 clocks/bit
+    CAN_BIT_VALUE(7, 5, 4),     // 13 clocks/bit
+    CAN_BIT_VALUE(7, 6, 4),     // 14 clocks/bit
+    CAN_BIT_VALUE(8, 6, 4),     // 15 clocks/bit
+    CAN_BIT_VALUE(8, 7, 4),     // 16 clocks/bit
+    CAN_BIT_VALUE(9, 7, 4),     // 17 clocks/bit
+    CAN_BIT_VALUE(9, 8, 4),     // 18 clocks/bit
+    CAN_BIT_VALUE(10, 8, 4)     // 19 clocks/bit
 };
 
 //*****************************************************************************
@@ -237,7 +263,7 @@ CANRegRead(unsigned long ulRegAddress)
     }
 
     //
-    // Trigger the inital read to the CAN controller.  The value returned at
+    // Trigger the initial read to the CAN controller.  The value returned at
     // this point is not valid.
     //
     HWREG(ulRegAddress);
@@ -255,7 +281,7 @@ CANRegRead(unsigned long ulRegAddress)
     ulRetVal = HWREG(ulRegAddress);
 
     //
-    // Reenable CAN interrupts if they were enabled before this call.
+    // Enable CAN interrupts if they were enabled before this call.
     //
     if(ulReenableInts)
     {
@@ -294,7 +320,7 @@ CANRegWrite(unsigned long ulRegAddress, unsigned long ulRegValue)
     volatile int iDelay;
 
     //
-    // Trigger the inital write to the CAN controller.  The value will not make
+    // Trigger the initial write to the CAN controller.  The value will not make
     // it out to the CAN controller for CAN_RW_DELAY cycles.
     //
     HWREG(ulRegAddress) = ulRegValue;
@@ -618,17 +644,19 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
     //
     // Set the phase 2 segment.
     //
-    pClkParms->uPhase2Seg = ((uBitReg & CAN_BIT_TSEG2_M) >> 12) + 1;
+    pClkParms->uPhase2Seg =
+        ((uBitReg & CAN_BIT_TSEG2_M) >> CAN_BIT_TSEG2_S) + 1;
 
     //
     // Set the phase 1 segment.
     //
-    pClkParms->uSyncPropPhase1Seg = ((uBitReg & CAN_BIT_TSEG1_M) >> 8) + 1;
+    pClkParms->uSyncPropPhase1Seg =
+        ((uBitReg & CAN_BIT_TSEG1_M) >> CAN_BIT_TSEG1_S) + 1;
 
     //
-    // Set the sychronous jump width.
+    // Set the synchronous jump width.
     //
-    pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> 6) + 1;
+    pClkParms->uSJW = ((uBitReg & CAN_BIT_SJW_M) >> CAN_BIT_SJW_S) + 1;
 
     //
     // Set the pre-divider for the CAN bus bit clock.
@@ -651,12 +679,14 @@ CANBitTimingGet(unsigned long ulBase, tCANBitClkParms *pClkParms)
 //! \e ulBitRate parameter based on the \e ulSourceClock parameter.  Since the
 //! CAN clock is based off of the system clock the calling function should pass
 //! in the source clock rate either by retrieving it from SysCtlClockGet() or
-//! using a specific value in Hz.  The CAN bit clock is calculated to be an
-//! average timing value that should work for most systems.  If tighter timing
-//! requirements are needed, then the CANBitTimingSet() function is available
-//! for full customization of all of the CAN bit timing values.  Since not all
-//! bit rates can be matched exactly, the bit rate is set to the value closest
-//! to the desired bit rate without being higher than the \e ulBitRate value.
+//! using a specific value in Hz.  The CAN bit timing is calculated assuming a
+//! minimal amount of propagation delay, which will work for most cases where
+//! the network length is short.  If tighter timing requirements or longer
+//! network lengths are needed, then the CANBitTimingSet() function is
+//! available for full customization of all of the CAN bit timing values.
+//! Since not all bit rates can be matched exactly, the bit rate is set to the
+//! value closest to the desired bit rate without being higher than the
+//! \e ulBitRate value.
 //!
 //! \note On some devices the source clock is fixed at 8MHz so the
 //! \e ulSourceClock should be set to 8000000.
@@ -676,22 +706,24 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
     unsigned long ulRegValue;
     unsigned short usCANCTL;
 
+    //
+    // Check the arguments.
+    //
+    ASSERT(CANBaseValid(ulBase));
+    ASSERT(ulSourceClock != 0);
     ASSERT(ulBitRate != 0);
 
     //
-    // Caclulate the desired clock rate.
+    // Calculate the desired clock rate.
     //
     ulDesiredRatio = ulSourceClock / ulBitRate;
 
     //
-    // If the ratio of CAN bit rate to processor clock is too small or too
-    // large then return 0 indicating that no bit rate was set.
+    // Make sure that the ratio of CAN bit rate to processor clock is not too
+    // small or too large.
     //
-    if((ulDesiredRatio > (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR)) ||
-       (ulDesiredRatio < CAN_MIN_BIT_DIVISOR))
-    {
-        return(0);
-    }
+    ASSERT(ulDesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR));
+    ASSERT(ulDesiredRatio >= (CAN_MIN_PRE_DIVISOR * CAN_MIN_BIT_DIVISOR));
 
     //
     // Make sure that the Desired Ratio is not too large.  This enforces the
@@ -705,7 +737,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
     //
     // Check all possible values to find a matching value.
     //
-    while(ulDesiredRatio <= CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR)
+    while(ulDesiredRatio <= (CAN_MAX_PRE_DIVISOR * CAN_MAX_BIT_DIVISOR))
     {
         //
         // Loop through all possible CAN bit divisors.
@@ -719,7 +751,7 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
             ulPreDivide = ulDesiredRatio / ulCANBits;
 
             //
-            // If the caculated divisors match the desired clock ratio then
+            // If the calculated divisors match the desired clock ratio then
             // return these bit rate and set the CAN bit timing.
             //
             if((ulPreDivide * ulCANBits) == ulDesiredRatio)
@@ -733,17 +765,17 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
                 //
                 // To set the bit timing register, the controller must be placed
                 // in init mode (if not already), and also configuration change
-                // bit enabled.  The stat of the register should be saved
+                // bit enabled.  The state of the register should be saved
                 // so it can be restored.
                 //
                 usCANCTL = CANRegRead(ulBase + CAN_O_CTL);
-                CANRegWrite(ulBase + CAN_O_CTL, usCANCTL | CAN_CTL_INIT |
-                                                CAN_CTL_CCE);
+                CANRegWrite(ulBase + CAN_O_CTL,
+                            usCANCTL | CAN_CTL_INIT | CAN_CTL_CCE);
 
                 //
                 // Now add in the pre-scalar on the bit rate.
                 //
-                ulRegValue |= ((ulPreDivide - 1)& CAN_BIT_BRP_M);
+                ulRegValue |= ((ulPreDivide - 1) & CAN_BIT_BRP_M);
 
                 //
                 // Set the clock bits in the and the lower bits of the
@@ -775,6 +807,11 @@ CANBitRateSet(unsigned long ulBase, unsigned long ulSourceClock,
         //
         ulDesiredRatio++;
     }
+
+    //
+    // A valid combination could not be found, so return 0 to indicate that the
+    // bit rate was not changed.
+    //
     return(0);
 }
 
@@ -864,9 +901,11 @@ CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
     //
     // Set the bit fields of the bit timing register according to the parms.
     //
-    uBitReg = ((pClkParms->uPhase2Seg - 1) << 12) & CAN_BIT_TSEG2_M;
-    uBitReg |= ((pClkParms->uSyncPropPhase1Seg - 1) << 8) & CAN_BIT_TSEG1_M;
-    uBitReg |= ((pClkParms->uSJW - 1) << 6) & CAN_BIT_SJW_M;
+    uBitReg = (((pClkParms->uPhase2Seg - 1) << CAN_BIT_TSEG2_S) &
+               CAN_BIT_TSEG2_M);
+    uBitReg |= (((pClkParms->uSyncPropPhase1Seg - 1) << CAN_BIT_TSEG1_S) &
+                CAN_BIT_TSEG1_M);
+    uBitReg |= ((pClkParms->uSJW - 1) << CAN_BIT_SJW_S) & CAN_BIT_SJW_M;
     uBitReg |= (pClkParms->uQuantumPrescaler - 1) & CAN_BIT_BRP_M;
     CANRegWrite(ulBase + CAN_O_BIT, uBitReg);
 
@@ -875,6 +914,7 @@ CANBitTimingSet(unsigned long ulBase, tCANBitClkParms *pClkParms)
     //
     CANRegWrite(ulBase + CAN_O_BRPE,
                 ((pClkParms->uQuantumPrescaler - 1) >> 6) & CAN_BRPE_BRPE_M);
+
     //
     // Clear the config change bit, and restore the init bit.
     //
@@ -1556,14 +1596,13 @@ CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount,
 //! -# Set \e pMsgObject->ulMsgIDMask bits that should be used for masking
 //! during comparison.
 //! -# Set \e pMsgObject->ulFlags as follows:
-//!   - Set \b MSG_OBJ_TX_INT_ENABLE flag to be interrupted when the data frame
+//!   - Set \b MSG_OBJ_RX_INT_ENABLE flag to be interrupted when the data frame
 //!   is received.
 //!   - Set \b MSG_OBJ_USE_ID_FILTER flag to enable identifier based filtering.
 //! -# Set \e pMsgObject->ulMsgLen to the number of bytes in the expected data
 //! frame.
-//! -# The buffer pointed to by \e pMsgObject->pucMsgData  and
-//! \e pMsgObject->ulMsgLen are not used by this call as no data is present at
-//! the time of the call.
+//! -# The buffer pointed to by \e pMsgObject->pucMsgData is not used by this
+//! call as no data is present at the time of the call.
 //! -# Call this function with \e ulObjID set to one of the 32 object buffers.
 //!
 //! If you specify a message object buffer that already contains a message
@@ -1577,8 +1616,8 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
               tCANMsgObject *pMsgObject, tMsgObjType eMsgType)
 {
     unsigned short usCmdMaskReg;
-    unsigned short usMaskReg[2];
-    unsigned short usArbReg[2];
+    unsigned short usMaskReg0, usMaskReg1;
+    unsigned short usArbReg0, usArbReg1;
     unsigned short usMsgCtrl;
     tBoolean bTransferData;
     tBoolean bUseExtendedID;
@@ -1630,10 +1669,11 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     // Initialize the values to a known state before filling them in based on
     // the type of message object that is being configured.
     //
-    usArbReg[0] = 0;
+    usArbReg0 = 0;
+    usArbReg1 = 0;
     usMsgCtrl = 0;
-    usMaskReg[0] = 0;
-    usMaskReg[1] = 0;
+    usMaskReg0 = 0;
+    usMaskReg1 = 0;
 
     switch(eMsgType)
     {
@@ -1646,7 +1686,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             // Set the TXRQST bit and the reset the rest of the register.
             //
             usMsgCtrl |= CAN_IF1MCTL_TXRQST;
-            usArbReg[1] = CAN_IF1ARB2_DIR;
+            usArbReg1 = CAN_IF1ARB2_DIR;
             bTransferData = 1;
             break;
         }
@@ -1660,7 +1700,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             // Set the TXRQST bit and the reset the rest of the register.
             //
             usMsgCtrl |= CAN_IF1MCTL_TXRQST;
-            usArbReg[1] = 0;
+            usArbReg1 = 0;
             break;
         }
 
@@ -1670,10 +1710,10 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         case MSG_OBJ_TYPE_RX:
         {
             //
-            // This clears the DIR bit along with everthing else.  The TXRQST
-            // bit was cleard by defaulting usMsgCtrl to 0.
+            // This clears the DIR bit along with everything else.  The TXRQST
+            // bit was cleared by defaulting usMsgCtrl to 0.
             //
-            usArbReg[1] = 0;
+            usArbReg1 = 0;
             break;
         }
 
@@ -1684,9 +1724,9 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         {
             //
             // The DIR bit is set to one for remote receivers.  The TXRQST bit
-            // was cleard by defaulting usMsgCtrl to 0.
+            // was cleared by defaulting usMsgCtrl to 0.
             //
-            usArbReg[1] = CAN_IF1ARB2_DIR;
+            usArbReg1 = CAN_IF1ARB2_DIR;
 
             //
             // Set this object so that it only indicates that a remote frame
@@ -1698,8 +1738,8 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Use the full Identifier by default.
             //
-            usMaskReg[0] = 0xffff;
-            usMaskReg[1] = 0x1fff;
+            usMaskReg0 = 0xffff;
+            usMaskReg1 = 0x1fff;
 
             //
             // Make sure to send the mask to the message object.
@@ -1716,7 +1756,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Oddly the DIR bit is set to one for remote receivers.
             //
-            usArbReg[1] = CAN_IF1ARB2_DIR;
+            usArbReg1 = CAN_IF1ARB2_DIR;
 
             //
             // Set this object to auto answer if a matching identifier is seen.
@@ -1750,8 +1790,8 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Set the 29 bits of Identifier mask that were requested.
             //
-            usMaskReg[0] = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M;
-            usMaskReg[1] = ((pMsgObject->ulMsgIDMask >> 16) &
+            usMaskReg0 = pMsgObject->ulMsgIDMask & CAN_IF1MSK1_IDMSK_M;
+            usMaskReg1 = ((pMsgObject->ulMsgIDMask >> 16) &
                             CAN_IF1MSK2_IDMSK_M);
         }
         else
@@ -1759,13 +1799,13 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
             //
             // Lower 16 bit are unused so set them to zero.
             //
-            usMaskReg[0] = 0;
+            usMaskReg0 = 0;
 
             //
             // Put the 11 bit Mask Identifier into the upper bits of the field
             // in the register.
             //
-            usMaskReg[1] = ((pMsgObject->ulMsgIDMask << 2) &
+            usMaskReg1 = ((pMsgObject->ulMsgIDMask << 2) &
                             CAN_IF1MSK2_IDMSK_M);
         }
     }
@@ -1776,7 +1816,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     if((pMsgObject->ulFlags & MSG_OBJ_USE_EXT_FILTER) ==
        MSG_OBJ_USE_EXT_FILTER)
     {
-        usMaskReg[1] |= CAN_IF1MSK2_MXTD;
+        usMaskReg1 |= CAN_IF1MSK2_MXTD;
     }
 
     //
@@ -1785,7 +1825,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     if((pMsgObject->ulFlags & MSG_OBJ_USE_DIR_FILTER) ==
        MSG_OBJ_USE_DIR_FILTER)
     {
-        usMaskReg[1] |= CAN_IF1MSK2_MDIR;
+        usMaskReg1 |= CAN_IF1MSK2_MDIR;
     }
 
     if(pMsgObject->ulFlags & (MSG_OBJ_USE_ID_FILTER | MSG_OBJ_USE_DIR_FILTER |
@@ -1797,7 +1837,7 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         usMsgCtrl |= CAN_IF1MCTL_UMASK;
 
         //
-        // Set the MASK bit so that this gets trasferred to the Message Object.
+        // Set the MASK bit so that this gets transferred to the Message Object.
         //
         usCmdMaskReg |= CAN_IF1CMSK_MASK;
     }
@@ -1815,13 +1855,13 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         //
         // Set the 29 bit version of the Identifier for this message object.
         //
-        usArbReg[0] |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M;
-        usArbReg[1] |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M;
+        usArbReg0 |= pMsgObject->ulMsgID & CAN_IF1ARB1_ID_M;
+        usArbReg1 |= (pMsgObject->ulMsgID >> 16) & CAN_IF1ARB2_ID_M;
 
         //
         // Mark the message as valid and set the extended ID bit.
         //
-        usArbReg[1] |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
+        usArbReg1 |= CAN_IF1ARB2_MSGVAL | CAN_IF1ARB2_XTD;
     }
     else
     {
@@ -1829,19 +1869,27 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
         // Set the 11 bit version of the Identifier for this message object.
         // The lower 18 bits are set to zero.
         //
-        usArbReg[1] |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M;
+        usArbReg1 |= (pMsgObject->ulMsgID << 2) & CAN_IF1ARB2_ID_M;
 
         //
         // Mark the message as valid.
         //
-        usArbReg[1] |= CAN_IF1ARB2_MSGVAL;
+        usArbReg1 |= CAN_IF1ARB2_MSGVAL;
     }
 
     //
     // Set the data length since this is set for all transfers.  This is also a
     // single transfer and not a FIFO transfer so set EOB bit.
     //
-    usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M) | CAN_IF1MCTL_EOB;
+    usMsgCtrl |= (pMsgObject->ulMsgLen & CAN_IF1MCTL_DLC_M);
+
+    //
+    // Mark this as the last entry if this is not the last entry in a FIFO.
+    //
+    if((pMsgObject->ulFlags & MSG_OBJ_FIFO) == 0)
+    {
+        usMsgCtrl |= CAN_IF1MCTL_EOB;
+    }
 
     //
     // Enable transmit interrupts if they should be enabled.
@@ -1873,10 +1921,10 @@ CANMessageSet(unsigned long ulBase, unsigned long ulObjID,
     // Write out the registers to program the message object.
     //
     CANRegWrite(ulBase + CAN_O_IF1CMSK, usCmdMaskReg);
-    CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg[0]);
-    CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg[1]);
-    CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg[0]);
-    CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg[1]);
+    CANRegWrite(ulBase + CAN_O_IF1MSK1, usMaskReg0);
+    CANRegWrite(ulBase + CAN_O_IF1MSK2, usMaskReg1);
+    CANRegWrite(ulBase + CAN_O_IF1ARB1, usArbReg0);
+    CANRegWrite(ulBase + CAN_O_IF1ARB2, usArbReg1);
     CANRegWrite(ulBase + CAN_O_IF1MCTL, usMsgCtrl);
 
     //
@@ -1928,8 +1976,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
               tCANMsgObject *pMsgObject, tBoolean bClrPendingInt)
 {
     unsigned short usCmdMaskReg;
-    unsigned short usMaskReg[2];
-    unsigned short usArbReg[2];
+    unsigned short usMaskReg0, usMaskReg1;
+    unsigned short usArbReg0, usArbReg1;
     unsigned short usMsgCtrl;
 
     //
@@ -1959,7 +2007,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     CANRegWrite(ulBase + CAN_O_IF2CMSK, usCmdMaskReg);
 
     //
-    // Transfer the message object to the message object specifiec by ulObjID.
+    // Transfer the message object to the message object specified by ulObjID.
     //
     CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);
 
@@ -1973,10 +2021,10 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     //
     // Read out the IF Registers.
     //
-    usMaskReg[0] = CANRegRead(ulBase + CAN_O_IF2MSK1);
-    usMaskReg[1] = CANRegRead(ulBase + CAN_O_IF2MSK2);
-    usArbReg[0] = CANRegRead(ulBase + CAN_O_IF2ARB1);
-    usArbReg[1] = CANRegRead(ulBase + CAN_O_IF2ARB2);
+    usMaskReg0 = CANRegRead(ulBase + CAN_O_IF2MSK1);
+    usMaskReg1 = CANRegRead(ulBase + CAN_O_IF2MSK2);
+    usArbReg0 = CANRegRead(ulBase + CAN_O_IF2ARB1);
+    usArbReg1 = CANRegRead(ulBase + CAN_O_IF2ARB2);
     usMsgCtrl = CANRegRead(ulBase + CAN_O_IF2MCTL);
 
     pMsgObject->ulFlags = MSG_OBJ_NO_FLAGS;
@@ -1984,10 +2032,8 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     //
     // Determine if this is a remote frame by checking the TXRQST and DIR bits.
     //
-    if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
-        (usArbReg[1] & CAN_IF1ARB2_DIR)) ||
-       ((usMsgCtrl & CAN_IF1MCTL_TXRQST) &&
-        (!(usArbReg[1] & CAN_IF1ARB2_DIR))))
+    if((!(usMsgCtrl & CAN_IF1MCTL_TXRQST) && (usArbReg1 & CAN_IF1ARB2_DIR)) ||
+       ((usMsgCtrl & CAN_IF1MCTL_TXRQST) && (!(usArbReg1 & CAN_IF1ARB2_DIR))))
     {
         pMsgObject->ulFlags |= MSG_OBJ_REMOTE_FRAME;
     }
@@ -1996,13 +2042,13 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     // Get the identifier out of the register, the format depends on size of
     // the mask.
     //
-    if(usArbReg[1] & CAN_IF1ARB2_XTD)
+    if(usArbReg1 & CAN_IF1ARB2_XTD)
     {
         //
         // Set the 29 bit version of the Identifier for this message object.
         //
-        pMsgObject->ulMsgID = ((usArbReg[1] & CAN_IF1ARB2_ID_M) << 16) |
-            usArbReg[0];
+        pMsgObject->ulMsgID = ((usArbReg1 & CAN_IF1ARB2_ID_M) << 16) |
+            usArbReg0;
 
         pMsgObject->ulFlags |= MSG_OBJ_EXTENDED_ID;
     }
@@ -2011,7 +2057,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         //
         // The Identifier is an 11 bit value.
         //
-        pMsgObject->ulMsgID = (usArbReg[1] & CAN_IF1ARB2_ID_M) >> 2;
+        pMsgObject->ulMsgID = (usArbReg1 & CAN_IF1ARB2_ID_M) >> 2;
     }
 
     //
@@ -2027,13 +2073,14 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
     //
     if(usMsgCtrl & CAN_IF1MCTL_UMASK)
     {
-        if(usArbReg[1] & CAN_IF1ARB2_XTD)
+        if(usArbReg1 & CAN_IF1ARB2_XTD)
         {
             //
             // The Identifier Mask is assumed to also be a 29 bit value.
             //
             pMsgObject->ulMsgIDMask =
-                ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg[0];
+                ((usMaskReg1 & CAN_IF1MSK2_IDMSK_M) << 16) | usMaskReg0;
+
             //
             // If this is a fully specified Mask and a remote frame then don't
             // set the MSG_OBJ_USE_ID_FILTER because the ID was not really
@@ -2050,7 +2097,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
             //
             // The Identifier Mask is assumed to also be an 11 bit value.
             //
-            pMsgObject->ulMsgIDMask = ((usMaskReg[1] & CAN_IF1MSK2_IDMSK_M) >>
+            pMsgObject->ulMsgIDMask = ((usMaskReg1 & CAN_IF1MSK2_IDMSK_M) >>
                                        2);
 
             //
@@ -2068,7 +2115,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         //
         // Indicate if the extended bit was used in filtering.
         //
-        if(usMaskReg[1] & CAN_IF1MSK2_MXTD)
+        if(usMaskReg1 & CAN_IF1MSK2_MXTD)
         {
             pMsgObject->ulFlags |= MSG_OBJ_USE_EXT_FILTER;
         }
@@ -2076,14 +2123,14 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         //
         // Indicate if direction filtering was enabled.
         //
-        if(usMaskReg[1] & CAN_IF1MSK2_MDIR)
+        if(usMaskReg1 & CAN_IF1MSK2_MDIR)
         {
             pMsgObject->ulFlags |= MSG_OBJ_USE_DIR_FILTER;
         }
     }
 
     //
-    // Set the interupt flags.
+    // Set the interrupt flags.
     //
     if(usMsgCtrl & CAN_IF1MCTL_TXIE)
     {
@@ -2124,7 +2171,7 @@ CANMessageGet(unsigned long ulBase, unsigned long ulObjID,
         CANRegWrite(ulBase + CAN_O_IF2CMSK, CAN_IF1CMSK_NEWDAT);
 
         //
-        // Transfer the message object to the message object specifiec by
+        // Transfer the message object to the message object specified by
         // ulObjID.
         //
         CANRegWrite(ulBase + CAN_O_IF2CRQ, ulObjID & CAN_IF1CRQ_MNUM_M);

bsp/lm3s/Libraries/driverlib/can.h

@@ -2,26 +2,23 @@
 //
 // can.h - Defines and Macros for the CAN controller.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -54,77 +51,80 @@ extern "C"
 
 //*****************************************************************************
 //
-//! These are the flags used by the tCANMsgObject variable when calling the
-//! CANMessageSet() and CANMessageGet() functions.
+// These are the flags used by the tCANMsgObject.ulFlags value when calling the
+// CANMessageSet() and CANMessageGet() functions.
 //
 //*****************************************************************************
-typedef enum
-{
-    //
-    //! This indicates that transmit interrupts should be enabled, or are
-    //! enabled.
-    //
-    MSG_OBJ_TX_INT_ENABLE =     0x00000001,
 
-    //
-    //! This indicates that receive interrupts should be enabled, or are
-    //! enabled.
-    //
-    MSG_OBJ_RX_INT_ENABLE =     0x00000002,
+//
+//! This definition is used with the tCANMsgObject ulFlags value and indicates
+//! that transmit interrupts should be enabled, or are enabled.
+//
+#define MSG_OBJ_TX_INT_ENABLE   0x00000001
 
-    //
-    //! This indicates that a message object will use or is using an extended
-    //! identifier.
-    //
-    MSG_OBJ_EXTENDED_ID =       0x00000004,
+//
+//! This indicates that receive interrupts should be enabled, or are
+//! enabled.
+//
+#define MSG_OBJ_RX_INT_ENABLE   0x00000002
 
-    //
-    //! This indicates that a message object will use or is using filtering
-    //! based on the object's message identifier.
-    //
-    MSG_OBJ_USE_ID_FILTER =     0x00000008,
+//
+//! This indicates that a message object will use or is using an extended
+//! identifier.
+//
+#define MSG_OBJ_EXTENDED_ID     0x00000004
 
-    //
-    //! This indicates that new data was available in the message object.
-    //
-    MSG_OBJ_NEW_DATA =          0x00000080,
+//
+//! This indicates that a message object will use or is using filtering
+//! based on the object's message identifier.
+//
+#define MSG_OBJ_USE_ID_FILTER   0x00000008
 
-    //
-    //! This indicates that data was lost since this message object was last
-    //! read.
-    //
-    MSG_OBJ_DATA_LOST =         0x00000100,
+//
+//! This indicates that new data was available in the message object.
+//
+#define MSG_OBJ_NEW_DATA        0x00000080
 
-    //
-    //! This indicates that a message object will use or is using filtering
-    //! based on the direction of the transfer.  If the direction filtering is
-    //! used, then ID filtering must also be enabled.
-    //
-    MSG_OBJ_USE_DIR_FILTER =    (0x00000010 | MSG_OBJ_USE_ID_FILTER),
+//
+//! This indicates that data was lost since this message object was last
+//! read.
+//
+#define MSG_OBJ_DATA_LOST       0x00000100
 
-    //
-    //! This indicates that a message object will use or is using message
-    //! identifier filtering based on the extended identifier.  If the extended
-    //! identifier filtering is used, then ID filtering must also be enabled.
-    //
-    MSG_OBJ_USE_EXT_FILTER =    (0x00000020 | MSG_OBJ_USE_ID_FILTER),
+//
+//! This indicates that a message object will use or is using filtering
+//! based on the direction of the transfer.  If the direction filtering is
+//! used, then ID filtering must also be enabled.
+//
+#define MSG_OBJ_USE_DIR_FILTER  (0x00000010 | MSG_OBJ_USE_ID_FILTER)
 
-    //
-    //! This indicates that a message object is a remote frame.
-    //
-    MSG_OBJ_REMOTE_FRAME =      0x00000040,
+//
+//! This indicates that a message object will use or is using message
+//! identifier filtering based on the extended identifier.  If the extended
+//! identifier filtering is used, then ID filtering must also be enabled.
+//
+#define MSG_OBJ_USE_EXT_FILTER  (0x00000020 | MSG_OBJ_USE_ID_FILTER)
 
-    //
-    //! This indicates that a message object has no flags set.
-    //
-    MSG_OBJ_NO_FLAGS =          0x00000000
-}
-tCANObjFlags;
+//
+//! This indicates that a message object is a remote frame.
+//
+#define MSG_OBJ_REMOTE_FRAME    0x00000040
+
+//
+//! This indicates that this message object is part of a FIFO structure and
+//! not the final message object in a FIFO.
+//
+#define MSG_OBJ_FIFO            0x00000200
+
+//
+//! This indicates that a message object has no flags set.
+//
+#define MSG_OBJ_NO_FLAGS        0x00000000
 
 //*****************************************************************************
 //
-//! This define is used with the #tCANObjFlags enumerated values to allow
-//! checking only status flags and not configuration flags.
+//! This define is used with the flag values to allow checking only status
+//! flags and not configuration flags.
 //
 //*****************************************************************************
 #define MSG_OBJ_STATUS_MASK     (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
@@ -254,32 +254,28 @@ tCANStsReg;
 
 //*****************************************************************************
 //
-//! These definitions are used to specify interrupt sources to CANIntEnable()
-//! and CANIntDisable().
+// These definitions are used to specify interrupt sources to CANIntEnable()
+// and CANIntDisable().
 //
 //*****************************************************************************
-typedef enum
-{
-    //
-    //! This flag is used to allow a CAN controller to generate error
-    //! interrupts.
-    //
-    CAN_INT_ERROR =             0x00000008,
+//
+//! This flag is used to allow a CAN controller to generate error
+//! interrupts.
+//
+#define CAN_INT_ERROR           0x00000008
 
-    //
-    //! This flag is used to allow a CAN controller to generate status
-    //! interrupts.
-    //
-    CAN_INT_STATUS =            0x00000004,
+//
+//! This flag is used to allow a CAN controller to generate status
+//! interrupts.
+//
+#define CAN_INT_STATUS          0x00000004
 
-    //
-    //! This flag is used to allow a CAN controller to generate any CAN
-    //! interrupts.  If this is not set, then no interrupts will be generated
-    //! by the CAN controller.
-    //
-    CAN_INT_MASTER =            0x00000002
-}
-tCANIntFlags;
+//
+//! This flag is used to allow a CAN controller to generate any CAN
+//! interrupts.  If this is not set, then no interrupts will be generated
+//! by the CAN controller.
+//
+#define CAN_INT_MASTER          0x00000002
 
 //*****************************************************************************
 //
@@ -318,84 +314,80 @@ tMsgObjType;
 
 //*****************************************************************************
 //
-//! The following enumeration contains all error or status indicators that can
-//! be returned when calling the CANStatusGet() function.
+// The following enumeration contains all error or status indicators that can
+// be returned when calling the CANStatusGet() function.
 //
 //*****************************************************************************
-typedef enum
-{
-    //
-    //! CAN controller has entered a Bus Off state.
-    //
-    CAN_STATUS_BUS_OFF =        0x00000080,
+//
+//! CAN controller has entered a Bus Off state.
+//
+#define CAN_STATUS_BUS_OFF      0x00000080
 
-    //
-    //! CAN controller error level has reached warning level.
-    //
-    CAN_STATUS_EWARN =          0x00000040,
+//
+//! CAN controller error level has reached warning level.
+//
+#define CAN_STATUS_EWARN        0x00000040
 
-    //
-    //! CAN controller error level has reached error passive level.
-    //
-    CAN_STATUS_EPASS =          0x00000020,
+//
+//! CAN controller error level has reached error passive level.
+//
+#define CAN_STATUS_EPASS        0x00000020
 
-    //
-    //! A message was received successfully since the last read of this status.
-    //
-    CAN_STATUS_RXOK =           0x00000010,
+//
+//! A message was received successfully since the last read of this status.
+//
+#define CAN_STATUS_RXOK         0x00000010
 
-    //
-    //! A message was transmitted successfully since the last read of this
-    //! status.
-    //
-    CAN_STATUS_TXOK =           0x00000008,
+//
+//! A message was transmitted successfully since the last read of this
+//! status.
+//
+#define CAN_STATUS_TXOK         0x00000008
 
-    //
-    //! This is the mask for the last error code field.
-    //
-    CAN_STATUS_LEC_MSK =        0x00000007,
+//
+//! This is the mask for the last error code field.
+//
+#define CAN_STATUS_LEC_MSK      0x00000007
 
-    //
-    //! There was no error.
-    //
-    CAN_STATUS_LEC_NONE =       0x00000000,
+//
+//! There was no error.
+//
+#define CAN_STATUS_LEC_NONE     0x00000000
 
-    //
-    //! A bit stuffing error has occurred.
-    //
-    CAN_STATUS_LEC_STUFF =      0x00000001,
+//
+//! A bit stuffing error has occurred.
+//
+#define CAN_STATUS_LEC_STUFF    0x00000001
 
-    //
-    //! A formatting error has occurred.
-    //
-    CAN_STATUS_LEC_FORM =       0x00000002,
+//
+//! A formatting error has occurred.
+//
+#define CAN_STATUS_LEC_FORM     0x00000002
 
-    //
-    //! An acknowledge error has occurred.
-    //
-    CAN_STATUS_LEC_ACK =        0x00000003,
+//
+//! An acknowledge error has occurred.
+//
+#define CAN_STATUS_LEC_ACK      0x00000003
 
-    //
-    //! The bus remained a bit level of 1 for longer than is allowed.
-    //
-    CAN_STATUS_LEC_BIT1 =       0x00000004,
+//
+//! The bus remained a bit level of 1 for longer than is allowed.
+//
+#define CAN_STATUS_LEC_BIT1     0x00000004
 
-    //
-    //! The bus remained a bit level of 0 for longer than is allowed.
-    //
-    CAN_STATUS_LEC_BIT0 =       0x00000005,
+//
+//! The bus remained a bit level of 0 for longer than is allowed.
+//
+#define CAN_STATUS_LEC_BIT0     0x00000005
 
-    //
-    //! A CRC error has occurred.
-    //
-    CAN_STATUS_LEC_CRC =        0x00000006,
+//
+//! A CRC error has occurred.
+//
+#define CAN_STATUS_LEC_CRC      0x00000006
 
-    //
-    //! This is the mask for the CAN Last Error Code (LEC).
-    //
-    CAN_STATUS_LEC_MASK =       0x00000007
-}
-tCANStatusCtrl;
+//
+//! This is the mask for the CAN Last Error Code (LEC).
+//
+#define CAN_STATUS_LEC_MASK     0x00000007
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/comp.c

@@ -2,26 +2,23 @@
 //
 // comp.c - Driver for the analog comparator.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/comp.h

@@ -2,26 +2,23 @@
 //
 // comp.h - Prototypes for the analog comparator driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/cpu.c

@@ -3,26 +3,23 @@
 // cpu.c - Instruction wrappers for special CPU instructions needed by the
 //         drivers.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -43,7 +40,7 @@ CPUcpsid(void)
     //
     // Read PRIMASK and disable interrupts.
     //
-    __asm("    mrs     %0, PRIMASK\n"
+    __asm("    mrs     r0, PRIMASK\n"
           "    cpsid   i\n"
           "    bx      lr\n"
           : "=r" (ulRet));
@@ -88,6 +85,105 @@ CPUcpsid(void)
     bx      lr
 }
 #endif
+#if defined(ccs)
+unsigned long
+CPUcpsid(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsid   i\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUprimask(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    mrs     r0, PRIMASK;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUprimask(void)
+{
+    //
+    // Read PRIMASK and disable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
 
 //*****************************************************************************
 //
@@ -104,7 +200,7 @@ CPUcpsie(void)
     //
     // Read PRIMASK and enable interrupts.
     //
-    __asm("    mrs     %0, PRIMASK\n"
+    __asm("    mrs     r0, PRIMASK\n"
           "    cpsie   i\n"
           "    bx      lr\n"
           : "=r" (ulRet));
@@ -149,6 +245,27 @@ CPUcpsie(void)
     bx      lr
 }
 #endif
+#if defined(ccs)
+unsigned long
+CPUcpsie(void)
+{
+    //
+    // Read PRIMASK and enable interrupts.
+    //
+    __asm("    mrs     r0, PRIMASK\n"
+          "    cpsie   i\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif
 
 //*****************************************************************************
 //
@@ -187,3 +304,140 @@ CPUwfi(void)
     bx      lr
 }
 #endif
+#if defined(ccs)
+void
+CPUwfi(void)
+{
+    //
+    // Wait for the next interrupt.
+    //
+    __asm("    wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    bx      lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    msr     BASEPRI, r0;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+    //
+    // Set the BASEPRI register
+    //
+    __asm("    msr     BASEPRI, r0\n"
+          "    bx      lr\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUbasepriGet(void)
+{
+    unsigned long ulRet;
+
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n"
+          : "=r" (ulRet));
+
+    //
+    // The return is handled in the inline assembly, but the compiler will
+    // still complain if there is not an explicit return here (despite the fact
+    // that this does not result in any code being produced because of the
+    // naked attribute).
+    //
+    return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n");
+
+    //
+    // "Warning[Pe940]: missing return statement at end of non-void function"
+    // is suppressed here to avoid putting a "bx lr" in the inline assembly
+    // above and a superfluous return statement here.
+    //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    mrs     r0, BASEPRI;
+    bx      lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUbasepriGet(void)
+{
+    //
+    // Read BASEPRI
+    //
+    __asm("    mrs     r0, BASEPRI\n"
+          "    bx      lr\n");
+
+    //
+    // The following keeps the compiler happy, because it wants to see a
+    // return value from this function.  It will generate code to return
+    // a zero.  However, the real return is the "bx lr" above, so the
+    // return(0) is never executed and the function returns with the value
+    // you expect in R0.
+    //
+    return(0);
+}
+#endif

bsp/lm3s/Libraries/driverlib/cpu.h

@@ -2,26 +2,23 @@
 //
 // cpu.h - Prototypes for the CPU instruction wrapper functions.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -46,7 +43,10 @@ extern "C"
 //*****************************************************************************
 extern unsigned long CPUcpsid(void);
 extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
 extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/cr_project.xml

@@ -1,26 +1,23 @@
 <!--
 Configuration file for Code Red project libdriver
 
-Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 Software License Agreement
 
-Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-exclusively on LMI's microcontroller products.
+Texas Instruments (TI) is supplying this software for use solely and
+exclusively on TI's microcontroller products. The software is owned by
+TI and/or its suppliers, and is protected under applicable copyright
+laws. You may not combine this software with "viral" open-source
+software in order to form a larger program.
 
-The software is owned by LMI and/or its suppliers, and is protected under
-applicable copyright laws.  All rights are reserved.  You may not combine
-this software with "viral" open-source software in order to form a larger
-program.  Any use in violation of the foregoing restrictions may subject
-the user to criminal sanctions under applicable laws, as well as to civil
-liability for the breach of the terms and conditions of this license.
+THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+DAMAGES, FOR ANY REASON WHATSOEVER.
 
-THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-
-This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 -->
 
 <project chip="LM3S101"
@@ -28,8 +25,8 @@ This is part of revision 4694 of the Stellaris Peripheral Driver Library.
          type="Static library"
          vendor="LMI">
   <import src=".">
-    <exclude>{(Makefile|codered|ewarm|gcc|rvmdk|sourcerygxx)}</exclude>
-    <exclude>{.*\.(ewd|ewp|eww|icf|Opt|sct|Uv2|xml|ld)}</exclude>
+    <exclude>{(Makefile|ccs|codered|ewarm|gcc|rvmdk|sourcerygxx)}</exclude>
+    <exclude>{.*\.(ewd|ewp|eww|icf|Opt|sct|sgxx|Uv2|uvopt|uvproj|xml|ld|cmd)}</exclude>
   </import>
   <requires>
     <value>inc</value>
@@ -54,11 +51,19 @@ This is part of revision 4694 of the Stellaris Peripheral Driver Library.
   </setting>
   <setting id="compiler.opt"
            buildType="Debug">
-    <value>-O2</value>
+    <value>-Os</value>
   </setting>
   <setting id="compiler.opt"
            buildType="Release">
-    <value>-O2</value>
+    <value>-Os</value>
+  </setting>
+  <setting id="compiler.flags"
+           buildType="Debug">
+    <value>-Os</value>
+  </setting>
+  <setting id="compiler.flags"
+           buildType="Release">
+    <value>-Os</value>
   </setting>
   <setting id="compiler.inc">
     <value>${workspace_loc:/}</value>

bsp/lm3s/Libraries/driverlib/debug.h

@@ -2,26 +2,23 @@
 //
 // debug.h - Macros for assisting debug of the driver library.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/driverlib.Opt

@@ -12,48 +12,48 @@
 
 Target (driverlib), 0x0004 // Tools: 'ARM-ADS'
 GRPOPT 1,(Source),1,0,0
-GRPOPT 2,(Documentation),0,0,0
+GRPOPT 2,(Documentation),1,0,0
 
-OPTFFF 1,1,1,0,0,0,0,0,<.\adc.c><adc.c> 
-OPTFFF 1,2,1,0,0,0,0,0,<.\can.c><can.c> 
-OPTFFF 1,3,1,0,0,0,0,0,<.\comp.c><comp.c> 
-OPTFFF 1,4,1,0,0,0,0,0,<.\cpu.c><cpu.c> 
-OPTFFF 1,5,1,0,0,0,0,0,<.\epi.c><epi.c> 
-OPTFFF 1,6,1,0,0,0,0,0,<.\ethernet.c><ethernet.c> 
-OPTFFF 1,7,1,0,0,0,0,0,<.\flash.c><flash.c> 
-OPTFFF 1,8,1,0,0,0,0,0,<.\gpio.c><gpio.c> 
-OPTFFF 1,9,1,0,0,0,0,0,<.\hibernate.c><hibernate.c> 
-OPTFFF 1,10,1,0,0,0,0,0,<.\i2c.c><i2c.c> 
-OPTFFF 1,11,1,0,0,0,0,0,<.\i2s.c><i2s.c> 
-OPTFFF 1,12,1,0,0,0,0,0,<.\interrupt.c><interrupt.c> 
-OPTFFF 1,13,1,0,0,0,0,0,<.\mpu.c><mpu.c> 
-OPTFFF 1,14,1,0,0,0,0,0,<.\pwm.c><pwm.c> 
-OPTFFF 1,15,1,0,0,0,0,0,<.\qei.c><qei.c> 
-OPTFFF 1,16,1,0,0,0,0,0,<.\ssi.c><ssi.c> 
-OPTFFF 1,17,1,0,0,0,0,0,<.\sysctl.c><sysctl.c> 
-OPTFFF 1,18,1,0,0,0,0,0,<.\systick.c><systick.c> 
-OPTFFF 1,19,1,0,0,0,0,0,<.\timer.c><timer.c> 
-OPTFFF 1,20,1,738197506,0,707,707,0,<.\uart.c><uart.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,0,0,0,0,0,0,0,0,182,2,0,0,196,0,0,0 }
-OPTFFF 1,21,1,0,0,0,0,0,<.\udma.c><udma.c> 
-OPTFFF 1,22,1,0,0,0,0,0,<.\usb.c><usb.c> 
-OPTFFF 1,23,1,0,0,0,0,0,<.\watchdog.c><watchdog.c> 
-OPTFFF 2,24,5,0,0,0,0,0,<.\readme.txt><readme.txt> 
+OPTFFF 1,1,1,0,0,0,0,0,<.\adc.c><adc.c>
+OPTFFF 1,2,1,0,0,0,0,0,<.\can.c><can.c>
+OPTFFF 1,3,1,0,0,0,0,0,<.\comp.c><comp.c>
+OPTFFF 1,4,1,0,0,0,0,0,<.\cpu.c><cpu.c>
+OPTFFF 1,5,1,0,0,0,0,0,<.\epi.c><epi.c>
+OPTFFF 1,6,1,0,0,0,0,0,<.\ethernet.c><ethernet.c>
+OPTFFF 1,7,1,0,0,0,0,0,<.\flash.c><flash.c>
+OPTFFF 1,8,1,0,0,0,0,0,<.\gpio.c><gpio.c>
+OPTFFF 1,9,1,0,0,0,0,0,<.\hibernate.c><hibernate.c>
+OPTFFF 1,10,1,0,0,0,0,0,<.\i2c.c><i2c.c>
+OPTFFF 1,11,1,0,0,0,0,0,<.\i2s.c><i2s.c>
+OPTFFF 1,12,1,0,0,0,0,0,<.\interrupt.c><interrupt.c>
+OPTFFF 1,13,1,0,0,0,0,0,<.\mpu.c><mpu.c>
+OPTFFF 1,14,1,0,0,0,0,0,<.\pwm.c><pwm.c>
+OPTFFF 1,15,1,0,0,0,0,0,<.\qei.c><qei.c>
+OPTFFF 1,16,1,0,0,0,0,0,<.\ssi.c><ssi.c>
+OPTFFF 1,17,1,0,0,0,0,0,<.\sysctl.c><sysctl.c>
+OPTFFF 1,18,1,0,0,0,0,0,<.\systick.c><systick.c>
+OPTFFF 1,19,1,0,0,0,0,0,<.\timer.c><timer.c>
+OPTFFF 1,20,1,0,0,0,0,0,<.\uart.c><uart.c>
+OPTFFF 1,21,1,0,0,0,0,0,<.\udma.c><udma.c>
+OPTFFF 1,22,1,0,0,0,0,0,<.\usb.c><usb.c>
+OPTFFF 1,23,1,0,0,0,0,0,<.\watchdog.c><watchdog.c>
+OPTFFF 2,24,5,2,0,1,1,0,<.\readme.txt><readme.txt> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,217,2,0,0,44,1,0,0 }
 
+ExtF <.\readme.txt> 1,1,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,0,0,0,217,2,0,0,44,1,0,0 }
 
 TARGOPT 1, (driverlib)
- ADSCLK=6000000
-  OPTTT 0,1,1,0
+ ADSCLK=20000000
+  OPTTT 1,1,1,0
   OPTHX 1,65535,0,0,0
   OPTLX 79,66,8,<.\rvmdk\>
   OPTOX 16
   OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
   OPTXL 1,1,1,1,1,1,1,0,0
   OPTFL 1,0,1
-  OPTAX 0
-  OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)
+  OPTBL 0,(Data Sheet)<DATASHTS\Luminary\LM3S101.PDF>
+  OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101)
   OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
-  OPTDF 0x0
+  OPTDF 0x40000002
   OPTLE <>
   OPTLC <>
 EndOpt
-

bsp/lm3s/Libraries/driverlib/driverlib.Uv2

@@ -6,41 +6,41 @@ Target (driverlib), 0x0004 // Tools: 'ARM-ADS'
 Group (Source)
 Group (Documentation)
 
-File 1,1,<.\adc.c><adc.c>
-File 1,1,<.\can.c><can.c>
-File 1,1,<.\comp.c><comp.c>
-File 1,1,<.\cpu.c><cpu.c>
-File 1,1,<.\epi.c><epi.c>
-File 1,1,<.\ethernet.c><ethernet.c>
-File 1,1,<.\flash.c><flash.c>
-File 1,1,<.\gpio.c><gpio.c>
-File 1,1,<.\hibernate.c><hibernate.c>
-File 1,1,<.\i2c.c><i2c.c>
-File 1,1,<.\i2s.c><i2s.c>
-File 1,1,<.\interrupt.c><interrupt.c>
-File 1,1,<.\mpu.c><mpu.c>
-File 1,1,<.\pwm.c><pwm.c>
-File 1,1,<.\qei.c><qei.c>
-File 1,1,<.\ssi.c><ssi.c>
-File 1,1,<.\sysctl.c><sysctl.c>
-File 1,1,<.\systick.c><systick.c>
-File 1,1,<.\timer.c><timer.c>
-File 1,1,<.\uart.c><uart.c>
-File 1,1,<.\udma.c><udma.c>
-File 1,1,<.\usb.c><usb.c>
-File 1,1,<.\watchdog.c><watchdog.c>
-File 2,5,<.\readme.txt><readme.txt>
+File 1,1,<.\adc.c><adc.c> 0x0
+File 1,1,<.\can.c><can.c> 0x0
+File 1,1,<.\comp.c><comp.c> 0x0
+File 1,1,<.\cpu.c><cpu.c> 0x0
+File 1,1,<.\epi.c><epi.c> 0x0
+File 1,1,<.\ethernet.c><ethernet.c> 0x0
+File 1,1,<.\flash.c><flash.c> 0x0
+File 1,1,<.\gpio.c><gpio.c> 0x0
+File 1,1,<.\hibernate.c><hibernate.c> 0x0
+File 1,1,<.\i2c.c><i2c.c> 0x0
+File 1,1,<.\i2s.c><i2s.c> 0x0
+File 1,1,<.\interrupt.c><interrupt.c> 0x0
+File 1,1,<.\mpu.c><mpu.c> 0x0
+File 1,1,<.\pwm.c><pwm.c> 0x0
+File 1,1,<.\qei.c><qei.c> 0x0
+File 1,1,<.\ssi.c><ssi.c> 0x0
+File 1,1,<.\sysctl.c><sysctl.c> 0x0
+File 1,1,<.\systick.c><systick.c> 0x0
+File 1,1,<.\timer.c><timer.c> 0x0
+File 1,1,<.\uart.c><uart.c> 0x0
+File 1,1,<.\udma.c><udma.c> 0x0
+File 1,1,<.\usb.c><usb.c> 0x0
+File 1,1,<.\watchdog.c><watchdog.c> 0x0
+File 2,5,<.\readme.txt><readme.txt> 0x0
 
 
 Options 1,0,0  // Target 'driverlib'
- Device (LM3S6965)
+ Device (LM3S101)
  Vendor (Luminary Micro)
- Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(6000000) CPUTYPE("Cortex-M3"))
+ Cpu (IRAM(0x20000000-0x200007FF) IROM(0-0x1FFF) CLOCK(20000000) CPUTYPE("Cortex-M3"))
  FlashUt ()
  StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))
- FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_256 -FS00 -FL040000))
- DevID (4337)
- Rgf (LM3Sxxxx.H)
+ FlashDR (UL2CM3(-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000))
+ DevID (4079)
+ Rgf (LM3Sxxx.H)
  Mem ()
  C ()
  A ()
@@ -56,7 +56,7 @@ Options 1,0,0  // Target 'driverlib'
  EnvLib ()
  EnvReg (ÿLuminary\)
  OrgReg (ÿLuminary\)
- TgStat=16
+ TgStat=0
  OutDir (.\rvmdk\)
  OutName (driverlib)
  GenApp=0
@@ -77,14 +77,13 @@ Options 1,0,0  // Target 'driverlib'
  SVCSID <>
  GLFLAGS=1790
  ADSFLGA { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- ACPUTYP ("Cortex-M3")
- RVDEV ()
- ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP (Cortex-M3)
+ ADSTFLGA { 0,12,0,18,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
  OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
- OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }
- OCMADSIROM { 1,0,0,0,0,0,0,4,0 }
+ OCMADSIRAM { 0,0,0,0,32,0,128,0,0 }
+ OCMADSIROM { 1,0,0,0,0,0,120,1,0 }
  OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
- OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,8,0,0,0,0,0,0,0,0,0,0,0 }
  RV_STAVEC ()
  ADSCCFLG { 12,34,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
  ADSCMISC ()
@@ -114,11 +113,10 @@ Options 1,0,0  // Target 'driverlib'
  ADSLDMC ()
  ADSLDIF ()
  ADSLDDW ()
-  OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S6965)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S6965)
+  OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S101)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S101)
   OPTDBG 48125,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
- FLASH1 { 1,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH1 { 1,0,0,0,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0 }
  FLASH2 (BIN\UL2CM3.DLL)
  FLASH3 ("" ())
  FLASH4 ()
 EndOpt
-

bsp/lm3s/Libraries/driverlib/epi.c

@@ -2,26 +2,23 @@
 //
 // epi.c - Driver for the EPI module.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -50,7 +47,7 @@
 //! This functions sets the operating mode of the EPI module.  The parameter
 //! \e ulMode must be one of the following:
 //!
-//! - \b EPI_MODE_NONE - non-moded operation
+//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation
 //! - \b EPI_MODE_SDRAM - use with SDRAM device
 //! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
 //! - \b EPI_MODE_DISABLE - disable the EPI module
@@ -68,7 +65,7 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode)
     // Check the arguments.
     //
     ASSERT(ulBase == EPI0_BASE);
-    ASSERT((ulMode == EPI_MODE_NONE) ||
+    ASSERT((ulMode == EPI_MODE_GENERAL) ||
            (ulMode == EPI_MODE_SDRAM) ||
            (ulMode == EPI_MODE_HB8) ||
            (ulMode == EPI_MODE_DISABLE));
@@ -87,13 +84,21 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode)
 //! \param ulDivider is the value of the clock divider to be applied to
 //! the external interface (0-65535).
 //!
-//! This functions sets the clock divider that will be used to determine the
-//! clock rate of the external interface.  The value is the number of high
-//! and low ticks of the system clock per external bus clock.  A value of 0
-//! means that the system clock is used without any reduction.  The system
-//! clock will be divided by the value of \e ulDivider multiplied by 2.  A
-//! value of 1 gives a divider of 2, and value of 2 gives a divider of 4, a
-//! value of 3 gives a divider of 6, and so on.
+//! This functions sets the clock divider(s) that will be used to determine the
+//! clock rate of the external interface.  The \e ulDivider value is used to
+//! derive the EPI clock rate from the system clock based upon the following
+//! formula.
+//!
+//! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
+//!
+//! For example, a divider value of 1 results in an EPI clock rate of half
+//! the system clock, value of 2 or 3 yield one quarter of the system clock and
+//! a value of 4 results in one sixth of the system clock rate.
+//!
+//! In cases where a dual chip select mode is in use and different clock rates
+//! are required for each chip select, the \e ulDivider parameter must contain
+//! two dividers.  The lower 16 bits define the divider to be used with CS0n
+//! and the upper 16 bits define the divider for CS1n.
 //!
 //! \return None.
 //
@@ -198,6 +203,26 @@ EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
 //! - one of \b EPI_HB8_RDWAIT_0, \b EPI_HB8_RDWAIT_1, \b EPI_HB8_RDWAIT_2,
 //! or \b EPI_HB8_RDWAIT_3 to select the number of read wait states (default
 //! is 0 wait states)
+//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the
+//! correct byte lanes allowing data to be stored in bits [31:8].  If absent,
+//! all data transfers use bits [7:0].
+//! - \b EPI_HB8_CSBAUD_DUAL - use different baud rates when accessing devices
+//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the
+//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the
+//! upper 16 bits.  If this option is absent, both chip selects use the baud
+//! rate resulting from the divider in the lower 16 bits of the parameter passed
+//! to EPIDividerSet().
+//! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE,
+//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL. \b EPI_HB8_CSCFG_CS
+//! sets EPI30 to operate as a Chip Select (CSn) signal.  When using this mode,
+//! \b EPI_HB8_MODE_ADMUX must not be specified. \b EPI_HB8_CSCFG_ALE sets
+//! EPI30 to operate as an address latch (ALE). \b EPI_HB8_CSCFG_DUAL_CS sets
+//! EPI30 to operate as CS0n and EPI27 as CS1n with the asserted chip select
+//! determined from the most significant address bit for the respective external
+//! address map. \b EPI_HB8_CSCFG_DUAL_ALE sets EPI30 as an address latch (ALE),
+//! EPI27 as CS0n and EPI26 as CS1n with the asserted chip select determined
+//! from the most significant address bit for the respective external address
+//! map.
 //!
 //! The parameter \e ulMaxWait is used if the FIFO mode is chosen.  If a
 //! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
@@ -218,6 +243,12 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
     ASSERT(ulBase == EPI0_BASE);
     ASSERT(ulMaxWait < 256);
 
+    //
+    // Determine the CS and word access modes.
+    //
+    HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ?
+                                       EPI_HB8CFG2_WORD : 0) |
+                                     ((ulConfig & EPI_HB8_CSBAUD_DUAL) ?                                       EPI_HB8CFG2_CSBAUD : 0) |                                      ((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
     //
     // Fill in the max wait field of the configuration word.
     //
@@ -225,14 +256,14 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
     ulConfig |= ulMaxWait << EPI_HB8CFG_MAXWAIT_S;
 
     //
-    // Write the non-moded configuration register.
+    // Write the main HostBus8 configuration register.
     //
-    HWREG(ulBase + EPI_O_HB8CFG) = ulConfig;
+    HWREG(ulBase + EPI_O_HB8CFG)  = ulConfig;
 }
 
 //*****************************************************************************
 //
-//! Configures the interface for non-moded operation.
+//! Configures the interface for general-purpose mode operation.
 //!
 //! \param ulBase is the EPI module base address.
 //! \param ulConfig is the interface configuration.
@@ -241,37 +272,44 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
 //! \param ulMaxWait is the maximum number of external clocks to wait
 //! when the external clock enable is holding off the transaction (0-255).
 //!
-//! This function is used to configure the interface when used in non-moded
-//! operation as chosen with the function EPIModeSet().  The parameter
+//! This function is used to configure the interface when used in
+//! general-purpose operation as chosen with the function EPIModeSet().  The
+//! parameter
 //! \e ulConfig is the logical OR of any of the following:
 //!
-//! - \b EPI_NONMODE_CLKPIN - interface clock is output on a pin
-//! - \b EPI_NONMODE_CLKSTOP - clock is stopped when there is no transaction,
+//! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin
+//! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction,
 //! otherwise it is free-running
-//! - \b EPI_NONMODE_CLKENA - enable the clock enable input from the device
-//! - \b EPI_NONMODE_FRAMEPIN - framing signal is emitted on a pin
-//! - \b EPI_NONMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
+//! - \b EPI_GPMODE_RDYEN - the external peripheral drives an iRDY signal into
+//! pin EPI0S27.  If absent, the peripheral is assumed to be ready at all times.
+//! This flag may only be used with a free-running clock (\b EPI_GPMODE_CLKGATE
+//! is absent).
+//! - \b EPI_GPMODE_FRAMEPIN - framing signal is emitted on a pin
+//! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
 //! is a pulse
-//! - \b EPI_NONMODE_READWRITE - read and write strobes are emitted on pins
-//! - \b EPI_NONMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
+//! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins
+//! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
 //! single-cycle write is used
-//! - \b EPI_NONMODE_READ2CYCLE - a two cycle read is used, otherwise a
+//! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a
 //! single-cycle read is used
-//! - \b EPI_NONMODE_ASIZE_NONE, \b EPI_NONMODE_ASIZE_4,
-//! \b EPI_NONMODE_ASIZE_12, or \b EPI_NONMODE_ASIZE_20 to choose no address
+//! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4,
+//! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address
 //! bus, or and address bus size of 4, 12, or 20 bits
-//! - \b EPI_NONMODE_DSIZE_8, \b EPI_NONMODE_DSIZE_16,
-//! \b EPI_NONMODE_DSIZE_24, or \b EPI_NONMODE_DSIZE_32 to select a data bus
+//! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16,
+//! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus
 //! size of 8, 16, 24, or 32 bits
+//! - \b EPI_GPMODE_WORD_ACCESS - use Word Access mode to route bytes to the
+//! correct byte lanes allowing data to be stored in the upper bits of the word
+//! when necessary.
 //!
 //! The parameter \e ulFrameCount is the number of clocks used to form the
 //! framing signal, if the framing signal is used.  The behavior depends on
 //! whether the frame signal is a pulse or a 50/50 duty cycle.  This value
 //! is not used if the framing signal is not enabled with the option
-//! \b EPI_NONMMODE_FRAMEPIN.
+//! \b EPI_GPMODE_FRAMEPIN.
 //!
 //! The parameter \e ulMaxWait is used if the external clock enable is turned
-//! on with the \b EPI_NONMODE_CLKENA option is used.  In the case that
+//! on with the \b EPI_GPMODE_CLKENA option is used.  In the case that
 //! external clock enable is used, this parameter determines the maximum
 //! number of clocks to wait when the external clock enable signal is holding
 //! off a transaction.  A value of 0 means to wait forever.  If a non-zero
@@ -282,7 +320,7 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
 //
 //*****************************************************************************
 void
-EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig,
+EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
                    unsigned long ulFrameCount, unsigned long ulMaxWait)
 {
     //
@@ -292,6 +330,12 @@ EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig,
     ASSERT(ulFrameCount < 16);
     ASSERT(ulMaxWait < 256);
 
+    //
+    // Set the word access mode.
+    //
+    HWREG(ulBase + EPI_O_GPCFG2) = ((ulConfig & EPI_GPMODE_WORD_ACCESS) ?
+                                    EPI_GPCFG2_WORD : 0);
+
     //
     // Fill in the frame count field of the configuration word.
     //
@@ -778,7 +822,7 @@ EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig)
 //
 //*****************************************************************************
 unsigned long
-EPINonBlockingWriteCount(unsigned long ulBase)
+EPIWriteFIFOCountGet(unsigned long ulBase)
 {
     //
     // Check the arguments.

bsp/lm3s/Libraries/driverlib/epi.h

@@ -2,26 +2,23 @@
 //
 // epi.h - Prototypes and macros for the EPI module.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -44,7 +41,7 @@ extern "C"
 // Values that can be passed to EPIModeSet()
 //
 //*****************************************************************************
-#define EPI_MODE_NONE                   0x00000010
+#define EPI_MODE_GENERAL                0x00000010
 #define EPI_MODE_SDRAM                  0x00000011
 #define EPI_MODE_HB8                    0x00000012
 #define EPI_MODE_DISABLE                0x00000000
@@ -67,25 +64,26 @@ extern "C"
 
 //*****************************************************************************
 //
-// Values that can be passed to EPIConfigNoModeSet()
+// Values that can be passed to EPIConfigGPModeSet()
 //
 //*****************************************************************************
-#define EPI_NONMODE_CLKPIN              0x80000000
-#define EPI_NONMODE_CLKSTOP             0x40000000
-#define EPI_NONMODE_CLKENA              0x10000000
-#define EPI_NONMODE_FRAMEPIN            0x08000000
-#define EPI_NONMODE_FRAME50             0x04000000
-#define EPI_NONMODE_READWRITE           0x00200000
-#define EPI_NONMODE_WRITE2CYCLE         0x00080000
-#define EPI_NONMODE_READ2CYCLE          0x00040000
-#define EPI_NONMODE_ASIZE_NONE          0x00000000
-#define EPI_NONMODE_ASIZE_4             0x00000010
-#define EPI_NONMODE_ASIZE_12            0x00000020
-#define EPI_NONMODE_ASIZE_20            0x00000030
-#define EPI_NONMODE_DSIZE_8             0x00000000
-#define EPI_NONMODE_DSIZE_16            0x00000001
-#define EPI_NONMODE_DSIZE_24            0x00000002
-#define EPI_NONMODE_DSIZE_32            0x00000003
+#define EPI_GPMODE_CLKPIN               0x80000000
+#define EPI_GPMODE_CLKGATE              0x40000000
+#define EPI_GPMODE_RDYEN                0x10000000
+#define EPI_GPMODE_FRAMEPIN             0x08000000
+#define EPI_GPMODE_FRAME50              0x04000000
+#define EPI_GPMODE_READWRITE            0x00200000
+#define EPI_GPMODE_WRITE2CYCLE          0x00080000
+#define EPI_GPMODE_READ2CYCLE           0x00040000
+#define EPI_GPMODE_ASIZE_NONE           0x00000000
+#define EPI_GPMODE_ASIZE_4              0x00000010
+#define EPI_GPMODE_ASIZE_12             0x00000020
+#define EPI_GPMODE_ASIZE_20             0x00000030
+#define EPI_GPMODE_DSIZE_8              0x00000000
+#define EPI_GPMODE_DSIZE_16             0x00000001
+#define EPI_GPMODE_DSIZE_24             0x00000002
+#define EPI_GPMODE_DSIZE_32             0x00000003
+#define EPI_GPMODE_WORD_ACCESS          0x00000100
 
 //*****************************************************************************
 //
@@ -108,6 +106,14 @@ extern "C"
 #define EPI_HB8_MODE_ADDEMUX            0x00000001
 #define EPI_HB8_MODE_SRAM               0x00000002
 #define EPI_HB8_MODE_FIFO               0x00000003
+#define EPI_HB8_WORD_ACCESS             0x00000100
+#define EPI_HB8_CSCFG_ALE               0x00000000
+#define EPI_HB8_CSCFG_CS                0x00000200
+#define EPI_HB8_CSCFG_DUAL_CS           0x00000400
+#define EPI_HB8_CSCFG_ALE_DUAL_CS       0x00000600
+#define EPI_HB8_CSBAUD_DUAL             0x00000800
+
+#define EPI_HB8_CSCFG_MASK              0x00000600
 
 //*****************************************************************************
 //
@@ -117,14 +123,14 @@ extern "C"
 #define EPI_ADDR_PER_SIZE_256B          0x00000000
 #define EPI_ADDR_PER_SIZE_64KB          0x00000040
 #define EPI_ADDR_PER_SIZE_16MB          0x00000080
-#define EPI_ADDR_PER_SIZE_512MB         0x000000C0
+#define EPI_ADDR_PER_SIZE_256MB         0x000000C0
 #define EPI_ADDR_PER_BASE_NONE          0x00000000
 #define EPI_ADDR_PER_BASE_A             0x00000010
 #define EPI_ADDR_PER_BASE_C             0x00000020
 #define EPI_ADDR_RAM_SIZE_256B          0x00000000
 #define EPI_ADDR_RAM_SIZE_64KB          0x00000004
 #define EPI_ADDR_RAM_SIZE_16MB          0x00000008
-#define EPI_ADDR_RAM_SIZE_512MB         0x0000000C
+#define EPI_ADDR_RAM_SIZE_256MB         0x0000000C
 #define EPI_ADDR_RAM_BASE_NONE          0x00000000
 #define EPI_ADDR_RAM_BASE_6             0x00000001
 #define EPI_ADDR_RAM_BASE_8             0x00000002
@@ -181,41 +187,76 @@ extern "C"
 // API Function prototypes
 //
 //*****************************************************************************
-void EPIModeSet(unsigned long ulBase, unsigned long ulMode);
-void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider);
-void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
-                       unsigned long ulRefresh);
-void EPIConfigNoModeSet(unsigned long ulBase, unsigned long ulConfig,
-                        unsigned long ulFrameCount, unsigned long ulMaxWait);
-void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
-                     unsigned long ulMaxWait);
-void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
-void EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
-                            unsigned long ulDataSize, unsigned long ulAddress);
-void EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel,
-                             unsigned long ulCount);
-void EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel);
-unsigned long EPINonBlockingReadCount(unsigned long ulBase,
-                                      unsigned long ulChannel);
-unsigned long EPINonBlockingReadAvail(unsigned long ulBase);
-unsigned long EPINonBlockingReadGet32(unsigned long ulBase,
-                                      unsigned long ulCount,
-                                      unsigned long *pulBuf);
-unsigned long EPINonBlockingReadGet16(unsigned long ulBase,
-                                      unsigned long ulCount,
-                                      unsigned short *pusBuf);
-unsigned long EPINonBlockingReadGet8(unsigned long ulBase,
-                                     unsigned long ulCount,
-                                     unsigned char *pucBuf);
-void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig);
-unsigned long EPINonBlockingWriteCount(unsigned long ulBase);
-void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
-void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked);
-unsigned long EPIIntErrorStatus(unsigned long ulBase);
-void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags);
-void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
-void EPIIntUnregister(unsigned long ulBase);
+extern void EPIModeSet(unsigned long ulBase, unsigned long ulMode);
+extern void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider);
+extern void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
+                              unsigned long ulRefresh);
+extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
+                               unsigned long ulFrameCount,
+                               unsigned long ulMaxWait);
+extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
+                            unsigned long ulMaxWait);
+extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
+extern void EPINonBlockingReadConfigure(unsigned long ulBase,
+                                        unsigned long ulChannel,
+                                        unsigned long ulDataSize,
+                                        unsigned long ulAddress);
+extern void EPINonBlockingReadStart(unsigned long ulBase,
+                                    unsigned long ulChannel,
+                                    unsigned long ulCount);
+extern void EPINonBlockingReadStop(unsigned long ulBase,
+                                   unsigned long ulChannel);
+extern unsigned long EPINonBlockingReadCount(unsigned long ulBase,
+                                             unsigned long ulChannel);
+extern unsigned long EPINonBlockingReadAvail(unsigned long ulBase);
+extern unsigned long EPINonBlockingReadGet32(unsigned long ulBase,
+                                             unsigned long ulCount,
+                                             unsigned long *pulBuf);
+extern unsigned long EPINonBlockingReadGet16(unsigned long ulBase,
+                                             unsigned long ulCount,
+                                             unsigned short *pusBuf);
+extern unsigned long EPINonBlockingReadGet8(unsigned long ulBase,
+                                            unsigned long ulCount,
+                                            unsigned char *pucBuf);
+extern void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig);
+extern unsigned long EPIWriteFIFOCountGet(unsigned long ulBase);
+extern void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern unsigned long EPIIntErrorStatus(unsigned long ulBase);
+extern void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags);
+extern void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void EPIIntUnregister(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several EPI APIs and labels have been renamed, with the original definition
+// name being deprecated.  These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define EPI_MODE_NONE           EPI_MODE_GENERAL
+#define EPI_NONMODE_CLKPIN      EPI_GPMODE_CLKPIN
+#define EPI_NONMODE_CLKSTOP     EPI_GPMODE_CLKGATE
+#define EPI_NONMODE_CLKENA      EPI_GPMODE_RDYEN
+#define EPI_NONMODE_FRAMEPIN    EPI_GPMODE_FRAMEPIN
+#define EPI_NONMODE_FRAME50     EPI_GPMODE_FRAME50
+#define EPI_NONMODE_READWRITE   EPI_GPMODE_READWRITE
+#define EPI_NONMODE_WRITE2CYCLE EPI_GPMODE_WRITE2CYCLE
+#define EPI_NONMODE_READ2CYCLE  EPI_GPMODE_READ2CYCLE
+#define EPI_NONMODE_ASIZE_NONE  EPI_GPMODE_ASIZE_NONE
+#define EPI_NONMODE_ASIZE_4     EPI_GPMODE_ASIZE_4
+#define EPI_NONMODE_ASIZE_12    EPI_GPMODE_ASIZE_12
+#define EPI_NONMODE_ASIZE_20    EPI_GPMODE_ASIZE_20
+#define EPI_NONMODE_DSIZE_8     EPI_GPMODE_DSIZE_8
+#define EPI_NONMODE_DSIZE_16    EPI_GPMODE_DSIZE_16
+#define EPI_NONMODE_DSIZE_24    EPI_GPMODE_DSIZE_24
+#define EPI_NONMODE_DSIZE_32    EPI_GPMODE_DSIZE_32
+#define EPI_NONMODE_WORD_ACCESS EPI_GPMODE_WORD_ACCESS
+
+#define EPINonBlockingWriteCount(a) EPIWriteFIFOCountGet(a)
+#define EPIConfigNoModeSet(a, b, c, d) EPIConfigGPModeSet((a), (b), (c), (d))
+#endif
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/ethernet.c

@@ -2,26 +2,23 @@
 //
 // ethernet.c - Driver for the Integrated Ethernet Controller
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/ethernet.h

@@ -2,26 +2,23 @@
 //
 // ethernet.h - Defines and Macros for the ethernet module.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/flash.c

@@ -2,26 +2,23 @@
 //
 // flash.c - Driver for programming the on-chip flash.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -802,7 +799,7 @@ FlashIntUnregister(void)
 //! Enables individual flash controller interrupt sources.
 //!
 //! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
-//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
 //!
 //! Enables the indicated flash controller interrupt sources.  Only the sources
 //! that are enabled can be reflected to the processor interrupt; disabled
@@ -825,7 +822,7 @@ FlashIntEnable(unsigned long ulIntFlags)
 //! Disables individual flash controller interrupt sources.
 //!
 //! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
-//! Can be any of the \b FLASH_FCIM_PROGRAM or \b FLASH_FCIM_ACCESS values.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
 //!
 //! Disables the indicated flash controller interrupt sources.  Only the
 //! sources that are enabled can be reflected to the processor interrupt;
@@ -855,11 +852,11 @@ FlashIntDisable(unsigned long ulIntFlags)
 //! the processor can be returned.
 //!
 //! \return The current interrupt status, enumerated as a bit field of
-//! \b FLASH_FCMISC_PROGRAM and \b FLASH_FCMISC_AMISC.
+//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
 //
 //*****************************************************************************
 unsigned long
-FlashIntGetStatus(tBoolean bMasked)
+FlashIntStatus(tBoolean bMasked)
 {
     //
     // Return either the interrupt status or the raw interrupt status as
@@ -880,7 +877,7 @@ FlashIntGetStatus(tBoolean bMasked)
 //! Clears flash controller interrupt sources.
 //!
 //! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
-//! Can be any of the \b FLASH_FCMISC_PROGRAM or \b FLASH_FCMISC_AMISC values.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
 //!
 //! The specified flash controller interrupt sources are cleared, so that they
 //! no longer assert.  This must be done in the interrupt handler to keep it

bsp/lm3s/Libraries/driverlib/flash.h

@@ -2,26 +2,23 @@
 //
 // flash.h - Prototypes for the flash driver.
 //
-// Copyright (c) 2005-2007 Luminary Micro, Inc.  All rights reserved
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -53,6 +50,15 @@ typedef enum
 }
 tFlashProtection;
 
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_PROGRAM       0x00000002  // Programming Interrupt Mask
+#define FLASH_INT_ACCESS        0x00000001  // Access Interrupt Mask
+
 //*****************************************************************************
 //
 // Prototypes for the APIs.
@@ -74,9 +80,20 @@ extern void FlashIntRegister(void (*pfnHandler)(void));
 extern void FlashIntUnregister(void);
 extern void FlashIntEnable(unsigned long ulIntFlags);
 extern void FlashIntDisable(unsigned long ulIntFlags);
-extern unsigned long FlashIntGetStatus(tBoolean bMasked);
+extern unsigned long FlashIntStatus(tBoolean bMasked);
 extern void FlashIntClear(unsigned long ulIntFlags);
 
+//*****************************************************************************
+//
+// Deprecated function names.  These definitions ensure backwards compatibility
+// but new code should avoid using deprecated function names since these will
+// be removed at some point in the future.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define FlashIntGetStatus       FlashIntStatus
+#endif
+
 //*****************************************************************************
 //
 // Mark the end of the C bindings section for C++ compilers.

bsp/lm3s/Libraries/driverlib/gpio.c

@@ -2,26 +2,23 @@
 //
 // gpio.c - API for GPIO ports
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -215,6 +212,9 @@ GPIOGetIntNumber(unsigned long ulPort)
 //! set identifies the pin to be accessed, and where bit 0 of the byte
 //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
 //!
+//! \note GPIOPadConfigSet() must also be used to configure the corresponding
+//! pad(s) in order for them to propagate the signal to/from the GPIO.
+//!
 //! \return None.
 //
 //*****************************************************************************
@@ -1333,6 +1333,10 @@ GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
 //! the digital USB pin(s); other configurations may work as well depending
 //! upon the board setup (for example, using the on-chip pull-ups).
 //!
+//! This function should only be used with EPEN and PFAULT pins as all other
+//! USB pins are analog in nature or are not used in devices without OTG
+//! functionality.
+//!
 //! The pin(s) are specified using a bit-packed byte, where each bit that is
 //! set identifies the pin to be accessed, and where bit 0 of the byte
 //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
@@ -1371,7 +1375,8 @@ GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
 //!
 //! Some USB analog pins must be properly configured for the USB peripheral to
 //! function correctly.  This function provides the proper configuration for
-//! those pin(s).
+//! any USB pin(s).  This can also be used to configure the EPEN and PFAULT pins
+//! so that they are no longer used by the USB controller.
 //!
 //! The pin(s) are specified using a bit-packed byte, where each bit that is
 //! set identifies the pin to be accessed, and where bit 0 of the byte
@@ -1443,12 +1448,95 @@ GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
     GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
 }
 
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Ethernet peripheral as LED signals.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The Ethernet peripheral provides two signals that can be used to drive
+//! an LED (e.g. for link status/activity).  This function provides a typical
+//! configuration for the pins.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an Ethernet LED pin; it only
+//! configures an Ethernet LED pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the external peripheral interface.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The external peripheral interface pins must be properly configured for the
+//! external peripheral interface to function correctly.  This function
+//! provides a typica configuration for those pin(s); other configurations may
+//! work as well depending upon the board setup (for exampe, using the on-chip
+//! pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an external peripheral
+//! interface pin; it only configures an external peripheral interface pin for
+//! proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(GPIOBaseValid(ulPort));
+
+    //
+    // Make the pin(s) be peripheral controlled.
+    //
+    GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+    //
+    // Set the pad(s) for standard push-pull operation.
+    //
+    GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
 //*****************************************************************************
 //
 //! Configures the alternate function of a GPIO pin.
 //!
-//! \param ulPinConfig is the pin configuration value, specified as one of the
-//! \b GPIO_P??_??? values.
+//! \param ulPinConfig is the pin configuration value, specified as only one of
+//! the \b GPIO_P??_??? values.
 //!
 //! This function configures the pin mux that selects the peripheral function
 //! associated with a particular GPIO pin.  Only one peripheral function at a

bsp/lm3s/Libraries/driverlib/gpio.h

@@ -2,26 +2,23 @@
 //
 // gpio.h - Defines and Macros for GPIO API.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -742,6 +739,8 @@ extern void GPIOPinConfigure(unsigned long ulPinConfig);
 extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
 extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,

bsp/lm3s/Libraries/driverlib/hibernate.c

@@ -2,26 +2,23 @@
 //
 // hibernate.c - Driver for the Hibernation module
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/hibernate.h

@@ -2,26 +2,23 @@
 //
 // hibernate.h - API definition for the Hibernation module.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/i2c.c

@@ -2,26 +2,23 @@
 //
 // i2c.c - Driver for Inter-IC (I2C) bus block.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -950,7 +947,7 @@ I2CMasterErr(unsigned long ulBase)
     //
     // Check for errors.
     //
-    if(ulErr & I2C_MCS_ERROR)
+    if(ulErr & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
     {
         return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
     }

bsp/lm3s/Libraries/driverlib/i2c.h

@@ -2,26 +2,23 @@
 //
 // i2c.h - Prototypes for the I2C Driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -58,16 +55,26 @@ extern "C"
 // I2C Master commands.
 //
 //*****************************************************************************
-#define I2C_MASTER_CMD_SINGLE_SEND              0x00000007
-#define I2C_MASTER_CMD_SINGLE_RECEIVE           0x00000007
-#define I2C_MASTER_CMD_BURST_SEND_START         0x00000003
-#define I2C_MASTER_CMD_BURST_SEND_CONT          0x00000001
-#define I2C_MASTER_CMD_BURST_SEND_FINISH        0x00000005
-#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP    0x00000004
-#define I2C_MASTER_CMD_BURST_RECEIVE_START      0x0000000b
-#define I2C_MASTER_CMD_BURST_RECEIVE_CONT       0x00000009
-#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH     0x00000005
-#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005
+#define I2C_MASTER_CMD_SINGLE_SEND                                            \
+                                0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE                                         \
+                                0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START                                       \
+                                0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT                                        \
+                                0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH                                      \
+                                0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP                                  \
+                                0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START                                    \
+                                0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT                                     \
+                                0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH                                   \
+                                0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP                               \
+                                0x00000004
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/i2s.c

@@ -2,26 +2,23 @@
 //
 // i2s.c - Driver for the I2S controller.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/i2s.h

@@ -2,26 +2,23 @@
 //
 // i2s.h - Prototypes and macros for the I2S controller.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/interrupt.c

@@ -2,26 +2,23 @@
 //
 // interrupt.c - Driver for the NVIC Interrupt Controller.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -104,6 +101,9 @@ static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
 #elif defined(sourcerygxx)
 static __attribute__((section(".cs3.region-head.ram")))
 void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#elif defined(ccs)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
 #else
 static __attribute__((section("vtable")))
 void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
@@ -542,6 +542,181 @@ IntDisable(unsigned long ulInterrupt)
     }
 }
 
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller.  This will
+//! cause the interrupt controller to execute the corresponding interrupt
+//! handler at the next available time, based on the current interrupt state
+//! priorities.  For example, if called by a higher priority interrupt handler,
+//! the specified interrupt handler will not be called until after the current
+//! interrupt handler has completed execution.  The interrupt must have been
+//! enabled for it to be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendSet(unsigned long ulInterrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to pend.
+    //
+    if(ulInterrupt == FAULT_NMI)
+    {
+        //
+        // Pend the NMI interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
+    }
+    else if(ulInterrupt == FAULT_PENDSV)
+    {
+        //
+        // Pend the PendSV interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
+    }
+    else if(ulInterrupt == FAULT_SYSTICK)
+    {
+        //
+        // Pend the SysTick interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
+    }
+    else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
+    }
+    else if(ulInterrupt >= 48)
+    {
+        //
+        // Pend the general interrupt.
+        //
+        HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
+    }
+}
+
+//*****************************************************************************
+//
+//! Unpends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be unpended.
+//!
+//! The specified interrupt is unpended in the interrupt controller.  This will
+//! cause any previously generated interrupts that have not been handled yet
+//! (due to higher priority interrupts or the interrupt no having been enabled
+//! yet) to be discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendClear(unsigned long ulInterrupt)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+    //
+    // Determine the interrupt to unpend.
+    //
+    if(ulInterrupt == FAULT_PENDSV)
+    {
+        //
+        // Unpend the PendSV interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
+    }
+    else if(ulInterrupt == FAULT_SYSTICK)
+    {
+        //
+        // Unpend the SysTick interrupt.
+        //
+        HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
+    }
+    else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
+    }
+    else if(ulInterrupt >= 48)
+    {
+        //
+        // Unpend the general interrupt.
+        //
+        HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
+    }
+}
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param ulPriorityMask is the priority level that will be masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level is masked.  This
+//! can be used to globally disable a set of interrupts with priority below
+//! a predetermined threshold.  A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityMaskSet(unsigned long ulPriorityMask)
+{
+    CPUbasepriSet(ulPriorityMask);
+}
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level.  The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked.  A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities.  So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityMaskGet(void)
+{
+    return(CPUbasepriGet());
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.

bsp/lm3s/Libraries/driverlib/interrupt.h

@@ -2,26 +2,23 @@
 //
 // interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -63,6 +60,10 @@ extern void IntPrioritySet(unsigned long ulInterrupt,
 extern long IntPriorityGet(unsigned long ulInterrupt);
 extern void IntEnable(unsigned long ulInterrupt);
 extern void IntDisable(unsigned long ulInterrupt);
+extern void IntPendSet(unsigned long ulInterrupt);
+extern void IntPendClear(unsigned long ulInterrupt);
+extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
+extern unsigned long IntPriorityMaskGet(void);
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/mpu.c

@@ -2,26 +2,23 @@
 //
 // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/mpu.h

@@ -2,26 +2,23 @@
 //
 // mpu.h - Defines and Macros for the memory protection unit.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/pwm.c

@@ -2,26 +2,23 @@
 //
 // pwm.c - API for the PWM modules
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -1510,11 +1507,15 @@ PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
 //! \param ulGen is the PWM generator whose fault triggers are being set.  Must
 //! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of possible faults that are to be
-//! configured.  This must be \b PWM_FAULT_GROUP_0.
+//! configured.  This must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //! \param ulFaultTriggers defines the set of inputs that are to contribute
 //! towards generation of the fault signal to the given PWM generator.  For
 //! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
-//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.
+//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3.  For
+//! \b PWM_FAULT_GROUP_1, this will be the logical OR of \b PWM_FAULT_DCMP0,
+//!  \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b
+//! PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b
+//! PWM_FAULT_DCMP7.
 //!
 //! This function allows selection of the set of fault inputs that will be
 //! combined to generate a fault condition to a given PWM generator.  By
@@ -1545,8 +1546,14 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
     ASSERT(ulBase == PWM_BASE);
     ASSERT(PWMGenValid(ulGen));
     ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
-    ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
-                                PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+    ASSERT((ulGroup == PWM_FAULT_GROUP_0) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+                                 PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0));
+    ASSERT((ulGroup == PWM_FAULT_GROUP_1) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+                                 PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+                                 PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+                                 PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
 
     //
     // Write the fault triggers to the appropriate register.
@@ -1572,7 +1579,7 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
 //! \param ulGen is the PWM generator whose fault triggers are being queried.
 //! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of faults that are being queried.  This
-//! must be \b PWM_FAULT_GROUP_0.
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //!
 //! This function allows an application to query the current set of inputs that
 //! contribute towards the generation of a fault condition to a given PWM
@@ -1584,7 +1591,10 @@ PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
 //! \return Returns the current fault triggers configured for the fault group
 //! provided.  For \b PWM_FAULT_GROUP_0, the returned value will be a logical
 //! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
-//! \b PWM_FAULT_FAULT3.
+//! \b PWM_FAULT_FAULT3.  For \b PWM_FAULT_GROUP_1, the return value will be
+//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, \b
+//! PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5,
+//! \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
 //
 //*****************************************************************************
 unsigned long
@@ -1621,7 +1631,7 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
 //! queried.  Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
 //! \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of faults that are being queried.  This
-//! must be \b PWM_FAULT_GROUP_0.
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //!
 //! This function allows an application to query the current state of each of
 //! the fault trigger inputs to a given PWM generator.  The current state of
@@ -1640,7 +1650,10 @@ PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
 //! generator.  A set bit indicates that the associated trigger is active.  For
 //! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
 //! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
-//! \b PWM_FAULT_FAULT3.
+//! \b PWM_FAULT_FAULT3.  For \b PWM_FAULT_GROUP_1, the return value will be
+//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, \b
+//! PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5,
+//! \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
 //
 //*****************************************************************************
 unsigned long
@@ -1677,7 +1690,7 @@ PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
 //! queried.  Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
 //! \b PWM_GEN_3.
 //! \param ulGroup indicates the subset of faults that are being queried.  This
-//! must be \b PWM_FAULT_GROUP_0.
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
 //! \param ulFaultTriggers is the set of fault triggers which are to be
 //! cleared.
 //!
@@ -1702,8 +1715,14 @@ PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
     ASSERT(ulBase == PWM_BASE);
     ASSERT(PWMGenValid(ulGen));
     ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
-    ASSERT((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
-                                PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0);
+    ASSERT((ulGroup == PWM_FAULT_GROUP_0) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+                                 PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0));
+    ASSERT((ulGroup == PWM_FAULT_GROUP_1) &&
+           ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+                                 PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+                                 PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+                                 PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
 
     //
     // Clear the given faults.

bsp/lm3s/Libraries/driverlib/pwm.h

@@ -2,26 +2,23 @@
 //
 // pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -184,6 +181,15 @@ extern "C"
 //*****************************************************************************
 #define PWM_FAULT_GROUP_1       1
 
+#define PWM_FAULT_DCMP0         0x00000001
+#define PWM_FAULT_DCMP1         0x00000002
+#define PWM_FAULT_DCMP2         0x00000004
+#define PWM_FAULT_DCMP3         0x00000008
+#define PWM_FAULT_DCMP4         0x00000010
+#define PWM_FAULT_DCMP5         0x00000020
+#define PWM_FAULT_DCMP6         0x00000040
+#define PWM_FAULT_DCMP7         0x00000080
+
 //*****************************************************************************
 //
 // Defines to identify the sense of each of the external FAULTn signals

bsp/lm3s/Libraries/driverlib/qei.c

@@ -2,26 +2,23 @@
 //
 // qei.c - Driver for the Quadrature Encoder with Index.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/qei.h

@@ -2,26 +2,23 @@
 //
 // qei.h - Prototypes for the Quadrature Encoder Driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/readme.txt

@@ -2,23 +2,20 @@ This project will build the Stellaris Peripheral Driver Library.
 
 -------------------------------------------------------------------------------
 
-Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 Software License Agreement
 
-Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-exclusively on LMI's microcontroller products.
+Texas Instruments (TI) is supplying this software for use solely and
+exclusively on TI's microcontroller products. The software is owned by
+TI and/or its suppliers, and is protected under applicable copyright
+laws. You may not combine this software with "viral" open-source
+software in order to form a larger program.
 
-The software is owned by LMI and/or its suppliers, and is protected under
-applicable copyright laws.  All rights are reserved.  You may not combine
-this software with "viral" open-source software in order to form a larger
-program.  Any use in violation of the foregoing restrictions may subject
-the user to criminal sanctions under applicable laws, as well as to civil
-liability for the breach of the terms and conditions of this license.
+THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+DAMAGES, FOR ANY REASON WHATSOEVER.
 
-THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-
-This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+This is part of revision 6459 of the Stellaris Peripheral Driver Library.

bsp/lm3s/Libraries/driverlib/rom_map.h

@@ -3,26 +3,23 @@
 // rom_map.h - Macros to facilitate calling functions in the ROM when they are
 //             available and in flash otherwise.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -139,6 +136,55 @@
 #define MAP_ADCHardwareOversampleConfigure \
         ADCHardwareOversampleConfigure
 #endif
+#ifdef ROM_ADCComparatorConfigure
+#define MAP_ADCComparatorConfigure \
+        ROM_ADCComparatorConfigure
+#else
+#define MAP_ADCComparatorConfigure \
+        ADCComparatorConfigure
+#endif
+#ifdef ROM_ADCComparatorRegionSet
+#define MAP_ADCComparatorRegionSet \
+        ROM_ADCComparatorRegionSet
+#else
+#define MAP_ADCComparatorRegionSet \
+        ADCComparatorRegionSet
+#endif
+#ifdef ROM_ADCComparatorReset
+#define MAP_ADCComparatorReset \
+        ROM_ADCComparatorReset
+#else
+#define MAP_ADCComparatorReset \
+        ADCComparatorReset
+#endif
+#ifdef ROM_ADCComparatorIntDisable
+#define MAP_ADCComparatorIntDisable \
+        ROM_ADCComparatorIntDisable
+#else
+#define MAP_ADCComparatorIntDisable \
+        ADCComparatorIntDisable
+#endif
+#ifdef ROM_ADCComparatorIntEnable
+#define MAP_ADCComparatorIntEnable \
+        ROM_ADCComparatorIntEnable
+#else
+#define MAP_ADCComparatorIntEnable \
+        ADCComparatorIntEnable
+#endif
+#ifdef ROM_ADCComparatorIntStatus
+#define MAP_ADCComparatorIntStatus \
+        ROM_ADCComparatorIntStatus
+#else
+#define MAP_ADCComparatorIntStatus \
+        ADCComparatorIntStatus
+#endif
+#ifdef ROM_ADCComparatorIntClear
+#define MAP_ADCComparatorIntClear \
+        ROM_ADCComparatorIntClear
+#else
+#define MAP_ADCComparatorIntClear \
+        ADCComparatorIntClear
+#endif
 
 //*****************************************************************************
 //
@@ -257,6 +303,13 @@
 #define MAP_CANErrCntrGet \
         CANErrCntrGet
 #endif
+#ifdef ROM_CANBitRateSet
+#define MAP_CANBitRateSet \
+        ROM_CANBitRateSet
+#else
+#define MAP_CANBitRateSet \
+        CANBitRateSet
+#endif
 
 //*****************************************************************************
 //
@@ -313,6 +366,166 @@
         ComparatorIntStatus
 #endif
 
+//*****************************************************************************
+//
+// Macros for the Ethernet API.
+//
+//*****************************************************************************
+#ifdef ROM_EPIIntStatus
+#define MAP_EPIIntStatus \
+        ROM_EPIIntStatus
+#else
+#define MAP_EPIIntStatus \
+        EPIIntStatus
+#endif
+#ifdef ROM_EPIModeSet
+#define MAP_EPIModeSet \
+        ROM_EPIModeSet
+#else
+#define MAP_EPIModeSet \
+        EPIModeSet
+#endif
+#ifdef ROM_EPIDividerSet
+#define MAP_EPIDividerSet \
+        ROM_EPIDividerSet
+#else
+#define MAP_EPIDividerSet \
+        EPIDividerSet
+#endif
+#ifdef ROM_EPIConfigSDRAMSet
+#define MAP_EPIConfigSDRAMSet \
+        ROM_EPIConfigSDRAMSet
+#else
+#define MAP_EPIConfigSDRAMSet \
+        EPIConfigSDRAMSet
+#endif
+#ifdef ROM_EPIConfigGPModeSet
+#define MAP_EPIConfigGPModeSet \
+        ROM_EPIConfigGPModeSet
+#else
+#define MAP_EPIConfigGPModeSet \
+        EPIConfigGPModeSet
+#endif
+#ifdef ROM_EPIConfigHB8Set
+#define MAP_EPIConfigHB8Set \
+        ROM_EPIConfigHB8Set
+#else
+#define MAP_EPIConfigHB8Set \
+        EPIConfigHB8Set
+#endif
+#ifdef ROM_EPIConfigHB16Set
+#define MAP_EPIConfigHB16Set \
+        ROM_EPIConfigHB16Set
+#else
+#define MAP_EPIConfigHB16Set \
+        EPIConfigHB16Set
+#endif
+#ifdef ROM_EPIAddressMapSet
+#define MAP_EPIAddressMapSet \
+        ROM_EPIAddressMapSet
+#else
+#define MAP_EPIAddressMapSet \
+        EPIAddressMapSet
+#endif
+#ifdef ROM_EPINonBlockingReadConfigure
+#define MAP_EPINonBlockingReadConfigure \
+        ROM_EPINonBlockingReadConfigure
+#else
+#define MAP_EPINonBlockingReadConfigure \
+        EPINonBlockingReadConfigure
+#endif
+#ifdef ROM_EPINonBlockingReadStart
+#define MAP_EPINonBlockingReadStart \
+        ROM_EPINonBlockingReadStart
+#else
+#define MAP_EPINonBlockingReadStart \
+        EPINonBlockingReadStart
+#endif
+#ifdef ROM_EPINonBlockingReadStop
+#define MAP_EPINonBlockingReadStop \
+        ROM_EPINonBlockingReadStop
+#else
+#define MAP_EPINonBlockingReadStop \
+        EPINonBlockingReadStop
+#endif
+#ifdef ROM_EPINonBlockingReadCount
+#define MAP_EPINonBlockingReadCount \
+        ROM_EPINonBlockingReadCount
+#else
+#define MAP_EPINonBlockingReadCount \
+        EPINonBlockingReadCount
+#endif
+#ifdef ROM_EPINonBlockingReadAvail
+#define MAP_EPINonBlockingReadAvail \
+        ROM_EPINonBlockingReadAvail
+#else
+#define MAP_EPINonBlockingReadAvail \
+        EPINonBlockingReadAvail
+#endif
+#ifdef ROM_EPINonBlockingReadGet32
+#define MAP_EPINonBlockingReadGet32 \
+        ROM_EPINonBlockingReadGet32
+#else
+#define MAP_EPINonBlockingReadGet32 \
+        EPINonBlockingReadGet32
+#endif
+#ifdef ROM_EPINonBlockingReadGet16
+#define MAP_EPINonBlockingReadGet16 \
+        ROM_EPINonBlockingReadGet16
+#else
+#define MAP_EPINonBlockingReadGet16 \
+        EPINonBlockingReadGet16
+#endif
+#ifdef ROM_EPINonBlockingReadGet8
+#define MAP_EPINonBlockingReadGet8 \
+        ROM_EPINonBlockingReadGet8
+#else
+#define MAP_EPINonBlockingReadGet8 \
+        EPINonBlockingReadGet8
+#endif
+#ifdef ROM_EPIFIFOConfig
+#define MAP_EPIFIFOConfig \
+        ROM_EPIFIFOConfig
+#else
+#define MAP_EPIFIFOConfig \
+        EPIFIFOConfig
+#endif
+#ifdef ROM_EPIWriteFIFOCountGet
+#define MAP_EPIWriteFIFOCountGet \
+        ROM_EPIWriteFIFOCountGet
+#else
+#define MAP_EPIWriteFIFOCountGet \
+        EPIWriteFIFOCountGet
+#endif
+#ifdef ROM_EPIIntEnable
+#define MAP_EPIIntEnable \
+        ROM_EPIIntEnable
+#else
+#define MAP_EPIIntEnable \
+        EPIIntEnable
+#endif
+#ifdef ROM_EPIIntDisable
+#define MAP_EPIIntDisable \
+        ROM_EPIIntDisable
+#else
+#define MAP_EPIIntDisable \
+        EPIIntDisable
+#endif
+#ifdef ROM_EPIIntErrorStatus
+#define MAP_EPIIntErrorStatus \
+        ROM_EPIIntErrorStatus
+#else
+#define MAP_EPIIntErrorStatus \
+        EPIIntErrorStatus
+#endif
+#ifdef ROM_EPIIntErrorClear
+#define MAP_EPIIntErrorClear \
+        ROM_EPIIntErrorClear
+#else
+#define MAP_EPIIntErrorClear \
+        EPIIntErrorClear
+#endif
+
 //*****************************************************************************
 //
 // Macros for the Ethernet API.
@@ -541,12 +754,12 @@
 #define MAP_FlashIntDisable \
         FlashIntDisable
 #endif
-#ifdef ROM_FlashIntGetStatus
-#define MAP_FlashIntGetStatus \
-        ROM_FlashIntGetStatus
+#ifdef ROM_FlashIntStatus
+#define MAP_FlashIntStatus \
+        ROM_FlashIntStatus
 #else
-#define MAP_FlashIntGetStatus \
-        FlashIntGetStatus
+#define MAP_FlashIntStatus \
+        FlashIntStatus
 #endif
 #ifdef ROM_FlashIntClear
 #define MAP_FlashIntClear \
@@ -736,6 +949,34 @@
 #define MAP_GPIOPinTypeUSBDigital \
         GPIOPinTypeUSBDigital
 #endif
+#ifdef ROM_GPIOPinTypeI2S
+#define MAP_GPIOPinTypeI2S \
+        ROM_GPIOPinTypeI2S
+#else
+#define MAP_GPIOPinTypeI2S \
+        GPIOPinTypeI2S
+#endif
+#ifdef ROM_GPIOPinConfigure
+#define MAP_GPIOPinConfigure \
+        ROM_GPIOPinConfigure
+#else
+#define MAP_GPIOPinConfigure \
+        GPIOPinConfigure
+#endif
+#ifdef ROM_GPIOPinTypeEthernetLED
+#define MAP_GPIOPinTypeEthernetLED \
+        ROM_GPIOPinTypeEthernetLED
+#else
+#define MAP_GPIOPinTypeEthernetLED \
+        GPIOPinTypeEthernetLED
+#endif
+#ifdef ROM_GPIOPinTypeUSBAnalog
+#define MAP_GPIOPinTypeUSBAnalog \
+        ROM_GPIOPinTypeUSBAnalog
+#else
+#define MAP_GPIOPinTypeUSBAnalog \
+        GPIOPinTypeUSBAnalog
+#endif
 
 //*****************************************************************************
 //
@@ -1091,6 +1332,208 @@
 #define MAP_I2CSlaveDataGet \
         I2CSlaveDataGet
 #endif
+#ifdef ROM_I2CSlaveIntEnableEx
+#define MAP_I2CSlaveIntEnableEx \
+        ROM_I2CSlaveIntEnableEx
+#else
+#define MAP_I2CSlaveIntEnableEx \
+        I2CSlaveIntEnableEx
+#endif
+#ifdef ROM_I2CSlaveIntDisableEx
+#define MAP_I2CSlaveIntDisableEx \
+        ROM_I2CSlaveIntDisableEx
+#else
+#define MAP_I2CSlaveIntDisableEx \
+        I2CSlaveIntDisableEx
+#endif
+#ifdef ROM_I2CSlaveIntStatusEx
+#define MAP_I2CSlaveIntStatusEx \
+        ROM_I2CSlaveIntStatusEx
+#else
+#define MAP_I2CSlaveIntStatusEx \
+        I2CSlaveIntStatusEx
+#endif
+#ifdef ROM_I2CSlaveIntClearEx
+#define MAP_I2CSlaveIntClearEx \
+        ROM_I2CSlaveIntClearEx
+#else
+#define MAP_I2CSlaveIntClearEx \
+        I2CSlaveIntClearEx
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2S API.
+//
+//*****************************************************************************
+#ifdef ROM_I2SIntStatus
+#define MAP_I2SIntStatus \
+        ROM_I2SIntStatus
+#else
+#define MAP_I2SIntStatus \
+        I2SIntStatus
+#endif
+#ifdef ROM_I2STxEnable
+#define MAP_I2STxEnable \
+        ROM_I2STxEnable
+#else
+#define MAP_I2STxEnable \
+        I2STxEnable
+#endif
+#ifdef ROM_I2STxDisable
+#define MAP_I2STxDisable \
+        ROM_I2STxDisable
+#else
+#define MAP_I2STxDisable \
+        I2STxDisable
+#endif
+#ifdef ROM_I2STxDataPut
+#define MAP_I2STxDataPut \
+        ROM_I2STxDataPut
+#else
+#define MAP_I2STxDataPut \
+        I2STxDataPut
+#endif
+#ifdef ROM_I2STxDataPutNonBlocking
+#define MAP_I2STxDataPutNonBlocking \
+        ROM_I2STxDataPutNonBlocking
+#else
+#define MAP_I2STxDataPutNonBlocking \
+        I2STxDataPutNonBlocking
+#endif
+#ifdef ROM_I2STxConfigSet
+#define MAP_I2STxConfigSet \
+        ROM_I2STxConfigSet
+#else
+#define MAP_I2STxConfigSet \
+        I2STxConfigSet
+#endif
+#ifdef ROM_I2STxFIFOLimitSet
+#define MAP_I2STxFIFOLimitSet \
+        ROM_I2STxFIFOLimitSet
+#else
+#define MAP_I2STxFIFOLimitSet \
+        I2STxFIFOLimitSet
+#endif
+#ifdef ROM_I2STxFIFOLimitGet
+#define MAP_I2STxFIFOLimitGet \
+        ROM_I2STxFIFOLimitGet
+#else
+#define MAP_I2STxFIFOLimitGet \
+        I2STxFIFOLimitGet
+#endif
+#ifdef ROM_I2STxFIFOLevelGet
+#define MAP_I2STxFIFOLevelGet \
+        ROM_I2STxFIFOLevelGet
+#else
+#define MAP_I2STxFIFOLevelGet \
+        I2STxFIFOLevelGet
+#endif
+#ifdef ROM_I2SRxEnable
+#define MAP_I2SRxEnable \
+        ROM_I2SRxEnable
+#else
+#define MAP_I2SRxEnable \
+        I2SRxEnable
+#endif
+#ifdef ROM_I2SRxDisable
+#define MAP_I2SRxDisable \
+        ROM_I2SRxDisable
+#else
+#define MAP_I2SRxDisable \
+        I2SRxDisable
+#endif
+#ifdef ROM_I2SRxDataGet
+#define MAP_I2SRxDataGet \
+        ROM_I2SRxDataGet
+#else
+#define MAP_I2SRxDataGet \
+        I2SRxDataGet
+#endif
+#ifdef ROM_I2SRxDataGetNonBlocking
+#define MAP_I2SRxDataGetNonBlocking \
+        ROM_I2SRxDataGetNonBlocking
+#else
+#define MAP_I2SRxDataGetNonBlocking \
+        I2SRxDataGetNonBlocking
+#endif
+#ifdef ROM_I2SRxConfigSet
+#define MAP_I2SRxConfigSet \
+        ROM_I2SRxConfigSet
+#else
+#define MAP_I2SRxConfigSet \
+        I2SRxConfigSet
+#endif
+#ifdef ROM_I2SRxFIFOLimitSet
+#define MAP_I2SRxFIFOLimitSet \
+        ROM_I2SRxFIFOLimitSet
+#else
+#define MAP_I2SRxFIFOLimitSet \
+        I2SRxFIFOLimitSet
+#endif
+#ifdef ROM_I2SRxFIFOLimitGet
+#define MAP_I2SRxFIFOLimitGet \
+        ROM_I2SRxFIFOLimitGet
+#else
+#define MAP_I2SRxFIFOLimitGet \
+        I2SRxFIFOLimitGet
+#endif
+#ifdef ROM_I2SRxFIFOLevelGet
+#define MAP_I2SRxFIFOLevelGet \
+        ROM_I2SRxFIFOLevelGet
+#else
+#define MAP_I2SRxFIFOLevelGet \
+        I2SRxFIFOLevelGet
+#endif
+#ifdef ROM_I2STxRxEnable
+#define MAP_I2STxRxEnable \
+        ROM_I2STxRxEnable
+#else
+#define MAP_I2STxRxEnable \
+        I2STxRxEnable
+#endif
+#ifdef ROM_I2STxRxDisable
+#define MAP_I2STxRxDisable \
+        ROM_I2STxRxDisable
+#else
+#define MAP_I2STxRxDisable \
+        I2STxRxDisable
+#endif
+#ifdef ROM_I2STxRxConfigSet
+#define MAP_I2STxRxConfigSet \
+        ROM_I2STxRxConfigSet
+#else
+#define MAP_I2STxRxConfigSet \
+        I2STxRxConfigSet
+#endif
+#ifdef ROM_I2SMasterClockSelect
+#define MAP_I2SMasterClockSelect \
+        ROM_I2SMasterClockSelect
+#else
+#define MAP_I2SMasterClockSelect \
+        I2SMasterClockSelect
+#endif
+#ifdef ROM_I2SIntEnable
+#define MAP_I2SIntEnable \
+        ROM_I2SIntEnable
+#else
+#define MAP_I2SIntEnable \
+        I2SIntEnable
+#endif
+#ifdef ROM_I2SIntDisable
+#define MAP_I2SIntDisable \
+        ROM_I2SIntDisable
+#else
+#define MAP_I2SIntDisable \
+        I2SIntDisable
+#endif
+#ifdef ROM_I2SIntClear
+#define MAP_I2SIntClear \
+        ROM_I2SIntClear
+#else
+#define MAP_I2SIntClear \
+        I2SIntClear
+#endif
 
 //*****************************************************************************
 //
@@ -1153,6 +1596,20 @@
 #define MAP_IntPriorityGet \
         IntPriorityGet
 #endif
+#ifdef ROM_IntPendSet
+#define MAP_IntPendSet \
+        ROM_IntPendSet
+#else
+#define MAP_IntPendSet \
+        IntPendSet
+#endif
+#ifdef ROM_IntPendClear
+#define MAP_IntPendClear \
+        ROM_IntPendClear
+#else
+#define MAP_IntPendClear \
+        IntPendClear
+#endif
 
 //*****************************************************************************
 //
@@ -1625,6 +2082,13 @@
 #define MAP_SSIDMADisable \
         SSIDMADisable
 #endif
+#ifdef ROM_SSIBusy
+#define MAP_SSIBusy \
+        ROM_SSIBusy
+#else
+#define MAP_SSIBusy \
+        SSIBusy
+#endif
 
 //*****************************************************************************
 //
@@ -1862,6 +2326,20 @@
 #define MAP_SysCtlUSBPLLDisable \
         SysCtlUSBPLLDisable
 #endif
+#ifdef ROM_SysCtlI2SMClkSet
+#define MAP_SysCtlI2SMClkSet \
+        ROM_SysCtlI2SMClkSet
+#else
+#define MAP_SysCtlI2SMClkSet \
+        SysCtlI2SMClkSet
+#endif
+#ifdef ROM_SysCtlDelay
+#define MAP_SysCtlDelay \
+        ROM_SysCtlDelay
+#else
+#define MAP_SysCtlDelay \
+        SysCtlDelay
+#endif
 
 //*****************************************************************************
 //
@@ -2230,6 +2708,55 @@
 #define MAP_UARTDMADisable \
         UARTDMADisable
 #endif
+#ifdef ROM_UARTFIFOEnable
+#define MAP_UARTFIFOEnable \
+        ROM_UARTFIFOEnable
+#else
+#define MAP_UARTFIFOEnable \
+        UARTFIFOEnable
+#endif
+#ifdef ROM_UARTFIFODisable
+#define MAP_UARTFIFODisable \
+        ROM_UARTFIFODisable
+#else
+#define MAP_UARTFIFODisable \
+        UARTFIFODisable
+#endif
+#ifdef ROM_UARTBusy
+#define MAP_UARTBusy \
+        ROM_UARTBusy
+#else
+#define MAP_UARTBusy \
+        UARTBusy
+#endif
+#ifdef ROM_UARTTxIntModeSet
+#define MAP_UARTTxIntModeSet \
+        ROM_UARTTxIntModeSet
+#else
+#define MAP_UARTTxIntModeSet \
+        UARTTxIntModeSet
+#endif
+#ifdef ROM_UARTTxIntModeGet
+#define MAP_UARTTxIntModeGet \
+        ROM_UARTTxIntModeGet
+#else
+#define MAP_UARTTxIntModeGet \
+        UARTTxIntModeGet
+#endif
+#ifdef ROM_UARTRxErrorGet
+#define MAP_UARTRxErrorGet \
+        ROM_UARTRxErrorGet
+#else
+#define MAP_UARTRxErrorGet \
+        UARTRxErrorGet
+#endif
+#ifdef ROM_UARTRxErrorClear
+#define MAP_UARTRxErrorClear \
+        ROM_UARTRxErrorClear
+#else
+#define MAP_UARTRxErrorClear \
+        UARTRxErrorClear
+#endif
 
 //*****************************************************************************
 //
@@ -2355,6 +2882,20 @@
 #define MAP_uDMAChannelModeGet \
         uDMAChannelModeGet
 #endif
+#ifdef ROM_uDMAChannelSelectSecondary
+#define MAP_uDMAChannelSelectSecondary \
+        ROM_uDMAChannelSelectSecondary
+#else
+#define MAP_uDMAChannelSelectSecondary \
+        uDMAChannelSelectSecondary
+#endif
+#ifdef ROM_uDMAChannelSelectDefault
+#define MAP_uDMAChannelSelectDefault \
+        ROM_uDMAChannelSelectDefault
+#else
+#define MAP_uDMAChannelSelectDefault \
+        uDMAChannelSelectDefault
+#endif
 
 //*****************************************************************************
 //
@@ -2396,12 +2937,12 @@
 #define MAP_USBDevDisconnect \
         USBDevDisconnect
 #endif
-#ifdef ROM_USBDevEndpointConfig
-#define MAP_USBDevEndpointConfig \
-        ROM_USBDevEndpointConfig
+#ifdef ROM_USBDevEndpointConfigSet
+#define MAP_USBDevEndpointConfigSet \
+        ROM_USBDevEndpointConfigSet
 #else
-#define MAP_USBDevEndpointConfig \
-        USBDevEndpointConfig
+#define MAP_USBDevEndpointConfigSet \
+        USBDevEndpointConfigSet
 #endif
 #ifdef ROM_USBDevEndpointDataAck
 #define MAP_USBDevEndpointDataAck \
@@ -2571,12 +3112,12 @@
 #define MAP_USBHostPwrEnable \
         USBHostPwrEnable
 #endif
-#ifdef ROM_USBHostPwrFaultConfig
-#define MAP_USBHostPwrFaultConfig \
-        ROM_USBHostPwrFaultConfig
+#ifdef ROM_USBHostPwrConfig
+#define MAP_USBHostPwrConfig \
+        ROM_USBHostPwrConfig
 #else
-#define MAP_USBHostPwrFaultConfig \
-        USBHostPwrFaultConfig
+#define MAP_USBHostPwrConfig \
+        USBHostPwrConfig
 #endif
 #ifdef ROM_USBHostPwrFaultDisable
 #define MAP_USBHostPwrFaultDisable \
@@ -2648,6 +3189,104 @@
 #define MAP_USBIntEnable \
         USBIntEnable
 #endif
+#ifdef ROM_USBDevEndpointConfigGet
+#define MAP_USBDevEndpointConfigGet \
+        ROM_USBDevEndpointConfigGet
+#else
+#define MAP_USBDevEndpointConfigGet \
+        USBDevEndpointConfigGet
+#endif
+#ifdef ROM_USBEndpointDMAEnable
+#define MAP_USBEndpointDMAEnable \
+        ROM_USBEndpointDMAEnable
+#else
+#define MAP_USBEndpointDMAEnable \
+        USBEndpointDMAEnable
+#endif
+#ifdef ROM_USBEndpointDMADisable
+#define MAP_USBEndpointDMADisable \
+        ROM_USBEndpointDMADisable
+#else
+#define MAP_USBEndpointDMADisable \
+        USBEndpointDMADisable
+#endif
+#ifdef ROM_USBEndpointDataAvail
+#define MAP_USBEndpointDataAvail \
+        ROM_USBEndpointDataAvail
+#else
+#define MAP_USBEndpointDataAvail \
+        USBEndpointDataAvail
+#endif
+#ifdef ROM_USBOTGHostRequest
+#define MAP_USBOTGHostRequest \
+        ROM_USBOTGHostRequest
+#else
+#define MAP_USBOTGHostRequest \
+        USBOTGHostRequest
+#endif
+#ifdef ROM_USBModeGet
+#define MAP_USBModeGet \
+        ROM_USBModeGet
+#else
+#define MAP_USBModeGet \
+        USBModeGet
+#endif
+#ifdef ROM_USBEndpointDMAChannel
+#define MAP_USBEndpointDMAChannel \
+        ROM_USBEndpointDMAChannel
+#else
+#define MAP_USBEndpointDMAChannel \
+        USBEndpointDMAChannel
+#endif
+#ifdef ROM_USBIntDisableControl
+#define MAP_USBIntDisableControl \
+        ROM_USBIntDisableControl
+#else
+#define MAP_USBIntDisableControl \
+        USBIntDisableControl
+#endif
+#ifdef ROM_USBIntEnableControl
+#define MAP_USBIntEnableControl \
+        ROM_USBIntEnableControl
+#else
+#define MAP_USBIntEnableControl \
+        USBIntEnableControl
+#endif
+#ifdef ROM_USBIntStatusControl
+#define MAP_USBIntStatusControl \
+        ROM_USBIntStatusControl
+#else
+#define MAP_USBIntStatusControl \
+        USBIntStatusControl
+#endif
+#ifdef ROM_USBIntDisableEndpoint
+#define MAP_USBIntDisableEndpoint \
+        ROM_USBIntDisableEndpoint
+#else
+#define MAP_USBIntDisableEndpoint \
+        USBIntDisableEndpoint
+#endif
+#ifdef ROM_USBIntEnableEndpoint
+#define MAP_USBIntEnableEndpoint \
+        ROM_USBIntEnableEndpoint
+#else
+#define MAP_USBIntEnableEndpoint \
+        USBIntEnableEndpoint
+#endif
+#ifdef ROM_USBIntStatusEndpoint
+#define MAP_USBIntStatusEndpoint \
+        ROM_USBIntStatusEndpoint
+#else
+#define MAP_USBIntStatusEndpoint \
+        USBIntStatusEndpoint
+#endif
+#ifdef ROM_USBHostMode
+#define MAP_USBHostMode \
+        ROM_USBHostMode
+#else
+#define MAP_USBHostMode \
+        USBHostMode
+#endif
 
 //*****************************************************************************
 //
@@ -2760,4 +3399,18 @@
         WatchdogStallDisable
 #endif
 
+//*****************************************************************************
+//
+// Deprecated ROM functions.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define MAP_FlashIntGetStatus \
+        MAP_FlashIntStatus
+#define MAP_USBDevEndpointConfig \
+        MAP_USBDevEndpointConfigSet
+#define MAP_USBHostPwrFaultConfig \
+        MAP_USBHostPwrConfig
+#endif
+
 #endif // __ROM_MAP_H__

bsp/lm3s/Libraries/driverlib/ssi.c

@@ -2,26 +2,23 @@
 //
 // ssi.c - Driver for Synchronous Serial Interface.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -149,7 +146,7 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
     //
     // Set protocol and clock rate.
     //
-    ulSPH_SPO = ulProtocol << 6;
+    ulSPH_SPO = (ulProtocol & 3) << 6;
     ulProtocol &= SSI_CR0_FRF_M;
     ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
     HWREG(ulBase + SSI_O_CR0) = ulRegVal;
@@ -161,8 +158,8 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
 //!
 //! \param ulBase specifies the SSI module base address.
 //!
-//! This will enable operation of the synchronous serial interface.  It must be
-//! configured before it is enabled.
+//! This function enables operation of the synchronous serial interface.  The
+//! synchronous serial interface must be configured before it is enabled.
 //!
 //! \return None.
 //
@@ -187,7 +184,7 @@ SSIEnable(unsigned long ulBase)
 //!
 //! \param ulBase specifies the SSI module base address.
 //!
-//! This will disable operation of the synchronous serial interface.
+//! This function disables operation of the synchronous serial interface.
 //!
 //! \return None.
 //
@@ -356,12 +353,12 @@ SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
 //! Gets the current interrupt status.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param bMasked is \b false if the raw interrupt status is required and
+//! \param bMasked is \b false if the raw interrupt status is required or
 //! \b true if the masked interrupt status is required.
 //!
-//! This returns the interrupt status for the SSI module.  Either the raw
-//! interrupt status or the status of interrupts that are allowed to reflect to
-//! the processor can be returned.
+//! This function returns the interrupt status for the SSI module.  Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
 //!
 //! \return The current interrupt status, enumerated as a bit field of
 //! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
@@ -396,11 +393,11 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! \param ulBase specifies the SSI module base address.
 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
 //!
-//! The specified SSI interrupt sources are cleared, so that
-//! they no longer assert.  This must be done in the interrupt handler to
-//! keep it from being called again immediately upon exit.
-//! The \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO
-//! and \b SSI_RXOR values.
+//! The specified SSI interrupt sources are cleared so that they no longer
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupts from being recognized again immediately upon exit.  The
+//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
+//! \b SSI_RXOR values.
 //!
 //! \note Since there is a write buffer in the Cortex-M3 processor, it may take
 //! several clock cycles before the interrupt source is actually cleared.
@@ -433,15 +430,15 @@ SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
 //! Puts a data element into the SSI transmit FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param ulData data to be transmitted over the SSI interface.
+//! \param ulData is the data to be transmitted over the SSI interface.
 //!
-//! This function will place the supplied data into the transmit FIFO of
-//! the specified SSI module.
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.
 //!
-//! \note The upper 32 - N bits of the \e ulData will be discarded by the
-//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
-//! For example, if the interface is configured for 8-bit data width, the upper
-//! 24 bits of \e ulData will be discarded.
+//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk().  For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ulData are discarded.
 //!
 //! \return None.
 //
@@ -474,20 +471,20 @@ SSIDataPut(unsigned long ulBase, unsigned long ulData)
 //! Puts a data element into the SSI transmit FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param ulData data to be transmitted over the SSI interface.
+//! \param ulData is the data to be transmitted over the SSI interface.
 //!
-//! This function will place the supplied data into the transmit FIFO of
-//! the specified SSI module.  If there is no space in the FIFO, then this
-//! function will return a zero.
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.  If there is no space in the FIFO, then this function
+//! returns a zero.
 //!
 //! This function replaces the original SSIDataNonBlockingPut() API and
 //! performs the same actions.  A macro is provided in <tt>ssi.h</tt> to map
 //! the original API to this API.
 //!
-//! \note The upper 32 - N bits of the \e ulData will be discarded by the
-//! hardware, where N is the data width as configured by SSIConfigSetExpClk().
-//! For example, if the interface is configured for 8-bit data width, the upper
-//! 24 bits of \e ulData will be discarded.
+//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk().  For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ulData are discarded.
 //!
 //! \return Returns the number of elements written to the SSI transmit FIFO.
 //
@@ -521,18 +518,18 @@ SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
 //! Gets a data element from the SSI receive FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param pulData pointer to a storage location for data that was received
-//! over the SSI interface.
+//! \param pulData is a pointer to a storage location for data that was
+//! received over the SSI interface.
 //!
-//! This function will get received data from the receive FIFO of the specified
-//! SSI module, and place that data into the location specified by the
+//! This function gets received data from the receive FIFO of the specified
+//! SSI module and places that data into the location specified by the
 //! \e pulData parameter.
 //!
-//! \note Only the lower N bits of the value written to \e pulData will contain
+//! \note Only the lower N bits of the value written to \e pulData contain
 //! valid data, where N is the data width as configured by
 //! SSIConfigSetExpClk().  For example, if the interface is configured for
 //! 8-bit data width, only the lower 8 bits of the value written to \e pulData
-//! will contain valid data.
+//! contain valid data.
 //!
 //! \return None.
 //
@@ -563,23 +560,23 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData)
 //! Gets a data element from the SSI receive FIFO.
 //!
 //! \param ulBase specifies the SSI module base address.
-//! \param pulData pointer to a storage location for data that was received
-//! over the SSI interface.
+//! \param pulData is a pointer to a storage location for data that was
+//! received over the SSI interface.
 //!
-//! This function will get received data from the receive FIFO of
-//! the specified SSI module, and place that data into the location specified
-//! by the \e ulData parameter.  If there is no data in the FIFO, then this
-//! function will return a zero.
+//! This function gets received data from the receive FIFO of the specified SSI
+//! module and places that data into the location specified by the \e ulData
+//! parameter.  If there is no data in the FIFO, then this function  returns a
+//! zero.
 //!
 //! This function replaces the original SSIDataNonBlockingGet() API and
 //! performs the same actions.  A macro is provided in <tt>ssi.h</tt> to map
 //! the original API to this API.
 //!
-//! \note Only the lower N bits of the value written to \e pulData will contain
+//! \note Only the lower N bits of the value written to \e pulData contain
 //! valid data, where N is the data width as configured by
 //! SSIConfigSetExpClk().  For example, if the interface is configured for
 //! 8-bit data width, only the lower 8 bits of the value written to \e pulData
-//! will contain valid data.
+//! contain valid data.
 //!
 //! \return Returns the number of elements read from the SSI receive FIFO.
 //
@@ -672,6 +669,35 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
     HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
 }
 
+//*****************************************************************************
+//
+//! Determines whether the SSI transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the SSI port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware.  If \b false is returned, then the transmit FIFO
+//! is empty and all bits of the last transmitted word have left the hardware
+//! shift register.
+//!
+//! \return Returns \b true if the SSI is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+SSIBusy(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+    //
+    // Determine if the SSI is busy.
+    //
+    return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
+}
+
 //*****************************************************************************
 //
 // Close the Doxygen group.

bsp/lm3s/Libraries/driverlib/ssi.h

@@ -2,26 +2,23 @@
 //
 // ssi.h - Prototypes for the Synchronous Serial Interface Driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -45,8 +42,8 @@ extern "C"
 // as the ulIntFlags parameter, and returned by SSIIntStatus.
 //
 //*****************************************************************************
-#define SSI_TXFF                0x00000008  // TX FIFO half empty or less
-#define SSI_RXFF                0x00000004  // RX FIFO half full or less
+#define SSI_TXFF                0x00000008  // TX FIFO half full or less
+#define SSI_RXFF                0x00000004  // RX FIFO half full or more
 #define SSI_RXTO                0x00000002  // RX timeout
 #define SSI_RXOR                0x00000001  // RX overrun
 
@@ -98,6 +95,7 @@ extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
 extern void SSIIntUnregister(unsigned long ulBase);
 extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
 extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern tBoolean SSIBusy(unsigned long ulBase);
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/sysctl.c

@@ -2,26 +2,23 @@
 //
 // sysctl.c - Driver for the system controller.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -347,19 +344,21 @@ SysCtlPinPresent(unsigned long ulPin)
 //! determine which are present on this device.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_IEEE1588, \b SYSCTL_PERIPH_MPU,
-//! \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TEMP, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
-//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0,
-//! \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA,
-//! \b SYSCTL_PERIPH_USB0, or \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_IEEE1588,
+//! \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return Returns \b true if the specified peripheral is present and \b false
 //! if it is not.
@@ -376,8 +375,22 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral)
     //
     // Read the correct DC register and determine if this peripheral exists.
     //
-    if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
-       SYSCTL_PERIPH_MASK(ulPeripheral))
+    if(ulPeripheral == SYSCTL_PERIPH_USB0)
+    {
+        //
+        // USB is a special case since the DC bit is missing for USB0.
+        //
+        if(HWREG(SYSCTL_DC6) & SYSCTL_DC6_USB0_M)
+        {
+            return(true);
+        }
+        else
+        {
+            return(false);
+        }
+    }
+    else if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
+            SYSCTL_PERIPH_MASK(ulPeripheral))
     {
         return(true);
     }
@@ -395,22 +408,24 @@ SysCtlPeripheralPresent(unsigned long ulPeripheral)
 //!
 //! This function performs a software reset of the specified peripheral.  An
 //! individual peripheral reset signal is asserted for a brief period and then
-//! deasserted, leaving the peripheral in a operating state but in its reset
+//! deasserted, returning the internal state of the peripheral to its reset
 //! condition.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -456,18 +471,20 @@ SysCtlPeripheralReset(unsigned long ulPeripheral)
 //! register reads/writes.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \note It takes five clock cycles after the write to enable a peripheral
 //! before the the peripheral is actually enabled.  During this time, attempts
@@ -503,18 +520,20 @@ SysCtlPeripheralEnable(unsigned long ulPeripheral)
 //! operate or respond to register reads/writes.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -551,18 +570,20 @@ SysCtlPeripheralDisable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when sleep mode is entered.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -600,18 +621,20 @@ SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when sleep mode is entered.
 //!
 //! The \e ulPeripheral parameter must be only one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -649,19 +672,21 @@ SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when deep-sleep mode is
 //! entered.
 //!
-//! The \e ulPeripheral parameter must be one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -701,19 +726,21 @@ SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
 //! configuration is maintained but has no effect when deep-sleep mode is
 //! entered.
 //!
-//! The \e ulPeripheral parameter must be one of the following values:
-//! \b SYSCTL_PERIPH_ADC, \b SYSCTL_PERIPH_CAN0, \b SYSCTL_PERIPH_CAN1,
-//! \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0, \b SYSCTL_PERIPH_COMP1,
-//! \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA,
-//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
-//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
-//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
-//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_PWM, \b SYSCTL_PERIPH_QEI0,
-//! \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0, \b SYSCTL_PERIPH_SSI1,
-//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
-//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1,
-//! \b SYSCTL_PERIPH_UART2, \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, or
-//! \b SYSCTL_PERIPH_WDOG.
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
 //!
 //! \return None.
 //
@@ -1256,6 +1283,21 @@ SysCtlDelay(unsigned long ulCount)
     bx      lr;
 }
 #endif
+#if defined(ccs)
+volatile unsigned long g_ulInlineCCSWorkaround;
+void
+SysCtlDelay(unsigned long ulCount)
+{
+    __asm("delay?: subs    r0, #1\n"
+          "    bne.n   delay?\n"
+          "    bx lr\n");
+
+    //
+    // This is needed to keep TI compiler from optimizing away this code.
+    //
+    g_ulInlineCCSWorkaround += ulCount;
+}
+#endif
 
 //*****************************************************************************
 //
@@ -1455,15 +1497,15 @@ SysCtlClockSet(unsigned long ulConfig)
                          SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
     ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
     ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
-    if(ulConfig & SYSCTL_RCC2_USEFRACT)
+    if(ulConfig & SYSCTL_RCC2_DIV400)
     {
         ulRCC |= SYSCTL_RCC_USESYSDIV;
         ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV);
-        ulRCC2 |= ulConfig & (SYSCTL_RCC2_USEFRACT | SYSCTL_RCC2_FRACT);
+        ulRCC2 |= ulConfig & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB);
     }
     else
     {
-        ulRCC2 &= ~(SYSCTL_RCC2_USEFRACT);
+        ulRCC2 &= ~(SYSCTL_RCC2_DIV400);
     }
 
     //
@@ -1713,6 +1755,12 @@ SysCtlClockGet(void)
         {
             ulClk /= 4;
         }
+
+        //
+        // Force the system divider to be enabled.  It is always used when
+        // using the PLL, but in some cases it will not read as being enabled.
+        //
+        ulRCC |= SYSCTL_RCC_USESYSDIV;
     }
 
     //
@@ -1725,7 +1773,7 @@ SysCtlClockGet(void)
         //
         if(ulRCC2 & SYSCTL_RCC2_USERCC2)
         {
-            if((ulRCC2 & SYSCTL_RCC2_USEFRACT) &&
+            if((ulRCC2 & SYSCTL_RCC2_DIV400) &&
                (((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
                  !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
                 (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
@@ -1733,7 +1781,7 @@ SysCtlClockGet(void)
 
             {
                 ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M |
-                                                    SYSCTL_RCC2_FRACT)) >>
+                                                    SYSCTL_RCC2_SYSDIV2LSB)) >>
                                          (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1));
             }
             else
@@ -1882,8 +1930,6 @@ SysCtlADCSpeedSet(unsigned long ulSpeed)
                            ulSpeed);
     HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
                            ulSpeed);
-    HWREG(SYSCTL_DCGC0) = ((HWREG(SYSCTL_DCGC0) & ~(SYSCTL_DCGC0_ADCSPD_M)) |
-                           ulSpeed);
 }
 
 //*****************************************************************************

bsp/lm3s/Libraries/driverlib/sysctl.h

@@ -2,26 +2,23 @@
 //
 // sysctl.h - Prototypes for the system control driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -234,9 +231,9 @@ extern "C"
 // API.
 //
 //*****************************************************************************
-#define SYSCTL_ADCSPEED_1MSPS   0x00000300  // 1,000,000 samples per second
-#define SYSCTL_ADCSPEED_500KSPS 0x00000200  // 500,000 samples per second
-#define SYSCTL_ADCSPEED_250KSPS 0x00000100  // 250,000 samples per second
+#define SYSCTL_ADCSPEED_1MSPS   0x00000F00  // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000A00  // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000500  // 250,000 samples per second
 #define SYSCTL_ADCSPEED_125KSPS 0x00000000  // 125,000 samples per second
 
 //*****************************************************************************

bsp/lm3s/Libraries/driverlib/systick.c

@@ -2,26 +2,23 @@
 //
 // systick.c - Driver for the SysTick timer in NVIC.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/systick.h

@@ -2,26 +2,23 @@
 //
 // systick.h - Prototypes for the SysTick driver.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/timer.c

@@ -2,26 +2,23 @@
 //
 // timer.c - Driver for the timer module.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -134,8 +131,12 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer)
 //! state.  The configuration is specified in \e ulConfig as one of the
 //! following values:
 //!
-//! - \b TIMER_CFG_32_BIT_OS - 32-bit one shot timer
+//! - \b TIMER_CFG_32_BIT_OS - 32-bit one-shot timer
+//! - \b TIMER_CFG_32_BIT_OS_UP - 32-bit one-shot timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
+//! - \b TIMER_CFG_32_BIT_PER_UP - 32-bit periodic timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
 //! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
 //!
@@ -144,8 +145,12 @@ TimerDisable(unsigned long ulBase, unsigned long ulTimer)
 //! the result of a logical OR operation between one of the following values
 //! and \e ulConfig:
 //!
-//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one-shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT_UP - 16-bit one-shot timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
+//! - \b TIMER_CFG_A_PERIODIC_UP - 16-bit periodic timer that counts up instead
+//!   of down (not available on all parts)
 //! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
 //! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
 //! - \b TIMER_CFG_A_PWM - 16-bit PWM output
@@ -165,17 +170,23 @@ TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
     //
     ASSERT(TimerBaseValid(ulBase));
     ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
+           (ulConfig == TIMER_CFG_32_BIT_OS_UP) ||
            (ulConfig == TIMER_CFG_32_BIT_PER) ||
+           (ulConfig == TIMER_CFG_32_BIT_PER_UP) ||
            (ulConfig == TIMER_CFG_32_RTC) ||
            ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
     ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
            ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+             ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+             ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
              ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
             (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+             ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
              ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
@@ -344,6 +355,67 @@ TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
                                    (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
 }
 
+//*****************************************************************************
+//
+//! Controls the wait on trigger handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bWait specifies if the timer should wait for a trigger input.
+//!
+//! This function controls whether or not a timer waits for a trigger input to
+//! start counting.  When enabled, the previous timer in the trigger chain must
+//! count to its timeout in order for this timer to start counting.  Refer to
+//! the part's data sheet for a description of the trigger chain.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer,
+                          tBoolean bWait)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(TimerBaseValid(ulBase));
+    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+           (ulTimer == TIMER_BOTH));
+
+    //
+    // Set the wait on trigger mode for timer A.
+    //
+    if((ulTimer & TIMER_A) != 0)
+    {
+        if(bWait)
+        {
+            HWREG(ulBase + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
+        }
+        else
+        {
+            HWREG(ulBase + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
+        }
+    }
+
+    //
+    // Set the wait on trigger mode for timer A.
+    //
+    if((ulTimer & TIMER_B) != 0)
+    {
+        if(bWait)
+        {
+            HWREG(ulBase + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
+        }
+        else
+        {
+            HWREG(ulBase + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
+        }
+    }
+}
+
 //*****************************************************************************
 //
 //! Enable RTC counting.
@@ -473,6 +545,88 @@ TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
            HWREG(ulBase + TIMER_O_TBPR));
 }
 
+//*****************************************************************************
+//
+//! Set the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale match value; must be between 0 and
+//! 255, inclusive.
+//!
+//! This function sets the value of the input clock prescaler match value.
+//! When in a 16-bit mode that uses the counter match and the prescaler, the
+//! prescale match effectively extends the range of the counter to 24-bits.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                      unsigned long ulValue)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(TimerBaseValid(ulBase));
+    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+           (ulTimer == TIMER_BOTH));
+    ASSERT(ulValue < 256);
+
+    //
+    // Set the timer A prescale match if requested.
+    //
+    if(ulTimer & TIMER_A)
+    {
+        HWREG(ulBase + TIMER_O_TAPMR) = ulValue;
+    }
+
+    //
+    // Set the timer B prescale match if requested.
+    //
+    if(ulTimer & TIMER_B)
+    {
+        HWREG(ulBase + TIMER_O_TBPMR) = ulValue;
+    }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a 16-bit mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the counter to 24-bits.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return The value of the timer prescale match.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(TimerBaseValid(ulBase));
+    ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+           (ulTimer == TIMER_BOTH));
+
+    //
+    // Return the appropriate prescale match value.
+    //
+    return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :
+           HWREG(ulBase + TIMER_O_TBPMR));
+}
+
 //*****************************************************************************
 //
 //! Sets the timer load value.

bsp/lm3s/Libraries/driverlib/timer.h

@@ -2,26 +2,23 @@
 //
 // timer.h - Prototypes for the timer module
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -45,16 +42,22 @@ extern "C"
 //
 //*****************************************************************************
 #define TIMER_CFG_32_BIT_OS     0x00000001  // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_OS_UP  0x00000011  // 32-bit one-shot up-count timer
 #define TIMER_CFG_32_BIT_PER    0x00000002  // 32-bit periodic timer
+#define TIMER_CFG_32_BIT_PER_UP 0x00000012  // 32-bit periodic up-count timer
 #define TIMER_CFG_32_RTC        0x01000000  // 32-bit RTC timer
 #define TIMER_CFG_16_BIT_PAIR   0x04000000  // Two 16-bit timers
 #define TIMER_CFG_A_ONE_SHOT    0x00000001  // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP 0x00000011  // Timer A one-shot up-count timer
 #define TIMER_CFG_A_PERIODIC    0x00000002  // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP 0x00000012  // Timer A periodic up-count timer
 #define TIMER_CFG_A_CAP_COUNT   0x00000003  // Timer A event counter
 #define TIMER_CFG_A_CAP_TIME    0x00000007  // Timer A event timer
 #define TIMER_CFG_A_PWM         0x0000000A  // Timer A PWM output
 #define TIMER_CFG_B_ONE_SHOT    0x00000100  // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP 0x00001100  // Timer B one-shot up-count timer
 #define TIMER_CFG_B_PERIODIC    0x00000200  // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP 0x00001200  // Timer B periodic up-count timer
 #define TIMER_CFG_B_CAP_COUNT   0x00000300  // Timer B event counter
 #define TIMER_CFG_B_CAP_TIME    0x00000700  // Timer B event timer
 #define TIMER_CFG_B_PWM         0x00000A00  // Timer B PWM output
@@ -65,9 +68,11 @@ extern "C"
 // TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
 //
 //*****************************************************************************
+#define TIMER_TIMB_MATCH        0x00000800  // TimerB match interrupt
 #define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt
 #define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt
 #define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt
+#define TIMER_TIMA_MATCH        0x00000010  // TimerA match interrupt
 #define TIMER_RTC_MATCH         0x00000008  // RTC interrupt mask
 #define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt
 #define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt
@@ -108,12 +113,19 @@ extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
                               unsigned long ulEvent);
 extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
                               tBoolean bStall);
+extern void TimerControlWaitOnTrigger(unsigned long ulBase,
+                                      unsigned long ulTimer,
+                                      tBoolean bWait);
 extern void TimerRTCEnable(unsigned long ulBase);
 extern void TimerRTCDisable(unsigned long ulBase);
 extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
                              unsigned long ulValue);
 extern unsigned long TimerPrescaleGet(unsigned long ulBase,
                                       unsigned long ulTimer);
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+                                  unsigned long ulValue);
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
+                                           unsigned long ulTimer);
 extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
                          unsigned long ulValue);
 extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);

bsp/lm3s/Libraries/driverlib/uart.c

@@ -2,26 +2,23 @@
 //
 // uart.c - Driver for the UART.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -85,7 +82,7 @@ UARTBaseValid(unsigned long ulBase)
 //! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
 //! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
 //! or \b UART_CONFIG_PAR_ZERO.  The last two allow direct control of the
-//! parity bit; it will always be either be one or zero based on the mode.
+//! parity bit; it is always either one or zero based on the mode.
 //!
 //! \return None.
 //
@@ -117,7 +114,7 @@ UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
 //!
 //! \param ulBase is the base address of the UART port.
 //!
-//! This function gets the type of parity used for transmitting data, and
+//! This function gets the type of parity used for transmitting data and
 //! expected when receiving data.
 //!
 //! \return Returns the current parity settings, specified as one of
@@ -153,7 +150,7 @@ UARTParityModeGet(unsigned long ulBase)
 //! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
 //!
 //! This function sets the FIFO level at which transmit and receive interrupts
-//! will be generated.
+//! are generated.
 //!
 //! \return None.
 //
@@ -190,13 +187,13 @@ UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
 //! \param ulBase is the base address of the UART port.
 //! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
 //! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
-//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or UART_FIFO_TX7_8.
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
 //! \param pulRxLevel is a pointer to storage for the receive FIFO level,
 //! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
 //! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
 //!
 //! This function gets the FIFO level at which transmit and receive interrupts
-//! will be generated.
+//! are xogenerated.
 //!
 //! \return None.
 //
@@ -234,7 +231,7 @@ UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
 //! \param ulConfig is the data format for the port (number of data bits,
 //! number of stop bits, and parity).
 //!
-//! This function will configure the UART for operation in the specified data
+//! This function configures the UART for operation in the specified data
 //! format.  The baud rate is provided in the \e ulBaud parameter and the data
 //! format in the \e ulConfig parameter.
 //!
@@ -970,7 +967,7 @@ UARTTxIntModeGet(unsigned long ulBase)
 //! This function returns a flag indicating whether or not there is data
 //! available in the receive FIFO.
 //!
-//! \return Returns \b true if there is data in the receive FIFO, and \b false
+//! \return Returns \b true if there is data in the receive FIFO or \b false
 //! if there is no data in the receive FIFO.
 //
 //*****************************************************************************
@@ -997,8 +994,8 @@ UARTCharsAvail(unsigned long ulBase)
 //! This function returns a flag indicating whether or not there is space
 //! available in the transmit FIFO.
 //!
-//! \return Returns \b true if there is space available in the transmit FIFO,
-//! and \b false if there is no space available in the transmit FIFO.
+//! \return Returns \b true if there is space available in the transmit FIFO
+//! or \b false if there is no space available in the transmit FIFO.
 //
 //*****************************************************************************
 tBoolean
@@ -1028,8 +1025,8 @@ UARTSpaceAvail(unsigned long ulBase)
 //! the original API to this API.
 //!
 //! \return Returns the character read from the specified port, cast as a
-//! \e long.  A \b -1 will be returned if there are no characters present in
-//! the receive FIFO.  The UARTCharsAvail() function should be called before
+//! \e long.  A \b -1 is returned if there are no characters present in the
+//! receive FIFO.  The UARTCharsAvail() function should be called before
 //! attempting to call this function.
 //
 //*****************************************************************************
@@ -1067,10 +1064,10 @@ UARTCharGetNonBlocking(unsigned long ulBase)
 //! \param ulBase is the base address of the UART port.
 //!
 //! Gets a character from the receive FIFO for the specified port.  If there
-//! are no characters available, this function will wait until a character is
+//! are no characters available, this function waits until a character is
 //! received before returning.
 //!
-//! \return Returns the character read from the specified port, cast as an
+//! \return Returns the character read from the specified port, cast as a
 //! \e long.
 //
 //*****************************************************************************
@@ -1104,15 +1101,14 @@ UARTCharGet(unsigned long ulBase)
 //!
 //! Writes the character \e ucData to the transmit FIFO for the specified port.
 //! This function does not block, so if there is no space available, then a
-//! \b false is returned, and the application will have to retry the function
-//! later.
+//! \b false is returned, and the application must retry the function later.
 //!
 //! This function replaces the original UARTCharNonBlockingPut() API and
 //! performs the same actions.  A macro is provided in <tt>uart.h</tt> to map
 //! the original API to this API.
 //!
 //! \return Returns \b true if the character was successfully placed in the
-//! transmit FIFO, and \b false if there was no space available in the transmit
+//! transmit FIFO or \b false if there was no space available in the transmit
 //! FIFO.
 //
 //*****************************************************************************
@@ -1156,8 +1152,8 @@ UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
 //! \param ucData is the character to be transmitted.
 //!
 //! Sends the character \e ucData to the transmit FIFO for the specified port.
-//! If there is no space available in the transmit FIFO, this function will
-//! wait until there is space available before returning.
+//! If there is no space available in the transmit FIFO, this function waits
+//! until there is space available before returning.
 //!
 //! \return None.
 //
@@ -1190,10 +1186,10 @@ UARTCharPut(unsigned long ulBase, unsigned char ucData)
 //! \param ulBase is the base address of the UART port.
 //! \param bBreakState controls the output level.
 //!
-//! Calling this function with \e bBreakState set to \b true will assert a
-//! break condition on the UART.  Calling this function with \e bBreakState set
-//! to \b false will remove the break condition.  For proper transmission of a
-//! break command, the break must be asserted for at least two complete frames.
+//! Calling this function with \e bBreakState set to \b true asserts a break
+//! condition on the UART.  Calling this function with \e bBreakState set to
+//! \b false removes the break condition.  For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
 //!
 //! \return None.
 //
@@ -1412,8 +1408,8 @@ UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
 //! Gets the current interrupt status.
 //!
 //! \param ulBase is the base address of the UART port.
-//! \param bMasked is false if the raw interrupt status is required and true
-//! if the masked interrupt status is required.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
 //!
 //! This returns the interrupt status for the specified UART.  Either the raw
 //! interrupt status or the status of interrupts that are allowed to reflect to
@@ -1453,8 +1449,8 @@ UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
 //! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
 //!
 //! The specified UART interrupt sources are cleared, so that they no longer
-//! assert.  This must be done in the interrupt handler to keep it from being
-//! called again immediately upon exit.
+//! assert.  This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
 //!
 //! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
 //! parameter to UARTIntEnable().

bsp/lm3s/Libraries/driverlib/uart.h

@@ -2,26 +2,23 @@
 //
 // uart.h - Defines and Macros for the UART.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/udma.c

@@ -2,26 +2,23 @@
 //
 // udma.c - Driver for the micro-DMA controller.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -932,14 +929,32 @@ uDMAChannelSizeGet(unsigned long ulChannel)
     pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
 
     //
-    // Get the current control word value and mask off all but the size field.
+    // Get the current control word value and mask off all but the size field
+    // and the mode field.
+    //
+    ulControl = pControlTable[ulChannel].ulControl &
+                (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M);
+
+    //
+    // If the size field and mode field are 0 then the transfer is finished
+    // and there are no more items to transfer
     //
-    ulControl = pControlTable[ulChannel].ulControl & UDMA_CHCTL_XFERSIZE_M;
+    if(ulControl == 0)
+    {
+        return(0);
+    }
 
     //
-    // Shift the size field and add one, then return to user.
+    // Otherwise, if either the size field or more field is non-zero, then
+    // not all the items have been transferred.
     //
-    return((ulControl >> 4) + 1);
+    else
+    {
+        //
+        // Shift the size field and add one, then return to user.
+        //
+        return((ulControl >> 4) + 1);
+    }
 }
 
 //*****************************************************************************
@@ -1003,7 +1018,7 @@ uDMAChannelModeGet(unsigned long ulChannel)
 
 //*****************************************************************************
 //
-//! Select the secondary peripheral for a set of uDMA channels.
+//! Selects the secondary peripheral for a set of uDMA channels.
 //!
 //! \param ulSecPeriphs is the logical or of the uDMA channels for which to
 //! use the secondary peripheral, instead of the default peripheral.
@@ -1038,8 +1053,8 @@ uDMAChannelModeGet(unsigned long ulChannel)
 //! - \b UDMA_DEF_ADC03_SEC_RESERVED
 //! - \b UDMA_DEF_TMR0A_SEC_TMR1A
 //! - \b UDMA_DEF_TMR0B_SEC_TMR1B
-//! - \b UDMA_DEF_TMR1A_SEC_GPIORX
-//! - \b UDMA_DEF_TMR1B_SEC_GPIOTX
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
 //! - \b UDMA_DEF_UART1RX_SEC_RESERVED
 //! - \b UDMA_DEF_UART1TX_SEC_RESERVED
 //! - \b UDMA_DEF_SSI1RX_SEC_ADC10
@@ -1063,7 +1078,7 @@ uDMAChannelSelectSecondary(unsigned long ulSecPeriphs)
 
 //*****************************************************************************
 //
-//! Select the default peripheral for a set of uDMA channels.
+//! Selects the default peripheral for a set of uDMA channels.
 //!
 //! \param ulDefPeriphs is the logical or of the uDMA channels for which to
 //! use the default peripheral, instead of the secondary peripheral.
@@ -1096,8 +1111,8 @@ uDMAChannelSelectSecondary(unsigned long ulSecPeriphs)
 //! - \b UDMA_DEF_ADC03_SEC_RESERVED
 //! - \b UDMA_DEF_TMR0A_SEC_TMR1A
 //! - \b UDMA_DEF_TMR0B_SEC_TMR1B
-//! - \b UDMA_DEF_TMR1A_SEC_GPIORX
-//! - \b UDMA_DEF_TMR1B_SEC_GPIOTX
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
 //! - \b UDMA_DEF_UART1RX_SEC_RESERVED
 //! - \b UDMA_DEF_UART1TX_SEC_RESERVED
 //! - \b UDMA_DEF_SSI1RX_SEC_ADC10
@@ -1119,47 +1134,6 @@ uDMAChannelSelectDefault(unsigned long ulDefPeriphs)
     HWREG(UDMA_CHALT) &= ~ulDefPeriphs;
 }
 
-//*****************************************************************************
-//
-//! Gets the uDMA controller channel interrupt status.
-//!
-//! This function is used to get the interrupt status of the uDMA controller.
-//! The returned value is a 32-bit bit mask that indicates which channels are
-//! requesting an interrupt.  This function can be used from within an
-//! interrupt handler to determine or confirm which uDMA channel has requested
-//! an interrupt.
-//!
-//! \return Returns a 32-bit mask which indicates requesting uDMA channels.
-//! There is a bit for each channel, and a 1 in a bit indicates that channel
-//! is requesting an interrupt.  Multiple bits can be set.
-//
-//*****************************************************************************
-unsigned long
-uDMAIntStatus(void)
-{
-    return(HWREG(UDMA_CHIS));
-}
-
-//*****************************************************************************
-//
-//! Clears uDMA interrupt status.
-//!
-//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel.
-//!
-//! Clears bits in the uDMA interrupt status register according to which bits
-//! are set in \e ulChanMask.  There is one bit for each channel.  If a a bit
-//! is set in \e ulChanMask, then that corresponding channel's interrupt
-//! status will be cleared (if it was set).
-//!
-//! \return None.
-//
-//*****************************************************************************
-void
-uDMAIntClear(unsigned long ulChanMask)
-{
-    HWREG(UDMA_CHIS) = ulChanMask;
-}
-
 //*****************************************************************************
 //
 //! Registers an interrupt handler for the uDMA controller.

bsp/lm3s/Libraries/driverlib/udma.h

@@ -2,26 +2,23 @@
 //
 // udma.h - Prototypes and macros for the uDMA controller.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -323,8 +320,6 @@ extern void uDMAIntRegister(unsigned long ulIntChannel,
 extern void uDMAIntUnregister(unsigned long ulIntChannel);
 extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
 extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
-extern unsigned long uDMAIntStatus(void);
-extern void uDMAIntClear(unsigned long ulChanMask);
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/usb.c

@@ -2,26 +2,23 @@
 //
 // usb.c - Driver for the USB Interface.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -47,7 +44,10 @@
 // interrupt calls.
 //
 //*****************************************************************************
+#ifndef DEPRECATED
 #define USB_INT_RX_SHIFT        8
+#endif
+#define USB_INTEP_RX_SHIFT      16
 
 //*****************************************************************************
 //
@@ -55,7 +55,9 @@
 // interrupt calls.
 //
 //*****************************************************************************
+#ifndef DEPRECATED
 #define USB_INT_STATUS_SHIFT    24
+#endif
 
 //*****************************************************************************
 //
@@ -146,7 +148,7 @@ USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint,
 // \param ulEndpoint is the endpoint index to target for this write.
 // \param ulIndexedReg is the indexed register to write to.
 //
-// This function is used interally to access the indexed registers for each
+// This function is used internally to access the indexed registers for each
 // endpoint.  The only registers that are indexed are the FIFO configuration
 // registers which are not used after configuration.
 //
@@ -379,10 +381,15 @@ USBHostSpeedGet(unsigned long ulBase)
 //! \note This call will clear the source of all of the general status
 //! interrupts.
 //!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntStatusControl() or USBIntStatusEndpoint() should be
+//! used instead.
+//!
 //! \return Returns the status of the sources for the USB controller's
 //! interrupt.
 //
 //*****************************************************************************
+#ifndef DEPRECATED
 unsigned long
 USBIntStatus(unsigned long ulBase)
 {
@@ -396,13 +403,13 @@ USBIntStatus(unsigned long ulBase)
     //
     // Get the transmit interrupt status.
     //
-    ulStatus = (HWREGH(ulBase + USB_O_TXIS));
+    ulStatus = (HWREGB(ulBase + USB_O_TXIS));
 
     //
     // Get the receive interrupt status, these bits go into the second byte of
     // the returned value.
     //
-    ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT);
+    ulStatus |= (HWREGB(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT);
 
     //
     // Get the general interrupt status, these bits go into the upper 8 bits
@@ -444,6 +451,7 @@ USBIntStatus(unsigned long ulBase)
     //
     return(ulStatus);
 }
+#endif
 
 //*****************************************************************************
 //
@@ -459,9 +467,14 @@ USBIntStatus(unsigned long ulBase)
 //! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS.  If
 //! \b USB_INT_ALL is specified then all interrupts will be disabled.
 //!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntDisableControl() or USBIntDisableEndpoint() should be
+//! used instead.
+//!
 //! \return None.
 //
 //*****************************************************************************
+#ifndef DEPRECATED
 void
 USBIntDisable(unsigned long ulBase, unsigned long ulFlags)
 {
@@ -518,6 +531,7 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags)
         HWREG(USB0_BASE + USB_O_IDVIM) = 0;
     }
 }
+#endif
 
 //*****************************************************************************
 //
@@ -540,9 +554,14 @@ USBIntDisable(unsigned long ulBase, unsigned long ulFlags)
 //! are used then then a call to IntEnable() must be made in order to allow any
 //! USB interrupts to occur.
 //!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntEnableControl() or USBIntEnableEndpoint() should be
+//! used instead.
+//!
 //! \return None.
 //
 //*****************************************************************************
+#ifndef DEPRECATED
 void
 USBIntEnable(unsigned long ulBase, unsigned long ulFlags)
 {
@@ -599,6 +618,322 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags)
         HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
     }
 }
+#endif
+
+//*****************************************************************************
+//
+//! Disable control interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which control interrupts to disable.
+//!
+//! This function will disable the control interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which control interrupts to disable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTCTRL_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableControl(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & ~(USB_INTCTRL_ALL)) == 0);
+
+    //
+    // If any general interrupts were disabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & USB_INTCTRL_STATUS)
+    {
+        HWREGB(ulBase + USB_O_IE) &= ~(ulFlags & USB_INTCTRL_STATUS);
+    }
+
+    //
+    // Disable the power fault interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_POWER_FAULT)
+    {
+        HWREG(ulBase + USB_O_EPCIM) = 0;
+    }
+
+    //
+    // Disable the ID pin detect interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+    }
+}
+
+//*****************************************************************************
+//
+//! Enable control interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which control interrupts to enable.
+//!
+//! This function will enable the control interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which control interrupts to enable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTCTRL_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+    ASSERT((ulFlags & (~USB_INTCTRL_ALL)) == 0);
+
+    //
+    // If any general interrupts were enabled then write the general interrupt
+    // settings out to the hardware.
+    //
+    if(ulFlags & USB_INTCTRL_STATUS)
+    {
+        HWREGB(ulBase + USB_O_IE) |= ulFlags;
+    }
+
+    //
+    // Enable the power fault interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_POWER_FAULT)
+    {
+        HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF;
+    }
+
+    //
+    // Enable the ID pin detect interrupt.
+    //
+    if(ulFlags & USB_INTCTRL_MODE_DETECT)
+    {
+        HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+    }
+}
+
+//*****************************************************************************
+//
+//! Returns the control interrupt status on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read control interrupt status for a USB controller.
+//! This call will return the current status for control interrupts only, the
+//! endpoint interrupt status is retrieved by calling USBIntStatusEndpoint().
+//! The bit values returned should be compared against the \b USB_INTCTRL_*
+//! values.
+//!
+//! The following are the meanings of all \b USB_INCTRL_ flags and the modes
+//! for which they are valid.  These values apply to any calls to
+//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableConrol().
+//! Some of these flags are only valid in the following modes as indicated in
+//! the parenthesis:  Host, Device, and OTG.
+//!
+//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources.
+//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only).
+//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable
+//!                            (OTG Only).
+//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only)
+//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only)
+//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only)
+//! - \b USB_INTCTRL_SOF - Start of Frame Detected.
+//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past
+//!                           the end of a frame. (Host Only)
+//! - \b USB_INTCTRL_RESET - Reset signaling detected by device. (Device Only)
+//! - \b USB_INTCTRL_RESUME - Resume signaling detected.
+//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device
+//!                            Only)
+//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed
+//!                                (OTG Only)
+//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected. (Host Only)
+//!
+//! \note This call will clear the source of all of the control status
+//! interrupts.
+//!
+//! \return Returns the status of the control interrupts for a USB controller.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatusControl(unsigned long ulBase)
+{
+    unsigned long ulStatus;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Get the general interrupt status, these bits go into the upper 8 bits
+    // of the returned value.
+    //
+    ulStatus = HWREGB(ulBase + USB_O_IS);
+
+    //
+    // Add the power fault status.
+    //
+    if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF)
+    {
+        //
+        // Indicate a power fault was detected.
+        //
+        ulStatus |= USB_INTCTRL_POWER_FAULT;
+
+        //
+        // Clear the power fault interrupt.
+        //
+        HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF;
+    }
+
+    if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+    {
+        //
+        // Indicate a id detection was detected.
+        //
+        ulStatus |= USB_INTCTRL_MODE_DETECT;
+
+        //
+        // Clear the id detection interrupt.
+        //
+        HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+    }
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Disable endpoint interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which endpoint interrupts to disable.
+//!
+//! This function will disable endpoint interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which endpoint interrupts to disable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // If any transmit interrupts were disabled then write the transmit
+    // interrupt settings out to the hardware.
+    //
+    HWREGH(ulBase + USB_O_TXIE) &=
+        ~(ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
+
+    //
+    // If any receive interrupts were disabled then write the receive interrupt
+    // settings out to the hardware.
+    //
+    HWREGH(ulBase + USB_O_RXIE) &=
+        ~((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+          USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Enable endpoint interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which endpoint interrupts to enable.
+//!
+//! This function will enable endpoint interrupts for the USB controller
+//! specified by the \e ulBase parameter.  The \e ulFlags parameter specifies
+//! which endpoint interrupts to enable.  The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableEndpoint(unsigned long ulBase, unsigned long ulFlags)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Enable any transmit endpoint interrupts.
+    //
+    HWREGH(ulBase + USB_O_TXIE) |=
+           ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
+
+    //
+    // Enable any receive endpoint interrupts.
+    //
+    HWREGH(ulBase + USB_O_RXIE) |=
+        ((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+         USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Returns the endpoint interrupt status on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read endpoint interrupt status for a USB controller.
+//! This call will return the current status for endpoint interrupts only, the
+//! control interrupt status is retrieved by calling USBIntStatusControl().
+//! The bit values returned should be compared against the \b USB_INTEP_*
+//! values.  These are grouped into classes for \b USB_INTEP_HOST_* and
+//! \b USB_INTEP_DEV_* values to handle both host and device modes with all
+//! endpoints.
+//!
+//! \note This call will clear the source of all of the endpoint interrupts.
+//!
+//! \return Returns the status of the endpoint interrupts for a USB controller.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatusEndpoint(unsigned long ulBase)
+{
+    unsigned long ulStatus;
+
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Get the transmit interrupt status.
+    //
+    ulStatus = HWREGH(ulBase + USB_O_TXIS);
+
+    ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INTEP_RX_SHIFT);
+
+    //
+    // Return the combined interrupt status.
+    //
+    return(ulStatus);
+}
 
 //*****************************************************************************
 //
@@ -612,7 +947,8 @@ USBIntEnable(unsigned long ulBase, unsigned long ulFlags)
 //! also enable the global USB interrupt in the interrupt controller.  The
 //! specific desired USB interrupts must be enabled via a separate call to
 //! USBIntEnable().  It is the interrupt handler's responsibility to clear the
-//! interrupt sources via a call to USBIntStatus().
+//! interrupt sources via a calls to USBIntStatusControl() and
+//! USBIntStatusEndpoint().
 //!
 //! \sa IntRegister() for important information about registering interrupt
 //! handlers.
@@ -1204,7 +1540,7 @@ USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint,
         // Reset the data toggle.
         //
         HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
-            USB_TXCSRL1_CLRDT;
+            USB_RXCSRL1_CLRDT;
     }
 }
 
@@ -1646,8 +1982,8 @@ USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
 //
 //*****************************************************************************
 void
-USBDevEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
-                     unsigned long ulMaxPacketSize, unsigned long ulFlags)
+USBDevEndpointConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+                        unsigned long ulMaxPacketSize, unsigned long ulFlags)
 {
     unsigned long ulRegister;
 
@@ -1758,7 +2094,7 @@ USBDevEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
         //
         // Enable isochronous mode if requested.
         //
-        if(USB_EP_MODE_ISOC & (ulFlags & USB_EP_MODE_MASK))
+        if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
         {
             ulRegister |= USB_RXCSRH1_ISO;
         }
@@ -1793,7 +2129,7 @@ USBDevEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
 //! This function will return the basic configuration for an endpoint in device
 //! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are
 //! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to
-//! USBDevEndpointConfig for this endpoint.
+//! USBDevEndpointConfigSet() for this endpoint.
 //!
 //! \note This function should only be called in device mode.
 //!
@@ -1882,7 +2218,7 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
             // and control mode for the endpoint so we just set something
             // that isn't isochronous.  This ensures that anyone modifying
             // the returned flags in preparation for a call to
-            // USBDevEndpointConfig will not see an unexpected mode change.
+            // USBDevEndpointConfigSet will not see an unexpected mode change.
             // If they decode the returned mode, however, they may be in for
             // a surprise.
             //
@@ -1947,7 +2283,7 @@ USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
             // and control mode for the endpoint so we just set something
             // that isn't isochronous.  This ensures that anyone modifying
             // the returned flags in preparation for a call to
-            // USBDevEndpointConfig will not see an unexpected mode change.
+            // USBDevEndpointConfigSet will not see an unexpected mode change.
             // If they decode the returned mode, however, they may be in for
             // a surprise.
             //
@@ -2125,19 +2461,15 @@ USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
     if(ulFlags & USB_EP_DEV_IN)
     {
         //
-        // Enable DMA on this end point.
+        // Enable DMA on the transmit end point.
         //
         HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |=
             USB_TXCSRH1_DMAEN;
     }
-
-    //
-    // See if the receive DMA is being enabled.
-    //
-    if(ulFlags & USB_EP_DEV_OUT)
+    else
     {
         //
-        // Enable DMA on this end point.
+        // Enable DMA on the receive end point.
         //
         HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |=
             USB_RXCSRH1_DMAEN;
@@ -2164,7 +2496,7 @@ USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint,
                       unsigned long ulFlags)
 {
     //
-    // If this was a reques to disable DMA on the IN portion of the end point
+    // If this was a request to disable DMA on the IN portion of the end point
     // then handle it.
     //
     if(ulFlags & USB_EP_DEV_IN)
@@ -2173,20 +2505,15 @@ USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint,
         // Just disable DMA leave the mode setting.
         //
         HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) &=
-            ~USB_TXCSRH1_DMAEN;
+               ~USB_TXCSRH1_DMAEN;
     }
-
-    //
-    // If this was a request to disable DMA on the OUT portion of the end point
-    // then handle it.
-    //
-    if(ulFlags & USB_EP_DEV_OUT)
+    else
     {
         //
         // Just disable DMA leave the mode setting.
         //
         HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) &=
-            ~USB_RXCSRH1_DMAEN;
+               ~USB_RXCSRH1_DMAEN;
     }
 }
 
@@ -2674,31 +3001,34 @@ USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
         //
         // Only reset the IN or OUT FIFO.
         //
-        if(ulFlags & (USB_EP_HOST_IN | USB_EP_DEV_OUT))
+        if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
         {
             //
-            // Nothing in the FIFO if neither of these bits are set.
+            // Make sure the FIFO is not empty.
             //
-            if((HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &
-                USB_RXCSRL1_RXRDY) == 0)
+            if(HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &
+               USB_TXCSRL1_TXRDY)
             {
                 //
                 // Hit the Flush FIFO bit.
                 //
-                HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
-                    USB_RXCSRL1_FLUSH;
+                HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+                    USB_TXCSRL1_FLUSH;
             }
         }
         else
         {
-            if((HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &
-                USB_TXCSRL1_TXRDY) == 0)
+            //
+            // Make sure that the FIFO is not empty.
+            //
+            if(HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &
+               USB_RXCSRL1_RXRDY)
             {
                 //
                 // Hit the Flush FIFO bit.
                 //
-                HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
-                    USB_TXCSRL1_FLUSH;
+                HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+                    USB_RXCSRL1_FLUSH;
             }
         }
     }
@@ -3010,42 +3340,67 @@ USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
 //! \param ulBase specifies the USB module base address.
 //! \param ulFlags specifies the configuration of the power fault.
 //!
-//! This function will set the behavior of the USB controller during a power
-//! fault and the behavior of the USBPEN pin.  The flags specify the power
+//! This function controls how the USB controller uses its external power
+//! control pins(USBnPFTL and USBnEPEN).  The flags specify the power
 //! fault level sensitivity, the power fault action, and the power enable level
-//! and source.  One of the following can be selected as the power fault level
+//! and source.
+//!
+//! One of the following can be selected as the power fault level
 //! sensitivity:
 //!
-//! - \b USB_HOST_PWRFLT_LOW - Power fault is indicated by the pin being driven
-//!   low.
-//! - \b USB_HOST_PWRFLT_HIGH - Power fault is indicated by the pin being
-//!   driven! high.
+//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin
+//!                            being driven low.
+//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin
+//!                             being driven high.
 //!
 //! One of the following can be selected as the power fault action:
 //!
 //! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault
 //!   detected.
-//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBEPEN pin on a
-//!   power fault.
-//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBEPEN pin low on a
-//!   power fault.
-//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBEPEN pin high on a
-//!   power fault.
+//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBnEPEN pin on a
+//!                               power fault.
+//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a
+//!                               power fault.
+//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a
+//!                                power fault.
 //!
 //! One of the following can be selected as the power enable level and source:
 //!
-//! - \b USB_HOST_PWREN_LOW - USBEPEN is driven low when power is enabled.
-//! - \b USB_HOST_PWREN_HIGH - USBEPEN is driven high when power is enabled.
-//! - \b USB_HOST_PWREN_VBLOW - USBEPEN is driven high when VBUS is low.
-//! - \b USB_HOST_PWREN_VBHIGH - USBEPEN is driven high when VBUS is high.
-//!
-//! \note This function should only be called in host mode.
+//! - \b USB_HOST_PWREN_MAN_LOW - USBEPEN is driven low by the USB controller
+//!                               when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_MAN_HIGH - USBEPEN is driven high by the USB controller
+//!                                when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_AUTOLOW - USBEPEN is driven low by the USB controller
+//!                               automatically if USBOTGSessionRequest() has
+//!                               enabled a session.
+//! - \b USB_HOST_PWREN_AUTOHIGH - USBEPEN is driven high by the USB controller
+//!                                automatically if USBOTGSessionRequest() has
+//!                                enabled a session.
+//!
+//! On devices that support the VBUS glitch filter, the
+//! \b USB_HOST_PWREN_FILTER can be added to ignore small short drops in VBUS
+//! level caused by high power consumption.  This is mainly used to avoid
+//! causing VBUS errors caused by devices with high in-rush current.
+//!
+//! \note The following values have been deprecated and should no longer be
+//!       used.
+//! - \b USB_HOST_PWREN_LOW - Automatically drive USBnEPEN low when power is
+//!                           enabled.
+//! - \b USB_HOST_PWREN_HIGH - Automatically drive USBnEPEN high when power is
+//!                            enabled.
+//! - \b USB_HOST_PWREN_VBLOW - Automatically drive USBnEPEN low when power is
+//!                             enabled.
+//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power is
+//!                              enabled.
+//!
+//! \note This function should only be called on microcontrollers that support
+//! host mode or OTG operation.
 //!
 //! \return None.
 //
 //*****************************************************************************
 void
-USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags)
+USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags)
 {
     //
     // Check the arguments.
@@ -3054,6 +3409,12 @@ USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags)
     ASSERT((ulFlags & ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
                        USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)) == 0);
 
+    //
+    // If requested, enable VBUS droop detection on parts that support this
+    // feature.
+    //
+    HWREG(ulBase + USB_O_VDC) = ulFlags >> 16;
+
     //
     // Set the power fault configuration as specified.  This will not change
     // whether fault detection is enabled or not.
@@ -3142,7 +3503,7 @@ USBHostPwrEnable(unsigned long ulBase)
     ASSERT(ulBase == USB0_BASE);
 
     //
-    // Enable the external power suppply enable signal.
+    // Enable the external power supply enable signal.
     //
     HWREGH(ulBase + USB_O_EPC) |= USB_EPC_EPENDE;
 }
@@ -3385,7 +3746,7 @@ USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint,
     //
     // Clear out the current selection for the channel.
     //
-    ulMask = HWREG(ulBase + USB_O_EPS) & (~ulMask);
+    ulMask = HWREG(ulBase + USB_O_DMASEL) & (~ulMask);
 
     //
     // The input select is now shifted into the correct position based on the
@@ -3396,7 +3757,7 @@ USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint,
     //
     // Write the value out to the register.
     //
-    HWREG(ulBase + USB_O_EPS) = ulMask;
+    HWREG(ulBase + USB_O_DMASEL) = ulMask;
 }
 
 //*****************************************************************************
@@ -3421,9 +3782,39 @@ USBHostMode(unsigned long ulBase)
     ASSERT(ulBase == USB0_BASE);
 
     //
-    // Set the USB controller mode to host.
+    // Force mode in OTG parts that support forcing USB controller mode.
+    // This bit is not writable in USB controllers that do not support
+    // forcing the mode.  Not setting the USB_GPCS_DEVMOD bit makes this a
+    // force of host mode.
+    //
+    HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to device.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to device mode.  This
+//! is only valid on microcontrollers that have the host and device
+//! capabilities and not the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevMode(unsigned long ulBase)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT(ulBase == USB0_BASE);
+
+    //
+    // Set the USB controller mode to device.
     //
-    HWREGB(ulBase + USB_O_GPCS) &= ~(USB_GPCS_DEVMOD);
+    HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD;
 }
 
 //*****************************************************************************

bsp/lm3s/Libraries/driverlib/usb.h

@@ -2,26 +2,23 @@
 //
 // usb.h - Prototypes for the USB Interface Driver.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 
@@ -41,42 +38,103 @@ extern "C"
 
 //*****************************************************************************
 //
-// The following are values that can be passed to USBIntEnable(),
-// USBIntDisable(), and USBIntClear() as the ulIntFlags parameter, and which
-// are returned from USBIntStatus().
-//
+// The following are values that can be passed to USBIntEnableControl() and
+// USBIntDisableControl() as the ulFlags parameter, and are returned from
+// USBIntStatusControl().
+//
+//*****************************************************************************
+#define USB_INTCTRL_ALL         0x000003FF  // All control interrupt sources
+#define USB_INTCTRL_STATUS      0x000000FF  // Status Interrupts
+#define USB_INTCTRL_VBUS_ERR    0x00000080  // VBUS Error
+#define USB_INTCTRL_SESSION     0x00000040  // Session Start Detected
+#define USB_INTCTRL_SESSION_END 0x00000040  // Session End Detected
+#define USB_INTCTRL_DISCONNECT  0x00000020  // Disconnect Detected
+#define USB_INTCTRL_CONNECT     0x00000010  // Device Connect Detected
+#define USB_INTCTRL_SOF         0x00000008  // Start of Frame Detected
+#define USB_INTCTRL_BABBLE      0x00000004  // Babble signaled
+#define USB_INTCTRL_RESET       0x00000004  // Reset signaled
+#define USB_INTCTRL_RESUME      0x00000002  // Resume detected
+#define USB_INTCTRL_SUSPEND     0x00000001  // Suspend detected
+#define USB_INTCTRL_MODE_DETECT 0x00000200  // Mode value valid
+#define USB_INTCTRL_POWER_FAULT 0x00000100  // Power Fault detected
+
 //*****************************************************************************
-#define USB_INT_ALL             0xFF030E0F  // All Interrupt sources
-#define USB_INT_STATUS          0xFF000000  // Status Interrupts
-#define USB_INT_VBUS_ERR        0x80000000  // VBUS Error
-#define USB_INT_SESSION_START   0x40000000  // Session Start Detected
-#define USB_INT_SESSION_END     0x20000000  // Session End Detected
-#define USB_INT_DISCONNECT      0x20000000  // Disconnect Detected
-#define USB_INT_CONNECT         0x10000000  // Device Connect Detected
-#define USB_INT_SOF             0x08000000  // Start of Frame Detected
-#define USB_INT_BABBLE          0x04000000  // Babble signaled
-#define USB_INT_RESET           0x04000000  // Reset signaled
-#define USB_INT_RESUME          0x02000000  // Resume detected
-#define USB_INT_SUSPEND         0x01000000  // Suspend detected
-#define USB_INT_MODE_DETECT     0x00020000  // Mode value valid
-#define USB_INT_POWER_FAULT     0x00010000  // Power Fault detected
-#define USB_INT_HOST_IN         0x00000E00  // Host IN Interrupts
-#define USB_INT_DEV_OUT         0x00000E00  // Device OUT Interrupts
-#define USB_INT_HOST_IN_EP3     0x00000800  // Endpoint 3 Host IN Interrupt
-#define USB_INT_HOST_IN_EP2     0x00000400  // Endpoint 2 Host IN Interrupt
-#define USB_INT_HOST_IN_EP1     0x00000200  // Endpoint 1 Host IN Interrupt
-#define USB_INT_DEV_OUT_EP3     0x00000800  // Endpoint 3 Device OUT Interrupt
-#define USB_INT_DEV_OUT_EP2     0x00000400  // Endpoint 2 Device OUT Interrupt
-#define USB_INT_DEV_OUT_EP1     0x00000200  // Endpoint 1 Device OUT Interrupt
-#define USB_INT_HOST_OUT        0x0000000E  // Host OUT Interrupts
-#define USB_INT_DEV_IN          0x0000000E  // Device IN Interrupts
-#define USB_INT_HOST_OUT_EP3    0x00000008  // Endpoint 3 HOST_OUT Interrupt
-#define USB_INT_HOST_OUT_EP2    0x00000004  // Endpoint 2 HOST_OUT Interrupt
-#define USB_INT_HOST_OUT_EP1    0x00000002  // Endpoint 1 HOST_OUT Interrupt
-#define USB_INT_DEV_IN_EP3      0x00000008  // Endpoint 3 DEV_IN Interrupt
-#define USB_INT_DEV_IN_EP2      0x00000004  // Endpoint 2 DEV_IN Interrupt
-#define USB_INT_DEV_IN_EP1      0x00000002  // Endpoint 1 DEV_IN Interrupt
-#define USB_INT_EP0             0x00000001  // Endpoint 0 Interrupt
+//
+// The following are values that can be passed to USBIntEnableEndpoint() and
+// USBIntDisableEndpoint() as the ulFlags parameter, and are returned from
+// USBIntStatusEndpoint().
+//
+//*****************************************************************************
+#define USB_INTEP_ALL           0xFFFFFFFF  // Host IN Interrupts
+#define USB_INTEP_HOST_IN       0xFFFE0000  // Host IN Interrupts
+#define USB_INTEP_HOST_IN_15    0x80000000  // Endpoint 15 Host IN Interrupt
+#define USB_INTEP_HOST_IN_14    0x40000000  // Endpoint 14 Host IN Interrupt
+#define USB_INTEP_HOST_IN_13    0x20000000  // Endpoint 13 Host IN Interrupt
+#define USB_INTEP_HOST_IN_12    0x10000000  // Endpoint 12 Host IN Interrupt
+#define USB_INTEP_HOST_IN_11    0x08000000  // Endpoint 11 Host IN Interrupt
+#define USB_INTEP_HOST_IN_10    0x04000000  // Endpoint 10 Host IN Interrupt
+#define USB_INTEP_HOST_IN_9     0x02000000  // Endpoint 9 Host IN Interrupt
+#define USB_INTEP_HOST_IN_8     0x01000000  // Endpoint 8 Host IN Interrupt
+#define USB_INTEP_HOST_IN_7     0x00800000  // Endpoint 7 Host IN Interrupt
+#define USB_INTEP_HOST_IN_6     0x00400000  // Endpoint 6 Host IN Interrupt
+#define USB_INTEP_HOST_IN_5     0x00200000  // Endpoint 5 Host IN Interrupt
+#define USB_INTEP_HOST_IN_4     0x00100000  // Endpoint 4 Host IN Interrupt
+#define USB_INTEP_HOST_IN_3     0x00080000  // Endpoint 3 Host IN Interrupt
+#define USB_INTEP_HOST_IN_2     0x00040000  // Endpoint 2 Host IN Interrupt
+#define USB_INTEP_HOST_IN_1     0x00020000  // Endpoint 1 Host IN Interrupt
+
+#define USB_INTEP_DEV_OUT       0xFFFE0000  // Device OUT Interrupts
+#define USB_INTEP_DEV_OUT_15    0x80000000  // Endpoint 15 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_14    0x40000000  // Endpoint 14 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_13    0x20000000  // Endpoint 13 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_12    0x10000000  // Endpoint 12 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_11    0x08000000  // Endpoint 11 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_10    0x04000000  // Endpoint 10 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_9     0x02000000  // Endpoint 9 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_8     0x01000000  // Endpoint 8 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_7     0x00800000  // Endpoint 7 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_6     0x00400000  // Endpoint 6 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_5     0x00200000  // Endpoint 5 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_4     0x00100000  // Endpoint 4 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_3     0x00080000  // Endpoint 3 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_2     0x00040000  // Endpoint 2 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_1     0x00020000  // Endpoint 1 Device OUT Interrupt
+
+#define USB_INTEP_HOST_OUT      0x0000FFFE  // Host OUT Interrupts
+#define USB_INTEP_HOST_OUT_15   0x00008000  // Endpoint 15 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_14   0x00004000  // Endpoint 14 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_13   0x00002000  // Endpoint 13 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_12   0x00001000  // Endpoint 12 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_11   0x00000800  // Endpoint 11 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_10   0x00000400  // Endpoint 10 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_9    0x00000200  // Endpoint 9 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_8    0x00000100  // Endpoint 8 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_7    0x00000080  // Endpoint 7 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_6    0x00000040  // Endpoint 6 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_5    0x00000020  // Endpoint 5 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_4    0x00000010  // Endpoint 4 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_3    0x00000008  // Endpoint 3 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_2    0x00000004  // Endpoint 2 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_1    0x00000002  // Endpoint 1 Host OUT Interrupt
+
+#define USB_INTEP_DEV_IN        0x0000FFFE  // Device IN Interrupts
+#define USB_INTEP_DEV_IN_15     0x00008000  // Endpoint 15 Device IN Interrupt
+#define USB_INTEP_DEV_IN_14     0x00004000  // Endpoint 14 Device IN Interrupt
+#define USB_INTEP_DEV_IN_13     0x00002000  // Endpoint 13 Device IN Interrupt
+#define USB_INTEP_DEV_IN_12     0x00001000  // Endpoint 12 Device IN Interrupt
+#define USB_INTEP_DEV_IN_11     0x00000800  // Endpoint 11 Device IN Interrupt
+#define USB_INTEP_DEV_IN_10     0x00000400  // Endpoint 10 Device IN Interrupt
+#define USB_INTEP_DEV_IN_9      0x00000200  // Endpoint 9 Device IN Interrupt
+#define USB_INTEP_DEV_IN_8      0x00000100  // Endpoint 8 Device IN Interrupt
+#define USB_INTEP_DEV_IN_7      0x00000080  // Endpoint 7 Device IN Interrupt
+#define USB_INTEP_DEV_IN_6      0x00000040  // Endpoint 6 Device IN Interrupt
+#define USB_INTEP_DEV_IN_5      0x00000020  // Endpoint 5 Device IN Interrupt
+#define USB_INTEP_DEV_IN_4      0x00000010  // Endpoint 4 Device IN Interrupt
+#define USB_INTEP_DEV_IN_3      0x00000008  // Endpoint 3 Device IN Interrupt
+#define USB_INTEP_DEV_IN_2      0x00000004  // Endpoint 2 Device IN Interrupt
+#define USB_INTEP_DEV_IN_1      0x00000002  // Endpoint 1 Device IN Interrupt
+
+#define USB_INTEP_0             0x00000001  // Endpoint 0 Interrupt
 
 //*****************************************************************************
 //
@@ -142,7 +200,7 @@ extern "C"
 //*****************************************************************************
 //
 // The following are values that can be passed to USBHostEndpointConfig() and
-// USBDevEndpointConfig() as the ulFlags parameter.
+// USBDevEndpointConfigSet() as the ulFlags parameter.
 //
 //*****************************************************************************
 #define USB_EP_AUTO_SET         0x00000001  // Auto set feature enabled
@@ -157,16 +215,14 @@ extern "C"
 #define USB_EP_MODE_MASK        0x00000300  // Mode Mask
 #define USB_EP_SPEED_LOW        0x00000000  // Low Speed
 #define USB_EP_SPEED_FULL       0x00001000  // Full Speed
-#define USB_EP_HOST_EP0         0x00002000  // Host endpoint 0
-#define USB_EP_HOST_IN          0x00001000  // Host IN endpoint
+#define USB_EP_HOST_IN          0x00000000  // Host IN endpoint
 #define USB_EP_HOST_OUT         0x00002000  // Host OUT endpoint
-#define USB_EP_DEV_EP0          0x00002000  // Device endpoint 0
 #define USB_EP_DEV_IN           0x00002000  // Device IN endpoint
-#define USB_EP_DEV_OUT          0x00001000  // Device OUT endpoint
+#define USB_EP_DEV_OUT          0x00000000  // Device OUT endpoint
 
 //*****************************************************************************
 //
-// The following are values that can be passed to USBHostPwrFaultConfig() as
+// The following are values that can be passed to USBHostPwrConfig() as
 // the ulFlags parameter.
 //
 //*****************************************************************************
@@ -176,10 +232,17 @@ extern "C"
 #define USB_HOST_PWRFLT_EP_TRI  0x00000140
 #define USB_HOST_PWRFLT_EP_LOW  0x00000240
 #define USB_HOST_PWRFLT_EP_HIGH 0x00000340
-#define USB_HOST_PWREN_LOW      0x00000000
-#define USB_HOST_PWREN_HIGH     0x00000001
+#ifndef DEPRECATED
+#define USB_HOST_PWREN_LOW      0x00000002
+#define USB_HOST_PWREN_HIGH     0x00000003
 #define USB_HOST_PWREN_VBLOW    0x00000002
 #define USB_HOST_PWREN_VBHIGH   0x00000003
+#endif
+#define USB_HOST_PWREN_MAN_LOW  0x00000000
+#define USB_HOST_PWREN_MAN_HIGH 0x00000001
+#define USB_HOST_PWREN_AUTOLOW  0x00000002
+#define USB_HOST_PWREN_AUTOHIGH 0x00000003
+#define USB_HOST_PWREN_FILTER   0x00010000
 
 //*****************************************************************************
 //
@@ -305,6 +368,10 @@ extern "C"
                                             // the cable.
 #define USB_OTG_MODE_ASIDE_NPWR 0x00000001  // OTG controller on the A side of
                                             // the cable.
+#define USB_OTG_MODE_ASIDE_SESS 0x00000009  // OTG controller on the A side of
+                                            // the cable Session Valid.
+#define USB_OTG_MODE_ASIDE_AVAL 0x00000011  // OTG controller on the A side of
+                                            // the cable A valid.
 #define USB_OTG_MODE_ASIDE_DEV  0x00000019  // OTG controller on the A side of
                                             // the cable.
 #define USB_OTG_MODE_BSIDE_HOST 0x0000009d  // OTG controller on the B side of
@@ -324,10 +391,10 @@ extern unsigned long USBDevAddrGet(unsigned long ulBase);
 extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress);
 extern void USBDevConnect(unsigned long ulBase);
 extern void USBDevDisconnect(unsigned long ulBase);
-extern void USBDevEndpointConfig(unsigned long ulBase,
-                                 unsigned long ulEndpoint,
-                                 unsigned long ulMaxPacketSize,
-                                 unsigned long ulFlags);
+extern void USBDevEndpointConfigSet(unsigned long ulBase,
+                                    unsigned long ulEndpoint,
+                                    unsigned long ulMaxPacketSize,
+                                    unsigned long ulFlags);
 extern void USBDevEndpointConfigGet(unsigned long ulBase,
                                     unsigned long ulEndpoint,
                                     unsigned long *pulMaxPacketSize,
@@ -400,7 +467,10 @@ extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
                               unsigned long ulAddr, unsigned long ulFlags);
 extern void USBHostPwrDisable(unsigned long ulBase);
 extern void USBHostPwrEnable(unsigned long ulBase);
-extern void USBHostPwrFaultConfig(unsigned long ulBase, unsigned long ulFlags);
+extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags);
+#ifndef DEPRECATED
+#define USBHostPwrFaultConfig   USBHostPwrConfig
+#endif
 extern void USBHostPwrFaultDisable(unsigned long ulBase);
 extern void USBHostPwrFaultEnable(unsigned long ulBase);
 extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
@@ -409,10 +479,17 @@ extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
 extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
 extern unsigned long USBHostSpeedGet(unsigned long ulBase);
 extern void USBHostSuspend(unsigned long ulBase);
-extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
-extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void USBIntDisableControl(unsigned long ulBase,
+                                 unsigned long ulIntFlags);
+extern void USBIntEnableControl(unsigned long ulBase,
+                                unsigned long ulIntFlags);
+extern unsigned long USBIntStatusControl(unsigned long ulBase);
+extern void USBIntDisableEndpoint(unsigned long ulBase,
+                                  unsigned long ulIntFlags);
+extern void USBIntEnableEndpoint(unsigned long ulBase,
+                                 unsigned long ulIntFlags);
+extern unsigned long USBIntStatusEndpoint(unsigned long ulBase);
 extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
-extern unsigned long USBIntStatus(unsigned long ulBase);
 extern void USBIntUnregister(unsigned long ulBase);
 extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart);
 extern unsigned long USBModeGet(unsigned long ulBase);
@@ -420,6 +497,61 @@ extern void USBEndpointDMAChannel(unsigned long ulBase,
                                   unsigned long ulEndpoint,
                                   unsigned long ulChannel);
 extern void USBHostMode(unsigned long ulBase);
+extern void USBHostMode(unsigned long ulBase);
+extern void USBDevMode(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several USB APIs have been renamed, with the original function name being
+// deprecated.  These defines and function protypes provide backward
+// compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnable() and
+// USBIntDisable() as the ulIntFlags parameter, and are returned from
+// USBIntStatus().
+//
+//*****************************************************************************
+#define USB_INT_ALL             0xFF030E0F  // All Interrupt sources
+#define USB_INT_STATUS          0xFF000000  // Status Interrupts
+#define USB_INT_VBUS_ERR        0x80000000  // VBUS Error
+#define USB_INT_SESSION_START   0x40000000  // Session Start Detected
+#define USB_INT_SESSION_END     0x20000000  // Session End Detected
+#define USB_INT_DISCONNECT      0x20000000  // Disconnect Detected
+#define USB_INT_CONNECT         0x10000000  // Device Connect Detected
+#define USB_INT_SOF             0x08000000  // Start of Frame Detected
+#define USB_INT_BABBLE          0x04000000  // Babble signaled
+#define USB_INT_RESET           0x04000000  // Reset signaled
+#define USB_INT_RESUME          0x02000000  // Resume detected
+#define USB_INT_SUSPEND         0x01000000  // Suspend detected
+#define USB_INT_MODE_DETECT     0x00020000  // Mode value valid
+#define USB_INT_POWER_FAULT     0x00010000  // Power Fault detected
+#define USB_INT_HOST_IN         0x00000E00  // Host IN Interrupts
+#define USB_INT_DEV_OUT         0x00000E00  // Device OUT Interrupts
+#define USB_INT_HOST_IN_EP3     0x00000800  // Endpoint 3 Host IN Interrupt
+#define USB_INT_HOST_IN_EP2     0x00000400  // Endpoint 2 Host IN Interrupt
+#define USB_INT_HOST_IN_EP1     0x00000200  // Endpoint 1 Host IN Interrupt
+#define USB_INT_DEV_OUT_EP3     0x00000800  // Endpoint 3 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP2     0x00000400  // Endpoint 2 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP1     0x00000200  // Endpoint 1 Device OUT Interrupt
+#define USB_INT_HOST_OUT        0x0000000E  // Host OUT Interrupts
+#define USB_INT_DEV_IN          0x0000000E  // Device IN Interrupts
+#define USB_INT_HOST_OUT_EP3    0x00000008  // Endpoint 3 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP2    0x00000004  // Endpoint 2 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP1    0x00000002  // Endpoint 1 HOST_OUT Interrupt
+#define USB_INT_DEV_IN_EP3      0x00000008  // Endpoint 3 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP2      0x00000004  // Endpoint 2 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP1      0x00000002  // Endpoint 1 DEV_IN Interrupt
+#define USB_INT_EP0             0x00000001  // Endpoint 0 Interrupt
+
+#define USBDevEndpointConfig    USBDevEndpointConfigSet
+extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long USBIntStatus(unsigned long ulBase);
+#endif
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/driverlib/watchdog.c

@@ -2,26 +2,23 @@
 //
 // watchdog.c - Driver for the Watchdog Timer Module.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/driverlib/watchdog.h

@@ -2,26 +2,23 @@
 //
 // watchdog.h - Prototypes for the Watchdog Timer API
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Peripheral Driver Library.
+// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/inc/asmdefs.h

@@ -2,26 +2,23 @@
 //
 // asmdefs.h - Macros to allow assembly code be portable among toolchains.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/inc/cr_project.xml

@@ -1,26 +1,23 @@
 <!--
 Configuration file for Code Red project inc
 
-Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 Software License Agreement
 
-Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-exclusively on LMI's microcontroller products.
+Texas Instruments (TI) is supplying this software for use solely and
+exclusively on TI's microcontroller products. The software is owned by
+TI and/or its suppliers, and is protected under applicable copyright
+laws. You may not combine this software with "viral" open-source
+software in order to form a larger program.
 
-The software is owned by LMI and/or its suppliers, and is protected under
-applicable copyright laws.  All rights are reserved.  You may not combine
-this software with "viral" open-source software in order to form a larger
-program.  Any use in violation of the foregoing restrictions may subject
-the user to criminal sanctions under applicable laws, as well as to civil
-liability for the breach of the terms and conditions of this license.
+THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+DAMAGES, FOR ANY REASON WHATSOEVER.
 
-THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-
-This is part of revision 4694 of the Stellaris Firmware Development Package.
+This is part of revision 6459 of the Stellaris Firmware Development Package.
 -->
 
 <project>

bsp/lm3s/Libraries/inc/hw_can.h

@@ -1,27 +1,24 @@
 //*****************************************************************************
 //
-// hw_can.h - Defines and macros used when accessing the can.
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,39 +30,40 @@
 // The following are defines for the CAN register offsets.
 //
 //*****************************************************************************
-#define CAN_O_CTL               0x00000000  // Control register
-#define CAN_O_STS               0x00000004  // Status register
-#define CAN_O_ERR               0x00000008  // Error register
-#define CAN_O_BIT               0x0000000C  // Bit Timing register
-#define CAN_O_INT               0x00000010  // Interrupt register
-#define CAN_O_TST               0x00000014  // Test register
-#define CAN_O_BRPE              0x00000018  // Baud Rate Prescaler register
-#define CAN_O_IF1CRQ            0x00000020  // Interface 1 Command Request reg.
-#define CAN_O_IF1CMSK           0x00000024  // Interface 1 Command Mask reg.
-#define CAN_O_IF1MSK1           0x00000028  // Interface 1 Mask 1 register
-#define CAN_O_IF1MSK2           0x0000002C  // Interface 1 Mask 2 register
-#define CAN_O_IF1ARB1           0x00000030  // Interface 1 Arbitration 1 reg.
-#define CAN_O_IF1ARB2           0x00000034  // Interface 1 Arbitration 2 reg.
-#define CAN_O_IF1MCTL           0x00000038  // Interface 1 Message Control reg.
-#define CAN_O_IF1DA1            0x0000003C  // Interface 1 DataA 1 register
-#define CAN_O_IF1DA2            0x00000040  // Interface 1 DataA 2 register
-#define CAN_O_IF1DB1            0x00000044  // Interface 1 DataB 1 register
-#define CAN_O_IF1DB2            0x00000048  // Interface 1 DataB 2 register
-#define CAN_O_IF2CRQ            0x00000080  // Interface 2 Command Request reg.
-#define CAN_O_IF2CMSK           0x00000084  // Interface 2 Command Mask reg.
-#define CAN_O_IF2MSK1           0x00000088  // Interface 2 Mask 1 register
-#define CAN_O_IF2MSK2           0x0000008C  // Interface 2 Mask 2 register
-#define CAN_O_IF2ARB1           0x00000090  // Interface 2 Arbitration 1 reg.
-#define CAN_O_IF2ARB2           0x00000094  // Interface 2 Arbitration 2 reg.
-#define CAN_O_IF2MCTL           0x00000098  // Interface 2 Message Control reg.
-#define CAN_O_IF2DA1            0x0000009C  // Interface 2 DataA 1 register
-#define CAN_O_IF2DA2            0x000000A0  // Interface 2 DataA 2 register
-#define CAN_O_IF2DB1            0x000000A4  // Interface 2 DataB 1 register
-#define CAN_O_IF2DB2            0x000000A8  // Interface 2 DataB 2 register
-#define CAN_O_TXRQ1             0x00000100  // Transmission Request 1 register
-#define CAN_O_TXRQ2             0x00000104  // Transmission Request 2 register
-#define CAN_O_NWDA1             0x00000120  // New Data 1 register
-#define CAN_O_NWDA2             0x00000124  // New Data 2 register
+#define CAN_O_CTL               0x00000000  // CAN Control
+#define CAN_O_STS               0x00000004  // CAN Status
+#define CAN_O_ERR               0x00000008  // CAN Error Counter
+#define CAN_O_BIT               0x0000000C  // CAN Bit Timing
+#define CAN_O_INT               0x00000010  // CAN Interrupt
+#define CAN_O_TST               0x00000014  // CAN Test
+#define CAN_O_BRPE              0x00000018  // CAN Baud Rate Prescaler
+                                            // Extension
+#define CAN_O_IF1CRQ            0x00000020  // CAN IF1 Command Request
+#define CAN_O_IF1CMSK           0x00000024  // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1           0x00000028  // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2           0x0000002C  // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1           0x00000030  // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2           0x00000034  // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL           0x00000038  // CAN IF1 Message Control
+#define CAN_O_IF1DA1            0x0000003C  // CAN IF1 Data A1
+#define CAN_O_IF1DA2            0x00000040  // CAN IF1 Data A2
+#define CAN_O_IF1DB1            0x00000044  // CAN IF1 Data B1
+#define CAN_O_IF1DB2            0x00000048  // CAN IF1 Data B2
+#define CAN_O_IF2CRQ            0x00000080  // CAN IF2 Command Request
+#define CAN_O_IF2CMSK           0x00000084  // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1           0x00000088  // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2           0x0000008C  // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1           0x00000090  // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2           0x00000094  // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL           0x00000098  // CAN IF2 Message Control
+#define CAN_O_IF2DA1            0x0000009C  // CAN IF2 Data A1
+#define CAN_O_IF2DA2            0x000000A0  // CAN IF2 Data A2
+#define CAN_O_IF2DB1            0x000000A4  // CAN IF2 Data B1
+#define CAN_O_IF2DB2            0x000000A8  // CAN IF2 Data B2
+#define CAN_O_TXRQ1             0x00000100  // CAN Transmission Request 1
+#define CAN_O_TXRQ2             0x00000104  // CAN Transmission Request 2
+#define CAN_O_NWDA1             0x00000120  // CAN New Data 1
+#define CAN_O_NWDA2             0x00000124  // CAN New Data 2
 #define CAN_O_MSG1INT           0x00000140  // CAN Message 1 Interrupt Pending
 #define CAN_O_MSG2INT           0x00000144  // CAN Message 2 Interrupt Pending
 #define CAN_O_MSG1VAL           0x00000160  // CAN Message 1 Valid
@@ -73,58 +71,58 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_CTL register.
+// The following are defines for the bit fields in the CAN_O_CTL register.
 //
 //*****************************************************************************
-#define CAN_CTL_TEST            0x00000080  // Test mode enable
-#define CAN_CTL_CCE             0x00000040  // Configuration change enable
-#define CAN_CTL_DAR             0x00000020  // Disable automatic retransmission
-#define CAN_CTL_EIE             0x00000008  // Error interrupt enable
-#define CAN_CTL_SIE             0x00000004  // Status change interrupt enable
-#define CAN_CTL_IE              0x00000002  // Module interrupt enable
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
 #define CAN_CTL_INIT            0x00000001  // Initialization
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_STS register.
+// The following are defines for the bit fields in the CAN_O_STS register.
 //
 //*****************************************************************************
-#define CAN_STS_BOFF            0x00000080  // Bus Off status
-#define CAN_STS_EWARN           0x00000040  // Error Warning status
-#define CAN_STS_EPASS           0x00000020  // Error Passive status
-#define CAN_STS_RXOK            0x00000010  // Received Message Successful
-#define CAN_STS_TXOK            0x00000008  // Transmitted Message Successful
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
 #define CAN_STS_LEC_M           0x00000007  // Last Error Code
-#define CAN_STS_LEC_NONE        0x00000000  // No error
-#define CAN_STS_LEC_STUFF       0x00000001  // Stuff error
-#define CAN_STS_LEC_FORM        0x00000002  // Form(at) error
-#define CAN_STS_LEC_ACK         0x00000003  // Ack error
-#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 error
-#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 error
-#define CAN_STS_LEC_CRC         0x00000006  // CRC error
-#define CAN_STS_LEC_NOEVENT     0x00000007  // Unused
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_ERR register.
+// The following are defines for the bit fields in the CAN_O_ERR register.
 //
 //*****************************************************************************
-#define CAN_ERR_RP              0x00008000  // Receive error passive status
-#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter.
-#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter.
-#define CAN_ERR_REC_S           8           // Receive error counter bit pos
-#define CAN_ERR_TEC_S           0           // Transmit error counter bit pos
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_BIT register.
+// The following are defines for the bit fields in the CAN_O_BIT register.
 //
 //*****************************************************************************
-#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point.
-#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample
-                                            // Point.
-#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width.
-#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescalar.
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
 #define CAN_BIT_TSEG2_S         12
 #define CAN_BIT_TSEG1_S         8
 #define CAN_BIT_SJW_S           6
@@ -132,100 +130,69 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_INT register.
+// The following are defines for the bit fields in the CAN_O_INT register.
 //
 //*****************************************************************************
-#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier.
-#define CAN_INT_INTID_NONE      0x00000000  // No Interrupt Pending
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
 #define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_TST register.
+// The following are defines for the bit fields in the CAN_O_TST register.
 //
 //*****************************************************************************
-#define CAN_TST_RX              0x00000080  // CAN_RX pin status
-#define CAN_TST_TX_M            0x00000060  // Overide control of CAN_TX pin
-#define CAN_TST_TX_CANCTL       0x00000000  // CAN core controls CAN_TX
-#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point on CAN_TX
-#define CAN_TST_TX_DOMINANT     0x00000040  // Dominant value on CAN_TX
-#define CAN_TST_TX_RECESSIVE    0x00000060  // Recessive value on CAN_TX
-#define CAN_TST_LBACK           0x00000010  // Loop back mode
-#define CAN_TST_SILENT          0x00000008  // Silent mode
-#define CAN_TST_BASIC           0x00000004  // Basic mode
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the CAN_BRPE register.
+// The following are defines for the bit fields in the CAN_O_BRPE register.
 //
 //*****************************************************************************
-#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescalar Extension.
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
 #define CAN_BRPE_BRPE_S         0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TXRQ1 register.
-//
-//*****************************************************************************
-#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
-#define CAN_TXRQ1_TXRQST_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_TXRQ2 register.
-//
-//*****************************************************************************
-#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits.
-#define CAN_TXRQ2_TXRQST_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_NWDA1 register.
-//
-//*****************************************************************************
-#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits.
-#define CAN_NWDA1_NEWDAT_S      0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_NWDA2 register.
-//
-//*****************************************************************************
-#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits.
-#define CAN_NWDA2_NEWDAT_S      0
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF1CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data.
-#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request.
-#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF1MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -233,9 +200,9 @@
 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF1MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -243,7 +210,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF1ARB1_ID_S        0
 
 //*****************************************************************************
@@ -251,10 +218,10 @@
 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF1ARB2_ID_S        0
 
 //*****************************************************************************
@@ -262,16 +229,16 @@
 // The following are defines for the bit fields in the CAN_O_IF1MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF1MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -279,7 +246,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA1_DATA_S       0
 
 //*****************************************************************************
@@ -287,7 +254,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DA2_DATA_S       0
 
 //*****************************************************************************
@@ -295,7 +262,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB1_DATA_S       0
 
 //*****************************************************************************
@@ -303,7 +270,7 @@
 // The following are defines for the bit fields in the CAN_O_IF1DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF1DB2_DATA_S       0
 
 //*****************************************************************************
@@ -311,33 +278,34 @@
 // The following are defines for the bit fields in the CAN_O_IF2CRQ register.
 //
 //*****************************************************************************
-#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag.
-#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number.
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
 #define CAN_IF2CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
                                             // it is interpreted as 0x20, or
-                                            // object 32.
+                                            // object 32
+#define CAN_IF2CRQ_MNUM_S       0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2CMSK register.
 //
 //*****************************************************************************
-#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read.
-#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits.
-#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits.
-#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits.
-#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit.
-#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data.
-#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request.
-#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3.
-#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7.
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask.
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
 #define CAN_IF2MSK1_IDMSK_S     0
 
 //*****************************************************************************
@@ -345,9 +313,9 @@
 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
 //
 //*****************************************************************************
-#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier.
-#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction.
-#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask.
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
 #define CAN_IF2MSK2_IDMSK_S     0
 
 //*****************************************************************************
@@ -355,7 +323,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier.
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
 #define CAN_IF2ARB1_ID_S        0
 
 //*****************************************************************************
@@ -363,10 +331,10 @@
 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid.
-#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier.
-#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction.
-#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier.
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
 #define CAN_IF2ARB2_ID_S        0
 
 //*****************************************************************************
@@ -374,16 +342,16 @@
 // The following are defines for the bit fields in the CAN_O_IF2MCTL register.
 //
 //*****************************************************************************
-#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data.
-#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost.
-#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending.
-#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask.
-#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable.
-#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable.
-#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable.
-#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request.
-#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer.
-#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code.
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
 #define CAN_IF2MCTL_DLC_S       0
 
 //*****************************************************************************
@@ -391,7 +359,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA1_DATA_S       0
 
 //*****************************************************************************
@@ -399,7 +367,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DA2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DA2_DATA_S       0
 
 //*****************************************************************************
@@ -407,7 +375,7 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB1 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB1_DATA_S       0
 
 //*****************************************************************************
@@ -415,15 +383,47 @@
 // The following are defines for the bit fields in the CAN_O_IF2DB2 register.
 //
 //*****************************************************************************
-#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data.
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
 #define CAN_IF2DB2_DATA_S       0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the CAN_O_MSG1INT register.
 //
 //*****************************************************************************
-#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG1INT_INTPND_S    0
 
 //*****************************************************************************
@@ -431,7 +431,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG2INT register.
 //
 //*****************************************************************************
-#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits.
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
 #define CAN_MSG2INT_INTPND_S    0
 
 //*****************************************************************************
@@ -439,7 +439,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG1VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG1VAL_MSGVAL_S    0
 
 //*****************************************************************************
@@ -447,7 +447,7 @@
 // The following are defines for the bit fields in the CAN_O_MSG2VAL register.
 //
 //*****************************************************************************
-#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits.
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
 #define CAN_MSG2VAL_MSGVAL_S    0
 
 //*****************************************************************************
@@ -462,58 +462,14 @@
 // The following are deprecated defines for the CAN register offsets.
 //
 //*****************************************************************************
-#define CAN_O_MSGINT1           0x00000140  // Intr. Pending in Msg Obj 1 reg.
-#define CAN_O_MSGINT2           0x00000144  // Intr. Pending in Msg Obj 2 reg.
-#define CAN_O_MSGVAL1           0x00000160  // Message Valid in Msg Obj 1 reg.
-#define CAN_O_MSGVAL2           0x00000164  // Message Valid in Msg Obj 2 reg.
+#define CAN_O_MSGINT1           0x00000140  // Intr. Pending in Msg Obj 1 reg
+#define CAN_O_MSGINT2           0x00000144  // Intr. Pending in Msg Obj 2 reg
+#define CAN_O_MSGVAL1           0x00000160  // Message Valid in Msg Obj 1 reg
+#define CAN_O_MSGVAL2           0x00000164  // Message Valid in Msg Obj 2 reg
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the reset values of the can
-// registers.
-//
-//*****************************************************************************
-#define CAN_RV_IF1MSK2          0x0000FFFF
-#define CAN_RV_IF1MSK1          0x0000FFFF
-#define CAN_RV_IF2MSK1          0x0000FFFF
-#define CAN_RV_IF2MSK2          0x0000FFFF
-#define CAN_RV_BIT              0x00002301
-#define CAN_RV_CTL              0x00000001
-#define CAN_RV_IF1CRQ           0x00000001
-#define CAN_RV_IF2CRQ           0x00000001
-#define CAN_RV_TXRQ2            0x00000000
-#define CAN_RV_IF2DB1           0x00000000
-#define CAN_RV_INT              0x00000000
-#define CAN_RV_IF1DB2           0x00000000
-#define CAN_RV_BRPE             0x00000000
-#define CAN_RV_IF2DA2           0x00000000
-#define CAN_RV_MSGVAL2          0x00000000
-#define CAN_RV_TXRQ1            0x00000000
-#define CAN_RV_IF1MCTL          0x00000000
-#define CAN_RV_IF1DB1           0x00000000
-#define CAN_RV_STS              0x00000000
-#define CAN_RV_MSGINT1          0x00000000
-#define CAN_RV_IF1DA2           0x00000000
-#define CAN_RV_TST              0x00000000
-#define CAN_RV_IF1ARB1          0x00000000
-#define CAN_RV_IF1ARB2          0x00000000
-#define CAN_RV_NWDA2            0x00000000
-#define CAN_RV_IF2CMSK          0x00000000
-#define CAN_RV_NWDA1            0x00000000
-#define CAN_RV_IF1DA1           0x00000000
-#define CAN_RV_IF2DA1           0x00000000
-#define CAN_RV_IF2MCTL          0x00000000
-#define CAN_RV_MSGVAL1          0x00000000
-#define CAN_RV_IF1CMSK          0x00000000
-#define CAN_RV_ERR              0x00000000
-#define CAN_RV_IF2ARB2          0x00000000
-#define CAN_RV_MSGINT2          0x00000000
-#define CAN_RV_IF2ARB1          0x00000000
-#define CAN_RV_IF2DB2           0x00000000
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_STS
+// The following are deprecated defines for the bit fields in the CAN_O_STS
 // register.
 //
 //*****************************************************************************
@@ -521,7 +477,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the CAN_ERR
+// The following are deprecated defines for the bit fields in the CAN_O_ERR
 // register.
 //
 //*****************************************************************************
@@ -532,7 +488,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the CAN_BIT
+// The following are deprecated defines for the bit fields in the CAN_O_BIT
 // register.
 //
 //*****************************************************************************
@@ -543,7 +499,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the CAN_INT
+// The following are deprecated defines for the bit fields in the CAN_O_INT
 // register.
 //
 //*****************************************************************************
@@ -551,7 +507,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the CAN_TST
+// The following are deprecated defines for the bit fields in the CAN_O_TST
 // register.
 //
 //*****************************************************************************
@@ -559,17 +515,125 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the CAN_BRPE
+// The following are deprecated defines for the bit fields in the CAN_O_BRPE
 // register.
 //
 //*****************************************************************************
 #define CAN_BRPE_BRPE           0x0000000F  // Baud rate prescaler extension
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TXRQ1
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST        0x0000FFFF  // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TXRQ2
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST        0x0000FFFF  // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_NWDA1
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDATA       0x0000FFFF  // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_NWDA2
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDATA       0x0000FFFF  // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGINT1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT1_INTPND      0x0000FFFF  // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGINT2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT2_INTPND      0x0000FFFF  // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL1_MSGVAL      0x0000FFFF  // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL2_MSGVAL      0x0000FFFF  // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the can
+// registers.
+//
+//*****************************************************************************
+#define CAN_RV_IF1MSK2          0x0000FFFF
+#define CAN_RV_IF1MSK1          0x0000FFFF
+#define CAN_RV_IF2MSK1          0x0000FFFF
+#define CAN_RV_IF2MSK2          0x0000FFFF
+#define CAN_RV_BIT              0x00002301
+#define CAN_RV_CTL              0x00000001
+#define CAN_RV_IF1CRQ           0x00000001
+#define CAN_RV_IF2CRQ           0x00000001
+#define CAN_RV_TXRQ2            0x00000000
+#define CAN_RV_IF2DB1           0x00000000
+#define CAN_RV_INT              0x00000000
+#define CAN_RV_IF1DB2           0x00000000
+#define CAN_RV_BRPE             0x00000000
+#define CAN_RV_IF2DA2           0x00000000
+#define CAN_RV_MSGVAL2          0x00000000
+#define CAN_RV_TXRQ1            0x00000000
+#define CAN_RV_IF1MCTL          0x00000000
+#define CAN_RV_IF1DB1           0x00000000
+#define CAN_RV_STS              0x00000000
+#define CAN_RV_MSGINT1          0x00000000
+#define CAN_RV_IF1DA2           0x00000000
+#define CAN_RV_TST              0x00000000
+#define CAN_RV_IF1ARB1          0x00000000
+#define CAN_RV_IF1ARB2          0x00000000
+#define CAN_RV_NWDA2            0x00000000
+#define CAN_RV_IF2CMSK          0x00000000
+#define CAN_RV_NWDA1            0x00000000
+#define CAN_RV_IF1DA1           0x00000000
+#define CAN_RV_IF2DA1           0x00000000
+#define CAN_RV_IF2MCTL          0x00000000
+#define CAN_RV_MSGVAL1          0x00000000
+#define CAN_RV_IF1CMSK          0x00000000
+#define CAN_RV_ERR              0x00000000
+#define CAN_RV_IF2ARB2          0x00000000
+#define CAN_RV_MSGINT2          0x00000000
+#define CAN_RV_IF2ARB1          0x00000000
+#define CAN_RV_IF2DB2           0x00000000
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1CRQ
 // and CAN_IF1CRQ registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFCRQ_BUSY          0x00008000  // Busy flag status
@@ -579,7 +643,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1CMSK
 // and CAN_IF2CMSK registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFCMSK_WRNRD        0x00000080  // Write, not Read
@@ -596,7 +660,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1MSK1
 // and CAN_IF2MSK1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFMSK1_MSK          0x0000FFFF  // Identifier Mask
@@ -605,7 +669,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1MSK2
 // and CAN_IF2MSK2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFMSK2_MXTD         0x00008000  // Mask extended identifier
@@ -616,7 +680,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1ARB1
 // and CAN_IF2ARB1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFARB1_ID           0x0000FFFF  // Identifier
@@ -625,7 +689,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1ARB2
 // and CAN_IF2ARB2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFARB2_MSGVAL       0x00008000  // Message valid
@@ -637,7 +701,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1MCTL
 // and CAN_IF2MCTL registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFMCTL_NEWDAT       0x00008000  // New Data
@@ -655,7 +719,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DA1
 // and CAN_IF2DA1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDA1_DATA          0x0000FFFF  // Data - bytes 1 and 0
@@ -664,7 +728,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DA2
 // and CAN_IF2DA2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDA2_DATA          0x0000FFFF  // Data - bytes 3 and 2
@@ -673,7 +737,7 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DB1
 // and CAN_IF2DB1 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDB1_DATA          0x0000FFFF  // Data - bytes 5 and 4
@@ -682,75 +746,11 @@
 //
 // The following are deprecated defines for the bit fields in the CAN_IF1DB2
 // and CAN_IF2DB2 registers.
-// Note: All bits may not be available in all registers
+// Note: All bits may not be available in all registers.
 //
 //*****************************************************************************
 #define CAN_IFDB2_DATA          0x0000FFFF  // Data - bytes 7 and 6
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_TXRQ1
-// register.
-//
-//*****************************************************************************
-#define CAN_TXRQ1_TXRQST        0x0000FFFF  // Transmission Request Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_TXRQ2
-// register.
-//
-//*****************************************************************************
-#define CAN_TXRQ2_TXRQST        0x0000FFFF  // Transmission Request Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_NWDA1
-// register.
-//
-//*****************************************************************************
-#define CAN_NWDA1_NEWDATA       0x0000FFFF  // New Data Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_NWDA2
-// register.
-//
-//*****************************************************************************
-#define CAN_NWDA2_NEWDATA       0x0000FFFF  // New Data Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGINT1
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGINT1_INTPND      0x0000FFFF  // Interrupt Pending Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGINT2
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGINT2_INTPND      0x0000FFFF  // Interrupt Pending Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGVAL1
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGVAL1_MSGVAL      0x0000FFFF  // Message Valid Bits
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the CAN_MSGVAL2
-// register.
-//
-//*****************************************************************************
-#define CAN_MSGVAL2_MSGVAL      0x0000FFFF  // Message Valid Bits
-
 #endif
 
 #endif // __HW_CAN_H__

bsp/lm3s/Libraries/inc/hw_comp.h

@@ -2,26 +2,23 @@
 //
 // hw_comp.h - Macros used when accessing the comparator hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,7 +27,7 @@
 
 //*****************************************************************************
 //
-// The following are defines for the comparator register offsets.
+// The following are defines for the Comparator register offsets.
 //
 //*****************************************************************************
 #define COMP_O_ACMIS            0x00000000  // Analog Comparator Masked
@@ -41,12 +38,12 @@
                                             // Enable
 #define COMP_O_ACREFCTL         0x00000010  // Analog Comparator Reference
                                             // Voltage Control
-#define COMP_O_ACSTAT0          0x00000020  // Comp0 status register
-#define COMP_O_ACCTL0           0x00000024  // Comp0 control register
-#define COMP_O_ACSTAT1          0x00000040  // Comp1 status register
-#define COMP_O_ACCTL1           0x00000044  // Comp1 control register
-#define COMP_O_ACSTAT2          0x00000060  // Comp2 status register
-#define COMP_O_ACCTL2           0x00000064  // Comp2 control register
+#define COMP_O_ACSTAT0          0x00000020  // Analog Comparator Status 0
+#define COMP_O_ACCTL0           0x00000024  // Analog Comparator Control 0
+#define COMP_O_ACSTAT1          0x00000040  // Analog Comparator Status 1
+#define COMP_O_ACCTL1           0x00000044  // Analog Comparator Control 1
+#define COMP_O_ACSTAT2          0x00000060  // Analog Comparator Status 2
+#define COMP_O_ACCTL2           0x00000064  // Analog Comparator Control 2
 
 //*****************************************************************************
 //
@@ -54,29 +51,29 @@
 //
 //*****************************************************************************
 #define COMP_ACMIS_IN2          0x00000004  // Comparator 2 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
-                                            // Status.
+                                            // Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACRIS register.
 //
 //*****************************************************************************
-#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status.
-#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status.
-#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status.
+#define COMP_ACRIS_IN2          0x00000004  // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACINTEN register.
 //
 //*****************************************************************************
-#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable.
-#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable.
-#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable.
+#define COMP_ACINTEN_IN2        0x00000004  // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
 
 //*****************************************************************************
 //
@@ -84,9 +81,9 @@
 // register.
 //
 //*****************************************************************************
-#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable.
-#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range.
-#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref.
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
 #define COMP_ACREFCTL_VREF_S    0
 
 //*****************************************************************************
@@ -94,93 +91,96 @@
 // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL1 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
 //
 //*****************************************************************************
-#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value.
+#define COMP_ACSTAT2_OVAL       0x00000002  // Comparator Output Value
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the COMP_O_ACCTL2 register.
 //
 //*****************************************************************************
-#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable.
-#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive.
-#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value
+#define COMP_ACCTL2_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN   0x00000000  // Pin value of Cn+
 #define COMP_ACCTL2_ASRCP_PIN0  0x00000200  // Pin value of C0+
 #define COMP_ACCTL2_ASRCP_REF   0x00000400  // Internal voltage reference
-#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value.
-#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense.
+                                            // (VIREF)
+#define COMP_ACCTL2_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M      0x00000060  // Trigger Sense
 #define COMP_ACCTL2_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
 #define COMP_ACCTL2_TSEN_FALL   0x00000020  // Falling edge
 #define COMP_ACCTL2_TSEN_RISE   0x00000040  // Rising edge
 #define COMP_ACCTL2_TSEN_BOTH   0x00000060  // Either edge
-#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value.
-#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense.
+#define COMP_ACCTL2_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M      0x0000000C  // Interrupt Sense
 #define COMP_ACCTL2_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
 #define COMP_ACCTL2_ISEN_FALL   0x00000004  // Falling edge
 #define COMP_ACCTL2_ISEN_RISE   0x00000008  // Rising edge
 #define COMP_ACCTL2_ISEN_BOTH   0x0000000C  // Either edge
-#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert.
+#define COMP_ACCTL2_CINV        0x00000002  // Comparator Output Invert
 
 //*****************************************************************************
 //
@@ -191,27 +191,17 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the comparator register offsets.
+// The following are deprecated defines for the Comparator register offsets.
 //
 //*****************************************************************************
 #define COMP_O_MIS              0x00000000  // Interrupt status register
 #define COMP_O_RIS              0x00000004  // Raw interrupt status register
 #define COMP_O_INTEN            0x00000008  // Interrupt enable register
-#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the COMP_MIS,
-// COMP_RIS, and COMP_INTEN registers.
-//
-//*****************************************************************************
-#define COMP_INT_2              0x00000004  // Comp2 interrupt
-#define COMP_INT_1              0x00000002  // Comp1 interrupt
-#define COMP_INT_0              0x00000001  // Comp0 interrupt
+#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the COMP_REFCTL
+// The following are deprecated defines for the bit fields in the COMP_O_REFCTL
 // register.
 //
 //*****************************************************************************
@@ -220,6 +210,16 @@
 #define COMP_REFCTL_VREF_MASK   0x0000000F  // Reference voltage select mask
 #define COMP_REFCTL_VREF_SHIFT  0
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_MIS,
+// COMP_RIS, and COMP_INTEN registers.
+//
+//*****************************************************************************
+#define COMP_INT_2              0x00000004  // Comp2 interrupt
+#define COMP_INT_1              0x00000002  // Comp1 interrupt
+#define COMP_INT_0              0x00000001  // Comp0 interrupt
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
@@ -270,7 +270,7 @@
 #define COMP_RV_MIS             0x00000000  // Interrupt status register
 #define COMP_RV_ACCTL0          0x00000000  // Comp0 control register
 #define COMP_RV_ACSTAT1         0x00000000  // Comp1 status register
-#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg.
+#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg
 
 #endif
 

bsp/lm3s/Libraries/inc/hw_epi.h

@@ -2,26 +2,23 @@
 //
 // hw_epi.h - Macros for use in accessing the EPI registers.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,18 +27,19 @@
 
 //*****************************************************************************
 //
-// The following are defines for the External Peripheral Interface (EPI)
+// The following are defines for the External Peripheral Interface register
+// offsets.
 //
 //*****************************************************************************
 #define EPI_O_CFG               0x00000000  // EPI Configuration
 #define EPI_O_BAUD              0x00000004  // EPI Main Baud Rate
-#define EPI_O_GPCFG             0x00000010  // EPI General Purpose
-                                            // Configuration
-#define EPI_O_SDRAMCFG          0x00000010  // EPI SDRAM Mode Configuration
-#define EPI_O_HB8CFG            0x00000010  // EPI Host-Bus 8 Mode
+#define EPI_O_HB16CFG           0x00000010  // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG             0x00000010  // EPI General-Purpose
                                             // Configuration
+#define EPI_O_SDRAMCFG          0x00000010  // EPI SDRAM Configuration
+#define EPI_O_HB8CFG            0x00000010  // EPI Host-Bus 8 Configuration
 #define EPI_O_HB8CFG2           0x00000014  // EPI Host-Bus 8 Configuration 2
-#define EPI_O_SDRAMCFG2         0x00000014  // EPI SDRAM Configuration 2
+#define EPI_O_HB16CFG2          0x00000014  // EPI Host-Bus 16 Configuration 2
 #define EPI_O_GPCFG2            0x00000014  // EPI General-Purpose
                                             // Configuration 2
 #define EPI_O_ADDRMAP           0x0000001C  // EPI Address Map
@@ -74,130 +72,199 @@
 // The following are defines for the bit fields in the EPI_O_CFG register.
 //
 //*****************************************************************************
-#define EPI_CFG_BLKEN           0x00000010  // Block Enable.
-#define EPI_CFG_MODE_M          0x0000000F  // Mode Select.
-#define EPI_CFG_MODE_NONE       0x00000000  // None
+#define EPI_CFG_BLKEN           0x00000010  // Block Enable
+#define EPI_CFG_MODE_M          0x0000000F  // Mode Select
+#define EPI_CFG_MODE_NONE       0x00000000  // General Purpose
 #define EPI_CFG_MODE_SDRAM      0x00000001  // SDRAM
 #define EPI_CFG_MODE_HB8        0x00000002  // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16       0x00000003  // 16-Bit Host-Bus (HB16)
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_BAUD register.
 //
 //*****************************************************************************
-#define EPI_BAUD_COUNT_M        0x0000FFFF  // Baud Rate Counter.
-#define EPI_BAUD_COUNT_S        0
+#define EPI_BAUD_COUNT1_M       0xFFFF0000  // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M       0x0000FFFF  // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S       16
+#define EPI_BAUD_COUNT0_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
 //
 //*****************************************************************************
-#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range.
-#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0
-#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15
-#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30
-#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50
-#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter.
-#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode.
-#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM.
-#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64Mb (8MB)
-#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128Mb (16MB)
-#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256Mb (32MB)
-#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512Mb (64MB)
-#define EPI_SDRAMCFG_RFSH_S     16
+#define EPI_HB16CFG_XFFEN       0x00800000  // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN       0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH      0x00200000  // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH      0x00100000  // READ Strobe Polarity
+#define EPI_HB16CFG_MAXWAIT_M   0x0000FF00  // Maximum Wait
+#define EPI_HB16CFG_WRWS_M      0x000000C0  // CS0n Write Wait States
+#define EPI_HB16CFG_WRWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_WRWS_1      0x00000040  // 1 wait state
+#define EPI_HB16CFG_WRWS_2      0x00000080  // 2 wait states
+#define EPI_HB16CFG_WRWS_3      0x000000C0  // 3 wait states
+#define EPI_HB16CFG_RDWS_M      0x00000030  // CS0n Read Wait States
+#define EPI_HB16CFG_RDWS_0      0x00000000  // No wait states
+#define EPI_HB16CFG_RDWS_1      0x00000010  // 1 wait state
+#define EPI_HB16CFG_RDWS_2      0x00000020  // 2 wait states
+#define EPI_HB16CFG_RDWS_3      0x00000030  // 3 wait states
+#define EPI_HB16CFG_BSEL        0x00000004  // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M      0x00000003  // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX  0x00000000  // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001  // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM   0x00000002  // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO  0x00000003  // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S   8
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_GPCFG register.
 //
 //*****************************************************************************
-#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin.
-#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated.
-#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable.
-#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin.
-#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame.
-#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count.
-#define EPI_GPCFG_RW            0x00200000  // Read and Write.
-#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes.
-#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads.
-#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait.
-#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size.
+#define EPI_GPCFG_CLKPIN        0x80000000  // Clock Pin
+#define EPI_GPCFG_CLKGATE       0x40000000  // Clock Gated
+#define EPI_GPCFG_RDYEN         0x10000000  // Ready Enable
+#define EPI_GPCFG_FRMPIN        0x08000000  // Framing Pin
+#define EPI_GPCFG_FRM50         0x04000000  // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M      0x03C00000  // Frame Count
+#define EPI_GPCFG_RW            0x00200000  // Read and Write
+#define EPI_GPCFG_WR2CYC        0x00080000  // 2-Cycle Writes
+#define EPI_GPCFG_RD2CYC        0x00040000  // 2-Cycle Reads
+#define EPI_GPCFG_MAXWAIT_M     0x0000FF00  // Maximum Wait
+#define EPI_GPCFG_ASIZE_M       0x00000030  // Address Bus Size
 #define EPI_GPCFG_ASIZE_NONE    0x00000000  // No address
-#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // 4 Bits Wide (EPI24 to EPI27)
-#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // 12 Bits Wide (EPI16 to EPI27).
-                                            // Cannot be used with 24-bit data
-#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // 20 Bits Wide
-#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus.
-#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 4 Bits Wide (EPI0 to EPI7)
-#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0 to EPI15)
-#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0 to EPI23)
-#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide. May not be used
-                                            // with clock (EPI0 to EPI31). This
-                                            // value is normally used for
-                                            // acquisition input and actuator
-                                            // control as well as other general
-                                            // purpose uses.
+#define EPI_GPCFG_ASIZE_4BIT    0x00000010  // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT   0x00000020  // Up to 12 bits wide. This size
+                                            // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT   0x00000030  // Up to 20 bits wide. This size
+                                            // cannot be used with data sizes
+                                            // other than 8
+#define EPI_GPCFG_DSIZE_M       0x00000003  // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT    0x00000000  // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT   0x00000001  // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT   0x00000002  // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT   0x00000003  // 32 Bits Wide (EPI0S0 to EPI0S31)
 #define EPI_GPCFG_FRMCNT_S      22
 #define EPI_GPCFG_MAXWAIT_S     8
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M     0xC0000000  // Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE  0x00000000  // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000  // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000  // 30 - 50 MHz
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000  // 50 - 100 MHz
+#define EPI_SDRAMCFG_RFSH_M     0x07FF0000  // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP      0x00000200  // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M     0x00000003  // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB   0x00000000  // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB  0x00000001  // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB  0x00000002  // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB  0x00000003  // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S     16
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_HB8CFG register.
 //
 //*****************************************************************************
-#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable.
-#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable.
-#define EPI_HB8CFG_WRHIGH       0x00200000  // WRITE Strobe Polarity.
-#define EPI_HB8CFG_RDHIGH       0x00100000  // READ Strobe Polarity.
-#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait.
-#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States.
+#define EPI_HB8CFG_XFFEN        0x00800000  // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN        0x00400000  // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH       0x00200000  // CS0n WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH       0x00100000  // CS0n READ Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M    0x0000FF00  // Maximum Wait
+#define EPI_HB8CFG_WRWS_M       0x000000C0  // Write Wait States
 #define EPI_HB8CFG_WRWS_0       0x00000000  // No wait states
 #define EPI_HB8CFG_WRWS_1       0x00000040  // 1 wait state
 #define EPI_HB8CFG_WRWS_2       0x00000080  // 2 wait states
 #define EPI_HB8CFG_WRWS_3       0x000000C0  // 3 wait states
-#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States.
+#define EPI_HB8CFG_RDWS_M       0x00000030  // Read Wait States
 #define EPI_HB8CFG_RDWS_0       0x00000000  // No wait states
 #define EPI_HB8CFG_RDWS_1       0x00000010  // 1 wait state
 #define EPI_HB8CFG_RDWS_2       0x00000020  // 2 wait states
 #define EPI_HB8CFG_RDWS_3       0x00000030  // 3 wait states
-#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode.
+#define EPI_HB8CFG_MODE_M       0x00000003  // Host Bus Sub-Mode
 #define EPI_HB8CFG_MODE_MUX     0x00000000  // ADMUX - AD[7:0]
 #define EPI_HB8CFG_MODE_NMUX    0x00000001  // ADNONMUX - D[7:0]
-#define EPI_HB8CFG_MODE_SRAM    0x00000002  // SRAM
-#define EPI_HB8CFG_MODE_FIFO    0x00000003  // FIFO - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM    0x00000002  // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO    0x00000003  // XFIFO - D[7:0]
 #define EPI_HB8CFG_MAXWAIT_S    8
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode
+#define EPI_HB8CFG2_CSBAUD      0x04000000  // Chip Select Baud Rate
+#define EPI_HB8CFG2_CSCFG_M     0x03000000  // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE   0x00000000  // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS    0x01000000  // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS   0x02000000  // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS  0x03000000  // ALE with Dual CSn Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_WORD       0x80000000  // Word Access Mode
+#define EPI_HB16CFG2_CSBAUD     0x04000000  // Chip Select Baud Rate
+#define EPI_HB16CFG2_CSCFG_M    0x03000000  // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE  0x00000000  // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS   0x01000000  // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS  0x02000000  // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000  // ALE with Dual CSn Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_ADDRMAP register.
 //
 //*****************************************************************************
-#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size.
-#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 0x100 (256)
-#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 0x10000 (64 KB)
-#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 0x1000000 (16 MB)
-#define EPI_ADDRMAP_EPSZ_512MB  0x000000C0  // 0x20000000 (512 MB)
-#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address.
+#define EPI_ADDRMAP_EPSZ_M      0x000000C0  // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB   0x00000040  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB   0x00000080  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB  0x000000C0  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M     0x00000030  // External Peripheral Address
 #define EPI_ADDRMAP_EPADR_NONE  0x00000000  // Not mapped
-#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA0000000
-#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC0000000
-#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size.
-#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 0x100 (256)
-#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 0x10000 (64KB)
-#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 0x1000000 (16MB)
-#define EPI_ADDRMAP_ERSZ_512MB  0x0000000C  // 0x20000000 (512MB)
-#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address.
+#define EPI_ADDRMAP_EPADR_A000  0x00000010  // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000  0x00000020  // At 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M      0x0000000C  // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B   0x00000000  // 256 bytes; lower address range:
+                                            // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB   0x00000004  // 64 KB; lower address range:
+                                            // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB   0x00000008  // 16 MB; lower address range:
+                                            // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB  0x0000000C  // 256 MB; lower address range:
+                                            // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M     0x00000003  // External RAM Address
 #define EPI_ADDRMAP_ERADR_NONE  0x00000000  // Not mapped
-#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x60000000
-#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x80000000
+#define EPI_ADDRMAP_ERADR_6000  0x00000001  // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000  0x00000002  // At 0x8000.0000
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_RSIZE0 register.
 //
 //*****************************************************************************
-#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size.
+#define EPI_RSIZE0_SIZE_M       0x00000003  // Current Size
 #define EPI_RSIZE0_SIZE_8BIT    0x00000001  // Byte (8 bits)
 #define EPI_RSIZE0_SIZE_16BIT   0x00000002  // Half-word (16 bits)
 #define EPI_RSIZE0_SIZE_32BIT   0x00000003  // Word (32 bits)
@@ -207,7 +274,7 @@
 // The following are defines for the bit fields in the EPI_O_RADDR0 register.
 //
 //*****************************************************************************
-#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address.
+#define EPI_RADDR0_ADDR_M       0x1FFFFFFF  // Current Address
 #define EPI_RADDR0_ADDR_S       0
 
 //*****************************************************************************
@@ -215,7 +282,7 @@
 // The following are defines for the bit fields in the EPI_O_RPSTD0 register.
 //
 //*****************************************************************************
-#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count.
+#define EPI_RPSTD0_POSTCNT_M    0x00001FFF  // Post Count
 #define EPI_RPSTD0_POSTCNT_S    0
 
 //*****************************************************************************
@@ -223,7 +290,7 @@
 // The following are defines for the bit fields in the EPI_O_RSIZE1 register.
 //
 //*****************************************************************************
-#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size.
+#define EPI_RSIZE1_SIZE_M       0x00000003  // Current Size
 #define EPI_RSIZE1_SIZE_8BIT    0x00000001  // Byte (8 bits)
 #define EPI_RSIZE1_SIZE_16BIT   0x00000002  // Half-word (16 bits)
 #define EPI_RSIZE1_SIZE_32BIT   0x00000003  // Word (32 bits)
@@ -233,7 +300,7 @@
 // The following are defines for the bit fields in the EPI_O_RADDR1 register.
 //
 //*****************************************************************************
-#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address.
+#define EPI_RADDR1_ADDR_M       0x1FFFFFFF  // Current Address
 #define EPI_RADDR1_ADDR_S       0
 
 //*****************************************************************************
@@ -241,15 +308,28 @@
 // The following are defines for the bit fields in the EPI_O_RPSTD1 register.
 //
 //*****************************************************************************
-#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count.
+#define EPI_RPSTD1_POSTCNT_M    0x00001FFF  // Post Count
 #define EPI_RPSTD1_POSTCNT_S    0
 
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low
+#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full
+#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty
+#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence
+#define EPI_STAT_WBUSY          0x00000020  // Write Busy
+#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE         0x00000001  // Register Active
+
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
 //
 //*****************************************************************************
-#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count.
+#define EPI_RFIFOCNT_COUNT_M    0x00000007  // FIFO Count
 #define EPI_RFIFOCNT_COUNT_S    0
 
 //*****************************************************************************
@@ -257,7 +337,7 @@
 // The following are defines for the bit fields in the EPI_O_READFIFO register.
 //
 //*****************************************************************************
-#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO_DATA_M     0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO_DATA_S     0
 
 //*****************************************************************************
@@ -266,7 +346,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO1_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO1_DATA_S    0
 
 //*****************************************************************************
@@ -275,7 +355,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO2_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO2_DATA_S    0
 
 //*****************************************************************************
@@ -284,7 +364,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO3_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO3_DATA_S    0
 
 //*****************************************************************************
@@ -293,7 +373,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO4_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO4_DATA_S    0
 
 //*****************************************************************************
@@ -302,7 +382,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO5_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO5_DATA_S    0
 
 //*****************************************************************************
@@ -311,7 +391,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO6_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO6_DATA_S    0
 
 //*****************************************************************************
@@ -320,7 +400,7 @@
 // register.
 //
 //*****************************************************************************
-#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data.
+#define EPI_READFIFO7_DATA_M    0xFFFFFFFF  // Reads Data
 #define EPI_READFIFO7_DATA_S    0
 
 //*****************************************************************************
@@ -328,101 +408,92 @@
 // The following are defines for the bit fields in the EPI_O_FIFOLVL register.
 //
 //*****************************************************************************
-#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error.
-#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error.
-#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO.
-#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Empty
-#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // >= 1/4 full
-#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // >= 1/2 full
-#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // >= 3/4 full
-#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO.
+#define EPI_FIFOLVL_WFERR       0x00020000  // Write Full Error
+#define EPI_FIFOLVL_RSERR       0x00010000  // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M    0x00000070  // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000  // Trigger when there are 1 to 4
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_4  0x00000020  // Trigger when there are 1 to 3
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2  0x00000030  // Trigger when there are 1 to 2
+                                            // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4  0x00000040  // Trigger when there is 1 space
+                                            // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_M    0x00000007  // Read FIFO
 #define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000  // Empty
-#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // <= 1/8 full
-#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // <= 1/4 full
-#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // <= 1/2 full
-#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // <= 3/4 full
-#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // <= 7/8 full
+#define EPI_FIFOLVL_RDFIFO_1_8  0x00000001  // Trigger when there are 1 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4  0x00000002  // Trigger when there are 2 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2  0x00000003  // Trigger when there are 4 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4  0x00000004  // Trigger when there are 6 or more
+                                            // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8  0x00000005  // Trigger when there are 7 or more
+                                            // entries in the NBRFIFO
 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006  // Trigger when there are 8 entries
-                                            // in the NBRFIFO.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_IM register.
-//
-//*****************************************************************************
-#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask.
-#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask.
-#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask.
+                                            // in the NBRFIFO
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_RIS register.
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
 //
 //*****************************************************************************
-#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status.
-#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status.
-#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status.
+#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_MIS register.
+// The following are defines for the bit fields in the EPI_O_IM register.
 //
 //*****************************************************************************
-#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status.
-#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status.
-#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status.
+#define EPI_IM_WRIM             0x00000004  // Write Interrupt Mask
+#define EPI_IM_RDIM             0x00000002  // Read Interrupt Mask
+#define EPI_IM_ERRIM            0x00000001  // Error Interrupt Mask
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
-// register.
+// The following are defines for the bit fields in the EPI_O_RIS register.
 //
 //*****************************************************************************
-#define EPI_SDRAMCFG2_RCM       0x80000000  // Read Capture Mode.
+#define EPI_RIS_WRRIS           0x00000004  // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS           0x00000002  // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS          0x00000001  // Error Raw Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+// The following are defines for the bit fields in the EPI_O_MIS register.
 //
 //*****************************************************************************
-#define EPI_HB8CFG2_WORD        0x80000000  // Word Access Mode.
-#define EPI_HB8CFG2_CSCFG       0x01000000  // Chip Select Configuration.
+#define EPI_MIS_WRMIS           0x00000004  // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS           0x00000002  // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS          0x00000001  // Error Masked Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+// The following are defines for the bit fields in the EPI_O_EISC register.
 //
 //*****************************************************************************
-#define EPI_GPCFG2_WORD         0x80000000  // Word Access Mode.
+#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error
+#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error
+#define EPI_EISC_TOUT           0x00000001  // Timeout Error
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_STAT register.
+// The following definitions are deprecated.
 //
 //*****************************************************************************
-#define EPI_STAT_CELOW          0x00000200  // Clock Enable Low.
-#define EPI_STAT_XFFULL         0x00000100  // External FIFO Full.
-#define EPI_STAT_XFEMPTY        0x00000080  // External FIFO Empty.
-#define EPI_STAT_INITSEQ        0x00000040  // Initialization Sequence.
-#define EPI_STAT_WBUSY          0x00000020  // Write Busy.
-#define EPI_STAT_NBRBUSY        0x00000010  // Non-Blocking Read Busy.
-#define EPI_STAT_ACTIVE         0x00000001  // Register Active.
+#ifndef DEPRECATED
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+// The following are deprecated defines for the bit fields in the EPI_O_BAUD
+// register.
 //
 //*****************************************************************************
-#define EPI_WFIFOCNT_WTAV_M     0x00000007  // Available Write Transactions.
-#define EPI_WFIFOCNT_WTAV_S     0
+#define EPI_BAUD_COUNT_M        0x0000FFFF  // Baud Rate Counter
+#define EPI_BAUD_COUNT_S        0
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EPI_O_EISC register.
-//
-//*****************************************************************************
-#define EPI_EISC_WTFULL         0x00000004  // Write FIFO Full Error.
-#define EPI_EISC_RSTALL         0x00000002  // Read Stalled Error.
-#define EPI_EISC_TOUT           0x00000001  // Timeout Error.
+#endif
 
 #endif // __HW_EPI_H__

bsp/lm3s/Libraries/inc/hw_ethernet.h

@@ -2,26 +2,23 @@
 //
 // hw_ethernet.h - Macros used when accessing the Ethernet hardware.
 //
-// Copyright (c) 2006-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2006-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,86 +27,114 @@
 
 //*****************************************************************************
 //
-// The following are defines for the MAC register offsets in the Ethernet
-// Controller.
+// The following are defines for the Ethernet MAC register offsets.
 //
 //*****************************************************************************
 #define MAC_O_RIS               0x00000000  // Ethernet MAC Raw Interrupt
-                                            // Status
-#define MAC_O_IACK              0x00000000  // Interrupt Acknowledge Register
-#define MAC_O_IM                0x00000004  // Interrupt Mask Register
-#define MAC_O_RCTL              0x00000008  // Receive Control Register
-#define MAC_O_TCTL              0x0000000C  // Transmit Control Register
-#define MAC_O_DATA              0x00000010  // Data Register
-#define MAC_O_IA0               0x00000014  // Individual Address Register 0
-#define MAC_O_IA1               0x00000018  // Individual Address Register 1
-#define MAC_O_THR               0x0000001C  // Threshold Register
-#define MAC_O_MCTL              0x00000020  // Management Control Register
-#define MAC_O_MDV               0x00000024  // Management Divider Register
-#define MAC_O_MTXD              0x0000002C  // Management Transmit Data Reg
-#define MAC_O_MRXD              0x00000030  // Management Receive Data Reg
-#define MAC_O_NP                0x00000034  // Number of Packets Register
-#define MAC_O_TR                0x00000038  // Transmission Request Register
-#define MAC_O_TS                0x0000003C  // Timer Support Register
+                                            // Status/Acknowledge
+#define MAC_O_IACK              0x00000000  // Ethernet MAC Raw Interrupt
+                                            // Status/Acknowledge
+#define MAC_O_IM                0x00000004  // Ethernet MAC Interrupt Mask
+#define MAC_O_RCTL              0x00000008  // Ethernet MAC Receive Control
+#define MAC_O_TCTL              0x0000000C  // Ethernet MAC Transmit Control
+#define MAC_O_DATA              0x00000010  // Ethernet MAC Data
+#define MAC_O_IA0               0x00000014  // Ethernet MAC Individual Address
+                                            // 0
+#define MAC_O_IA1               0x00000018  // Ethernet MAC Individual Address
+                                            // 1
+#define MAC_O_THR               0x0000001C  // Ethernet MAC Threshold
+#define MAC_O_MCTL              0x00000020  // Ethernet MAC Management Control
+#define MAC_O_MDV               0x00000024  // Ethernet MAC Management Divider
+#define MAC_O_MTXD              0x0000002C  // Ethernet MAC Management Transmit
+                                            // Data
+#define MAC_O_MRXD              0x00000030  // Ethernet MAC Management Receive
+                                            // Data
+#define MAC_O_NP                0x00000034  // Ethernet MAC Number of Packets
+#define MAC_O_TR                0x00000038  // Ethernet MAC Transmission
+                                            // Request
+#define MAC_O_TS                0x0000003C  // Ethernet MAC Timer Support
 #define MAC_O_LED               0x00000040  // Ethernet MAC LED Encoding
-#define MAC_O_MDIX              0x00000044  // MDIX Register
+#define MAC_O_MDIX              0x00000044  // Ethernet PHY MDIX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IACK register.
+// The following are defines for the bit fields in the MAC_O_IACK register.
 //
 //*****************************************************************************
 #define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
-#define MAC_IACK_MDINT          0x00000020  // Clear MDI Transaction Complete
-#define MAC_IACK_RXER           0x00000010  // Clear RX Error
-#define MAC_IACK_FOV            0x00000008  // Clear RX FIFO Overrun
-#define MAC_IACK_TXEMP          0x00000004  // Clear TX FIFO Empy
-#define MAC_IACK_TXER           0x00000002  // Clear TX Error
-#define MAC_IACK_RXINT          0x00000001  // Clear RX Packet Available
+#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear Receive Error
+#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error
+#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IM register.
+// The following are defines for the bit fields in the MAC_O_IM register.
 //
 //*****************************************************************************
 #define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
-#define MAC_IM_MDINTM           0x00000020  // Mask MDI Transaction Complete
-#define MAC_IM_RXERM            0x00000010  // Mask RX Error
-#define MAC_IM_FOVM             0x00000008  // Mask RX FIFO Overrun
-#define MAC_IM_TXEMPM           0x00000004  // Mask TX FIFO Empy
-#define MAC_IM_TXERM            0x00000002  // Mask TX Error
-#define MAC_IM_RXINTM           0x00000001  // Mask RX Packet Available
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_RCTL register.
+// The following are defines for the bit fields in the MAC_O_RCTL register.
 //
 //*****************************************************************************
-#define MAC_RCTL_RSTFIFO        0x00000010  // Clear the Receive FIFO
-#define MAC_RCTL_BADCRC         0x00000008  // Reject Packets With Bad CRC
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
 #define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
-#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Packets
-#define MAC_RCTL_RXEN           0x00000001  // Enable Ethernet Receiver
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TCTL register.
+// The following are defines for the bit fields in the MAC_O_TCTL register.
 //
 //*****************************************************************************
-#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex mode
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
 #define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
-#define MAC_TCTL_PADEN          0x00000002  // Enable Automatic Padding
-#define MAC_TCTL_TXEN           0x00000001  // Enable Ethernet Transmitter
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IA0 register.
+// The following are defines for the bit fields in the MAC_O_DATA register.
 //
 //*****************************************************************************
-#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4.
-#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3.
-#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2.
-#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1.
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
 #define MAC_IA0_MACOCT4_S       24
 #define MAC_IA0_MACOCT3_S       16
 #define MAC_IA0_MACOCT2_S       8
@@ -117,85 +142,107 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_IA1 register.
+// The following are defines for the bit fields in the MAC_O_IA1 register.
 //
 //*****************************************************************************
-#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6.
-#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5.
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
 #define MAC_IA1_MACOCT6_S       8
 #define MAC_IA1_MACOCT5_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TXTH register.
+// The following are defines for the bit fields in the MAC_O_THR register.
 //
 //*****************************************************************************
-#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value.
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
 #define MAC_THR_THRESH_S        0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MCTL register.
+// The following are defines for the bit fields in the MAC_O_MCTL register.
 //
 //*****************************************************************************
-#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address.
-#define MAC_MCTL_WRITE          0x00000002  // Next MII Transaction is Write
-#define MAC_MCTL_START          0x00000001  // Start MII Transaction
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
 #define MAC_MCTL_REGADR_S       3
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MDV register.
+// The following are defines for the bit fields in the MAC_O_MDV register.
 //
 //*****************************************************************************
-#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider.
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
 #define MAC_MDV_DIV_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MTXD register.
+// The following are defines for the bit fields in the MAC_O_MTXD register.
 //
 //*****************************************************************************
-#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data.
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
 #define MAC_MTXD_MDTX_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MRXD register.
+// The following are defines for the bit fields in the MAC_O_MRXD register.
 //
 //*****************************************************************************
-#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data.
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
 #define MAC_MRXD_MDRX_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_NP register.
+// The following are defines for the bit fields in the MAC_O_NP register.
 //
 //*****************************************************************************
 #define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
-                                            // FIFO.
+                                            // FIFO
 #define MAC_NP_NPR_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TXRQ register.
+// The following are defines for the bit fields in the MAC_O_TR register.
 //
 //*****************************************************************************
-#define MAC_TR_NEWTX            0x00000001  // Start an Ethernet Transmission
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_TS register.
+// The following are defines for the bit fields in the MAC_O_TS register.
 //
 //*****************************************************************************
-#define MAC_TS_TSEN             0x00000001  // Enable Timestamp Logic
+#define MAC_TS_TSEN             0x00000001  // Time Stamp Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the MAC_MDIX register.
+// The following are defines for the bit fields in the MAC_O_LED register.
 //
 //*****************************************************************************
-#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable.
+#define MAC_LED_LED1_M          0x00000F00  // LED1 Source
+#define MAC_LED_LED1_LINK       0x00000000  // Link OK
+#define MAC_LED_LED1_RXTX       0x00000100  // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100        0x00000500  // 100BASE-TX mode
+#define MAC_LED_LED1_10         0x00000600  // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX     0x00000700  // Full-Duplex
+#define MAC_LED_LED1_LINKACT    0x00000800  // Link OK & Blink=RX or TX
+                                            // Activity
+#define MAC_LED_LED0_M          0x0000000F  // LED0 Source
+#define MAC_LED_LED0_LINK       0x00000000  // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX       0x00000001  // RX or TX Activity
+#define MAC_LED_LED0_100        0x00000005  // 100BASE-TX mode
+#define MAC_LED_LED0_10         0x00000006  // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX     0x00000007  // Full-Duplex
+#define MAC_LED_LED0_LINKACT    0x00000008  // Link OK & Blink=RX or TX
+                                            // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN             0x00000001  // MDI/MDI-X Enable
 
 //*****************************************************************************
 //
@@ -221,7 +268,7 @@
 #define PHY_MR16                0x00000010  // Ethernet PHY Management Register
                                             // 16 - Vendor-Specific
 #define PHY_MR17                0x00000011  // Ethernet PHY Management Register
-                                            // 17 - Interrupt Control/Status
+                                            // 17 - Mode Control/Status
 #define PHY_MR18                0x00000012  // Ethernet PHY Management Register
                                             // 18 - Diagnostic
 #define PHY_MR19                0x00000013  // Ethernet PHY Management Register
@@ -231,7 +278,7 @@
 #define PHY_MR24                0x00000018  // Ethernet PHY Management Register
                                             // 24 -MDI/MDIX Control
 #define PHY_MR27                0x0000001B  // Ethernet PHY Management Register
-                                            // 27 -Special Control/Status
+                                            // 27 - Special Control/Status
 #define PHY_MR29                0x0000001D  // Ethernet PHY Management Register
                                             // 29 - Interrupt Status
 #define PHY_MR30                0x0000001E  // Ethernet PHY Management Register
@@ -244,46 +291,33 @@
 // The following are defines for the bit fields in the PHY_MR0 register.
 //
 //*****************************************************************************
-#define PHY_MR0_RESET           0x00008000  // Reset Registers.
-#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode.
-#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select.
-#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable.
-#define PHY_MR0_PWRDN           0x00000800  // Power Down.
-#define PHY_MR0_ISO             0x00000400  // Isolate.
-#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation.
-#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode.
-#define PHY_MR0_COLT            0x00000080  // Collision Test.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_RIS register.
-//
-//*****************************************************************************
-#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt.
-#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete.
-#define MAC_RIS_RXER            0x00000010  // Receive Error.
-#define MAC_RIS_FOV             0x00000008  // FIFO Overrrun.
-#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty.
-#define MAC_RIS_TXER            0x00000002  // Transmit Error.
-#define MAC_RIS_RXINT           0x00000001  // Packet Received.
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR1 register.
 //
 //*****************************************************************************
-#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode.
-#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode.
-#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode.
-#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode.
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
 #define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
-                                            // Suppressed.
-#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete.
-#define PHY_MR1_RFAULT          0x00000010  // Remote Fault.
-#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation.
-#define PHY_MR1_LINK            0x00000004  // Link Made.
-#define PHY_MR1_JAB             0x00000002  // Jabber Condition.
-#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities.
+                                            // Suppressed
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
 
 //*****************************************************************************
 //
@@ -291,7 +325,7 @@
 //
 //*****************************************************************************
 #define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
-                                            // Identifier[21:6].
+                                            // Identifier[21:6]
 #define PHY_MR2_OUI_S           0
 
 //*****************************************************************************
@@ -300,9 +334,9 @@
 //
 //*****************************************************************************
 #define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
-                                            // Identifier[5:0].
-#define PHY_MR3_MN_M            0x000003F0  // Model Number.
-#define PHY_MR3_RN_M            0x0000000F  // Revision Number.
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
 #define PHY_MR3_OUI_S           10
 #define PHY_MR3_MN_S            4
 #define PHY_MR3_RN_S            0
@@ -312,13 +346,13 @@
 // The following are defines for the bit fields in the PHY_MR4 register.
 //
 //*****************************************************************************
-#define PHY_MR4_NP              0x00008000  // Next Page.
-#define PHY_MR4_RF              0x00002000  // Remote Fault.
-#define PHY_MR4_A3              0x00000100  // Technology Ability Field[3].
-#define PHY_MR4_A2              0x00000080  // Technology Ability Field[2].
-#define PHY_MR4_A1              0x00000040  // Technology Ability Field[1].
-#define PHY_MR4_A0              0x00000020  // Technology Ability Field[0].
-#define PHY_MR4_S_M             0x0000001F  // Selector Field.
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
 #define PHY_MR4_S_S             0
 
 //*****************************************************************************
@@ -326,11 +360,11 @@
 // The following are defines for the bit fields in the PHY_MR5 register.
 //
 //*****************************************************************************
-#define PHY_MR5_NP              0x00008000  // Next Page.
-#define PHY_MR5_ACK             0x00004000  // Acknowledge.
-#define PHY_MR5_RF              0x00002000  // Remote Fault.
-#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field.
-#define PHY_MR5_S_M             0x0000001F  // Selector Field.
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
 #define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
 #define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
 #define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
@@ -342,37 +376,27 @@
 // The following are defines for the bit fields in the PHY_MR6 register.
 //
 //*****************************************************************************
-#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault.
-#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able.
-#define PHY_MR6_PRX             0x00000002  // New Page Received.
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
 #define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
-                                            // Able.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_DATA register.
-//
-//*****************************************************************************
-#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data.
-#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data.
-#define MAC_DATA_RXDATA_S       0
-#define MAC_DATA_TXDATA_S       0
+                                            // Able
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR16 register.
 //
 //*****************************************************************************
-#define PHY_MR16_RPTR           0x00008000  // Repeater Mode.
-#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity.
-#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode.
-#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing.
-#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode.
-#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier.
-#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable.
-#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity.
-#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass.
-#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control.
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode
+#define PHY_MR16_SR_M           0x000003C0  // Silicon Revision Identifier
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control
 #define PHY_MR16_SR_S           6
 
 //*****************************************************************************
@@ -380,55 +404,51 @@
 // The following are defines for the bit fields in the PHY_MR17 register.
 //
 //*****************************************************************************
-#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable.
-#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable.
-#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable.
-#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down.
-#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable.
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable
+#define PHY_MR17_FASTRIP        0x00004000  // 10-BASE-T Fast Mode Enable
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable
+#define PHY_MR17_EDPD           0x00002000  // Enable Energy Detect Power Down
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable
 #define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
-                                            // Interrupt Enable.
-#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable.
-#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable.
+                                            // Interrupt Enable
+#define PHY_MR17_LSQE           0x00000800  // Low Squelch Enable
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable
 #define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
-                                            // Enable.
-#define PHY_MR17_MDPB           0x00000400  // Management Data Preamble Bypass.
-#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable.
-#define PHY_MR17_FLPBK          0x00000200  // Far Loopback Mode.
+                                            // Enable
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable
 #define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
-                                            // Interrupt Enable.
-#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode.
-#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt.
-#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt.
-#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt.
+                                            // Interrupt Enable
+#define PHY_MR17_FASTEST        0x00000100  // Auto-Negotiation Test Mode
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt
 #define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
-                                            // Interrupt.
-#define PHY_MR17_REFCE          0x00000010  // Reference Clock Enable.
-#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt.
-#define PHY_MR17_PADBP          0x00000008  // PHY Address Bypass.
-#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt.
-#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status.
-#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt.
-#define PHY_MR17_ENON           0x00000002  // Energy On.
+                                            // Interrupt
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt
+#define PHY_MR17_FGLS           0x00000004  // Force Good Link Status
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt
+#define PHY_MR17_ENON           0x00000002  // Energy On
 #define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
-                                            // Interrupt.
+                                            // Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR18 register.
 //
 //*****************************************************************************
-#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure.
-#define PHY_MR18_DPLX           0x00000800  // Duplex Mode.
-#define PHY_MR18_RATE           0x00000400  // Rate.
-#define PHY_MR18_RXSD           0x00000200  // Receive Detection.
-#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock.
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode
+#define PHY_MR18_RATE           0x00000400  // Rate
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR19 register.
 //
 //*****************************************************************************
-#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection.
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection
 #define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
                                             // loss
 #define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
@@ -443,7 +463,7 @@
 // The following are defines for the bit fields in the PHY_MR23 register.
 //
 //*****************************************************************************
-#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source.
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source
 #define PHY_MR23_LED1_LINK      0x00000000  // Link OK
 #define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
 #define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
@@ -451,7 +471,7 @@
 #define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
 #define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
                                             // Activity
-#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source.
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source
 #define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
 #define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
 #define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
@@ -465,11 +485,11 @@
 // The following are defines for the bit fields in the PHY_MR24 register.
 //
 //*****************************************************************************
-#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode.
-#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable.
-#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration.
-#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete.
-#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed.
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed
 #define PHY_MR24_MDIX_SD_S      0
 
 //*****************************************************************************
@@ -477,72 +497,50 @@
 // The following are defines for the bit fields in the PHY_MR27 register.
 //
 //*****************************************************************************
-#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T.
+#define PHY_MR27_XPOL           0x00000010  // Polarity State of 10 BASE-T
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR29 register.
 //
 //*****************************************************************************
-#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt.
+#define PHY_MR29_EONIS          0x00000080  // ENERGYON Interrupt
 #define PHY_MR29_ANCOMPIS       0x00000040  // Auto-Negotiation Complete
-                                            // Interrupt.
-#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt.
-#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt.
-#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge.
-#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault.
-#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received.
+                                            // Interrupt
+#define PHY_MR29_RFLTIS         0x00000020  // Remote Fault Interrupt
+#define PHY_MR29_LDIS           0x00000010  // Link Down Interrupt
+#define PHY_MR29_LPACKIS        0x00000008  // Auto-Negotiation LP Acknowledge
+#define PHY_MR29_PDFIS          0x00000004  // Parallel Detection Fault
+#define PHY_MR29_PRXIS          0x00000002  // Auto Negotiation Page Received
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR30 register.
 //
 //*****************************************************************************
-#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled.
+#define PHY_MR30_EONIM          0x00000080  // ENERGYON Interrupt Enabled
 #define PHY_MR30_ANCOMPIM       0x00000040  // Auto-Negotiation Complete
-                                            // Interrupt Enabled.
-#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled.
-#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled.
+                                            // Interrupt Enabled
+#define PHY_MR30_RFLTIM         0x00000020  // Remote Fault Interrupt Enabled
+#define PHY_MR30_LDIM           0x00000010  // Link Down Interrupt Enabled
 #define PHY_MR30_LPACKIM        0x00000008  // Auto-Negotiation LP Acknowledge
-                                            // Enabled.
-#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault
-                                            // Enabled.
+                                            // Enabled
+#define PHY_MR30_PDFIM          0x00000004  // Parallel Detection Fault Enabled
 #define PHY_MR30_PRXIM          0x00000002  // Auto Negotiation Page Received
-                                            // Enabled.
+                                            // Enabled
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PHY_MR31 register.
 //
 //*****************************************************************************
-#define PHY_MR31_BPRMG          0x00008000  // Bypass Remove Glitch.
-#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done.
-#define PHY_MR31_EN4B5B         0x00000040  // Enable 4B5B Encoding/Decoding.
-#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value.
-#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable.
-#define PHY_MR31_SPEED_S        2
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the MAC_O_LED register.
-//
-//*****************************************************************************
-#define MAC_LED_LED1_M          0x000000F0  // LED1 Source.
-#define MAC_LED_LED1_LINK       0x00000000  // Link OK
-#define MAC_LED_LED1_RXTX       0x00000010  // RX or TX Activity (Default LED1)
-#define MAC_LED_LED1_100        0x00000050  // 100BASE-TX mode
-#define MAC_LED_LED1_10         0x00000060  // 10BASE-T mode
-#define MAC_LED_LED1_DUPLEX     0x00000070  // Full-Duplex
-#define MAC_LED_LED1_LINKACT    0x00000080  // Link OK & Blink=RX or TX
-                                            // Activity
-#define MAC_LED_LED0_M          0x0000000F  // LED0 Source.
-#define MAC_LED_LED0_LINK       0x00000000  // Link OK (Default LED0)
-#define MAC_LED_LED0_RXTX       0x00000001  // RX or TX Activity
-#define MAC_LED_LED0_100        0x00000005  // 100BASE-TX mode
-#define MAC_LED_LED0_10         0x00000006  // 10BASE-T mode
-#define MAC_LED_LED0_DUPLEX     0x00000007  // Full-Duplex
-#define MAC_LED_LED0_LINKACT    0x00000008  // Link OK & Blink=RX or TX
-                                            // Activity
+#define PHY_MR31_AUTODONE       0x00001000  // Auto Negotiation Done
+#define PHY_MR31_SPEED_M        0x0000001C  // HCD Speed Value
+#define PHY_MR31_SPEED_10HD     0x00000004  // 10BASE-T half duplex
+#define PHY_MR31_SPEED_100HD    0x00000008  // 100BASE-T half duplex
+#define PHY_MR31_SPEED_10FD     0x00000014  // 10BASE-T full duplex
+#define PHY_MR31_SPEED_100FD    0x00000018  // 100BASE-T full duplex
+#define PHY_MR31_SCRDIS         0x00000001  // Scramble Disable
 
 //*****************************************************************************
 //
@@ -553,39 +551,14 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the MAC register offsets in the
-// Ethernet Controller.
+// The following are deprecated defines for the Ethernet MAC register offsets.
 //
 //*****************************************************************************
 #define MAC_O_IS                0x00000000  // Interrupt Status Register
-#define MAC_O_MADD              0x00000028  // Management Address Register
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the reset values of the MAC
-// registers.
-//
-//*****************************************************************************
-#define MAC_RV_MDV              0x00000080
-#define MAC_RV_IM               0x0000007F
-#define MAC_RV_THR              0x0000003F
-#define MAC_RV_RCTL             0x00000008
-#define MAC_RV_IA0              0x00000000
-#define MAC_RV_TCTL             0x00000000
-#define MAC_RV_DATA             0x00000000
-#define MAC_RV_MRXD             0x00000000
-#define MAC_RV_TR               0x00000000
-#define MAC_RV_IS               0x00000000
-#define MAC_RV_NP               0x00000000
-#define MAC_RV_MCTL             0x00000000
-#define MAC_RV_MTXD             0x00000000
-#define MAC_RV_IA1              0x00000000
-#define MAC_RV_IACK             0x00000000
-#define MAC_RV_MADD             0x00000000
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_IS
+// The following are deprecated defines for the bit fields in the MAC_O_IS
 // register.
 //
 //*****************************************************************************
@@ -599,7 +572,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_IA0
+// The following are deprecated defines for the bit fields in the MAC_O_IA0
 // register.
 //
 //*****************************************************************************
@@ -610,7 +583,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_IA1
+// The following are deprecated defines for the bit fields in the MAC_O_IA1
 // register.
 //
 //*****************************************************************************
@@ -619,7 +592,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_TXTH
+// The following are deprecated defines for the bit fields in the MAC_O_THR
 // register.
 //
 //*****************************************************************************
@@ -627,7 +600,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_MCTL
+// The following are deprecated defines for the bit fields in the MAC_O_MCTL
 // register.
 //
 //*****************************************************************************
@@ -635,7 +608,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_MDV
+// The following are deprecated defines for the bit fields in the MAC_O_MDV
 // register.
 //
 //*****************************************************************************
@@ -643,7 +616,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_MTXD
+// The following are deprecated defines for the bit fields in the MAC_O_MTXD
 // register.
 //
 //*****************************************************************************
@@ -651,15 +624,15 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_MRXD
+// The following are deprecated defines for the bit fields in the MAC_O_MRXD
 // register.
 //
 //*****************************************************************************
-#define MAC_MRXD_MDRX           0x0000FFFF  // Data Read from Last MII Trans.
+#define MAC_MRXD_MDRX           0x0000FFFF  // Data Read from Last MII Trans
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the MAC_NP
+// The following are deprecated defines for the bit fields in the MAC_O_NP
 // register.
 //
 //*****************************************************************************
@@ -678,6 +651,29 @@
 #define PHY_MR23_LED0_RX        0x00000003  // RX Activity
 #define PHY_MR23_LED0_COL       0x00000004  // Collision
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the MAC
+// registers.
+//
+//*****************************************************************************
+#define MAC_RV_MDV              0x00000080
+#define MAC_RV_IM               0x0000007F
+#define MAC_RV_THR              0x0000003F
+#define MAC_RV_RCTL             0x00000008
+#define MAC_RV_IA0              0x00000000
+#define MAC_RV_TCTL             0x00000000
+#define MAC_RV_DATA             0x00000000
+#define MAC_RV_MRXD             0x00000000
+#define MAC_RV_TR               0x00000000
+#define MAC_RV_IS               0x00000000
+#define MAC_RV_NP               0x00000000
+#define MAC_RV_MCTL             0x00000000
+#define MAC_RV_MTXD             0x00000000
+#define MAC_RV_IA1              0x00000000
+#define MAC_RV_IACK             0x00000000
+#define MAC_RV_MADD             0x00000000
+
 #endif
 
 #endif // __HW_ETHERNET_H__

bsp/lm3s/Libraries/inc/hw_flash.h

@@ -2,26 +2,23 @@
 //
 // hw_flash.h - Macros used when accessing the flash controller.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,220 +30,232 @@
 // The following are defines for the FLASH register offsets.
 //
 //*****************************************************************************
-#define FLASH_FMA               0x400FD000  // Memory address register
-#define FLASH_FMD               0x400FD004  // Memory data register
-#define FLASH_FMC               0x400FD008  // Memory control register
-#define FLASH_FCRIS             0x400FD00C  // Raw interrupt status register
-#define FLASH_FCIM              0x400FD010  // Interrupt mask register
-#define FLASH_FCMISC            0x400FD014  // Interrupt status register
+#define FLASH_FMA               0x400FD000  // Flash Memory Address
+#define FLASH_FMD               0x400FD004  // Flash Memory Data
+#define FLASH_FMC               0x400FD008  // Flash Memory Control
+#define FLASH_FCRIS             0x400FD00C  // Flash Controller Raw Interrupt
+                                            // Status
+#define FLASH_FCIM              0x400FD010  // Flash Controller Interrupt Mask
+#define FLASH_FCMISC            0x400FD014  // Flash Controller Masked
+                                            // Interrupt Status and Clear
 #define FLASH_FMC2              0x400FD020  // Flash Memory Control 2
 #define FLASH_FWBVAL            0x400FD030  // Flash Write Buffer Valid
-#define FLASH_FWBN              0x400FD100  // Flash Write Buffer Register n
+#define FLASH_FCTL              0x400FD0F8  // Flash Control
+#define FLASH_FWBN              0x400FD100  // Flash Write Buffer n
 #define FLASH_RMCTL             0x400FE0F0  // ROM Control
 #define FLASH_RMVER             0x400FE0F4  // ROM Version Register
-#define FLASH_FMPRE             0x400FE130  // FLASH read protect register
-#define FLASH_FMPPE             0x400FE134  // FLASH program protect register
-#define FLASH_USECRL            0x400FE140  // uSec reload register
+#define FLASH_FMPRE             0x400FE130  // Flash Memory Protection Read
+                                            // Enable
+#define FLASH_FMPPE             0x400FE134  // Flash Memory Protection Program
+                                            // Enable
+#define FLASH_USECRL            0x400FE140  // USec Reload
 #define FLASH_USERDBG           0x400FE1D0  // User Debug
+#define FLASH_BOOTCFG           0x400FE1D0  // Boot Configuration
 #define FLASH_USERREG0          0x400FE1E0  // User Register 0
 #define FLASH_USERREG1          0x400FE1E4  // User Register 1
 #define FLASH_USERREG2          0x400FE1E8  // User Register 2
 #define FLASH_USERREG3          0x400FE1EC  // User Register 3
-#define FLASH_FMPRE0            0x400FE200  // FLASH read protect register 0
-#define FLASH_FMPRE1            0x400FE204  // FLASH read protect register 1
-#define FLASH_FMPRE2            0x400FE208  // FLASH read protect register 2
-#define FLASH_FMPRE3            0x400FE20C  // FLASH read protect register 3
-#define FLASH_FMPPE0            0x400FE400  // FLASH program protect register 0
-#define FLASH_FMPPE1            0x400FE404  // FLASH program protect register 1
-#define FLASH_FMPPE2            0x400FE408  // FLASH program protect register 2
-#define FLASH_FMPPE3            0x400FE40C  // FLASH program protect register 3
+#define FLASH_FMPRE0            0x400FE200  // Flash Memory Protection Read
+                                            // Enable 0
+#define FLASH_FMPRE1            0x400FE204  // Flash Memory Protection Read
+                                            // Enable 1
+#define FLASH_FMPRE2            0x400FE208  // Flash Memory Protection Read
+                                            // Enable 2
+#define FLASH_FMPRE3            0x400FE20C  // Flash Memory Protection Read
+                                            // Enable 3
+#define FLASH_FMPPE0            0x400FE400  // Flash Memory Protection Program
+                                            // Enable 0
+#define FLASH_FMPPE1            0x400FE404  // Flash Memory Protection Program
+                                            // Enable 1
+#define FLASH_FMPPE2            0x400FE408  // Flash Memory Protection Program
+                                            // Enable 2
+#define FLASH_FMPPE3            0x400FE40C  // Flash Memory Protection Program
+                                            // Enable 3
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMC register.
+// The following are defines for the bit fields in the FLASH_FMA register.
 //
 //*****************************************************************************
-#define FLASH_FMC_WRKEY_M       0xFFFF0000  // FLASH write key mask
-#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
-#define FLASH_FMC_COMT          0x00000008  // Commit user register
-#define FLASH_FMC_MERASE        0x00000004  // Mass erase FLASH
-#define FLASH_FMC_ERASE         0x00000002  // Erase FLASH page
-#define FLASH_FMC_WRITE         0x00000001  // Write FLASH word
-#define FLASH_FMC_WRKEY_S       16
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMC2 register.
+// The following are defines for the bit fields in the FLASH_FMD register.
 //
 //*****************************************************************************
-#define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
-#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Write.
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCRIS register.
 //
 //*****************************************************************************
-#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt
-                                            // Status.
-#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status.
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_FCIM register.
 //
 //*****************************************************************************
-#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask.
-#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask.
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMIS register.
+// The following are defines for the bit fields in the FLASH_FCMISC register.
 //
 //*****************************************************************************
 #define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
-                                            // Status and Clear.
+                                            // Status and Clear
 #define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
-                                            // and Clear.
+                                            // and Clear
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMPRE and
-// FLASH_FMPPE registers.
+// The following are defines for the bit fields in the FLASH_FMC2 register.
 //
 //*****************************************************************************
-#define FLASH_FMP_BLOCK_31      0x80000000  // Enable for block 31
-#define FLASH_FMP_BLOCK_30      0x40000000  // Enable for block 30
-#define FLASH_FMP_BLOCK_29      0x20000000  // Enable for block 29
-#define FLASH_FMP_BLOCK_28      0x10000000  // Enable for block 28
-#define FLASH_FMP_BLOCK_27      0x08000000  // Enable for block 27
-#define FLASH_FMP_BLOCK_26      0x04000000  // Enable for block 26
-#define FLASH_FMP_BLOCK_25      0x02000000  // Enable for block 25
-#define FLASH_FMP_BLOCK_24      0x01000000  // Enable for block 24
-#define FLASH_FMP_BLOCK_23      0x00800000  // Enable for block 23
-#define FLASH_FMP_BLOCK_22      0x00400000  // Enable for block 22
-#define FLASH_FMP_BLOCK_21      0x00200000  // Enable for block 21
-#define FLASH_FMP_BLOCK_20      0x00100000  // Enable for block 20
-#define FLASH_FMP_BLOCK_19      0x00080000  // Enable for block 19
-#define FLASH_FMP_BLOCK_18      0x00040000  // Enable for block 18
-#define FLASH_FMP_BLOCK_17      0x00020000  // Enable for block 17
-#define FLASH_FMP_BLOCK_16      0x00010000  // Enable for block 16
-#define FLASH_FMP_BLOCK_15      0x00008000  // Enable for block 15
-#define FLASH_FMP_BLOCK_14      0x00004000  // Enable for block 14
-#define FLASH_FMP_BLOCK_13      0x00002000  // Enable for block 13
-#define FLASH_FMP_BLOCK_12      0x00001000  // Enable for block 12
-#define FLASH_FMP_BLOCK_11      0x00000800  // Enable for block 11
-#define FLASH_FMP_BLOCK_10      0x00000400  // Enable for block 10
-#define FLASH_FMP_BLOCK_9       0x00000200  // Enable for block 9
-#define FLASH_FMP_BLOCK_8       0x00000100  // Enable for block 8
-#define FLASH_FMP_BLOCK_7       0x00000080  // Enable for block 7
-#define FLASH_FMP_BLOCK_6       0x00000040  // Enable for block 6
-#define FLASH_FMP_BLOCK_5       0x00000020  // Enable for block 5
-#define FLASH_FMP_BLOCK_4       0x00000010  // Enable for block 4
-#define FLASH_FMP_BLOCK_3       0x00000008  // Enable for block 3
-#define FLASH_FMP_BLOCK_2       0x00000004  // Enable for block 2
-#define FLASH_FMP_BLOCK_1       0x00000002  // Enable for block 1
-#define FLASH_FMP_BLOCK_0       0x00000001  // Enable for block 0
+#define FLASH_FMC2_WRKEY        0xA4420000  // FLASH write key
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_USECRL register.
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
 //
 //*****************************************************************************
-#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value.
-#define FLASH_USECRL_S          0
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
 
 //*****************************************************************************
 //
-// The following are defines for the erase size of the FLASH block that is
-// erased by an erase operation, and the protect size is the size of the FLASH
-// block that is protected by each protection register.
+// The following are defines for the bit fields in the FLASH_FCTL register.
 //
 //*****************************************************************************
-#define FLASH_PROTECT_SIZE      0x00000800
-#define FLASH_ERASE_SIZE        0x00000400
+#define FLASH_FCTL_USDACK       0x00000002  // User Shut Down Acknowledge
+#define FLASH_FCTL_USDREQ       0x00000001  // User Shut Down Request
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMA register.
+// The following are defines for the bit fields in the FLASH_FWBN register.
 //
 //*****************************************************************************
-#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset.
-#define FLASH_FMA_OFFSET_S      0
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FMD register.
+// The following are defines for the bit fields in the FLASH_RMCTL register.
 //
 //*****************************************************************************
-#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value.
-#define FLASH_FMD_DATA_S        0
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_USERDBG register.
+// The following are defines for the bit fields in the FLASH_RMVER register.
 //
 //*****************************************************************************
-#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written.
-#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data.
-#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1.
-#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0.
-#define FLASH_USERDBG_DATA_S    2
+#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents
+#define FLASH_RMVER_CONT_LM     0x00000000  // Stellaris Boot Loader &
+                                            // DriverLib
+#define FLASH_RMVER_CONT_LM_AES 0x02000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES
+#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
+                                0x03000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES and SAFERTOS
+#define FLASH_RMVER_CONT_LM_AES2 \
+                                0x05000000  // Stellaris Boot Loader &
+                                            // DriverLib with AES
+#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version
+#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision
+#define FLASH_RMVER_VER_S       8
+#define FLASH_RMVER_REV_S       0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_USERREG0 register.
+// The following are defines for the bit fields in the FLASH_USECRL register.
 //
 //*****************************************************************************
-#define FLASH_USERREG0_NW       0x80000000  // Not Written.
-#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data.
-#define FLASH_USERREG0_DATA_S   0
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value
+#define FLASH_USECRL_S          0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_USERREG1 register.
+// The following are defines for the bit fields in the FLASH_USERDBG register.
 //
 //*****************************************************************************
-#define FLASH_USERREG1_NW       0x80000000  // Not Written.
-#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data.
-#define FLASH_USERREG1_DATA_S   0
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
+#define FLASH_USERDBG_DATA_S    2
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_RMCTL register.
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
 //
 //*****************************************************************************
-#define FLASH_RMCTL_BA          0x00000001  // Boot Alias.
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_RMVER register.
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
 //
 //*****************************************************************************
-#define FLASH_RMVER_CONT_M      0xFF000000  // ROM Contents.
-#define FLASH_RMVER_CONT_LM     0x00000000  // Stellaris Boot Loader &
-                                            // DriverLib
-#define FLASH_RMVER_CONT_LM_AES 0x02000000  // Stellaris Boot Loader &
-                                            // DriverLib with AES
-#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
-                                0x03000000  // Stellaris Boot Loader &
-                                            // DriverLib with AES and SAFERTOS
-#define FLASH_RMVER_SIZE_M      0x00FF0000  // ROM Size.
-#define FLASH_RMVER_SIZE_11K    0x00000000  // 11KB Size
-#define FLASH_RMVER_SIZE_23_75K 0x00020000  // 23.75KB Size
-#define FLASH_RMVER_SIZE_28_25K 0x00030000  // 28.25KB Size
-#define FLASH_RMVER_VER_M       0x0000FF00  // ROM Version.
-#define FLASH_RMVER_REV_M       0x000000FF  // ROM Revision.
-#define FLASH_RMVER_VER_S       8
-#define FLASH_RMVER_REV_S       0
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the FLASH_USERREG2 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG2_NW       0x80000000  // Not Written.
-#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG2_NW       0x80000000  // Not Written
+#define FLASH_USERREG2_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG2_DATA_S   0
 
 //*****************************************************************************
@@ -254,23 +263,58 @@
 // The following are defines for the bit fields in the FLASH_USERREG3 register.
 //
 //*****************************************************************************
-#define FLASH_USERREG3_NW       0x80000000  // Not Written.
-#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data.
+#define FLASH_USERREG3_NW       0x80000000  // Not Written
+#define FLASH_USERREG3_DATA_M   0x7FFFFFFF  // User Data
 #define FLASH_USERREG3_DATA_S   0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FWBVAL register.
+// The following are defines for the bit fields in the FLASH_FMPRE and
+// FLASH_FMPPE registers.
 //
 //*****************************************************************************
-#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Write Buffer.
+#define FLASH_FMP_BLOCK_31      0x80000000  // Enable for block 31
+#define FLASH_FMP_BLOCK_30      0x40000000  // Enable for block 30
+#define FLASH_FMP_BLOCK_29      0x20000000  // Enable for block 29
+#define FLASH_FMP_BLOCK_28      0x10000000  // Enable for block 28
+#define FLASH_FMP_BLOCK_27      0x08000000  // Enable for block 27
+#define FLASH_FMP_BLOCK_26      0x04000000  // Enable for block 26
+#define FLASH_FMP_BLOCK_25      0x02000000  // Enable for block 25
+#define FLASH_FMP_BLOCK_24      0x01000000  // Enable for block 24
+#define FLASH_FMP_BLOCK_23      0x00800000  // Enable for block 23
+#define FLASH_FMP_BLOCK_22      0x00400000  // Enable for block 22
+#define FLASH_FMP_BLOCK_21      0x00200000  // Enable for block 21
+#define FLASH_FMP_BLOCK_20      0x00100000  // Enable for block 20
+#define FLASH_FMP_BLOCK_19      0x00080000  // Enable for block 19
+#define FLASH_FMP_BLOCK_18      0x00040000  // Enable for block 18
+#define FLASH_FMP_BLOCK_17      0x00020000  // Enable for block 17
+#define FLASH_FMP_BLOCK_16      0x00010000  // Enable for block 16
+#define FLASH_FMP_BLOCK_15      0x00008000  // Enable for block 15
+#define FLASH_FMP_BLOCK_14      0x00004000  // Enable for block 14
+#define FLASH_FMP_BLOCK_13      0x00002000  // Enable for block 13
+#define FLASH_FMP_BLOCK_12      0x00001000  // Enable for block 12
+#define FLASH_FMP_BLOCK_11      0x00000800  // Enable for block 11
+#define FLASH_FMP_BLOCK_10      0x00000400  // Enable for block 10
+#define FLASH_FMP_BLOCK_9       0x00000200  // Enable for block 9
+#define FLASH_FMP_BLOCK_8       0x00000100  // Enable for block 8
+#define FLASH_FMP_BLOCK_7       0x00000080  // Enable for block 7
+#define FLASH_FMP_BLOCK_6       0x00000040  // Enable for block 6
+#define FLASH_FMP_BLOCK_5       0x00000020  // Enable for block 5
+#define FLASH_FMP_BLOCK_4       0x00000010  // Enable for block 4
+#define FLASH_FMP_BLOCK_3       0x00000008  // Enable for block 3
+#define FLASH_FMP_BLOCK_2       0x00000004  // Enable for block 2
+#define FLASH_FMP_BLOCK_1       0x00000002  // Enable for block 1
+#define FLASH_FMP_BLOCK_0       0x00000001  // Enable for block 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the FLASH_FWBN register.
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
 //
 //*****************************************************************************
-#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data.
+#define FLASH_PROTECT_SIZE      0x00000800
+#define FLASH_ERASE_SIZE        0x00000400
 
 //*****************************************************************************
 //
@@ -286,6 +330,8 @@
 //
 //*****************************************************************************
 #define FLASH_FMC_WRKEY_MASK    0xFFFF0000  // FLASH write key mask
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
 
 //*****************************************************************************
 //
@@ -307,7 +353,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the FLASH_FMIS
+// The following are deprecated defines for the bit fields in the FLASH_FCMISC
 // register.
 //
 //*****************************************************************************

bsp/lm3s/Libraries/inc/hw_gpio.h

@@ -2,26 +2,23 @@
 //
 // hw_gpio.h - Defines and Macros for GPIO hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,44 +27,46 @@
 
 //*****************************************************************************
 //
-// The following are defines for the GPIO Register offsets.
+// The following are defines for the GPIO register offsets.
 //
 //*****************************************************************************
-#define GPIO_O_DATA             0x00000000  // Data register.
-#define GPIO_O_DIR              0x00000400  // Data direction register.
-#define GPIO_O_IS               0x00000404  // Interrupt sense register.
-#define GPIO_O_IBE              0x00000408  // Interrupt both edges register.
-#define GPIO_O_IEV              0x0000040C  // Interrupt event register.
-#define GPIO_O_IM               0x00000410  // Interrupt mask register.
-#define GPIO_O_RIS              0x00000414  // Raw interrupt status register.
-#define GPIO_O_MIS              0x00000418  // Masked interrupt status reg.
-#define GPIO_O_ICR              0x0000041C  // Interrupt clear register.
-#define GPIO_O_AFSEL            0x00000420  // Mode control select register.
-#define GPIO_O_DR2R             0x00000500  // 2ma drive select register.
-#define GPIO_O_DR4R             0x00000504  // 4ma drive select register.
-#define GPIO_O_DR8R             0x00000508  // 8ma drive select register.
-#define GPIO_O_ODR              0x0000050C  // Open drain select register.
-#define GPIO_O_PUR              0x00000510  // Pull up select register.
-#define GPIO_O_PDR              0x00000514  // Pull down select register.
-#define GPIO_O_SLR              0x00000518  // Slew rate control enable reg.
-#define GPIO_O_DEN              0x0000051C  // Digital input enable register.
-#define GPIO_O_LOCK             0x00000520  // Lock register.
-#define GPIO_O_CR               0x00000524  // Commit register.
+#define GPIO_O_DATA             0x00000000  // GPIO Data
+#define GPIO_O_DIR              0x00000400  // GPIO Direction
+#define GPIO_O_IS               0x00000404  // GPIO Interrupt Sense
+#define GPIO_O_IBE              0x00000408  // GPIO Interrupt Both Edges
+#define GPIO_O_IEV              0x0000040C  // GPIO Interrupt Event
+#define GPIO_O_IM               0x00000410  // GPIO Interrupt Mask
+#define GPIO_O_RIS              0x00000414  // GPIO Raw Interrupt Status
+#define GPIO_O_MIS              0x00000418  // GPIO Masked Interrupt Status
+#define GPIO_O_ICR              0x0000041C  // GPIO Interrupt Clear
+#define GPIO_O_AFSEL            0x00000420  // GPIO Alternate Function Select
+#define GPIO_O_DR2R             0x00000500  // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R             0x00000504  // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R             0x00000508  // GPIO 8-mA Drive Select
+#define GPIO_O_ODR              0x0000050C  // GPIO Open Drain Select
+#define GPIO_O_PUR              0x00000510  // GPIO Pull-Up Select
+#define GPIO_O_PDR              0x00000514  // GPIO Pull-Down Select
+#define GPIO_O_SLR              0x00000518  // GPIO Slew Rate Control Select
+#define GPIO_O_DEN              0x0000051C  // GPIO Digital Enable
+#define GPIO_O_LOCK             0x00000520  // GPIO Lock
+#define GPIO_O_CR               0x00000524  // GPIO Commit
 #define GPIO_O_AMSEL            0x00000528  // GPIO Analog Mode Select
 #define GPIO_O_PCTL             0x0000052C  // GPIO Port Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the GPIO_LOCK register.
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
 //
 //*****************************************************************************
-#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock.
-#define GPIO_LOCK_UNLOCKED      0x00000000  // GPIO_CR register is unlocked
-#define GPIO_LOCK_LOCKED        0x00000001  // GPIO_CR register is locked
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
 #define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
 #define GPIO_LOCK_KEY_DD        0x4C4F434B  // Unlocks the GPIO_CR register on
                                             // DustDevil-class devices and
-                                            // later.
+                                            // later
 
 //*****************************************************************************
 //
@@ -535,7 +534,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the GPIO Register offsets.
+// The following are deprecated defines for the GPIO register offsets.
 //
 //*****************************************************************************
 #define GPIO_O_PeriphID4        0x00000FD0
@@ -556,9 +555,9 @@
 // The following are deprecated defines for the GPIO Register reset values.
 //
 //*****************************************************************************
-#define GPIO_RV_DEN             0x000000FF  // Digital input enable reg RV.
-#define GPIO_RV_PUR             0x000000FF  // Pull up select reg RV.
-#define GPIO_RV_DR2R            0x000000FF  // 2ma drive select reg RV.
+#define GPIO_RV_DEN             0x000000FF  // Digital input enable reg RV
+#define GPIO_RV_PUR             0x000000FF  // Pull up select reg RV
+#define GPIO_RV_DR2R            0x000000FF  // 2ma drive select reg RV
 #define GPIO_RV_PCellID1        0x000000F0
 #define GPIO_RV_PCellID3        0x000000B1
 #define GPIO_RV_PeriphID0       0x00000061
@@ -566,27 +565,27 @@
 #define GPIO_RV_PCellID0        0x0000000D
 #define GPIO_RV_PCellID2        0x00000005
 #define GPIO_RV_PeriphID2       0x00000004
-#define GPIO_RV_LOCK            0x00000001  // Lock register RV.
+#define GPIO_RV_LOCK            0x00000001  // Lock register RV
 #define GPIO_RV_PeriphID7       0x00000000
-#define GPIO_RV_PDR             0x00000000  // Pull down select reg RV.
-#define GPIO_RV_IC              0x00000000  // Interrupt clear reg RV.
-#define GPIO_RV_SLR             0x00000000  // Slew rate control enable reg RV.
-#define GPIO_RV_ODR             0x00000000  // Open drain select reg RV.
-#define GPIO_RV_IBE             0x00000000  // Interrupt both edges reg RV.
-#define GPIO_RV_AFSEL           0x00000000  // Mode control select reg RV.
-#define GPIO_RV_IS              0x00000000  // Interrupt sense reg RV.
-#define GPIO_RV_IM              0x00000000  // Interrupt mask reg RV.
+#define GPIO_RV_PDR             0x00000000  // Pull down select reg RV
+#define GPIO_RV_IC              0x00000000  // Interrupt clear reg RV
+#define GPIO_RV_SLR             0x00000000  // Slew rate control enable reg RV
+#define GPIO_RV_ODR             0x00000000  // Open drain select reg RV
+#define GPIO_RV_IBE             0x00000000  // Interrupt both edges reg RV
+#define GPIO_RV_AFSEL           0x00000000  // Mode control select reg RV
+#define GPIO_RV_IS              0x00000000  // Interrupt sense reg RV
+#define GPIO_RV_IM              0x00000000  // Interrupt mask reg RV
 #define GPIO_RV_PeriphID4       0x00000000
 #define GPIO_RV_PeriphID5       0x00000000
-#define GPIO_RV_DR8R            0x00000000  // 8ma drive select reg RV.
-#define GPIO_RV_RIS             0x00000000  // Raw interrupt status reg RV.
-#define GPIO_RV_DR4R            0x00000000  // 4ma drive select reg RV.
-#define GPIO_RV_IEV             0x00000000  // Intterupt event reg RV.
-#define GPIO_RV_DIR             0x00000000  // Data direction reg RV.
+#define GPIO_RV_DR8R            0x00000000  // 8ma drive select reg RV
+#define GPIO_RV_RIS             0x00000000  // Raw interrupt status reg RV
+#define GPIO_RV_DR4R            0x00000000  // 4ma drive select reg RV
+#define GPIO_RV_IEV             0x00000000  // Intterupt event reg RV
+#define GPIO_RV_DIR             0x00000000  // Data direction reg RV
 #define GPIO_RV_PeriphID6       0x00000000
 #define GPIO_RV_PeriphID3       0x00000000
-#define GPIO_RV_DATA            0x00000000  // Data register reset value.
-#define GPIO_RV_MIS             0x00000000  // Masked interrupt status reg RV.
+#define GPIO_RV_DATA            0x00000000  // Data register reset value
+#define GPIO_RV_MIS             0x00000000  // Masked interrupt status reg RV
 
 #endif
 

bsp/lm3s/Libraries/inc/hw_hibernate.h

@@ -2,26 +2,23 @@
 //
 // hw_hibernate.h - Defines and Macros for the Hibernation module.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,132 +30,132 @@
 // The following are defines for the Hibernation module register addresses.
 //
 //*****************************************************************************
-#define HIB_RTCC                0x400FC000  // Hibernate RTC counter
-#define HIB_RTCM0               0x400FC004  // Hibernate RTC match 0
-#define HIB_RTCM1               0x400FC008  // Hibernate RTC match 1
-#define HIB_RTCLD               0x400FC00C  // Hibernate RTC load
-#define HIB_CTL                 0x400FC010  // Hibernate RTC control
-#define HIB_IM                  0x400FC014  // Hibernate interrupt mask
-#define HIB_RIS                 0x400FC018  // Hibernate raw interrupt status
-#define HIB_MIS                 0x400FC01C  // Hibernate masked interrupt stat
-#define HIB_IC                  0x400FC020  // Hibernate interrupt clear
-#define HIB_RTCT                0x400FC024  // Hibernate RTC trim
-#define HIB_DATA                0x400FC030  // Hibernate data area
+#define HIB_RTCC                0x400FC000  // Hibernation RTC Counter
+#define HIB_RTCM0               0x400FC004  // Hibernation RTC Match 0
+#define HIB_RTCM1               0x400FC008  // Hibernation RTC Match 1
+#define HIB_RTCLD               0x400FC00C  // Hibernation RTC Load
+#define HIB_CTL                 0x400FC010  // Hibernation Control
+#define HIB_IM                  0x400FC014  // Hibernation Interrupt Mask
+#define HIB_RIS                 0x400FC018  // Hibernation Raw Interrupt Status
+#define HIB_MIS                 0x400FC01C  // Hibernation Masked Interrupt
+                                            // Status
+#define HIB_IC                  0x400FC020  // Hibernation Interrupt Clear
+#define HIB_RTCT                0x400FC024  // Hibernation RTC Trim
+#define HIB_DATA                0x400FC030  // Hibernation Data
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC counter
-// register.
+// The following are defines for the bit fields in the HIB_RTCC register.
 //
 //*****************************************************************************
-#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter.
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
 #define HIB_RTCC_S              0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC match 0
-// register.
+// The following are defines for the bit fields in the HIB_RTCM0 register.
 //
 //*****************************************************************************
-#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0.
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
 #define HIB_RTCM0_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC match 1
-// register.
+// The following are defines for the bit fields in the HIB_RTCM1 register.
 //
 //*****************************************************************************
-#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1.
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1
 #define HIB_RTCM1_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC load
-// register.
+// The following are defines for the bit fields in the HIB_RTCLD register.
 //
 //*****************************************************************************
-#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load.
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
 #define HIB_RTCLD_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate control
-// register
+// The following are defines for the bit fields in the HIB_CTL register.
 //
 //*****************************************************************************
-#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable.
-#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered.
-#define HIB_CTL_VABORT          0x00000080  // low bat abort
-#define HIB_CTL_CLK32EN         0x00000040  // enable clock/oscillator
-#define HIB_CTL_LOWBATEN        0x00000020  // enable low battery detect
-#define HIB_CTL_PINWEN          0x00000010  // enable wake on WAKE pin
-#define HIB_CTL_RTCWEN          0x00000008  // enable wake on RTC match
-#define HIB_CTL_CLKSEL          0x00000004  // clock input selection
-#define HIB_CTL_HIBREQ          0x00000002  // request hibernation
-#define HIB_CTL_RTCEN           0x00000001  // RTC enable
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable
+#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate interrupt mask
-// reg.
+// The following are defines for the bit fields in the HIB_IM register.
 //
 //*****************************************************************************
-#define HIB_IM_EXTW             0x00000008  // wake from external pin interrupt
-#define HIB_IM_LOWBAT           0x00000004  // low battery interrupt
-#define HIB_IM_RTCALT1          0x00000002  // RTC match 1 interrupt
-#define HIB_IM_RTCALT0          0x00000001  // RTC match 0 interrupt
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT1          0x00000002  // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate raw interrupt
-// status.
+// The following are defines for the bit fields in the HIB_RIS register.
 //
 //*****************************************************************************
-#define HIB_RIS_EXTW            0x00000008  // wake from external pin interrupt
-#define HIB_RIS_LOWBAT          0x00000004  // low battery interrupt
-#define HIB_RIS_RTCALT1         0x00000002  // RTC match 1 interrupt
-#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert0 Raw Interrupt Status.
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate masked int
-// status.
+// The following are defines for the bit fields in the HIB_MIS register.
 //
 //*****************************************************************************
-#define HIB_MIS_EXTW            0x00000008  // wake from external pin interrupt
-#define HIB_MIS_LOWBAT          0x00000004  // low battery interrupt
-#define HIB_MIS_RTCALT1         0x00000002  // RTC match 1 interrupt
-#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert0 Masked Interrupt
-                                            // Status.
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert 1 Masked Interrupt
+                                            // Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate interrupt
-// clear reg.
+// The following are defines for the bit fields in the HIB_IC register.
 //
 //*****************************************************************************
-#define HIB_IC_EXTW             0x00000008  // wake from external pin interrupt
-#define HIB_IC_LOWBAT           0x00000004  // low battery interrupt
-#define HIB_IC_RTCALT1          0x00000002  // RTC match 1 interrupt
-#define HIB_IC_RTCALT0          0x00000001  // RTC match 0 interrupt
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Masked
+                                            // Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Clear
+#define HIB_IC_RTCALT1          0x00000002  // RTC Alert1 Masked Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate RTC trim
-// register.
+// The following are defines for the bit fields in the HIB_RTCT register.
 //
 //*****************************************************************************
-#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value.
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
 #define HIB_RTCT_TRIM_S         0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the Hibernate data register.
+// The following are defines for the bit fields in the HIB_DATA register.
 //
 //*****************************************************************************
-#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV
-                                            // Registers[63:0].
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
 #define HIB_DATA_RTD_S          0
 
 //*****************************************************************************
@@ -178,64 +175,64 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// counter register.
+// The following are deprecated defines for the bit fields in the HIB_RTCC
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCC_MASK           0xFFFFFFFF  // RTC counter mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// match 0 register.
+// The following are deprecated defines for the bit fields in the HIB_RTCM0
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCM0_MASK          0xFFFFFFFF  // RTC match 0 mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// match 1 register.
+// The following are deprecated defines for the bit fields in the HIB_RTCM1
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCM1_MASK          0xFFFFFFFF  // RTC match 1 mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// load register.
+// The following are deprecated defines for the bit fields in the HIB_RTCLD
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCLD_MASK          0xFFFFFFFF  // RTC load mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate raw
-// interrupt status.
+// The following are deprecated defines for the bit fields in the HIB_RIS
+// register.
 //
 //*****************************************************************************
 #define HIB_RID_RTCALT0         0x00000001  // RTC match 0 interrupt
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate
-// masked int status.
+// The following are deprecated defines for the bit fields in the HIB_MIS
+// register.
 //
 //*****************************************************************************
 #define HIB_MID_RTCALT0         0x00000001  // RTC match 0 interrupt
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate RTC
-// trim register.
+// The following are deprecated defines for the bit fields in the HIB_RTCT
+// register.
 //
 //*****************************************************************************
 #define HIB_RTCT_MASK           0x0000FFFF  // RTC trim mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the Hibernate
-// data register.
+// The following are deprecated defines for the bit fields in the HIB_DATA
+// register.
 //
 //*****************************************************************************
 #define HIB_DATA_MASK           0xFFFFFFFF  // NV memory data mask

bsp/lm3s/Libraries/inc/hw_i2c.h

@@ -2,26 +2,23 @@
 //
 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,8 +27,7 @@
 
 //*****************************************************************************
 //
-// The following are defines for the offsets between the I2C master and slave
-// registers.
+// The following are defines for the I2C register offsets.
 //
 //*****************************************************************************
 #define I2C_O_MSA               0x00000000  // I2C Master Slave Address
@@ -58,8 +54,8 @@
 // The following are defines for the bit fields in the I2C_O_MSA register.
 //
 //*****************************************************************************
-#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address.
-#define I2C_MSA_RS              0x00000001  // Receive not Send
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
 #define I2C_MSA_SA_S            1
 
 //*****************************************************************************
@@ -67,7 +63,7 @@
 // The following are defines for the bit fields in the I2C_O_SOAR register.
 //
 //*****************************************************************************
-#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address.
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
 #define I2C_SOAR_OAR_S          0
 
 //*****************************************************************************
@@ -75,34 +71,34 @@
 // The following are defines for the bit fields in the I2C_O_SCSR register.
 //
 //*****************************************************************************
-#define I2C_SCSR_FBR            0x00000004  // First Byte Received.
-#define I2C_SCSR_TREQ           0x00000002  // Transmit Request.
-#define I2C_SCSR_DA             0x00000001  // Device Active.
-#define I2C_SCSR_RREQ           0x00000001  // Receive Request.
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCS register.
 //
 //*****************************************************************************
-#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy.
-#define I2C_MCS_IDLE            0x00000020  // I2C Idle.
-#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost.
-#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable.
-#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data.
-#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address.
-#define I2C_MCS_STOP            0x00000004  // Generate STOP.
-#define I2C_MCS_START           0x00000002  // Generate START.
-#define I2C_MCS_ERROR           0x00000002  // Error.
-#define I2C_MCS_RUN             0x00000001  // I2C Master Enable.
-#define I2C_MCS_BUSY            0x00000001  // I2C Busy.
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SDR register.
 //
 //*****************************************************************************
-#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer.
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
 #define I2C_SDR_DATA_S          0
 
 //*****************************************************************************
@@ -110,7 +106,7 @@
 // The following are defines for the bit fields in the I2C_O_MDR register.
 //
 //*****************************************************************************
-#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred.
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
 #define I2C_MDR_DATA_S          0
 
 //*****************************************************************************
@@ -118,7 +114,7 @@
 // The following are defines for the bit fields in the I2C_O_MTPR register.
 //
 //*****************************************************************************
-#define I2C_MTPR_TPR_M          0x000000FF  // SCL Clock Period.
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
 #define I2C_MTPR_TPR_S          0
 
 //*****************************************************************************
@@ -126,9 +122,9 @@
 // The following are defines for the bit fields in the I2C_O_SIMR register.
 //
 //*****************************************************************************
-#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask.
-#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask.
-#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask.
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
 
 //*****************************************************************************
 //
@@ -136,24 +132,24 @@
 //
 //*****************************************************************************
 #define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
-                                            // Status.
+                                            // Status
 #define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
-                                            // Status.
-#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status.
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MIMR register.
 //
 //*****************************************************************************
-#define I2C_MIMR_IM             0x00000001  // Interrupt Mask.
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MRIS register.
 //
 //*****************************************************************************
-#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status.
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
 
 //*****************************************************************************
 //
@@ -161,42 +157,42 @@
 //
 //*****************************************************************************
 #define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
-                                            // Status.
+                                            // Status
 #define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
-                                            // Status.
-#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status.
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_SICR register.
 //
 //*****************************************************************************
-#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear.
-#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear.
-#define I2C_SICR_DATAIC         0x00000001  // Data Clear Interrupt.
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MMIS register.
 //
 //*****************************************************************************
-#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status.
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MICR register.
 //
 //*****************************************************************************
-#define I2C_MICR_IC             0x00000001  // Interrupt Clear.
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2C_O_MCR register.
 //
 //*****************************************************************************
-#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable.
-#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable.
-#define I2C_MCR_LPBK            0x00000001  // I2C Loopback.
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
 
 //*****************************************************************************
 //
@@ -207,12 +203,43 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the offsets between the I2C master
-// and slave registers.
+// The following are deprecated defines for the I2C register offsets.
 //
 //*****************************************************************************
 #define I2C_O_SLAVE             0x00000800  // Offset from master to slave
 
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR
+// register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SICR
+// register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt
+
 //*****************************************************************************
 //
 // The following are deprecated defines for the I2C master register offsets.
@@ -375,38 +402,6 @@
 //*****************************************************************************
 #define I2C_SLAVE_SICR_IC       0x00000001  // Slave interrupt clear
 
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SIMR
-// register.
-//
-//*****************************************************************************
-#define I2C_SIMR_IM             0x00000001  // Interrupt Mask.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SRIS
-// register.
-//
-//*****************************************************************************
-#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SMIS
-// register.
-//
-//*****************************************************************************
-#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status.
-
-//*****************************************************************************
-//
-// The following are deprecated defines for the bit fields in the I2C_O_SICR
-// register.
-//
-//*****************************************************************************
-#define I2C_SICR_IC             0x00000001  // Clear Interrupt.
-
 #endif
 
 #endif // __HW_I2C_H__

bsp/lm3s/Libraries/inc/hw_i2s.h

@@ -2,26 +2,23 @@
 //
 // hw_i2s.h - Macros for use in accessing the I2S registers.
 //
-// Copyright (c) 2008-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2008-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,8 +27,8 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Inter-Integrated Circuit Sound (I2S)
-// Interface
+// The following are defines for the Inter-Integrated Circuit Sound register
+// offsets.
 //
 //*****************************************************************************
 #define I2S_O_TXFIFO            0x00000000  // I2S Transmit FIFO Data
@@ -60,7 +57,7 @@
 // The following are defines for the bit fields in the I2S_O_TXFIFO register.
 //
 //*****************************************************************************
-#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data.
+#define I2S_TXFIFO_M            0xFFFFFFFF  // TX Data
 #define I2S_TXFIFO_S            0
 
 //*****************************************************************************
@@ -69,26 +66,26 @@
 // register.
 //
 //*****************************************************************************
-#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size.
-#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator.
+#define I2S_TXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_TXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXCFG register.
 //
 //*****************************************************************************
-#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data.
-#define I2S_TXCFG_DLY           0x10000000  // Data Delay.
-#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity.
-#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity.
-#define I2S_TXCFG_WM_M          0x03000000  // Write Mode.
+#define I2S_TXCFG_JST           0x20000000  // Justification of Output Data
+#define I2S_TXCFG_DLY           0x10000000  // Data Delay
+#define I2S_TXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_TXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_TXCFG_WM_M          0x03000000  // Write Mode
 #define I2S_TXCFG_WM_DUAL       0x00000000  // Stereo mode
 #define I2S_TXCFG_WM_COMPACT    0x01000000  // Compact Stereo mode
 #define I2S_TXCFG_WM_MONO       0x02000000  // Mono mode
-#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty.
-#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave.
-#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size.
-#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size.
+#define I2S_TXCFG_FMT           0x00800000  // FIFO Empty
+#define I2S_TXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_TXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_TXCFG_SDSZ_M        0x000003F0  // System Data Size
 #define I2S_TXCFG_SSZ_S         10
 #define I2S_TXCFG_SDSZ_S        4
 
@@ -97,7 +94,7 @@
 // The following are defines for the bit fields in the I2S_O_TXLIMIT register.
 //
 //*****************************************************************************
-#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit.
+#define I2S_TXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
 #define I2S_TXLIMIT_LIMIT_S     0
 
 //*****************************************************************************
@@ -106,15 +103,15 @@
 //
 //*****************************************************************************
 #define I2S_TXISM_FFI           0x00010000  // Transmit FIFO Service Request
-                                            // Interrupt.
-#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask.
+                                            // Interrupt
+#define I2S_TXISM_FFM           0x00000001  // FIFO Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_TXLEV register.
 //
 //*****************************************************************************
-#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples.
+#define I2S_TXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
 #define I2S_TXLEV_LEVEL_S       0
 
 //*****************************************************************************
@@ -122,7 +119,7 @@
 // The following are defines for the bit fields in the I2S_O_RXFIFO register.
 //
 //*****************************************************************************
-#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data.
+#define I2S_RXFIFO_M            0xFFFFFFFF  // RX Data
 #define I2S_RXFIFO_S            0
 
 //*****************************************************************************
@@ -131,23 +128,23 @@
 // register.
 //
 //*****************************************************************************
-#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode.
-#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size.
-#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator.
+#define I2S_RXFIFOCFG_FMM       0x00000004  // FIFO Mono Mode
+#define I2S_RXFIFOCFG_CSS       0x00000002  // Compact Stereo Sample Size
+#define I2S_RXFIFOCFG_LRS       0x00000001  // Left-Right Sample Indicator
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RXCFG register.
 //
 //*****************************************************************************
-#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data.
-#define I2S_RXCFG_DLY           0x10000000  // Data Delay.
-#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity.
-#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity.
-#define I2S_RXCFG_RM            0x01000000  // Read Mode.
-#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave.
-#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size.
-#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size.
+#define I2S_RXCFG_JST           0x20000000  // Justification of Input Data
+#define I2S_RXCFG_DLY           0x10000000  // Data Delay
+#define I2S_RXCFG_SCP           0x08000000  // SCLK Polarity
+#define I2S_RXCFG_LRP           0x04000000  // Left/Right Clock Polarity
+#define I2S_RXCFG_RM            0x01000000  // Read Mode
+#define I2S_RXCFG_MSL           0x00400000  // SCLK Master/Slave
+#define I2S_RXCFG_SSZ_M         0x0000FC00  // Sample Size
+#define I2S_RXCFG_SDSZ_M        0x000003F0  // System Data Size
 #define I2S_RXCFG_SSZ_S         10
 #define I2S_RXCFG_SDSZ_S        4
 
@@ -156,7 +153,7 @@
 // The following are defines for the bit fields in the I2S_O_RXLIMIT register.
 //
 //*****************************************************************************
-#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit.
+#define I2S_RXLIMIT_LIMIT_M     0x0000001F  // FIFO Limit
 #define I2S_RXLIMIT_LIMIT_S     0
 
 //*****************************************************************************
@@ -165,15 +162,15 @@
 //
 //*****************************************************************************
 #define I2S_RXISM_FFI           0x00010000  // Receive FIFO Service Request
-                                            // Interrupt.
-#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask.
+                                            // Interrupt
+#define I2S_RXISM_FFM           0x00000001  // FIFO Interrupt Mask
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RXLEV register.
 //
 //*****************************************************************************
-#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples.
+#define I2S_RXLEV_LEVEL_M       0x0000001F  // Number of Audio Samples
 #define I2S_RXLEV_LEVEL_S       0
 
 //*****************************************************************************
@@ -181,53 +178,47 @@
 // The following are defines for the bit fields in the I2S_O_CFG register.
 //
 //*****************************************************************************
-#define I2S_CFG_RXSLV           0x00000020  // When clear, this bit configures
-                                            // the receiver to use the
-                                            // externally driven I2S0RXMCLK
-                                            // signal.
-#define I2S_CFG_TXSLV           0x00000010  // When clear, this bit configures
-                                            // the transmitter to use the
-                                            // externally driven I2S0TXMCLK
-                                            // signal.
-#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable.
-#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable.
+#define I2S_CFG_RXSLV           0x00000020  // Use External I2S0RXMCLK
+#define I2S_CFG_TXSLV           0x00000010  // Use External I2S0TXMCLK
+#define I2S_CFG_RXEN            0x00000002  // Serial Receive Engine Enable
+#define I2S_CFG_TXEN            0x00000001  // Serial Transmit Engine Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_IM register.
 //
 //*****************************************************************************
-#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error.
-#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request.
-#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error.
-#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request.
+#define I2S_IM_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IM_RXFSR            0x00000010  // Receive FIFO Service Request
+#define I2S_IM_TXWE             0x00000002  // Transmit FIFO Write Error
+#define I2S_IM_TXFSR            0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_RIS register.
 //
 //*****************************************************************************
-#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error.
-#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request.
-#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error.
-#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request.
+#define I2S_RIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_RIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_RIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_RIS_TXFSR           0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_MIS register.
 //
 //*****************************************************************************
-#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error.
-#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request.
-#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error.
-#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request.
+#define I2S_MIS_RXRE            0x00000020  // Receive FIFO Read Error
+#define I2S_MIS_RXFSR           0x00000010  // Receive FIFO Service Request
+#define I2S_MIS_TXWE            0x00000002  // Transmit FIFO Write Error
+#define I2S_MIS_TXFSR           0x00000001  // Transmit FIFO Service Request
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the I2S_O_IC register.
 //
 //*****************************************************************************
-#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error.
-#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error.
+#define I2S_IC_RXRE             0x00000020  // Receive FIFO Read Error
+#define I2S_IC_TXWE             0x00000002  // Transmit FIFO Write Error
 
 #endif // __HW_I2S_H__

bsp/lm3s/Libraries/inc/hw_ints.h

@@ -2,26 +2,23 @@
 //
 // hw_ints.h - Macros that define the interrupt assignment on Stellaris.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -62,10 +59,10 @@
 #define INT_PWM1                27          // PWM Generator 1
 #define INT_PWM2                28          // PWM Generator 2
 #define INT_QEI0                29          // Quadrature Encoder 0
-#define INT_ADC0                30          // ADC Sequence 0
-#define INT_ADC1                31          // ADC Sequence 1
-#define INT_ADC2                32          // ADC Sequence 2
-#define INT_ADC3                33          // ADC Sequence 3
+#define INT_ADC0SS0             30          // ADC0 Sequence 0
+#define INT_ADC0SS1             31          // ADC0 Sequence 1
+#define INT_ADC0SS2             32          // ADC0 Sequence 2
+#define INT_ADC0SS3             33          // ADC0 Sequence 3
 #define INT_WATCHDOG            34          // Watchdog timer
 #define INT_TIMER0A             35          // Timer 0 subtimer A
 #define INT_TIMER0B             36          // Timer 0 subtimer B
@@ -109,7 +106,7 @@
 // The following are defines for the total number of interrupts.
 //
 //*****************************************************************************
-#define NUM_INTERRUPTS          70
+#define NUM_INTERRUPTS          71
 
 //*****************************************************************************
 //
@@ -134,6 +131,10 @@
 #define INT_SSI                 23          // SSI Rx and Tx
 #define INT_I2C                 24          // I2C Master and Slave
 #define INT_QEI                 29          // Quadrature Encoder
+#define INT_ADC0                30          // ADC Sequence 0
+#define INT_ADC1                31          // ADC Sequence 1
+#define INT_ADC2                32          // ADC Sequence 2
+#define INT_ADC3                33          // ADC Sequence 3
 
 #endif
 

bsp/lm3s/Libraries/inc/hw_memmap.h

@@ -2,26 +2,23 @@
 //
 // hw_memmap.h - Macros defining the memory map of Stellaris.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 

bsp/lm3s/Libraries/inc/hw_nvic.h

@@ -2,26 +2,23 @@
 //
 // hw_nvic.h - Macros used when accessing the NVIC hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,19 +30,19 @@
 // The following are defines for the NVIC register addresses.
 //
 //*****************************************************************************
-#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg.
-#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status Reg.
+#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg
+#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status Reg
 #define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register
 #define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register
-#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg.
+#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg
 #define NVIC_EN0                0xE000E100  // IRQ 0 to 31 Set Enable Register
 #define NVIC_EN1                0xE000E104  // IRQ 32 to 63 Set Enable Register
-#define NVIC_DIS0               0xE000E180  // IRQ 0 to 31 Clear Enable Reg.
-#define NVIC_DIS1               0xE000E184  // IRQ 32 to 63 Clear Enable Reg.
+#define NVIC_DIS0               0xE000E180  // IRQ 0 to 31 Clear Enable Reg
+#define NVIC_DIS1               0xE000E184  // IRQ 32 to 63 Clear Enable Reg
 #define NVIC_PEND0              0xE000E200  // IRQ 0 to 31 Set Pending Register
-#define NVIC_PEND1              0xE000E204  // IRQ 32 to 63 Set Pending Reg.
-#define NVIC_UNPEND0            0xE000E280  // IRQ 0 to 31 Clear Pending Reg.
-#define NVIC_UNPEND1            0xE000E284  // IRQ 32 to 63 Clear Pending Reg.
+#define NVIC_PEND1              0xE000E204  // IRQ 32 to 63 Set Pending Reg
+#define NVIC_UNPEND0            0xE000E280  // IRQ 0 to 31 Clear Pending Reg
+#define NVIC_UNPEND1            0xE000E284  // IRQ 32 to 63 Clear Pending Reg
 #define NVIC_ACTIVE0            0xE000E300  // IRQ 0 to 31 Active Register
 #define NVIC_ACTIVE1            0xE000E304  // IRQ 32 to 63 Active Register
 #define NVIC_PRI0               0xE000E400  // IRQ 0 to 3 Priority Register
@@ -65,14 +62,14 @@
 #define NVIC_CPUID              0xE000ED00  // CPUID Base Register
 #define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control State Register
 #define NVIC_VTABLE             0xE000ED08  // Vector Table Offset Register
-#define NVIC_APINT              0xE000ED0C  // App. Int & Reset Control Reg.
+#define NVIC_APINT              0xE000ED0C  // App. Int & Reset Control Reg
 #define NVIC_SYS_CTRL           0xE000ED10  // System Control Register
 #define NVIC_CFG_CTRL           0xE000ED14  // Configuration Control Register
 #define NVIC_SYS_PRI1           0xE000ED18  // Sys. Handlers 4 to 7 Priority
 #define NVIC_SYS_PRI2           0xE000ED1C  // Sys. Handlers 8 to 11 Priority
 #define NVIC_SYS_PRI3           0xE000ED20  // Sys. Handlers 12 to 15 Priority
 #define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State
-#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status Reg.
+#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status Reg
 #define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status Register
 #define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register
 #define NVIC_MM_ADDR            0xE000ED34  // Mem Manage Address Register
@@ -81,12 +78,12 @@
 #define NVIC_MPU_CTRL           0xE000ED94  // MPU Control Register
 #define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number Register
 #define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address Register
-#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute & Size Reg.
-#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg.
+#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute & Size Reg
+#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg
 #define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select
 #define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data
 #define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control
-#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt Reg.
+#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt Reg
 
 //*****************************************************************************
 //
@@ -665,6 +662,8 @@
 #define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
 #define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // Set pending SysTick interrupt
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // Clear pending SysTick interrupt
 #define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
 #define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
 #define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
@@ -691,17 +690,17 @@
 #define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
 #define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
 #define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
 #define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
 #define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
 #define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
 #define NVIC_APINT_VECT_RESET   0x00000001  // System reset
-#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
 
 //*****************************************************************************
 //
@@ -969,27 +968,27 @@
 //*****************************************************************************
 #define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
-#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
-#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
-#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
-#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
-#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
-#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
-#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
-#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
-#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
-#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
-#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
-#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
-#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
-#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
-#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
-#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
-#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
 #define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/inc/hw_pwm.h

@@ -1,27 +1,24 @@
 //*****************************************************************************
 //
-// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,19 +27,20 @@
 
 //*****************************************************************************
 //
-// The following are defines for the PWM Module Register offsets.
+// The following are defines for the PWM register offsets.
 //
 //*****************************************************************************
-#define PWM_O_CTL               0x00000000  // PWM Master Control register
-#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync register
-#define PWM_O_ENABLE            0x00000008  // PWM Output Enable register
-#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion register
-#define PWM_O_FAULT             0x00000010  // PWM Output Fault register
-#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable register
-#define PWM_O_RIS               0x00000018  // PWM Interrupt Raw Status reg.
-#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status register
-#define PWM_O_STATUS            0x00000020  // PWM Status register
+#define PWM_O_CTL               0x00000000  // PWM Master Control
+#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync
+#define PWM_O_ENABLE            0x00000008  // PWM Output Enable
+#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion
+#define PWM_O_FAULT             0x00000010  // PWM Output Fault
+#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable
+#define PWM_O_RIS               0x00000018  // PWM Raw Interrupt Status
+#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status and Clear
+#define PWM_O_STATUS            0x00000020  // PWM Status
 #define PWM_O_FAULTVAL          0x00000024  // PWM Fault Condition Value
+#define PWM_O_ENUPD             0x00000028  // PWM Enable Update
 #define PWM_O_0_CTL             0x00000040  // PWM0 Control
 #define PWM_O_0_INTEN           0x00000044  // PWM0 Interrupt and Trigger
                                             // Enable
@@ -62,7 +60,8 @@
 #define PWM_O_0_FLTSRC1         0x00000078  // PWM0 Fault Source 1
 #define PWM_O_0_MINFLTPER       0x0000007C  // PWM0 Minimum Fault Period
 #define PWM_O_1_CTL             0x00000080  // PWM1 Control
-#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt Enable
+#define PWM_O_1_INTEN           0x00000084  // PWM1 Interrupt and Trigger
+                                            // Enable
 #define PWM_O_1_RIS             0x00000088  // PWM1 Raw Interrupt Status
 #define PWM_O_1_ISC             0x0000008C  // PWM1 Interrupt Status and Clear
 #define PWM_O_1_LOAD            0x00000090  // PWM1 Load
@@ -79,7 +78,8 @@
 #define PWM_O_1_FLTSRC1         0x000000B8  // PWM1 Fault Source 1
 #define PWM_O_1_MINFLTPER       0x000000BC  // PWM1 Minimum Fault Period
 #define PWM_O_2_CTL             0x000000C0  // PWM2 Control
-#define PWM_O_2_INTEN           0x000000C4  // PWM2 InterruptEnable
+#define PWM_O_2_INTEN           0x000000C4  // PWM2 Interrupt and Trigger
+                                            // Enable
 #define PWM_O_2_RIS             0x000000C8  // PWM2 Raw Interrupt Status
 #define PWM_O_2_ISC             0x000000CC  // PWM2 Interrupt Status and Clear
 #define PWM_O_2_LOAD            0x000000D0  // PWM2 Load
@@ -128,249 +128,264 @@
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Master Control
-// register.
+// The following are defines for the bit fields in the PWM_O_CTL register.
 //
 //*****************************************************************************
-#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3.
-#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2.
-#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1.
-#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0.
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Time Base Sync
-// register.
+// The following are defines for the bit fields in the PWM_O_SYNC register.
 //
 //*****************************************************************************
-#define PWM_SYNC_SYNC3          0x00000008  // Reset generator 3 counter
-#define PWM_SYNC_SYNC2          0x00000004  // Reset generator 2 counter
-#define PWM_SYNC_SYNC1          0x00000002  // Reset generator 1 counter
-#define PWM_SYNC_SYNC0          0x00000001  // Reset generator 0 counter
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Output Enable
-// register.
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
 //
 //*****************************************************************************
-#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 pin enable
-#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 pin enable
-#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 pin enable
-#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 pin enable
-#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 pin enable
-#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 pin enable
-#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 pin enable
-#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 pin enable
+#define PWM_ENABLE_PWM7EN       0x00000080  // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Inversion register.
+// The following are defines for the bit fields in the PWM_O_INVERT register.
 //
 //*****************************************************************************
-#define PWM_INVERT_PWM7INV      0x00000080  // PWM7 pin invert
-#define PWM_INVERT_PWM6INV      0x00000040  // PWM6 pin invert
-#define PWM_INVERT_PWM5INV      0x00000020  // PWM5 pin invert
-#define PWM_INVERT_PWM4INV      0x00000010  // PWM4 pin invert
-#define PWM_INVERT_PWM3INV      0x00000008  // PWM3 pin invert
-#define PWM_INVERT_PWM2INV      0x00000004  // PWM2 pin invert
-#define PWM_INVERT_PWM1INV      0x00000002  // PWM1 pin invert
-#define PWM_INVERT_PWM0INV      0x00000001  // PWM0 pin invert
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Fault register.
+// The following are defines for the bit fields in the PWM_O_FAULT register.
 //
 //*****************************************************************************
-#define PWM_FAULT_FAULT7        0x00000080  // PWM7 pin fault
-#define PWM_FAULT_FAULT6        0x00000040  // PWM6 pin fault
-#define PWM_FAULT_FAULT5        0x00000020  // PWM5 pin fault
-#define PWM_FAULT_FAULT4        0x00000010  // PWM4 pin fault
-#define PWM_FAULT_FAULT3        0x00000008  // PWM3 pin fault
-#define PWM_FAULT_FAULT2        0x00000004  // PWM2 pin fault
-#define PWM_FAULT_FAULT1        0x00000002  // PWM1 pin fault
-#define PWM_FAULT_FAULT0        0x00000001  // PWM0 pin fault
+#define PWM_FAULT_FAULT7        0x00000080  // PWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // PWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM Status register.
+// The following are defines for the bit fields in the PWM_O_INTEN register.
 //
 //*****************************************************************************
-#define PWM_STATUS_FAULT3       0x00000008  // Fault3 Interrupt Status.
-#define PWM_STATUS_FAULT2       0x00000004  // Fault2 Interrupt Status.
-#define PWM_STATUS_FAULT1       0x00000002  // Fault1 Interrupt Status.
-#define PWM_STATUS_FAULT0       0x00000001  // Fault0 Interrupt Status.
+#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
 
 //*****************************************************************************
 //
-// The following are defines for the PWM Generator standard offsets.
+// The following are defines for the bit fields in the PWM_O_RIS register.
 //
 //*****************************************************************************
-#define PWM_O_X_CTL             0x00000000  // Gen Control Reg
-#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg
-#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg
-#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg
-#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg
-#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg
-#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg
-#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg
-#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg
-#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg
-#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg
-#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg
-#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg
-#define PWM_O_X_FLTSRC0         0x00000034  // Fault pin, comparator condition
-#define PWM_O_X_FLTSRC1         0x00000038  // Digital comparator condition
-#define PWM_O_X_MINFLTPER       0x0000003C  // Fault minimum period extension
-#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base
-#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base
-#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
-#define PWM_GEN_3_OFFSET        0x00000100  // PWM3 base
+#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
 
 //*****************************************************************************
 //
-// The following are defines for the PWM_X Control Register bit definitions.
+// The following are defines for the bit fields in the PWM_O_ISC register.
 //
 //*****************************************************************************
-#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input.
-#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum fault period enabled
-#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source.
-#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // Specifies the update mode for
-                                            // the PWMnDBFALL register.
+#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3       0x00000008  // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2       0x00000004  // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
 #define PWM_X_CTL_DBFALLUPD_I   0x00000000  // Immediate
 #define PWM_X_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
 #define PWM_X_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
-#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode.
+#define PWM_X_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
 #define PWM_X_CTL_DBRISEUPD_I   0x00000000  // Immediate
 #define PWM_X_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
 #define PWM_X_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
-#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode.
+#define PWM_X_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
 #define PWM_X_CTL_DBCTLUPD_I    0x00000000  // Immediate
 #define PWM_X_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
 #define PWM_X_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
-#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode.
+#define PWM_X_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
 #define PWM_X_CTL_GENBUPD_I     0x00000000  // Immediate
 #define PWM_X_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
 #define PWM_X_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
-#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode.
+#define PWM_X_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
 #define PWM_X_CTL_GENAUPD_I     0x00000000  // Immediate
 #define PWM_X_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
 #define PWM_X_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
-#define PWM_X_CTL_CMPBUPD       0x00000020  // Update mode for comp B reg
-#define PWM_X_CTL_CMPAUPD       0x00000010  // Update mode for comp A reg
-#define PWM_X_CTL_LOADUPD       0x00000008  // Update mode for the load reg
-#define PWM_X_CTL_DEBUG         0x00000004  // Debug mode
-#define PWM_X_CTL_MODE          0x00000002  // Counter mode, down or up/down
-#define PWM_X_CTL_ENABLE        0x00000001  // Master enable for gen block
-
-//*****************************************************************************
-//
-// The following are defines for the PWM Generator extended offsets.
-//
-//*****************************************************************************
-#define PWM_O_X_FLTSEN          0x00000000  // Fault logic sense
-#define PWM_O_X_FLTSTAT0        0x00000004  // Pin and comparator status
-#define PWM_O_X_FLTSTAT1        0x00000008  // Digital comparator status
-#define PWM_EXT_0_OFFSET        0x00000800  // PWM0 extended base
-#define PWM_EXT_1_OFFSET        0x00000880  // PWM1 extended base
-#define PWM_EXT_2_OFFSET        0x00000900  // PWM2 extended base
-#define PWM_EXT_3_OFFSET        0x00000980  // PWM3 extended base
-
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Interrupt/Trigger Enable Register
-// bit definitions.
-//
-//*****************************************************************************
-#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trig if COUNT = CMPB D
-#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trig if COUNT = CMPB U
-#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trig if COUNT = CMPA D
-#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trig if COUNT = CMPA U
-#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trig if COUNT = LOAD
-#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trig if COUNT = 0
-#define PWM_X_INTEN_INTCMPBD    0x00000020  // Int if COUNT = CMPA D
-#define PWM_X_INTEN_INTCMPBU    0x00000010  // Int if COUNT = CMPA U
-#define PWM_X_INTEN_INTCMPAD    0x00000008  // Int if COUNT = CMPA D
-#define PWM_X_INTEN_INTCMPAU    0x00000004  // Int if COUNT = CMPA U
-#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Int if COUNT = LOAD
-#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Int if COUNT = 0
-
-//*****************************************************************************
-//
-// The following are defines for the PWM_X Raw Interrupt Status Register bit
-// definitions.
-//
-//*****************************************************************************
-#define PWM_X_RIS_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D int
-#define PWM_X_RIS_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U int
-#define PWM_X_RIS_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D int
-#define PWM_X_RIS_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U int
-#define PWM_X_RIS_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD int
-#define PWM_X_RIS_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 int
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_INTEN register.
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
 //
 //*****************************************************************************
-#define PWM_INTEN_INTFAULT3     0x00080000  // Interrupt Fault 3.
-#define PWM_INTEN_INTFAULT2     0x00040000  // Interrupt Fault 2.
-#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1.
-#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable.
-#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0.
-#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable.
-#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable.
-#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable.
-#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable.
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_RIS register.
-//
-//*****************************************************************************
-#define PWM_RIS_INTFAULT3       0x00080000  // Interrupt Fault PWM 3.
-#define PWM_RIS_INTFAULT2       0x00040000  // Interrupt Fault PWM 2.
-#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1.
-#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0.
-#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted.
-#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted.
-#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted.
-#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the PWM_O_ISC register.
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
 //
 //*****************************************************************************
-#define PWM_ISC_INTFAULT3       0x00080000  // FAULT3 Interrupt Asserted.
-#define PWM_ISC_INTFAULT2       0x00040000  // FAULT2 Interrupt Asserted.
-#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted.
-#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted.
-#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted.
-#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status.
-#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status.
-#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status.
-#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status.
+#define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_X_ISC register.
 //
 //*****************************************************************************
-#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt.
-#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt.
-#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt.
-#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt.
-#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt.
-#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt.
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_X_LOAD register.
 //
 //*****************************************************************************
-#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value.
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
 #define PWM_X_LOAD_S            0
 
 //*****************************************************************************
@@ -378,7 +393,7 @@
 // The following are defines for the bit fields in the PWM_O_X_COUNT register.
 //
 //*****************************************************************************
-#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value.
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
 #define PWM_X_COUNT_S           0
 
 //*****************************************************************************
@@ -386,7 +401,7 @@
 // The following are defines for the bit fields in the PWM_O_X_CMPA register.
 //
 //*****************************************************************************
-#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value.
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
 #define PWM_X_CMPA_S            0
 
 //*****************************************************************************
@@ -394,7 +409,7 @@
 // The following are defines for the bit fields in the PWM_O_X_CMPB register.
 //
 //*****************************************************************************
-#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value.
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
 #define PWM_X_CMPB_S            0
 
 //*****************************************************************************
@@ -402,102 +417,102 @@
 // The following are defines for the bit fields in the PWM_O_X_GENA register.
 //
 //*****************************************************************************
-#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENA_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENA_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
 #define PWM_X_GENA_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENA_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENA_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
 #define PWM_X_GENA_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_X_GENB register.
 //
 //*****************************************************************************
-#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down.
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
 #define PWM_X_GENB_ACTCMPBD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBD_ZERO \
-                                0x00000800  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up.
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
 #define PWM_X_GENB_ACTCMPBU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
 #define PWM_X_GENB_ACTCMPBU_ZERO \
-                                0x00000200  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down.
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
 #define PWM_X_GENB_ACTCMPAD_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAD_ZERO \
-                                0x00000080  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Set the output signal to 1.
-#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up.
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
 #define PWM_X_GENB_ACTCMPAU_NONE \
-                                0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert the output signal.
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
 #define PWM_X_GENB_ACTCMPAU_ZERO \
-                                0x00000020  // Set the output signal to 0.
-#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Set the output signal to 1.
-#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=Load.
-#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert the output signal.
-#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Set the output signal to 0.
-#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Set the output signal to 1.
-#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0.
-#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing.
-#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert the output signal.
-#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Set the output signal to 0.
-#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Set the output signal to 1.
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_X_DBCTL register.
 //
 //*****************************************************************************
-#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable.
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the PWM_O_X_DBRISE register.
 //
 //*****************************************************************************
-#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay.
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
 #define PWM_X_DBRISE_DELAY_S    0
 
 //*****************************************************************************
@@ -505,22 +520,34 @@
 // The following are defines for the bit fields in the PWM_O_X_DBFALL register.
 //
 //*****************************************************************************
-#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay.
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
 #define PWM_X_DBFALL_DELAY_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
 //
 //*****************************************************************************
-#define PWM_FAULTVAL_PWM7       0x00000080  // PWM7 Fault Value.
-#define PWM_FAULTVAL_PWM6       0x00000040  // PWM6 Fault Value.
-#define PWM_FAULTVAL_PWM5       0x00000020  // PWM5 Fault Value.
-#define PWM_FAULTVAL_PWM4       0x00000010  // PWM4 Fault Value.
-#define PWM_FAULTVAL_PWM3       0x00000008  // PWM3 Fault Value.
-#define PWM_FAULTVAL_PWM2       0x00000004  // PWM2 Fault Value.
-#define PWM_FAULTVAL_PWM1       0x00000002  // PWM1 Fault Value.
-#define PWM_FAULTVAL_PWM0       0x00000001  // PWM0 Fault Value.
+#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
 
 //*****************************************************************************
 //
@@ -528,7 +555,7 @@
 // register.
 //
 //*****************************************************************************
-#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period.
+#define PWM_X_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
 #define PWM_X_MINFLTPER_S       0
 
 //*****************************************************************************
@@ -536,62 +563,75 @@
 // The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense.
-#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense.
-#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense.
-#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense.
+#define PWM_X_FLTSEN_FAULT3     0x00000008  // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2     0x00000004  // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
 // register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSRC0_FAULT3    0x00000008  // Fault3.
-#define PWM_X_FLTSRC0_FAULT2    0x00000004  // Fault2.
-#define PWM_X_FLTSRC0_FAULT1    0x00000002  // Fault1.
-#define PWM_X_FLTSRC0_FAULT0    0x00000001  // Fault0.
+#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
 // register.
 //
 //*****************************************************************************
-#define PWM_X_FLTSTAT0_FAULT3   0x00000008  // Fault Input 3.
-#define PWM_X_FLTSTAT0_FAULT2   0x00000004  // Fault Input 2.
-#define PWM_X_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1.
-#define PWM_X_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0.
+#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
-// register.
+// The following are defines for the PWM Generator standard offsets.
 //
 //*****************************************************************************
-#define PWM_X_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7.
-#define PWM_X_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6.
-#define PWM_X_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5.
-#define PWM_X_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4.
-#define PWM_X_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3.
-#define PWM_X_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2.
-#define PWM_X_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1.
-#define PWM_X_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0.
+#define PWM_O_X_CTL             0x00000000  // Gen Control Reg
+#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg
+#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg
+#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg
+#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg
+#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg
+#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg
+#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0         0x00000034  // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1         0x00000038  // Digital comparator condition
+#define PWM_O_X_MINFLTPER       0x0000003C  // Fault minimum period extension
+#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base
+#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base
+#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base
+#define PWM_GEN_3_OFFSET        0x00000100  // PWM3 base
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
-// register.
+// The following are defines for the PWM Generator extended offsets.
 //
 //*****************************************************************************
-#define PWM_X_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger.
-#define PWM_X_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger.
-#define PWM_X_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger.
-#define PWM_X_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger.
-#define PWM_X_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger.
-#define PWM_X_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger.
-#define PWM_X_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger.
-#define PWM_X_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger.
+#define PWM_O_X_FLTSEN          0x00000000  // Fault logic sense
+#define PWM_O_X_FLTSTAT0        0x00000004  // Pin and comparator status
+#define PWM_O_X_FLTSTAT1        0x00000008  // Digital comparator status
+#define PWM_EXT_0_OFFSET        0x00000800  // PWM0 extended base
+#define PWM_EXT_1_OFFSET        0x00000880  // PWM1 extended base
+#define PWM_EXT_2_OFFSET        0x00000900  // PWM2 extended base
+#define PWM_EXT_3_OFFSET        0x00000980  // PWM3 extended base
 
 //*****************************************************************************
 //
@@ -602,8 +642,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the PWM Master
-// Control register.
+// The following are deprecated defines for the bit fields in the PWM_O_CTL
+// register.
 //
 //*****************************************************************************
 #define PWM_CTL_GLOBAL_SYNC2    0x00000004  // Global sync generator 2
@@ -612,19 +652,19 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the PWM Interrupt Register bit
-// definitions.
+// The following are deprecated defines for the bit fields in the PWM_O_STATUS
+// register.
 //
 //*****************************************************************************
-#define PWM_INT_INTFAULT        0x00010000  // Fault interrupt pending
+#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the PWM Status
-// register.
+// The following are deprecated defines for the PWM Interrupt Register bit
+// definitions.
 //
 //*****************************************************************************
-#define PWM_STATUS_FAULT        0x00000001  // Fault status
+#define PWM_INT_INTFAULT        0x00010000  // Fault interrupt pending
 
 //*****************************************************************************
 //

bsp/lm3s/Libraries/inc/hw_qei.h

@@ -2,26 +2,23 @@
 //
 // hw_qei.h - Macros used when accessing the QEI hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,132 +30,135 @@
 // The following are defines for the QEI register offsets.
 //
 //*****************************************************************************
-#define QEI_O_CTL               0x00000000  // Configuration and control reg.
-#define QEI_O_STAT              0x00000004  // Status register
-#define QEI_O_POS               0x00000008  // Current position register
-#define QEI_O_MAXPOS            0x0000000C  // Maximum position register
-#define QEI_O_LOAD              0x00000010  // Velocity timer load register
-#define QEI_O_TIME              0x00000014  // Velocity timer register
-#define QEI_O_COUNT             0x00000018  // Velocity pulse count register
-#define QEI_O_SPEED             0x0000001C  // Velocity speed register
-#define QEI_O_INTEN             0x00000020  // Interrupt enable register
-#define QEI_O_RIS               0x00000024  // Raw interrupt status register
-#define QEI_O_ISC               0x00000028  // Interrupt status register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the QEI_CTL register.
-//
-//*****************************************************************************
-#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Pre-Scale Count.
-#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter.
-#define QEI_CTL_STALLEN         0x00001000  // Stall enable
-#define QEI_CTL_INVI            0x00000800  // Invert Index input
-#define QEI_CTL_INVB            0x00000400  // Invert PhB input
-#define QEI_CTL_INVA            0x00000200  // Invert PhA input
-#define QEI_CTL_VELDIV_M        0x000001C0  // Velocity predivider mask
-#define QEI_CTL_VELDIV_1        0x00000000  // Predivide by 1
-#define QEI_CTL_VELDIV_2        0x00000040  // Predivide by 2
-#define QEI_CTL_VELDIV_4        0x00000080  // Predivide by 4
-#define QEI_CTL_VELDIV_8        0x000000C0  // Predivide by 8
-#define QEI_CTL_VELDIV_16       0x00000100  // Predivide by 16
-#define QEI_CTL_VELDIV_32       0x00000140  // Predivide by 32
-#define QEI_CTL_VELDIV_64       0x00000180  // Predivide by 64
-#define QEI_CTL_VELDIV_128      0x000001C0  // Predivide by 128
-#define QEI_CTL_VELEN           0x00000020  // Velocity enable
-#define QEI_CTL_RESMODE         0x00000010  // Position counter reset mode
-#define QEI_CTL_CAPMODE         0x00000008  // Edge capture mode
-#define QEI_CTL_SIGMODE         0x00000004  // Encoder signaling mode
-#define QEI_CTL_SWAP            0x00000002  // Swap input signals
-#define QEI_CTL_ENABLE          0x00000001  // QEI enable
+#define QEI_O_CTL               0x00000000  // QEI Control
+#define QEI_O_STAT              0x00000004  // QEI Status
+#define QEI_O_POS               0x00000008  // QEI Position
+#define QEI_O_MAXPOS            0x0000000C  // QEI Maximum Position
+#define QEI_O_LOAD              0x00000010  // QEI Timer Load
+#define QEI_O_TIME              0x00000014  // QEI Timer
+#define QEI_O_COUNT             0x00000018  // QEI Velocity Counter
+#define QEI_O_SPEED             0x0000001C  // QEI Velocity
+#define QEI_O_INTEN             0x00000020  // QEI Interrupt Enable
+#define QEI_O_RIS               0x00000024  // QEI Raw Interrupt Status
+#define QEI_O_ISC               0x00000028  // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
 #define QEI_CTL_FILTCNT_S       16
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_STAT register.
+// The following are defines for the bit fields in the QEI_O_STAT register.
 //
 //*****************************************************************************
-#define QEI_STAT_DIRECTION      0x00000002  // Direction of rotation
-#define QEI_STAT_ERROR          0x00000001  // Signalling error detected
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_POS register.
+// The following are defines for the bit fields in the QEI_O_POS register.
 //
 //*****************************************************************************
-#define QEI_POS_M               0xFFFFFFFF  // Current encoder position
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
 #define QEI_POS_S               0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_MAXPOS register.
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
 //
 //*****************************************************************************
-#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum encoder position
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
 #define QEI_MAXPOS_S            0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_LOAD register.
+// The following are defines for the bit fields in the QEI_O_LOAD register.
 //
 //*****************************************************************************
-#define QEI_LOAD_M              0xFFFFFFFF  // Velocity timer load value
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
 #define QEI_LOAD_S              0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_TIME register.
+// The following are defines for the bit fields in the QEI_O_TIME register.
 //
 //*****************************************************************************
-#define QEI_TIME_M              0xFFFFFFFF  // Velocity timer current value
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
 #define QEI_TIME_S              0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_COUNT register.
+// The following are defines for the bit fields in the QEI_O_COUNT register.
 //
 //*****************************************************************************
-#define QEI_COUNT_M             0xFFFFFFFF  // Encoder running pulse count
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
 #define QEI_COUNT_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_SPEED register.
+// The following are defines for the bit fields in the QEI_O_SPEED register.
 //
 //*****************************************************************************
-#define QEI_SPEED_M             0xFFFFFFFF  // Encoder pulse count
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
 #define QEI_SPEED_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_INTEN register.
+// The following are defines for the bit fields in the QEI_O_INTEN register.
 //
 //*****************************************************************************
-#define QEI_INTEN_ERROR         0x00000008  // Phase error detected
-#define QEI_INTEN_DIR           0x00000004  // Direction change
-#define QEI_INTEN_TIMER         0x00000002  // Velocity timer expired
-#define QEI_INTEN_INDEX         0x00000001  // Index pulse detected
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the QEI_RIS register.
+// The following are defines for the bit fields in the QEI_O_RIS register.
 //
 //*****************************************************************************
-#define QEI_RIS_ERROR           0x00000008  // Phase error detected
-#define QEI_RIS_DIR             0x00000004  // Direction change
-#define QEI_RIS_TIMER           0x00000002  // Velocity timer expired
-#define QEI_RIS_INDEX           0x00000001  // Index pulse detected
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the QEI_O_ISC register.
 //
 //*****************************************************************************
-#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt.
-#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt.
-#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired
-                                            // Interrupt.
-#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt.
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
 
 //*****************************************************************************
 //
@@ -186,7 +186,7 @@
 //*****************************************************************************
 #define QEI_RV_POS              0x00000000  // Current position register
 #define QEI_RV_LOAD             0x00000000  // Velocity timer load register
-#define QEI_RV_CTL              0x00000000  // Configuration and control reg.
+#define QEI_RV_CTL              0x00000000  // Configuration and control reg
 #define QEI_RV_RIS              0x00000000  // Raw interrupt status register
 #define QEI_RV_ISC              0x00000000  // Interrupt status register
 #define QEI_RV_SPEED            0x00000000  // Velocity speed register

bsp/lm3s/Libraries/inc/hw_ssi.h

@@ -2,26 +2,23 @@
 //
 // hw_ssi.h - Macros used when accessing the SSI hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,96 +30,96 @@
 // The following are defines for the SSI register offsets.
 //
 //*****************************************************************************
-#define SSI_O_CR0               0x00000000  // Control register 0
-#define SSI_O_CR1               0x00000004  // Control register 1
-#define SSI_O_DR                0x00000008  // Data register
-#define SSI_O_SR                0x0000000C  // Status register
-#define SSI_O_CPSR              0x00000010  // Clock prescale register
-#define SSI_O_IM                0x00000014  // Int mask set and clear register
-#define SSI_O_RIS               0x00000018  // Raw interrupt register
-#define SSI_O_MIS               0x0000001C  // Masked interrupt register
-#define SSI_O_ICR               0x00000020  // Interrupt clear register
+#define SSI_O_CR0               0x00000000  // SSI Control 0
+#define SSI_O_CR1               0x00000004  // SSI Control 1
+#define SSI_O_DR                0x00000008  // SSI Data
+#define SSI_O_SR                0x0000000C  // SSI Status
+#define SSI_O_CPSR              0x00000010  // SSI Clock Prescale
+#define SSI_O_IM                0x00000014  // SSI Interrupt Mask
+#define SSI_O_RIS               0x00000018  // SSI Raw Interrupt Status
+#define SSI_O_MIS               0x0000001C  // SSI Masked Interrupt Status
+#define SSI_O_ICR               0x00000020  // SSI Interrupt Clear
 #define SSI_O_DMACTL            0x00000024  // SSI DMA Control
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI Control register 0.
-//
-//*****************************************************************************
-#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate.
-#define SSI_CR0_SPH             0x00000080  // SSPCLKOUT phase
-#define SSI_CR0_SPO             0x00000040  // SSPCLKOUT polarity
-#define SSI_CR0_FRF_M           0x00000030  // Frame format mask
-#define SSI_CR0_FRF_MOTO        0x00000000  // Motorola SPI frame format
-#define SSI_CR0_FRF_TI          0x00000010  // TI sync serial frame format
-#define SSI_CR0_FRF_NMW         0x00000020  // National Microwire frame format
-#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select.
-#define SSI_CR0_DSS_4           0x00000003  // 4 bit data
-#define SSI_CR0_DSS_5           0x00000004  // 5 bit data
-#define SSI_CR0_DSS_6           0x00000005  // 6 bit data
-#define SSI_CR0_DSS_7           0x00000006  // 7 bit data
-#define SSI_CR0_DSS_8           0x00000007  // 8 bit data
-#define SSI_CR0_DSS_9           0x00000008  // 9 bit data
-#define SSI_CR0_DSS_10          0x00000009  // 10 bit data
-#define SSI_CR0_DSS_11          0x0000000A  // 11 bit data
-#define SSI_CR0_DSS_12          0x0000000B  // 12 bit data
-#define SSI_CR0_DSS_13          0x0000000C  // 13 bit data
-#define SSI_CR0_DSS_14          0x0000000D  // 14 bit data
-#define SSI_CR0_DSS_15          0x0000000E  // 15 bit data
-#define SSI_CR0_DSS_16          0x0000000F  // 16 bit data
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
+                                            // Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
 #define SSI_CR0_SCR_S           8
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI Control register 1.
+// The following are defines for the bit fields in the SSI_O_CR1 register.
 //
 //*****************************************************************************
-#define SSI_CR1_EOT             0x00000010  // End of Transmission.
-#define SSI_CR1_SOD             0x00000008  // Slave mode output disable
-#define SSI_CR1_MS              0x00000004  // Master or slave mode select
-#define SSI_CR1_SSE             0x00000002  // Sync serial port enable
-#define SSI_CR1_LBM             0x00000001  // Loopback mode
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI Status register.
+// The following are defines for the bit fields in the SSI_O_DR register.
 //
 //*****************************************************************************
-#define SSI_SR_BSY              0x00000010  // SSI busy
-#define SSI_SR_RFF              0x00000008  // RX FIFO full
-#define SSI_SR_RNE              0x00000004  // RX FIFO not empty
-#define SSI_SR_TNF              0x00000002  // TX FIFO not full
-#define SSI_SR_TFE              0x00000001  // TX FIFO empty
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI clock prescale
-// register.
+// The following are defines for the bit fields in the SSI_O_SR register.
 //
 //*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor.
-#define SSI_CPSR_CPSDVSR_S      0
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the SSI_O_DR register.
+// The following are defines for the bit fields in the SSI_O_CPSR register.
 //
 //*****************************************************************************
-#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data.
-#define SSI_DR_DATA_S           0
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_IM register.
 //
 //*****************************************************************************
-#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt
-                                            // Mask.
-#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask.
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
 #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Mask.
+                                            // Mask
 #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
-                                            // Mask.
+                                            // Mask
 
 //*****************************************************************************
 //
@@ -130,13 +127,13 @@
 //
 //*****************************************************************************
 #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
-                                            // Status.
+                                            // Status
 #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -144,13 +141,13 @@
 //
 //*****************************************************************************
 #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
@@ -158,17 +155,17 @@
 //
 //*****************************************************************************
 #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
-                                            // Clear.
+                                            // Clear
 #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
-                                            // Clear.
+                                            // Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the SSI_O_DMACTL register.
 //
 //*****************************************************************************
-#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable.
-#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable.
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
 
 //*****************************************************************************
 //
@@ -179,8 +176,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the SSI Control
-// register 0.
+// The following are deprecated defines for the bit fields in the SSI_O_CR0
+// register.
 //
 //*****************************************************************************
 #define SSI_CR0_SCR             0x0000FF00  // Serial clock rate
@@ -189,8 +186,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the SSI clock
-// prescale register.
+// The following are deprecated defines for the bit fields in the SSI_O_CPSR
+// register.
 //
 //*****************************************************************************
 #define SSI_CPSR_CPSDVSR_MASK   0x000000FF  // Clock prescale

bsp/lm3s/Libraries/inc/hw_timer.h

@@ -2,26 +2,23 @@
 //
 // hw_timer.h - Defines and macros used when accessing the timer.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,236 +27,243 @@
 
 //*****************************************************************************
 //
-// The following are defines for the timer register offsets.
-//
-//*****************************************************************************
-#define TIMER_O_CFG             0x00000000  // Configuration register
-#define TIMER_O_TAMR            0x00000004  // TimerA mode register
-#define TIMER_O_TBMR            0x00000008  // TimerB mode register
-#define TIMER_O_CTL             0x0000000C  // Control register
-#define TIMER_O_IMR             0x00000018  // Interrupt mask register
-#define TIMER_O_RIS             0x0000001C  // Interrupt status register
-#define TIMER_O_MIS             0x00000020  // Masked interrupt status reg.
-#define TIMER_O_ICR             0x00000024  // Interrupt clear register
-#define TIMER_O_TAILR           0x00000028  // TimerA interval load register
-#define TIMER_O_TBILR           0x0000002C  // TimerB interval load register
-#define TIMER_O_TAMATCHR        0x00000030  // TimerA match register
-#define TIMER_O_TBMATCHR        0x00000034  // TimerB match register
-#define TIMER_O_TAPR            0x00000038  // TimerA prescale register
-#define TIMER_O_TBPR            0x0000003C  // TimerB prescale register
-#define TIMER_O_TAPMR           0x00000040  // TimerA prescale match register
-#define TIMER_O_TBPMR           0x00000044  // TimerB prescale match register
-#define TIMER_O_TAR             0x00000048  // TimerA register
-#define TIMER_O_TBR             0x0000004C  // TimerB register
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG             0x00000000  // GPTM Configuration
+#define TIMER_O_TAMR            0x00000004  // GPTM Timer A Mode
+#define TIMER_O_TBMR            0x00000008  // GPTM Timer B Mode
+#define TIMER_O_CTL             0x0000000C  // GPTM Control
+#define TIMER_O_IMR             0x00000018  // GPTM Interrupt Mask
+#define TIMER_O_RIS             0x0000001C  // GPTM Raw Interrupt Status
+#define TIMER_O_MIS             0x00000020  // GPTM Masked Interrupt Status
+#define TIMER_O_ICR             0x00000024  // GPTM Interrupt Clear
+#define TIMER_O_TAILR           0x00000028  // GPTM Timer A Interval Load
+#define TIMER_O_TBILR           0x0000002C  // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR        0x00000030  // GPTM Timer A Match
+#define TIMER_O_TBMATCHR        0x00000034  // GPTM Timer B Match
+#define TIMER_O_TAPR            0x00000038  // GPTM Timer A Prescale
+#define TIMER_O_TBPR            0x0000003C  // GPTM Timer B Prescale
+#define TIMER_O_TAPMR           0x00000040  // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR           0x00000044  // GPTM TimerB Prescale Match
+#define TIMER_O_TAR             0x00000048  // GPTM Timer A
+#define TIMER_O_TBR             0x0000004C  // GPTM Timer B
 #define TIMER_O_TAV             0x00000050  // GPTM Timer A Value
 #define TIMER_O_TBV             0x00000054  // GPTM Timer B Value
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_CFG register.
-//
-//*****************************************************************************
-#define TIMER_CFG_M             0x00000007  // GPTM Configuration.
-#define TIMER_CFG_16_BIT        0x00000004  // Two 16 bit timers
-#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32 bit RTC
-#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32 bit timer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_CTL register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBPWML        0x00004000  // TimerB PWM output level invert
-#define TIMER_CTL_TBOTE         0x00002000  // TimerB output trigger enable
-#define TIMER_CTL_TBEVENT_POS   0x00000000  // TimerB event mode - pos edge
-#define TIMER_CTL_TBEVENT_NEG   0x00000400  // TimerB event mode - neg edge
-#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // TimerB event mode - both edges
-#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM TimerB Event Mode.
-#define TIMER_CTL_TBSTALL       0x00000200  // TimerB stall enable
-#define TIMER_CTL_TBEN          0x00000100  // TimerB enable
-#define TIMER_CTL_TAPWML        0x00000040  // TimerA PWM output level invert
-#define TIMER_CTL_TAOTE         0x00000020  // TimerA output trigger enable
-#define TIMER_CTL_RTCEN         0x00000010  // RTC counter enable
-#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM TimerA Event Mode.
-#define TIMER_CTL_TAEVENT_POS   0x00000000  // TimerA event mode - pos edge
-#define TIMER_CTL_TAEVENT_NEG   0x00000004  // TimerA event mode - neg edge
-#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // TimerA event mode - both edges
-#define TIMER_CTL_TASTALL       0x00000002  // TimerA stall enable
-#define TIMER_CTL_TAEN          0x00000001  // TimerA enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_IMR register.
+// The following are defines for the bit fields in the TIMER_O_CFG register.
 //
 //*****************************************************************************
-#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Mask.
-#define TIMER_IMR_CBEIM         0x00000400  // CaptureB event interrupt mask
-#define TIMER_IMR_CBMIM         0x00000200  // CaptureB match interrupt mask
-#define TIMER_IMR_TBTOIM        0x00000100  // TimerB time out interrupt mask
-#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Mask.
-#define TIMER_IMR_RTCIM         0x00000008  // RTC interrupt mask
-#define TIMER_IMR_CAEIM         0x00000004  // CaptureA event interrupt mask
-#define TIMER_IMR_CAMIM         0x00000002  // CaptureA match interrupt mask
-#define TIMER_IMR_TATOIM        0x00000001  // TimerA time out interrupt mask
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
+                                            // function is controlled by bits
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_RIS register.
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
 //
 //*****************************************************************************
-#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_CBERIS        0x00000400  // CaptureB event raw int status
-#define TIMER_RIS_CBMRIS        0x00000200  // CaptureB match raw int status
-#define TIMER_RIS_TBTORIS       0x00000100  // TimerB time out raw int status
-#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
-                                            // Interrupt.
-#define TIMER_RIS_RTCRIS        0x00000008  // RTC raw int status
-#define TIMER_RIS_CAERIS        0x00000004  // CaptureA event raw int status
-#define TIMER_RIS_CAMRIS        0x00000002  // CaptureA match raw int status
-#define TIMER_RIS_TATORIS       0x00000001  // TimerA time out raw int status
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_ICR register.
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
 //
 //*****************************************************************************
-#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
-                                            // Interrupt Clear.
-#define TIMER_ICR_CBECINT       0x00000400  // CaptureB event interrupt clear
-#define TIMER_ICR_CBMCINT       0x00000200  // CaptureB match interrupt clear
-#define TIMER_ICR_TBTOCINT      0x00000100  // TimerB time out interrupt clear
-#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
-                                            // Interrupt Clear.
-#define TIMER_ICR_RTCCINT       0x00000008  // RTC interrupt clear
-#define TIMER_ICR_CAECINT       0x00000004  // CaptureA event interrupt clear
-#define TIMER_ICR_CAMCINT       0x00000002  // CaptureA match interrupt clear
-#define TIMER_ICR_TATOCINT      0x00000001  // TimerA time out interrupt clear
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_TAILR register.
+// The following are defines for the bit fields in the TIMER_O_CTL register.
 //
 //*****************************************************************************
-#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM TimerA Interval Load
-                                            // Register High.
-#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM TimerA Interval Load
-                                            // Register Low.
-#define TIMER_TAILR_TAILRH_S    16
-#define TIMER_TAILR_TAILRL_S    0
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_TBILR register.
+// The following are defines for the bit fields in the TIMER_O_IMR register.
 //
 //*****************************************************************************
-#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM TimerB Interval Load
-                                            // Register.
-#define TIMER_TBILR_TBILRL_S    0
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_TAMATCHR register.
+// The following are defines for the bit fields in the TIMER_O_RIS register.
 //
 //*****************************************************************************
-#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM TimerA Match Register High.
-#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM TimerA Match Register Low.
-#define TIMER_TAMATCHR_TAMRH_S  16
-#define TIMER_TAMATCHR_TAMRL_S  0
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
+                                            // Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_TBMATCHR register.
+// The following are defines for the bit fields in the TIMER_O_MIS register.
 //
 //*****************************************************************************
-#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM TimerB Match Register Low.
-#define TIMER_TBMATCHR_TBMRL_S  0
+#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_TAR register.
+// The following are defines for the bit fields in the TIMER_O_ICR register.
 //
 //*****************************************************************************
-#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM TimerA Register High.
-#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM TimerA Register Low.
-#define TIMER_TAR_TARH_S        16
-#define TIMER_TAR_TARL_S        0
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_TBR register.
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
 //
 //*****************************************************************************
-#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM TimerB.
-#define TIMER_TBR_TBRL_S        0
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
+#define TIMER_TAILR_TAILRH_S    16
+#define TIMER_TAILR_TAILRL_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_O_TAMR register.
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
 //
 //*****************************************************************************
-#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode.
-#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger.
-#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
-                                            // Enable.
-#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction.
-#define TIMER_TAMR_TAAMS        0x00000008  // GPTM TimerA Alternate Mode
-                                            // Select.
-#define TIMER_TAMR_TACMR        0x00000004  // GPTM TimerA Capture Mode.
-#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM TimerA Mode.
-#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode.
-#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode.
-#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode.
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_TBILRL_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_O_TBMR register.
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
 //
 //*****************************************************************************
-#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode.
-#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger.
-#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
-                                            // Enable.
-#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction.
-#define TIMER_TBMR_TBAMS        0x00000008  // GPTM TimerB Alternate Mode
-                                            // Select.
-#define TIMER_TBMR_TBCMR        0x00000004  // GPTM TimerB Capture Mode.
-#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM TimerB Mode.
-#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode.
-#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode.
-#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode.
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S  16
+#define TIMER_TAMATCHR_TAMRL_S  0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_O_MIS register.
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
 //
 //*****************************************************************************
-#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBEMIS        0x00000400  // GPTM CaptureB Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CBMMIS        0x00000200  // GPTM CaptureB Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM TimerB Time-Out Masked
-                                            // Interrupt.
-#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt.
-#define TIMER_MIS_CAEMIS        0x00000004  // GPTM CaptureA Event Masked
-                                            // Interrupt.
-#define TIMER_MIS_CAMMIS        0x00000002  // GPTM CaptureA Match Masked
-                                            // Interrupt.
-#define TIMER_MIS_TATOMIS       0x00000001  // GPTM TimerA Time-Out Masked
-                                            // Interrupt.
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMRL_S  0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the TIMER_O_TAPR register.
 //
 //*****************************************************************************
-#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM TimerA Prescale.
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
 #define TIMER_TAPR_TAPSR_S      0
 
 //*****************************************************************************
@@ -267,7 +271,7 @@
 // The following are defines for the bit fields in the TIMER_O_TBPR register.
 //
 //*****************************************************************************
-#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM TimerB Prescale.
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
 #define TIMER_TBPR_TBPSR_S      0
 
 //*****************************************************************************
@@ -275,7 +279,7 @@
 // The following are defines for the bit fields in the TIMER_O_TAPMR register.
 //
 //*****************************************************************************
-#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match.
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
 #define TIMER_TAPMR_TAPSMR_S    0
 
 //*****************************************************************************
@@ -283,83 +287,63 @@
 // The following are defines for the bit fields in the TIMER_O_TBPMR register.
 //
 //*****************************************************************************
-#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match.
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
 #define TIMER_TBPMR_TBPSMR_S    0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_O_TAV register.
+// The following are defines for the bit fields in the TIMER_O_TAR register.
 //
 //*****************************************************************************
-#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High.
-#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low.
-#define TIMER_TAV_TAVH_S        16
-#define TIMER_TAV_TAVL_S        0
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S        16
+#define TIMER_TAR_TARL_S        0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the TIMER_O_TBV register.
+// The following are defines for the bit fields in the TIMER_O_TBR register.
 //
 //*****************************************************************************
-#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register.
-#define TIMER_TBV_TBVL_S        0
+#define TIMER_TBR_TBRL_M        0x00FFFFFF  // GPTM Timer B
+#define TIMER_TBR_TBRL_S        0
 
 //*****************************************************************************
 //
-// The following definitions are deprecated.
+// The following are defines for the bit fields in the TIMER_O_TAV register.
 //
 //*****************************************************************************
-#ifndef DEPRECATED
+#define TIMER_TAV_TAVH_M        0xFFFF0000  // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M        0x0000FFFF  // GPTM Timer A Register Low
+#define TIMER_TAV_TAVH_S        16
+#define TIMER_TAV_TAVL_S        0
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the reset values of the timer
-// registers.
+// The following are defines for the bit fields in the TIMER_O_TBV register.
 //
 //*****************************************************************************
-#define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV
-#define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV
-#define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV
-#define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV
-#define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV
-#define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV
-#define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV
-#define TIMER_RV_CFG            0x00000000  // Configuration register RV
-#define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV
-#define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV
-#define TIMER_RV_CTL            0x00000000  // Control register RV
-#define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV
-#define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV
-#define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV
-#define TIMER_RV_RIS            0x00000000  // Interrupt status register RV
-#define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV
-#define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
-#define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
+#define TIMER_TBV_TBVL_M        0x0000FFFF  // GPTM Timer B Register
+#define TIMER_TBV_TBVL_S        0
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_CFG
-// register.
+// The following definitions are deprecated.
 //
 //*****************************************************************************
-#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
+#ifndef DEPRECATED
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// The following are deprecated defines for the bit fields in the TIMER_O_CFG
 // register.
 //
 //*****************************************************************************
-#define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select
-#define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time
-#define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask
-#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot
-#define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
-#define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
+#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_CTL
+// The following are deprecated defines for the bit fields in the TIMER_O_CTL
 // register.
 //
 //*****************************************************************************
@@ -368,7 +352,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_MIS
+// The following are deprecated defines for the bit fields in the TIMER_O_RIS
 // register.
 //
 //*****************************************************************************
@@ -382,7 +366,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TAILR
+// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
 // register.
 //
 //*****************************************************************************
@@ -391,7 +375,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TBILR
+// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
 // register.
 //
 //*****************************************************************************
@@ -400,7 +384,7 @@
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the
-// TIMER_TAMATCHR register.
+// TIMER_O_TAMATCHR register.
 //
 //*****************************************************************************
 #define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode
@@ -409,43 +393,81 @@
 //*****************************************************************************
 //
 // The following are deprecated defines for the bit fields in the
-// TIMER_TBMATCHR register.
+// TIMER_O_TBMATCHR register.
 //
 //*****************************************************************************
 #define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TnPR
+// The following are deprecated defines for the bit fields in the TIMER_O_TAR
 // register.
 //
 //*****************************************************************************
-#define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value
+#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TnPMR
+// The following are deprecated defines for the bit fields in the TIMER_O_TBR
 // register.
 //
 //*****************************************************************************
-#define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
+#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the timer
+// registers.
+//
+//*****************************************************************************
+#define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV
+#define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV
+#define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV
+#define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV
+#define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV
+#define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV
+#define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV
+#define TIMER_RV_CFG            0x00000000  // Configuration register RV
+#define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV
+#define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV
+#define TIMER_RV_CTL            0x00000000  // Control register RV
+#define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV
+#define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV
+#define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV
+#define TIMER_RV_RIS            0x00000000  // Interrupt status register RV
+#define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV
+#define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV
+#define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select
+#define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time
+#define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic
+#define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TAR
+// The following are deprecated defines for the bit fields in the TIMER_TnPR
 // register.
 //
 //*****************************************************************************
-#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode
-#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value
+#define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the TIMER_TBR
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR
 // register.
 //
 //*****************************************************************************
-#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value
+#define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value
 
 #endif
 

bsp/lm3s/Libraries/inc/hw_types.h

@@ -2,26 +2,23 @@
 //
 // hw_types.h - Common types and macros.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -148,6 +145,12 @@ typedef unsigned char tBoolean;
          (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
 #endif
 
+#ifndef REVISION_IS_C0
+#define REVISION_IS_C0                                                     \
+        ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+         (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
+#endif
+
 #ifndef REVISION_IS_C1
 #define REVISION_IS_C1                                                     \
         ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \

bsp/lm3s/Libraries/inc/hw_uart.h

@@ -1,27 +1,24 @@
 //*****************************************************************************
 //
-// hw_uart.h - Macros and defines used when accessing the UART hardware
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,23 +27,24 @@
 
 //*****************************************************************************
 //
-// The following are defines for the UART Register offsets.
+// The following are defines for the UART register offsets.
 //
 //*****************************************************************************
-#define UART_O_DR               0x00000000  // Data Register
-#define UART_O_RSR              0x00000004  // Receive Status Register (read)
-#define UART_O_ECR              0x00000004  // Error Clear Register (write)
-#define UART_O_FR               0x00000018  // Flag Register (read only)
+#define UART_O_DR               0x00000000  // UART Data
+#define UART_O_RSR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_ECR              0x00000004  // UART Receive Status/Error Clear
+#define UART_O_FR               0x00000018  // UART Flag
 #define UART_O_ILPR             0x00000020  // UART IrDA Low-Power Register
-#define UART_O_IBRD             0x00000024  // Integer Baud Rate Divisor Reg
-#define UART_O_FBRD             0x00000028  // Fractional Baud Rate Divisor Reg
+#define UART_O_IBRD             0x00000024  // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD             0x00000028  // UART Fractional Baud-Rate
+                                            // Divisor
 #define UART_O_LCRH             0x0000002C  // UART Line Control
-#define UART_O_CTL              0x00000030  // Control Register
-#define UART_O_IFLS             0x00000034  // Interrupt FIFO Level Select Reg
-#define UART_O_IM               0x00000038  // Interrupt Mask Set/Clear Reg
-#define UART_O_RIS              0x0000003C  // Raw Interrupt Status Register
-#define UART_O_MIS              0x00000040  // Masked Interrupt Status Register
-#define UART_O_ICR              0x00000044  // Interrupt Clear Register
+#define UART_O_CTL              0x00000030  // UART Control
+#define UART_O_IFLS             0x00000034  // UART Interrupt FIFO Level Select
+#define UART_O_IM               0x00000038  // UART Interrupt Mask
+#define UART_O_RIS              0x0000003C  // UART Raw Interrupt Status
+#define UART_O_MIS              0x00000040  // UART Masked Interrupt Status
+#define UART_O_ICR              0x00000044  // UART Interrupt Clear
 #define UART_O_DMACTL           0x00000048  // UART DMA Control
 #define UART_O_LCTL             0x00000090  // UART LIN Control
 #define UART_O_LSS              0x00000094  // UART LIN Snap Shot
@@ -54,260 +52,279 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Data Register bits
+// The following are defines for the bit fields in the UART_O_DR register.
 //
 //*****************************************************************************
-#define UART_DR_OE              0x00000800  // Overrun Error
-#define UART_DR_BE              0x00000400  // Break Error
-#define UART_DR_PE              0x00000200  // Parity Error
-#define UART_DR_FE              0x00000100  // Framing Error
-#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received.
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
 #define UART_DR_DATA_S          0
 
 //*****************************************************************************
 //
-// The following are defines for the Receive Status Register bits
+// The following are defines for the bit fields in the UART_O_RSR register.
 //
 //*****************************************************************************
-#define UART_RSR_OE             0x00000008  // Overrun Error
-#define UART_RSR_BE             0x00000004  // Break Error
-#define UART_RSR_PE             0x00000002  // Parity Error
-#define UART_RSR_FE             0x00000001  // Framing Error
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
 
 //*****************************************************************************
 //
-// The following are defines for the Flag Register bits
+// The following are defines for the bit fields in the UART_O_ECR register.
 //
 //*****************************************************************************
-#define UART_FR_RI              0x00000100  // Ring Indicator.
-#define UART_FR_TXFE            0x00000080  // TX FIFO Empty
-#define UART_FR_RXFF            0x00000040  // RX FIFO Full
-#define UART_FR_TXFF            0x00000020  // TX FIFO Full
-#define UART_FR_RXFE            0x00000010  // RX FIFO Empty
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI              0x00000100  // Ring Indicator
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
 #define UART_FR_BUSY            0x00000008  // UART Busy
-#define UART_FR_DCD             0x00000004  // Data Carrier Detect.
-#define UART_FR_DSR             0x00000002  // Data Set Ready.
-#define UART_FR_CTS             0x00000001  // Clear To Send.
+#define UART_FR_DCD             0x00000004  // Data Carrier Detect
+#define UART_FR_DSR             0x00000002  // Data Set Ready
+#define UART_FR_CTS             0x00000001  // Clear To Send
 
 //*****************************************************************************
 //
-// The following are defines for the Integer baud-rate divisor
+// The following are defines for the bit fields in the UART_O_ILPR register.
 //
 //*****************************************************************************
-#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor.
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
 #define UART_IBRD_DIVINT_S      0
 
 //*****************************************************************************
 //
-// The following are defines for the Fractional baud-rate divisor
+// The following are defines for the bit fields in the UART_O_FBRD register.
 //
 //*****************************************************************************
-#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor.
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
 #define UART_FBRD_DIVFRAC_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the Control Register bits
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
 //
 //*****************************************************************************
-#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send.
-#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send.
-#define UART_CTL_RTS            0x00000800  // Request to Send.
-#define UART_CTL_DTR            0x00000400  // Data Terminal Ready.
-#define UART_CTL_RXE            0x00000200  // Receive Enable
-#define UART_CTL_TXE            0x00000100  // Transmit Enable
-#define UART_CTL_LBE            0x00000080  // Loopback Enable
-#define UART_CTL_LIN            0x00000040  // LIN Mode Enable.
-#define UART_CTL_HSE            0x00000020  // High-Speed Enable.
-#define UART_CTL_EOT            0x00000010  // End of Transmission.
-#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support.
-#define UART_CTL_SIRLP          0x00000004  // SIR (IrDA) Low Power Enable
-#define UART_CTL_SIREN          0x00000002  // SIR (IrDA) Enable
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_DTR            0x00000400  // Data Terminal Ready
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_LIN            0x00000040  // LIN Mode Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
 #define UART_CTL_UARTEN         0x00000001  // UART Enable
 
 //*****************************************************************************
 //
-// The following are defines for the Interrupt FIFO Level Select Register bits
+// The following are defines for the bit fields in the UART_O_IFLS register.
 //
 //*****************************************************************************
-#define UART_IFLS_RX_M          0x00000038  // RX FIFO Level Interrupt Mask
-#define UART_IFLS_RX1_8         0x00000000  // 1/8 Full
-#define UART_IFLS_RX2_8         0x00000008  // 1/4 Full
-#define UART_IFLS_RX4_8         0x00000010  // 1/2 Full
-#define UART_IFLS_RX6_8         0x00000018  // 3/4 Full
-#define UART_IFLS_RX7_8         0x00000020  // 7/8 Full
-#define UART_IFLS_TX_M          0x00000007  // TX FIFO Level Interrupt Mask
-#define UART_IFLS_TX1_8         0x00000000  // 1/8 Full
-#define UART_IFLS_TX2_8         0x00000001  // 1/4 Full
-#define UART_IFLS_TX4_8         0x00000002  // 1/2 Full
-#define UART_IFLS_TX6_8         0x00000003  // 3/4 Full
-#define UART_IFLS_TX7_8         0x00000004  // 7/8 Full
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
 
 //*****************************************************************************
 //
-// The following are defines for the Interrupt Mask Set/Clear Register bits
+// The following are defines for the bit fields in the UART_O_IM register.
 //
 //*****************************************************************************
-#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask.
-#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask.
+#define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask
 #define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Mask.
-#define UART_IM_OEIM            0x00000400  // Overrun Error Interrupt Mask
-#define UART_IM_BEIM            0x00000200  // Break Error Interrupt Mask
-#define UART_IM_PEIM            0x00000100  // Parity Error Interrupt Mask
-#define UART_IM_FEIM            0x00000080  // Framing Error Interrupt Mask
-#define UART_IM_RTIM            0x00000040  // Receive Timeout Interrupt Mask
-#define UART_IM_TXIM            0x00000020  // Transmit Interrupt Mask
-#define UART_IM_RXIM            0x00000010  // Receive Interrupt Mask
+                                            // Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
 #define UART_IM_DSRMIM          0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define UART_IM_DCDMIM          0x00000004  // UART Data Carrier Detect Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 #define UART_IM_RIMIM           0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Mask.
+                                            // Interrupt Mask
 
 //*****************************************************************************
 //
-// The following are defines for the Raw Interrupt Status Register
+// The following are defines for the bit fields in the UART_O_RIS register.
 //
 //*****************************************************************************
 #define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
-                                            // Status.
+                                            // Status
 #define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
-                                            // Interrupt Status.
-#define UART_RIS_OERIS          0x00000400  // Overrun Error Interrupt Status
-#define UART_RIS_BERIS          0x00000200  // Break Error Interrupt Status
-#define UART_RIS_PERIS          0x00000100  // Parity Error Interrupt Status
-#define UART_RIS_FERIS          0x00000080  // Framing Error Interrupt Status
-#define UART_RIS_RTRIS          0x00000040  // Receive Timeout Interrupt Status
-#define UART_RIS_TXRIS          0x00000020  // Transmit Interrupt Status
-#define UART_RIS_RXRIS          0x00000010  // Receive Interrupt Status
+                                            // Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
 #define UART_RIS_DSRRIS         0x00000008  // UART Data Set Ready Modem Raw
-                                            // Interrupt Status.
-#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect odem
-                                            // Raw Interrupt Status.
+                                            // Interrupt Status
+#define UART_RIS_DCDRIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Raw Interrupt Status
 #define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_RIS_RIRIS          0x00000001  // UART Ring Indicator Modem Raw
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the Masked Interrupt Status Register
+// The following are defines for the bit fields in the UART_O_MIS register.
 //
 //*****************************************************************************
 #define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
-                                            // Status.
+                                            // Status
 #define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
-                                            // Interrupt Status.
-#define UART_MIS_OEMIS          0x00000400  // Overrun Error Interrupt Status
-#define UART_MIS_BEMIS          0x00000200  // Break Error Interrupt Status
-#define UART_MIS_PEMIS          0x00000100  // Parity Error Interrupt Status
-#define UART_MIS_FEMIS          0x00000080  // Framing Error Interrupt Status
-#define UART_MIS_RTMIS          0x00000040  // Receive Timeout Interrupt Status
-#define UART_MIS_TXMIS          0x00000020  // Transmit Interrupt Status
-#define UART_MIS_RXMIS          0x00000010  // Receive Interrupt Status
+                                            // Interrupt Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
 #define UART_MIS_DSRMIS         0x00000008  // UART Data Set Ready Modem Masked
-                                            // Interrupt Status.
-#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect odem
-                                            // Masked Interrupt Status.
+                                            // Interrupt Status
+#define UART_MIS_DCDMIS         0x00000004  // UART Data Carrier Detect Modem
+                                            // Masked Interrupt Status
 #define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 #define UART_MIS_RIMIS          0x00000001  // UART Ring Indicator Modem Masked
-                                            // Interrupt Status.
+                                            // Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the Interrupt Clear Register bits
+// The following are defines for the bit fields in the UART_O_ICR register.
 //
 //*****************************************************************************
-#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear.
-#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear.
+#define UART_ICR_LME5MIC        0x00008000  // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC        0x00004000  // LIN Mode Edge 1 Interrupt Clear
 #define UART_ICR_LMSBMIC        0x00002000  // LIN Mode Sync Break Interrupt
-                                            // Clear.
+                                            // Clear
 #define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
 #define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
 #define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
 #define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
-#define UART_ICR_RTIC           0x00000040  // Receive Timeout Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
 #define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
 #define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
 #define UART_ICR_DSRMIC         0x00000008  // UART Data Set Ready Modem
-                                            // Interrupt Clear.
-#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect odem
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
+#define UART_ICR_DCDMIC         0x00000004  // UART Data Carrier Detect Modem
+                                            // Interrupt Clear
 #define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
-                                            // Interrupt Clear.
+                                            // Interrupt Clear
 #define UART_ICR_RIMIC          0x00000001  // UART Ring Indicator Modem
-                                            // Interrupt Clear.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ECR register.
-//
-//*****************************************************************************
-#define UART_ECR_DATA_M         0x000000FF  // Error Clear.
-#define UART_ECR_DATA_S         0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LCRH register.
-//
-//*****************************************************************************
-#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select.
-#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length.
-#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
-#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
-#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
-#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
-#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs.
-#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select.
-#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select.
-#define UART_LCRH_PEN           0x00000002  // UART Parity Enable.
-#define UART_LCRH_BRK           0x00000001  // UART Send Break.
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ILPR register.
-//
-//*****************************************************************************
-#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor.
-#define UART_ILPR_ILPDVSR_S     0
+                                            // Interrupt Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_DMACTL register.
 //
 //*****************************************************************************
-#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error.
-#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable.
-#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable.
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_LCTL register.
 //
 //*****************************************************************************
-#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length.
+#define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length
 #define UART_LCTL_BLEN_13T      0x00000000  // Sync break length is 13T bits
                                             // (default)
 #define UART_LCTL_BLEN_14T      0x00000010  // Sync break length is 14T bits
 #define UART_LCTL_BLEN_15T      0x00000020  // Sync break length is 15T bits
 #define UART_LCTL_BLEN_16T      0x00000030  // Sync break length is 16T bits
-#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable.
+#define UART_LCTL_MASTER        0x00000001  // LIN Master Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UART_O_LSS register.
 //
 //*****************************************************************************
-#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot.
+#define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot
 #define UART_LSS_TSS_S          0
 
 //*****************************************************************************
@@ -315,7 +332,7 @@
 // The following are defines for the bit fields in the UART_O_LTIM register.
 //
 //*****************************************************************************
-#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value.
+#define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value
 #define UART_LTIM_TIMER_S       0
 
 //*****************************************************************************
@@ -327,7 +344,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the UART Register offsets.
+// The following are deprecated defines for the UART register offsets.
 //
 //*****************************************************************************
 #define UART_O_LCR_H            0x0000002C  // Line Control Register, HIGH byte
@@ -346,28 +363,32 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Data Register bits
+// The following are deprecated defines for the bit fields in the UART_O_DR
+// register.
 //
 //*****************************************************************************
 #define UART_DR_DATA_MASK       0x000000FF  // UART data
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Integer baud-rate divisor
+// The following are deprecated defines for the bit fields in the UART_O_IBRD
+// register.
 //
 //*****************************************************************************
 #define UART_IBRD_DIVINT_MASK   0x0000FFFF  // Integer baud-rate divisor
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Fractional baud-rate divisor
+// The following are deprecated defines for the bit fields in the UART_O_FBRD
+// register.
 //
 //*****************************************************************************
 #define UART_FBRD_DIVFRAC_MASK  0x0000003F  // Fractional baud-rate divisor
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Line Control Register High bits
+// The following are deprecated defines for the bit fields in the UART_O_LCR_H
+// register.
 //
 //*****************************************************************************
 #define UART_LCR_H_SPS          0x00000080  // Stick Parity Select
@@ -384,8 +405,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Interrupt FIFO Level Select
-// Register bits
+// The following are deprecated defines for the bit fields in the UART_O_IFLS
+// register.
 //
 //*****************************************************************************
 #define UART_IFLS_RX_MASK       0x00000038  // RX FIFO level mask
@@ -393,7 +414,8 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the Interrupt Clear Register bits
+// The following are deprecated defines for the bit fields in the UART_O_ICR
+// register.
 //
 //*****************************************************************************
 #define UART_RSR_ANY            (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \

bsp/lm3s/Libraries/inc/hw_udma.h

@@ -2,26 +2,23 @@
 //
 // hw_udma.h - Macros for use in accessing the UDMA registers.
 //
-// Copyright (c) 2007-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -30,7 +27,8 @@
 
 //*****************************************************************************
 //
-// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
 //
 //*****************************************************************************
 #define UDMA_STAT               0x400FF000  // DMA Status
@@ -38,7 +36,7 @@
 #define UDMA_CTLBASE            0x400FF008  // DMA Channel Control Base Pointer
 #define UDMA_ALTBASE            0x400FF00C  // DMA Alternate Channel Control
                                             // Base Pointer
-#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait on Request
+#define UDMA_WAITSTAT           0x400FF010  // DMA Channel Wait-on-Request
                                             // Status
 #define UDMA_SWREQ              0x400FF014  // DMA Channel Software Request
 #define UDMA_USEBURSTSET        0x400FF018  // DMA Channel Useburst Set
@@ -55,34 +53,14 @@
 #define UDMA_PRIOCLR            0x400FF03C  // DMA Channel Priority Clear
 #define UDMA_ERRCLR             0x400FF04C  // DMA Bus Error Clear
 #define UDMA_CHALT              0x400FF500  // DMA Channel Alternate Select
-#define UDMA_CHIS               0x400FF504  // DMA Channel Interrupt Status
-
-//*****************************************************************************
-//
-// Micro Direct Memory Access (uDMA) offsets.
-//
-//*****************************************************************************
-#define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
-                                            // Pointer
-#define UDMA_O_DSTENDP          0x00000004  // DMA Channel Destination Address
-                                            // End Pointer
-#define UDMA_O_CHCTL            0x00000008  // DMA Channel Control Word
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
-//
-//*****************************************************************************
-#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer.
-#define UDMA_SRCENDP_ADDR_S     0
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_STAT register.
 //
 //*****************************************************************************
-#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available DMA Channels Minus 1.
-#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine State.
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
 #define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
 #define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
 #define UDMA_STAT_STATE_RD_SRCENDP \
@@ -93,101 +71,37 @@
                                 0x00000040  // Reading source data
 #define UDMA_STAT_STATE_WR_DSTDAT \
                                 0x00000050  // Writing destination data
-#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for DMA request to clear
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
 #define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
 #define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
 #define UDMA_STAT_STATE_DONE    0x00000090  // Done
 #define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
-#define UDMA_STAT_MASTEN        0x00000001  // Master Enable.
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
 #define UDMA_STAT_DMACHANS_S    16
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
-//
-//*****************************************************************************
-#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer.
-#define UDMA_DSTENDP_ADDR_S     0
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_CFG register.
 //
 //*****************************************************************************
-#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable.
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_CTLBASE register.
 //
 //*****************************************************************************
-#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address.
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
 #define UDMA_CTLBASE_ADDR_S     10
 
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHCTL register.
-//
-//*****************************************************************************
-#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment.
-#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
-#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
-#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
-#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
-#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size.
-#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
-#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
-#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
-#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment.
-#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
-#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
-#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
-#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
-#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size.
-#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
-#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
-#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
-#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size.
-#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
-#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
-#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
-#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
-#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
-#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
-#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
-#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
-#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
-#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
-#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
-#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1).
-#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst.
-#define UDMA_CHCTL_XFERMODE_M   0x00000007  // DMA Transfer Mode.
-#define UDMA_CHCTL_XFERMODE_STOP \
-                                0x00000000  // Stop
-#define UDMA_CHCTL_XFERMODE_BASIC \
-                                0x00000001  // Basic
-#define UDMA_CHCTL_XFERMODE_AUTO \
-                                0x00000002  // Auto-Request
-#define UDMA_CHCTL_XFERMODE_PINGPONG \
-                                0x00000003  // Ping-Pong
-#define UDMA_CHCTL_XFERMODE_MEM_SG \
-                                0x00000004  // Memory Scatter-Gather
-#define UDMA_CHCTL_XFERMODE_MEM_SGA \
-                                0x00000005  // Alternate Memory Scatter-Gather
-#define UDMA_CHCTL_XFERMODE_PER_SG \
-                                0x00000006  // Peripheral Scatter-Gather
-#define UDMA_CHCTL_XFERMODE_PER_SGA \
-                                0x00000007  // Alternate Peripheral
-                                            // Scatter-Gather
-#define UDMA_CHCTL_XFERSIZE_S   4
-
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_ALTBASE register.
 //
 //*****************************************************************************
 #define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
-                                            // Pointer.
+                                            // Pointer
 #define UDMA_ALTBASE_ADDR_S     0
 
 //*****************************************************************************
@@ -195,14 +109,14 @@
 // The following are defines for the bit fields in the UDMA_WAITSTAT register.
 //
 //*****************************************************************************
-#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status.
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_SWREQ register.
 //
 //*****************************************************************************
-#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request.
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
 
 //*****************************************************************************
 //
@@ -210,7 +124,7 @@
 // register.
 //
 //*****************************************************************************
-#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set.
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
 
 //*****************************************************************************
 //
@@ -218,7 +132,7 @@
 // register.
 //
 //*****************************************************************************
-#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear.
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
 
 //*****************************************************************************
 //
@@ -226,7 +140,7 @@
 // register.
 //
 //*****************************************************************************
-#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set.
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
 
 //*****************************************************************************
 //
@@ -234,56 +148,56 @@
 // register.
 //
 //*****************************************************************************
-#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear.
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_ENASET register.
 //
 //*****************************************************************************
-#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set.
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_ENACLR register.
 //
 //*****************************************************************************
-#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable.
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_ALTSET register.
 //
 //*****************************************************************************
-#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set.
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_ALTCLR register.
 //
 //*****************************************************************************
-#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear.
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_PRIOSET register.
 //
 //*****************************************************************************
-#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set.
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_PRIOCLR register.
 //
 //*****************************************************************************
-#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear.
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
 
 //*****************************************************************************
 //
 // The following are defines for the bit fields in the UDMA_ERRCLR register.
 //
 //*****************************************************************************
-#define UDMA_ERRCLR_ERRCLR      0x00000001  // DMA Bus Error Status.
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
 
 //*****************************************************************************
 //
@@ -291,14 +205,91 @@
 //
 //*****************************************************************************
 #define UDMA_CHALT_M            0xFFFFFFFF  // Channel [n] Alternate Assignment
-                                            // Select.
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP          0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_O_DSTENDP          0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_O_CHCTL            0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S     0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the UDMA_CHIS register.
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
 //
 //*****************************************************************************
-#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status.
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
 
 //*****************************************************************************
 //
@@ -313,7 +304,7 @@
 // register.
 //
 //*****************************************************************************
-#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set.
+#define UDMA_ENASET_CHENSET_M   0xFFFFFFFF  // Channel [n] Enable Set
 
 #endif
 

bsp/lm3s/Libraries/inc/hw_watchdog.h

@@ -2,26 +2,23 @@
 //
 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
 //
-// Copyright (c) 2005-2009 Luminary Micro, Inc.  All rights reserved.
+// Copyright (c) 2005-2010 Texas Instruments Incorporated.  All rights reserved.
 // Software License Agreement
 // 
-// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
-// exclusively on LMI's microcontroller products.
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
 // 
-// The software is owned by LMI and/or its suppliers, and is protected under
-// applicable copyright laws.  All rights are reserved.  You may not combine
-// this software with "viral" open-source software in order to form a larger
-// program.  Any use in violation of the foregoing restrictions may subject
-// the user to criminal sanctions under applicable laws, as well as to civil
-// liability for the breach of the terms and conditions of this license.
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
 // 
-// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-// 
-// This is part of revision 4694 of the Stellaris Firmware Development Package.
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
 //
 //*****************************************************************************
 
@@ -33,86 +30,86 @@
 // The following are defines for the Watchdog Timer register offsets.
 //
 //*****************************************************************************
-#define WDT_O_LOAD              0x00000000  // Load register
-#define WDT_O_VALUE             0x00000004  // Current value register
-#define WDT_O_CTL               0x00000008  // Control register
-#define WDT_O_ICR               0x0000000C  // Interrupt clear register
-#define WDT_O_RIS               0x00000010  // Raw interrupt status register
-#define WDT_O_MIS               0x00000014  // Masked interrupt status register
-#define WDT_O_TEST              0x00000418  // Test register
-#define WDT_O_LOCK              0x00000C00  // Lock register
+#define WDT_O_LOAD              0x00000000  // Watchdog Load
+#define WDT_O_VALUE             0x00000004  // Watchdog Value
+#define WDT_O_CTL               0x00000008  // Watchdog Control
+#define WDT_O_ICR               0x0000000C  // Watchdog Interrupt Clear
+#define WDT_O_RIS               0x00000010  // Watchdog Raw Interrupt Status
+#define WDT_O_MIS               0x00000014  // Watchdog Masked Interrupt Status
+#define WDT_O_TEST              0x00000418  // Watchdog Test
+#define WDT_O_LOCK              0x00000C00  // Watchdog Lock
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_CTL register.
+// The following are defines for the bit fields in the WDT_O_LOAD register.
 //
 //*****************************************************************************
-#define WDT_CTL_RESEN           0x00000002  // Enable reset output
-#define WDT_CTL_INTEN           0x00000001  // Enable the WDT counter and int
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
-// WDT_MIS registers.
+// The following are defines for the bit fields in the WDT_O_VALUE register.
 //
 //*****************************************************************************
-#define WDT_INT_TIMEOUT         0x00000001  // Watchdog timer expired
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_TEST register.
+// The following are defines for the bit fields in the WDT_O_CTL register.
 //
 //*****************************************************************************
-#define WDT_TEST_STALL          0x00000100  // Watchdog stall enable
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_LOCK register.
+// The following are defines for the bit fields in the WDT_O_ICR register.
 //
 //*****************************************************************************
-#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock.
-#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
-#define WDT_LOCK_LOCKED         0x00000001  // Watchdog timer is locked
-#define WDT_LOCK_UNLOCKED       0x00000000  // Watchdog timer is unlocked
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_O_LOAD register.
+// The following are defines for the bit fields in the WDT_O_RIS register.
 //
 //*****************************************************************************
-#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value.
-#define WDT_LOAD_S              0
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_O_VALUE register.
+// The following are defines for the bit fields in the WDT_O_MIS register.
 //
 //*****************************************************************************
-#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value.
-#define WDT_VALUE_S             0
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_O_ICR register.
+// The following are defines for the bit fields in the WDT_O_TEST register.
 //
 //*****************************************************************************
-#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear.
-#define WDT_ICR_S               0
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_O_RIS register.
+// The following are defines for the bit fields in the WDT_O_LOCK register.
 //
 //*****************************************************************************
-#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status.
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
 
 //*****************************************************************************
 //
-// The following are defines for the bit fields in the WDT_O_MIS register.
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
 //
 //*****************************************************************************
-#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt
-                                            // Status.
+#define WDT_INT_TIMEOUT         0x00000001  // Watchdog timer expired
 
 //*****************************************************************************
 //
@@ -142,7 +139,7 @@
 
 //*****************************************************************************
 //
-// The following are deprecated defines for the bit fields in the WDT_TEST
+// The following are deprecated defines for the bit fields in the WDT_O_TEST
 // register.
 //
 //*****************************************************************************

bsp/lm3s/Libraries/inc/lm3s8962.h

@@ -0,0 +1,5034 @@
+//*****************************************************************************
+//
+// lm3s8962.h - LM3S8962 Register Definitions
+//
+// Copyright (c) 2007-2010 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+// 
+// This is part of revision 6459 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S8962_H__
+#define __LM3S8962_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R        (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R  ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R       (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R        (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R         (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R        (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R        (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R         (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R        (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R        (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R        (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R      (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R       (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R       (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R       (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R        (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R        (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R        (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R        (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R        (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R       (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R         (*((volatile unsigned long *)0x40004524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R  ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R       (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R        (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R         (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R        (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R        (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R         (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R        (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R        (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R        (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R      (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R       (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R       (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R       (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R        (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R        (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R        (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R        (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R        (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R       (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R         (*((volatile unsigned long *)0x40005524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R  ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R       (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R        (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R         (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R        (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R        (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R         (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R        (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R        (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R        (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R      (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R       (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R       (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R       (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R        (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R        (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R        (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R        (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R        (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R       (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R         (*((volatile unsigned long *)0x40006524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R  ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R       (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R        (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R         (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R        (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R        (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R         (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R        (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R        (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R        (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R      (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R       (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R       (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R       (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R        (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R        (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R        (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R        (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R        (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R       (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R         (*((volatile unsigned long *)0x40007524))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R              (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R              (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R               (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R               (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R             (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R               (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R              (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R              (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R              (*((volatile unsigned long *)0x40008020))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R              (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R             (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R             (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R              (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R            (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R            (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R            (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R            (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R             (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R            (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R              (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R             (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R             (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R             (*((volatile unsigned long *)0x4000C044))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R              (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R             (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R             (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R              (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R            (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R            (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R            (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R            (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R             (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R            (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R              (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R             (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R             (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R             (*((volatile unsigned long *)0x4000D044))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 MASTER)
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R       (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SOAR_R      (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_SCSR_R      (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MCS_R       (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_SDR_R       (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MDR_R       (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R      (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SIMR_R      (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_SRIS_R      (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MIMR_R      (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R      (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SMIS_R      (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_SICR_R      (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MMIS_R      (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R      (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R       (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 SLAVE)
+//
+//*****************************************************************************
+#define I2C0_SLAVE_MSA_R        (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SOAR_R       (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R       (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_MCS_R        (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R        (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MDR_R        (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_MTPR_R       (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SIMR_R       (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R       (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MIMR_R       (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_MRIS_R       (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SMIS_R       (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R       (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MMIS_R       (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_MICR_R       (*((volatile unsigned long *)0x4002081C))
+#define I2C0_SLAVE_MCR_R        (*((volatile unsigned long *)0x40020820))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R  ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R       (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R        (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R         (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R        (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R        (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R         (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R        (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R        (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R        (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R      (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R       (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R       (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R       (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R        (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R        (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R        (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R        (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R        (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R       (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R         (*((volatile unsigned long *)0x40024524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R  ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R       (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R        (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R         (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R        (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R        (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R         (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R        (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R        (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R        (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R      (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R       (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R       (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R       (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R        (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R        (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R        (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R        (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R        (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R       (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R         (*((volatile unsigned long *)0x40025524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R  ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R       (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R        (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R         (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R        (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R        (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R         (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R        (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R        (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R        (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R      (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R       (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R       (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R       (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R        (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R        (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R        (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R        (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R        (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R       (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R         (*((volatile unsigned long *)0x40026524))
+
+//*****************************************************************************
+//
+// PWM registers (PWM)
+//
+//*****************************************************************************
+#define PWM_CTL_R               (*((volatile unsigned long *)0x40028000))
+#define PWM_SYNC_R              (*((volatile unsigned long *)0x40028004))
+#define PWM_ENABLE_R            (*((volatile unsigned long *)0x40028008))
+#define PWM_INVERT_R            (*((volatile unsigned long *)0x4002800C))
+#define PWM_FAULT_R             (*((volatile unsigned long *)0x40028010))
+#define PWM_INTEN_R             (*((volatile unsigned long *)0x40028014))
+#define PWM_RIS_R               (*((volatile unsigned long *)0x40028018))
+#define PWM_ISC_R               (*((volatile unsigned long *)0x4002801C))
+#define PWM_STATUS_R            (*((volatile unsigned long *)0x40028020))
+#define PWM_0_CTL_R             (*((volatile unsigned long *)0x40028040))
+#define PWM_0_INTEN_R           (*((volatile unsigned long *)0x40028044))
+#define PWM_0_RIS_R             (*((volatile unsigned long *)0x40028048))
+#define PWM_0_ISC_R             (*((volatile unsigned long *)0x4002804C))
+#define PWM_0_LOAD_R            (*((volatile unsigned long *)0x40028050))
+#define PWM_0_COUNT_R           (*((volatile unsigned long *)0x40028054))
+#define PWM_0_CMPA_R            (*((volatile unsigned long *)0x40028058))
+#define PWM_0_CMPB_R            (*((volatile unsigned long *)0x4002805C))
+#define PWM_0_GENA_R            (*((volatile unsigned long *)0x40028060))
+#define PWM_0_GENB_R            (*((volatile unsigned long *)0x40028064))
+#define PWM_0_DBCTL_R           (*((volatile unsigned long *)0x40028068))
+#define PWM_0_DBRISE_R          (*((volatile unsigned long *)0x4002806C))
+#define PWM_0_DBFALL_R          (*((volatile unsigned long *)0x40028070))
+#define PWM_1_CTL_R             (*((volatile unsigned long *)0x40028080))
+#define PWM_1_INTEN_R           (*((volatile unsigned long *)0x40028084))
+#define PWM_1_RIS_R             (*((volatile unsigned long *)0x40028088))
+#define PWM_1_ISC_R             (*((volatile unsigned long *)0x4002808C))
+#define PWM_1_LOAD_R            (*((volatile unsigned long *)0x40028090))
+#define PWM_1_COUNT_R           (*((volatile unsigned long *)0x40028094))
+#define PWM_1_CMPA_R            (*((volatile unsigned long *)0x40028098))
+#define PWM_1_CMPB_R            (*((volatile unsigned long *)0x4002809C))
+#define PWM_1_GENA_R            (*((volatile unsigned long *)0x400280A0))
+#define PWM_1_GENB_R            (*((volatile unsigned long *)0x400280A4))
+#define PWM_1_DBCTL_R           (*((volatile unsigned long *)0x400280A8))
+#define PWM_1_DBRISE_R          (*((volatile unsigned long *)0x400280AC))
+#define PWM_1_DBFALL_R          (*((volatile unsigned long *)0x400280B0))
+#define PWM_2_CTL_R             (*((volatile unsigned long *)0x400280C0))
+#define PWM_2_INTEN_R           (*((volatile unsigned long *)0x400280C4))
+#define PWM_2_RIS_R             (*((volatile unsigned long *)0x400280C8))
+#define PWM_2_ISC_R             (*((volatile unsigned long *)0x400280CC))
+#define PWM_2_LOAD_R            (*((volatile unsigned long *)0x400280D0))
+#define PWM_2_COUNT_R           (*((volatile unsigned long *)0x400280D4))
+#define PWM_2_CMPA_R            (*((volatile unsigned long *)0x400280D8))
+#define PWM_2_CMPB_R            (*((volatile unsigned long *)0x400280DC))
+#define PWM_2_GENA_R            (*((volatile unsigned long *)0x400280E0))
+#define PWM_2_GENB_R            (*((volatile unsigned long *)0x400280E4))
+#define PWM_2_DBCTL_R           (*((volatile unsigned long *)0x400280E8))
+#define PWM_2_DBRISE_R          (*((volatile unsigned long *)0x400280EC))
+#define PWM_2_DBFALL_R          (*((volatile unsigned long *)0x400280F0))
+
+//*****************************************************************************
+//
+// QEI registers (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R              (*((volatile unsigned long *)0x4002C000))
+#define QEI0_STAT_R             (*((volatile unsigned long *)0x4002C004))
+#define QEI0_POS_R              (*((volatile unsigned long *)0x4002C008))
+#define QEI0_MAXPOS_R           (*((volatile unsigned long *)0x4002C00C))
+#define QEI0_LOAD_R             (*((volatile unsigned long *)0x4002C010))
+#define QEI0_TIME_R             (*((volatile unsigned long *)0x4002C014))
+#define QEI0_COUNT_R            (*((volatile unsigned long *)0x4002C018))
+#define QEI0_SPEED_R            (*((volatile unsigned long *)0x4002C01C))
+#define QEI0_INTEN_R            (*((volatile unsigned long *)0x4002C020))
+#define QEI0_RIS_R              (*((volatile unsigned long *)0x4002C024))
+#define QEI0_ISC_R              (*((volatile unsigned long *)0x4002C028))
+
+//*****************************************************************************
+//
+// QEI registers (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R              (*((volatile unsigned long *)0x4002D000))
+#define QEI1_STAT_R             (*((volatile unsigned long *)0x4002D004))
+#define QEI1_POS_R              (*((volatile unsigned long *)0x4002D008))
+#define QEI1_MAXPOS_R           (*((volatile unsigned long *)0x4002D00C))
+#define QEI1_LOAD_R             (*((volatile unsigned long *)0x4002D010))
+#define QEI1_TIME_R             (*((volatile unsigned long *)0x4002D014))
+#define QEI1_COUNT_R            (*((volatile unsigned long *)0x4002D018))
+#define QEI1_SPEED_R            (*((volatile unsigned long *)0x4002D01C))
+#define QEI1_INTEN_R            (*((volatile unsigned long *)0x4002D020))
+#define QEI1_RIS_R              (*((volatile unsigned long *)0x4002D024))
+#define QEI1_ISC_R              (*((volatile unsigned long *)0x4002D028))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R            (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R           (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R           (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R            (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R            (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R            (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R            (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R            (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R          (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R          (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R       (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R       (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R           (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R           (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R          (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R          (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R            (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R            (*((volatile unsigned long *)0x4003004C))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R            (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R           (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R           (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R            (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R            (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R            (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R            (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R            (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R          (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R          (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R       (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R       (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R           (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R           (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R          (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R          (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R            (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R            (*((volatile unsigned long *)0x4003104C))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R            (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R           (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R           (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R            (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R            (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R            (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R            (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R            (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R          (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R          (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R       (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R       (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R           (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R           (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R          (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R          (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R            (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R            (*((volatile unsigned long *)0x4003204C))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R            (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R           (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R           (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R            (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R            (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R            (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R            (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R            (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R          (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R          (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R       (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R       (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R           (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R           (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R          (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R          (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R            (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R            (*((volatile unsigned long *)0x4003304C))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R            (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R              (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R               (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R              (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R            (*((volatile unsigned long *)0x40038020))
+#define ADC0_PSSI_R             (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R              (*((volatile unsigned long *)0x40038030))
+#define ADC0_SSMUX0_R           (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSMUX1_R           (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSMUX2_R           (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSMUX3_R           (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile unsigned long *)0x400380AC))
+#define ADC0_TMLB_R             (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R            (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R            (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R          (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R         (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R          (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R           (*((volatile unsigned long *)0x4003C024))
+
+//*****************************************************************************
+//
+// CAN registers (CAN0)
+//
+//*****************************************************************************
+#define CAN0_CTL_R              (*((volatile unsigned long *)0x40040000))
+#define CAN0_STS_R              (*((volatile unsigned long *)0x40040004))
+#define CAN0_ERR_R              (*((volatile unsigned long *)0x40040008))
+#define CAN0_BIT_R              (*((volatile unsigned long *)0x4004000C))
+#define CAN0_INT_R              (*((volatile unsigned long *)0x40040010))
+#define CAN0_TST_R              (*((volatile unsigned long *)0x40040014))
+#define CAN0_BRPE_R             (*((volatile unsigned long *)0x40040018))
+#define CAN0_IF1CRQ_R           (*((volatile unsigned long *)0x40040020))
+#define CAN0_IF1CMSK_R          (*((volatile unsigned long *)0x40040024))
+#define CAN0_IF1MSK1_R          (*((volatile unsigned long *)0x40040028))
+#define CAN0_IF1MSK2_R          (*((volatile unsigned long *)0x4004002C))
+#define CAN0_IF1ARB1_R          (*((volatile unsigned long *)0x40040030))
+#define CAN0_IF1ARB2_R          (*((volatile unsigned long *)0x40040034))
+#define CAN0_IF1MCTL_R          (*((volatile unsigned long *)0x40040038))
+#define CAN0_IF1DA1_R           (*((volatile unsigned long *)0x4004003C))
+#define CAN0_IF1DA2_R           (*((volatile unsigned long *)0x40040040))
+#define CAN0_IF1DB1_R           (*((volatile unsigned long *)0x40040044))
+#define CAN0_IF1DB2_R           (*((volatile unsigned long *)0x40040048))
+#define CAN0_IF2CRQ_R           (*((volatile unsigned long *)0x40040080))
+#define CAN0_IF2CMSK_R          (*((volatile unsigned long *)0x40040084))
+#define CAN0_IF2MSK1_R          (*((volatile unsigned long *)0x40040088))
+#define CAN0_IF2MSK2_R          (*((volatile unsigned long *)0x4004008C))
+#define CAN0_IF2ARB1_R          (*((volatile unsigned long *)0x40040090))
+#define CAN0_IF2ARB2_R          (*((volatile unsigned long *)0x40040094))
+#define CAN0_IF2MCTL_R          (*((volatile unsigned long *)0x40040098))
+#define CAN0_IF2DA1_R           (*((volatile unsigned long *)0x4004009C))
+#define CAN0_IF2DA2_R           (*((volatile unsigned long *)0x400400A0))
+#define CAN0_IF2DB1_R           (*((volatile unsigned long *)0x400400A4))
+#define CAN0_IF2DB2_R           (*((volatile unsigned long *)0x400400A8))
+#define CAN0_TXRQ1_R            (*((volatile unsigned long *)0x40040100))
+#define CAN0_TXRQ2_R            (*((volatile unsigned long *)0x40040104))
+#define CAN0_NWDA1_R            (*((volatile unsigned long *)0x40040120))
+#define CAN0_NWDA2_R            (*((volatile unsigned long *)0x40040124))
+#define CAN0_MSG1INT_R          (*((volatile unsigned long *)0x40040140))
+#define CAN0_MSG2INT_R          (*((volatile unsigned long *)0x40040144))
+#define CAN0_MSG1VAL_R          (*((volatile unsigned long *)0x40040160))
+#define CAN0_MSG2VAL_R          (*((volatile unsigned long *)0x40040164))
+
+//*****************************************************************************
+//
+// Ethernet MAC registers (MAC)
+//
+//*****************************************************************************
+#define MAC_RIS_R               (*((volatile unsigned long *)0x40048000))
+#define MAC_IACK_R              (*((volatile unsigned long *)0x40048000))
+#define MAC_IM_R                (*((volatile unsigned long *)0x40048004))
+#define MAC_RCTL_R              (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R              (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R              (*((volatile unsigned long *)0x40048010))
+#define MAC_IA0_R               (*((volatile unsigned long *)0x40048014))
+#define MAC_IA1_R               (*((volatile unsigned long *)0x40048018))
+#define MAC_THR_R               (*((volatile unsigned long *)0x4004801C))
+#define MAC_MCTL_R              (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R               (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R              (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R              (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R                (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R                (*((volatile unsigned long *)0x40048038))
+#define MAC_TS_R                (*((volatile unsigned long *)0x4004803C))
+
+//*****************************************************************************
+//
+// Ethernet Controller PHY registers (MAC)
+//
+//*****************************************************************************
+#define PHY_MR0                 0x00000000  // Ethernet PHY Management Register
+                                            // 0 - Control
+#define PHY_MR1                 0x00000001  // Ethernet PHY Management Register
+                                            // 1 - Status
+#define PHY_MR2                 0x00000002  // Ethernet PHY Management Register
+                                            // 2 - PHY Identifier 1
+#define PHY_MR3                 0x00000003  // Ethernet PHY Management Register
+                                            // 3 - PHY Identifier 2
+#define PHY_MR4                 0x00000004  // Ethernet PHY Management Register
+                                            // 4 - Auto-Negotiation
+                                            // Advertisement
+#define PHY_MR5                 0x00000005  // Ethernet PHY Management Register
+                                            // 5 - Auto-Negotiation Link
+                                            // Partner Base Page Ability
+#define PHY_MR6                 0x00000006  // Ethernet PHY Management Register
+                                            // 6 - Auto-Negotiation Expansion
+#define PHY_MR16                0x00000010  // Ethernet PHY Management Register
+                                            // 16 - Vendor-Specific
+#define PHY_MR17                0x00000011  // Ethernet PHY Management Register
+                                            // 17 - Mode Control/Status
+#define PHY_MR18                0x00000012  // Ethernet PHY Management Register
+                                            // 18 - Diagnostic
+#define PHY_MR19                0x00000013  // Ethernet PHY Management Register
+                                            // 19 - Transceiver Control
+#define PHY_MR23                0x00000017  // Ethernet PHY Management Register
+                                            // 23 - LED Configuration
+#define PHY_MR24                0x00000018  // Ethernet PHY Management Register
+                                            // 24 -MDI/MDIX Control
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R              (*((volatile unsigned long *)0x400FC000))
+#define HIB_RTCM0_R             (*((volatile unsigned long *)0x400FC004))
+#define HIB_RTCM1_R             (*((volatile unsigned long *)0x400FC008))
+#define HIB_RTCLD_R             (*((volatile unsigned long *)0x400FC00C))
+#define HIB_CTL_R               (*((volatile unsigned long *)0x400FC010))
+#define HIB_IM_R                (*((volatile unsigned long *)0x400FC014))
+#define HIB_RIS_R               (*((volatile unsigned long *)0x400FC018))
+#define HIB_MIS_R               (*((volatile unsigned long *)0x400FC01C))
+#define HIB_IC_R                (*((volatile unsigned long *)0x400FC020))
+#define HIB_RTCT_R              (*((volatile unsigned long *)0x400FC024))
+#define HIB_DATA_R              (*((volatile unsigned long *)0x400FC030))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R             (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R             (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R             (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R           (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R            (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R          (*((volatile unsigned long *)0x400FD014))
+#define FLASH_USECRL_R          (*((volatile unsigned long *)0x400FE140))
+#define FLASH_USERDBG_R         (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R        (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R        (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_FMPRE0_R          (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R          (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R          (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R          (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R          (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R          (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R          (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R          (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R           (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R           (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R            (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R            (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R            (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R            (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R            (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_PBORCTL_R        (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_LDOPCTL_R        (*((volatile unsigned long *)0x400FE034))
+#define SYSCTL_SRCR0_R          (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R          (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R          (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R            (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R            (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R           (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R           (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R            (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R         (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_RCC2_R           (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_RCGC0_R          (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R          (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R          (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R          (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R          (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R          (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R          (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R          (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R          (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R     (*((volatile unsigned long *)0x400FE144))
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R         (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ST_CTRL_R          (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R        (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R       (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R           (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R              (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R              (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R             (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R             (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R            (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R            (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R          (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R          (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R          (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R          (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R             (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R             (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R             (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R             (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R             (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R             (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R             (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R             (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R             (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R             (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R            (*((volatile unsigned long *)0xE000E428))
+#define NVIC_CPUID_R            (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R         (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R           (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R            (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R         (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R         (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R         (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R         (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R         (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R     (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R       (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R      (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R       (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R          (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R       (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R         (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R         (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R       (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_BASE_R         (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R         (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_DBG_CTRL_R         (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R         (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R         (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R          (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R          (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
+#define GPIO_LOCK_KEY           0x1ACCE551  // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
+                                            // Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC             0x00000001  // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // PWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // PWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // PWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // PWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT      0x00010000  // Fault Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT        0x00010000  // Fault Interrupt Asserted
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT        0x00000001  // Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_X_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_X_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_X_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_X_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_X_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_X_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_X_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+                                0x00000800  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+                                0x00000200  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+                                0x00000080  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+                                0x00000020  // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+                                0x00000800  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+                                0x00000200  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+                                0x00000080  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+                                0x00000000  // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+                                0x00000020  // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_X_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
+                                            // counter configuration
+#define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
+                                            // function is controlled by bits
+                                            // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
+                                            // Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
+                                            // Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
+                                            // Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
+                                            // Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
+                                            // Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M    0xFFFF0000  // GPTM Timer A Interval Load
+                                            // Register High
+#define TIMER_TAILR_TAILRL_M    0x0000FFFF  // GPTM Timer A Interval Load
+                                            // Register Low
+#define TIMER_TAILR_TAILRH_S    16
+#define TIMER_TAILR_TAILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M    0x0000FFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_TBILRL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M  0xFFFF0000  // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M  0x0000FFFF  // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S  16
+#define TIMER_TAMATCHR_TAMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M  0x0000FFFF  // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMRL_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M        0xFFFF0000  // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M        0x0000FFFF  // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S        16
+#define TIMER_TAR_TARL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M        0x0000FFFF  // GPTM Timer B
+#define TIMER_TBR_TBRL_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
+#define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
+#define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
+#define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
+#define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
+#define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
+#define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
+#define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
+#define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
+#define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
+#define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
+#define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
+#define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
+#define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0x30000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x03000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00300000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x00030000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x00000003  // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x000003FF  // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x00000003  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x000003FF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x00003000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000300  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x00000030  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x00000003  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x000003FF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x00000003  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x000003FF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB             0x00000001  // Loopback Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT    0x00000020  // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF    0x00000010  // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS      0x00000008  // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M   0x00000007  // Analog Input Indicator
+#define ADC_SSFIFO_TMLB_CNT_S   6           // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S   0           // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+                                            // (VIREF)
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF1CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
+                                            // it is interpreted as 0x20, or
+                                            // object 32
+#define CAN_IF1CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF2CRQ_MNUM_RSVD    0x00000000  // 0 is not a valid message number;
+                                            // it is interpreted as 0x20, or
+                                            // object 32
+#define CAN_IF2CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT          0x00000040  // PHY Interrupt
+#define MAC_RIS_MDINT           0x00000020  // MII Transaction Complete
+#define MAC_RIS_RXER            0x00000010  // Receive Error
+#define MAC_RIS_FOV             0x00000008  // FIFO Overrun
+#define MAC_RIS_TXEMP           0x00000004  // Transmit FIFO Empty
+#define MAC_RIS_TXER            0x00000002  // Transmit Error
+#define MAC_RIS_RXINT           0x00000001  // Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT         0x00000040  // Clear PHY Interrupt
+#define MAC_IACK_MDINT          0x00000020  // Clear MII Transaction Complete
+#define MAC_IACK_RXER           0x00000010  // Clear Receive Error
+#define MAC_IACK_FOV            0x00000008  // Clear FIFO Overrun
+#define MAC_IACK_TXEMP          0x00000004  // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER           0x00000002  // Clear Transmit Error
+#define MAC_IACK_RXINT          0x00000001  // Clear Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM          0x00000040  // Mask PHY Interrupt
+#define MAC_IM_MDINTM           0x00000020  // Mask MII Transaction Complete
+#define MAC_IM_RXERM            0x00000010  // Mask Receive Error
+#define MAC_IM_FOVM             0x00000008  // Mask FIFO Overrun
+#define MAC_IM_TXEMPM           0x00000004  // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM            0x00000002  // Mask Transmit Error
+#define MAC_IM_RXINTM           0x00000001  // Mask Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO        0x00000010  // Clear Receive FIFO
+#define MAC_RCTL_BADCRC         0x00000008  // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS           0x00000004  // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL           0x00000002  // Enable Multicast Frames
+#define MAC_RCTL_RXEN           0x00000001  // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX         0x00000010  // Enable Duplex Mode
+#define MAC_TCTL_CRC            0x00000004  // Enable CRC Generation
+#define MAC_TCTL_PADEN          0x00000002  // Enable Packet Padding
+#define MAC_TCTL_TXEN           0x00000001  // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M       0xFFFFFFFF  // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M       0xFFFFFFFF  // Receive FIFO Data
+#define MAC_DATA_RXDATA_S       0
+#define MAC_DATA_TXDATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M       0xFF000000  // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M       0x00FF0000  // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M       0x0000FF00  // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M       0x000000FF  // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S       24
+#define MAC_IA0_MACOCT3_S       16
+#define MAC_IA0_MACOCT2_S       8
+#define MAC_IA0_MACOCT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M       0x0000FF00  // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M       0x000000FF  // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S       8
+#define MAC_IA1_MACOCT5_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M        0x0000003F  // Threshold Value
+#define MAC_THR_THRESH_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M       0x000000F8  // MII Register Address
+#define MAC_MCTL_WRITE          0x00000002  // MII Register Transaction Type
+#define MAC_MCTL_START          0x00000001  // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S       3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M           0x000000FF  // Clock Divider
+#define MAC_MDV_DIV_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M         0x0000FFFF  // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M         0x0000FFFF  // MII Register Receive Data
+#define MAC_MRXD_MDRX_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M            0x0000003F  // Number of Packets in Receive
+                                            // FIFO
+#define MAC_NP_NPR_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX            0x00000001  // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN             0x00000001  // Time Stamp Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET           0x00008000  // Reset Registers
+#define PHY_MR0_LOOPBK          0x00004000  // Loopback Mode
+#define PHY_MR0_SPEEDSL         0x00002000  // Speed Select
+#define PHY_MR0_ANEGEN          0x00001000  // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN           0x00000800  // Power Down
+#define PHY_MR0_ISO             0x00000400  // Isolate
+#define PHY_MR0_RANEG           0x00000200  // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX          0x00000100  // Set Duplex Mode
+#define PHY_MR0_COLT            0x00000080  // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F          0x00004000  // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H          0x00002000  // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F           0x00001000  // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H           0x00000800  // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS            0x00000040  // Management Frames with Preamble
+                                            // Suppressed
+#define PHY_MR1_ANEGC           0x00000020  // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT          0x00000010  // Remote Fault
+#define PHY_MR1_ANEGA           0x00000008  // Auto-Negotiation
+#define PHY_MR1_LINK            0x00000004  // Link Made
+#define PHY_MR1_JAB             0x00000002  // Jabber Condition
+#define PHY_MR1_EXTD            0x00000001  // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M           0x0000FFFF  // Organizationally Unique
+                                            // Identifier[21:6]
+#define PHY_MR2_OUI_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M           0x0000FC00  // Organizationally Unique
+                                            // Identifier[5:0]
+#define PHY_MR3_MN_M            0x000003F0  // Model Number
+#define PHY_MR3_RN_M            0x0000000F  // Revision Number
+#define PHY_MR3_OUI_S           10
+#define PHY_MR3_MN_S            4
+#define PHY_MR3_RN_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP              0x00008000  // Next Page
+#define PHY_MR4_RF              0x00002000  // Remote Fault
+#define PHY_MR4_A3              0x00000100  // Technology Ability Field [3]
+#define PHY_MR4_A2              0x00000080  // Technology Ability Field [2]
+#define PHY_MR4_A1              0x00000040  // Technology Ability Field [1]
+#define PHY_MR4_A0              0x00000020  // Technology Ability Field [0]
+#define PHY_MR4_S_M             0x0000001F  // Selector Field
+#define PHY_MR4_S_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP              0x00008000  // Next Page
+#define PHY_MR5_ACK             0x00004000  // Acknowledge
+#define PHY_MR5_RF              0x00002000  // Remote Fault
+#define PHY_MR5_A_M             0x00001FE0  // Technology Ability Field
+#define PHY_MR5_S_M             0x0000001F  // Selector Field
+#define PHY_MR5_S_8023          0x00000001  // IEEE Std 802.3
+#define PHY_MR5_S_8029          0x00000002  // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025          0x00000003  // IEEE Std 802.5
+#define PHY_MR5_S_1394          0x00000004  // IEEE Std 1394
+#define PHY_MR5_A_S             5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF             0x00000010  // Parallel Detection Fault
+#define PHY_MR6_LPNPA           0x00000008  // Link Partner is Next Page Able
+#define PHY_MR6_PRX             0x00000002  // New Page Received
+#define PHY_MR6_LPANEGA         0x00000001  // Link Partner is Auto-Negotiation
+                                            // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR           0x00008000  // Repeater Mode
+#define PHY_MR16_INPOL          0x00004000  // Interrupt Polarity
+#define PHY_MR16_TXHIM          0x00001000  // Transmit High Impedance Mode
+#define PHY_MR16_SQEI           0x00000800  // SQE Inhibit Testing
+#define PHY_MR16_NL10           0x00000400  // Natural Loopback Mode
+#define PHY_MR16_APOL           0x00000020  // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL         0x00000010  // Receive Data Polarity
+#define PHY_MR16_PCSBP          0x00000002  // PCS Bypass
+#define PHY_MR16_RXCC           0x00000001  // Receive Clock Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE      0x00008000  // Jabber Interrupt Enable
+#define PHY_MR17_RXER_IE        0x00004000  // Receive Error Interrupt Enable
+#define PHY_MR17_PRX_IE         0x00002000  // Page Received Interrupt Enable
+#define PHY_MR17_PDF_IE         0x00001000  // Parallel Detection Fault
+                                            // Interrupt Enable
+#define PHY_MR17_LPACK_IE       0x00000800  // LP Acknowledge Interrupt Enable
+#define PHY_MR17_LSCHG_IE       0x00000400  // Link Status Change Interrupt
+                                            // Enable
+#define PHY_MR17_RFAULT_IE      0x00000200  // Remote Fault Interrupt Enable
+#define PHY_MR17_ANEGCOMP_IE    0x00000100  // Auto-Negotiation Complete
+                                            // Interrupt Enable
+#define PHY_MR17_JABBER_INT     0x00000080  // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT       0x00000040  // Receive Error Interrupt
+#define PHY_MR17_PRX_INT        0x00000020  // Page Receive Interrupt
+#define PHY_MR17_PDF_INT        0x00000010  // Parallel Detection Fault
+                                            // Interrupt
+#define PHY_MR17_LPACK_INT      0x00000008  // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT      0x00000004  // Link Status Change Interrupt
+#define PHY_MR17_RFAULT_INT     0x00000002  // Remote Fault Interrupt
+#define PHY_MR17_ANEGCOMP_INT   0x00000001  // Auto-Negotiation Complete
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF          0x00001000  // Auto-Negotiation Failure
+#define PHY_MR18_DPLX           0x00000800  // Duplex Mode
+#define PHY_MR18_RATE           0x00000400  // Rate
+#define PHY_MR18_RXSD           0x00000200  // Receive Detection
+#define PHY_MR18_RX_LOCK        0x00000100  // Receive PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M          0x0000C000  // Transmit Amplitude Selection
+#define PHY_MR19_TXO_00DB       0x00000000  // Gain set for 0.0dB of insertion
+                                            // loss
+#define PHY_MR19_TXO_04DB       0x00004000  // Gain set for 0.4dB of insertion
+                                            // loss
+#define PHY_MR19_TXO_08DB       0x00008000  // Gain set for 0.8dB of insertion
+                                            // loss
+#define PHY_MR19_TXO_12DB       0x0000C000  // Gain set for 1.2dB of insertion
+                                            // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M         0x000000F0  // LED1 Source
+#define PHY_MR23_LED1_LINK      0x00000000  // Link OK
+#define PHY_MR23_LED1_RXTX      0x00000010  // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100       0x00000050  // 100BASE-TX mode
+#define PHY_MR23_LED1_10        0x00000060  // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX    0x00000070  // Full-Duplex
+#define PHY_MR23_LED1_LINKACT   0x00000080  // Link OK & Blink=RX or TX
+                                            // Activity
+#define PHY_MR23_LED0_M         0x0000000F  // LED0 Source
+#define PHY_MR23_LED0_LINK      0x00000000  // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX      0x00000001  // RX or TX Activity
+#define PHY_MR23_LED0_100       0x00000005  // 100BASE-TX mode
+#define PHY_MR23_LED0_10        0x00000006  // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX    0x00000007  // Full-Duplex
+#define PHY_MR23_LED0_LINKACT   0x00000008  // Link OK & Blink=RX or TX
+                                            // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE        0x00000080  // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW        0x00000040  // Auto-Switching Enable
+#define PHY_MR24_MDIX           0x00000020  // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM        0x00000010  // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M      0x0000000F  // Auto-Switching Seed
+#define PHY_MR24_MDIX_SD_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
+#define HIB_RTCC_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
+#define HIB_RTCM0_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M             0xFFFFFFFF  // RTC Match 1
+#define HIB_RTCM1_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
+#define HIB_RTCLD_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_LOWBATEN        0x00000020  // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN          0x00000010  // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL          0x00000004  // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT1          0x00000002  // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT1         0x00000002  // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT1         0x00000002  // RTC Alert 1 Masked Interrupt
+                                            // Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Masked
+                                            // Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Clear
+#define HIB_IC_RTCALT1          0x00000002  // RTC Alert1 Masked Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
+#define HIB_RTCT_TRIM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
+#define HIB_DATA_RTD_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M          0x000000FF  // Microsecond Reload Value
+#define FLASH_USECRL_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW        0x80000000  // User Debug Not Written
+#define FLASH_USERDBG_DATA_M    0x7FFFFFFC  // User Data
+#define FLASH_USERDBG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_USERDBG_DBG0      0x00000001  // Debug Control 0
+#define FLASH_USERDBG_DATA_S    2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW       0x80000000  // Not Written
+#define FLASH_USERREG0_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW       0x80000000  // Not Written
+#define FLASH_USERREG1_DATA_M   0x7FFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE      0x00000800
+#define FLASH_ERASE_SIZE        0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_FURY  0x00010000  // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
+#define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
+                                            // register format
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
+#define SYSCTL_DID1_FAM_STELLARIS \
+                                0x00000000  // Stellaris family of
+                                            // microcontollers, that is, all
+                                            // devices with external part
+                                            // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
+#define SYSCTL_DID1_PRTNO_8962  0x00A60000  // LM3S8962
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
+                                            // to 70C)
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+                                            // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
+                                            // to 105C)
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_64KB  0x00FF0000  // 64 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM          0x00100000  // PWM Module Present
+#define SYSCTL_DC1_ADC          0x00010000  // ADC Module Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_ADCSPD_M     0x00000300  // Max ADC Speed
+#define SYSCTL_DC1_ADCSPD_500K  0x00000200  // 500K samples/second
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT          0x00000008  // Watchdog Timer Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M        0x0000003F  // LDO Output Voltage
+#define SYSCTL_LDOPCTL_2_50V    0x00000000  // 2.50
+#define SYSCTL_LDOPCTL_2_45V    0x00000001  // 2.45
+#define SYSCTL_LDOPCTL_2_40V    0x00000002  // 2.40
+#define SYSCTL_LDOPCTL_2_35V    0x00000003  // 2.35
+#define SYSCTL_LDOPCTL_2_30V    0x00000004  // 2.30
+#define SYSCTL_LDOPCTL_2_25V    0x00000005  // 2.25
+#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // 2.75
+#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // 2.70
+#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // 2.65
+#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // 2.60
+#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM        0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC        0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT        0x00000008  // WDT Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0      0x40000000  // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0      0x10000000  // MAC0 Reset Control
+#define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT         0x00000008  // Watchdog Timer Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000003C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ    0x00000000  // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040  // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ    0x00000080  // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0  // 2.4576 MHz
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140  // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M       0x00003FE0  // PLL F Value
+#define SYSCTL_PLLCFG_R_M       0x0000001F  // PLL R Value
+#define SYSCTL_PLLCFG_F_S       5
+#define SYSCTL_PLLCFG_R_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5   0x02000000  // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6   0x02800000  // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7   0x03000000  // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8   0x03800000  // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9   0x04000000  // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10  0x04800000  // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11  0x05000000  // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12  0x05800000  // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13  0x06000000  // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14  0x06800000  // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15  0x07000000  // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16  0x07800000  // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17  0x08000000  // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18  0x08800000  // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19  0x09000000  // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20  0x09800000  // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21  0x0A000000  // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22  0x0A800000  // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23  0x0B000000  // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24  0x0B800000  // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25  0x0C000000  // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26  0x0C800000  // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27  0x0D000000  // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28  0x0D800000  // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29  0x0E000000  // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30  0x0E800000  // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31  0x0F000000  // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32  0x0F800000  // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33  0x10000000  // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34  0x10800000  // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35  0x11000000  // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36  0x11800000  // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37  0x12000000  // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38  0x12800000  // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39  0x13000000  // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40  0x13800000  // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41  0x14000000  // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42  0x14800000  // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43  0x15000000  // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44  0x15800000  // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45  0x16000000  // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46  0x16800000  // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47  0x17000000  // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48  0x17800000  // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49  0x18000000  // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50  0x18800000  // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51  0x19000000  // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52  0x19800000  // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53  0x1A000000  // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54  0x1A800000  // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55  0x1B000000  // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56  0x1B800000  // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57  0x1C000000  // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58  0x1C800000  // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59  0x1D000000  // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60  0x1D800000  // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61  0x1E000000  // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT        0x00000008  // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M   0x00000300  // ADC Sample Speed
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000  // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100  // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200  // 500K samples/second
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT        0x00000008  // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM        0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC        0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT        0x00000008  // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0      0x40000000  // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0      0x10000000  // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5   0x02000000  // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6   0x02800000  // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7   0x03000000  // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8   0x03800000  // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9   0x04000000  // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10  0x04800000  // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11  0x05000000  // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12  0x05800000  // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13  0x06000000  // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14  0x06800000  // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15  0x07000000  // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16  0x07800000  // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17  0x08000000  // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18  0x08800000  // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19  0x09000000  // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20  0x09800000  // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21  0x0A000000  // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22  0x0A800000  // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23  0x0B000000  // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24  0x0B800000  // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25  0x0C000000  // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26  0x0C800000  // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27  0x0D000000  // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28  0x0D800000  // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29  0x0E000000  // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30  0x0E800000  // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31  0x0F000000  // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32  0x0F800000  // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33  0x10000000  // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34  0x10800000  // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35  0x11000000  // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36  0x11800000  // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37  0x12000000  // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38  0x12800000  // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39  0x13000000  // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40  0x13800000  // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41  0x14000000  // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42  0x14800000  // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43  0x15000000  // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44  0x15800000  // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45  0x16000000  // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46  0x16800000  // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47  0x17000000  // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48  0x17800000  // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49  0x18000000  // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50  0x18800000  // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51  0x19000000  // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52  0x19800000  // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53  0x1A000000  // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54  0x1A800000  // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55  0x1B000000  // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56  0x1B800000  // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57  0x1C000000  // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58  0x1C800000  // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59  0x1D000000  // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60  0x1D800000  // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61  0x1E000000  // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62  0x1E800000  // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63  0x1F000000  // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_D_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF       0x80000000  // No reference clock
+#define NVIC_ST_CAL_SKEW        0x40000000  // Clock skew
+#define NVIC_ST_CAL_ONEMS_M     0x00FFFFFF  // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable
+#define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT59          0x08000000  // Interrupt 59 enable
+#define NVIC_EN1_INT58          0x04000000  // Interrupt 58 enable
+#define NVIC_EN1_INT57          0x02000000  // Interrupt 57 enable
+#define NVIC_EN1_INT56          0x01000000  // Interrupt 56 enable
+#define NVIC_EN1_INT55          0x00800000  // Interrupt 55 enable
+#define NVIC_EN1_INT54          0x00400000  // Interrupt 54 enable
+#define NVIC_EN1_INT53          0x00200000  // Interrupt 53 enable
+#define NVIC_EN1_INT52          0x00100000  // Interrupt 52 enable
+#define NVIC_EN1_INT51          0x00080000  // Interrupt 51 enable
+#define NVIC_EN1_INT50          0x00040000  // Interrupt 50 enable
+#define NVIC_EN1_INT49          0x00020000  // Interrupt 49 enable
+#define NVIC_EN1_INT48          0x00010000  // Interrupt 48 enable
+#define NVIC_EN1_INT47          0x00008000  // Interrupt 47 enable
+#define NVIC_EN1_INT46          0x00004000  // Interrupt 46 enable
+#define NVIC_EN1_INT45          0x00002000  // Interrupt 45 enable
+#define NVIC_EN1_INT44          0x00001000  // Interrupt 44 enable
+#define NVIC_EN1_INT43          0x00000800  // Interrupt 43 enable
+#define NVIC_EN1_INT42          0x00000400  // Interrupt 42 enable
+#define NVIC_EN1_INT41          0x00000200  // Interrupt 41 enable
+#define NVIC_EN1_INT40          0x00000100  // Interrupt 40 enable
+#define NVIC_EN1_INT39          0x00000080  // Interrupt 39 enable
+#define NVIC_EN1_INT38          0x00000040  // Interrupt 38 enable
+#define NVIC_EN1_INT37          0x00000020  // Interrupt 37 enable
+#define NVIC_EN1_INT36          0x00000010  // Interrupt 36 enable
+#define NVIC_EN1_INT35          0x00000008  // Interrupt 35 enable
+#define NVIC_EN1_INT34          0x00000004  // Interrupt 34 enable
+#define NVIC_EN1_INT33          0x00000002  // Interrupt 33 enable
+#define NVIC_EN1_INT32          0x00000001  // Interrupt 32 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable
+#define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT59         0x08000000  // Interrupt 59 disable
+#define NVIC_DIS1_INT58         0x04000000  // Interrupt 58 disable
+#define NVIC_DIS1_INT57         0x02000000  // Interrupt 57 disable
+#define NVIC_DIS1_INT56         0x01000000  // Interrupt 56 disable
+#define NVIC_DIS1_INT55         0x00800000  // Interrupt 55 disable
+#define NVIC_DIS1_INT54         0x00400000  // Interrupt 54 disable
+#define NVIC_DIS1_INT53         0x00200000  // Interrupt 53 disable
+#define NVIC_DIS1_INT52         0x00100000  // Interrupt 52 disable
+#define NVIC_DIS1_INT51         0x00080000  // Interrupt 51 disable
+#define NVIC_DIS1_INT50         0x00040000  // Interrupt 50 disable
+#define NVIC_DIS1_INT49         0x00020000  // Interrupt 49 disable
+#define NVIC_DIS1_INT48         0x00010000  // Interrupt 48 disable
+#define NVIC_DIS1_INT47         0x00008000  // Interrupt 47 disable
+#define NVIC_DIS1_INT46         0x00004000  // Interrupt 46 disable
+#define NVIC_DIS1_INT45         0x00002000  // Interrupt 45 disable
+#define NVIC_DIS1_INT44         0x00001000  // Interrupt 44 disable
+#define NVIC_DIS1_INT43         0x00000800  // Interrupt 43 disable
+#define NVIC_DIS1_INT42         0x00000400  // Interrupt 42 disable
+#define NVIC_DIS1_INT41         0x00000200  // Interrupt 41 disable
+#define NVIC_DIS1_INT40         0x00000100  // Interrupt 40 disable
+#define NVIC_DIS1_INT39         0x00000080  // Interrupt 39 disable
+#define NVIC_DIS1_INT38         0x00000040  // Interrupt 38 disable
+#define NVIC_DIS1_INT37         0x00000020  // Interrupt 37 disable
+#define NVIC_DIS1_INT36         0x00000010  // Interrupt 36 disable
+#define NVIC_DIS1_INT35         0x00000008  // Interrupt 35 disable
+#define NVIC_DIS1_INT34         0x00000004  // Interrupt 34 disable
+#define NVIC_DIS1_INT33         0x00000002  // Interrupt 33 disable
+#define NVIC_DIS1_INT32         0x00000001  // Interrupt 32 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend
+#define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT59        0x08000000  // Interrupt 59 pend
+#define NVIC_PEND1_INT58        0x04000000  // Interrupt 58 pend
+#define NVIC_PEND1_INT57        0x02000000  // Interrupt 57 pend
+#define NVIC_PEND1_INT56        0x01000000  // Interrupt 56 pend
+#define NVIC_PEND1_INT55        0x00800000  // Interrupt 55 pend
+#define NVIC_PEND1_INT54        0x00400000  // Interrupt 54 pend
+#define NVIC_PEND1_INT53        0x00200000  // Interrupt 53 pend
+#define NVIC_PEND1_INT52        0x00100000  // Interrupt 52 pend
+#define NVIC_PEND1_INT51        0x00080000  // Interrupt 51 pend
+#define NVIC_PEND1_INT50        0x00040000  // Interrupt 50 pend
+#define NVIC_PEND1_INT49        0x00020000  // Interrupt 49 pend
+#define NVIC_PEND1_INT48        0x00010000  // Interrupt 48 pend
+#define NVIC_PEND1_INT47        0x00008000  // Interrupt 47 pend
+#define NVIC_PEND1_INT46        0x00004000  // Interrupt 46 pend
+#define NVIC_PEND1_INT45        0x00002000  // Interrupt 45 pend
+#define NVIC_PEND1_INT44        0x00001000  // Interrupt 44 pend
+#define NVIC_PEND1_INT43        0x00000800  // Interrupt 43 pend
+#define NVIC_PEND1_INT42        0x00000400  // Interrupt 42 pend
+#define NVIC_PEND1_INT41        0x00000200  // Interrupt 41 pend
+#define NVIC_PEND1_INT40        0x00000100  // Interrupt 40 pend
+#define NVIC_PEND1_INT39        0x00000080  // Interrupt 39 pend
+#define NVIC_PEND1_INT38        0x00000040  // Interrupt 38 pend
+#define NVIC_PEND1_INT37        0x00000020  // Interrupt 37 pend
+#define NVIC_PEND1_INT36        0x00000010  // Interrupt 36 pend
+#define NVIC_PEND1_INT35        0x00000008  // Interrupt 35 pend
+#define NVIC_PEND1_INT34        0x00000004  // Interrupt 34 pend
+#define NVIC_PEND1_INT33        0x00000002  // Interrupt 33 pend
+#define NVIC_PEND1_INT32        0x00000001  // Interrupt 32 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT59      0x08000000  // Interrupt 59 unpend
+#define NVIC_UNPEND1_INT58      0x04000000  // Interrupt 58 unpend
+#define NVIC_UNPEND1_INT57      0x02000000  // Interrupt 57 unpend
+#define NVIC_UNPEND1_INT56      0x01000000  // Interrupt 56 unpend
+#define NVIC_UNPEND1_INT55      0x00800000  // Interrupt 55 unpend
+#define NVIC_UNPEND1_INT54      0x00400000  // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT53      0x00200000  // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT52      0x00100000  // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT51      0x00080000  // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT50      0x00040000  // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT49      0x00020000  // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT48      0x00010000  // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT47      0x00008000  // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT46      0x00004000  // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT45      0x00002000  // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT44      0x00001000  // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT43      0x00000800  // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT42      0x00000400  // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT41      0x00000200  // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT40      0x00000100  // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT39      0x00000080  // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT38      0x00000040  // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT37      0x00000020  // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT36      0x00000010  // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT35      0x00000008  // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT34      0x00000004  // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT33      0x00000002  // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT32      0x00000001  // Interrupt 32 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active
+#define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT59      0x08000000  // Interrupt 59 active
+#define NVIC_ACTIVE1_INT58      0x04000000  // Interrupt 58 active
+#define NVIC_ACTIVE1_INT57      0x02000000  // Interrupt 57 active
+#define NVIC_ACTIVE1_INT56      0x01000000  // Interrupt 56 active
+#define NVIC_ACTIVE1_INT55      0x00800000  // Interrupt 55 active
+#define NVIC_ACTIVE1_INT54      0x00400000  // Interrupt 54 active
+#define NVIC_ACTIVE1_INT53      0x00200000  // Interrupt 53 active
+#define NVIC_ACTIVE1_INT52      0x00100000  // Interrupt 52 active
+#define NVIC_ACTIVE1_INT51      0x00080000  // Interrupt 51 active
+#define NVIC_ACTIVE1_INT50      0x00040000  // Interrupt 50 active
+#define NVIC_ACTIVE1_INT49      0x00020000  // Interrupt 49 active
+#define NVIC_ACTIVE1_INT48      0x00010000  // Interrupt 48 active
+#define NVIC_ACTIVE1_INT47      0x00008000  // Interrupt 47 active
+#define NVIC_ACTIVE1_INT46      0x00004000  // Interrupt 46 active
+#define NVIC_ACTIVE1_INT45      0x00002000  // Interrupt 45 active
+#define NVIC_ACTIVE1_INT44      0x00001000  // Interrupt 44 active
+#define NVIC_ACTIVE1_INT43      0x00000800  // Interrupt 43 active
+#define NVIC_ACTIVE1_INT42      0x00000400  // Interrupt 42 active
+#define NVIC_ACTIVE1_INT41      0x00000200  // Interrupt 41 active
+#define NVIC_ACTIVE1_INT40      0x00000100  // Interrupt 40 active
+#define NVIC_ACTIVE1_INT39      0x00000080  // Interrupt 39 active
+#define NVIC_ACTIVE1_INT38      0x00000040  // Interrupt 38 active
+#define NVIC_ACTIVE1_INT37      0x00000020  // Interrupt 37 active
+#define NVIC_ACTIVE1_INT36      0x00000010  // Interrupt 36 active
+#define NVIC_ACTIVE1_INT35      0x00000008  // Interrupt 35 active
+#define NVIC_ACTIVE1_INT34      0x00000004  // Interrupt 34 active
+#define NVIC_ACTIVE1_INT33      0x00000002  // Interrupt 33 active
+#define NVIC_ACTIVE1_INT32      0x00000001  // Interrupt 32 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask
+#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask
+#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask
+#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask
+#define NVIC_PRI0_INT3_S        24
+#define NVIC_PRI0_INT2_S        16
+#define NVIC_PRI0_INT1_S        8
+#define NVIC_PRI0_INT0_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask
+#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask
+#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask
+#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask
+#define NVIC_PRI1_INT7_S        24
+#define NVIC_PRI1_INT6_S        16
+#define NVIC_PRI1_INT5_S        8
+#define NVIC_PRI1_INT4_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask
+#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask
+#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask
+#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask
+#define NVIC_PRI2_INT11_S       24
+#define NVIC_PRI2_INT10_S       16
+#define NVIC_PRI2_INT9_S        8
+#define NVIC_PRI2_INT8_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask
+#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask
+#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask
+#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask
+#define NVIC_PRI3_INT15_S       24
+#define NVIC_PRI3_INT14_S       16
+#define NVIC_PRI3_INT13_S       8
+#define NVIC_PRI3_INT12_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask
+#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask
+#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask
+#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask
+#define NVIC_PRI4_INT19_S       24
+#define NVIC_PRI4_INT18_S       16
+#define NVIC_PRI4_INT17_S       8
+#define NVIC_PRI4_INT16_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask
+#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask
+#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask
+#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask
+#define NVIC_PRI5_INT23_S       24
+#define NVIC_PRI5_INT22_S       16
+#define NVIC_PRI5_INT21_S       8
+#define NVIC_PRI5_INT20_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask
+#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask
+#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask
+#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask
+#define NVIC_PRI6_INT27_S       24
+#define NVIC_PRI6_INT26_S       16
+#define NVIC_PRI6_INT25_S       8
+#define NVIC_PRI6_INT24_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask
+#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask
+#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask
+#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask
+#define NVIC_PRI7_INT31_S       24
+#define NVIC_PRI7_INT30_S       16
+#define NVIC_PRI7_INT29_S       8
+#define NVIC_PRI7_INT28_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xFF000000  // Interrupt 35 priority mask
+#define NVIC_PRI8_INT34_M       0x00FF0000  // Interrupt 34 priority mask
+#define NVIC_PRI8_INT33_M       0x0000FF00  // Interrupt 33 priority mask
+#define NVIC_PRI8_INT32_M       0x000000FF  // Interrupt 32 priority mask
+#define NVIC_PRI8_INT35_S       24
+#define NVIC_PRI8_INT34_S       16
+#define NVIC_PRI8_INT33_S       8
+#define NVIC_PRI8_INT32_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xFF000000  // Interrupt 39 priority mask
+#define NVIC_PRI9_INT38_M       0x00FF0000  // Interrupt 38 priority mask
+#define NVIC_PRI9_INT37_M       0x0000FF00  // Interrupt 37 priority mask
+#define NVIC_PRI9_INT36_M       0x000000FF  // Interrupt 36 priority mask
+#define NVIC_PRI9_INT39_S       24
+#define NVIC_PRI9_INT38_S       16
+#define NVIC_PRI9_INT37_S       8
+#define NVIC_PRI9_INT36_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xFF000000  // Interrupt 43 priority mask
+#define NVIC_PRI10_INT42_M      0x00FF0000  // Interrupt 42 priority mask
+#define NVIC_PRI10_INT41_M      0x0000FF00  // Interrupt 41 priority mask
+#define NVIC_PRI10_INT40_M      0x000000FF  // Interrupt 40 priority mask
+#define NVIC_PRI10_INT43_S      24
+#define NVIC_PRI10_INT42_S      16
+#define NVIC_PRI10_INT41_S      8
+#define NVIC_PRI10_INT40_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // Set pending SysTick interrupt
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // Clear pending SysTick interrupt
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE        0x20000000  // Vector table base
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset
+#define NVIC_VTABLE_OFFSET_S    8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info
+#define NVIC_APINT_VECT_RESET   0x00000001  // System reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler
+#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler
+#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler
+#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler
+#define NVIC_SYS_PRI1_USAGE_S   16
+#define NVIC_SYS_PRI1_BUS_S     8
+#define NVIC_SYS_PRI1_MEM_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler
+#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers
+#define NVIC_SYS_PRI2_SVC_S     24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler
+#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler
+#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler
+#define NVIC_SYS_PRI3_TICK_S    24
+#define NVIC_SYS_PRI3_PENDSV_S  16
+#define NVIC_SYS_PRI3_DEBUG_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU default region in priv mode
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base address mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid
+#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number
+#define NVIC_MPU_BASE_ADDR_S    8
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M         0xFFFF0000  // Attributes
+#define NVIC_MPU_ATTR_AP_NO_NO  0x00000000  // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type extension mask
+#define NVIC_MPU_ATTR_AP_RW_NO  0x01000000  // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO  0x02000000  // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW  0x03000000  // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO  0x05000000  // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO  0x06000000  // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access permissions mask
+#define NVIC_MPU_ATTR_XN        0x10000000  // Execute disable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Sub-region disable mask
+#define NVIC_MPU_ATTR_SRD_0     0x00000100  // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1     0x00000200  // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2     0x00000400  // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3     0x00000800  // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4     0x00001000  // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5     0x00002000  // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6     0x00004000  // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7     0x00008000  // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region size mask
+#define NVIC_MPU_ATTR_SIZE_32B  0x00000008  // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B  0x0000000A  // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C  // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E  // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010  // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K   0x00000012  // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K   0x00000014  // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K   0x00000016  // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K   0x00000018  // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K  0x0000001A  // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K  0x0000001C  // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K  0x0000001E  // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020  // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022  // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024  // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M   0x00000026  // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M   0x00000028  // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M   0x0000002A  // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M   0x0000002C  // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M  0x0000002E  // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M  0x00000030  // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M  0x00000032  // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034  // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036  // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038  // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G   0x0000003A  // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G   0x0000003C  // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G   0x0000003E  // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+                                0x02000000  // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+                                0x01000000  // Core has executed insruction
+                                            // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+                                0x00000020  // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger
+#define NVIC_SW_TRIG_INTID_S    0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the Watchdog
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R         (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R        (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R          (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R          (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R          (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R          (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R         (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R         (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC             0x00000001  // Clear Interrupt
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS            0x00000001  // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM             0x00000001  // Interrupt Mask
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled. register.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M          0x000003C0  // Continuous Sample Counter
+#define ADC_TMLB_CONT           0x00000020  // Continuation Sample Indicator
+#define ADC_TMLB_DIFF           0x00000010  // Differential Sample Indicator
+#define ADC_TMLB_TS             0x00000008  // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M          0x00000007  // Analog Input Indicator
+#define ADC_TMLB_CNT_S          6           // Sample counter shift
+#define ADC_TMLB_MUX_S          0           // Input channel number shift
+
+//*****************************************************************************
+//
+// Deprecated defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_ACTSS_R             (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R               (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R                (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R               (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R             (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R              (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R             (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R             (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R              (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R               (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R            (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R            (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R           (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R          (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R            (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R            (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R           (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R          (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R            (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R            (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R           (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R          (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R            (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R            (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R           (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R          (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R              (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M       0xFFFF0000  // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S       16
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // SOIC package
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // QFP package
+
+//*****************************************************************************
+//
+// Deprecated defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_MPU_R              (*((volatile unsigned long *)0xE000ED9C))
+
+#endif
+
+#endif // __LM3S8962_H__