废弃rt_hw_kernel_phys_to_virt, 加入rt_ioremap、rt_ioremap_nocache、rt_iormap_cached及rt_iounmap

bsp/imx6ull-100ask-smart/drivers/drv_timer.c

@@ -96,8 +96,8 @@ volatile unsigned int *CCM_CLPCR;
 
 static void imx6ull_enable_clk_in_waitmode(void)
 {
-    CCM_CLPCR = rt_hw_kernel_phys_to_virt((void*)0x20C4054, 4);
-    *CCM_CLPCR &= ~(1<<5 | 0x3);
+    CCM_CLPCR = rt_ioremap((void*)0x20C4054, 4);
+    *CCM_CLPCR &= ~((1 << 5) | 0x3);
 }
 
 static void system_counter_clk_source_init(void)
@@ -112,7 +112,7 @@ static void system_counter_init(void)
 #define CONFIG_SC_TIMER_CLK  8000000
 
     /* imx6ull, enable system counter */
-    struct sctr_regs *sctr = (struct sctr_regs *)rt_hw_kernel_phys_to_virt((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs));
+    struct sctr_regs *sctr = (struct sctr_regs *)rt_ioremap((void*)SCTR_BASE_ADDR, sizeof(struct sctr_regs));
     unsigned long val, freq;
 
     freq = CONFIG_SC_TIMER_CLK;

bsp/imx6ull-100ask-smart/drivers/serial.c

@@ -75,11 +75,11 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
     volatile unsigned int *CCM_CSCDR1;
     volatile unsigned int *CCM_CCGR5;
 
-    IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA     = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0084, 4);
-    IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA     = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0088, 4);
-    IOMUXC_UART1_RX_DATA_SELECT_INPUT       = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x20E0624, 4);
-    CCM_CSCDR1 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C4024, 4);
-    CCM_CCGR5 = (volatile unsigned int *)rt_hw_kernel_phys_to_virt((void *)0x020C407C, 4);
+    IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA     = (volatile unsigned int *)rt_ioremap((void *)0x20E0084, 4);
+    IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA     = (volatile unsigned int *)rt_ioremap((void *)0x20E0088, 4);
+    IOMUXC_UART1_RX_DATA_SELECT_INPUT       = (volatile unsigned int *)rt_ioremap((void *)0x20E0624, 4);
+    CCM_CSCDR1 = (volatile unsigned int *)rt_ioremap((void *)0x020C4024, 4);
+    CCM_CCGR5 = (volatile unsigned int *)rt_ioremap((void *)0x020C407C, 4);
 
     struct hw_uart_device * uart = (struct hw_uart_device *)serial->parent.user_data;
 
@@ -220,7 +220,7 @@ int rt_hw_uart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
 #ifdef RT_USING_UART0
-    _uart0_device.hw_base = (uint32_t)rt_hw_kernel_phys_to_virt((void*)_uart0_device.hw_base, 0x1000);
+    _uart0_device.hw_base = (uint32_t)rt_ioremap((void*)_uart0_device.hw_base, 0x1000);
     uart = &_uart0_device;
 
     _serial0.ops    = &_uart_ops;
@@ -234,7 +234,7 @@ int rt_hw_uart_init(void)
 #endif
 
 #ifdef RT_USING_UART1
-    _uart1_device.hw_base = (uint32_t)rt_hw_kernel_phys_to_virt((void*)_uart1_device.hw_base, 0x1000);
+    _uart1_device.hw_base = (uint32_t)rt_ioremap((void*)_uart1_device.hw_base, 0x1000);
     uart = &_uart1_device;
     _serial1.ops = &_uart_ops;
     _serial1.config = config;

bsp/qemu-vexpress-a9/drivers/board.h

@@ -20,6 +20,7 @@
 #include "vexpress_a9.h"
 
 #include "mmu.h"
+#include "ioremap.h"
 
 #if defined(__CC_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;

bsp/qemu-vexpress-a9/drivers/drv_clcd.c

@@ -49,7 +49,7 @@ static rt_err_t drv_clcd_init(struct rt_device *device)
 {
     struct drv_clcd_device *lcd = CLCD_DEVICE(device);
 
-    lcd = lcd; /* nothing, right now */
+    (void)lcd; /* nothing, right now */
     return RT_EOK;
 }
 
@@ -63,7 +63,7 @@ static rt_err_t drv_clcd_control(struct rt_device *device, int cmd, void *args)
         {
             struct rt_device_rect_info *info = (struct rt_device_rect_info*)args;
 
-            info = info; /* nothing, right now */
+            (void)info; /* nothing, right now */
             rt_kprintf("update screen...\n");
         }
         break;
@@ -156,9 +156,9 @@ int drv_clcd_hw_init(void)
     memset(_lcd.fb, 0xff, _lcd.width * _lcd.height * 2);
 #endif
 
-    plio = (PL111MMIO *)rt_hw_kernel_phys_to_virt((void*)PL111_IOBASE, 0x1000);
+    plio = (PL111MMIO *)rt_ioremap((void*)PL111_IOBASE, 0x1000);
 
-    plio->tim0 = 0x3F1F3C00 | ((CLCD_WIDTH/16 - 1) << 2);
+    plio->tim0 = 0x3F1F3C00 | ((CLCD_WIDTH / 16 - 1) << 2);
     plio->tim1 = 0x080B6000 | (CLCD_HEIGHT - 1);
 
     plio->upbase = (uint32_t)_lcd.fb;

bsp/qemu-vexpress-a9/drivers/drv_keyboard.c

@@ -425,7 +425,7 @@ int rt_hw_keyboard_init(void)
     virtual_addr_t virt;
     int irq = KEYBOARD_IRQ_NUM;
 
-    virt = (virtual_addr_t)rt_hw_kernel_phys_to_virt((void*)KEYBOARD_ADDRESS, 0x1000);
+    virt = (virtual_addr_t)rt_ioremap((void*)KEYBOARD_ADDRESS, 0x1000);
 
     id = (((read32(virt + 0xfec) & 0xff) << 24) |
                 ((read32(virt + 0xfe8) & 0xff) << 16) |

bsp/qemu-vexpress-a9/drivers/drv_mouse.c

@@ -230,7 +230,7 @@ int rt_hw_mouse_init(void)
     virtual_addr_t virt;
     int irq = MOUSE_IRQ_NUM;
 
-    virt = (virtual_addr_t)rt_hw_kernel_phys_to_virt((void*)MOUSE_ADDRESS, 0x1000);
+    virt = (virtual_addr_t)rt_ioremap((void*)MOUSE_ADDRESS, 0x1000);
 
     id = (((read32(virt + 0xfec) & 0xff) << 24) |
                 ((read32(virt + 0xfe8) & 0xff) << 16) |

bsp/qemu-vexpress-a9/drivers/drv_sdio.c

@@ -286,13 +286,13 @@ static rt_err_t sdhci_pl180_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
 
     if(clock)
     {
-        temp = read32(pdat->virt + PL180_CLOCK) | (0x1<<8);
-        temp = temp; // skip warning
+        temp = read32(pdat->virt + PL180_CLOCK) | (0x1 << 8);
+        (void)temp; // skip warning
         write32(pdat->virt + PL180_CLOCK, 0x100);
     }
     else
     {
-        //write32(pdat->virt + PL180_CLOCK, read32(pdat->virt + PL180_CLOCK) & (~(0x1<<8)));
+        //write32(pdat->virt + PL180_CLOCK, read32(pdat->virt + PL180_CLOCK) & (~(0x1 << 8)));
     }
     return RT_EOK;
 }
@@ -410,8 +410,8 @@ int pl180_init(void)
         goto err;
     }
     rt_memset(sdhci, 0, sizeof(struct sdhci_t));
-    
-    virt = (rt_uint32_t)rt_hw_kernel_phys_to_virt((void*)MMC_BASE_ADDR, 0x1000);
+
+    virt = (rt_uint32_t)rt_ioremap((void*)MMC_BASE_ADDR, 0x1000);
 
     id = (((read32((virt + 0xfec)) & 0xff) << 24) |
                 ((read32((virt + 0xfe8)) & 0xff) << 16) |

bsp/qemu-vexpress-a9/drivers/drv_smc911x.c

@@ -1,5 +1,6 @@
 #include <board.h>
 #include <rtthread.h>
+#include <rtdevice.h>
 #include <automac.h>
 #include <netif/ethernetif.h>
 #include <lwipopts.h>
@@ -499,7 +500,7 @@ int smc911x_emac_hw_init(void)
 {
     rt_memset(&_emac, 0x0, sizeof(_emac));
 
-    _emac.iobase = (uint32_t)rt_hw_kernel_phys_to_virt((void*)VEXPRESS_ETH_BASE, 0x1000);
+    _emac.iobase = (uint32_t)rt_ioremap((void*)VEXPRESS_ETH_BASE, 0x1000);
     _emac.irqno  = IRQ_VEXPRESS_A9_ETH;
 
     if (smc911x_detect_chip(&_emac))

bsp/qemu-vexpress-a9/drivers/drv_timer.c

@@ -74,8 +74,8 @@ int rt_hw_timer_init(void)
 {
     rt_uint32_t val;
 
-    sys_ctrl = (void*)rt_hw_kernel_phys_to_virt((void*)REALVIEW_SCTL_BASE, 0x1000);
-    timer_hw_base = (void*)rt_hw_kernel_phys_to_virt((void*)REALVIEW_TIMER2_3_BASE, 0x1000);
+    sys_ctrl = (void*)rt_ioremap((void*)REALVIEW_SCTL_BASE, 0x1000);
+    timer_hw_base = (void*)rt_ioremap((void*)REALVIEW_TIMER2_3_BASE, 0x1000);
 
     SYS_CTRL |= REALVIEW_REFCLK;
 
@@ -103,7 +103,7 @@ void timer_init(int timer, unsigned int preload)
 
     if (timer == 0)
     {
-        timer01_hw_base = (void*)rt_hw_kernel_phys_to_virt((void*)TIMER01_HW_BASE_PHY, 0x1000);
+        timer01_hw_base = (void*)rt_ioremap((void*)TIMER01_HW_BASE_PHY, 0x1000);
         /* Setup Timer0 for generating irq */
         val = TIMER_CTRL(TIMER01_HW_BASE);
         val &= ~TIMER_CTRL_ENABLE;
@@ -117,7 +117,7 @@ void timer_init(int timer, unsigned int preload)
     }
     else
     {
-        timer23_hw_base = (void*)rt_hw_kernel_phys_to_virt((void*)TIMER23_HW_BASE_PHY, 0x1000);
+        timer23_hw_base = (void*)rt_ioremap((void*)TIMER23_HW_BASE_PHY, 0x1000);
         /* Setup Timer1 for generating irq */
         val = TIMER_CTRL(TIMER23_HW_BASE);
         val &= ~TIMER_CTRL_ENABLE;

bsp/qemu-vexpress-a9/drivers/serial.c

@@ -153,7 +153,7 @@ int rt_hw_uart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
 #ifdef RT_USING_UART0
-    _uart0_device.hw_base = (uint32_t)rt_hw_kernel_phys_to_virt((void*)_uart0_device.hw_base, 0x1000);
+    _uart0_device.hw_base = (uint32_t)rt_ioremap((void*)_uart0_device.hw_base, 0x1000);
     uart = &_uart0_device;
 
     _serial0.ops    = &_uart_ops;
@@ -169,7 +169,7 @@ int rt_hw_uart_init(void)
 #endif
 
 #ifdef RT_USING_UART1
-    _uart1_device.hw_base = (uint32_t)rt_hw_kernel_phys_to_virt((void*)_uart1_device.hw_base, 0x1000);
+    _uart1_device.hw_base = (uint32_t)rt_ioremap((void*)_uart1_device.hw_base, 0x1000);
     uart = &_uart1_device;
     _serial1.ops = &_uart_ops;
     _serial1.config = config;

bsp/raspberry-pi/raspi4-32/driver/board.c

@@ -126,50 +126,50 @@ void rt_hw_board_init(void)
 #endif
 
     /* map peripheral address to virtual address */
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
 
     //gpio
-    gpio_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)GPIO_BASE_ADDR, 0x1000);
+    gpio_base_addr = (size_t)rt_ioremap((void*)GPIO_BASE_ADDR, 0x1000);
     //uart
-    //uart_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART_BASE, 0x1000);
+    //uart_base_addr = (size_t)rt_ioremap((void*)UART_BASE, 0x1000);
     //aux
-    //aux_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)AUX_BASE_ADDR, 0x1000);
+    //aux_addr = (size_t)rt_ioremap((void*)AUX_BASE_ADDR, 0x1000);
     //timer
-    arm_timer_base = (size_t)rt_hw_kernel_phys_to_virt((void*)ARM_TIMER_BASE, 0x1000);
+    arm_timer_base = (size_t)rt_ioremap((void*)ARM_TIMER_BASE, 0x1000);
     //gic
-    //gic_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)GIC_V2_BASE, 0x10000);
+    //gic_base_addr = (size_t)rt_ioremap((void*)GIC_V2_BASE, 0x10000);
     //pactl
-    pactl_cs_base = (size_t)rt_hw_kernel_phys_to_virt((void*)PACTL_CS_ADDR, 0x1000);
+    pactl_cs_base = (size_t)rt_ioremap((void*)PACTL_CS_ADDR, 0x1000);
 
     //stimer
-    stimer_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)STIMER_BASE, 0x1000);
+    stimer_base_addr = (size_t)rt_ioremap((void*)STIMER_BASE, 0x1000);
 
     //mmc2_base_addr 
-    mmc2_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)MMC2_BASE_ADDR, 0x1000);
+    mmc2_base_addr = (size_t)rt_ioremap((void*)MMC2_BASE_ADDR, 0x1000);
 
     //mbox
-    videocore_mbox = (size_t)rt_hw_kernel_phys_to_virt((void*)VIDEOCORE_MBOX, 0x1000);
+    videocore_mbox = (size_t)rt_ioremap((void*)VIDEOCORE_MBOX, 0x1000);
 
     //mbox msg
-    mbox_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)MBOX_ADDR, 0x1000);
+    mbox_addr = (size_t)rt_ioremap((void*)MBOX_ADDR, 0x1000);
     mbox = (volatile unsigned int *)mbox_addr;
 
     //wdt
-    wdt_base_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)WDT_BASE, 0x1000);
+    wdt_base_addr = (size_t)rt_ioremap((void*)WDT_BASE, 0x1000);
 
     //mac
-    mac_reg_base_addr = (void *)rt_hw_kernel_phys_to_virt((void*)MAC_REG, 0x80000);
+    mac_reg_base_addr = (void *)rt_ioremap((void*)MAC_REG, 0x80000);
 
     //eth data
-    eth_send_no_cache = (void *)rt_hw_kernel_phys_to_virt((void*)SEND_DATA_NO_CACHE, 0x200000);
-    eth_recv_no_cache = (void *)rt_hw_kernel_phys_to_virt((void*)RECV_DATA_NO_CACHE, 0x200000);
+    eth_send_no_cache = (void *)rt_ioremap((void*)SEND_DATA_NO_CACHE, 0x200000);
+    eth_recv_no_cache = (void *)rt_ioremap((void*)RECV_DATA_NO_CACHE, 0x200000);
 
     /* initialize hardware interrupt */
     rt_hw_interrupt_init();
 
-#ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-#endif
     /* initialize uart */
     rt_hw_uart_init();
 

bsp/raspberry-pi/raspi4-32/driver/board.h

@@ -14,6 +14,7 @@
 #include <stdint.h>
 #include "raspi4.h"
 #include "mmu.h"
+#include "ioremap.h"
 
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;

bsp/raspberry-pi/raspi4-32/driver/drv_uart.c

@@ -296,7 +296,7 @@ int rt_hw_uart_init(void)
     _serial0.ops    = &_uart_ops;
     _serial0.config = config;
 
-    uart0_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART0_BASE, 0x1000);
+    uart0_addr = (size_t)rt_ioremap((void*)UART0_BASE, 0x1000);
     uart0->hw_base = uart0_addr;
 
     
@@ -315,7 +315,7 @@ int rt_hw_uart_init(void)
     _serial1.ops    = &_uart_ops;
     _serial1.config = config;
     
-    uart1->hw_base = (size_t)rt_hw_kernel_phys_to_virt((void*)AUX_BASE, 0x1000);
+    uart1->hw_base = (size_t)rt_ioremap((void*)AUX_BASE, 0x1000);
 
     /* register UART1 device */
     rt_hw_serial_register(&_serial1, "uart1",
@@ -331,7 +331,7 @@ int rt_hw_uart_init(void)
     _serial3.ops    = &_uart_ops;
     _serial3.config = config;
 
-    uart3_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART3_BASE, 0x1000);
+    uart3_addr = (size_t)rt_ioremap((void*)UART3_BASE, 0x1000);
     uart3->hw_base = uart3_addr;
 
     /* register UART3 device */
@@ -348,7 +348,7 @@ int rt_hw_uart_init(void)
     _serial4.ops    = &_uart_ops;
     _serial4.config = config;
 
-    uart4_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART4_BASE, 0x1000);
+    uart4_addr = (size_t)rt_ioremap((void*)UART4_BASE, 0x1000);
     uart4->hw_base = uart4_addr;
 
     /* register UART4 device */
@@ -365,7 +365,7 @@ int rt_hw_uart_init(void)
     _serial5.ops    = &_uart_ops;
     _serial5.config = config;
 
-    uart5_addr = (size_t)rt_hw_kernel_phys_to_virt((void*)UART5_BASE, 0x1000);
+    uart5_addr = (size_t)rt_ioremap((void*)UART5_BASE, 0x1000);
     uart5->hw_base = uart5_addr;
 
     /* register UART5 device */

components/lwp/arch/arm/cortex-a/arch_user_space_init.c

@@ -60,4 +60,12 @@ void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors)
     rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)((char*)vectors + 0x1000 - kuser_sz), kuser_sz);
     rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void*)((char*)vectors + 0x1000 - kuser_sz), kuser_sz);
 }
+
+void arch_user_space_vtable_free(struct rt_lwp *lwp)
+{
+    if (lwp && lwp->mmu_info.vtable)
+    {
+        rt_pages_free(lwp->mmu_info.vtable, 2);
+    }
+}
 #endif

components/lwp/arch/arm/cortex-a/lwp_arch.h

@@ -27,6 +27,7 @@ extern "C" {
 #endif
 
 int arch_user_space_init(struct rt_lwp *lwp);
+void arch_user_space_vtable_free(struct rt_lwp *lwp);
 void *arch_kernel_mmu_table_get(void);
 void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors);
 int arch_expand_user_stack(void *addr);

components/lwp/arch/risc-v/virt64/arch_user_space_init.c

@@ -45,4 +45,11 @@ void *arch_kernel_mmu_table_get(void)
     return (void*)((char*)MMUTable);
 }
 
+void arch_user_space_vtable_free(struct rt_lwp *lwp)
+{
+    if (lwp && lwp->mmu_info.vtable)
+    {
+        rt_pages_free(lwp->mmu_info.vtable, 0);
+    }
+}
 #endif

components/lwp/arch/risc-v/virt64/lwp_arch.h

@@ -29,6 +29,7 @@ extern "C" {
 #endif
 
 int arch_user_space_init(struct rt_lwp *lwp);
+void arch_user_space_vtable_free(struct rt_lwp *lwp);
 void *arch_kernel_mmu_table_get(void);
 void arch_kuser_init(rt_mmu_info *mmu_info, void *vectors);
 int arch_expand_user_stack(void *addr);

components/lwp/ioremap.c

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-05-06     Jesven       first version
+ */
+#include <rtthread.h>
+#include <rthw.h>
+
+#ifdef RT_USING_USERSPACE
+#include <mmu.h>
+#include <lwp_mm_area.h>
+#endif
+
+#include <ioremap.h>
+
+#ifdef RT_USING_USERSPACE
+static struct lwp_avl_struct *k_map_area;
+extern rt_mmu_info mmu_info;
+
+static void _iounmap_range(void *addr, size_t size)
+{
+    void *va = RT_NULL, *pa = RT_NULL;
+    int i = 0;
+
+    for (va = addr, i = 0; i < size; va = (void *)((char *)va + ARCH_PAGE_SIZE), i += ARCH_PAGE_SIZE)
+    {
+        pa = rt_hw_mmu_v2p(&mmu_info, va);
+        if (pa)
+        {
+            rt_hw_mmu_unmap(&mmu_info, va, ARCH_PAGE_SIZE);
+        }
+    }
+}
+
+static void *_ioremap_type(void *p_addr, size_t size, int type)
+{
+    rt_base_t level;
+    void *v_addr = NULL;
+    size_t attr;
+
+    switch (type)
+    {
+    case MM_AREA_TYPE_PHY:
+        attr = MMU_MAP_K_DEVICE;
+        break;
+    case MM_AREA_TYPE_PHY_CACHED:
+        attr = MMU_MAP_K_RWCB;
+        break;
+    default:
+        return v_addr;
+    }
+
+    level = rt_hw_interrupt_disable();
+    v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, attr);
+    if (v_addr)
+    {
+        int ret = lwp_map_area_insert(&k_map_area, (size_t)v_addr, size, type);
+        if (ret != 0)
+        {
+            _iounmap_range(v_addr, size);
+            v_addr = NULL;
+        }
+    }
+    rt_hw_interrupt_enable(level);
+    return v_addr;
+}
+
+void *rt_ioremap(void *p_addr, size_t size)
+{
+    return _ioremap_type(p_addr, size, MM_AREA_TYPE_PHY);
+}
+
+void *rt_ioremap_nocache(void *p_addr, size_t size)
+{
+    return _ioremap_type(p_addr, size, MM_AREA_TYPE_PHY);
+}
+
+void *rt_ioremap_cached(void *p_addr, size_t size)
+{
+    return _ioremap_type(p_addr, size, MM_AREA_TYPE_PHY_CACHED);
+}
+
+#else
+
+void *rt_ioremap(void *p_addr, size_t size)
+{
+    return p_addr;
+}
+
+void *rt_ioremap_nocache(void *paddr, size_t size)
+{
+    return p_addr;
+}
+
+void *rt_ioremap_cached(void *paddr, size_t size)
+{
+    return p_addr;
+}
+
+#endif
+
+void rt_iounmap(volatile void *vaddr)
+{
+#ifdef RT_USING_USERSPACE
+    rt_base_t level;
+    struct lwp_avl_struct *ma_avl_node;
+
+    level = rt_hw_interrupt_disable();
+    ma_avl_node = lwp_map_find(k_map_area, (size_t)vaddr);
+    if (ma_avl_node)
+    {
+        struct rt_mm_area_struct *ma = (struct rt_mm_area_struct *)ma_avl_node->data;
+
+        _iounmap_range((void *)ma->addr, ma->size);
+        lwp_map_area_remove(&k_map_area, (size_t)vaddr);
+    }
+    rt_hw_interrupt_enable(level);
+#endif
+}

components/lwp/ioremap.h

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-05-06     Jesven       first version
+ */
+#ifndef  __IOREMAP_H__
+#define  __IOREMAP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void *rt_ioremap(void *paddr, size_t size);
+
+void *rt_ioremap_nocache(void *paddr, size_t size);
+
+void *rt_ioremap_cached(void *paddr, size_t size);
+
+void rt_iounmap(volatile void *addr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*__LWP_IOREMAP_H__*/

components/lwp/lwp_user_mm.c

@@ -115,7 +115,6 @@ static void unmap_range(struct rt_lwp *lwp, void *addr, size_t size, int pa_need
 void lwp_unmap_user_space(struct rt_lwp *lwp)
 {
     struct lwp_avl_struct *node = RT_NULL;
-    rt_mmu_info *m_info = &lwp->mmu_info;
 
     while ((node = lwp_map_find_first(lwp->map_area)) != 0)
     {
@@ -138,11 +137,7 @@ void lwp_unmap_user_space(struct rt_lwp *lwp)
         lwp_map_area_remove(&lwp->map_area, ma->addr);
     }
 
-#ifdef ARCH_RISCV
-    rt_pages_free(m_info->vtable, 0);
-#else
-    rt_pages_free(m_info->vtable, 2);
-#endif
+    arch_user_space_vtable_free(lwp);
 }
 
 static void *_lwp_map_user(struct rt_lwp *lwp, void *map_va, size_t map_size, int text)
@@ -315,11 +310,14 @@ static void *_lwp_map_user_type(struct rt_lwp *lwp, void *map_va, void *map_pa,
     }
 
     va = rt_hw_mmu_map(m_info, map_va, map_pa, map_size, attr);
-    ret = lwp_map_area_insert(&lwp->map_area, (size_t)va, map_size, type);
-    if (ret != 0)
+    if (va)
     {
-        unmap_range(lwp, va, map_size, 0);
-        return 0;
+        ret = lwp_map_area_insert(&lwp->map_area, (size_t)va, map_size, type);
+        if (ret != 0)
+        {
+            unmap_range(lwp, va, map_size, 0);
+            return 0;
+        }
     }
     return va;
 }

libcpu/arm/cortex-a/mmu.c

@@ -751,42 +751,6 @@ void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size)
     rt_hw_cpu_tlb_invalidate();
 }
 
-
-extern void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr);
-//va --> pa
-// void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size)
-void *rt_hw_kernel_virt_to_phys(void *v_addr)
-{
-    void *p_addr = 0;
-    #ifdef RT_USING_USERSPACE
-    rt_base_t level;
-
-    extern rt_mmu_info mmu_info;
-    level = rt_hw_interrupt_disable();
-    p_addr = _rt_hw_mmu_v2p(&mmu_info, v_addr);
-    rt_hw_interrupt_enable(level);
-    #else
-    p_addr = v_addr;
-    #endif
-
-    return p_addr;
-}
-
-//pa --> va
-void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size)
-{
-    void *v_addr = 0;
-
-    #ifdef RT_USING_USERSPACE
-    extern rt_mmu_info mmu_info;
-    v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, MMU_MAP_K_RW);
-    #else
-    v_addr = p_addr;
-    #endif
-
-    return v_addr;
-}
-
 #ifdef RT_USING_USERSPACE
 void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr)
 {

libcpu/arm/cortex-a/mmu.h

@@ -108,7 +108,4 @@ void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t att
 void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size);
 void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr);
 
-void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size);
-void *rt_hw_kernel_virt_to_phys(void *v_addr);
-
 #endif