feat : format code

1. ref https://github.com/mysterywolf/formatting

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/arm_common_tables.h

@@ -77,7 +77,7 @@
    * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
    * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
    * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.
-   * 
+   *
    *
    * Examples
    * --------

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armcc.h

@@ -58,9 +58,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   static __forceinline
-#endif           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __declspec(noreturn)
 #endif
@@ -443,7 +443,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
                    __schedule_barrier();\
                 } while (0U)
 
-                  
+
 /**
   \brief   Reverse byte order (32 bit)
   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_armclang.h

@@ -43,9 +43,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_compiler.h

@@ -46,9 +46,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -767,7 +767,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
+#if __has_builtin(__builtin_arm_get_fpscr)
 // Re-enable using built-in when GCC has been fixed
 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/core/cmsis_iccarm.h

@@ -21,13 +21,13 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
- 
+
 #ifndef ARM_MPU_ARMV7_H
 #define ARM_MPU_ARMV7_H
 
@@ -79,12 +79,12 @@
 
 /**
 * MPU Memory Access Attributes
-* 
+*
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
 * \param IsShareable       Region is shareable between multiple bus masters.
 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/  
+*/
 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
   ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
    (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
@@ -93,7 +93,7 @@
 
 /**
 * MPU Region Attribute and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
@@ -104,10 +104,10 @@
   ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
    (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
    (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
-  
+
 /**
 * MPU Region Attribute and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -116,7 +116,7 @@
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
 * \param SubRegionDisable  Sub-region disable field.
 * \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/                         
+*/
 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
   ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
 
@@ -126,7 +126,7 @@
 *  - Shareable
 *  - Non-cacheable
 *  - Non-bufferable
-*/ 
+*/
 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
 
 /**
@@ -137,7 +137,7 @@
 *  - Bufferable (if shareable) or non-bufferable (if non-shareable)
 *
 * \param IsShareable Configures the device memory as shareable or non-shareable.
-*/ 
+*/
 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
 
 /**
@@ -150,7 +150,7 @@
 * \param OuterCp Configures the outer cache policy.
 * \param InnerCp Configures the inner cache policy.
 * \param IsShareable Configures the memory as shareable or non-shareable.
-*/ 
+*/
 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
 
 /**
@@ -181,7 +181,7 @@ typedef struct {
   uint32_t RBAR; //!< The region base address register value (RBAR)
   uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
@@ -219,7 +219,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 /** Configure an MPU region.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 {
   MPU->RBAR = rbar;
@@ -230,7 +230,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
 {
   MPU->RNR = rnr;
@@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
-  for (i = 0U; i < len; ++i) 
+  for (i = 0U; i < len; ++i)
   {
     dst[i] = src[i];
   }
@@ -256,7 +256,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   while (cnt > MPU_TYPE_RALIASES) {

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/n32g45x.h

@@ -759,7 +759,7 @@ typedef struct
     __IO uint32_t   ECC2;           /*offset = 0x74*/
 
     uint32_t   RESERVED2[2];        /*offset = 0x78*/
-    
+
     __IO uint32_t   CTRL3;          /*offset = 0x80*/
     __IO uint32_t   STS3;           /*offset = 0x84*/
     __IO uint32_t   CMEMTM3;        /*offset = 0x88*/
@@ -1140,10 +1140,10 @@ typedef struct
     __IO uint32_t DAT29;
     __IO uint32_t DAT30;
     __IO uint32_t DAT31;
-    __IO uint32_t RESERVED2;	/*DAT32-DAT35 is reserved*/
-    __IO uint32_t RESERVED3;	/*DAT32-DAT35 is reserved*/
-    __IO uint32_t RESERVED4;	/*DAT32-DAT35 is reserved*/
-    __IO uint32_t RESERVED5;	/*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED2;    /*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED3;    /*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED4;    /*DAT32-DAT35 is reserved*/
+    __IO uint32_t RESERVED5;    /*DAT32-DAT35 is reserved*/
     __IO uint32_t RS_DELAY;
     __IO uint32_t ENH_CTRL0;
     __IO uint32_t DDR_TXDE;
@@ -1172,7 +1172,7 @@ typedef struct
     __IO uint32_t RESERVED;
     __IO uint32_t ANA_CTRL;
     __IO uint32_t ANA_SEL;
-	
+
 #if (TSC_USED_NEW_SDK)
     __IO uint32_t RESR[3];
     __IO uint32_t THRHD[24];
@@ -7671,13 +7671,13 @@ typedef struct
 #define USART_CTRL1_UEN      ((uint16_t)0x2000) /*!< USART Enable */
 
 /******************  Bit definition for USART_CTRL2 register  *******************/
-#define USART_CTRL2_ADDR    	((uint16_t)0x000F) /*!< Address of the USART node */
-#define USART_CTRL2_LINBDL  	((uint16_t)0x0020) /*!< LIN Break Detection Length */
-#define USART_CTRL2_LINBDIEN	((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CTRL2_LBCLK   	((uint16_t)0x0100) /*!< Last Bit Clock pulse */
-#define USART_CTRL2_CLKPHA  	((uint16_t)0x0200) /*!< Clock Phase */
-#define USART_CTRL2_CLKPOL  	((uint16_t)0x0400) /*!< Clock Polarity */
-#define USART_CTRL2_CLKEN   	((uint16_t)0x0800) /*!< Clock Enable */
+#define USART_CTRL2_ADDR        ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CTRL2_LINBDL      ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CTRL2_LINBDIEN    ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CTRL2_LBCLK       ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CTRL2_CLKPHA      ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CTRL2_CLKPOL      ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CTRL2_CLKEN       ((uint16_t)0x0800) /*!< Clock Enable */
 
 #define USART_CTRL2_STPB   ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
 #define USART_CTRL2_STPB_0 ((uint16_t)0x1000) /*!< Bit 0 */
@@ -8335,7 +8335,7 @@ typedef struct
 
 /******************************************************************************/
 /*                                                                            */
-/*                                 QSPI Registers           	              */
+/*                                 QSPI Registers                             */
 /*                                                                            */
 /******************************************************************************/
 
@@ -8346,58 +8346,58 @@ typedef struct
 #define QSPI_CTRL0_DFS_2                            ((uint32_t)0x00000004) /*!< Bit 2 */
 #define QSPI_CTRL0_DFS_3                            ((uint32_t)0x00000008) /*!< Bit 3 */
 #define QSPI_CTRL0_DFS_4                            ((uint32_t)0x00000010) /*!< Bit 4 */
-#define QSPI_CTRL0_DFS_4_BIT               					((uint32_t)0x00000003)
-#define QSPI_CTRL0_DFS_5_BIT               					((uint32_t)0x00000004)
-#define QSPI_CTRL0_DFS_6_BIT               					((uint32_t)0x00000005)
-#define QSPI_CTRL0_DFS_7_BIT               					((uint32_t)0x00000006)
-#define QSPI_CTRL0_DFS_8_BIT               					((uint32_t)0x00000007)
-#define QSPI_CTRL0_DFS_9_BIT               					((uint32_t)0x00000008)
-#define QSPI_CTRL0_DFS_10_BIT              					((uint32_t)0x00000009)
-#define QSPI_CTRL0_DFS_11_BIT              					((uint32_t)0x0000000A)
-#define QSPI_CTRL0_DFS_12_BIT              					((uint32_t)0x0000000B)
-#define QSPI_CTRL0_DFS_13_BIT              					((uint32_t)0x0000000C)
-#define QSPI_CTRL0_DFS_14_BIT              					((uint32_t)0x0000000D)
-#define QSPI_CTRL0_DFS_15_BIT              					((uint32_t)0x0000000E)
-#define QSPI_CTRL0_DFS_16_BIT              					((uint32_t)0x0000000F)
-#define QSPI_CTRL0_DFS_17_BIT              					((uint32_t)0x00000010)
-#define QSPI_CTRL0_DFS_18_BIT              					((uint32_t)0x00000011)
-#define QSPI_CTRL0_DFS_19_BIT              					((uint32_t)0x00000012)
-#define QSPI_CTRL0_DFS_20_BIT              					((uint32_t)0x00000013)
-#define QSPI_CTRL0_DFS_21_BIT              					((uint32_t)0x00000014)
-#define QSPI_CTRL0_DFS_22_BIT              					((uint32_t)0x00000015)
-#define QSPI_CTRL0_DFS_23_BIT              					((uint32_t)0x00000016)
-#define QSPI_CTRL0_DFS_24_BIT              					((uint32_t)0x00000017)
-#define QSPI_CTRL0_DFS_25_BIT              					((uint32_t)0x00000018)
-#define QSPI_CTRL0_DFS_26_BIT              					((uint32_t)0x00000019)
-#define QSPI_CTRL0_DFS_27_BIT              					((uint32_t)0x0000001A)
-#define QSPI_CTRL0_DFS_28_BIT              					((uint32_t)0x0000001B)
-#define QSPI_CTRL0_DFS_29_BIT              					((uint32_t)0x0000001C)
-#define QSPI_CTRL0_DFS_30_BIT              					((uint32_t)0x0000001D)
-#define QSPI_CTRL0_DFS_31_BIT              					((uint32_t)0x0000001E)
-#define QSPI_CTRL0_DFS_32_BIT              					((uint32_t)0x0000001F)
+#define QSPI_CTRL0_DFS_4_BIT                                ((uint32_t)0x00000003)
+#define QSPI_CTRL0_DFS_5_BIT                                ((uint32_t)0x00000004)
+#define QSPI_CTRL0_DFS_6_BIT                                ((uint32_t)0x00000005)
+#define QSPI_CTRL0_DFS_7_BIT                                ((uint32_t)0x00000006)
+#define QSPI_CTRL0_DFS_8_BIT                                ((uint32_t)0x00000007)
+#define QSPI_CTRL0_DFS_9_BIT                                ((uint32_t)0x00000008)
+#define QSPI_CTRL0_DFS_10_BIT                               ((uint32_t)0x00000009)
+#define QSPI_CTRL0_DFS_11_BIT                               ((uint32_t)0x0000000A)
+#define QSPI_CTRL0_DFS_12_BIT                               ((uint32_t)0x0000000B)
+#define QSPI_CTRL0_DFS_13_BIT                               ((uint32_t)0x0000000C)
+#define QSPI_CTRL0_DFS_14_BIT                               ((uint32_t)0x0000000D)
+#define QSPI_CTRL0_DFS_15_BIT                               ((uint32_t)0x0000000E)
+#define QSPI_CTRL0_DFS_16_BIT                               ((uint32_t)0x0000000F)
+#define QSPI_CTRL0_DFS_17_BIT                               ((uint32_t)0x00000010)
+#define QSPI_CTRL0_DFS_18_BIT                               ((uint32_t)0x00000011)
+#define QSPI_CTRL0_DFS_19_BIT                               ((uint32_t)0x00000012)
+#define QSPI_CTRL0_DFS_20_BIT                               ((uint32_t)0x00000013)
+#define QSPI_CTRL0_DFS_21_BIT                               ((uint32_t)0x00000014)
+#define QSPI_CTRL0_DFS_22_BIT                               ((uint32_t)0x00000015)
+#define QSPI_CTRL0_DFS_23_BIT                               ((uint32_t)0x00000016)
+#define QSPI_CTRL0_DFS_24_BIT                               ((uint32_t)0x00000017)
+#define QSPI_CTRL0_DFS_25_BIT                               ((uint32_t)0x00000018)
+#define QSPI_CTRL0_DFS_26_BIT                               ((uint32_t)0x00000019)
+#define QSPI_CTRL0_DFS_27_BIT                               ((uint32_t)0x0000001A)
+#define QSPI_CTRL0_DFS_28_BIT                               ((uint32_t)0x0000001B)
+#define QSPI_CTRL0_DFS_29_BIT                               ((uint32_t)0x0000001C)
+#define QSPI_CTRL0_DFS_30_BIT                               ((uint32_t)0x0000001D)
+#define QSPI_CTRL0_DFS_31_BIT                               ((uint32_t)0x0000001E)
+#define QSPI_CTRL0_DFS_32_BIT                               ((uint32_t)0x0000001F)
 
 #define QSPI_CTRL0_FRF                              ((uint32_t)0x000000C0) /*!< FRF[1:0] bits (Frame Format) */
 #define QSPI_CTRL0_FRF_0                            ((uint32_t)0x00000040) /*!< Bit 0 */
 #define QSPI_CTRL0_FRF_1                            ((uint32_t)0x00000080) /*!< Bit 1 */
-#define QSPI_CTRL0_FRF_MOTOROLA            					((uint32_t)0x00000000)
-#define QSPI_CTRL0_FRF_TI                  					((uint32_t)0x00000040)
-#define QSPI_CTRL0_FRF_MICROWIRE           					((uint32_t)0x00000080)
+#define QSPI_CTRL0_FRF_MOTOROLA                             ((uint32_t)0x00000000)
+#define QSPI_CTRL0_FRF_TI                                   ((uint32_t)0x00000040)
+#define QSPI_CTRL0_FRF_MICROWIRE                            ((uint32_t)0x00000080)
 
 #define QSPI_CTRL0_SCPH                             ((uint32_t)0x00000100) /*!< SCPH (Serial Clock Phase) */
-#define QSPI_CTRL0_SCPH_FIRST_EDGE         					((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPH_SECOND_EDGE        					((uint32_t)0x00000100)
+#define QSPI_CTRL0_SCPH_FIRST_EDGE                          ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPH_SECOND_EDGE                         ((uint32_t)0x00000100)
 
 #define QSPI_CTRL0_SCPOL                            ((uint32_t)0x00000200) /*!< SCPOL(Serial Clock Polarity) */
-#define QSPI_CTRL0_SCPOL_LOW               					((uint32_t)0x00000000)
-#define QSPI_CTRL0_SCPOL_HIGH              					((uint32_t)0x00000200)
+#define QSPI_CTRL0_SCPOL_LOW                                ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SCPOL_HIGH                               ((uint32_t)0x00000200)
 
 #define QSPI_CTRL0_TMOD                             ((uint32_t)0x00000C00) /*!< TMOD[1:0] bits (Transfer Mode) */
 #define QSPI_CTRL0_TMOD_0                           ((uint32_t)0x00000400) /*!< Bit 0 */
 #define QSPI_CTRL0_TMOD_1                           ((uint32_t)0x00000800) /*!< Bit 1 */
-#define QSPI_CTRL0_TMOD_TX_AND_RX          					((uint32_t)0x00000000)
-#define QSPI_CTRL0_TMOD_TX_ONLY            					((uint32_t)0x00000400)
-#define QSPI_CTRL0_TMOD_RX_ONLY            					((uint32_t)0x00000800)
-#define QSPI_CTRL0_TMOD_EEPROM_READ        					((uint32_t)0x00000C00)
+#define QSPI_CTRL0_TMOD_TX_AND_RX                           ((uint32_t)0x00000000)
+#define QSPI_CTRL0_TMOD_TX_ONLY                             ((uint32_t)0x00000400)
+#define QSPI_CTRL0_TMOD_RX_ONLY                             ((uint32_t)0x00000800)
+#define QSPI_CTRL0_TMOD_EEPROM_READ                         ((uint32_t)0x00000C00)
 
 #define QSPI_CTRL0_SRL_EN                           ((uint32_t)0x00002000) /*!< SRL (Shift Register Loop) */
 #define QSPI_CTRL0_SSTE_EN                          ((uint32_t)0x00004000) /*!< SSTE(Slave Select Toggle Enable) */
@@ -8407,29 +8407,29 @@ typedef struct
 #define QSPI_CTRL0_CFS_1                            ((uint32_t)0x00020000) /*!< Bit 1 */
 #define QSPI_CTRL0_CFS_2                            ((uint32_t)0x00040000) /*!< Bit 2 */
 #define QSPI_CTRL0_CFS_3                            ((uint32_t)0x00080000) /*!< Bit 3 */
-#define QSPI_CTRL0_CFS_1_BIT          	   					((uint32_t)0x00000000)
-#define QSPI_CTRL0_CFS_2_BIT          	   					((uint32_t)0x00010000)
-#define QSPI_CTRL0_CFS_3_BIT          	   					((uint32_t)0x00020000)
-#define QSPI_CTRL0_CFS_4_BIT          	   					((uint32_t)0x00030000)
-#define QSPI_CTRL0_CFS_5_BIT          	   					((uint32_t)0x00040000)
-#define QSPI_CTRL0_CFS_6_BIT          	   					((uint32_t)0x00050000)
-#define QSPI_CTRL0_CFS_7_BIT          	   					((uint32_t)0x00060000)
-#define QSPI_CTRL0_CFS_8_BIT          	   					((uint32_t)0x00070000)
-#define QSPI_CTRL0_CFS_9_BIT          	   					((uint32_t)0x00080000)
-#define QSPI_CTRL0_CFS_10_BIT         	   					((uint32_t)0x00090000)
-#define QSPI_CTRL0_CFS_11_BIT         	   					((uint32_t)0x000A0000)
-#define QSPI_CTRL0_CFS_12_BIT         	   					((uint32_t)0x000B0000)
-#define QSPI_CTRL0_CFS_13_BIT         	   					((uint32_t)0x000C0000)
-#define QSPI_CTRL0_CFS_14_BIT         	   					((uint32_t)0x000D0000)
-#define QSPI_CTRL0_CFS_15_BIT         	   					((uint32_t)0x000E0000)
-#define QSPI_CTRL0_CFS_16_BIT         	   					((uint32_t)0x000F0000)
+#define QSPI_CTRL0_CFS_1_BIT                                ((uint32_t)0x00000000)
+#define QSPI_CTRL0_CFS_2_BIT                                ((uint32_t)0x00010000)
+#define QSPI_CTRL0_CFS_3_BIT                                ((uint32_t)0x00020000)
+#define QSPI_CTRL0_CFS_4_BIT                                ((uint32_t)0x00030000)
+#define QSPI_CTRL0_CFS_5_BIT                                ((uint32_t)0x00040000)
+#define QSPI_CTRL0_CFS_6_BIT                                ((uint32_t)0x00050000)
+#define QSPI_CTRL0_CFS_7_BIT                                ((uint32_t)0x00060000)
+#define QSPI_CTRL0_CFS_8_BIT                                ((uint32_t)0x00070000)
+#define QSPI_CTRL0_CFS_9_BIT                                ((uint32_t)0x00080000)
+#define QSPI_CTRL0_CFS_10_BIT                               ((uint32_t)0x00090000)
+#define QSPI_CTRL0_CFS_11_BIT                               ((uint32_t)0x000A0000)
+#define QSPI_CTRL0_CFS_12_BIT                               ((uint32_t)0x000B0000)
+#define QSPI_CTRL0_CFS_13_BIT                               ((uint32_t)0x000C0000)
+#define QSPI_CTRL0_CFS_14_BIT                               ((uint32_t)0x000D0000)
+#define QSPI_CTRL0_CFS_15_BIT                               ((uint32_t)0x000E0000)
+#define QSPI_CTRL0_CFS_16_BIT                               ((uint32_t)0x000F0000)
 
 #define QSPI_CTRL0_SPI_FRF                          ((uint32_t)0x00C00000) /*!< SPI_FRF[1:0] bits (SPI Frame Format) */
 #define QSPI_CTRL0_SPI_FRF_0                        ((uint32_t)0x00400000) /*!< Bit 0 */
 #define QSPI_CTRL0_SPI_FRF_1                        ((uint32_t)0x00800000) /*!< Bit 1 */
-#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT 					((uint32_t)0x00000000)
-#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT     					((uint32_t)0x00400000)
-#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT     					((uint32_t)0x00800000)
+#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT                  ((uint32_t)0x00000000)
+#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT                      ((uint32_t)0x00400000)
+#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT                      ((uint32_t)0x00800000)
 
 /*******************  Bit definition for QSPI_CTRL1 register  *******************/
 #define QSPI_CTRL1_NDF                              ((uint32_t)0x0000FFFF) /*!< NDF[15:0] bits (Numver of Data Frames) */
@@ -8455,12 +8455,12 @@ typedef struct
 
 /*******************  Bit definition for QSPI_MW_CTRL register  *******************/
 #define QSPI_MW_CTRL_MWMOD                          ((uint32_t)0x00000001) /*!< MWMO (Microwire Transfer Mode) */
-#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL		  				((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL		  					((uint32_t)0x00000001)
+#define QSPI_MW_CTRL_MWMOD_UNSEQUENTIAL                     ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL                           ((uint32_t)0x00000001)
 
 #define QSPI_MW_CTRL_MC_DIR                         ((uint32_t)0x00000002) /*!< MC_DIR (Direction of Data when Microwire Control) */
-#define QSPI_MW_CTRL_MC_DIR_RX              				((uint32_t)0x00000000)
-#define QSPI_MW_CTRL_MC_DIR_TX              				((uint32_t)0x00000002)
+#define QSPI_MW_CTRL_MC_DIR_RX                              ((uint32_t)0x00000000)
+#define QSPI_MW_CTRL_MC_DIR_TX                              ((uint32_t)0x00000002)
 
 #define QSPI_MW_CTRL_MHS_EN                         ((uint32_t)0x00000004) /*!< MHS_EN (Microwire Handshaking Enable) */
 
@@ -8530,12 +8530,12 @@ typedef struct
 /*******************  Bit definition for QSPI_STS register  *******************/
 #define QSPI_STS                                    ((uint32_t)0x0000007F) /*!< STS[6:0] (status flag) */
 #define QSPI_STS_BUSY                               ((uint32_t)0x00000001) /*!< BUSY (Transfer Busy Flag) */
-#define QSPI_STS_TXFNF    	                        ((uint32_t)0x00000002) /*!< TXFNF (Transmit FIFO not Full) */
+#define QSPI_STS_TXFNF                              ((uint32_t)0x00000002) /*!< TXFNF (Transmit FIFO not Full) */
 #define QSPI_STS_TXFE                               ((uint32_t)0x00000004) /*!< TXFE (Transmit FIFO not Empty) */
 #define QSPI_STS_RXFNE                              ((uint32_t)0x00000008) /*!< RXFNE (Receive FIFO not Empty) */
 #define QSPI_STS_RXFF                               ((uint32_t)0x00000010) /*!< RXFF (Receive FIFO not Full) */
 #define QSPI_STS_TX_ERR                             ((uint32_t)0x00000020) /*!< TX_ERR (Transmit Error) */
-#define QSPI_STS_DC_ERR		                        	((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
+#define QSPI_STS_DC_ERR                                 ((uint32_t)0x00000040) /*!< DC_ERR (Data Conflict Error) */
 
 /*******************  Bit definition for QSPI_IMASK register  *******************/
 #define QSPI_IMASK                                  ((uint32_t)0x0000007F) /*!< IMASK[6:0] (Interrupt of Mask) */
@@ -8684,24 +8684,24 @@ typedef struct
 #define QSPI_RS_DELAY_SDCN_5                        ((uint32_t)0x00000020) /*!< Bit 5 */
 #define QSPI_RS_DELAY_SDCN_6                        ((uint32_t)0x00000040) /*!< Bit 6 */
 #define QSPI_RS_DELAY_SDCN_7                        ((uint32_t)0x00000080) /*!< Bit 7 */
-#define QSPI_RS_DELAY_SDCN_0_CYCLES    							((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SDCN_1_CYCLES    							((uint32_t)0x00000001)
-#define QSPI_RS_DELAY_SDCN_2_CYCLES    							((uint32_t)0x00000002)
-#define QSPI_RS_DELAY_SDCN_3_CYCLES    							((uint32_t)0x00000003)
-#define QSPI_RS_DELAY_SDCN_4_CYCLES    							((uint32_t)0x00000004)
-#define QSPI_RS_DELAY_SDCN_5_CYCLES    							((uint32_t)0x00000005)
-#define QSPI_RS_DELAY_SDCN_6_CYCLES    							((uint32_t)0x00000006)
-
-#define QSPI_RS_DELAY_SES                     			((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
-#define QSPI_RS_DELAY_SES_RISING_EDGE  							((uint32_t)0x00000000)
-#define QSPI_RS_DELAY_SES_FALLING_EDGE 							((uint32_t)0x00010000)
+#define QSPI_RS_DELAY_SDCN_0_CYCLES                             ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SDCN_1_CYCLES                             ((uint32_t)0x00000001)
+#define QSPI_RS_DELAY_SDCN_2_CYCLES                             ((uint32_t)0x00000002)
+#define QSPI_RS_DELAY_SDCN_3_CYCLES                             ((uint32_t)0x00000003)
+#define QSPI_RS_DELAY_SDCN_4_CYCLES                             ((uint32_t)0x00000004)
+#define QSPI_RS_DELAY_SDCN_5_CYCLES                             ((uint32_t)0x00000005)
+#define QSPI_RS_DELAY_SDCN_6_CYCLES                             ((uint32_t)0x00000006)
+
+#define QSPI_RS_DELAY_SES                               ((uint32_t)0x00010000) /*!< SES (Sample Edge Select of Receive Data) */
+#define QSPI_RS_DELAY_SES_RISING_EDGE                           ((uint32_t)0x00000000)
+#define QSPI_RS_DELAY_SES_FALLING_EDGE                          ((uint32_t)0x00010000)
 /*******************  Bit definition for QSPI_ENH_CTRL0 register  *******************/
 #define QSPI_ENH_CTRL0_TRANS_TYPE                   ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */
 #define QSPI_ENH_CTRL0_TRANS_TYPE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_TRANS_TYPE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD       		((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF 		((uint32_t)0x00000001)
-#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF     		((uint32_t)0x00000002)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD              ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF        ((uint32_t)0x00000001)
+#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF            ((uint32_t)0x00000002)
 
 #define QSPI_ENH_CTRL0_ADDR_LEN                     ((uint32_t)0x0000003C) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */
 #define QSPI_ENH_CTRL0_ADDR_LEN_0                   ((uint32_t)0x00000004) /*!< Bit 0 */
@@ -8729,10 +8729,10 @@ typedef struct
 #define QSPI_ENH_CTRL0_INST_L                       ((uint32_t)0x00000300) /*!< INST_L[1:0] (Dual/Quad mode instruction length in bits) */
 #define QSPI_ENH_CTRL0_INST_L_0                     ((uint32_t)0x00000100) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_INST_L_1                     ((uint32_t)0x00000200) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_INST_L_0_LINE       					((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_INST_L_4_LINE       					((uint32_t)0x00000100)
-#define QSPI_ENH_CTRL0_INST_L_8_LINE       					((uint32_t)0x00000200)
-#define QSPI_ENH_CTRL0_INST_L_16_LINE      					((uint32_t)0x00000300)
+#define QSPI_ENH_CTRL0_INST_L_0_LINE                        ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_INST_L_4_LINE                        ((uint32_t)0x00000100)
+#define QSPI_ENH_CTRL0_INST_L_8_LINE                        ((uint32_t)0x00000200)
+#define QSPI_ENH_CTRL0_INST_L_16_LINE                       ((uint32_t)0x00000300)
 
 #define QSPI_ENH_CTRL0_WAIT_CYCLES                  ((uint32_t)0x0000F800) /*!< WAIT_CYCLES[4:0] (Wait Cycles in Dual/Quad mode between control frames transmit and data reception) */
 #define QSPI_ENH_CTRL0_WAIT_CYCLES_0                ((uint32_t)0x00000800) /*!< Bit 0 */
@@ -8782,10 +8782,10 @@ typedef struct
 #define QSPI_ENH_CTRL0_XIP_MBL                      ((uint32_t)0x0C000000) /*!< XIP_MBL[1:0] (XIP Mode bits length) */
 #define QSPI_ENH_CTRL0_XIP_MBL_0                    ((uint32_t)0x04000000) /*!< Bit 0 */
 #define QSPI_ENH_CTRL0_XIP_MBL_1                    ((uint32_t)0x08000000) /*!< Bit 1 */
-#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT   							((uint32_t)0x00000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT   							((uint32_t)0x04000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT   							((uint32_t)0x08000000)
-#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT  							((uint32_t)0x0C000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT                            ((uint32_t)0x00000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT                            ((uint32_t)0x04000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT                            ((uint32_t)0x08000000)
+#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT                           ((uint32_t)0x0C000000)
 
 
 #define QSPI_ENH_CTRL0_CLK_STRETCH_EN               ((uint32_t)0x40000000) /*!< CLK_STRETCH_EN (Enable Continuous Transfer in XIP mode) */
@@ -8868,9 +8868,9 @@ typedef struct
 #define QSPI_XIP_CTRL_TRANS_TYPE          ((uint32_t)0x00000003) /*!< TRANS_TYPE[1:0] (Address and instruction transfer format) */
 #define QSPI_XIP_CTRL_TRANS_TYPE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
 #define QSPI_XIP_CTRL_TRANS_TYPE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
-#define QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI    		  ((uint32_t)0x00000000)
-#define QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF  	((uint32_t)0x00000004)
-#define QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF 	((uint32_t)0x00000008)
+#define QSPI_XIP_CTRL_TRANS_TYPE_STANDARD_SPI             ((uint32_t)0x00000000)
+#define QSPI_XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF     ((uint32_t)0x00000004)
+#define QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF    ((uint32_t)0x00000008)
 
 #define QSPI_XIP_CTRL_ADDR_LEN            ((uint32_t)0x000000F0) /*!< ADDR_LEN[3:0] (Length of Address to transmit) */
 #define QSPI_XIP_CTRL_ADDR_LEN_0          ((uint32_t)0x00000010) /*!< Bit 0 */
@@ -8973,7 +8973,7 @@ typedef struct
 #define QSPI_XIP_OUT_XTOUT_7              ((uint32_t)0x00000080) /*!< Bit 7 */
 /******************************************************************************/
 /*                                                                            */
-/*                                 TSC Registers           	                  */
+/*                                 TSC Registers                              */
 /*                                                                            */
 /******************************************************************************/
 #if     (TSC_USED_NEW_SDK)
@@ -9178,7 +9178,7 @@ typedef struct
 
 #else
 
-/****************  Bit definition for TSC_CTRL register 		   ****************/
+/****************  Bit definition for TSC_CTRL register            ****************/
 #define TSC_CTRL_DET_PERIOD                ((uint32_t)0x0000000F) /*!< DET_PERIOD[3:0] (Detect period) */
 #define TSC_CTRL_DET_PERIOD_0              ((uint32_t)0x00000001) /*!< Bit 0 */
 #define TSC_CTRL_DET_PERIOD_1              ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -9267,35 +9267,35 @@ typedef struct
 
 /*******************  Bit definition for TSC_ANA_CTRL register  *******************/
 #define TSC_ANA_CTRL_SW_PAD_MUX             ((uint32_t)0x0000001F) /*!< SW_PAD_MUX[4:0] (Select TSC channel) */
-#define TSC_ANA_CTRL_SW_PAD_MUX_0           ((uint32_t)0x00000001) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_1           ((uint32_t)0x00000002) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_2           ((uint32_t)0x00000004) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_3           ((uint32_t)0x00000008) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_4           ((uint32_t)0x00000010) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH0         ((uint32_t)0x00000000) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH1         ((uint32_t)0x00000001) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH2         ((uint32_t)0x00000002) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH3         ((uint32_t)0x00000003) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH4         ((uint32_t)0x00000004) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH5         ((uint32_t)0x00000005) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH6         ((uint32_t)0x00000006) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH7         ((uint32_t)0x00000007) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH8         ((uint32_t)0x00000008) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH9         ((uint32_t)0x00000009) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH10        ((uint32_t)0x0000000A) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH11        ((uint32_t)0x0000000B) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH12        ((uint32_t)0x0000000C) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH13        ((uint32_t)0x0000000D) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH14        ((uint32_t)0x0000000E) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH15        ((uint32_t)0x0000000F) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH16        ((uint32_t)0x00000010) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH17        ((uint32_t)0x00000011) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH18        ((uint32_t)0x00000012) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH19        ((uint32_t)0x00000013) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH20        ((uint32_t)0x00000014) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH21        ((uint32_t)0x00000015) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH22        ((uint32_t)0x00000016) 
-#define TSC_ANA_CTRL_SW_PAD_MUX_CH23        ((uint32_t)0x00000017) 
+#define TSC_ANA_CTRL_SW_PAD_MUX_0           ((uint32_t)0x00000001)
+#define TSC_ANA_CTRL_SW_PAD_MUX_1           ((uint32_t)0x00000002)
+#define TSC_ANA_CTRL_SW_PAD_MUX_2           ((uint32_t)0x00000004)
+#define TSC_ANA_CTRL_SW_PAD_MUX_3           ((uint32_t)0x00000008)
+#define TSC_ANA_CTRL_SW_PAD_MUX_4           ((uint32_t)0x00000010)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH0         ((uint32_t)0x00000000)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH1         ((uint32_t)0x00000001)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH2         ((uint32_t)0x00000002)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH3         ((uint32_t)0x00000003)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH4         ((uint32_t)0x00000004)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH5         ((uint32_t)0x00000005)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH6         ((uint32_t)0x00000006)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH7         ((uint32_t)0x00000007)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH8         ((uint32_t)0x00000008)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH9         ((uint32_t)0x00000009)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH10        ((uint32_t)0x0000000A)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH11        ((uint32_t)0x0000000B)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH12        ((uint32_t)0x0000000C)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH13        ((uint32_t)0x0000000D)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH14        ((uint32_t)0x0000000E)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH15        ((uint32_t)0x0000000F)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH16        ((uint32_t)0x00000010)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH17        ((uint32_t)0x00000011)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH18        ((uint32_t)0x00000012)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH19        ((uint32_t)0x00000013)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH20        ((uint32_t)0x00000014)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH21        ((uint32_t)0x00000015)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH22        ((uint32_t)0x00000016)
+#define TSC_ANA_CTRL_SW_PAD_MUX_CH23        ((uint32_t)0x00000017)
 
 #define TSC_ANA_CTRL_SW_TSC_EN              ((uint32_t)0x00000020) /*!< PAD_OPT (Enable TSC software mode) */
 
@@ -9653,7 +9653,7 @@ typedef struct
 
 /******************************************************************************/
 /*                                                                            */
-/*                                 DVP Registers           	                  */
+/*                                 DVP Registers                              */
 /*                                                                            */
 /******************************************************************************/
 
@@ -9934,17 +9934,17 @@ typedef struct
   */
 
 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-    
+
 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-    
+
 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
-    
+
 #define CLEAR_REG(REG)        ((REG) = (0x0))
-    
+
 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-    
+
 #define READ_REG(REG)         ((REG))
-    
+
 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 /**
  * @}

bsp/n32g452xx/Libraries/N32_Std_Driver/CMSIS/device/n32g45x_conf.h

@@ -44,7 +44,7 @@
  * @brief AES symmetrical cipher algorithm
  * @{
  */
- 
+
 #define AES_ECB (0x11111111)
 #define AES_CBC (0x22222222)
 #define AES_CTR (0x33333333)
@@ -54,34 +54,34 @@
 
 enum
 {
-	AES_Crypto_OK = 0x0,   //AES opreation success
-	AES_Init_OK = 0x0,   //AES Init opreation success
-	AES_Crypto_ModeError = 0x5a5a5a5a,	 //Working mode error(Neither ECB nor CBC nor CTR)
-	AES_Crypto_EnOrDeError,    //En&De error(Neither encryption nor decryption)
-	AES_Crypto_ParaNull,    // the part of input(output/iv) Null    
-	AES_Crypto_LengthError,     // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
-	                            //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
-
-	AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
+    AES_Crypto_OK = 0x0,   //AES opreation success
+    AES_Init_OK = 0x0,   //AES Init opreation success
+    AES_Crypto_ModeError = 0x5a5a5a5a,   //Working mode error(Neither ECB nor CBC nor CTR)
+    AES_Crypto_EnOrDeError,    //En&De error(Neither encryption nor decryption)
+    AES_Crypto_ParaNull,    // the part of input(output/iv) Null
+    AES_Crypto_LengthError,     // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
+                                //if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
+
+    AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
   AES_Crypto_UnInitError, //AES uninitialized
 };
 
 typedef struct
 {
-	uint32_t *in;		// the part of input to be encrypted or decrypted
-	uint32_t *iv;		// the part of initial vector
-	uint32_t *out;		// the part of out
-	uint32_t *key;		// the part of key
-	uint32_t keyWordLen;   // the length(by word) of key
-	uint32_t inWordLen;	// the length(by word) of plaintext or cipher
-	uint32_t En_De;	// 0x44444444- encrypt, 0x55555555 - decrypt
-	uint32_t Mode;  // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
+    uint32_t *in;       // the part of input to be encrypted or decrypted
+    uint32_t *iv;       // the part of initial vector
+    uint32_t *out;      // the part of out
+    uint32_t *key;      // the part of key
+    uint32_t keyWordLen;   // the length(by word) of key
+    uint32_t inWordLen; // the length(by word) of plaintext or cipher
+    uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
+    uint32_t Mode;  // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
 }AES_PARM;
 
  /**
  * @brief AES_Init
  * @return AES_Init_OK, AES Init success; othets: AES Init fail
- * @note    
+ * @note
  */
 
 uint32_t  AES_Init(AES_PARM *parm);
@@ -89,12 +89,12 @@ uint32_t  AES_Init(AES_PARM *parm);
 /**
  * @brief AES crypto
  * @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
- * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation) 
- * @note  1.Please refer to the demo in user guidance before using this function  
+ * @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
+ * @note  1.Please refer to the demo in user guidance before using this function
  *        2.Input and output can be the same buffer
  *        3. IV can be NULL when ECB mode
  *        4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
- *	         if Working mode is CTR,the length of input message cannot be zero;
+ *           if Working mode is CTR,the length of input message cannot be zero;
  *        5. If the input is in byte, make sure align by word.
  */
 uint32_t AES_Crypto(AES_PARM *parm);
@@ -111,7 +111,7 @@ void AES_Close(void);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get AES lib information

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_algo_common.h

@@ -41,11 +41,11 @@
  */
 enum{
   Cpy_OK=0,//copy success
-	SetZero_OK = 0,//set zero success
-	XOR_OK = 0,   //XOR success
-	Reverse_OK = 0, //Reverse success
-	Cmp_EQUAL = 0, //Two big number are equal
-	Cmp_UNEQUAL = 1, //Two big number are not equal
+    SetZero_OK = 0,//set zero success
+    XOR_OK = 0,   //XOR success
+    Reverse_OK = 0, //Reverse success
+    Cmp_EQUAL = 0, //Two big number are equal
+    Cmp_UNEQUAL = 1, //Two big number are not equal
 
 };
 
@@ -55,7 +55,7 @@ enum{
  * @param[in] rand pointer to random number
  * @param[in] the length of order
  * @return RandomSort_OK:  disturb order success;  Others: disturb order fail;
- * @note 
+ * @note
  */
 uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
 
@@ -63,7 +63,7 @@ uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
  * @brief Copy data by byte
  * @param[in]  dst pointer to destination data
  * @param[in]  src pointer to source data
- * @param[in]  byte length 
+ * @param[in]  byte length
  * @return Cpy_OK: success; others: fail.
  * @note 1. dst and  src cannot be same
  */
@@ -73,7 +73,7 @@ uint32_t Cpy_U8(uint8_t *dst, uint8_t *src, uint32_t byteLen);
  * @brief Copy data by word
  * @param[in]  dst pointer to destination data
  * @param[in]  src pointer to source data
- * @param[in]  word length 
+ * @param[in]  word length
  * @return Cpy_OK: success; others: fail.
  * @note 1. dst and  src must be aligned by word
  */
@@ -85,7 +85,7 @@ uint32_t Cpy_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
  * @param[in] b pointer to another data to be XORed
  * @param[in] the length of order
  * @return XOR_OK:  operation success;  Others: operation fail;
- * @note 
+ * @note
  */
 uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
 
@@ -95,33 +95,33 @@ uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
  * @param[in] b pointer to another data to be XORed
  * @param[in] the length of order
  * @return XOR_OK:  operation success;  Others: operation fail;
- * @note 
+ * @note
  */
 uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
 
 /**
  * @brief set zero by byte
- * @param[in] dst pointer to the address to be set zero 
- * @param[in]  byte length 
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in]  byte length
  * @return SetZero_OK: success; others: fail.
- * @note 
+ * @note
  */
 uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
 
 /**
  * @brief set zero by word
- * @param[in] dst pointer to the address to be set zero 
- * @param[in]  word length 
+ * @param[in] dst pointer to the address to be set zero
+ * @param[in]  word length
  * @return SetZero_OK: success; others: fail.
- * @note 
+ * @note
  */
 uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
 
 /**
  * @brief reverse byte order of every word, the words stay the same
  * @param[in]  dst pointer to the destination address
- * @param[in]  src pointer to the source address 
- * @param[in]  word length 
+ * @param[in]  src pointer to the source address
+ * @param[in]  word length
  * @return Reverse_OK: success; others: fail.
  * @note 1.dst and src can be same
  */
@@ -134,7 +134,7 @@ uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wor
  * @param[in] b pointer to another big number
  * @param[in]  word length of b
  * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
- * 
+ *
  */
 int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
 
@@ -145,7 +145,7 @@ int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_
  * @param[in] b pointer to another big number
  * @param[in]  word length of b
  * @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
- * 
+ *
  */
 int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_des.h

@@ -83,15 +83,15 @@ typedef struct
  /**
  * @brief DES_Init
  * @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
- * @note    
+ * @note
  */
 uint32_t DES_Init(DES_PARM* parm);
 
 /**
  * @brief DES crypto
  * @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
- * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation) 
- * @note  1.Please refer to the demo in user guidance before using this function  
+ * @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
+ * @note  1.Please refer to the demo in user guidance before using this function
  *        2.Input and output can be the same buffer
  *        3. IV can be NULL when ECB mode
  *        4. The word lengrh of message must be as times as 2.
@@ -111,7 +111,7 @@ void DES_Close(void);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get DES/TDES lib information

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_hash.h

@@ -48,55 +48,55 @@
 #define  ALG_SHA224   (uint16_t)(0x000A)
 #define  ALG_SHA256   (uint16_t)(0x000B)
 #define  ALG_MD5      (uint16_t)(0x000C)
-#define  ALG_SM3	    (uint16_t)(0x0012)
+#define  ALG_SM3        (uint16_t)(0x0012)
 
 enum
 {
-	HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
-	HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV 
-	HASH_Init_OK = 0,//hash init success
-	HASH_Start_OK = 0,//hash update success
-	HASH_Update_OK = 0,//hash update success
-	HASH_Complete_OK = 0,//hash complete success
-	HASH_Close_OK = 0,//hash close success
-	HASH_ByteLenPlus_OK = 0,//byte length plus success
-	HASH_PadMsg_OK = 0,//message padding success
-	HASH_ProcMsgBuf_OK = 0, //message processing success
-	SHA1_Hash_OK = 0,//sha1 operation success
-	SM3_Hash_OK = 0,//sm3 operation success
-	SHA224_Hash_OK = 0,//sha224 operation success
-	SHA256_Hash_OK = 0,//sha256 operation success
-	MD5_Hash_OK = 0,//MD5 operation success
-	
-	HASH_Init_ERROR = 0x01044400,//hash init error
-	HASH_Start_ERROR, //hash start error
-	HASH_Update_ERROR, //hash update error
-	HASH_ByteLenPlus_ERROR,//hash byte plus error
+    HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
+    HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
+    HASH_Init_OK = 0,//hash init success
+    HASH_Start_OK = 0,//hash update success
+    HASH_Update_OK = 0,//hash update success
+    HASH_Complete_OK = 0,//hash complete success
+    HASH_Close_OK = 0,//hash close success
+    HASH_ByteLenPlus_OK = 0,//byte length plus success
+    HASH_PadMsg_OK = 0,//message padding success
+    HASH_ProcMsgBuf_OK = 0, //message processing success
+    SHA1_Hash_OK = 0,//sha1 operation success
+    SM3_Hash_OK = 0,//sm3 operation success
+    SHA224_Hash_OK = 0,//sha224 operation success
+    SHA256_Hash_OK = 0,//sha256 operation success
+    MD5_Hash_OK = 0,//MD5 operation success
+
+    HASH_Init_ERROR = 0x01044400,//hash init error
+    HASH_Start_ERROR, //hash start error
+    HASH_Update_ERROR, //hash update error
+    HASH_ByteLenPlus_ERROR,//hash byte plus error
 };
 
 typedef struct _HASH_CTX_ HASH_CTX;
 
 typedef struct
 {
-	const uint16_t HashAlgID;//choice hash algorithm
-	const uint32_t * const K, KLen;//K and word length of K
-	const uint32_t * const IV, IVLen;//IV and word length of IV
-	const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
-	const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
-	const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
-	const uint32_t Cycle; //interation times
-	uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
-	uint32_t (* const PadMsg)(HASH_CTX *); //function pointer
+    const uint16_t HashAlgID;//choice hash algorithm
+    const uint32_t * const K, KLen;//K and word length of K
+    const uint32_t * const IV, IVLen;//IV and word length of IV
+    const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
+    const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
+    const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
+    const uint32_t Cycle; //interation times
+    uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
+    uint32_t (* const PadMsg)(HASH_CTX *); //function pointer
 }HASH_ALG;
 
 typedef struct _HASH_CTX_
 {
-	const HASH_ALG	*hashAlg;//pointer to HASH_ALG
-	uint32_t		sequence;	// TRUE if the IV should be saved
-	uint32_t 	IV[16]; 
-	uint32_t		msgByteLen[4];
-  uint8_t		msgBuf[128+4];
-  uint32_t		msgIdx;
+    const HASH_ALG  *hashAlg;//pointer to HASH_ALG
+    uint32_t        sequence;   // TRUE if the IV should be saved
+    uint32_t    IV[16];
+    uint32_t        msgByteLen[4];
+  uint8_t       msgBuf[128+4];
+  uint32_t      msgIdx;
 }HASH_CTX;
 
 extern const HASH_ALG HASH_ALG_SHA1[1];
@@ -109,7 +109,7 @@ extern const HASH_ALG HASH_ALG_SM3[1];
  * @brief  Hash init
  * @param[in] ctx pointer to HASH_CTX struct
  * @return HASH_Init_OK,  Hash init success; othets:  Hash init fail
- * @note   1.Please refer to the demo in user guidance before using this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t HASH_Init(HASH_CTX *ctx);
 
@@ -117,8 +117,8 @@ uint32_t HASH_Init(HASH_CTX *ctx);
  * @brief  Hash start
  * @param[in] ctx pointer to HASH_CTX struct
  * @return HASH_Start_OK,  Hash start success; othets:  Hash start fail
- * @note   1.Please refer to the demo in user guidance before using this function 
- *         2.HASH_Init() should be recalled before use this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init() should be recalled before use this function
  */
 uint32_t HASH_Start(HASH_CTX *ctx);
 
@@ -128,8 +128,8 @@ uint32_t HASH_Start(HASH_CTX *ctx);
  * @param[in] in pointer to message
  * @param[out] out pointer tohash result,digest
  * @return HASH_Update_OK,  Hash update success; othets:  Hash update fail
- * @note   1.Please refer to the demo in user guidance before using this function 
- *         2.HASH_Init() and HASH_Start() should be recalled before use this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init() and HASH_Start() should be recalled before use this function
  */
 uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
 
@@ -138,15 +138,15 @@ uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
  * @param[in] ctx pointer to HASH_CTX struct
  * @param[out] out pointer tohash result,digest
  * @return HASH_Complete_OK,  Hash complete success; othets:  Hash complete fail
- * @note   1.Please refer to the demo in user guidance before using this function 
- *         2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function 
+ * @note   1.Please refer to the demo in user guidance before using this function
+ *         2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
  */
 uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
 
 /**
  * @brief  Hash close
  * @return HASH_Close_OK, Hash close success; othets: Hash close fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t HASH_Close(void);
 
@@ -156,7 +156,7 @@ uint32_t HASH_Close(void);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -167,7 +167,7 @@ uint32_t SM3_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -177,7 +177,7 @@ uint32_t SHA1_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -188,7 +188,7 @@ uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[out] out pointer tohash result,digest
  * @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -198,7 +198,7 @@ uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[in] byte length of in
  * @param[in] out pointer tohash result,digest
  * @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
- * @note   1.Please refer to the demo in user guidance before using this function  
+ * @note   1.Please refer to the demo in user guidance before using this function
  */
 uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
 
@@ -207,7 +207,7 @@ uint32_t MD5_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get RSA lib information

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_algo_lib/inc/n32g45x_rng.h

@@ -49,8 +49,8 @@
 
 
 enum{
-	RNG_OK = 0x5a5a5a5a,
-	LENError = 0x311ECF50,   //RNG generation of key length error 
+    RNG_OK = 0x5a5a5a5a,
+    LENError = 0x311ECF50,   //RNG generation of key length error
     ADDRNULL = 0x7A9DB86C,   // This address is empty
 };
 
@@ -61,8 +61,8 @@ enum{
  * @param[out] rand pointer to random number
  * @param[in] the wordlen of random number
  * @param[in] the seed, can be NULL
- * @return RNG_OK:get random number success; othets: get random number fail 
- * @note    
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
  */
 uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
 
@@ -71,8 +71,8 @@ uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
  * @brief Get true random number
  * @param[out] rand pointer to random number
  * @param[in] the wordlen of random number
- * @return RNG_OK:get random number success; othets: get random number fail 
- * @note    
+ * @return RNG_OK:get random number success; othets: get random number fail
+ * @note
  */
 uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
 
@@ -81,7 +81,7 @@ uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
  * @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
  * @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
  * @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
- * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018 
+ * @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
  * @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
  * @return none
  * @1.You can recall this function to get RSA lib information

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/misc.h

@@ -536,7 +536,7 @@ typedef struct
 /**
  * @}
  */
- 
+
 typedef enum
 {
     ADC_CTRL3_CKMOD_AHB = 0,
@@ -547,7 +547,7 @@ typedef enum
     ADC_CTRL3_RES_12BIT  = 3,
     ADC_CTRL3_RES_10BIT  = 2,
     ADC_CTRL3_RES_8BIT   = 1,
-    ADC_CTRL3_RES_6BIT   = 0,   
+    ADC_CTRL3_RES_6BIT   = 0,
 } ADC_CTRL3_RES;
 typedef struct
 {

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_bkp.h

@@ -27,7 +27,7 @@
 
 /**
  * @file n32g45x_dbg.h
- * @author Nations 
+ * @author Nations
  * @version v1.0.1
  *
  * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_dma.h

@@ -89,7 +89,7 @@ typedef struct
     uint32_t SSTE;
     uint32_t CFS;
     uint32_t SPI_FRF;
-    
+
     /*QSPI_CTRL1*/
     uint32_t NDF;
 
@@ -130,7 +130,7 @@ typedef struct
     uint32_t ENHANCED_XIP_CT_EN;
     uint32_t ENHANCED_XIP_MBL;
     uint32_t ENHANCED_CLK_STRETCH_EN;
-    
+
     /*QSPI_DDR_TXDE*/
     uint32_t TXDE;
 
@@ -142,7 +142,7 @@ typedef struct
 
     /*QSPI_XIP_WRAP_TOC*/
     uint32_t WTOC;
-    
+
     /*QSPI_XIP_CTRL*/
     uint32_t XIP_FRF;
     uint32_t XIP_TRANS_TYPE;
@@ -165,14 +165,14 @@ typedef struct
 #define QSPI_TIME_OUT_CNT           200
 
 #define IS_QSPI_SPI_FRF(SPI_FRF)                                                                                            \
-    (((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))  
+    (((SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || ((SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
 
 #define IS_QSPI_CFS(CFS) ((((CFS) >= QSPI_CTRL0_CFS_2_BIT) && ((CFS) <= QSPI_CTRL0_CFS_16_BIT)) || ((CFS) == QSPI_CTRL0_CFS_1_BIT))
 
 #define IS_QSPI_SSTE(SSTE) (((SSTE) == QSPI_CTRL0_SSTE_EN) || ((SSTE) == 0))
 
 #define IS_QSPI_TMOD(TMOD)                                                                                            \
-    (((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ))  
+    (((TMOD) == QSPI_CTRL0_TMOD_TX_AND_RX) || ((TMOD) == QSPI_CTRL0_TMOD_TX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_RX_ONLY) || ((TMOD) == QSPI_CTRL0_TMOD_EEPROM_READ))
 
 #define IS_QSPI_SCPOL(SCPOL) (((SCPOL) == QSPI_CTRL0_SCPOL_LOW) || ((SCPOL) == QSPI_CTRL0_SCPOL_HIGH))
 
@@ -231,7 +231,7 @@ typedef struct
                                                     ((ENH_WAIT_CYCLES) == 0))
 
 #define IS_QSPI_ENH_INST_L(ENH_INST_L)                                                                                            \
-    (((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) || 													\
+    (((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_0_LINE) || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_4_LINE) ||                                                    \
     ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_8_LINE)  || ((ENH_INST_L) == QSPI_ENH_CTRL0_INST_L_16_LINE))
 
 #define IS_QSPI_ENH_MD_BIT_EN(ENH_MD_BIT_EN) (((ENH_MD_BIT_EN) == QSPI_ENH_CTRL0_MD_BIT_EN) || ((ENH_MD_BIT_EN) == 0))
@@ -242,7 +242,7 @@ typedef struct
 #define IS_QSPI_ENH_TRANS_TYPE(ENH_TRANS_TYPE) (((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD) ||   \
                                         ((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF)   ||   \
                                         ((ENH_TRANS_TYPE) == QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF))
-    
+
 
 #define IS_QSPI_DDR_TXDE(DDR_TXDE) (((DDR_TXDE) <= 0xFF))
 
@@ -257,7 +257,7 @@ typedef struct
 #define IS_QSPI_XIP_MBL(XIP_MBL)                                                                                            \
     (((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_2_BIT) || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_4_BIT) ||        \
     ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_8_BIT)  || ((XIP_MBL) == QSPI_XIP_CTRL_XIP_MBL_LEN_16_BIT))
-    
+
 #define IS_QSPI_XIP_CT_EN(XIP_CT_EN) (((XIP_CT_EN) == QSPI_XIP_CTRL_XIP_CT_EN) || ((XIP_CT_EN) == 0))
 
 #define IS_QSPI_XIP_INST_EN(XIP_INST_EN) (((XIP_INST_EN) == QSPI_XIP_CTRL_XIP_INST_EN) || ((XIP_INST_EN) == 0))
@@ -285,7 +285,7 @@ typedef struct
                                         ((XIP_TRANS_TYPE) == QSPI_XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF))
 
 #define IS_QSPI_XIP_FRF(XIP_FRF) (((XIP_FRF) == QSPI_XIP_CTRL_FRF_2_LINE) || ((XIP_FRF) == QSPI_XIP_CTRL_FRF_4_LINE) || ((XIP_FRF) == 0))
-    
+
 
 
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_rcc.h

@@ -917,11 +917,11 @@ typedef struct
 #define IsAdvancedTimCCENFlag(FLAG)                                                                                             \
     (((FLAG) == TIM_CC1EN) || ((FLAG) == TIM_CC1NEN) || ((FLAG) == TIM_CC2EN) || ((FLAG) == TIM_CC2NEN)   \
      || ((FLAG) == TIM_CC3EN) || ((FLAG) == TIM_CC3NEN)                              \
-     || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN)   )                      
+     || ((FLAG) == TIM_CC4EN) || ((FLAG) == TIM_CC5EN) || ((FLAG) == TIM_CC6EN)   )
 #define IsGeneralTimCCENFlag(FLAG)                                                                                             \
     (((FLAG) == TIM_CC1EN) ||  ((FLAG) == TIM_CC2EN)    \
      || ((FLAG) == TIM_CC3EN)                             \
-     || ((FLAG) == TIM_CC4EN)      )               
+     || ((FLAG) == TIM_CC4EN)      )
 
 /** @addtogroup TIM_Legacy
  * @{

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_tsc.h

@@ -127,7 +127,7 @@
 /**
  * @
  */
- 
+
 /**
  * @defgroup TSC_Interrupt
  */
@@ -260,7 +260,7 @@
  *     @arg TSC_DET_TYPE_NONE:  Detect disable
  *     @arg TSC_DET_TYPE_LESS:  Pulse number must be greater than the threshold(basee-delta) during a sample time
  *     @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
- *     @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) 
+ *     @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
                                  and also be less than (basee+delta) during a sample time
  * @retval None
  */
@@ -284,7 +284,7 @@
  * @param  __OUT__  specifies where the TSC output should go
  *     @arg TSC_OUT_PIN:      TSC output to the TSC_OUT pin
  *     @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
- *     @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR 
+ *     @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
  * @retval None
  */
 #define __TSC_OUT_CONFIG(__OUT__)           MODIFY_REG( TSC->CTRL,  \

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/inc/n32g45x_usart.h

@@ -73,7 +73,7 @@ typedef struct
                                     This parameter can be a value between 1 and 0xFF.
                                     @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
 
-    uint32_t BusRecoveryCycle;  /*!< Defines the number of HCLK cycles to configure 
+    uint32_t BusRecoveryCycle;  /*!< Defines the number of HCLK cycles to configure
                                     the duration of the bus turnaround.
                                     This parameter can be a value between 0 and 0xF.
                                     @note: It is only used for multiplexed NOR Flash memories. */
@@ -148,10 +148,10 @@ typedef struct
     uint32_t WriteBurstEnable;  /*!< Enables or disables the write burst operation.
                                     This parameter can be a value of @ref XFMC_Write_Burst */
 
-    XFMC_NorSramTimingInitType* RWTimingStruct; /*!< Timing Parameters for write and read access 
+    XFMC_NorSramTimingInitType* RWTimingStruct; /*!< Timing Parameters for write and read access
                                                         if the  ExtendedMode is not used*/
 
-    XFMC_NorSramTimingInitType* WTimingStruct;  /*!< Timing Parameters for write access if the  
+    XFMC_NorSramTimingInitType* WTimingStruct;  /*!< Timing Parameters for write access if the
                                                         ExtendedMode is used*/
 } XFMC_NorSramInitTpye;
 
@@ -431,7 +431,7 @@ typedef struct
 /**
  * @} End of NOR_SRAM_Controller
  */
- 
+
 
 /** @addtogroup NOR_SRAM_Time_Control
  * @{

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/misc.c

@@ -98,7 +98,7 @@ void GetUCID(uint8_t *UCIDbuf)
     uint8_t num = 0;
     uint32_t* ucid_addr = (void*)0;
     uint32_t temp = 0;
-    
+
     if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF260))
     {
         ucid_addr = (uint32_t*)UCID_BASE;
@@ -107,10 +107,10 @@ void GetUCID(uint8_t *UCIDbuf)
     {
         ucid_addr = (uint32_t*)(0x1FFFF260);
     }
-    
+
     for (num = 0; num < UCID_LENGTH;)
     {
-        temp = *(__IO uint32_t*)(ucid_addr++); 
+        temp = *(__IO uint32_t*)(ucid_addr++);
         UCIDbuf[num++] = (temp & 0xFF);
         UCIDbuf[num++] = (temp & 0xFF00) >> 8;
         UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
@@ -128,7 +128,7 @@ void GetUID(uint8_t *UIDbuf)
     uint8_t num = 0;
     uint32_t* uid_addr = (void*)0;
     uint32_t temp = 0;
-    
+
     if (0xFFFFFFFF == *(uint32_t*)(0x1FFFF270))
     {
         uid_addr = (uint32_t*)UID_BASE;
@@ -137,7 +137,7 @@ void GetUID(uint8_t *UIDbuf)
     {
         uid_addr = (uint32_t*)(0x1FFFF270);
     }
-        
+
     for (num = 0; num < UID_LENGTH;)
     {
         temp = *(__IO uint32_t*)(uid_addr++);
@@ -158,11 +158,11 @@ void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf)
     uint8_t num = 0;
     uint32_t* dbgid_addr = (void*)0;
     uint32_t temp = 0;
-    
+
     dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
     for (num = 0; num < DBGMCU_ID_LENGTH;)
     {
-        temp = *(__IO uint32_t*)(dbgid_addr++); 
+        temp = *(__IO uint32_t*)(dbgid_addr++);
         DBGMCU_IDbuf[num++] = (temp & 0xFF);
         DBGMCU_IDbuf[num++] = (temp & 0xFF00) >> 8;
         DBGMCU_IDbuf[num++] = (temp & 0xFF0000) >> 16;

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_dma.c

@@ -70,8 +70,8 @@ void DVP_Init( DVP_InitType* DVP_InitStruct)
 
     /*---------------------------- DVP CTRL Configuration -----------------------*/
     tmpregister  = 0;
-    tmpregister |=  DVP_InitStruct->LineCapture   | DVP_InitStruct->ByteCapture 
-                  | DVP_InitStruct->DataInvert    | DVP_InitStruct->PixelClkPolarity 
+    tmpregister |=  DVP_InitStruct->LineCapture   | DVP_InitStruct->ByteCapture
+                  | DVP_InitStruct->DataInvert    | DVP_InitStruct->PixelClkPolarity
                   | DVP_InitStruct->VsyncPolarity | DVP_InitStruct->HsyncPolarity
                   | DVP_InitStruct->CaptureMode   | DVP_InitStruct->FifoWatermark;
     DVP->CTRL = tmpregister;
@@ -79,7 +79,7 @@ void DVP_Init( DVP_InitType* DVP_InitStruct)
     /*---------------------------- DVP WST Configuration -----------------------*/
     if (DVP_InitStruct->RowStart)
         DVP_InitStruct->RowStart--;
-    
+
     if (DVP_InitStruct->ColumnStart)
         DVP_InitStruct->ColumnStart--;
 
@@ -162,5 +162,5 @@ void DVP_ResetFifo(void)
 
     DVP->CTRL |= DVP_FIFO_SOFT_RESET;
 
-    while(DVP->CTRL & DVP_FIFO_SOFT_RESET);    
+    while(DVP->CTRL & DVP_FIFO_SOFT_RESET);
 }

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_eth.c

@@ -661,7 +661,7 @@ FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
     FLASH_STS status = FLASH_COMPL;
 
     usertmp = ((OBR_USER_MSK & FLASH->OBR) << 0x0E);
-  
+
     /* Get the actual read protection L1 Option Byte value */
     if (FLASH_GetReadOutProtectionSTS() == RESET)
     {
@@ -691,7 +691,7 @@ FLASH_STS FLASH_ReadOutProtectionL2_ENABLE(void)
         if (status == FLASH_COMPL)
         {
             /* Clears the FLASH's pending flags */
-            FLASH_ClearFlag(FLASH_STS_CLRFLAG);	
+            FLASH_ClearFlag(FLASH_STS_CLRFLAG);
 
             /* if the erase operation is completed, disable the OPTER Bit */
             FLASH->CTRL &= CTRL_Reset_OPTER;

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_gpio.c

@@ -112,9 +112,9 @@ void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
 {
     __IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
     __IO uint32_t tmp  = *pCs;
-    
+
     SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
-    
+
     if(OPAMP_InitStruct->HighVolRangeEn==ENABLE)
         SetBitMsk(tmp, OPAMP_CS_RANGE_MASK, OPAMP_CS_RANGE_MASK);
     else
@@ -124,7 +124,7 @@ void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
         SetBitMsk(tmp,OPAMP_CS_TCMEN_MASK, OPAMP_CS_TCMEN_MASK);
     else
         ClrBit(tmp,OPAMP_CS_TCMEN_MASK);
-        
+
     SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
     *pCs = tmp;
 }

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_pwr.c

@@ -135,48 +135,48 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct)
     assert_param(IS_QSPI_TXFN(QSPI_InitStruct->TXFN));
     assert_param(IS_QSPI_RXFN(QSPI_InitStruct->RXFN));
     assert_param(IS_QSPI_DDR_TXDE(QSPI_InitStruct->TXDE));
-            
+
     if((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT)
     {
-        tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD 
+        tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD
                                 | QSPI_InitStruct->SCPOL | QSPI_InitStruct->SCPH | QSPI_InitStruct->FRF | QSPI_InitStruct->DFS);
-        QSPI->CTRL0 = tmpregister; 
-            
+        QSPI->CTRL0 = tmpregister;
+
         tmpregister = 0;
         tmpregister = (uint32_t)(QSPI_InitStruct->MWMOD | QSPI_InitStruct->MC_DIR | QSPI_InitStruct->MHS_EN);
         QSPI->MW_CTRL  = tmpregister;
-    
+
         tmpregister = 0;
         tmpregister = (uint32_t)(QSPI_InitStruct->SES | QSPI_InitStruct->SDCN);
         QSPI->RS_DELAY  = tmpregister;
     }
     else if((QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT) || (QSPI_InitStruct->SPI_FRF == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT))
     {
-        tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD 
+        tmpregister = (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->CFS | QSPI_InitStruct->SSTE | QSPI_InitStruct->TMOD
                                 | QSPI_InitStruct->SCPOL | QSPI_InitStruct->SCPH | QSPI_InitStruct->FRF | QSPI_InitStruct->DFS);
         QSPI->CTRL0 = tmpregister;
-            
+
         tmpregister = 0;
         tmpregister = (uint32_t)(QSPI_InitStruct->MWMOD | QSPI_InitStruct->MC_DIR | QSPI_InitStruct->MHS_EN);
         QSPI->MW_CTRL  = tmpregister;
-    
+
         tmpregister = 0;
         tmpregister = (uint32_t)(QSPI_InitStruct->SES | QSPI_InitStruct->SDCN);
         QSPI->RS_DELAY  = tmpregister;
-            
+
         tmpregister = 0;
-        tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_XIP_MBL | QSPI_InitStruct->ENHANCED_XIP_CT_EN 
+        tmpregister = (uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_XIP_MBL | QSPI_InitStruct->ENHANCED_XIP_CT_EN
                                 | QSPI_InitStruct->ENHANCED_XIP_INST_EN | QSPI_InitStruct->ENHANCED_XIP_DFS_HC | QSPI_InitStruct->ENHANCED_INST_DDR_EN
                                 | QSPI_InitStruct->ENHANCED_SPI_DDR_EN | QSPI_InitStruct->ENHANCED_WAIT_CYCLES | QSPI_InitStruct->ENHANCED_INST_L
                                 | QSPI_InitStruct->ENHANCED_MD_BIT_EN | QSPI_InitStruct->ENHANCED_ADDR_LEN | QSPI_InitStruct->ENHANCED_TRANS_TYPE);
         QSPI->ENH_CTRL0 = tmpregister;
-            
+
         tmpregister = 0;
         tmpregister = (uint32_t)(QSPI_InitStruct->XIP_MBL | QSPI_InitStruct->XIP_CT_EN | QSPI_InitStruct->XIP_INST_EN | QSPI_InitStruct->XIP_INST_DDR_EN
                                 | QSPI_InitStruct->XIP_DDR_EN | QSPI_InitStruct->XIP_DFS_HC | QSPI_InitStruct->XIP_WAIT_CYCLES | QSPI_InitStruct->XIP_MD_BITS_EN
                                 | QSPI_InitStruct->XIP_INST_L | QSPI_InitStruct->XIP_ADDR_LEN | QSPI_InitStruct->XIP_TRANS_TYPE | QSPI_InitStruct->XIP_FRF);
         QSPI->XIP_CTRL = tmpregister;
-                
+
                 QSPI->XIP_MODE  = QSPI_InitStruct->XIP_MD_BITS;
                 QSPI->XIP_INCR_TOC  = QSPI_InitStruct->ITOC;
                 QSPI->XIP_WRAP_TOC  = QSPI_InitStruct->WTOC;
@@ -188,7 +188,7 @@ void QspiInitConfig(QSPI_InitType* QSPI_InitStruct)
         QSPI->RXFT  = QSPI_InitStruct->RXFT;
         QSPI->TXFN  = QSPI_InitStruct->TXFN;
         QSPI->RXFN  = QSPI_InitStruct->RXFN;
-        QSPI->DDR_TXDE  = QSPI_InitStruct->TXDE;        
+        QSPI->DDR_TXDE  = QSPI_InitStruct->TXDE;
 }
 /**
  * @brief  Configure single GPIO port as GPIO_Mode_AF_PP.
@@ -238,14 +238,14 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
         {
             QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_7); // IO1
         }
-        
+
         if (IO3_Output)
         {
             GPIO_InitStructure.Pin        = GPIO_PIN_4 | GPIO_PIN_5; // IO2 and IO3
             GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
             GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
             GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure);
-                       
+
             GPIOC->PBSC |= GPIO_PIN_4 | GPIO_PIN_5;
         }
         else
@@ -275,14 +275,14 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
         {
             QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_0); // IO1
         }
-        
+
         if (IO3_Output)
         {
             GPIO_InitStructure.Pin        = GPIO_PIN_1 | GPIO_PIN_2; // IO2 and IO3
             GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
             GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
             GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure);
-                    
+
             GPIOD->PBSC |= GPIO_PIN_1 | GPIO_PIN_2;
         }
         else
@@ -310,14 +310,14 @@ void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Out
         {
             QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_3); // IO1
         }
-        
+
         if (IO3_Output)
         {
             GPIO_InitStructure.Pin        = GPIO_PIN_4 | GPIO_PIN_5; // IO2 and IO3
             GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
             GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
             GPIO_InitPeripheral(GPIOF, &GPIO_InitStructure);
-                      
+
             GPIOF->PBSC |= GPIO_PIN_4 | GPIO_PIN_5;
         }
         else
@@ -343,13 +343,13 @@ void QSPI_DMA_CTRL_Config(uint8_t TxRx,uint8_t TxDataLevel,uint8_t RxDataLevel)
     assert_param(IS_QSPI_DMA_CTRL(TxRx));
     assert_param(IS_QSPI_DMATDL_CTRL(TxDataLevel));
     assert_param(IS_QSPI_DMARDL_CTRL(RxDataLevel));
-    
+
     QSPI->DMA_CTRL  = 0x00;
-    
+
     if (TxRx & QSPI_DMA_CTRL_TX_DMA_EN)
     {
-        QSPI->DMATDL_CTRL = TxDataLevel;  
-        QSPI->DMA_CTRL   |= QSPI_DMA_CTRL_TX_DMA_EN; 
+        QSPI->DMATDL_CTRL = TxDataLevel;
+        QSPI->DMA_CTRL   |= QSPI_DMA_CTRL_TX_DMA_EN;
     }
     if (TxRx & QSPI_DMA_CTRL_RX_DMA_EN)
     {
@@ -550,7 +550,7 @@ void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt)
 {
     uint32_t num = 0;
     uint32_t timeout = 0;
-    
+
     while (num < cnt)
     {
         QspiSendWord(*(pSrcData++));
@@ -591,7 +591,7 @@ uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t Las
     uint32_t    timeout1 = 0;
 
     QspiSendWord(WrData);                   //trammit
-    *pRdData = QspiReadWord();  
+    *pRdData = QspiReadWord();
     if(LastRd != 0)
     {
         while(!GetQspiRxHaveDataStatus())   //wait for data
@@ -602,10 +602,10 @@ uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t Las
             }
         }
 
-        *pRdData = QspiReadWord();          //read data 
-        return QSPI_SUCCESS;    
+        *pRdData = QspiReadWord();          //read data
+        return QSPI_SUCCESS;
     }
-    
+
     return QSPI_NULL;
 }
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_rcc.c

@@ -102,7 +102,7 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value);
 
 /**
  * @brief  Deinitializes the RTC registers to their default reset values.
- * @note   This function doesn't reset the RTC Clock source 
+ * @note   This function doesn't reset the RTC Clock source
  * @return An ErrorStatus enumeration value:
  *          - SUCCESS: RTC registers are deinitialized
  *          - ERROR: RTC registers are not deinitialized
@@ -1576,14 +1576,14 @@ void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd)
 void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct)
 {
     uint32_t tmptime = 0, tmpdate = 0;
-    
+
     /* Check the parameters */
     assert_param(IS_RTC_FORMAT(RTC_Format));
 
     /* Get the TimeStamp time and date registers values */
     tmptime = (uint32_t)(RTC->TST & RTC_TR_RESERVED_MASK);
     tmpdate = (uint32_t)(RTC->TSD & RTC_DATE_RESERVED_MASK);
-    
+
     /* Fill the Time structure fields with the read parameters */
     RTC_StampTimeStruct->Hours   = (uint8_t)((tmptime & (RTC_TSH_HOT | RTC_TSH_HOU)) >> 16);
     RTC_StampTimeStruct->Minutes = (uint8_t)((tmptime & (RTC_TSH_MIT | RTC_TSH_MIU)) >> 8);

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_sdio.c

@@ -456,7 +456,7 @@ void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct)
     /* Set DBCKSIZE bits according to DatBlkSize value */
     tmpregister |= (uint32_t)SDIO_DataInitStruct->DatBlkSize | SDIO_DataInitStruct->TransferDirection
                    | SDIO_DataInitStruct->TransferMode | SDIO_DataInitStruct->DPSMConfig;
-                   
+
     if(SDIO_DataInitStruct->TransferDirection)
     {
         tmpregister &= ~(1<<12);
@@ -464,7 +464,7 @@ void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct)
     else
     {
         tmpregister |= 1<<12;
-    }              
+    }
 
     /* Write to SDIO DATCTRL */
     SDIO->DATCTRL = tmpregister;

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_spi.c

@@ -2947,7 +2947,7 @@ FlagStatus TIM_GetCCENStatus(TIM_Module* TIMx, uint32_t TIM_CCEN)
                 bitstatus = RESET;
         }
     }
-    
+
     return bitstatus;
 }
 

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_tsc.c

@@ -59,7 +59,7 @@ TSC_ErrorTypeDef TSC_Init(TSC_InitType* TSC_Init)
     do
     {
         __TSC_HW_DISABLE();
-        
+
         if(++timeout > TSC_TIMEOUT)
             return TSC_ERROR_HW_MODE;
     }while (__TSC_GET_HW_MODE());
@@ -85,7 +85,7 @@ TSC_ErrorTypeDef TSC_Init(TSC_InitType* TSC_Init)
 }
 
 /**
- * @brief  Config the clock source of TSC 
+ * @brief  Config the clock source of TSC
  * @param  TSC_ClkSource specifies the clock source of TSC
  *   This parameter can be one of the following values:
  *     @arg TSC_CLK_SRC_LSI:              TSC clock source is LSI(default)
@@ -96,7 +96,7 @@ TSC_ErrorTypeDef TSC_Init(TSC_InitType* TSC_Init)
 TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
 {
     uint32_t timeout;
-    
+
     /*Enable PWR  peripheral Clock*/
     RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_PWR,ENABLE);
 
@@ -130,7 +130,7 @@ TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
     }
     else
         return TSC_ERROR_PARAMETER;
-    
+
     /*Enable TSC clk*/
     RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TSC,ENABLE);
 
@@ -138,17 +138,17 @@ TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource)
 }
 
 /**
-* @brief  Configure internal charge resistor for some channels 
+* @brief  Configure internal charge resistor for some channels
 * @param  res:  internal resistor selecte
 *   This parameter can be one of the following values:
 *      @arg TSC_RESR_CHN_RESIST_0:    1M OHM
-*      @arg TSC_RESR_CHN_RESIST_1:    882K OHM 
-*      @arg TSC_RESR_CHN_RESIST_2:    756K OHM 
-*      @arg TSC_RESR_CHN_RESIST_3:    630K OHM 
-*      @arg TSC_RESR_CHN_RESIST_4:    504K OHM 
+*      @arg TSC_RESR_CHN_RESIST_1:    882K OHM
+*      @arg TSC_RESR_CHN_RESIST_2:    756K OHM
+*      @arg TSC_RESR_CHN_RESIST_3:    630K OHM
+*      @arg TSC_RESR_CHN_RESIST_4:    504K OHM
 *      @arg TSC_RESR_CHN_RESIST_5:    378K OHM
-*      @arg TSC_RESR_CHN_RESIST_6:    252K OHM 
-*      @arg TSC_RESR_CHN_RESIST_7:    126K OHM 
+*      @arg TSC_RESR_CHN_RESIST_6:    252K OHM
+*      @arg TSC_RESR_CHN_RESIST_7:    126K OHM
 * @param  Channels: channels to be configed, as TSC_CHNEN defined
 *   This parameter:bit[0:23] used,bit[24:31] must be 0
 *                  bitx: TSC channel x
@@ -164,20 +164,20 @@ TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res )
     /*Check charge resistor value */
     if(res > TSC_RESR_CHN_RESIST_125K)
         return TSC_ERROR_PARAMETER;
-    
+
     /* waiting tsc hw for idle status.*/
     timeout = 0;
     do
     {
         __TSC_HW_DISABLE();
-        
+
         if(++timeout > TSC_TIMEOUT)
             return TSC_ERROR_HW_MODE;
     }while (__TSC_GET_HW_MODE());
 
     /* Mask invalie bits*/
     chn  = Channels & TSC_CHNEN_CHN_SEL_MASK;
-    
+
     /* Set resistance for each channel one by one*/
     for (i = 0; i<MAX_TSC_HW_CHN; i++)
     {
@@ -195,7 +195,7 @@ TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res )
 }
 
 /**
-* @brief  Configure threshold value for some channels 
+* @brief  Configure threshold value for some channels
 * @param  Channels: channels to be configed, as TSC_CHNEN defined
 *   This parameter:bit[0:23] used,bit[24:31] must be 0
 *                  bitx: TSC channel x
@@ -213,20 +213,20 @@ TSC_ErrorTypeDef TSC_ConfigThreshold(  uint32_t Channels, uint32_t base, uint32_
     /*Check the base and delta value*/
     if( (base>MAX_TSC_THRESHOLD_BASE)||(delta>MAX_TSC_THRESHOLD_DELTA))
         return TSC_ERROR_PARAMETER;
-    
+
     /* waiting tsc hw for idle status.*/
     timeout = 0;
     do
     {
         __TSC_HW_DISABLE();
-        
+
         if(++timeout > TSC_TIMEOUT)
             return TSC_ERROR_HW_MODE;
     }while (__TSC_GET_HW_MODE());
 
     /*Mask invalie bits*/
     chn = Channels & TSC_CHNEN_CHN_SEL_MASK;
-    
+
     /* Set the base and delta for each channnel one by one*/
     for (i = 0; i<MAX_TSC_HW_CHN; i++)
     {
@@ -324,7 +324,7 @@ void TSC_Cmd(TSC_Module* TSC_Def, uint32_t Channels, FunctionalState Cmd)
 {
     if(TSC_Def != TSC)
         return;
-    
+
     if (Cmd != DISABLE)
     {
         // enable tsc channel
@@ -360,7 +360,7 @@ void TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, F
 
     if(TSC_Def != TSC)
         return;
-    
+
     /* Disable the TSC HW MODE */
     while (__TSC_GET_HW_MODE())
     {
@@ -390,7 +390,7 @@ void TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, F
 
             Channel >>= 1;
         }
-        
+
         // Select to output to specified TIMER.
         if (TIMx == TIM4)
         {
@@ -419,10 +419,10 @@ void TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg)
 {
     if(TSC_Def != TSC)
         return;
-    
+
     if(AnaoCfg == 0)
         return;
-    
+
     __TSC_PAD_OPT_CONFIG(AnaoCfg->TSC_AnaoptrResisOption);
     __TSC_PAD_SPEED_CONFIG(AnaoCfg->TSC_AnaoptrSpeedOption);
 }

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_usart.c

@@ -260,7 +260,7 @@ void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct)
     /* Determine the fractional part */
     fractionaldivider = integerdivider - (100 * (tmpregister >> 4));
 
-    /* Implement the fractional part in the register */   
+    /* Implement the fractional part in the register */
     tmpregister |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
 
     /* Write to USART PBC */

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_std_periph_driver/src/n32g45x_wwdg.c

@@ -94,7 +94,7 @@
  *   This parameter can be one of the following values:
  *     @arg XFMC_BANK1_BLOCK1   XFMC Bank1 NOR/SRAM1
  *     @arg XFMC_BANK1_BLOCK2   XFMC Bank1 NOR/SRAM2
- * @retval None 
+ * @retval None
  */
 void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block)
 {
@@ -111,7 +111,7 @@ void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block)
     {
         Block->CRx = XFMC_NOR_SRAM_CR2_RESET;
     }
-    
+
     Block->TRx   = XFMC_NOR_SRAM_TR_RESET;
     Block->WTRx  = XFMC_NOR_SRAM_WTR_RESET;
 }
@@ -122,7 +122,7 @@ void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block)
  *   This parameter can be one of the following values:
  *     @arg XFMC_BANK2_NAND XFMC Bank2 NAND
  *     @arg XFMC_BANK3_NAND XFMC Bank3 NAND
- * @retval None 
+ * @retval None
  */
 void XFMC_DeInitNand(XFMC_Bank23_Module *Bank)
 {
@@ -141,7 +141,7 @@ void XFMC_DeInitNand(XFMC_Bank23_Module *Bank)
  * @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye
  *         structure that contains the configuration information for
  *        the XFMC NOR/SRAM specified Banks.
- * @retval None 
+ * @retval None
  */
 void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
 {
@@ -170,14 +170,14 @@ void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
     /* Bank1 NOR/SRAM control register configuration */
     XFMC_NORSRAMInitStruct->Block->CRx = XFMC_NORSRAMInitStruct->DataAddrMux
                                         | XFMC_NORSRAMInitStruct->MemType
-                                        | XFMC_NORSRAMInitStruct->MemDataWidth 
+                                        | XFMC_NORSRAMInitStruct->MemDataWidth
                                         | XFMC_NORSRAMInitStruct->BurstAccMode
-                                        | XFMC_NORSRAMInitStruct->AsynchroWait 
+                                        | XFMC_NORSRAMInitStruct->AsynchroWait
                                         | XFMC_NORSRAMInitStruct->WaitSigPolarity
-                                        | XFMC_NORSRAMInitStruct->WrapMode 
-                                        | XFMC_NORSRAMInitStruct->WaitSigConfig 
+                                        | XFMC_NORSRAMInitStruct->WrapMode
+                                        | XFMC_NORSRAMInitStruct->WaitSigConfig
                                         | XFMC_NORSRAMInitStruct->WriteEnable
-                                        | XFMC_NORSRAMInitStruct->WaitSigEnable 
+                                        | XFMC_NORSRAMInitStruct->WaitSigEnable
                                         | XFMC_NORSRAMInitStruct->ExtModeEnable
                                         | XFMC_NORSRAMInitStruct->WriteBurstEnable;
 
@@ -223,7 +223,7 @@ void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
  * @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType
  *         structure that contains the configuration information for the XFMC
  *         NAND specified Banks.
- * @retval None 
+ * @retval None
  */
 void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct)
 {
@@ -248,7 +248,7 @@ void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct)
 
     /* Set the tmppcr value according to XFMC_NANDInitStruct parameters */
     tmppcr =    XFMC_BANK23_MEM_TYPE_NAND
-            |   XFMC_NANDInitStruct->WaitFeatureEnable 
+            |   XFMC_NANDInitStruct->WaitFeatureEnable
             |   XFMC_NANDInitStruct->MemDataWidth
             |   XFMC_NANDInitStruct->EccEnable
             |   XFMC_NANDInitStruct->EccPageSize
@@ -440,7 +440,7 @@ void XFMC_RestartNandEcc(XFMC_Bank23_Module *Bank)
 uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank)
 {
     uint32_t tEccPageSize,tECC = 0;
-    
+
     assert_param(IS_XFMC_NAND_BANK(Bank));
 
     tEccPageSize = Bank->CTRLx & XFMC_CTRL_ECCPGS_MASK;
@@ -468,7 +468,7 @@ uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank)
         default:
                 break;
     }
-    
+
     /* Return the error correction code value */
     return (tECC);
 }

bsp/n32g452xx/Libraries/N32_Std_Driver/n32g45x_usbfs_driver/inc/usb_core.h

@@ -187,8 +187,8 @@ static int rt_hw_adc_init(void)
     for (i = 0; i < sizeof(n32_adc_obj) / sizeof(n32_adc_obj[0]); i++)
     {
         /* register ADC device */
-        if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device, 
-                    n32_adc_obj[i].name, &at_adc_ops, 
+        if (rt_hw_adc_register(&n32_adc_obj[i].n32_adc_device,
+                    n32_adc_obj[i].name, &at_adc_ops,
                     n32_adc_obj[i].ADC_Handler) == RT_EOK)
         {
             LOG_D("%s register success", n32_adc_obj[i].name);

bsp/n32g452xx/Libraries/rt_drivers/drv_adc.h

@@ -29,15 +29,15 @@
 #define MAX_PERIOD 65535
 struct rt_device_pwm pwm_device;
 
-struct at32_pwm
+struct n32_pwm
 {
     struct rt_device_pwm pwm_device;
-    TMR_Type* tim_handle;
+    TIM_Module* tim_handle;
     rt_uint8_t channel;
     char *name;
 };
 
-static struct at32_pwm at32_pwm_obj[] =
+static struct n32_pwm n32_pwm_obj[] =
 {
   #ifdef BSP_USING_TIM1_CH1
     PWM1_CONFIG,
@@ -71,21 +71,21 @@ static struct at32_pwm at32_pwm_obj[] =
     PWM8_CONFIG,
   #endif
 
-  #ifdef BSP_USING_TIM3_CH1
-    PWM9_CONFIG,
-  #endif
+#ifdef BSP_USING_TIM3_CH1
+    PWM1_TIM3_CONFIG,
+#endif
 
-  #ifdef BSP_USING_TIM3_CH2
-    PWM10_CONFIG,
-  #endif
+#ifdef BSP_USING_TIM3_CH2
+    PWM2_TIM3_CONFIG,
+#endif
 
-  #ifdef BSP_USING_TIM3_CH3
-    PWM11_CONFIG,
-  #endif
+#ifdef BSP_USING_TIM3_CH3
+    PWM3_TIM3_CONFIG,
+#endif
 
-  #ifdef BSP_USING_TIM3_CH4
-    PWM12_CONFIG,
-  #endif
+#ifdef BSP_USING_TIM3_CH4
+    PWM4_TIM3_CONFIG,
+#endif
 };
 
 static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
@@ -94,7 +94,7 @@ static struct rt_pwm_ops drv_ops =
     drv_pwm_control
 };
 
-static rt_err_t drv_pwm_enable(TMR_Type* TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+static rt_err_t drv_pwm_enable(TIM_Module* TIMx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
 {
     /* Get the value of channel */
     rt_uint32_t channel = configuration->channel;
@@ -103,145 +103,145 @@ static rt_err_t drv_pwm_enable(TMR_Type* TIMx, struct rt_pwm_configuration *conf
     {
         if(channel == 1)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_1, TIM_CCx_Disable);
+            TIM_SelectOcMode(TIMx, TIM_CH_1, TIM_OCMODE_INACTIVE);
         }
         else if(channel == 2)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_2, TIM_CCx_Disable);
+            TIM_SelectOcMode(TIMx, TIM_CH_2, TIM_OCMODE_INACTIVE);
         }
         else if(channel == 3)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_3, TIM_CCx_Disable);
+            TIM_SelectOcMode(TIMx, TIM_CH_3, TIM_OCMODE_INACTIVE);
         }
         else if(channel == 4)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_4, TIM_CCx_Disable);
+            TIM_SelectOcMode(TIMx, TIM_CH_4, TIM_OCMODE_INACTIVE);
         }
     }
     else
     {
         if(channel == 1)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_1, TIM_CCx_Enable);
+            TIM_SelectOcMode(TIMx, TIM_CH_1, TIM_OCMODE_ACTIVE);
         }
         else if(channel == 2)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_1, TIM_CCx_Enable);
+            TIM_SelectOcMode(TIMx, TIM_CH_2, TIM_OCMODE_ACTIVE);
         }
         else if(channel == 3)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_1, TIM_CCx_Enable);
+            TIM_SelectOcMode(TIMx, TIM_CH_3, TIM_OCMODE_ACTIVE);
         }
         else if(channel == 4)
         {
-          TIM_CCxCmd(TIMx, TIM_Channel_1, TIM_CCx_Enable);
+            TIM_SelectOcMode(TIMx, TIM_CH_4, TIM_OCMODE_ACTIVE);
         }
     }
 
     /* TIMx enable counter */
-    TIM_Cmd(TIMx, ENABLE);
+    TIM_Enable(TIMx, ENABLE);
+
+    rt_kprintf("2222222 ch=[%d], en=[%d]\n", channel, enable);
 
     return RT_EOK;
 }
 
-static rt_err_t drv_pwm_get(TMR_Type* TIMx, struct rt_pwm_configuration *configuration)
+static rt_err_t drv_pwm_get(TIM_Module* TIMx, struct rt_pwm_configuration *configuration)
 {
-    RCC_ClockType  RCC_Clockstruct;
+    RCC_ClocksType  RCC_Clockstruct;
     rt_uint32_t ar, div, cc1, cc2, cc3, cc4;
     rt_uint32_t channel = configuration->channel;
     rt_uint64_t tim_clock;
 
     ar   = TIMx->AR;
-    div  = TIMx->DIV;
-    cc1  = TIMx->CC1;
-    cc2  = TIMx->CC2;
-    cc3  = TIMx->CC3;
-    cc4  = TIMx->CC4;
+    div  = TIMx->PSC;
+    cc1  = TIMx->CCDAT1;
+    cc2  = TIMx->CCDAT2;
+    cc3  = TIMx->CCDAT3;
+    cc4  = TIMx->CCDAT4;
 
-    RCC_GetClocksFreq(&RCC_Clockstruct);
+    RCC_GetClocksFreqValue(&RCC_Clockstruct);
 
-    tim_clock = RCC_Clockstruct.APB2CLK_Freq;
+    tim_clock = RCC_Clockstruct.Pclk2Freq;
 
     /* Convert nanosecond to frequency and duty cycle. */
     tim_clock /= 1000000UL;
     configuration->period = (ar + 1) * (div + 1) * 1000UL / tim_clock;
     if(channel == 1)
-      configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock;
+        configuration->pulse = (cc1 + 1) * (div + 1) * 1000UL / tim_clock;
     if(channel == 2)
-      configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock;
+        configuration->pulse = (cc2 + 1) * (div+ 1) * 1000UL / tim_clock;
     if(channel == 3)
-      configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
+        configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock;
     if(channel == 4)
-      configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
+        configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock;
+
+    rt_kprintf("33333333 ch=[%d], tim_clock=[%d], pulse=[%d]\n", channel, tim_clock, configuration->pulse);
 
     return RT_EOK;
 }
 
-static rt_err_t drv_pwm_set(TMR_Type* TIMx, struct rt_pwm_configuration *configuration)
+static rt_err_t drv_pwm_set(TIM_Module* TIMx, struct rt_pwm_configuration *configuration)
 {
-    TIM_TimerBaseInitType TIM_TIMeBaseStructure;
-    TIM_OCInitType  TIM_OCInitStructure;
+    TIM_TimeBaseInitType TIM_TIMeBaseStructure;
+    OCInitType  TIM_OCInitStructure;
     rt_uint32_t period, pulse;
     rt_uint64_t psc;
     /* Get the channel number */
     rt_uint32_t channel = configuration->channel;
 
     /* Init timer pin and enable clock */
-    at32_msp_tmr_init(TIMx);
+    n32_msp_tim_init(TIMx);
 
     /* Convert nanosecond to frequency and duty cycle. */
     period = (unsigned long long)configuration->period ;
     psc = period / MAX_PERIOD + 1;
     period = period / psc;
 
-    /* TIMe base configuration */
-    TIM_TimeBaseStructInit(&TIM_TIMeBaseStructure);
-    TIM_TIMeBaseStructure.TIM_Period = period;
-    TIM_TIMeBaseStructure.TIM_DIV = psc - 1;
-    TIM_TIMeBaseStructure.TIM_ClockDivision = 0;
-    TIM_TIMeBaseStructure.TIM_CounterMode = TIM_CounterDIR_Up;
+    rt_kprintf("444444 period=[%d], psc=[%d], channel=[%d]\n", period, psc, channel);
 
-    TIM_TimeBaseInit(TIMx, &TIM_TIMeBaseStructure);
+    /* TIMe base configuration */
+    TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
+    TIM_TIMeBaseStructure.Period = period;
+    TIM_TIMeBaseStructure.Prescaler = psc - 1;
+    TIM_TIMeBaseStructure.ClkDiv = 0;
+    TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
+    TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
 
     pulse = (unsigned long long)configuration->pulse;
-
     /* PWM1 Mode configuration: Channel1 */
-    TIM_OCStructInit(&TIM_OCInitStructure);
-    TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
-    TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
-    TIM_OCInitStructure.TIM_Pulse = pulse;
-    TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+    TIM_InitOcStruct(&TIM_OCInitStructure);
+    TIM_OCInitStructure.OcMode = TIM_OCMODE_PWM1;
+    TIM_OCInitStructure.OutputState = TIM_OUTPUT_STATE_ENABLE;
+    TIM_OCInitStructure.Pulse = pulse;
+    TIM_OCInitStructure.OcPolarity = TIM_OC_POLARITY_HIGH;
 
     if(channel == 1)
     {
-      TIM_OC1Init(TIMx, &TIM_OCInitStructure);
-      TIM_OC1PreloadConfig(TIMx, TIM_OCPreload_Enable);
+        TIM_InitOc1(TIMx, &TIM_OCInitStructure);
+        TIM_ConfigOc1Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
     }
     else if(channel == 2)
     {
-      TIM_OC2Init(TIMx, &TIM_OCInitStructure);
-      TIM_OC2PreloadConfig(TIMx, TIM_OCPreload_Enable);
+        TIM_InitOc2(TIMx, &TIM_OCInitStructure);
+        TIM_ConfigOc2Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
     }
     else if(channel == 3)
     {
-      TIM_OC3Init(TIMx, &TIM_OCInitStructure);
-      TIM_OC3PreloadConfig(TIMx, TIM_OCPreload_Enable);
+        TIM_InitOc3(TIMx, &TIM_OCInitStructure);
+        TIM_ConfigOc3Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
     }
     else if(channel == 4)
     {
-      TIM_OC4Init(TIMx, &TIM_OCInitStructure);
-      TIM_OC4PreloadConfig(TIMx, TIM_OCPreload_Enable);
+        TIM_InitOc4(TIMx, &TIM_OCInitStructure);
+        TIM_ConfigOc4Preload(TIMx, TIM_OC_PRE_LOAD_ENABLE);
     }
 
-    TIM_ARPreloadConfig(TIMx, ENABLE);
+    TIM_ConfigArPreload(TIMx, ENABLE);
 
-#if defined (SOC_SERIES_AT32F415)
-    if(TIMx == TIM1)
-#else
     if(TIMx == TIM1 || TIMx == TIM8)
-#endif
     {
-      TIM_CtrlPWMOutputs(TIMx,ENABLE);
+        TIM_EnableCtrlPwmOutputs(TIMx,ENABLE);
     }
 
     return RT_EOK;
@@ -250,42 +250,45 @@ static rt_err_t drv_pwm_set(TMR_Type* TIMx, struct rt_pwm_configuration *configu
 static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
 {
     struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
-    TIM_Type *TIMx = (TIM_Type *)device->parent.user_data;
+    TIM_Module *TIMx = (TIM_Module *)device->parent.user_data;
+    rt_kprintf("11111111111\n");
 
     switch (cmd)
     {
-    case PWM_CMD_ENABLE:
-        return drv_pwm_enable(TIMx, configuration, RT_TRUE);
-    case PWM_CMD_DISABLE:
-        return drv_pwm_enable(TIMx, configuration, RT_FALSE);
-    case PWM_CMD_SET:
-        return drv_pwm_set(TIMx, configuration);
-    case PWM_CMD_GET:
-        return drv_pwm_get(TIMx, configuration);
-    default:
-        return RT_EINVAL;
+        case PWM_CMD_ENABLE:
+            return drv_pwm_enable(TIMx, configuration, RT_TRUE);
+        case PWM_CMD_DISABLE:
+            return drv_pwm_enable(TIMx, configuration, RT_FALSE);
+        case PWM_CMD_SET:
+            return drv_pwm_set(TIMx, configuration);
+        case PWM_CMD_GET:
+            return drv_pwm_get(TIMx, configuration);
+        default:
+            return RT_EINVAL;
     }
 }
 
 static int rt_hw_pwm_init(void)
 {
+    rt_kprintf("??????\n");
+
     int i = 0;
     int result = RT_EOK;
 
-    for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++)
+    for(i = 0; i < sizeof(n32_pwm_obj) / sizeof(n32_pwm_obj[0]); i++)
     {
-        if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK)
+        if(rt_device_pwm_register(&n32_pwm_obj[i].pwm_device, n32_pwm_obj[i].name, &drv_ops, n32_pwm_obj[i].tim_handle) == RT_EOK)
         {
-          LOG_D("%s register success", at32_pwm_obj[i].name);
+            LOG_D("%s register success", n32_pwm_obj[i].name);
         }
         else
         {
-          LOG_D("%s register failed", at32_pwm_obj[i].name);
-          result = -RT_ERROR;
+            LOG_D("%s register failed", n32_pwm_obj[i].name);
+            result = -RT_ERROR;
         }
+        rt_kprintf("00000 i=[%d]\n", i);
     }
 
     return result;
 }
-
 INIT_BOARD_EXPORT(rt_hw_pwm_init);

bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.h

@@ -18,137 +18,49 @@
 extern "C" {
 #endif
 
-#ifdef BSP_USING_TMR1_CH1
-#ifndef PWM1_CONFIG
-#define PWM1_CONFIG              \
-  {                              \
-    .tim_handle   = TMR1,        \
-    .name         = "tmr1pwm1",  \
-    .channel      = 1            \
-  }
-#endif /* PWM1_CONFIG */
-#endif /* BSP_USING_TMR1_CH1 */
-
-#ifdef BSP_USING_TMR1_CH2
-#ifndef PWM2_CONFIG
-#define PWM2_CONFIG              \
-  {                              \
-    .tim_handle   = TMR1,        \
-    .name         = "tmr1pwm2",  \
-    .channel      = 2            \
-  }
-#endif /* PWM2_CONFIG */
-#endif /* BSP_USING_TMR1_CH2 */
-
-#ifdef BSP_USING_TMR1_CH3
-#ifndef PWM3_CONFIG
-#define PWM3_CONFIG              \
-  {                              \
-    .tim_handle   = TMR1,        \
-    .name         = "tmr1pwm3",  \
-    .channel      = 3            \
-  }
-#endif /* PWM3_CONFIG */
-#endif /* BSP_USING_TMR1_CH3 */
-
-#ifdef BSP_USING_TMR1_CH4
-#ifndef PWM4_CONFIG
-#define PWM4_CONFIG              \
-  {                              \
-    .tim_handle   = TMR1,        \
-    .name         = "tmr1pwm4",  \
-    .channel      = 4            \
-  }
-#endif /* PWM4_CONFIG */
-#endif /* BSP_USING_TMR1_CH4 */
-
-#ifdef BSP_USING_TMR2_CH1
-#ifndef PWM5_CONFIG
-#define PWM5_CONFIG              \
-  {                              \
-    .tim_handle   = TMR2,        \
-    .name         = "tmr2pwm1",  \
-    .channel      = 1            \
-  }
-#endif /* PWM5_CONFIG */
-#endif /* BSP_USING_TMR2_CH1 */
-
-#ifdef BSP_USING_TMR2_CH2
-#ifndef PWM6_CONFIG
-#define PWM6_CONFIG              \
-  {                              \
-    .tim_handle   = TMR2,        \
-    .name         = "tmr2pwm2",  \
-    .channel      = 2            \
-  }
-#endif /* PWM6_CONFIG */
-#endif /* BSP_USING_TMR2_CH2 */
-
-#ifdef BSP_USING_TMR2_CH3
-#ifndef PWM7_CONFIG
-#define PWM7_CONFIG              \
-  {                              \
-    .tim_handle   = TMR2,        \
-    .name         = "tmr2pwm3",  \
-    .channel      = 3            \
-  }
-#endif /* PWM7_CONFIG */
-#endif /* BSP_USING_TMR2_CH3 */
-
-#ifdef BSP_USING_TMR2_CH4
-#ifndef PWM8_CONFIG
-#define PWM8_CONFIG              \
-  {                              \
-    .tim_handle   = TMR2,        \
-    .name         = "tmr2pwm4",  \
-    .channel      = 4            \
-  }
-#endif /* PWM8_CONFIG */
-#endif /* BSP_USING_TMR2_CH4 */
-
-#ifdef BSP_USING_TMR3_CH1
-#ifndef PWM9_CONFIG
-#define PWM9_CONFIG              \
-  {                              \
-    .tim_handle   = TMR3,        \
-    .name         = "tmr3pwm1",  \
-    .channel      = 1            \
-  }
-#endif /* PWM9_CONFIG */
-#endif /* BSP_USING_TMR3_CH1 */
-
-#ifdef BSP_USING_TMR3_CH2
-#ifndef PWM10_CONFIG
-#define PWM10_CONFIG             \
-  {                              \
-    .tim_handle   = TMR3,        \
-    .name         = "tmr3pwm2",  \
-    .channel      = 2            \
-  }
-#endif /* PWM10_CONFIG */
-#endif /* BSP_USING_TMR3_CH2 */
-
-#ifdef BSP_USING_TMR3_CH3
-#ifndef PWM11_CONFIG
-#define PWM11_CONFIG             \
-  {                              \
-    .tim_handle   = TMR3,        \
-    .name         = "tmr3pwm3",  \
-    .channel      = 3            \
-  }
-#endif /* PWM11_CONFIG */
-#endif /* BSP_USING_TMR3_CH3 */
-
-#ifdef BSP_USING_TMR3_CH4
-#ifndef PWM12_CONFIG
-#define PWM12_CONFIG             \
-  {                              \
-    .tim_handle   = TMR3,        \
-    .name         = "tmr3pwm4",  \
-    .channel      = 4            \
-  }
-#endif /* PWM12_CONFIG */
-#endif /* BSP_USING_TMR3_CH4 */
+#ifdef BSP_USING_TIM3_CH1
+#ifndef PWM1_TIM3_CONFIG
+#define PWM1_TIM3_CONFIG         \
+    {                              \
+        .tim_handle   = TIM3,        \
+        .name         = "tim3pwm1",  \
+        .channel      = 1            \
+    }
+#endif /* PWM1_TIM3_CONFIG */
+#endif /* BSP_USING_TIM3_CH1 */
+
+#ifdef BSP_USING_TIM3_CH2
+#ifndef PWM2_TIM3_CONFIG
+#define PWM2_TIM3_CONFIG         \
+    {                              \
+        .tim_handle   = TIM3,        \
+        .name         = "tim3pwm2",  \
+        .channel      = 2            \
+    }
+#endif /* PWM2_TIM3_CONFIG */
+#endif /* BSP_USING_TIM3_CH2 */
+
+#ifdef BSP_USING_TIM3_CH3
+#ifndef PWM3_TIM3_CONFIG
+#define PWM3_TIM3_CONFIG         \
+    {                              \
+        .tim_handle   = TIM3,        \
+        .name         = "tim3pwm3",  \
+        .channel      = 3            \
+    }
+#endif /* PWM3_TIM3_CONFIG */
+#endif /* BSP_USING_TIM3_CH3 */
+
+#ifdef BSP_USING_TIM3_CH4
+#ifndef PWM4_TIM3_CONFIG
+#define PWM4_TIM3_CONFIG             \
+    {                              \
+        .tim_handle   = TIM3,        \
+        .name         = "tim3pwm4",  \
+        .channel      = 4            \
+    }
+#endif /* PWM4_TIM3_CONFIG */
+#endif /* BSP_USING_TIM3_CH4 */
 
 #ifdef __cplusplus
 }

bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c

@@ -1,7 +1,7 @@
 /*
  * File      : usart.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at

bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h

@@ -135,7 +135,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
@@ -572,7 +572,12 @@ CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
-# CONFIG_BSP_USING_PWM is not set
+CONFIG_BSP_USING_PWM=y
+CONFIG_BSP_USING_TIM3=y
+CONFIG_BSP_USING_TIM3_CH1=y
+CONFIG_BSP_USING_TIM3_CH2=y
+CONFIG_BSP_USING_TIM3_CH3=y
+CONFIG_BSP_USING_TIM3_CH4=y
 # CONFIG_BSP_USING_HWTIMER is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_I2C1 is not set

bsp/n32g452xx/n32g452xx-mini-system/applications/main.c

@@ -50,28 +50,21 @@ menu "On-chip Peripheral Drivers"
         default n
         select RT_USING_PWM
         if BSP_USING_PWM
-        menuconfig BSP_USING_TIM1
-            bool "Enable timer1 output PWM"
+        menuconfig BSP_USING_TIM3
+            bool "Enable timer3 output PWM"
             default n
-            if BSP_USING_TIM1
-                config BSP_USING_TIM1_CH1
-                    bool "Enable TIM1 channel1 PWM"
+            if BSP_USING_TIM3
+                config BSP_USING_TIM3_CH1
+                    bool "Enable TIM3 channel1 PWM"
                     default n
-
-                config BSP_USING_TIM1_CH4
-                    bool "Enable TIM1 channel4 PWM"
+                config BSP_USING_TIM3_CH2
+                    bool "Enable TIM3 channel2 PWM"
                     default n
-            endif
-        menuconfig BSP_USING_TIM2
-            bool "Enable timer2 output PWM"
-            default n
-            if BSP_USING_TIM2
-                config BSP_USING_TIM2_CH1
-                    bool "Enable TIM2 channel1 PWM"
+                config BSP_USING_TIM3_CH3
+                    bool "Enable TIM3 channel2 PWM"
                     default n
-
-                config BSP_USING_TIM2_CH2
-                    bool "Enable TIM2 channel2 PWM"
+                config BSP_USING_TIM3_CH4
+                    bool "Enable TIM3 channel2 PWM"
                     default n
             endif
         endif

bsp/n32g452xx/n32g452xx-mini-system/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -162,36 +162,51 @@ void n32_msp_tim_init(void *Instance)
     GPIO_InitStruct(&GPIO_InitCtlStructure);
     TIM_Module *TIMx = (TIM_Module *)Instance;
 
-    if(TIMx == TIM1)
+//    if(TIMx == TIM1)
+//    {
+//        /* TIM1 clock enable */
+//        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
+//        /* GPIOA clock enable */
+//        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+//
+//        /* GPIOA Configuration:TIM1 Channel1 and Channel4 as alternate function push-pull */
+//        GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_11;
+//        GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+//        GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
+//
+//        GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
+//    }
+
+//    if(TIMx == TIM2)
+//    {
+//        /* TIM2 clock enable */
+//        RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE);
+//        /* GPIOA clock enable */
+//        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+//
+//        /* GPIOA Configuration:TIM2 Channel1 and Channel2 as alternate function push-pull */
+//        GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1;
+//        GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+//        GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
+//
+//        GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
+//    }
+
+    if(TIMx == TIM3)
     {
-        /* TIM1 clock enable */
-        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_TIM1, ENABLE);
+        /* TIM3 clock enable */
+        RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM3, ENABLE);
         /* GPIOA clock enable */
-        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
+        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA|RCC_APB2_PERIPH_GPIOB, ENABLE);
 
-        /* GPIOA Configuration:TIM1 Channel1 and Channel4 as alternate function push-pull */
-        GPIO_InitCtlStructure.Pin = GPIO_PIN_8 | GPIO_PIN_11;
+        GPIO_InitCtlStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
         GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
         GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
         GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
-    }
 
-    if(TIMx == TIM2)
-    {
-        /* TIM2 clock enable */
-        RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_TIM2, ENABLE);
-        /* GPIOA clock enable */
-        RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA, ENABLE);
-
-        /* GPIOA Configuration:TIM2 Channel1 and Channel2 as alternate function push-pull */
         GPIO_InitCtlStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1;
-        GPIO_InitCtlStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-        GPIO_InitCtlStructure.GPIO_Speed = GPIO_Speed_50MHz;
-
-        GPIO_InitPeripheral(GPIOA, &GPIO_InitCtlStructure);
+        GPIO_InitPeripheral(GPIOB, &GPIO_InitCtlStructure);
     }
-    /* Add others */
 }
 #endif /* BSP_USING_PWM */
 
@@ -459,6 +474,31 @@ static int hwtimer_sample(int argc, char *argv[])
 MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
 #endif
 
+#ifdef RT_USING_PWM
+static int pwm_set_test(const char *name, int ch,
+                        rt_uint32_t period, rt_uint32_t pulse)
+{
+    struct rt_device_pwm *pwm_dev = (struct rt_device_pwm *)rt_device_find(name);
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("pwm sample run failed! can't find %s device!\n", name);
+        return RT_ERROR;
+    }
+    rt_pwm_set(pwm_dev, ch, period, pulse);
+    rt_pwm_enable(pwm_dev, ch);
+    return RT_EOK;
+}
+static int pwm_led_sample(int argc, char *argv[])
+{
+    pwm_set_test("tim3pwm1", 1, 1000, 200);
+    pwm_set_test("tim3pwm2", 2, 1000, 400);
+    pwm_set_test("tim3pwm3", 3, 1000, 600);
+    pwm_set_test("tim3pwm4", 4, 1000, 700);
+    return RT_EOK;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(pwm_led_sample, pwm sample);
+#endif
 
 #endif
 

bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2021-04-13     shelton      first version
  */
- 
+
 #ifndef __N32_MSP_H__
 #define __N32_MSP_H__
 

bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h

@@ -83,6 +83,7 @@
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
+#define RT_USING_PWM
 
 /* Using USB */
 
@@ -177,5 +178,11 @@
 #define RT_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART1
+#define BSP_USING_PWM
+#define BSP_USING_TIM3
+#define BSP_USING_TIM3_CH1
+#define BSP_USING_TIM3_CH2
+#define BSP_USING_TIM3_CH3
+#define BSP_USING_TIM3_CH4
 
 #endif