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@@ -68,10 +68,7 @@ static void RCC_Configuration(void)
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OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
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OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
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OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
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OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
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OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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- if (HAL_RCC_OscConfig(&OscInit) != HAL_OK)
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- {
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- RT_ASSERT(RT_NULL);
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- }
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+ HAL_RCC_OscConfig(&OscInit);
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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clocks dividers */
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@@ -84,10 +81,7 @@ static void RCC_Configuration(void)
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ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1;
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ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1;
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ClkInit.APB1CLKDivider = RCC_HCLK_DIV1;
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ClkInit.APB1CLKDivider = RCC_HCLK_DIV1;
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ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
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ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
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- if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK)
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- {
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- RT_ASSERT(RT_NULL);
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- }
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+ HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1);
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}
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}
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#ifdef PRINT_RCC_FREQ_INFO
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#ifdef PRINT_RCC_FREQ_INFO
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