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@@ -1,3 +1,11 @@
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+/*
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+ * Copyright (c) 2006-2018, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ */
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#ifndef __DRV_CODEC_H__
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#define __DRV_CODEC_H__
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@@ -58,7 +66,6 @@
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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-
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/*DAC_MIXER_CTRL: 0x20*/
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#define DAC_AG_R_EN 31 /* dac right enable bit */
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#define DAC_AG_L_EN 30 /* dac left enable bit */
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@@ -154,8 +161,6 @@
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#define ADDA_PR_RDAT 0
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-
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-/* 时钟配置相关寄存器 */
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#define R6_REG_CCU_BASE 0x01c20000
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#define R6_REG_PLL_AUDIO_CTRL (R6_REG_CCU_BASE + 0x008)
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#define R6_REG_BUS_CLK_GATING_0 (R6_REG_CCU_BASE + 0x060)
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@@ -166,7 +171,6 @@
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#define R6_REG_BUS_SOFT_RST_1 (R6_REG_CCU_BASE + 0x02C4)
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#define R6_REG_BUS_SOFT_RST_2 (R6_REG_CCU_BASE + 0x02D0)
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-/* GPIO配置相关寄存器 */
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#define R6_REG_PIO_BASE 0x01c20800
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#define R6_REG_PD_CFG0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X00))
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#define R6_REG_PD_CFG1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X04))
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@@ -178,8 +182,6 @@
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#define R6_REG_PD_PUL0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X1c))
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#define R6_REG_PD_PUL1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X20))
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-
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-/* AUDIO配置相关寄存器 */
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#define R6_REG_AC_BASE 0x01c23c00
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#define R6_REG_AC_DAC_DPC (R6_REG_AC_BASE + 0x00)
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#define R6_REG_AC_DAC_FIFOC (R6_REG_AC_BASE + 0x04)
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@@ -192,7 +194,6 @@
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#define R6_REG_ADC_MIXER_CTRL (R6_REG_AC_BASE + 0x24)
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#define R6_REG_AC_DAC_CNT (R6_REG_AC_BASE + 0x40)
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-/* DMA配置相关寄存器 */
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#define R6_REG_NDMA_0_BASE (0x01c02000 + 0x100 + 0 * 0x20)
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#define R6_REG_DMA_INT_CTRL (0x01c02000 + 0x00)
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@@ -202,8 +203,6 @@
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#define REG_NDMA_SRC_ADR (0x4)
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#define REG_NDMA_DES_ADR (0x8)
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#define REG_NDMA_BYTE_CNT (0xc)
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-// #define REG_NDMA_PAR (0x300 + 0x1c)
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-
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#define NDMA_CFG_SRC_DRQ_IR_RX (0x00 << 0)
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#define NDMA_CFG_SRC_DRQ_NONE (0x01 << 0)
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