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@@ -17,6 +17,8 @@
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/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
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/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
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#define L1CACHE_LINESIZE_BYTE (32)
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#define L1CACHE_LINESIZE_BYTE (32)
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+#ifdef RT_USING_CACHE
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+
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void rt_hw_cpu_icache_enable(void)
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void rt_hw_cpu_icache_enable(void)
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{
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{
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SCB_EnableICache();
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SCB_EnableICache();
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@@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
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RT_ASSERT(0);
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RT_ASSERT(0);
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}
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}
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}
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}
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+
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+#endif /* RT_USING_CACHE */
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+
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wirano