修复RTC问题，增加GCC工具链

bsp/swm320/.config

@@ -21,6 +21,13 @@ CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
 CONFIG_RT_DEBUG=y
 CONFIG_RT_DEBUG_COLOR=y
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -54,6 +61,7 @@ CONFIG_RT_USING_MEMHEAP=y
 # CONFIG_RT_USING_SLAB is not set
 CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
 # CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
 #
@@ -64,8 +72,9 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-CONFIG_RT_VER_NUM=0x40003
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
 CONFIG_ARCH_ARM=y
 CONFIG_RT_USING_CPU_FFS=y
 CONFIG_ARCH_ARM_CORTEX_M=y
@@ -89,19 +98,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
 CONFIG_FINSH_ARG_MAX=10
 
 #
@@ -116,6 +125,8 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
@@ -154,6 +165,7 @@ CONFIG_RT_USING_PIN=y
 CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set
 # CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 
 #
 # Network
@@ -190,8 +202,14 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_LWP is not set
 
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
 #
 # RT-Thread online packages
 #
@@ -239,6 +257,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
 
 #
 # IoT Cloud
@@ -259,8 +278,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LIBRWS is not set
 # CONFIG_PKG_USING_TCPSERVER is not set
 # CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
@@ -275,6 +292,13 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
 
 #
 # security packages
@@ -291,6 +315,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
 
 #
 # multimedia packages
@@ -300,9 +325,13 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
 # CONFIG_PKG_USING_HELIX is not set
 # CONFIG_PKG_USING_AZUREGUIX is not set
 # CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
 
 #
 # tools packages
@@ -311,6 +340,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
@@ -339,15 +369,37 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_ANV_MEMLEAK is not set
 # CONFIG_PKG_USING_ANV_TESTSUIT is not set
 # CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
 
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_PERSIMMON is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
 # CONFIG_PKG_USING_FLASHDB is not set
@@ -357,6 +409,9 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
 # CONFIG_PKG_USING_EV is not set
@@ -366,24 +421,14 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_RAMDISK is not set
 # CONFIG_PKG_USING_MININI is not set
 # CONFIG_PKG_USING_QBOOT is not set
-
-#
-# Micrium: Micrium software products porting for RT-Thread
-#
-# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
-# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
-# CONFIG_PKG_USING_UC_CRC is not set
-# CONFIG_PKG_USING_UC_CLK is not set
-# CONFIG_PKG_USING_UC_COMMON is not set
-# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
-# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
-# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
-# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
-# CONFIG_PKG_USING_QFPLIB_M3 is not set
 # CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
 
 #
 # peripheral libraries and drivers
@@ -408,7 +453,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@@ -446,10 +490,55 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
 # CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
 
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -460,44 +549,25 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
-
-#
-# games: games run on RT-Thread console
-#
-# CONFIG_PKG_USING_THREES is not set
-# CONFIG_PKG_USING_2048 is not set
-# CONFIG_PKG_USING_SNAKE is not set
-# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_LWGPS is not set
-# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
 # CONFIG_PKG_USING_MCURSES is not set
 # CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
 
 #
 # Hardware Drivers Config
@@ -508,8 +578,8 @@ CONFIG_SOC_SWM320=y
 # On-chip Peripheral Drivers
 #
 CONFIG_BSP_USING_UART=y
-CONFIG_BSP_USING_UART0=y
-# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART0 is not set
+CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
 CONFIG_BSP_USING_GPIO=y

bsp/swm320/JLinkLog.txt

@@ -0,0 +1,3853 @@
+T2F54 000:021.957   SEGGER J-Link V7.22b Log File
+T2F54 000:022.144   DLL Compiled: Jun 17 2021 17:22:49
+T2F54 000:022.150   Logging started @ 2021-09-13 08:02
+T2F54 000:022.156 - 22.159ms
+T2F54 000:022.170 JLINK_SetWarnOutHandler(...)
+T2F54 000:022.178 - 0.010ms
+T2F54 000:022.186 JLINK_OpenEx(...)
+T2F54 000:026.399   Firmware: J-Link EDU Mini V1 compiled Jun 24 2021 14:29:39
+T2F54 000:026.816   Firmware: J-Link EDU Mini V1 compiled Jun 24 2021 14:29:39
+T2F54 000:027.029   Decompressing FW timestamp took 154 us
+T2F54 000:041.069   Hardware: V1.00
+T2F54 000:041.087   S/N: 801010789
+T2F54 000:041.105   OEM: SEGGER
+T2F54 000:041.113   Feature(s): FlashBP, GDB
+T2F54 000:043.624   TELNET listener socket opened on port 19021
+T2F54 000:043.796   WEBSRV Starting webserver
+T2F54 000:044.069   WEBSRV Webserver running on local port 19080
+T2F54 000:044.082 - 21.899ms returns "O.K."
+T2F54 000:044.103 JLINK_GetEmuCaps()
+T2F54 000:044.160 - 0.061ms returns 0xB8EA5A33
+T2F54 000:044.178 JLINK_TIF_GetAvailable(...)
+T2F54 000:044.447 - 0.277ms
+T2F54 000:044.467 JLINK_SetErrorOutHandler(...)
+T2F54 000:044.473 - 0.009ms
+T2F54 000:044.507 JLINK_ExecCommand("ProjectFile = "D:\rtthread\rt-thread\bsp\swm320\JLinkSettings.ini"", ...). 
+T2F54 000:085.730   Device "CORTEX-M4" selected.
+T2F54 000:086.144 - 41.645ms returns 0x00
+T2F54 000:091.652 JLINK_ExecCommand("Device = SWM320xE", ...). 
+T2F54 000:096.908   Device "CORTEX-M4" selected.
+T2F54 000:097.347 - 5.674ms returns 0x00
+T2F54 000:097.380 JLINK_GetHardwareVersion()
+T2F54 000:097.387 - 0.010ms returns 10000
+T2F54 000:097.396 JLINK_GetDLLVersion()
+T2F54 000:097.401 - 0.008ms returns 72202
+T2F54 000:097.411 JLINK_GetOEMString(...)
+T2F54 000:097.419 JLINK_GetFirmwareString(...)
+T2F54 000:097.431 - 0.014ms
+T2F54 000:119.534 JLINK_GetDLLVersion()
+T2F54 000:119.555 - 0.023ms returns 72202
+T2F54 000:119.563 JLINK_GetCompileDateTime()
+T2F54 000:119.569 - 0.008ms
+T2F54 000:123.944 JLINK_GetFirmwareString(...)
+T2F54 000:123.962 - 0.021ms
+T2F54 000:128.443 JLINK_GetHardwareVersion()
+T2F54 000:128.461 - 0.041ms returns 10000
+T2F54 000:133.941 JLINK_GetSN()
+T2F54 000:133.961 - 0.022ms returns 801010789
+T2F54 000:138.334 JLINK_GetOEMString(...)
+T2F54 000:148.487 JLINK_TIF_Select(JLINKARM_TIF_SWD)
+T2F54 000:149.606 - 1.164ms returns 0x00
+T2F54 000:149.660 JLINK_HasError()
+T2F54 000:149.687 JLINK_SetSpeed(5000)
+T2F54 000:149.810 - 0.130ms
+T2F54 000:149.825 JLINK_GetId()
+T2F54 000:154.948   Found SW-DP with ID 0x2BA01477
+T2F54 000:164.094   DPIDR: 0x2BA01477
+T2F54 000:170.491   Scanning AP map to find all available APs
+T2F54 000:175.736   AP[1]: Stopped AP scan as end of AP map has been reached
+T2F54 000:180.016   AP[0]: AHB-AP (IDR: 0x24770011)
+T2F54 000:184.916   Iterating through AP map to find AHB-AP to use
+T2F54 000:190.193   AP[0]: Core found
+T2F54 000:195.585   AP[0]: AHB-AP ROM base: 0xE00FF000
+T2F54 000:200.822   CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
+T2F54 000:205.003   Found Cortex-M4 r0p1, Little endian.
+T2F54 000:306.274   -- Max. mem block: 0x000013E0
+T2F54 000:306.441   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 000:306.861   CPU_WriteMem(4 bytes @ 0xE000EDF0)
+T2F54 000:307.251   CPU_ReadMem(4 bytes @ 0xE0002000)
+T2F54 000:312.226   FPUnit: 6 code (BP) slots and 2 literal slots
+T2F54 000:312.253   CPU_ReadMem(4 bytes @ 0xE000EDFC)
+T2F54 000:312.696   CPU_WriteMem(4 bytes @ 0xE000EDFC)
+T2F54 000:313.163   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:313.599   CPU_WriteMem(4 bytes @ 0xE0001000)
+T2F54 000:314.050   CPU_ReadMem(4 bytes @ 0xE000ED88)
+T2F54 000:314.502   CPU_WriteMem(4 bytes @ 0xE000ED88)
+T2F54 000:314.995   CPU_ReadMem(4 bytes @ 0xE000ED88)
+T2F54 000:315.476   CPU_WriteMem(4 bytes @ 0xE000ED88)
+T2F54 000:323.078   CoreSight components:
+T2F54 000:327.342   ROMTbl[0] @ E00FF000
+T2F54 000:327.370   CPU_ReadMem(64 bytes @ 0xE00FF000)
+T2F54 000:328.547   CPU_ReadMem(32 bytes @ 0xE000EFE0)
+T2F54 000:334.608   ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB000 SCS
+T2F54 000:334.637   CPU_ReadMem(32 bytes @ 0xE0001FE0)
+T2F54 000:340.129   ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
+T2F54 000:340.157   CPU_ReadMem(32 bytes @ 0xE0002FE0)
+T2F54 000:345.515   ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
+T2F54 000:345.544   CPU_ReadMem(32 bytes @ 0xE0000FE0)
+T2F54 000:354.310   ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
+T2F54 000:354.340   CPU_ReadMem(32 bytes @ 0xE0040FE0)
+T2F54 000:359.505   ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
+T2F54 000:359.830 - 210.013ms returns 0x2BA01477
+T2F54 000:359.861 JLINK_GetDLLVersion()
+T2F54 000:359.867 - 0.009ms returns 72202
+T2F54 000:359.876 JLINK_CORE_GetFound()
+T2F54 000:359.882 - 0.009ms returns 0xE0000FF
+T2F54 000:359.920 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX)
+T2F54 000:359.928   Value=0xE00FF000
+T2F54 000:359.936 - 0.019ms returns 0
+T2F54 000:365.954 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX)
+T2F54 000:366.015   Value=0xE00FF000
+T2F54 000:366.024 - 0.073ms returns 0
+T2F54 000:366.049 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX)
+T2F54 000:366.056   Value=0x00000000
+T2F54 000:366.084 - 0.038ms returns 0
+T2F54 000:366.110 JLINK_ReadMemEx(0xE0041FF0, 0x10 Bytes, Flags = 0x02000004)
+T2F54 000:366.161   CPU_ReadMem(16 bytes @ 0xE0041FF0)
+T2F54 000:366.698   Data:  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+T2F54 000:366.711 - 0.604ms returns 16 (0x10)
+T2F54 000:366.722 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX)
+T2F54 000:366.729   Value=0x00000000
+T2F54 000:366.737 - 0.017ms returns 0
+T2F54 000:366.744 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX)
+T2F54 000:366.750   Value=0xE0040000
+T2F54 000:366.758 - 0.016ms returns 0
+T2F54 000:366.765 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX)
+T2F54 000:366.771   Value=0xE0000000
+T2F54 000:366.779 - 0.016ms returns 0
+T2F54 000:366.786 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX)
+T2F54 000:366.792   Value=0xE0001000
+T2F54 000:366.799 - 0.016ms returns 0
+T2F54 000:366.807 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX)
+T2F54 000:366.812   Value=0xE0002000
+T2F54 000:366.820 - 0.016ms returns 0
+T2F54 000:366.827 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX)
+T2F54 000:366.833   Value=0xE000E000
+T2F54 000:366.841 - 0.016ms returns 0
+T2F54 000:366.848 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX)
+T2F54 000:366.854   Value=0xE000EDF0
+T2F54 000:366.862 - 0.016ms returns 0
+T2F54 000:366.869 JLINK_GetDebugInfo(0x01 = Unknown)
+T2F54 000:366.875   Value=0x00000001
+T2F54 000:366.883 - 0.016ms returns 0
+T2F54 000:366.890 JLINK_ReadMemU32(0xE000ED00, 0x1 Items)
+T2F54 000:366.900   CPU_ReadMem(4 bytes @ 0xE000ED00)
+T2F54 000:367.307   Data:  41 C2 0F 41
+T2F54 000:367.324   Debug reg: CPUID
+T2F54 000:367.332 - 0.445ms returns 1 (0x1)
+T2F54 000:367.343 JLINK_GetDebugInfo(0x10F = JLINKARM_DEBUG_INFO_HAS_CORTEX_M_SECURITY_EXT_INDEX)
+T2F54 000:367.349   Value=0x00000000
+T2F54 000:367.357 - 0.017ms returns 0
+T2F54 000:367.365 JLINK_HasError()
+T2F54 000:367.373 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL)
+T2F54 000:367.379 - 0.008ms returns JLINKARM_CM3_RESET_TYPE_NORMAL
+T2F54 000:367.387 JLINK_Reset()
+T2F54 000:367.414   CPU is running
+T2F54 000:367.424   CPU_WriteMem(4 bytes @ 0xE000EDF0)
+T2F54 000:367.831   CPU is running
+T2F54 000:367.846   CPU_WriteMem(4 bytes @ 0xE000EDFC)
+T2F54 000:372.873   Reset: Halt core after reset via DEMCR.VC_CORERESET.
+T2F54 000:377.958   Reset: Reset device via AIRCR.SYSRESETREQ.
+T2F54 000:378.011   CPU is running
+T2F54 000:378.037   CPU_WriteMem(4 bytes @ 0xE000ED0C)
+T2F54 000:432.012   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 000:432.429   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 000:432.814   CPU is running
+T2F54 000:432.829   CPU_WriteMem(4 bytes @ 0xE000EDF0)
+T2F54 000:433.241   CPU is running
+T2F54 000:433.272   CPU_WriteMem(4 bytes @ 0xE000EDFC)
+T2F54 000:438.853   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 000:442.666   CPU_WriteMem(4 bytes @ 0xE0002000)
+T2F54 000:443.214   CPU_ReadMem(4 bytes @ 0xE000EDFC)
+T2F54 000:443.771   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:444.213 - 76.839ms
+T2F54 000:444.248 JLINK_Halt()
+T2F54 000:444.261 - 0.020ms returns 0x00
+T2F54 000:444.295 JLINK_ReadMemU32(0xE000EDF0, 0x1 Items)
+T2F54 000:444.329   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 000:444.765   Data:  03 00 03 00
+T2F54 000:444.795   Debug reg: DHCSR
+T2F54 000:444.822 - 0.529ms returns 1 (0x1)
+T2F54 000:444.837 JLINK_WriteU32_64(0xE000EDF0, 0xA05F0003)
+T2F54 000:444.862   Debug reg: DHCSR
+T2F54 000:445.515   CPU_WriteMem(4 bytes @ 0xE000EDF0)
+T2F54 000:445.879 - 1.051ms returns 0 (0x00000000)
+T2F54 000:445.902 JLINK_WriteU32_64(0xE000EDFC, 0x01000000)
+T2F54 000:445.910   Debug reg: DEMCR
+T2F54 000:445.929   CPU_WriteMem(4 bytes @ 0xE000EDFC)
+T2F54 000:446.290 - 0.396ms returns 0 (0x00000000)
+T2F54 000:468.997 JLINK_GetHWStatus(...)
+T2F54 000:469.302 - 0.314ms returns 0
+T2F54 000:485.116 JLINK_GetNumBPUnits(Type = 0xFFFFFF00)
+T2F54 000:485.138 - 0.025ms returns 0x06
+T2F54 000:485.147 JLINK_GetNumBPUnits(Type = 0xF0)
+T2F54 000:485.152 - 0.008ms returns 0x2000
+T2F54 000:485.160 JLINK_GetNumWPUnits()
+T2F54 000:485.165 - 0.008ms returns 4
+T2F54 000:500.751 JLINK_GetSpeed()
+T2F54 000:500.771 - 0.023ms returns 4000
+T2F54 000:511.271 JLINK_ReadMemU32(0xE000E004, 0x1 Items)
+T2F54 000:511.306   CPU_ReadMem(4 bytes @ 0xE000E004)
+T2F54 000:511.739   Data:  02 00 00 00
+T2F54 000:511.774 - 0.506ms returns 1 (0x1)
+T2F54 000:511.785 JLINK_ReadMemU32(0xE000E004, 0x1 Items)
+T2F54 000:511.797   CPU_ReadMem(4 bytes @ 0xE000E004)
+T2F54 000:512.182   Data:  02 00 00 00
+T2F54 000:512.197 - 0.414ms returns 1 (0x1)
+T2F54 000:512.208 JLINK_WriteMemEx(0xE0001000, 0x0000001C Bytes, Flags = 0x02000004)
+T2F54 000:512.216   Data:  01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
+T2F54 000:512.238   CPU_WriteMem(28 bytes @ 0xE0001000)
+T2F54 000:512.772 - 0.586ms returns 0x1C
+T2F54 000:512.826 JLINK_Halt()
+T2F54 000:512.846 - 0.022ms returns 0x00
+T2F54 000:512.854 JLINK_IsHalted()
+T2F54 000:512.860 - 0.009ms returns TRUE
+T2F54 000:517.052 JLINK_WriteMem(0x20000000, 0x108 Bytes, ...)
+T2F54 000:517.067   Data:  00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ...
+T2F54 000:517.336   CPU_WriteMem(264 bytes @ 0x20000000)
+T2F54 000:519.136 - 2.090ms returns 0x108
+T2F54 000:519.168 JLINK_HasError()
+T2F54 000:519.178 JLINK_WriteReg(R0, 0x00000000)
+T2F54 000:519.187 - 0.012ms returns 0
+T2F54 000:519.195 JLINK_WriteReg(R1, 0x00B71B00)
+T2F54 000:519.202 - 0.009ms returns 0
+T2F54 000:519.210 JLINK_WriteReg(R2, 0x00000001)
+T2F54 000:519.216 - 0.009ms returns 0
+T2F54 000:519.224 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:519.230 - 0.009ms returns 0
+T2F54 000:519.238 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:519.244 - 0.009ms returns 0
+T2F54 000:519.251 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:519.257 - 0.009ms returns 0
+T2F54 000:519.265 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:519.271 - 0.009ms returns 0
+T2F54 000:519.279 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:519.285 - 0.009ms returns 0
+T2F54 000:519.293 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:519.311 - 0.021ms returns 0
+T2F54 000:519.319 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:519.325 - 0.009ms returns 0
+T2F54 000:519.332 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:519.338 - 0.008ms returns 0
+T2F54 000:519.346 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:519.352 - 0.008ms returns 0
+T2F54 000:519.359 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:519.365 - 0.008ms returns 0
+T2F54 000:519.372 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:519.379 - 0.009ms returns 0
+T2F54 000:519.387 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:519.393 - 0.008ms returns 0
+T2F54 000:519.400 JLINK_WriteReg(R15 (PC), 0x20000040)
+T2F54 000:519.412 - 0.015ms returns 0
+T2F54 000:519.420 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:519.426 - 0.009ms returns 0
+T2F54 000:519.433 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:519.439 - 0.008ms returns 0
+T2F54 000:519.447 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:519.455 - 0.012ms returns 0
+T2F54 000:519.464 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:519.470 - 0.008ms returns 0
+T2F54 000:519.480 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:519.490   CPU_ReadMem(4 bytes @ 0x20000000)
+T2F54 000:519.884   CPU_WriteMem(4 bytes @ 0x20000000)
+T2F54 000:520.303   CPU_ReadMem(4 bytes @ 0x20000000)
+T2F54 000:520.737   CPU_WriteMem(4 bytes @ 0x20000000)
+T2F54 000:521.234   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:521.648 - 2.200ms returns 0x00000001
+T2F54 000:521.691 JLINK_Go()
+T2F54 000:521.703   CPU_WriteMem(2 bytes @ 0x20000000)
+T2F54 000:522.179   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:522.583   CPU_WriteMem(4 bytes @ 0xE0002008)
+T2F54 000:522.598   CPU_WriteMem(4 bytes @ 0xE000200C)
+T2F54 000:522.607   CPU_WriteMem(4 bytes @ 0xE0002010)
+T2F54 000:522.616   CPU_WriteMem(4 bytes @ 0xE0002014)
+T2F54 000:522.624   CPU_WriteMem(4 bytes @ 0xE0002018)
+T2F54 000:522.632   CPU_WriteMem(4 bytes @ 0xE000201C)
+T2F54 000:524.188   CPU_WriteMem(4 bytes @ 0xE0001004)
+T2F54 000:527.604 - 5.919ms
+T2F54 000:527.623 JLINK_IsHalted()
+T2F54 000:530.660   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:531.029 - 3.414ms returns TRUE
+T2F54 000:531.050 JLINK_ReadReg(R15 (PC))
+T2F54 000:531.059 - 0.012ms returns 0x20000000
+T2F54 000:531.068 JLINK_ClrBPEx(BPHandle = 0x00000001)
+T2F54 000:531.074 - 0.009ms returns 0x00
+T2F54 000:531.082 JLINK_ReadReg(R0)
+T2F54 000:531.089 - 0.009ms returns 0x00000000
+T2F54 000:532.228 JLINK_HasError()
+T2F54 000:532.251 JLINK_WriteReg(R0, 0x00000000)
+T2F54 000:532.261 - 0.013ms returns 0
+T2F54 000:532.269 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:532.279 - 0.012ms returns 0
+T2F54 000:532.306 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:532.312 - 0.009ms returns 0
+T2F54 000:532.320 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:532.326 - 0.009ms returns 0
+T2F54 000:532.334 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:532.340 - 0.009ms returns 0
+T2F54 000:532.348 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:532.354 - 0.009ms returns 0
+T2F54 000:532.362 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:532.368 - 0.009ms returns 0
+T2F54 000:532.376 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:532.383 - 0.009ms returns 0
+T2F54 000:532.406 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:532.413 - 0.009ms returns 0
+T2F54 000:532.422 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:532.428 - 0.009ms returns 0
+T2F54 000:532.435 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:532.442 - 0.009ms returns 0
+T2F54 000:532.452 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:532.458 - 0.030ms returns 0
+T2F54 000:532.487 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:532.494 - 0.009ms returns 0
+T2F54 000:532.501 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:532.508 - 0.009ms returns 0
+T2F54 000:532.532 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:532.538 - 0.009ms returns 0
+T2F54 000:532.546 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:532.552 - 0.009ms returns 0
+T2F54 000:532.560 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:532.585 - 0.028ms returns 0
+T2F54 000:532.593 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:532.599 - 0.009ms returns 0
+T2F54 000:532.607 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:532.613 - 0.009ms returns 0
+T2F54 000:532.634 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:532.641 - 0.009ms returns 0
+T2F54 000:532.649 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:532.661 - 0.015ms returns 0x00000002
+T2F54 000:532.669 JLINK_Go()
+T2F54 000:532.684   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:536.067 - 3.412ms
+T2F54 000:536.090 JLINK_IsHalted()
+T2F54 000:539.197   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:539.566 - 3.502ms returns TRUE
+T2F54 000:539.602 JLINK_ReadReg(R15 (PC))
+T2F54 000:539.625 - 0.026ms returns 0x20000000
+T2F54 000:539.634 JLINK_ClrBPEx(BPHandle = 0x00000002)
+T2F54 000:539.654 - 0.023ms returns 0x00
+T2F54 000:539.662 JLINK_ReadReg(R0)
+T2F54 000:539.668 - 0.009ms returns 0x00000001
+T2F54 000:539.691 JLINK_HasError()
+T2F54 000:539.719 JLINK_WriteReg(R0, 0x00000000)
+T2F54 000:539.739 - 0.023ms returns 0
+T2F54 000:539.827 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:539.869 - 0.045ms returns 0
+T2F54 000:539.876 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:539.882 - 0.008ms returns 0
+T2F54 000:539.890 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:539.910 - 0.023ms returns 0
+T2F54 000:539.918 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:539.924 - 0.009ms returns 0
+T2F54 000:539.932 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:539.951 - 0.022ms returns 0
+T2F54 000:539.959 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:539.965 - 0.008ms returns 0
+T2F54 000:539.972 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:539.978 - 0.008ms returns 0
+T2F54 000:539.986 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:539.992 - 0.009ms returns 0
+T2F54 000:539.999 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:540.005 - 0.008ms returns 0
+T2F54 000:540.013 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:540.019 - 0.009ms returns 0
+T2F54 000:540.026 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:540.032 - 0.008ms returns 0
+T2F54 000:540.040 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:540.046 - 0.008ms returns 0
+T2F54 000:540.053 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:540.060 - 0.009ms returns 0
+T2F54 000:540.067 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:540.073 - 0.008ms returns 0
+T2F54 000:540.081 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:540.087 - 0.009ms returns 0
+T2F54 000:540.094 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:540.100 - 0.008ms returns 0
+T2F54 000:540.108 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:540.114 - 0.008ms returns 0
+T2F54 000:540.121 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:540.127 - 0.008ms returns 0
+T2F54 000:540.135 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:540.141 - 0.008ms returns 0
+T2F54 000:540.148 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:540.155 - 0.009ms returns 0x00000003
+T2F54 000:540.163 JLINK_Go()
+T2F54 000:540.175   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:543.667 - 3.514ms
+T2F54 000:543.686 JLINK_IsHalted()
+T2F54 000:544.068 - 0.388ms returns FALSE
+T2F54 000:544.082 JLINK_HasError()
+T2F54 000:565.515 JLINK_IsHalted()
+T2F54 000:568.616   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:569.017 - 3.538ms returns TRUE
+T2F54 000:569.065 JLINK_ReadReg(R15 (PC))
+T2F54 000:569.076 - 0.014ms returns 0x20000000
+T2F54 000:569.085 JLINK_ClrBPEx(BPHandle = 0x00000003)
+T2F54 000:569.093 - 0.010ms returns 0x00
+T2F54 000:569.102 JLINK_ReadReg(R0)
+T2F54 000:569.129 - 0.030ms returns 0x00000000
+T2F54 000:571.200 JLINK_HasError()
+T2F54 000:571.224 JLINK_WriteReg(R0, 0x00001000)
+T2F54 000:571.236 - 0.014ms returns 0
+T2F54 000:571.245 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:571.251 - 0.009ms returns 0
+T2F54 000:571.259 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:571.265 - 0.009ms returns 0
+T2F54 000:571.273 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:571.279 - 0.009ms returns 0
+T2F54 000:571.287 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:571.293 - 0.009ms returns 0
+T2F54 000:571.301 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:571.307 - 0.009ms returns 0
+T2F54 000:571.315 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:571.321 - 0.009ms returns 0
+T2F54 000:571.329 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:571.335 - 0.009ms returns 0
+T2F54 000:571.343 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:571.349 - 0.009ms returns 0
+T2F54 000:571.356 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:571.363 - 0.009ms returns 0
+T2F54 000:571.370 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:571.377 - 0.010ms returns 0
+T2F54 000:571.385 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:571.391 - 0.009ms returns 0
+T2F54 000:571.399 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:571.405 - 0.009ms returns 0
+T2F54 000:571.413 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:571.420 - 0.010ms returns 0
+T2F54 000:571.428 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:571.434 - 0.009ms returns 0
+T2F54 000:571.442 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:571.448 - 0.009ms returns 0
+T2F54 000:571.456 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:571.462 - 0.009ms returns 0
+T2F54 000:571.470 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:571.479 - 0.014ms returns 0
+T2F54 000:571.489 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:571.496 - 0.009ms returns 0
+T2F54 000:571.503 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:571.510 - 0.009ms returns 0
+T2F54 000:571.518 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:571.539 - 0.024ms returns 0x00000004
+T2F54 000:571.566 JLINK_Go()
+T2F54 000:571.594   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:575.095 - 3.537ms
+T2F54 000:575.111 JLINK_IsHalted()
+T2F54 000:578.251   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:578.667 - 3.564ms returns TRUE
+T2F54 000:578.683 JLINK_ReadReg(R15 (PC))
+T2F54 000:578.691 - 0.011ms returns 0x20000000
+T2F54 000:578.700 JLINK_ClrBPEx(BPHandle = 0x00000004)
+T2F54 000:578.706 - 0.009ms returns 0x00
+T2F54 000:578.714 JLINK_ReadReg(R0)
+T2F54 000:578.721 - 0.009ms returns 0x00000001
+T2F54 000:578.729 JLINK_HasError()
+T2F54 000:578.738 JLINK_WriteReg(R0, 0x00001000)
+T2F54 000:578.744 - 0.009ms returns 0
+T2F54 000:578.753 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:578.759 - 0.009ms returns 0
+T2F54 000:578.767 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:578.773 - 0.009ms returns 0
+T2F54 000:578.781 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:578.787 - 0.009ms returns 0
+T2F54 000:578.795 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:578.801 - 0.009ms returns 0
+T2F54 000:578.809 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:578.815 - 0.009ms returns 0
+T2F54 000:578.823 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:578.829 - 0.009ms returns 0
+T2F54 000:578.837 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:578.843 - 0.009ms returns 0
+T2F54 000:578.851 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:578.857 - 0.009ms returns 0
+T2F54 000:578.865 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:578.871 - 0.009ms returns 0
+T2F54 000:578.879 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:578.885 - 0.009ms returns 0
+T2F54 000:578.893 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:578.899 - 0.009ms returns 0
+T2F54 000:578.907 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:578.913 - 0.009ms returns 0
+T2F54 000:578.921 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:578.927 - 0.009ms returns 0
+T2F54 000:578.935 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:578.942 - 0.009ms returns 0
+T2F54 000:578.949 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:578.955 - 0.009ms returns 0
+T2F54 000:578.963 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:578.969 - 0.009ms returns 0
+T2F54 000:578.977 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:578.983 - 0.009ms returns 0
+T2F54 000:578.991 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:578.997 - 0.009ms returns 0
+T2F54 000:579.005 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:579.011 - 0.009ms returns 0
+T2F54 000:579.019 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:579.026 - 0.009ms returns 0x00000005
+T2F54 000:579.034 JLINK_Go()
+T2F54 000:579.047   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:582.619 - 3.608ms
+T2F54 000:582.687 JLINK_IsHalted()
+T2F54 000:583.063 - 0.383ms returns FALSE
+T2F54 000:583.084 JLINK_HasError()
+T2F54 000:584.488 JLINK_IsHalted()
+T2F54 000:584.980 - 0.501ms returns FALSE
+T2F54 000:585.017 JLINK_HasError()
+T2F54 000:586.486 JLINK_IsHalted()
+T2F54 000:586.795 - 0.317ms returns FALSE
+T2F54 000:586.811 JLINK_HasError()
+T2F54 000:588.571 JLINK_IsHalted()
+T2F54 000:588.971 - 0.407ms returns FALSE
+T2F54 000:588.985 JLINK_HasError()
+T2F54 000:590.495 JLINK_IsHalted()
+T2F54 000:590.862 - 0.373ms returns FALSE
+T2F54 000:590.876 JLINK_HasError()
+T2F54 000:592.687 JLINK_IsHalted()
+T2F54 000:593.209 - 0.529ms returns FALSE
+T2F54 000:593.223 JLINK_HasError()
+T2F54 000:594.677 JLINK_IsHalted()
+T2F54 000:595.088 - 0.417ms returns FALSE
+T2F54 000:595.101 JLINK_HasError()
+T2F54 000:596.603 JLINK_IsHalted()
+T2F54 000:597.058 - 0.463ms returns FALSE
+T2F54 000:597.075 JLINK_HasError()
+T2F54 000:598.614 JLINK_IsHalted()
+T2F54 000:599.084 - 0.487ms returns FALSE
+T2F54 000:599.114 JLINK_HasError()
+T2F54 000:600.352 JLINK_IsHalted()
+T2F54 000:600.769 - 0.427ms returns FALSE
+T2F54 000:600.791 JLINK_HasError()
+T2F54 000:602.026 JLINK_IsHalted()
+T2F54 000:602.512 - 0.492ms returns FALSE
+T2F54 000:602.526 JLINK_HasError()
+T2F54 000:604.110 JLINK_IsHalted()
+T2F54 000:607.286   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:607.717 - 3.614ms returns TRUE
+T2F54 000:607.731 JLINK_ReadReg(R15 (PC))
+T2F54 000:607.740 - 0.011ms returns 0x20000000
+T2F54 000:607.748 JLINK_ClrBPEx(BPHandle = 0x00000005)
+T2F54 000:607.754 - 0.009ms returns 0x00
+T2F54 000:607.762 JLINK_ReadReg(R0)
+T2F54 000:607.768 - 0.009ms returns 0x00000000
+T2F54 000:608.358 JLINK_HasError()
+T2F54 000:608.370 JLINK_WriteReg(R0, 0x00002000)
+T2F54 000:608.378 - 0.011ms returns 0
+T2F54 000:608.386 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:608.392 - 0.009ms returns 0
+T2F54 000:608.400 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:608.405 - 0.008ms returns 0
+T2F54 000:608.413 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:608.419 - 0.008ms returns 0
+T2F54 000:608.426 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:608.432 - 0.008ms returns 0
+T2F54 000:608.439 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:608.445 - 0.008ms returns 0
+T2F54 000:608.452 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:608.457 - 0.008ms returns 0
+T2F54 000:608.465 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:608.470 - 0.008ms returns 0
+T2F54 000:608.478 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:608.484 - 0.008ms returns 0
+T2F54 000:608.491 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:608.497 - 0.008ms returns 0
+T2F54 000:608.504 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:608.510 - 0.008ms returns 0
+T2F54 000:608.517 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:608.523 - 0.008ms returns 0
+T2F54 000:608.530 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:608.536 - 0.008ms returns 0
+T2F54 000:608.543 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:608.549 - 0.009ms returns 0
+T2F54 000:608.556 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:608.562 - 0.008ms returns 0
+T2F54 000:608.569 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:608.575 - 0.008ms returns 0
+T2F54 000:608.583 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:608.588 - 0.008ms returns 0
+T2F54 000:608.596 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:608.601 - 0.008ms returns 0
+T2F54 000:608.609 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:608.614 - 0.008ms returns 0
+T2F54 000:608.622 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:608.627 - 0.008ms returns 0
+T2F54 000:608.635 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:608.642 - 0.010ms returns 0x00000006
+T2F54 000:608.650 JLINK_Go()
+T2F54 000:608.663   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:612.178 - 3.537ms
+T2F54 000:612.195 JLINK_IsHalted()
+T2F54 000:615.127   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:615.579 - 3.395ms returns TRUE
+T2F54 000:615.637 JLINK_ReadReg(R15 (PC))
+T2F54 000:615.648 - 0.013ms returns 0x20000000
+T2F54 000:615.656 JLINK_ClrBPEx(BPHandle = 0x00000006)
+T2F54 000:615.662 - 0.009ms returns 0x00
+T2F54 000:615.671 JLINK_ReadReg(R0)
+T2F54 000:615.677 - 0.009ms returns 0x00000001
+T2F54 000:615.686 JLINK_HasError()
+T2F54 000:615.695 JLINK_WriteReg(R0, 0x00002000)
+T2F54 000:615.704 - 0.012ms returns 0
+T2F54 000:615.712 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:615.737 - 0.027ms returns 0
+T2F54 000:615.765 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:615.772 - 0.009ms returns 0
+T2F54 000:615.779 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:615.786 - 0.009ms returns 0
+T2F54 000:615.794 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:615.800 - 0.009ms returns 0
+T2F54 000:615.808 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:615.817 - 0.013ms returns 0
+T2F54 000:615.830 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:615.850 - 0.025ms returns 0
+T2F54 000:615.864 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:615.879 - 0.018ms returns 0
+T2F54 000:615.888 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:615.895 - 0.009ms returns 0
+T2F54 000:615.903 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:615.909 - 0.009ms returns 0
+T2F54 000:615.918 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:615.924 - 0.009ms returns 0
+T2F54 000:615.932 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:615.954 - 0.027ms returns 0
+T2F54 000:615.997 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:616.006 - 0.012ms returns 0
+T2F54 000:616.015 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:616.039 - 0.027ms returns 0
+T2F54 000:616.063 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:616.070 - 0.010ms returns 0
+T2F54 000:616.078 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:616.103 - 0.028ms returns 0
+T2F54 000:616.112 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:616.119 - 0.031ms returns 0
+T2F54 000:616.149 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:616.156 - 0.010ms returns 0
+T2F54 000:616.164 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:616.171 - 0.010ms returns 0
+T2F54 000:616.180 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:616.186 - 0.009ms returns 0
+T2F54 000:616.196 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:616.208 - 0.015ms returns 0x00000007
+T2F54 000:616.218 JLINK_Go()
+T2F54 000:616.245   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:619.783 - 3.573ms
+T2F54 000:619.799 JLINK_IsHalted()
+T2F54 000:620.202 - 0.409ms returns FALSE
+T2F54 000:620.216 JLINK_HasError()
+T2F54 000:621.715 JLINK_IsHalted()
+T2F54 000:622.223 - 0.514ms returns FALSE
+T2F54 000:622.237 JLINK_HasError()
+T2F54 000:624.290 JLINK_IsHalted()
+T2F54 000:624.766 - 0.483ms returns FALSE
+T2F54 000:624.780 JLINK_HasError()
+T2F54 000:626.283 JLINK_IsHalted()
+T2F54 000:626.739 - 0.462ms returns FALSE
+T2F54 000:626.753 JLINK_HasError()
+T2F54 000:628.811 JLINK_IsHalted()
+T2F54 000:629.224 - 0.422ms returns FALSE
+T2F54 000:629.241 JLINK_HasError()
+T2F54 000:630.742 JLINK_IsHalted()
+T2F54 000:631.105 - 0.373ms returns FALSE
+T2F54 000:631.125 JLINK_HasError()
+T2F54 000:633.760 JLINK_IsHalted()
+T2F54 000:634.174 - 0.423ms returns FALSE
+T2F54 000:634.216 JLINK_HasError()
+T2F54 000:635.833 JLINK_IsHalted()
+T2F54 000:636.318 - 0.491ms returns FALSE
+T2F54 000:636.332 JLINK_HasError()
+T2F54 000:637.815 JLINK_IsHalted()
+T2F54 000:638.316 - 0.507ms returns FALSE
+T2F54 000:638.330 JLINK_HasError()
+T2F54 000:639.817 JLINK_IsHalted()
+T2F54 000:640.346 - 0.537ms returns FALSE
+T2F54 000:640.362 JLINK_HasError()
+T2F54 000:641.806 JLINK_IsHalted()
+T2F54 000:645.107   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:645.479 - 3.682ms returns TRUE
+T2F54 000:645.497 JLINK_ReadReg(R15 (PC))
+T2F54 000:645.507 - 0.013ms returns 0x20000000
+T2F54 000:645.516 JLINK_ClrBPEx(BPHandle = 0x00000007)
+T2F54 000:645.523 - 0.009ms returns 0x00
+T2F54 000:645.531 JLINK_ReadReg(R0)
+T2F54 000:645.537 - 0.009ms returns 0x00000000
+T2F54 000:646.127 JLINK_HasError()
+T2F54 000:646.144 JLINK_WriteReg(R0, 0x00003000)
+T2F54 000:646.154 - 0.013ms returns 0
+T2F54 000:646.162 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:646.168 - 0.009ms returns 0
+T2F54 000:646.176 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:646.182 - 0.009ms returns 0
+T2F54 000:646.190 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:646.196 - 0.009ms returns 0
+T2F54 000:646.204 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:646.210 - 0.009ms returns 0
+T2F54 000:646.218 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:646.224 - 0.009ms returns 0
+T2F54 000:646.231 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:646.237 - 0.009ms returns 0
+T2F54 000:646.245 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:646.251 - 0.009ms returns 0
+T2F54 000:646.259 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:646.265 - 0.009ms returns 0
+T2F54 000:646.273 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:646.279 - 0.009ms returns 0
+T2F54 000:646.287 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:646.293 - 0.009ms returns 0
+T2F54 000:646.301 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:646.307 - 0.009ms returns 0
+T2F54 000:646.314 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:646.321 - 0.009ms returns 0
+T2F54 000:646.329 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:646.336 - 0.010ms returns 0
+T2F54 000:646.344 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:646.350 - 0.009ms returns 0
+T2F54 000:646.358 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:646.364 - 0.009ms returns 0
+T2F54 000:646.372 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:646.378 - 0.009ms returns 0
+T2F54 000:646.386 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:646.460 - 0.077ms returns 0
+T2F54 000:646.468 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:646.475 - 0.009ms returns 0
+T2F54 000:646.486 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:646.494 - 0.011ms returns 0
+T2F54 000:646.502 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:646.510 - 0.011ms returns 0x00000008
+T2F54 000:646.519 JLINK_Go()
+T2F54 000:646.535   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:650.458 - 3.953ms
+T2F54 000:650.480 JLINK_IsHalted()
+T2F54 000:653.750   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:654.117 - 3.644ms returns TRUE
+T2F54 000:654.135 JLINK_ReadReg(R15 (PC))
+T2F54 000:654.144 - 0.012ms returns 0x20000000
+T2F54 000:654.153 JLINK_ClrBPEx(BPHandle = 0x00000008)
+T2F54 000:654.159 - 0.009ms returns 0x00
+T2F54 000:654.167 JLINK_ReadReg(R0)
+T2F54 000:654.174 - 0.009ms returns 0x00000001
+T2F54 000:654.183 JLINK_HasError()
+T2F54 000:654.191 JLINK_WriteReg(R0, 0x00003000)
+T2F54 000:654.198 - 0.010ms returns 0
+T2F54 000:654.206 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:654.212 - 0.009ms returns 0
+T2F54 000:654.220 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:654.226 - 0.009ms returns 0
+T2F54 000:654.233 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:654.239 - 0.009ms returns 0
+T2F54 000:654.247 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:654.253 - 0.009ms returns 0
+T2F54 000:654.261 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:654.267 - 0.009ms returns 0
+T2F54 000:654.275 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:654.281 - 0.009ms returns 0
+T2F54 000:654.288 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:654.295 - 0.009ms returns 0
+T2F54 000:654.302 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:654.308 - 0.009ms returns 0
+T2F54 000:654.316 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:654.322 - 0.009ms returns 0
+T2F54 000:654.330 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:654.336 - 0.009ms returns 0
+T2F54 000:654.343 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:654.350 - 0.009ms returns 0
+T2F54 000:654.357 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:654.363 - 0.009ms returns 0
+T2F54 000:654.371 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:654.377 - 0.009ms returns 0
+T2F54 000:654.385 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:654.391 - 0.009ms returns 0
+T2F54 000:654.399 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:654.405 - 0.009ms returns 0
+T2F54 000:654.413 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:654.419 - 0.009ms returns 0
+T2F54 000:654.427 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:654.433 - 0.009ms returns 0
+T2F54 000:654.440 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:654.447 - 0.009ms returns 0
+T2F54 000:654.454 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:654.460 - 0.009ms returns 0
+T2F54 000:654.468 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:654.475 - 0.009ms returns 0x00000009
+T2F54 000:654.483 JLINK_Go()
+T2F54 000:654.494   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:658.516 - 4.040ms
+T2F54 000:658.531 JLINK_IsHalted()
+T2F54 000:659.274 - 0.757ms returns FALSE
+T2F54 000:659.308 JLINK_HasError()
+T2F54 000:665.577 JLINK_IsHalted()
+T2F54 000:666.014 - 0.444ms returns FALSE
+T2F54 000:666.043 JLINK_HasError()
+T2F54 000:667.815 JLINK_IsHalted()
+T2F54 000:668.312 - 0.504ms returns FALSE
+T2F54 000:668.327 JLINK_HasError()
+T2F54 000:670.709 JLINK_IsHalted()
+T2F54 000:671.454 - 0.751ms returns FALSE
+T2F54 000:671.468 JLINK_HasError()
+T2F54 000:673.420 JLINK_IsHalted()
+T2F54 000:674.123 - 0.711ms returns FALSE
+T2F54 000:674.143 JLINK_HasError()
+T2F54 000:675.492 JLINK_IsHalted()
+T2F54 000:675.993 - 0.515ms returns FALSE
+T2F54 000:676.019 JLINK_HasError()
+T2F54 000:677.215 JLINK_IsHalted()
+T2F54 000:677.681 - 0.474ms returns FALSE
+T2F54 000:677.698 JLINK_HasError()
+T2F54 000:679.205 JLINK_IsHalted()
+T2F54 000:682.507   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:682.893 - 3.708ms returns TRUE
+T2F54 000:682.922 JLINK_ReadReg(R15 (PC))
+T2F54 000:682.931 - 0.011ms returns 0x20000000
+T2F54 000:682.939 JLINK_ClrBPEx(BPHandle = 0x00000009)
+T2F54 000:682.945 - 0.009ms returns 0x00
+T2F54 000:682.959 JLINK_ReadReg(R0)
+T2F54 000:682.967 - 0.010ms returns 0x00000000
+T2F54 000:683.506 JLINK_HasError()
+T2F54 000:683.518 JLINK_WriteReg(R0, 0x00004000)
+T2F54 000:683.526 - 0.010ms returns 0
+T2F54 000:683.534 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:683.540 - 0.009ms returns 0
+T2F54 000:683.548 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:683.554 - 0.008ms returns 0
+T2F54 000:683.561 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:683.567 - 0.008ms returns 0
+T2F54 000:683.574 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:683.580 - 0.008ms returns 0
+T2F54 000:683.588 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:683.594 - 0.008ms returns 0
+T2F54 000:683.601 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:683.607 - 0.008ms returns 0
+T2F54 000:683.614 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:683.620 - 0.008ms returns 0
+T2F54 000:683.628 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:683.634 - 0.008ms returns 0
+T2F54 000:683.641 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:683.647 - 0.008ms returns 0
+T2F54 000:683.654 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:683.660 - 0.008ms returns 0
+T2F54 000:683.668 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:683.674 - 0.008ms returns 0
+T2F54 000:683.681 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:683.687 - 0.008ms returns 0
+T2F54 000:683.695 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:683.701 - 0.009ms returns 0
+T2F54 000:683.709 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:683.714 - 0.008ms returns 0
+T2F54 000:683.722 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:683.728 - 0.008ms returns 0
+T2F54 000:683.735 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:683.741 - 0.008ms returns 0
+T2F54 000:683.749 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:683.755 - 0.008ms returns 0
+T2F54 000:683.762 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:683.768 - 0.008ms returns 0
+T2F54 000:683.776 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:683.781 - 0.008ms returns 0
+T2F54 000:683.789 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:683.796 - 0.009ms returns 0x0000000A
+T2F54 000:683.804 JLINK_Go()
+T2F54 000:683.819   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:687.256 - 3.460ms
+T2F54 000:687.294 JLINK_IsHalted()
+T2F54 000:690.606   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:691.103 - 3.819ms returns TRUE
+T2F54 000:691.128 JLINK_ReadReg(R15 (PC))
+T2F54 000:691.138 - 0.013ms returns 0x20000000
+T2F54 000:691.147 JLINK_ClrBPEx(BPHandle = 0x0000000A)
+T2F54 000:691.153 - 0.009ms returns 0x00
+T2F54 000:691.161 JLINK_ReadReg(R0)
+T2F54 000:691.170 - 0.012ms returns 0x00000001
+T2F54 000:691.179 JLINK_HasError()
+T2F54 000:691.278 JLINK_WriteReg(R0, 0x00004000)
+T2F54 000:691.299 - 0.024ms returns 0
+T2F54 000:691.308 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:691.315 - 0.009ms returns 0
+T2F54 000:691.323 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:691.329 - 0.009ms returns 0
+T2F54 000:691.336 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:691.342 - 0.008ms returns 0
+T2F54 000:691.350 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:691.356 - 0.009ms returns 0
+T2F54 000:691.363 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:691.369 - 0.009ms returns 0
+T2F54 000:691.377 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:691.383 - 0.008ms returns 0
+T2F54 000:691.390 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:691.396 - 0.008ms returns 0
+T2F54 000:691.404 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:691.410 - 0.008ms returns 0
+T2F54 000:691.417 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:691.423 - 0.008ms returns 0
+T2F54 000:691.430 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:691.436 - 0.008ms returns 0
+T2F54 000:691.444 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:691.450 - 0.008ms returns 0
+T2F54 000:691.457 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:691.463 - 0.008ms returns 0
+T2F54 000:691.471 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:691.477 - 0.009ms returns 0
+T2F54 000:691.485 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:691.491 - 0.008ms returns 0
+T2F54 000:691.498 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:691.504 - 0.009ms returns 0
+T2F54 000:691.512 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:691.527 - 0.023ms returns 0
+T2F54 000:691.563 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:691.603 - 0.047ms returns 0
+T2F54 000:691.620 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:691.630 - 0.013ms returns 0
+T2F54 000:691.642 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:691.653 - 0.021ms returns 0
+T2F54 000:691.673 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:691.686 - 0.017ms returns 0x0000000B
+T2F54 000:691.698 JLINK_Go()
+T2F54 000:691.725   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:695.221 - 3.540ms
+T2F54 000:695.250 JLINK_IsHalted()
+T2F54 000:695.625 - 0.383ms returns FALSE
+T2F54 000:695.642 JLINK_HasError()
+T2F54 000:697.525 JLINK_IsHalted()
+T2F54 000:697.976 - 0.465ms returns FALSE
+T2F54 000:698.000 JLINK_HasError()
+T2F54 000:699.706 JLINK_IsHalted()
+T2F54 000:700.166 - 0.467ms returns FALSE
+T2F54 000:700.182 JLINK_HasError()
+T2F54 000:701.733 JLINK_IsHalted()
+T2F54 000:702.306 - 0.581ms returns FALSE
+T2F54 000:702.323 JLINK_HasError()
+T2F54 000:703.760 JLINK_IsHalted()
+T2F54 000:704.367 - 0.614ms returns FALSE
+T2F54 000:704.382 JLINK_HasError()
+T2F54 000:706.510 JLINK_IsHalted()
+T2F54 000:707.192 - 0.689ms returns FALSE
+T2F54 000:707.208 JLINK_HasError()
+T2F54 000:709.305 JLINK_IsHalted()
+T2F54 000:709.779 - 0.482ms returns FALSE
+T2F54 000:709.808 JLINK_HasError()
+T2F54 000:711.891 JLINK_IsHalted()
+T2F54 000:712.236 - 0.356ms returns FALSE
+T2F54 000:712.255 JLINK_HasError()
+T2F54 000:713.893 JLINK_IsHalted()
+T2F54 000:714.334 - 0.449ms returns FALSE
+T2F54 000:714.351 JLINK_HasError()
+T2F54 000:716.331 JLINK_IsHalted()
+T2F54 000:719.640   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:720.448 - 4.135ms returns TRUE
+T2F54 000:720.483 JLINK_ReadReg(R15 (PC))
+T2F54 000:720.495 - 0.015ms returns 0x20000000
+T2F54 000:720.503 JLINK_ClrBPEx(BPHandle = 0x0000000B)
+T2F54 000:720.510 - 0.009ms returns 0x00
+T2F54 000:720.518 JLINK_ReadReg(R0)
+T2F54 000:720.525 - 0.009ms returns 0x00000000
+T2F54 000:721.264 JLINK_HasError()
+T2F54 000:721.286 JLINK_WriteReg(R0, 0x00005000)
+T2F54 000:721.297 - 0.014ms returns 0
+T2F54 000:721.306 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:721.312 - 0.009ms returns 0
+T2F54 000:721.319 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:721.325 - 0.009ms returns 0
+T2F54 000:721.333 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:721.339 - 0.008ms returns 0
+T2F54 000:721.346 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:721.352 - 0.008ms returns 0
+T2F54 000:721.360 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:721.366 - 0.008ms returns 0
+T2F54 000:721.373 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:721.379 - 0.008ms returns 0
+T2F54 000:721.386 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:721.392 - 0.008ms returns 0
+T2F54 000:721.400 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:721.406 - 0.008ms returns 0
+T2F54 000:721.413 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:721.419 - 0.008ms returns 0
+T2F54 000:721.426 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:721.432 - 0.008ms returns 0
+T2F54 000:721.440 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:721.446 - 0.008ms returns 0
+T2F54 000:721.453 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:721.460 - 0.009ms returns 0
+T2F54 000:721.467 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:721.474 - 0.009ms returns 0
+T2F54 000:721.482 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:721.488 - 0.008ms returns 0
+T2F54 000:721.495 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:721.501 - 0.009ms returns 0
+T2F54 000:721.509 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:721.515 - 0.008ms returns 0
+T2F54 000:721.522 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:721.528 - 0.008ms returns 0
+T2F54 000:721.536 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:721.541 - 0.008ms returns 0
+T2F54 000:721.549 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:721.555 - 0.008ms returns 0
+T2F54 000:721.563 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:721.570 - 0.010ms returns 0x0000000C
+T2F54 000:721.578 JLINK_Go()
+T2F54 000:721.592   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:724.959 - 3.396ms
+T2F54 000:724.984 JLINK_IsHalted()
+T2F54 000:727.971   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:728.307 - 3.331ms returns TRUE
+T2F54 000:728.324 JLINK_ReadReg(R15 (PC))
+T2F54 000:728.333 - 0.012ms returns 0x20000000
+T2F54 000:728.342 JLINK_ClrBPEx(BPHandle = 0x0000000C)
+T2F54 000:728.349 - 0.010ms returns 0x00
+T2F54 000:728.371 JLINK_ReadReg(R0)
+T2F54 000:728.377 - 0.009ms returns 0x00000001
+T2F54 000:728.386 JLINK_HasError()
+T2F54 000:728.395 JLINK_WriteReg(R0, 0x00005000)
+T2F54 000:728.402 - 0.009ms returns 0
+T2F54 000:728.410 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:728.416 - 0.009ms returns 0
+T2F54 000:728.423 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:728.429 - 0.008ms returns 0
+T2F54 000:728.437 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:728.443 - 0.008ms returns 0
+T2F54 000:728.450 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:728.456 - 0.008ms returns 0
+T2F54 000:728.463 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:728.469 - 0.008ms returns 0
+T2F54 000:728.477 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:728.483 - 0.008ms returns 0
+T2F54 000:728.490 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:728.496 - 0.008ms returns 0
+T2F54 000:728.504 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:728.510 - 0.009ms returns 0
+T2F54 000:728.517 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:728.523 - 0.008ms returns 0
+T2F54 000:728.530 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:728.536 - 0.008ms returns 0
+T2F54 000:728.544 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:728.550 - 0.008ms returns 0
+T2F54 000:728.557 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:728.563 - 0.008ms returns 0
+T2F54 000:728.571 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:728.577 - 0.009ms returns 0
+T2F54 000:728.585 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:728.590 - 0.008ms returns 0
+T2F54 000:728.598 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:728.604 - 0.009ms returns 0
+T2F54 000:728.612 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:728.618 - 0.008ms returns 0
+T2F54 000:728.625 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:728.631 - 0.009ms returns 0
+T2F54 000:728.639 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:728.645 - 0.008ms returns 0
+T2F54 000:728.653 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:728.659 - 0.008ms returns 0
+T2F54 000:728.667 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:728.673 - 0.009ms returns 0x0000000D
+T2F54 000:728.681 JLINK_Go()
+T2F54 000:728.693   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:731.835 - 3.175ms
+T2F54 000:731.865 JLINK_IsHalted()
+T2F54 000:732.174 - 0.316ms returns FALSE
+T2F54 000:732.191 JLINK_HasError()
+T2F54 000:733.983 JLINK_IsHalted()
+T2F54 000:734.314 - 0.338ms returns FALSE
+T2F54 000:734.329 JLINK_HasError()
+T2F54 000:736.249 JLINK_IsHalted()
+T2F54 000:736.634 - 0.392ms returns FALSE
+T2F54 000:736.649 JLINK_HasError()
+T2F54 000:737.781 JLINK_IsHalted()
+T2F54 000:738.604 - 0.880ms returns FALSE
+T2F54 000:738.712 JLINK_HasError()
+T2F54 000:740.711 JLINK_IsHalted()
+T2F54 000:741.161 - 0.472ms returns FALSE
+T2F54 000:741.210 JLINK_HasError()
+T2F54 000:743.743 JLINK_IsHalted()
+T2F54 000:744.217 - 0.482ms returns FALSE
+T2F54 000:744.233 JLINK_HasError()
+T2F54 000:745.706 JLINK_IsHalted()
+T2F54 000:746.137 - 0.439ms returns FALSE
+T2F54 000:746.158 JLINK_HasError()
+T2F54 000:747.686 JLINK_IsHalted()
+T2F54 000:748.107 - 0.429ms returns FALSE
+T2F54 000:748.124 JLINK_HasError()
+T2F54 000:749.663 JLINK_IsHalted()
+T2F54 000:750.445 - 0.799ms returns FALSE
+T2F54 000:750.474 JLINK_HasError()
+T2F54 000:752.013 JLINK_IsHalted()
+T2F54 000:755.444   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:755.958 - 3.956ms returns TRUE
+T2F54 000:755.998 JLINK_ReadReg(R15 (PC))
+T2F54 000:756.009 - 0.014ms returns 0x20000000
+T2F54 000:756.017 JLINK_ClrBPEx(BPHandle = 0x0000000D)
+T2F54 000:756.024 - 0.010ms returns 0x00
+T2F54 000:756.032 JLINK_ReadReg(R0)
+T2F54 000:756.039 - 0.009ms returns 0x00000000
+T2F54 000:757.802 JLINK_HasError()
+T2F54 000:757.817 JLINK_WriteReg(R0, 0x00006000)
+T2F54 000:757.839 - 0.025ms returns 0
+T2F54 000:757.861 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:757.867 - 0.022ms returns 0
+T2F54 000:757.888 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:757.899 - 0.013ms returns 0
+T2F54 000:757.920 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:757.926 - 0.008ms returns 0
+T2F54 000:757.934 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:757.953 - 0.022ms returns 0
+T2F54 000:757.961 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:757.980 - 0.022ms returns 0
+T2F54 000:758.001 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:758.006 - 0.008ms returns 0
+T2F54 000:758.014 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:758.033 - 0.022ms returns 0
+T2F54 000:758.040 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:758.046 - 0.008ms returns 0
+T2F54 000:758.054 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:758.073 - 0.022ms returns 0
+T2F54 000:758.094 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:758.100 - 0.009ms returns 0
+T2F54 000:758.107 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:758.113 - 0.008ms returns 0
+T2F54 000:758.120 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:758.126 - 0.008ms returns 0
+T2F54 000:758.134 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:758.140 - 0.009ms returns 0
+T2F54 000:758.148 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:758.154 - 0.008ms returns 0
+T2F54 000:758.161 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:758.167 - 0.008ms returns 0
+T2F54 000:758.174 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:758.180 - 0.008ms returns 0
+T2F54 000:758.188 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:758.194 - 0.008ms returns 0
+T2F54 000:758.201 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:758.207 - 0.008ms returns 0
+T2F54 000:758.214 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:758.220 - 0.008ms returns 0
+T2F54 000:758.228 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:758.239 - 0.013ms returns 0x0000000E
+T2F54 000:758.247 JLINK_Go()
+T2F54 000:758.260   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:761.555 - 3.318ms
+T2F54 000:761.573 JLINK_IsHalted()
+T2F54 000:764.550   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:764.969 - 3.404ms returns TRUE
+T2F54 000:764.987 JLINK_ReadReg(R15 (PC))
+T2F54 000:764.997 - 0.013ms returns 0x20000000
+T2F54 000:765.005 JLINK_ClrBPEx(BPHandle = 0x0000000E)
+T2F54 000:765.012 - 0.009ms returns 0x00
+T2F54 000:765.020 JLINK_ReadReg(R0)
+T2F54 000:765.026 - 0.009ms returns 0x00000001
+T2F54 000:765.035 JLINK_HasError()
+T2F54 000:765.043 JLINK_WriteReg(R0, 0x00006000)
+T2F54 000:765.050 - 0.009ms returns 0
+T2F54 000:765.058 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:765.064 - 0.009ms returns 0
+T2F54 000:765.072 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:765.078 - 0.009ms returns 0
+T2F54 000:765.086 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:765.092 - 0.009ms returns 0
+T2F54 000:765.099 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:765.106 - 0.009ms returns 0
+T2F54 000:765.113 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:765.119 - 0.009ms returns 0
+T2F54 000:765.127 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:765.133 - 0.009ms returns 0
+T2F54 000:765.141 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:765.147 - 0.009ms returns 0
+T2F54 000:765.154 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:765.161 - 0.009ms returns 0
+T2F54 000:765.169 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:765.175 - 0.009ms returns 0
+T2F54 000:765.183 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:765.189 - 0.009ms returns 0
+T2F54 000:765.196 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:765.202 - 0.009ms returns 0
+T2F54 000:765.210 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:765.216 - 0.009ms returns 0
+T2F54 000:765.224 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:765.230 - 0.009ms returns 0
+T2F54 000:765.238 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:765.244 - 0.009ms returns 0
+T2F54 000:765.251 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:765.258 - 0.009ms returns 0
+T2F54 000:765.265 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:765.271 - 0.009ms returns 0
+T2F54 000:765.279 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:765.285 - 0.009ms returns 0
+T2F54 000:765.293 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:765.299 - 0.009ms returns 0
+T2F54 000:765.307 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:765.313 - 0.009ms returns 0
+T2F54 000:765.324 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:765.333 - 0.012ms returns 0x0000000F
+T2F54 000:765.341 JLINK_Go()
+T2F54 000:765.353   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:769.909 - 4.596ms
+T2F54 000:769.959 JLINK_IsHalted()
+T2F54 000:770.450 - 0.521ms returns FALSE
+T2F54 000:770.489 JLINK_HasError()
+T2F54 000:771.795 JLINK_IsHalted()
+T2F54 000:772.261 - 0.475ms returns FALSE
+T2F54 000:772.278 JLINK_HasError()
+T2F54 000:773.786 JLINK_IsHalted()
+T2F54 000:774.202 - 0.423ms returns FALSE
+T2F54 000:774.217 JLINK_HasError()
+T2F54 000:775.995 JLINK_IsHalted()
+T2F54 000:776.433 - 0.446ms returns FALSE
+T2F54 000:776.466 JLINK_HasError()
+T2F54 000:778.442 JLINK_IsHalted()
+T2F54 000:778.889 - 0.455ms returns FALSE
+T2F54 000:778.906 JLINK_HasError()
+T2F54 000:780.324 JLINK_IsHalted()
+T2F54 000:780.781 - 0.478ms returns FALSE
+T2F54 000:780.810 JLINK_HasError()
+T2F54 000:782.374 JLINK_IsHalted()
+T2F54 000:782.834 - 0.468ms returns FALSE
+T2F54 000:782.850 JLINK_HasError()
+T2F54 000:784.112 JLINK_IsHalted()
+T2F54 000:784.604 - 0.504ms returns FALSE
+T2F54 000:784.645 JLINK_HasError()
+T2F54 000:786.674 JLINK_IsHalted()
+T2F54 000:787.028 - 0.363ms returns FALSE
+T2F54 000:787.046 JLINK_HasError()
+T2F54 000:788.695 JLINK_IsHalted()
+T2F54 000:789.173 - 0.485ms returns FALSE
+T2F54 000:789.188 JLINK_HasError()
+T2F54 000:790.695 JLINK_IsHalted()
+T2F54 000:793.889   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:794.282 - 3.608ms returns TRUE
+T2F54 000:794.311 JLINK_ReadReg(R15 (PC))
+T2F54 000:794.320 - 0.012ms returns 0x20000000
+T2F54 000:794.328 JLINK_ClrBPEx(BPHandle = 0x0000000F)
+T2F54 000:794.334 - 0.009ms returns 0x00
+T2F54 000:794.342 JLINK_ReadReg(R0)
+T2F54 000:794.348 - 0.008ms returns 0x00000000
+T2F54 000:795.000 JLINK_HasError()
+T2F54 000:795.017 JLINK_WriteReg(R0, 0x00007000)
+T2F54 000:795.026 - 0.011ms returns 0
+T2F54 000:795.034 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:795.040 - 0.009ms returns 0
+T2F54 000:795.048 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:795.054 - 0.008ms returns 0
+T2F54 000:795.061 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:795.067 - 0.008ms returns 0
+T2F54 000:795.074 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:795.080 - 0.008ms returns 0
+T2F54 000:795.088 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:795.094 - 0.008ms returns 0
+T2F54 000:795.101 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:795.107 - 0.008ms returns 0
+T2F54 000:795.115 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:795.120 - 0.008ms returns 0
+T2F54 000:795.128 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:795.134 - 0.008ms returns 0
+T2F54 000:795.141 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:795.147 - 0.008ms returns 0
+T2F54 000:795.155 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:795.161 - 0.009ms returns 0
+T2F54 000:795.169 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:795.174 - 0.008ms returns 0
+T2F54 000:795.182 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:795.188 - 0.008ms returns 0
+T2F54 000:795.195 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:795.202 - 0.009ms returns 0
+T2F54 000:795.210 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:795.216 - 0.008ms returns 0
+T2F54 000:795.223 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:795.229 - 0.008ms returns 0
+T2F54 000:795.237 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:795.243 - 0.009ms returns 0
+T2F54 000:795.251 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:795.257 - 0.009ms returns 0
+T2F54 000:795.264 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:795.270 - 0.008ms returns 0
+T2F54 000:795.278 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:795.284 - 0.009ms returns 0
+T2F54 000:795.292 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:795.299 - 0.010ms returns 0x00000010
+T2F54 000:795.307 JLINK_Go()
+T2F54 000:795.321   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:799.321 - 4.031ms
+T2F54 000:799.355 JLINK_IsHalted()
+T2F54 000:802.657   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:803.301 - 3.957ms returns TRUE
+T2F54 000:803.331 JLINK_ReadReg(R15 (PC))
+T2F54 000:803.343 - 0.029ms returns 0x20000000
+T2F54 000:803.369 JLINK_ClrBPEx(BPHandle = 0x00000010)
+T2F54 000:803.428 - 0.062ms returns 0x00
+T2F54 000:803.437 JLINK_ReadReg(R0)
+T2F54 000:803.462 - 0.028ms returns 0x00000001
+T2F54 000:803.474 JLINK_HasError()
+T2F54 000:803.667 JLINK_WriteReg(R0, 0x00007000)
+T2F54 000:803.682 - 0.018ms returns 0
+T2F54 000:803.704 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:803.724 - 0.022ms returns 0
+T2F54 000:803.745 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:803.751 - 0.008ms returns 0
+T2F54 000:803.758 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:803.783 - 0.027ms returns 0
+T2F54 000:803.790 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:803.796 - 0.008ms returns 0
+T2F54 000:803.817 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:803.823 - 0.008ms returns 0
+T2F54 000:803.844 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:803.850 - 0.008ms returns 0
+T2F54 000:803.857 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:803.863 - 0.008ms returns 0
+T2F54 000:803.884 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:803.909 - 0.027ms returns 0
+T2F54 000:803.916 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:803.935 - 0.021ms returns 0
+T2F54 000:803.943 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:803.949 - 0.008ms returns 0
+T2F54 000:803.956 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:803.975 - 0.022ms returns 0
+T2F54 000:803.983 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:803.989 - 0.008ms returns 0
+T2F54 000:803.996 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:804.016 - 0.022ms returns 0
+T2F54 000:804.023 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:804.029 - 0.008ms returns 0
+T2F54 000:804.036 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:804.042 - 0.008ms returns 0
+T2F54 000:804.049 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:804.055 - 0.008ms returns 0
+T2F54 000:804.062 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:804.082 - 0.022ms returns 0
+T2F54 000:804.089 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:804.095 - 0.008ms returns 0
+T2F54 000:804.116 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:804.122 - 0.008ms returns 0
+T2F54 000:804.148 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:804.169 - 0.023ms returns 0x00000011
+T2F54 000:804.177 JLINK_Go()
+T2F54 000:804.189   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:807.619 - 3.450ms
+T2F54 000:807.635 JLINK_IsHalted()
+T2F54 000:807.984 - 0.357ms returns FALSE
+T2F54 000:808.000 JLINK_HasError()
+T2F54 000:809.317 JLINK_IsHalted()
+T2F54 000:809.763 - 0.454ms returns FALSE
+T2F54 000:809.779 JLINK_HasError()
+T2F54 000:810.946 JLINK_IsHalted()
+T2F54 000:811.768 - 0.831ms returns FALSE
+T2F54 000:811.785 JLINK_HasError()
+T2F54 000:813.755 JLINK_IsHalted()
+T2F54 000:814.214 - 0.467ms returns FALSE
+T2F54 000:814.231 JLINK_HasError()
+T2F54 000:816.039 JLINK_IsHalted()
+T2F54 000:816.872 - 0.854ms returns FALSE
+T2F54 000:816.922 JLINK_HasError()
+T2F54 000:818.730 JLINK_IsHalted()
+T2F54 000:819.203 - 0.480ms returns FALSE
+T2F54 000:819.219 JLINK_HasError()
+T2F54 000:820.710 JLINK_IsHalted()
+T2F54 000:821.101 - 0.399ms returns FALSE
+T2F54 000:821.118 JLINK_HasError()
+T2F54 000:825.919 JLINK_IsHalted()
+T2F54 000:826.330 - 0.420ms returns FALSE
+T2F54 000:826.346 JLINK_HasError()
+T2F54 000:827.905 JLINK_IsHalted()
+T2F54 000:831.118   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:831.615 - 3.728ms returns TRUE
+T2F54 000:831.649 JLINK_ReadReg(R15 (PC))
+T2F54 000:831.661 - 0.015ms returns 0x20000000
+T2F54 000:831.677 JLINK_ClrBPEx(BPHandle = 0x00000011)
+T2F54 000:831.685 - 0.011ms returns 0x00
+T2F54 000:831.696 JLINK_ReadReg(R0)
+T2F54 000:831.702 - 0.009ms returns 0x00000000
+T2F54 000:832.259 JLINK_HasError()
+T2F54 000:832.276 JLINK_WriteReg(R0, 0x00008000)
+T2F54 000:832.286 - 0.012ms returns 0
+T2F54 000:832.294 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:832.300 - 0.009ms returns 0
+T2F54 000:832.308 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:832.314 - 0.008ms returns 0
+T2F54 000:832.322 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:832.328 - 0.008ms returns 0
+T2F54 000:832.335 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:832.341 - 0.008ms returns 0
+T2F54 000:832.349 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:832.358 - 0.014ms returns 0
+T2F54 000:832.368 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:832.374 - 0.008ms returns 0
+T2F54 000:832.381 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:832.387 - 0.008ms returns 0
+T2F54 000:832.395 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:832.401 - 0.008ms returns 0
+T2F54 000:832.408 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:832.414 - 0.008ms returns 0
+T2F54 000:832.421 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:832.427 - 0.008ms returns 0
+T2F54 000:832.435 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:832.441 - 0.008ms returns 0
+T2F54 000:832.448 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:832.454 - 0.008ms returns 0
+T2F54 000:832.461 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:832.468 - 0.009ms returns 0
+T2F54 000:832.475 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:832.481 - 0.008ms returns 0
+T2F54 000:832.489 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:832.495 - 0.008ms returns 0
+T2F54 000:832.502 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:832.508 - 0.008ms returns 0
+T2F54 000:832.516 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:832.521 - 0.008ms returns 0
+T2F54 000:832.529 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:832.535 - 0.008ms returns 0
+T2F54 000:832.542 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:832.548 - 0.008ms returns 0
+T2F54 000:832.556 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:832.563 - 0.010ms returns 0x00000012
+T2F54 000:832.571 JLINK_Go()
+T2F54 000:832.585   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:835.952 - 3.391ms
+T2F54 000:835.970 JLINK_IsHalted()
+T2F54 000:838.887   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:839.253 - 3.289ms returns TRUE
+T2F54 000:839.267 JLINK_ReadReg(R15 (PC))
+T2F54 000:839.276 - 0.011ms returns 0x20000000
+T2F54 000:839.284 JLINK_ClrBPEx(BPHandle = 0x00000012)
+T2F54 000:839.291 - 0.009ms returns 0x00
+T2F54 000:839.299 JLINK_ReadReg(R0)
+T2F54 000:839.305 - 0.009ms returns 0x00000001
+T2F54 000:839.314 JLINK_HasError()
+T2F54 000:839.322 JLINK_WriteReg(R0, 0x00008000)
+T2F54 000:839.329 - 0.009ms returns 0
+T2F54 000:839.336 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:839.343 - 0.009ms returns 0
+T2F54 000:839.351 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:839.357 - 0.009ms returns 0
+T2F54 000:839.364 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:839.371 - 0.009ms returns 0
+T2F54 000:839.378 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:839.384 - 0.009ms returns 0
+T2F54 000:839.392 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:839.398 - 0.009ms returns 0
+T2F54 000:839.406 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:839.412 - 0.009ms returns 0
+T2F54 000:839.420 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:839.426 - 0.009ms returns 0
+T2F54 000:839.433 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:839.440 - 0.009ms returns 0
+T2F54 000:839.447 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:839.453 - 0.009ms returns 0
+T2F54 000:839.461 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:839.467 - 0.009ms returns 0
+T2F54 000:839.475 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:839.481 - 0.009ms returns 0
+T2F54 000:839.488 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:839.495 - 0.009ms returns 0
+T2F54 000:839.502 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:839.509 - 0.009ms returns 0
+T2F54 000:839.516 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:839.523 - 0.009ms returns 0
+T2F54 000:839.530 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:839.536 - 0.009ms returns 0
+T2F54 000:839.545 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:839.551 - 0.009ms returns 0
+T2F54 000:839.558 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:839.565 - 0.009ms returns 0
+T2F54 000:839.572 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:839.578 - 0.009ms returns 0
+T2F54 000:839.586 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:839.592 - 0.009ms returns 0
+T2F54 000:839.600 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:839.607 - 0.009ms returns 0x00000013
+T2F54 000:839.615 JLINK_Go()
+T2F54 000:839.626   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:843.082 - 3.475ms
+T2F54 000:843.098 JLINK_IsHalted()
+T2F54 000:843.487 - 0.397ms returns FALSE
+T2F54 000:843.556 JLINK_HasError()
+T2F54 000:844.711 JLINK_IsHalted()
+T2F54 000:845.217 - 0.515ms returns FALSE
+T2F54 000:845.235 JLINK_HasError()
+T2F54 000:846.635 JLINK_IsHalted()
+T2F54 000:847.084 - 0.458ms returns FALSE
+T2F54 000:847.101 JLINK_HasError()
+T2F54 000:848.712 JLINK_IsHalted()
+T2F54 000:849.096 - 0.407ms returns FALSE
+T2F54 000:849.150 JLINK_HasError()
+T2F54 000:854.763 JLINK_IsHalted()
+T2F54 000:855.223 - 0.468ms returns FALSE
+T2F54 000:855.239 JLINK_HasError()
+T2F54 000:856.723 JLINK_IsHalted()
+T2F54 000:857.260 - 0.549ms returns FALSE
+T2F54 000:857.286 JLINK_HasError()
+T2F54 000:859.043 JLINK_IsHalted()
+T2F54 000:859.870 - 0.845ms returns FALSE
+T2F54 000:859.900 JLINK_HasError()
+T2F54 000:861.786 JLINK_IsHalted()
+T2F54 000:862.292 - 0.524ms returns FALSE
+T2F54 000:862.323 JLINK_HasError()
+T2F54 000:864.148 JLINK_IsHalted()
+T2F54 000:867.287   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:867.644 - 3.502ms returns TRUE
+T2F54 000:867.659 JLINK_ReadReg(R15 (PC))
+T2F54 000:867.668 - 0.012ms returns 0x20000000
+T2F54 000:867.677 JLINK_ClrBPEx(BPHandle = 0x00000013)
+T2F54 000:867.684 - 0.009ms returns 0x00
+T2F54 000:867.692 JLINK_ReadReg(R0)
+T2F54 000:867.698 - 0.009ms returns 0x00000000
+T2F54 000:868.306 JLINK_HasError()
+T2F54 000:868.319 JLINK_WriteReg(R0, 0x00009000)
+T2F54 000:868.328 - 0.011ms returns 0
+T2F54 000:868.336 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:868.342 - 0.009ms returns 0
+T2F54 000:868.350 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:868.355 - 0.009ms returns 0
+T2F54 000:868.363 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:868.369 - 0.008ms returns 0
+T2F54 000:868.377 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:868.383 - 0.008ms returns 0
+T2F54 000:868.390 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:868.396 - 0.008ms returns 0
+T2F54 000:868.403 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:868.409 - 0.008ms returns 0
+T2F54 000:868.417 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:868.423 - 0.008ms returns 0
+T2F54 000:868.430 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:868.436 - 0.008ms returns 0
+T2F54 000:868.444 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:868.450 - 0.008ms returns 0
+T2F54 000:868.457 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:868.463 - 0.008ms returns 0
+T2F54 000:868.470 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:868.476 - 0.008ms returns 0
+T2F54 000:868.484 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:868.490 - 0.008ms returns 0
+T2F54 000:868.497 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:868.504 - 0.009ms returns 0
+T2F54 000:868.511 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:868.517 - 0.008ms returns 0
+T2F54 000:868.525 JLINK_WriteReg(R15 (PC), 0x20000020)
+T2F54 000:868.531 - 0.009ms returns 0
+T2F54 000:868.538 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:868.544 - 0.008ms returns 0
+T2F54 000:868.552 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:868.558 - 0.008ms returns 0
+T2F54 000:868.565 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:868.571 - 0.008ms returns 0
+T2F54 000:868.579 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:868.585 - 0.008ms returns 0
+T2F54 000:868.592 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:868.599 - 0.009ms returns 0x00000014
+T2F54 000:868.607 JLINK_Go()
+T2F54 000:868.619   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:871.811 - 3.211ms
+T2F54 000:871.826 JLINK_IsHalted()
+T2F54 000:874.907   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:875.597 - 3.778ms returns TRUE
+T2F54 000:875.613 JLINK_ReadReg(R15 (PC))
+T2F54 000:875.621 - 0.012ms returns 0x20000000
+T2F54 000:875.630 JLINK_ClrBPEx(BPHandle = 0x00000014)
+T2F54 000:875.636 - 0.009ms returns 0x00
+T2F54 000:875.644 JLINK_ReadReg(R0)
+T2F54 000:875.651 - 0.009ms returns 0x00000001
+T2F54 000:875.659 JLINK_HasError()
+T2F54 000:875.667 JLINK_WriteReg(R0, 0x00009000)
+T2F54 000:875.673 - 0.009ms returns 0
+T2F54 000:875.681 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:875.687 - 0.009ms returns 0
+T2F54 000:875.695 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:875.701 - 0.009ms returns 0
+T2F54 000:875.709 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:875.715 - 0.066ms returns 0
+T2F54 000:875.783 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:875.790 - 0.010ms returns 0
+T2F54 000:875.798 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:875.804 - 0.008ms returns 0
+T2F54 000:875.811 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:875.817 - 0.008ms returns 0
+T2F54 000:875.825 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:875.831 - 0.008ms returns 0
+T2F54 000:875.838 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:875.844 - 0.008ms returns 0
+T2F54 000:875.852 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:875.858 - 0.008ms returns 0
+T2F54 000:875.865 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:875.871 - 0.008ms returns 0
+T2F54 000:875.879 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:875.885 - 0.008ms returns 0
+T2F54 000:875.892 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:875.898 - 0.008ms returns 0
+T2F54 000:875.906 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:875.912 - 0.009ms returns 0
+T2F54 000:875.920 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:875.925 - 0.008ms returns 0
+T2F54 000:875.933 JLINK_WriteReg(R15 (PC), 0x20000066)
+T2F54 000:875.939 - 0.009ms returns 0
+T2F54 000:875.947 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:875.953 - 0.008ms returns 0
+T2F54 000:875.960 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:875.966 - 0.008ms returns 0
+T2F54 000:875.974 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:875.980 - 0.008ms returns 0
+T2F54 000:875.987 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:875.993 - 0.008ms returns 0
+T2F54 000:876.001 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:876.008 - 0.009ms returns 0x00000015
+T2F54 000:876.015 JLINK_Go()
+T2F54 000:876.026   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:879.591 - 3.599ms
+T2F54 000:879.628 JLINK_IsHalted()
+T2F54 000:880.037 - 0.418ms returns FALSE
+T2F54 000:880.059 JLINK_HasError()
+T2F54 000:881.927 JLINK_IsHalted()
+T2F54 000:882.427 - 0.521ms returns FALSE
+T2F54 000:882.480 JLINK_HasError()
+T2F54 000:883.889 JLINK_IsHalted()
+T2F54 000:884.359 - 0.478ms returns FALSE
+T2F54 000:884.388 JLINK_HasError()
+T2F54 000:886.098 JLINK_IsHalted()
+T2F54 000:886.491 - 0.399ms returns FALSE
+T2F54 000:886.506 JLINK_HasError()
+T2F54 000:888.119 JLINK_IsHalted()
+T2F54 000:888.750 - 0.638ms returns FALSE
+T2F54 000:888.766 JLINK_HasError()
+T2F54 000:890.069 JLINK_IsHalted()
+T2F54 000:890.708 - 0.647ms returns FALSE
+T2F54 000:890.724 JLINK_HasError()
+T2F54 000:891.993 JLINK_IsHalted()
+T2F54 000:892.717 - 0.731ms returns FALSE
+T2F54 000:892.732 JLINK_HasError()
+T2F54 000:894.998 JLINK_IsHalted()
+T2F54 000:895.422 - 0.433ms returns FALSE
+T2F54 000:895.439 JLINK_HasError()
+T2F54 000:896.778 JLINK_IsHalted()
+T2F54 000:897.241 - 0.472ms returns FALSE
+T2F54 000:897.259 JLINK_HasError()
+T2F54 000:898.822 JLINK_IsHalted()
+T2F54 000:899.202 - 0.390ms returns FALSE
+T2F54 000:899.221 JLINK_HasError()
+T2F54 000:901.022 JLINK_IsHalted()
+T2F54 000:904.493   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:905.185 - 4.171ms returns TRUE
+T2F54 000:905.201 JLINK_ReadReg(R15 (PC))
+T2F54 000:905.210 - 0.012ms returns 0x20000000
+T2F54 000:905.219 JLINK_ClrBPEx(BPHandle = 0x00000015)
+T2F54 000:905.225 - 0.009ms returns 0x00
+T2F54 000:905.233 JLINK_ReadReg(R0)
+T2F54 000:905.240 - 0.009ms returns 0x00000000
+T2F54 000:905.582 JLINK_HasError()
+T2F54 000:905.594 JLINK_WriteReg(R0, 0x00000001)
+T2F54 000:905.602 - 0.011ms returns 0
+T2F54 000:905.610 JLINK_WriteReg(R1, 0x00001000)
+T2F54 000:905.616 - 0.008ms returns 0
+T2F54 000:905.624 JLINK_WriteReg(R2, 0x000000FF)
+T2F54 000:905.630 - 0.008ms returns 0
+T2F54 000:905.637 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:905.643 - 0.008ms returns 0
+T2F54 000:905.650 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:905.656 - 0.008ms returns 0
+T2F54 000:905.664 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:905.669 - 0.008ms returns 0
+T2F54 000:905.677 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:905.683 - 0.008ms returns 0
+T2F54 000:905.690 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:905.696 - 0.008ms returns 0
+T2F54 000:905.704 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:905.710 - 0.008ms returns 0
+T2F54 000:905.720 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:905.728 - 0.011ms returns 0
+T2F54 000:905.736 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:905.742 - 0.008ms returns 0
+T2F54 000:905.749 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:905.755 - 0.008ms returns 0
+T2F54 000:905.763 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:905.768 - 0.008ms returns 0
+T2F54 000:905.776 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:905.782 - 0.009ms returns 0
+T2F54 000:905.790 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:905.796 - 0.008ms returns 0
+T2F54 000:905.803 JLINK_WriteReg(R15 (PC), 0x20000044)
+T2F54 000:905.809 - 0.008ms returns 0
+T2F54 000:905.817 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:905.823 - 0.008ms returns 0
+T2F54 000:905.830 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:905.836 - 0.008ms returns 0
+T2F54 000:905.843 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:905.849 - 0.008ms returns 0
+T2F54 000:905.857 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:905.863 - 0.008ms returns 0
+T2F54 000:905.870 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:905.881 - 0.013ms returns 0x00000016
+T2F54 000:905.889 JLINK_Go()
+T2F54 000:905.901   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:910.035 - 4.154ms
+T2F54 000:910.055 JLINK_IsHalted()
+T2F54 000:913.376   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:913.825 - 3.779ms returns TRUE
+T2F54 000:913.850 JLINK_ReadReg(R15 (PC))
+T2F54 000:913.870 - 0.027ms returns 0x20000000
+T2F54 000:913.888 JLINK_ClrBPEx(BPHandle = 0x00000016)
+T2F54 000:913.902 - 0.022ms returns 0x00
+T2F54 000:913.922 JLINK_ReadReg(R0)
+T2F54 000:913.938 - 0.023ms returns 0x00000000
+T2F54 000:975.544 JLINK_WriteMem(0x20000000, 0x108 Bytes, ...)
+T2F54 000:975.572   Data:  00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ...
+T2F54 000:975.610   CPU_WriteMem(264 bytes @ 0x20000000)
+T2F54 000:977.422 - 1.887ms returns 0x108
+T2F54 000:977.483 JLINK_HasError()
+T2F54 000:977.507 JLINK_WriteReg(R0, 0x00000000)
+T2F54 000:977.517 - 0.025ms returns 0
+T2F54 000:977.538 JLINK_WriteReg(R1, 0x00B71B00)
+T2F54 000:977.545 - 0.009ms returns 0
+T2F54 000:977.552 JLINK_WriteReg(R2, 0x00000002)
+T2F54 000:977.572 - 0.022ms returns 0
+T2F54 000:977.579 JLINK_WriteReg(R3, 0x00000000)
+T2F54 000:977.599 - 0.022ms returns 0
+T2F54 000:977.619 JLINK_WriteReg(R4, 0x00000000)
+T2F54 000:977.625 - 0.008ms returns 0
+T2F54 000:977.633 JLINK_WriteReg(R5, 0x00000000)
+T2F54 000:977.652 - 0.022ms returns 0
+T2F54 000:977.659 JLINK_WriteReg(R6, 0x00000000)
+T2F54 000:977.665 - 0.008ms returns 0
+T2F54 000:977.673 JLINK_WriteReg(R7, 0x00000000)
+T2F54 000:977.679 - 0.008ms returns 0
+T2F54 000:977.686 JLINK_WriteReg(R8, 0x00000000)
+T2F54 000:977.692 - 0.008ms returns 0
+T2F54 000:977.699 JLINK_WriteReg(R9, 0x20000104)
+T2F54 000:977.705 - 0.008ms returns 0
+T2F54 000:977.713 JLINK_WriteReg(R10, 0x00000000)
+T2F54 000:977.719 - 0.009ms returns 0
+T2F54 000:977.731 JLINK_WriteReg(R11, 0x00000000)
+T2F54 000:977.737 - 0.009ms returns 0
+T2F54 000:977.745 JLINK_WriteReg(R12, 0x00000000)
+T2F54 000:977.751 - 0.008ms returns 0
+T2F54 000:977.758 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 000:977.765 - 0.009ms returns 0
+T2F54 000:977.772 JLINK_WriteReg(R14, 0x20000001)
+T2F54 000:977.778 - 0.008ms returns 0
+T2F54 000:977.786 JLINK_WriteReg(R15 (PC), 0x20000040)
+T2F54 000:977.792 - 0.009ms returns 0
+T2F54 000:977.799 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 000:977.806 - 0.009ms returns 0
+T2F54 000:977.813 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 000:977.819 - 0.008ms returns 0
+T2F54 000:977.827 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 000:977.833 - 0.008ms returns 0
+T2F54 000:977.840 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 000:977.846 - 0.008ms returns 0
+T2F54 000:977.854 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 000:977.864   CPU_ReadMem(4 bytes @ 0x20000000)
+T2F54 000:978.244   CPU_WriteMem(4 bytes @ 0x20000000)
+T2F54 000:978.566   CPU_ReadMem(4 bytes @ 0x20000000)
+T2F54 000:978.891   CPU_WriteMem(4 bytes @ 0x20000000)
+T2F54 000:979.282   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:979.612 - 1.768ms returns 0x00000017
+T2F54 000:979.632 JLINK_Go()
+T2F54 000:979.644   CPU_WriteMem(2 bytes @ 0x20000000)
+T2F54 000:980.025   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 000:983.217 - 3.597ms
+T2F54 000:983.239 JLINK_IsHalted()
+T2F54 000:986.357   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 000:986.679 - 3.446ms returns TRUE
+T2F54 000:986.694 JLINK_ReadReg(R15 (PC))
+T2F54 000:986.703 - 0.012ms returns 0x20000000
+T2F54 000:986.712 JLINK_ClrBPEx(BPHandle = 0x00000017)
+T2F54 000:986.719 - 0.009ms returns 0x00
+T2F54 000:986.727 JLINK_ReadReg(R0)
+T2F54 000:986.733 - 0.009ms returns 0x00000000
+T2F54 000:987.082 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 000:987.093   Data:  70 1B 00 20 29 03 00 00 2D 03 00 00 D9 02 00 00 ...
+T2F54 000:987.109   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 000:991.301 - 4.232ms returns 0x2F8
+T2F54 000:991.344 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 000:991.371   Data:  80 F3 09 88 00 B5 04 F0 8D F9 5D F8 04 EB 4E F0 ...
+T2F54 000:991.390   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 000:996.824 - 5.507ms returns 0x400
+T2F54 000:996.867 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 000:996.874   Data:  40 F0 15 80 4F F0 01 3E 12 1F C0 F2 0E 80 51 F8 ...
+T2F54 000:996.901   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:002.466 - 5.617ms returns 0x400
+T2F54 001:002.500 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:002.507   Data:  56 48 C0 F8 10 12 9F E0 4F F0 80 40 80 68 40 F0 ...
+T2F54 001:002.528   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:008.003 - 5.519ms returns 0x400
+T2F54 001:008.048 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:008.069   Data:  05 D9 02 E0 67 E1 CF E0 1B E0 01 24 00 E0 14 46 ...
+T2F54 001:008.088   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:009.886 - 1.848ms returns 0x108
+T2F54 001:009.909 JLINK_HasError()
+T2F54 001:009.962 JLINK_WriteReg(R0, 0x00000000)
+T2F54 001:009.977 - 0.018ms returns 0
+T2F54 001:009.985 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:009.992 - 0.010ms returns 0
+T2F54 001:010.000 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:010.007 - 0.009ms returns 0
+T2F54 001:010.014 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:010.020 - 0.009ms returns 0
+T2F54 001:010.029 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:010.036 - 0.010ms returns 0
+T2F54 001:010.044 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:010.050 - 0.009ms returns 0
+T2F54 001:010.058 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:010.064 - 0.009ms returns 0
+T2F54 001:010.072 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:010.078 - 0.009ms returns 0
+T2F54 001:010.086 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:010.092 - 0.009ms returns 0
+T2F54 001:010.100 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:010.106 - 0.009ms returns 0
+T2F54 001:010.114 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:010.120 - 0.009ms returns 0
+T2F54 001:010.128 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:010.134 - 0.009ms returns 0
+T2F54 001:010.141 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:010.148 - 0.009ms returns 0
+T2F54 001:010.155 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:010.162 - 0.009ms returns 0
+T2F54 001:010.170 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:010.176 - 0.009ms returns 0
+T2F54 001:010.184 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:010.190 - 0.009ms returns 0
+T2F54 001:010.198 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:010.204 - 0.009ms returns 0
+T2F54 001:010.212 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:010.218 - 0.009ms returns 0
+T2F54 001:010.225 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:010.231 - 0.009ms returns 0
+T2F54 001:010.239 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:010.245 - 0.009ms returns 0
+T2F54 001:010.253 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:010.261 - 0.010ms returns 0x00000018
+T2F54 001:010.269 JLINK_Go()
+T2F54 001:010.282   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:013.591 - 3.339ms
+T2F54 001:013.624 JLINK_IsHalted()
+T2F54 001:013.926 - 0.309ms returns FALSE
+T2F54 001:013.941 JLINK_HasError()
+T2F54 001:018.642 JLINK_IsHalted()
+T2F54 001:019.236 - 0.608ms returns FALSE
+T2F54 001:019.264 JLINK_HasError()
+T2F54 001:020.984 JLINK_IsHalted()
+T2F54 001:021.475 - 0.530ms returns FALSE
+T2F54 001:021.538 JLINK_HasError()
+T2F54 001:023.254 JLINK_IsHalted()
+T2F54 001:023.675 - 0.428ms returns FALSE
+T2F54 001:023.691 JLINK_HasError()
+T2F54 001:025.654 JLINK_IsHalted()
+T2F54 001:026.040 - 0.392ms returns FALSE
+T2F54 001:026.054 JLINK_HasError()
+T2F54 001:027.764 JLINK_IsHalted()
+T2F54 001:028.125 - 0.367ms returns FALSE
+T2F54 001:028.155 JLINK_HasError()
+T2F54 001:029.594 JLINK_IsHalted()
+T2F54 001:030.015 - 0.429ms returns FALSE
+T2F54 001:030.032 JLINK_HasError()
+T2F54 001:031.601 JLINK_IsHalted()
+T2F54 001:032.005 - 0.411ms returns FALSE
+T2F54 001:032.021 JLINK_HasError()
+T2F54 001:033.899 JLINK_IsHalted()
+T2F54 001:034.800 - 0.922ms returns FALSE
+T2F54 001:034.867 JLINK_HasError()
+T2F54 001:036.585 JLINK_IsHalted()
+T2F54 001:037.031 - 0.481ms returns FALSE
+T2F54 001:037.094 JLINK_HasError()
+T2F54 001:038.573 JLINK_IsHalted()
+T2F54 001:038.967 - 0.401ms returns FALSE
+T2F54 001:038.983 JLINK_HasError()
+T2F54 001:040.767 JLINK_IsHalted()
+T2F54 001:041.208 - 0.448ms returns FALSE
+T2F54 001:041.224 JLINK_HasError()
+T2F54 001:043.020 JLINK_IsHalted()
+T2F54 001:046.099   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:046.509 - 3.496ms returns TRUE
+T2F54 001:046.526 JLINK_ReadReg(R15 (PC))
+T2F54 001:046.536 - 0.013ms returns 0x20000000
+T2F54 001:046.545 JLINK_ClrBPEx(BPHandle = 0x00000018)
+T2F54 001:046.551 - 0.009ms returns 0x00
+T2F54 001:046.559 JLINK_ReadReg(R0)
+T2F54 001:046.566 - 0.010ms returns 0x00000000
+T2F54 001:047.169 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:047.181   Data:  C5 F8 6C 41 A2 F1 64 04 A1 F1 12 05 05 EB 85 05 ...
+T2F54 001:047.197   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:051.784 - 4.642ms returns 0x2F8
+T2F54 001:051.830 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:051.841   Data:  01 D9 01 24 00 E0 14 46 A1 F1 10 05 6D 00 AC 40 ...
+T2F54 001:051.881   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:057.494 - 5.678ms returns 0x400
+T2F54 001:057.517 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:057.525   Data:  13 68 C3 F3 08 00 08 60 03 F4 80 60 08 B1 02 20 ...
+T2F54 001:057.542   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:062.926 - 5.421ms returns 0x400
+T2F54 001:062.952 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:062.979   Data:  02 F0 2A F9 A8 46 F4 6C 2C B9 4F F4 89 72 1A 49 ...
+T2F54 001:062.996   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:068.601 - 5.707ms returns 0x400
+T2F54 001:068.677 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:068.690   Data:  70 BD 00 00 14 06 00 20 18 ED 00 E0 00 E4 00 E0 ...
+T2F54 001:068.719   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:070.558 - 1.889ms returns 0x108
+T2F54 001:070.592 JLINK_HasError()
+T2F54 001:071.248 JLINK_WriteReg(R0, 0x00001000)
+T2F54 001:071.279 - 0.033ms returns 0
+T2F54 001:071.288 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:071.308 - 0.041ms returns 0
+T2F54 001:071.334 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:071.340 - 0.009ms returns 0
+T2F54 001:071.348 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:071.354 - 0.008ms returns 0
+T2F54 001:071.361 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:071.367 - 0.008ms returns 0
+T2F54 001:071.375 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:071.381 - 0.022ms returns 0
+T2F54 001:071.401 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:071.421 - 0.022ms returns 0
+T2F54 001:071.428 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:071.434 - 0.008ms returns 0
+T2F54 001:071.442 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:071.448 - 0.009ms returns 0
+T2F54 001:071.456 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:071.462 - 0.022ms returns 0
+T2F54 001:071.483 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:071.502 - 0.022ms returns 0
+T2F54 001:071.510 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:071.516 - 0.008ms returns 0
+T2F54 001:071.523 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:071.529 - 0.008ms returns 0
+T2F54 001:071.537 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:071.543 - 0.025ms returns 0
+T2F54 001:071.582 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:071.588 - 0.009ms returns 0
+T2F54 001:071.596 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:071.602 - 0.009ms returns 0
+T2F54 001:071.609 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:071.615 - 0.008ms returns 0
+T2F54 001:071.623 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:071.629 - 0.022ms returns 0
+T2F54 001:071.649 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:071.669 - 0.022ms returns 0
+T2F54 001:071.682 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:071.688 - 0.009ms returns 0
+T2F54 001:071.696 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:071.718 - 0.024ms returns 0x00000019
+T2F54 001:071.739 JLINK_Go()
+T2F54 001:071.752   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:075.223 - 3.491ms
+T2F54 001:075.239 JLINK_IsHalted()
+T2F54 001:075.641 - 0.409ms returns FALSE
+T2F54 001:075.656 JLINK_HasError()
+T2F54 001:078.116 JLINK_IsHalted()
+T2F54 001:078.586 - 0.492ms returns FALSE
+T2F54 001:078.617 JLINK_HasError()
+T2F54 001:079.985 JLINK_IsHalted()
+T2F54 001:080.487 - 0.509ms returns FALSE
+T2F54 001:080.504 JLINK_HasError()
+T2F54 001:082.049 JLINK_IsHalted()
+T2F54 001:082.487 - 0.446ms returns FALSE
+T2F54 001:082.503 JLINK_HasError()
+T2F54 001:083.850 JLINK_IsHalted()
+T2F54 001:084.292 - 0.450ms returns FALSE
+T2F54 001:084.325 JLINK_HasError()
+T2F54 001:085.916 JLINK_IsHalted()
+T2F54 001:086.283 - 0.375ms returns FALSE
+T2F54 001:086.313 JLINK_HasError()
+T2F54 001:088.040 JLINK_IsHalted()
+T2F54 001:088.441 - 0.408ms returns FALSE
+T2F54 001:088.457 JLINK_HasError()
+T2F54 001:089.888 JLINK_IsHalted()
+T2F54 001:090.682 - 0.802ms returns FALSE
+T2F54 001:090.725 JLINK_HasError()
+T2F54 001:091.925 JLINK_IsHalted()
+T2F54 001:092.641 - 0.727ms returns FALSE
+T2F54 001:092.660 JLINK_HasError()
+T2F54 001:093.910 JLINK_IsHalted()
+T2F54 001:094.609 - 0.706ms returns FALSE
+T2F54 001:094.624 JLINK_HasError()
+T2F54 001:096.751 JLINK_IsHalted()
+T2F54 001:097.138 - 0.396ms returns FALSE
+T2F54 001:097.155 JLINK_HasError()
+T2F54 001:098.748 JLINK_IsHalted()
+T2F54 001:099.258 - 0.517ms returns FALSE
+T2F54 001:099.274 JLINK_HasError()
+T2F54 001:100.696 JLINK_IsHalted()
+T2F54 001:101.061 - 0.372ms returns FALSE
+T2F54 001:101.077 JLINK_HasError()
+T2F54 001:102.917 JLINK_IsHalted()
+T2F54 001:103.262 - 0.353ms returns FALSE
+T2F54 001:103.278 JLINK_HasError()
+T2F54 001:104.937 JLINK_IsHalted()
+T2F54 001:108.271   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:108.731 - 3.806ms returns TRUE
+T2F54 001:108.753 JLINK_ReadReg(R15 (PC))
+T2F54 001:108.764 - 0.014ms returns 0x20000000
+T2F54 001:108.772 JLINK_ClrBPEx(BPHandle = 0x00000019)
+T2F54 001:108.779 - 0.009ms returns 0x00
+T2F54 001:108.788 JLINK_ReadReg(R0)
+T2F54 001:108.794 - 0.009ms returns 0x00000000
+T2F54 001:109.359 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:109.373   Data:  0A 00 00 00 10 B5 02 A0 02 F0 34 FE 00 20 10 BD ...
+T2F54 001:109.391   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:113.749 - 4.406ms returns 0x2F8
+T2F54 001:113.792 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:113.799   Data:  04 F0 2A FC 00 20 E1 E7 54 95 00 00 7C 94 00 00 ...
+T2F54 001:113.818   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:119.267 - 5.516ms returns 0x400
+T2F54 001:119.316 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:119.323   Data:  0A 02 0E 49 09 68 B1 F8 08 12 88 42 59 DA 0B 4B ...
+T2F54 001:119.337   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:124.764 - 5.478ms returns 0x400
+T2F54 001:124.812 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:124.819   Data:  E0 69 23 46 08 22 41 46 CD E9 00 0A 21 A0 02 F0 ...
+T2F54 001:124.839   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:130.443 - 5.645ms returns 0x400
+T2F54 001:130.474 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:130.487   Data:  05 AA 19 46 0D A8 FF F7 5B FE 4F F0 08 0A 5A 46 ...
+T2F54 001:130.514   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:132.280 - 1.816ms returns 0x108
+T2F54 001:132.319 JLINK_HasError()
+T2F54 001:132.438 JLINK_WriteReg(R0, 0x00002000)
+T2F54 001:132.497 - 0.063ms returns 0
+T2F54 001:132.507 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:132.528 - 0.023ms returns 0
+T2F54 001:132.536 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:132.543 - 0.029ms returns 0
+T2F54 001:132.572 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:132.578 - 0.009ms returns 0
+T2F54 001:132.586 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:132.607 - 0.024ms returns 0
+T2F54 001:132.636 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:132.643 - 0.009ms returns 0
+T2F54 001:132.651 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:132.670 - 0.022ms returns 0
+T2F54 001:132.678 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:132.684 - 0.028ms returns 0
+T2F54 001:132.711 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:132.717 - 0.009ms returns 0
+T2F54 001:132.738 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:132.744 - 0.041ms returns 0
+T2F54 001:132.772 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:132.778 - 0.009ms returns 0
+T2F54 001:132.786 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:132.806 - 0.022ms returns 0
+T2F54 001:132.813 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:132.819 - 0.028ms returns 0
+T2F54 001:132.846 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:132.853 - 0.010ms returns 0
+T2F54 001:132.861 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:132.867 - 0.009ms returns 0
+T2F54 001:132.875 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:132.881 - 0.009ms returns 0
+T2F54 001:132.889 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:132.909 - 0.022ms returns 0
+T2F54 001:132.916 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:132.942 - 0.028ms returns 0
+T2F54 001:132.955 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:132.964 - 0.016ms returns 0
+T2F54 001:132.982 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:132.994 - 0.015ms returns 0
+T2F54 001:133.004 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:133.027 - 0.045ms returns 0x0000001A
+T2F54 001:133.054 JLINK_Go()
+T2F54 001:133.081   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:136.764 - 3.723ms
+T2F54 001:136.786 JLINK_IsHalted()
+T2F54 001:137.249 - 0.471ms returns FALSE
+T2F54 001:137.265 JLINK_HasError()
+T2F54 001:140.036 JLINK_IsHalted()
+T2F54 001:140.861 - 0.834ms returns FALSE
+T2F54 001:140.878 JLINK_HasError()
+T2F54 001:142.041 JLINK_IsHalted()
+T2F54 001:142.780 - 0.747ms returns FALSE
+T2F54 001:142.809 JLINK_HasError()
+T2F54 001:144.021 JLINK_IsHalted()
+T2F54 001:144.769 - 0.757ms returns FALSE
+T2F54 001:144.789 JLINK_HasError()
+T2F54 001:146.825 JLINK_IsHalted()
+T2F54 001:147.235 - 0.419ms returns FALSE
+T2F54 001:147.254 JLINK_HasError()
+T2F54 001:148.752 JLINK_IsHalted()
+T2F54 001:149.096 - 0.353ms returns FALSE
+T2F54 001:149.131 JLINK_HasError()
+T2F54 001:150.877 JLINK_IsHalted()
+T2F54 001:151.338 - 0.470ms returns FALSE
+T2F54 001:151.355 JLINK_HasError()
+T2F54 001:152.948 JLINK_IsHalted()
+T2F54 001:153.470 - 0.530ms returns FALSE
+T2F54 001:153.486 JLINK_HasError()
+T2F54 001:155.002 JLINK_IsHalted()
+T2F54 001:155.652 - 0.658ms returns FALSE
+T2F54 001:155.668 JLINK_HasError()
+T2F54 001:156.981 JLINK_IsHalted()
+T2F54 001:157.732 - 0.759ms returns FALSE
+T2F54 001:157.749 JLINK_HasError()
+T2F54 001:158.947 JLINK_IsHalted()
+T2F54 001:159.589 - 0.650ms returns FALSE
+T2F54 001:159.606 JLINK_HasError()
+T2F54 001:160.784 JLINK_IsHalted()
+T2F54 001:161.250 - 0.486ms returns FALSE
+T2F54 001:161.279 JLINK_HasError()
+T2F54 001:162.729 JLINK_IsHalted()
+T2F54 001:163.192 - 0.484ms returns FALSE
+T2F54 001:163.235 JLINK_HasError()
+T2F54 001:164.721 JLINK_IsHalted()
+T2F54 001:165.066 - 0.352ms returns FALSE
+T2F54 001:165.081 JLINK_HasError()
+T2F54 001:167.820 JLINK_IsHalted()
+T2F54 001:170.954   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:171.622 - 3.809ms returns TRUE
+T2F54 001:171.638 JLINK_ReadReg(R15 (PC))
+T2F54 001:171.647 - 0.012ms returns 0x20000000
+T2F54 001:171.655 JLINK_ClrBPEx(BPHandle = 0x0000001A)
+T2F54 001:171.662 - 0.009ms returns 0x00
+T2F54 001:171.670 JLINK_ReadReg(R0)
+T2F54 001:171.677 - 0.009ms returns 0x00000000
+T2F54 001:172.243 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:172.257   Data:  20 2D 2D 2D 2D 20 20 2D 2D 2D 2D 20 20 2D 2D 2D ...
+T2F54 001:172.274   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:176.509 - 4.281ms returns 0x2F8
+T2F54 001:176.535 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:176.542   Data:  FC F7 9C FF 83 46 30 7A 20 F0 80 00 9D F8 30 10 ...
+T2F54 001:176.562   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:181.997 - 5.484ms returns 0x400
+T2F54 001:182.043 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:182.050   Data:  76 61 74 65 64 0A 00 00 64 65 61 63 74 69 76 61 ...
+T2F54 001:182.068   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:187.864 - 5.839ms returns 0x400
+T2F54 001:187.898 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:187.906   Data:  48 F8 27 40 7F 1C 01 E0 64 1C 6D 1C 20 78 20 28 ...
+T2F54 001:187.933   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:193.436 - 5.553ms returns 0x400
+T2F54 001:193.486 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:193.494   Data:  08 60 00 BF 00 BF FC F7 99 F9 80 46 00 F0 8C FE ...
+T2F54 001:193.513   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:195.293 - 1.816ms returns 0x108
+T2F54 001:195.315 JLINK_HasError()
+T2F54 001:195.369 JLINK_WriteReg(R0, 0x00003000)
+T2F54 001:195.383 - 0.018ms returns 0
+T2F54 001:195.392 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:195.399 - 0.009ms returns 0
+T2F54 001:195.407 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:195.414 - 0.009ms returns 0
+T2F54 001:195.422 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:195.428 - 0.009ms returns 0
+T2F54 001:195.436 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:195.442 - 0.009ms returns 0
+T2F54 001:195.449 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:195.456 - 0.009ms returns 0
+T2F54 001:195.463 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:195.469 - 0.009ms returns 0
+T2F54 001:195.477 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:195.483 - 0.009ms returns 0
+T2F54 001:195.491 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:195.497 - 0.009ms returns 0
+T2F54 001:195.505 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:195.511 - 0.009ms returns 0
+T2F54 001:195.519 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:195.525 - 0.009ms returns 0
+T2F54 001:195.533 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:195.539 - 0.009ms returns 0
+T2F54 001:195.546 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:195.553 - 0.009ms returns 0
+T2F54 001:195.560 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:195.567 - 0.009ms returns 0
+T2F54 001:195.575 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:195.581 - 0.009ms returns 0
+T2F54 001:195.589 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:195.595 - 0.009ms returns 0
+T2F54 001:195.603 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:195.609 - 0.009ms returns 0
+T2F54 001:195.617 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:195.623 - 0.009ms returns 0
+T2F54 001:195.631 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:195.637 - 0.009ms returns 0
+T2F54 001:195.645 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:195.651 - 0.009ms returns 0
+T2F54 001:195.659 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:195.667 - 0.011ms returns 0x0000001B
+T2F54 001:195.675 JLINK_Go()
+T2F54 001:195.717   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:198.931 - 3.271ms
+T2F54 001:198.955 JLINK_IsHalted()
+T2F54 001:199.294 - 0.346ms returns FALSE
+T2F54 001:199.309 JLINK_HasError()
+T2F54 001:202.020 JLINK_IsHalted()
+T2F54 001:202.527 - 0.516ms returns FALSE
+T2F54 001:202.545 JLINK_HasError()
+T2F54 001:204.413 JLINK_IsHalted()
+T2F54 001:205.284 - 0.887ms returns FALSE
+T2F54 001:205.313 JLINK_HasError()
+T2F54 001:207.056 JLINK_IsHalted()
+T2F54 001:207.512 - 0.467ms returns FALSE
+T2F54 001:207.533 JLINK_HasError()
+T2F54 001:209.024 JLINK_IsHalted()
+T2F54 001:209.408 - 0.392ms returns FALSE
+T2F54 001:209.426 JLINK_HasError()
+T2F54 001:210.699 JLINK_IsHalted()
+T2F54 001:211.204 - 0.512ms returns FALSE
+T2F54 001:211.219 JLINK_HasError()
+T2F54 001:213.241 JLINK_IsHalted()
+T2F54 001:213.638 - 0.404ms returns FALSE
+T2F54 001:213.654 JLINK_HasError()
+T2F54 001:215.499 JLINK_IsHalted()
+T2F54 001:216.285 - 0.795ms returns FALSE
+T2F54 001:216.303 JLINK_HasError()
+T2F54 001:217.948 JLINK_IsHalted()
+T2F54 001:218.647 - 0.706ms returns FALSE
+T2F54 001:218.662 JLINK_HasError()
+T2F54 001:219.981 JLINK_IsHalted()
+T2F54 001:220.406 - 0.431ms returns FALSE
+T2F54 001:220.424 JLINK_HasError()
+T2F54 001:222.082 JLINK_IsHalted()
+T2F54 001:222.509 - 0.442ms returns FALSE
+T2F54 001:222.538 JLINK_HasError()
+T2F54 001:224.627 JLINK_IsHalted()
+T2F54 001:225.001 - 0.381ms returns FALSE
+T2F54 001:225.017 JLINK_HasError()
+T2F54 001:226.833 JLINK_IsHalted()
+T2F54 001:227.218 - 0.412ms returns FALSE
+T2F54 001:227.255 JLINK_HasError()
+T2F54 001:228.625 JLINK_IsHalted()
+T2F54 001:231.705   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:232.238 - 3.644ms returns TRUE
+T2F54 001:232.279 JLINK_ReadReg(R15 (PC))
+T2F54 001:232.296 - 0.020ms returns 0x20000000
+T2F54 001:232.305 JLINK_ClrBPEx(BPHandle = 0x0000001B)
+T2F54 001:232.312 - 0.010ms returns 0x00
+T2F54 001:232.321 JLINK_ReadReg(R0)
+T2F54 001:232.328 - 0.010ms returns 0x00000000
+T2F54 001:233.081 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:233.096   Data:  80 47 24 1D 02 48 84 42 F9 D3 10 BD 6C 94 00 00 ...
+T2F54 001:233.114   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:237.458 - 4.398ms returns 0x2F8
+T2F54 001:237.505 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:237.514   Data:  64 65 20 69 73 20 25 64 0A 00 00 00 64 65 76 2D ...
+T2F54 001:237.568   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:243.095 - 5.605ms returns 0x400
+T2F54 001:243.121 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:243.129   Data:  0C 00 00 20 70 73 72 3A 20 30 78 25 30 38 78 0A ...
+T2F54 001:243.151   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:248.596 - 5.491ms returns 0x400
+T2F54 001:248.628 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:248.636   Data:  01 EB C4 01 1F 4A 42 F8 31 00 1F 49 04 EB 44 00 ...
+T2F54 001:248.656   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:254.223 - 5.629ms returns 0x400
+T2F54 001:254.288 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:254.295   Data:  FE F7 2A FF 20 46 00 F0 C9 FC 07 28 04 D0 BD 22 ...
+T2F54 001:254.350   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:256.221 - 1.941ms returns 0x108
+T2F54 001:256.241 JLINK_HasError()
+T2F54 001:256.265 JLINK_WriteReg(R0, 0x00004000)
+T2F54 001:256.289 - 0.026ms returns 0
+T2F54 001:256.300 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:256.320 - 0.023ms returns 0
+T2F54 001:256.350 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:256.371 - 0.023ms returns 0
+T2F54 001:256.381 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:256.387 - 0.009ms returns 0
+T2F54 001:256.529 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:256.556 - 0.030ms returns 0
+T2F54 001:256.568 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:256.583 - 0.020ms returns 0
+T2F54 001:256.613 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:256.635 - 0.024ms returns 0
+T2F54 001:256.642 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:256.667 - 0.027ms returns 0
+T2F54 001:256.675 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:256.681 - 0.008ms returns 0
+T2F54 001:256.701 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:256.707 - 0.021ms returns 0
+T2F54 001:256.728 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:256.734 - 0.009ms returns 0
+T2F54 001:256.742 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:256.761 - 0.022ms returns 0
+T2F54 001:256.787 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:256.793 - 0.009ms returns 0
+T2F54 001:256.801 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:256.807 - 0.009ms returns 0
+T2F54 001:256.829 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:256.835 - 0.023ms returns 0
+T2F54 001:256.856 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:256.876 - 0.022ms returns 0
+T2F54 001:256.883 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:256.889 - 0.008ms returns 0
+T2F54 001:256.915 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:256.921 - 0.009ms returns 0
+T2F54 001:256.929 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:256.934 - 0.008ms returns 0
+T2F54 001:256.942 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:256.948 - 0.008ms returns 0
+T2F54 001:256.958 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:256.967 - 0.025ms returns 0x0000001C
+T2F54 001:256.989 JLINK_Go()
+T2F54 001:257.020   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:260.321 - 3.339ms
+T2F54 001:260.337 JLINK_IsHalted()
+T2F54 001:260.710 - 0.380ms returns FALSE
+T2F54 001:260.724 JLINK_HasError()
+T2F54 001:262.322 JLINK_IsHalted()
+T2F54 001:262.775 - 0.465ms returns FALSE
+T2F54 001:262.798 JLINK_HasError()
+T2F54 001:265.076 JLINK_IsHalted()
+T2F54 001:265.808 - 0.739ms returns FALSE
+T2F54 001:265.824 JLINK_HasError()
+T2F54 001:267.013 JLINK_IsHalted()
+T2F54 001:267.744 - 0.738ms returns FALSE
+T2F54 001:267.763 JLINK_HasError()
+T2F54 001:269.069 JLINK_IsHalted()
+T2F54 001:269.408 - 0.346ms returns FALSE
+T2F54 001:269.437 JLINK_HasError()
+T2F54 001:270.795 JLINK_IsHalted()
+T2F54 001:271.233 - 0.445ms returns FALSE
+T2F54 001:271.248 JLINK_HasError()
+T2F54 001:272.813 JLINK_IsHalted()
+T2F54 001:273.230 - 0.423ms returns FALSE
+T2F54 001:273.244 JLINK_HasError()
+T2F54 001:274.822 JLINK_IsHalted()
+T2F54 001:275.267 - 0.451ms returns FALSE
+T2F54 001:275.281 JLINK_HasError()
+T2F54 001:277.323 JLINK_IsHalted()
+T2F54 001:278.165 - 0.863ms returns FALSE
+T2F54 001:278.198 JLINK_HasError()
+T2F54 001:279.383 JLINK_IsHalted()
+T2F54 001:279.832 - 0.470ms returns FALSE
+T2F54 001:279.862 JLINK_HasError()
+T2F54 001:281.061 JLINK_IsHalted()
+T2F54 001:281.591 - 0.550ms returns FALSE
+T2F54 001:281.627 JLINK_HasError()
+T2F54 001:283.417 JLINK_IsHalted()
+T2F54 001:283.876 - 0.469ms returns FALSE
+T2F54 001:283.896 JLINK_HasError()
+T2F54 001:285.499 JLINK_IsHalted()
+T2F54 001:285.984 - 0.498ms returns FALSE
+T2F54 001:286.013 JLINK_HasError()
+T2F54 001:288.032 JLINK_IsHalted()
+T2F54 001:288.458 - 0.433ms returns FALSE
+T2F54 001:288.475 JLINK_HasError()
+T2F54 001:291.055 JLINK_IsHalted()
+T2F54 001:294.207   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:294.599 - 3.552ms returns TRUE
+T2F54 001:294.637 JLINK_ReadReg(R15 (PC))
+T2F54 001:294.647 - 0.013ms returns 0x20000000
+T2F54 001:294.656 JLINK_ClrBPEx(BPHandle = 0x0000001C)
+T2F54 001:294.662 - 0.009ms returns 0x00
+T2F54 001:294.671 JLINK_ReadReg(R0)
+T2F54 001:294.677 - 0.023ms returns 0x00000000
+T2F54 001:295.389 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:295.404   Data:  28 61 68 61 1F 48 40 1C 28 60 04 F1 44 00 00 F0 ...
+T2F54 001:295.423   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:299.938 - 4.567ms returns 0x2F8
+T2F54 001:299.967 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:299.975   Data:  08 61 B9 F1 00 0F 0B D0 A8 6A 00 69 20 61 A8 6A ...
+T2F54 001:299.994   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:305.526 - 5.573ms returns 0x400
+T2F54 001:305.552 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:305.559   Data:  00 20 20 72 FA F7 9A FD 05 46 04 F1 0C 00 FF F7 ...
+T2F54 001:305.578   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:311.132 - 5.589ms returns 0x400
+T2F54 001:311.154 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:311.180   Data:  28 46 00 F0 57 F8 20 46 00 F0 A2 F8 94 F8 34 00 ...
+T2F54 001:311.208   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:316.744 - 5.626ms returns 0x400
+T2F54 001:316.794 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:316.822   Data:  88 47 00 BF 00 20 A3 E7 08 8A 00 00 73 65 6D 20 ...
+T2F54 001:316.855   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:318.782 - 1.995ms returns 0x108
+T2F54 001:318.802 JLINK_HasError()
+T2F54 001:318.960 JLINK_WriteReg(R0, 0x00005000)
+T2F54 001:318.985 - 0.027ms returns 0
+T2F54 001:318.994 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:319.000 - 0.009ms returns 0
+T2F54 001:319.008 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:319.015 - 0.009ms returns 0
+T2F54 001:319.022 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:319.030 - 0.010ms returns 0
+T2F54 001:319.038 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:319.044 - 0.009ms returns 0
+T2F54 001:319.052 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:319.071 - 0.022ms returns 0
+T2F54 001:319.098 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:319.106 - 0.013ms returns 0
+T2F54 001:319.116 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:319.123 - 0.009ms returns 0
+T2F54 001:319.130 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:319.137 - 0.009ms returns 0
+T2F54 001:319.144 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:319.150 - 0.008ms returns 0
+T2F54 001:319.158 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:319.164 - 0.009ms returns 0
+T2F54 001:319.172 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:319.178 - 0.009ms returns 0
+T2F54 001:319.199 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:319.205 - 0.028ms returns 0
+T2F54 001:319.232 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:319.240 - 0.011ms returns 0
+T2F54 001:319.248 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:319.254 - 0.009ms returns 0
+T2F54 001:319.262 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:319.268 - 0.009ms returns 0
+T2F54 001:319.276 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:319.282 - 0.009ms returns 0
+T2F54 001:319.290 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:319.296 - 0.009ms returns 0
+T2F54 001:319.303 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:319.309 - 0.009ms returns 0
+T2F54 001:319.317 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:319.323 - 0.009ms returns 0
+T2F54 001:319.331 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:319.339 - 0.011ms returns 0x0000001D
+T2F54 001:319.348 JLINK_Go()
+T2F54 001:319.361   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:322.767 - 3.428ms
+T2F54 001:322.784 JLINK_IsHalted()
+T2F54 001:323.201 - 0.424ms returns FALSE
+T2F54 001:323.217 JLINK_HasError()
+T2F54 001:327.623 JLINK_IsHalted()
+T2F54 001:328.102 - 0.489ms returns FALSE
+T2F54 001:328.120 JLINK_HasError()
+T2F54 001:329.539 JLINK_IsHalted()
+T2F54 001:330.001 - 0.471ms returns FALSE
+T2F54 001:330.019 JLINK_HasError()
+T2F54 001:331.629 JLINK_IsHalted()
+T2F54 001:332.096 - 0.502ms returns FALSE
+T2F54 001:332.142 JLINK_HasError()
+T2F54 001:333.523 JLINK_IsHalted()
+T2F54 001:333.947 - 0.431ms returns FALSE
+T2F54 001:333.963 JLINK_HasError()
+T2F54 001:336.130 JLINK_IsHalted()
+T2F54 001:336.529 - 0.406ms returns FALSE
+T2F54 001:336.544 JLINK_HasError()
+T2F54 001:338.149 JLINK_IsHalted()
+T2F54 001:338.538 - 0.397ms returns FALSE
+T2F54 001:338.554 JLINK_HasError()
+T2F54 001:340.489 JLINK_IsHalted()
+T2F54 001:341.058 - 0.586ms returns FALSE
+T2F54 001:341.087 JLINK_HasError()
+T2F54 001:342.342 JLINK_IsHalted()
+T2F54 001:342.946 - 0.621ms returns FALSE
+T2F54 001:342.974 JLINK_HasError()
+T2F54 001:344.886 JLINK_IsHalted()
+T2F54 001:345.403 - 0.536ms returns FALSE
+T2F54 001:345.434 JLINK_HasError()
+T2F54 001:347.560 JLINK_IsHalted()
+T2F54 001:347.955 - 0.404ms returns FALSE
+T2F54 001:347.973 JLINK_HasError()
+T2F54 001:349.548 JLINK_IsHalted()
+T2F54 001:350.027 - 0.505ms returns FALSE
+T2F54 001:350.062 JLINK_HasError()
+T2F54 001:351.533 JLINK_IsHalted()
+T2F54 001:354.578   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:354.909 - 3.382ms returns TRUE
+T2F54 001:354.923 JLINK_ReadReg(R15 (PC))
+T2F54 001:354.931 - 0.011ms returns 0x20000000
+T2F54 001:354.940 JLINK_ClrBPEx(BPHandle = 0x0000001D)
+T2F54 001:354.946 - 0.009ms returns 0x00
+T2F54 001:354.954 JLINK_ReadReg(R0)
+T2F54 001:354.960 - 0.009ms returns 0x00000000
+T2F54 001:355.489 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:355.499   Data:  48 72 0B 49 14 A0 FD F7 A3 FE 30 46 FE F7 E8 FA ...
+T2F54 001:355.513   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:360.083 - 4.611ms returns 0x2F8
+T2F54 001:360.118 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:360.125   Data:  2C B9 4F F4 52 72 0C 49 0C A0 FD F7 25 FD 15 B9 ...
+T2F54 001:360.164   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:365.631 - 5.529ms returns 0x400
+T2F54 001:365.658 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:365.678   Data:  48 46 E8 E7 10 B5 00 22 0A 49 08 68 88 42 0E D0 ...
+T2F54 001:365.711   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:371.204 - 5.569ms returns 0x400
+T2F54 001:371.239 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:371.246   Data:  FD F7 2A F9 F9 F7 9A FB 05 46 20 46 00 F0 86 F8 ...
+T2F54 001:371.285   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:377.064 - 5.843ms returns 0x400
+T2F54 001:377.099 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:377.106   Data:  05 E0 00 BF 05 48 FD F7 12 FF 00 28 AB D0 00 BF ...
+T2F54 001:377.125   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:378.942 - 1.862ms returns 0x108
+T2F54 001:378.980 JLINK_HasError()
+T2F54 001:379.063 JLINK_WriteReg(R0, 0x00006000)
+T2F54 001:379.082 - 0.022ms returns 0
+T2F54 001:379.091 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:379.098 - 0.009ms returns 0
+T2F54 001:379.105 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:379.112 - 0.009ms returns 0
+T2F54 001:379.119 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:379.125 - 0.009ms returns 0
+T2F54 001:379.133 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:379.140 - 0.009ms returns 0
+T2F54 001:379.147 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:379.153 - 0.009ms returns 0
+T2F54 001:379.161 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:379.167 - 0.009ms returns 0
+T2F54 001:379.175 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:379.181 - 0.009ms returns 0
+T2F54 001:379.189 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:379.195 - 0.009ms returns 0
+T2F54 001:379.202 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:379.209 - 0.009ms returns 0
+T2F54 001:379.216 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:379.222 - 0.009ms returns 0
+T2F54 001:379.230 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:379.236 - 0.009ms returns 0
+T2F54 001:379.244 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:379.250 - 0.009ms returns 0
+T2F54 001:379.258 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:379.265 - 0.010ms returns 0
+T2F54 001:379.273 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:379.279 - 0.009ms returns 0
+T2F54 001:379.287 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:379.293 - 0.009ms returns 0
+T2F54 001:379.301 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:379.307 - 0.009ms returns 0
+T2F54 001:379.315 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:379.321 - 0.009ms returns 0
+T2F54 001:379.329 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:379.349 - 0.022ms returns 0
+T2F54 001:379.356 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:379.381 - 0.028ms returns 0
+T2F54 001:379.406 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:379.414 - 0.011ms returns 0x0000001E
+T2F54 001:379.422 JLINK_Go()
+T2F54 001:379.455   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:382.823 - 3.465ms
+T2F54 001:382.897 JLINK_IsHalted()
+T2F54 001:383.342 - 0.453ms returns FALSE
+T2F54 001:383.375 JLINK_HasError()
+T2F54 001:384.607 JLINK_IsHalted()
+T2F54 001:385.021 - 0.422ms returns FALSE
+T2F54 001:385.037 JLINK_HasError()
+T2F54 001:386.612 JLINK_IsHalted()
+T2F54 001:386.987 - 0.383ms returns FALSE
+T2F54 001:387.003 JLINK_HasError()
+T2F54 001:388.809 JLINK_IsHalted()
+T2F54 001:389.257 - 0.456ms returns FALSE
+T2F54 001:389.273 JLINK_HasError()
+T2F54 001:390.817 JLINK_IsHalted()
+T2F54 001:391.271 - 0.461ms returns FALSE
+T2F54 001:391.287 JLINK_HasError()
+T2F54 001:393.574 JLINK_IsHalted()
+T2F54 001:394.147 - 0.585ms returns FALSE
+T2F54 001:394.189 JLINK_HasError()
+T2F54 001:396.108 JLINK_IsHalted()
+T2F54 001:396.487 - 0.390ms returns FALSE
+T2F54 001:396.507 JLINK_HasError()
+T2F54 001:399.303 JLINK_IsHalted()
+T2F54 001:399.938 - 0.643ms returns FALSE
+T2F54 001:399.954 JLINK_HasError()
+T2F54 001:402.103 JLINK_IsHalted()
+T2F54 001:402.810 - 0.713ms returns FALSE
+T2F54 001:402.823 JLINK_HasError()
+T2F54 001:405.040 JLINK_IsHalted()
+T2F54 001:405.784 - 0.750ms returns FALSE
+T2F54 001:405.803 JLINK_HasError()
+T2F54 001:406.993 JLINK_IsHalted()
+T2F54 001:407.487 - 0.501ms returns FALSE
+T2F54 001:407.501 JLINK_HasError()
+T2F54 001:408.995 JLINK_IsHalted()
+T2F54 001:409.533 - 0.552ms returns FALSE
+T2F54 001:409.572 JLINK_HasError()
+T2F54 001:410.796 JLINK_IsHalted()
+T2F54 001:411.222 - 0.433ms returns FALSE
+T2F54 001:411.258 JLINK_HasError()
+T2F54 001:412.960 JLINK_IsHalted()
+T2F54 001:415.939   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:416.290 - 3.338ms returns TRUE
+T2F54 001:416.307 JLINK_ReadReg(R15 (PC))
+T2F54 001:416.328 - 0.024ms returns 0x20000000
+T2F54 001:416.337 JLINK_ClrBPEx(BPHandle = 0x0000001E)
+T2F54 001:416.344 - 0.010ms returns 0x00
+T2F54 001:416.352 JLINK_ReadReg(R0)
+T2F54 001:416.359 - 0.009ms returns 0x00000000
+T2F54 001:417.020 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:417.045   Data:  2C B9 4F F4 86 72 15 49 15 A0 FC F7 A1 FE 20 46 ...
+T2F54 001:417.073   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:421.423 - 4.427ms returns 0x2F8
+T2F54 001:421.459 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:421.465   Data:  F5 12 17 49 17 A0 FC F7 27 FD 20 46 FE F7 C6 FA ...
+T2F54 001:421.484   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:426.935 - 5.499ms returns 0x400
+T2F54 001:426.970 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:426.977   Data:  4F F0 FF 31 28 46 02 9B FF F7 56 FE 3E BD 00 20 ...
+T2F54 001:426.997   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:432.905 - 5.952ms returns 0x400
+T2F54 001:432.939 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:432.946   Data:  9D FE 04 46 14 B9 06 20 BD E8 F8 83 01 2E 6D D1 ...
+T2F54 001:432.966   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:438.883 - 5.966ms returns 0x400
+T2F54 001:438.941 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:438.949   Data:  69 67 75 72 65 20 21 3D 20 52 54 5F 4E 55 4C 4C ...
+T2F54 001:438.968   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:440.976 - 2.052ms returns 0x108
+T2F54 001:441.011 JLINK_HasError()
+T2F54 001:441.096 JLINK_WriteReg(R0, 0x00007000)
+T2F54 001:441.130 - 0.050ms returns 0
+T2F54 001:441.151 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:441.158 - 0.027ms returns 0
+T2F54 001:441.184 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:441.190 - 0.008ms returns 0
+T2F54 001:441.198 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:441.204 - 0.008ms returns 0
+T2F54 001:441.226 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:441.251 - 0.028ms returns 0
+T2F54 001:441.272 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:441.278 - 0.008ms returns 0
+T2F54 001:441.285 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:441.291 - 0.008ms returns 0
+T2F54 001:441.317 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:441.323 - 0.008ms returns 0
+T2F54 001:441.331 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:441.337 - 0.021ms returns 0
+T2F54 001:441.357 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:441.363 - 0.008ms returns 0
+T2F54 001:441.389 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:441.395 - 0.008ms returns 0
+T2F54 001:441.403 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:441.409 - 0.023ms returns 0
+T2F54 001:441.431 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:441.456 - 0.028ms returns 0
+T2F54 001:441.477 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:441.484 - 0.009ms returns 0
+T2F54 001:441.491 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:441.516 - 0.027ms returns 0
+T2F54 001:441.523 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:441.529 - 0.009ms returns 0
+T2F54 001:441.537 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:441.543 - 0.008ms returns 0
+T2F54 001:441.550 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:441.556 - 0.008ms returns 0
+T2F54 001:441.564 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:441.570 - 0.008ms returns 0
+T2F54 001:441.590 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:441.596 - 0.027ms returns 0
+T2F54 001:441.623 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:441.631 - 0.010ms returns 0x0000001F
+T2F54 001:441.639 JLINK_Go()
+T2F54 001:441.652   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:445.062 - 3.434ms
+T2F54 001:445.081 JLINK_IsHalted()
+T2F54 001:445.396 - 0.323ms returns FALSE
+T2F54 001:445.413 JLINK_HasError()
+T2F54 001:446.711 JLINK_IsHalted()
+T2F54 001:447.057 - 0.353ms returns FALSE
+T2F54 001:447.072 JLINK_HasError()
+T2F54 001:448.831 JLINK_IsHalted()
+T2F54 001:449.310 - 0.486ms returns FALSE
+T2F54 001:449.325 JLINK_HasError()
+T2F54 001:450.832 JLINK_IsHalted()
+T2F54 001:451.367 - 0.543ms returns FALSE
+T2F54 001:451.383 JLINK_HasError()
+T2F54 001:453.848 JLINK_IsHalted()
+T2F54 001:454.736 - 0.905ms returns FALSE
+T2F54 001:454.768 JLINK_HasError()
+T2F54 001:456.454 JLINK_IsHalted()
+T2F54 001:457.040 - 0.610ms returns FALSE
+T2F54 001:457.093 JLINK_HasError()
+T2F54 001:458.459 JLINK_IsHalted()
+T2F54 001:458.803 - 0.353ms returns FALSE
+T2F54 001:458.820 JLINK_HasError()
+T2F54 001:460.479 JLINK_IsHalted()
+T2F54 001:460.931 - 0.458ms returns FALSE
+T2F54 001:460.945 JLINK_HasError()
+T2F54 001:462.214 JLINK_IsHalted()
+T2F54 001:462.571 - 0.365ms returns FALSE
+T2F54 001:462.586 JLINK_HasError()
+T2F54 001:464.205 JLINK_IsHalted()
+T2F54 001:464.615 - 0.419ms returns FALSE
+T2F54 001:464.633 JLINK_HasError()
+T2F54 001:466.561 JLINK_IsHalted()
+T2F54 001:467.142 - 0.590ms returns FALSE
+T2F54 001:467.163 JLINK_HasError()
+T2F54 001:468.616 JLINK_IsHalted()
+T2F54 001:469.231 - 0.640ms returns FALSE
+T2F54 001:469.267 JLINK_HasError()
+T2F54 001:470.894 JLINK_IsHalted()
+T2F54 001:471.362 - 0.481ms returns FALSE
+T2F54 001:471.391 JLINK_HasError()
+T2F54 001:473.473 JLINK_IsHalted()
+T2F54 001:473.905 - 0.441ms returns FALSE
+T2F54 001:473.926 JLINK_HasError()
+T2F54 001:475.400 JLINK_IsHalted()
+T2F54 001:478.399   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:478.785 - 3.394ms returns TRUE
+T2F54 001:478.805 JLINK_ReadReg(R15 (PC))
+T2F54 001:478.816 - 0.014ms returns 0x20000000
+T2F54 001:478.824 JLINK_ClrBPEx(BPHandle = 0x0000001F)
+T2F54 001:478.831 - 0.010ms returns 0x00
+T2F54 001:478.840 JLINK_ReadReg(R0)
+T2F54 001:478.847 - 0.009ms returns 0x00000000
+T2F54 001:479.567 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:479.584   Data:  5F 55 46 53 52 3A 30 78 25 30 32 58 20 00 00 00 ...
+T2F54 001:479.605   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:483.818 - 4.268ms returns 0x2F8
+T2F54 001:483.846 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:483.854   Data:  04 00 00 00 34 00 00 00 12 00 00 00 00 20 01 40 ...
+T2F54 001:483.873   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:489.423 - 5.586ms returns 0x400
+T2F54 001:489.442 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:489.449   Data:  05 00 00 00 38 00 00 00 52 00 00 00 00 80 01 40 ...
+T2F54 001:489.464   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:494.920 - 5.502ms returns 0x400
+T2F54 001:494.977 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:494.984   Data:  76 00 72 74 5F 65 76 65 6E 74 5F 63 6F 6E 74 72 ...
+T2F54 001:495.001   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:500.907 - 5.987ms returns 0x400
+T2F54 001:500.981 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:500.990   Data:  61 63 6B 5F 63 68 65 63 6B 00 72 74 5F 73 63 68 ...
+T2F54 001:501.025   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:503.305 - 2.349ms returns 0x108
+T2F54 001:503.364 JLINK_HasError()
+T2F54 001:503.480 JLINK_WriteReg(R0, 0x00008000)
+T2F54 001:503.532 - 0.075ms returns 0
+T2F54 001:503.563 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:503.570 - 0.010ms returns 0
+T2F54 001:503.578 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:503.599 - 0.023ms returns 0
+T2F54 001:503.626 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:503.646 - 0.022ms returns 0
+T2F54 001:503.654 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:503.661 - 0.010ms returns 0
+T2F54 001:503.688 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:503.694 - 0.009ms returns 0
+T2F54 001:503.702 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:503.709 - 0.022ms returns 0
+T2F54 001:503.730 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:503.755 - 0.028ms returns 0
+T2F54 001:503.763 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:503.770 - 0.011ms returns 0
+T2F54 001:503.779 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:503.786 - 0.010ms returns 0
+T2F54 001:503.794 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:503.800 - 0.009ms returns 0
+T2F54 001:503.821 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:503.827 - 0.028ms returns 0
+T2F54 001:503.854 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:503.865 - 0.014ms returns 0
+T2F54 001:503.874 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:503.896 - 0.024ms returns 0
+T2F54 001:503.904 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:503.929 - 0.041ms returns 0
+T2F54 001:503.953 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:503.962 - 0.011ms returns 0
+T2F54 001:503.989 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:503.995 - 0.009ms returns 0
+T2F54 001:504.003 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:504.024 - 0.023ms returns 0
+T2F54 001:504.051 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:504.057 - 0.009ms returns 0
+T2F54 001:504.065 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:504.072 - 0.023ms returns 0
+T2F54 001:504.094 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:504.121 - 0.030ms returns 0x00000020
+T2F54 001:504.130 JLINK_Go()
+T2F54 001:504.158   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:507.666 - 3.544ms
+T2F54 001:507.682 JLINK_IsHalted()
+T2F54 001:508.050 - 0.375ms returns FALSE
+T2F54 001:508.066 JLINK_HasError()
+T2F54 001:510.932 JLINK_IsHalted()
+T2F54 001:511.441 - 0.518ms returns FALSE
+T2F54 001:511.459 JLINK_HasError()
+T2F54 001:513.187 JLINK_IsHalted()
+T2F54 001:513.681 - 0.502ms returns FALSE
+T2F54 001:513.698 JLINK_HasError()
+T2F54 001:515.567 JLINK_IsHalted()
+T2F54 001:516.391 - 0.842ms returns FALSE
+T2F54 001:516.420 JLINK_HasError()
+T2F54 001:517.803 JLINK_IsHalted()
+T2F54 001:518.610 - 0.831ms returns FALSE
+T2F54 001:518.651 JLINK_HasError()
+T2F54 001:520.444 JLINK_IsHalted()
+T2F54 001:520.953 - 0.518ms returns FALSE
+T2F54 001:520.971 JLINK_HasError()
+T2F54 001:522.092 JLINK_IsHalted()
+T2F54 001:522.485 - 0.400ms returns FALSE
+T2F54 001:522.500 JLINK_HasError()
+T2F54 001:524.136 JLINK_IsHalted()
+T2F54 001:524.558 - 0.429ms returns FALSE
+T2F54 001:524.572 JLINK_HasError()
+T2F54 001:526.131 JLINK_IsHalted()
+T2F54 001:526.547 - 0.422ms returns FALSE
+T2F54 001:526.561 JLINK_HasError()
+T2F54 001:528.142 JLINK_IsHalted()
+T2F54 001:528.501 - 0.367ms returns FALSE
+T2F54 001:528.530 JLINK_HasError()
+T2F54 001:530.125 JLINK_IsHalted()
+T2F54 001:530.525 - 0.407ms returns FALSE
+T2F54 001:530.560 JLINK_HasError()
+T2F54 001:532.215 JLINK_IsHalted()
+T2F54 001:532.799 - 0.622ms returns FALSE
+T2F54 001:532.849 JLINK_HasError()
+T2F54 001:534.236 JLINK_IsHalted()
+T2F54 001:534.713 - 0.513ms returns FALSE
+T2F54 001:534.762 JLINK_HasError()
+T2F54 001:536.816 JLINK_IsHalted()
+T2F54 001:540.037   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:540.424 - 3.616ms returns TRUE
+T2F54 001:540.441 JLINK_ReadReg(R15 (PC))
+T2F54 001:540.450 - 0.012ms returns 0x20000000
+T2F54 001:540.459 JLINK_ClrBPEx(BPHandle = 0x00000020)
+T2F54 001:540.466 - 0.009ms returns 0x00
+T2F54 001:540.474 JLINK_ReadReg(R0)
+T2F54 001:540.480 - 0.009ms returns 0x00000000
+T2F54 001:541.329 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:541.340   Data:  4E 65 74 77 6F 72 6B 20 49 6E 74 65 72 66 61 63 ...
+T2F54 001:541.355   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:545.571 - 4.260ms returns 0x2F8
+T2F54 001:545.598 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:545.605   Data:  6C 69 73 74 20 65 76 65 6E 74 20 69 6E 20 73 79 ...
+T2F54 001:545.621   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:551.158 - 5.591ms returns 0x400
+T2F54 001:551.200 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:551.207   Data:  FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ...
+T2F54 001:551.258   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:556.762 - 5.572ms returns 0x400
+T2F54 001:556.785 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:556.793   Data:  FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ...
+T2F54 001:556.808   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:562.332 - 5.564ms returns 0x400
+T2F54 001:562.366 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:562.374   Data:  FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ...
+T2F54 001:562.393   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:564.286 - 1.929ms returns 0x108
+T2F54 001:564.314 JLINK_HasError()
+T2F54 001:564.324 JLINK_WriteReg(R0, 0x00009000)
+T2F54 001:564.334 - 0.013ms returns 0
+T2F54 001:564.342 JLINK_WriteReg(R1, 0x000006C4)
+T2F54 001:564.349 - 0.009ms returns 0
+T2F54 001:564.356 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:564.362 - 0.011ms returns 0
+T2F54 001:564.377 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:564.384 - 0.009ms returns 0
+T2F54 001:564.391 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:564.397 - 0.008ms returns 0
+T2F54 001:564.405 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:564.411 - 0.008ms returns 0
+T2F54 001:564.418 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:564.424 - 0.008ms returns 0
+T2F54 001:564.432 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:564.438 - 0.008ms returns 0
+T2F54 001:564.448 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:564.454 - 0.009ms returns 0
+T2F54 001:564.544 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:564.559 - 0.018ms returns 0
+T2F54 001:564.568 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:564.575 - 0.009ms returns 0
+T2F54 001:564.583 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:564.589 - 0.009ms returns 0
+T2F54 001:564.597 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:564.603 - 0.009ms returns 0
+T2F54 001:564.611 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:564.617 - 0.009ms returns 0
+T2F54 001:564.625 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:564.631 - 0.009ms returns 0
+T2F54 001:564.639 JLINK_WriteReg(R15 (PC), 0x20000080)
+T2F54 001:564.645 - 0.009ms returns 0
+T2F54 001:564.653 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:564.659 - 0.009ms returns 0
+T2F54 001:564.667 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:564.673 - 0.009ms returns 0
+T2F54 001:564.681 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:564.687 - 0.009ms returns 0
+T2F54 001:564.694 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:564.700 - 0.009ms returns 0
+T2F54 001:564.708 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:564.716 - 0.010ms returns 0x00000021
+T2F54 001:564.724 JLINK_Go()
+T2F54 001:564.738   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:568.174 - 3.483ms
+T2F54 001:568.217 JLINK_IsHalted()
+T2F54 001:568.600 - 0.407ms returns FALSE
+T2F54 001:568.633 JLINK_HasError()
+T2F54 001:572.819 JLINK_IsHalted()
+T2F54 001:573.191 - 0.379ms returns FALSE
+T2F54 001:573.207 JLINK_HasError()
+T2F54 001:574.868 JLINK_IsHalted()
+T2F54 001:575.381 - 0.519ms returns FALSE
+T2F54 001:575.395 JLINK_HasError()
+T2F54 001:577.048 JLINK_IsHalted()
+T2F54 001:577.763 - 0.723ms returns FALSE
+T2F54 001:577.779 JLINK_HasError()
+T2F54 001:579.894 JLINK_IsHalted()
+T2F54 001:580.289 - 0.403ms returns FALSE
+T2F54 001:580.306 JLINK_HasError()
+T2F54 001:581.853 JLINK_IsHalted()
+T2F54 001:585.011   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:585.408 - 3.562ms returns TRUE
+T2F54 001:585.427 JLINK_ReadReg(R15 (PC))
+T2F54 001:585.436 - 0.012ms returns 0x20000000
+T2F54 001:585.445 JLINK_ClrBPEx(BPHandle = 0x00000021)
+T2F54 001:585.452 - 0.009ms returns 0x00
+T2F54 001:585.460 JLINK_ReadReg(R0)
+T2F54 001:585.466 - 0.009ms returns 0x00000000
+T2F54 001:585.475 JLINK_HasError()
+T2F54 001:585.483 JLINK_WriteReg(R0, 0x00000002)
+T2F54 001:585.490 - 0.010ms returns 0
+T2F54 001:585.498 JLINK_WriteReg(R1, 0x000006C4)
+T2F54 001:585.504 - 0.009ms returns 0
+T2F54 001:585.512 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:585.518 - 0.009ms returns 0
+T2F54 001:585.526 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:585.532 - 0.009ms returns 0
+T2F54 001:585.540 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:585.546 - 0.008ms returns 0
+T2F54 001:585.553 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:585.559 - 0.009ms returns 0
+T2F54 001:585.567 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:585.573 - 0.009ms returns 0
+T2F54 001:585.581 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:585.587 - 0.009ms returns 0
+T2F54 001:585.595 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:585.601 - 0.009ms returns 0
+T2F54 001:585.608 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:585.614 - 0.009ms returns 0
+T2F54 001:585.622 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:585.628 - 0.009ms returns 0
+T2F54 001:585.636 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:585.642 - 0.009ms returns 0
+T2F54 001:585.649 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:585.655 - 0.008ms returns 0
+T2F54 001:585.663 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:585.669 - 0.009ms returns 0
+T2F54 001:585.677 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:585.686 - 0.014ms returns 0
+T2F54 001:585.696 JLINK_WriteReg(R15 (PC), 0x20000044)
+T2F54 001:585.702 - 0.009ms returns 0
+T2F54 001:585.710 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:585.751 - 0.044ms returns 0
+T2F54 001:585.759 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:585.765 - 0.009ms returns 0
+T2F54 001:585.773 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:585.779 - 0.009ms returns 0
+T2F54 001:585.787 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:585.793 - 0.009ms returns 0
+T2F54 001:585.800 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:585.807 - 0.010ms returns 0x00000022
+T2F54 001:585.815 JLINK_Go()
+T2F54 001:585.828   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:589.073 - 3.268ms
+T2F54 001:589.127 JLINK_IsHalted()
+T2F54 001:592.699   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:593.543 - 4.468ms returns TRUE
+T2F54 001:593.597 JLINK_ReadReg(R15 (PC))
+T2F54 001:593.609 - 0.015ms returns 0x20000000
+T2F54 001:593.772 JLINK_ClrBPEx(BPHandle = 0x00000022)
+T2F54 001:593.791 - 0.035ms returns 0x00
+T2F54 001:593.814 JLINK_ReadReg(R0)
+T2F54 001:593.821 - 0.010ms returns 0x00000000
+T2F54 001:656.255 JLINK_WriteMem(0x20000000, 0x108 Bytes, ...)
+T2F54 001:656.271   Data:  00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ...
+T2F54 001:656.291   CPU_WriteMem(264 bytes @ 0x20000000)
+T2F54 001:658.354 - 2.107ms returns 0x108
+T2F54 001:658.386 JLINK_HasError()
+T2F54 001:658.396 JLINK_WriteReg(R0, 0x00000000)
+T2F54 001:658.405 - 0.011ms returns 0
+T2F54 001:658.412 JLINK_WriteReg(R1, 0x00B71B00)
+T2F54 001:658.419 - 0.009ms returns 0
+T2F54 001:658.426 JLINK_WriteReg(R2, 0x00000003)
+T2F54 001:658.432 - 0.008ms returns 0
+T2F54 001:658.440 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:658.446 - 0.008ms returns 0
+T2F54 001:658.453 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:658.459 - 0.008ms returns 0
+T2F54 001:658.467 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:658.472 - 0.008ms returns 0
+T2F54 001:658.480 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:658.486 - 0.008ms returns 0
+T2F54 001:658.493 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:658.499 - 0.008ms returns 0
+T2F54 001:658.507 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:658.513 - 0.008ms returns 0
+T2F54 001:658.520 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:658.526 - 0.008ms returns 0
+T2F54 001:658.533 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:658.539 - 0.008ms returns 0
+T2F54 001:658.547 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:658.552 - 0.008ms returns 0
+T2F54 001:658.560 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:658.566 - 0.008ms returns 0
+T2F54 001:658.573 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:658.579 - 0.009ms returns 0
+T2F54 001:658.587 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:658.593 - 0.008ms returns 0
+T2F54 001:658.600 JLINK_WriteReg(R15 (PC), 0x20000040)
+T2F54 001:658.606 - 0.009ms returns 0
+T2F54 001:658.614 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:658.620 - 0.008ms returns 0
+T2F54 001:658.627 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:658.633 - 0.008ms returns 0
+T2F54 001:658.640 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:658.646 - 0.008ms returns 0
+T2F54 001:658.654 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:658.660 - 0.008ms returns 0
+T2F54 001:658.667 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:658.677   CPU_ReadMem(4 bytes @ 0x20000000)
+T2F54 001:659.388   CPU_WriteMem(4 bytes @ 0x20000000)
+T2F54 001:659.791   CPU_ReadMem(4 bytes @ 0x20000000)
+T2F54 001:660.324   CPU_WriteMem(4 bytes @ 0x20000000)
+T2F54 001:660.904   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:661.330 - 2.671ms returns 0x00000023
+T2F54 001:661.349 JLINK_Go()
+T2F54 001:661.362   CPU_WriteMem(2 bytes @ 0x20000000)
+T2F54 001:661.720   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:664.959 - 3.625ms
+T2F54 001:664.984 JLINK_IsHalted()
+T2F54 001:668.110   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:668.775 - 3.798ms returns TRUE
+T2F54 001:668.792 JLINK_ReadReg(R15 (PC))
+T2F54 001:668.802 - 0.012ms returns 0x20000000
+T2F54 001:668.810 JLINK_ClrBPEx(BPHandle = 0x00000023)
+T2F54 001:668.817 - 0.012ms returns 0x00
+T2F54 001:668.830 JLINK_ReadReg(R0)
+T2F54 001:668.836 - 0.009ms returns 0x00000000
+T2F54 001:668.845 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:668.852   Data:  70 1B 00 20 29 03 00 00 2D 03 00 00 D9 02 00 00 ...
+T2F54 001:668.865   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:673.358 - 4.521ms returns 0x2F8
+T2F54 001:673.379 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:673.387   Data:  80 F3 09 88 00 B5 04 F0 8D F9 5D F8 04 EB 4E F0 ...
+T2F54 001:673.401   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:678.921 - 5.560ms returns 0x400
+T2F54 001:678.958 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:678.971   Data:  40 F0 15 80 4F F0 01 3E 12 1F C0 F2 0E 80 51 F8 ...
+T2F54 001:678.997   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:684.706 - 5.758ms returns 0x400
+T2F54 001:684.730 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:684.738   Data:  56 48 C0 F8 10 12 9F E0 4F F0 80 40 80 68 40 F0 ...
+T2F54 001:684.755   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:690.389 - 5.684ms returns 0x400
+T2F54 001:690.436 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:690.446   Data:  05 D9 02 E0 67 E1 CF E0 1B E0 01 24 00 E0 14 46 ...
+T2F54 001:690.470   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:692.304 - 1.882ms returns 0x108
+T2F54 001:692.337 JLINK_HasError()
+T2F54 001:692.399 JLINK_WriteReg(R0, 0x00000000)
+T2F54 001:692.417 - 0.021ms returns 0
+T2F54 001:692.426 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:692.433 - 0.009ms returns 0
+T2F54 001:692.441 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:692.447 - 0.009ms returns 0
+T2F54 001:692.454 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:692.461 - 0.009ms returns 0
+T2F54 001:692.468 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:692.475 - 0.009ms returns 0
+T2F54 001:692.496 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:692.502 - 0.030ms returns 0
+T2F54 001:692.531 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:692.550 - 0.022ms returns 0
+T2F54 001:692.557 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:692.583 - 0.028ms returns 0
+T2F54 001:692.591 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:692.597 - 0.009ms returns 0
+T2F54 001:692.618 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:692.624 - 0.028ms returns 0
+T2F54 001:692.651 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:692.657 - 0.009ms returns 0
+T2F54 001:692.678 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:692.684 - 0.028ms returns 0
+T2F54 001:692.711 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:692.731 - 0.082ms returns 0
+T2F54 001:692.819 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:692.827 - 0.011ms returns 0
+T2F54 001:692.834 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:692.841 - 0.009ms returns 0
+T2F54 001:692.848 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:692.855 - 0.024ms returns 0
+T2F54 001:692.877 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:692.883 - 0.009ms returns 0
+T2F54 001:692.891 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:692.897 - 0.008ms returns 0
+T2F54 001:692.904 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:692.910 - 0.008ms returns 0
+T2F54 001:692.918 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:692.924 - 0.008ms returns 0
+T2F54 001:692.931 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:692.939 - 0.010ms returns 0x00000024
+T2F54 001:692.947 JLINK_Go()
+T2F54 001:692.961   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:696.261 - 3.328ms
+T2F54 001:696.287 JLINK_IsHalted()
+T2F54 001:696.661 - 0.381ms returns FALSE
+T2F54 001:696.677 JLINK_HasError()
+T2F54 001:702.935 JLINK_IsHalted()
+T2F54 001:706.415   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:706.975 - 4.065ms returns TRUE
+T2F54 001:707.010 JLINK_ReadReg(R15 (PC))
+T2F54 001:707.025 - 0.018ms returns 0x20000000
+T2F54 001:707.033 JLINK_ClrBPEx(BPHandle = 0x00000024)
+T2F54 001:707.058 - 0.028ms returns 0x00
+T2F54 001:707.067 JLINK_ReadReg(R0)
+T2F54 001:707.073 - 0.009ms returns 0x00001000
+T2F54 001:707.997 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:708.022   Data:  C5 F8 6C 41 A2 F1 64 04 A1 F1 12 05 05 EB 85 05 ...
+T2F54 001:708.037   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:712.223 - 4.241ms returns 0x2F8
+T2F54 001:712.248 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:712.255   Data:  01 D9 01 24 00 E0 14 46 A1 F1 10 05 6D 00 AC 40 ...
+T2F54 001:712.273   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:717.804 - 5.573ms returns 0x400
+T2F54 001:717.837 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:717.845   Data:  13 68 C3 F3 08 00 08 60 03 F4 80 60 08 B1 02 20 ...
+T2F54 001:717.870   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:723.350 - 5.540ms returns 0x400
+T2F54 001:723.393 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:723.414   Data:  02 F0 2A F9 A8 46 F4 6C 2C B9 4F F4 89 72 1A 49 ...
+T2F54 001:723.453   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:728.805 - 5.427ms returns 0x400
+T2F54 001:728.854 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:728.861   Data:  70 BD 00 00 14 06 00 20 18 ED 00 E0 00 E4 00 E0 ...
+T2F54 001:728.888   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:730.666 - 1.833ms returns 0x108
+T2F54 001:730.702 JLINK_HasError()
+T2F54 001:730.715 JLINK_WriteReg(R0, 0x00001000)
+T2F54 001:730.726 - 0.014ms returns 0
+T2F54 001:730.733 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:730.740 - 0.009ms returns 0
+T2F54 001:730.748 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:730.754 - 0.009ms returns 0
+T2F54 001:730.822 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:730.834 - 0.015ms returns 0
+T2F54 001:730.842 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:730.848 - 0.009ms returns 0
+T2F54 001:730.856 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:730.862 - 0.009ms returns 0
+T2F54 001:730.870 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:730.876 - 0.009ms returns 0
+T2F54 001:730.883 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:730.889 - 0.008ms returns 0
+T2F54 001:730.896 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:730.905 - 0.012ms returns 0
+T2F54 001:730.913 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:730.919 - 0.009ms returns 0
+T2F54 001:730.927 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:730.933 - 0.009ms returns 0
+T2F54 001:730.941 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:730.947 - 0.009ms returns 0
+T2F54 001:730.955 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:730.961 - 0.009ms returns 0
+T2F54 001:730.969 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:730.977 - 0.011ms returns 0
+T2F54 001:730.985 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:730.991 - 0.009ms returns 0
+T2F54 001:730.999 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:731.006 - 0.010ms returns 0
+T2F54 001:731.014 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:731.021 - 0.010ms returns 0
+T2F54 001:731.030 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:731.041 - 0.015ms returns 0
+T2F54 001:731.050 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:731.057 - 0.009ms returns 0
+T2F54 001:731.065 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:731.071 - 0.009ms returns 0
+T2F54 001:731.080 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:731.090 - 0.014ms returns 0x00000025
+T2F54 001:731.100 JLINK_Go()
+T2F54 001:731.121   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:735.531 - 4.449ms
+T2F54 001:735.560 JLINK_IsHalted()
+T2F54 001:738.824   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:739.208 - 3.656ms returns TRUE
+T2F54 001:739.226 JLINK_ReadReg(R15 (PC))
+T2F54 001:739.236 - 0.013ms returns 0x20000000
+T2F54 001:739.244 JLINK_ClrBPEx(BPHandle = 0x00000025)
+T2F54 001:739.251 - 0.009ms returns 0x00
+T2F54 001:739.259 JLINK_ReadReg(R0)
+T2F54 001:739.279 - 0.022ms returns 0x00002000
+T2F54 001:740.270 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:740.283   Data:  0A 00 00 00 10 B5 02 A0 02 F0 34 FE 00 20 10 BD ...
+T2F54 001:740.300   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:744.560 - 4.299ms returns 0x2F8
+T2F54 001:744.594 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:744.601   Data:  04 F0 2A FC 00 20 E1 E7 54 95 00 00 7C 94 00 00 ...
+T2F54 001:744.635   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:750.216 - 5.639ms returns 0x400
+T2F54 001:750.244 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:750.254   Data:  0A 02 0E 49 09 68 B1 F8 08 12 88 42 59 DA 0B 4B ...
+T2F54 001:750.274   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:755.745 - 5.516ms returns 0x400
+T2F54 001:755.773 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:755.780   Data:  E0 69 23 46 08 22 41 46 CD E9 00 0A 21 A0 02 F0 ...
+T2F54 001:755.805   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:761.260 - 5.505ms returns 0x400
+T2F54 001:761.314 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:761.322   Data:  05 AA 19 46 0D A8 FF F7 5B FE 4F F0 08 0A 5A 46 ...
+T2F54 001:761.341   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:763.279 - 1.980ms returns 0x108
+T2F54 001:763.330 JLINK_HasError()
+T2F54 001:763.341 JLINK_WriteReg(R0, 0x00002000)
+T2F54 001:763.362 - 0.024ms returns 0
+T2F54 001:763.373 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:763.381 - 0.010ms returns 0
+T2F54 001:763.502 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:763.517 - 0.018ms returns 0
+T2F54 001:763.526 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:763.533 - 0.009ms returns 0
+T2F54 001:763.540 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:763.547 - 0.009ms returns 0
+T2F54 001:763.555 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:763.561 - 0.009ms returns 0
+T2F54 001:763.568 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:763.574 - 0.009ms returns 0
+T2F54 001:763.582 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:763.588 - 0.008ms returns 0
+T2F54 001:763.595 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:763.601 - 0.008ms returns 0
+T2F54 001:763.609 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:763.615 - 0.008ms returns 0
+T2F54 001:763.623 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:763.629 - 0.009ms returns 0
+T2F54 001:763.638 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:763.644 - 0.009ms returns 0
+T2F54 001:763.652 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:763.658 - 0.009ms returns 0
+T2F54 001:763.666 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:763.673 - 0.009ms returns 0
+T2F54 001:763.681 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:763.688 - 0.009ms returns 0
+T2F54 001:763.696 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:763.702 - 0.009ms returns 0
+T2F54 001:763.711 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:763.717 - 0.010ms returns 0
+T2F54 001:763.725 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:763.731 - 0.009ms returns 0
+T2F54 001:763.739 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:763.746 - 0.009ms returns 0
+T2F54 001:763.754 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:763.760 - 0.009ms returns 0
+T2F54 001:763.768 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:763.779 - 0.014ms returns 0x00000026
+T2F54 001:763.788 JLINK_Go()
+T2F54 001:763.802   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:767.611 - 3.839ms
+T2F54 001:767.657 JLINK_IsHalted()
+T2F54 001:770.735   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:771.171 - 3.521ms returns TRUE
+T2F54 001:771.186 JLINK_ReadReg(R15 (PC))
+T2F54 001:771.195 - 0.016ms returns 0x20000000
+T2F54 001:771.210 JLINK_ClrBPEx(BPHandle = 0x00000026)
+T2F54 001:771.217 - 0.009ms returns 0x00
+T2F54 001:771.225 JLINK_ReadReg(R0)
+T2F54 001:771.231 - 0.009ms returns 0x00003000
+T2F54 001:771.960 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:771.971   Data:  20 2D 2D 2D 2D 20 20 2D 2D 2D 2D 20 20 2D 2D 2D ...
+T2F54 001:771.987   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:776.443 - 4.492ms returns 0x2F8
+T2F54 001:776.460 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:776.467   Data:  FC F7 9C FF 83 46 30 7A 20 F0 80 00 9D F8 30 10 ...
+T2F54 001:776.481   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:782.023 - 5.600ms returns 0x400
+T2F54 001:782.071 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:782.078   Data:  76 61 74 65 64 0A 00 00 64 65 61 63 74 69 76 61 ...
+T2F54 001:782.107   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:787.598 - 5.559ms returns 0x400
+T2F54 001:787.645 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:787.652   Data:  48 F8 27 40 7F 1C 01 E0 64 1C 6D 1C 20 78 20 28 ...
+T2F54 001:787.670   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:793.539 - 5.912ms returns 0x400
+T2F54 001:793.573 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:793.581   Data:  08 60 00 BF 00 BF FC F7 99 F9 80 46 00 F0 8C FE ...
+T2F54 001:793.600   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:795.530 - 1.974ms returns 0x108
+T2F54 001:795.565 JLINK_HasError()
+T2F54 001:795.576 JLINK_WriteReg(R0, 0x00003000)
+T2F54 001:795.587 - 0.015ms returns 0
+T2F54 001:795.596 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:795.602 - 0.009ms returns 0
+T2F54 001:795.610 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:795.616 - 0.009ms returns 0
+T2F54 001:795.624 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:795.630 - 0.009ms returns 0
+T2F54 001:795.640 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:795.647 - 0.009ms returns 0
+T2F54 001:795.654 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:795.661 - 0.009ms returns 0
+T2F54 001:795.668 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:795.674 - 0.009ms returns 0
+T2F54 001:795.682 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:795.688 - 0.009ms returns 0
+T2F54 001:795.791 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:795.806 - 0.018ms returns 0
+T2F54 001:795.815 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:795.822 - 0.009ms returns 0
+T2F54 001:795.830 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:795.836 - 0.009ms returns 0
+T2F54 001:795.844 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:795.850 - 0.009ms returns 0
+T2F54 001:795.858 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:795.864 - 0.009ms returns 0
+T2F54 001:795.872 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:795.880 - 0.010ms returns 0
+T2F54 001:795.887 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:795.893 - 0.009ms returns 0
+T2F54 001:795.901 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:795.907 - 0.009ms returns 0
+T2F54 001:795.915 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:795.921 - 0.009ms returns 0
+T2F54 001:795.929 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:795.935 - 0.009ms returns 0
+T2F54 001:795.943 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:795.949 - 0.009ms returns 0
+T2F54 001:795.956 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:795.962 - 0.009ms returns 0
+T2F54 001:795.970 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:795.978 - 0.011ms returns 0x00000027
+T2F54 001:795.986 JLINK_Go()
+T2F54 001:796.001   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:799.425 - 3.484ms
+T2F54 001:799.483 JLINK_IsHalted()
+T2F54 001:799.916 - 0.443ms returns FALSE
+T2F54 001:799.935 JLINK_HasError()
+T2F54 001:805.530 JLINK_IsHalted()
+T2F54 001:808.764   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:809.217 - 3.695ms returns TRUE
+T2F54 001:809.233 JLINK_ReadReg(R15 (PC))
+T2F54 001:809.242 - 0.012ms returns 0x20000000
+T2F54 001:809.250 JLINK_ClrBPEx(BPHandle = 0x00000027)
+T2F54 001:809.257 - 0.009ms returns 0x00
+T2F54 001:809.264 JLINK_ReadReg(R0)
+T2F54 001:809.271 - 0.009ms returns 0x00004000
+T2F54 001:809.832 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:809.843   Data:  80 47 24 1D 02 48 84 42 F9 D3 10 BD 6C 94 00 00 ...
+T2F54 001:809.857   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:814.221 - 4.406ms returns 0x2F8
+T2F54 001:814.248 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:814.255   Data:  64 65 20 69 73 20 25 64 0A 00 00 00 64 65 76 2D ...
+T2F54 001:814.274   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:819.712 - 5.492ms returns 0x400
+T2F54 001:819.750 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:819.776   Data:  0C 00 00 20 70 73 72 3A 20 30 78 25 30 38 78 0A ...
+T2F54 001:819.793   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:825.565 - 5.832ms returns 0x400
+T2F54 001:825.599 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:825.607   Data:  01 EB C4 01 1F 4A 42 F8 31 00 1F 49 04 EB 44 00 ...
+T2F54 001:825.626   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:831.130 - 5.548ms returns 0x400
+T2F54 001:831.187 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:831.194   Data:  FE F7 2A FF 20 46 00 F0 C9 FC 07 28 04 D0 BD 22 ...
+T2F54 001:831.214   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:833.073 - 1.894ms returns 0x108
+T2F54 001:833.097 JLINK_HasError()
+T2F54 001:833.140 JLINK_WriteReg(R0, 0x00004000)
+T2F54 001:833.154 - 0.017ms returns 0
+T2F54 001:833.281 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:833.310 - 0.032ms returns 0
+T2F54 001:833.319 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:833.345 - 0.028ms returns 0
+T2F54 001:833.353 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:833.359 - 0.009ms returns 0
+T2F54 001:833.367 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:833.373 - 0.009ms returns 0
+T2F54 001:833.380 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:833.387 - 0.009ms returns 0
+T2F54 001:833.394 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:833.414 - 0.022ms returns 0
+T2F54 001:833.440 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:833.446 - 0.009ms returns 0
+T2F54 001:833.454 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:833.465 - 0.013ms returns 0
+T2F54 001:833.473 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:833.479 - 0.009ms returns 0
+T2F54 001:833.487 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:833.506 - 0.022ms returns 0
+T2F54 001:833.533 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:833.539 - 0.009ms returns 0
+T2F54 001:833.547 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:833.566 - 0.022ms returns 0
+T2F54 001:833.588 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:833.595 - 0.010ms returns 0
+T2F54 001:833.602 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:833.622 - 0.022ms returns 0
+T2F54 001:833.630 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:833.655 - 0.028ms returns 0
+T2F54 001:833.663 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:833.669 - 0.009ms returns 0
+T2F54 001:833.690 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:833.710 - 0.022ms returns 0
+T2F54 001:833.717 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:833.723 - 0.009ms returns 0
+T2F54 001:833.731 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:833.751 - 0.022ms returns 0
+T2F54 001:833.777 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:833.785 - 0.011ms returns 0x00000028
+T2F54 001:833.807 JLINK_Go()
+T2F54 001:833.833   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:837.178 - 3.378ms
+T2F54 001:837.194 JLINK_IsHalted()
+T2F54 001:837.518 - 0.332ms returns FALSE
+T2F54 001:837.535 JLINK_HasError()
+T2F54 001:842.915 JLINK_IsHalted()
+T2F54 001:846.130   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:846.599 - 3.696ms returns TRUE
+T2F54 001:846.628 JLINK_ReadReg(R15 (PC))
+T2F54 001:846.650 - 0.026ms returns 0x20000000
+T2F54 001:846.664 JLINK_ClrBPEx(BPHandle = 0x00000028)
+T2F54 001:846.675 - 0.016ms returns 0x00
+T2F54 001:846.689 JLINK_ReadReg(R0)
+T2F54 001:846.700 - 0.016ms returns 0x00005000
+T2F54 001:848.964 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:848.996   Data:  28 61 68 61 1F 48 40 1C 28 60 04 F1 44 00 00 F0 ...
+T2F54 001:849.018   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:853.227 - 4.278ms returns 0x2F8
+T2F54 001:853.253 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:853.260   Data:  08 61 B9 F1 00 0F 0B D0 A8 6A 00 69 20 61 A8 6A ...
+T2F54 001:853.278   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:858.846 - 5.629ms returns 0x400
+T2F54 001:858.899 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:858.908   Data:  00 20 20 72 FA F7 9A FD 05 46 04 F1 0C 00 FF F7 ...
+T2F54 001:858.929   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:864.479 - 5.614ms returns 0x400
+T2F54 001:864.551 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:864.576   Data:  28 46 00 F0 57 F8 20 46 00 F0 A2 F8 94 F8 34 00 ...
+T2F54 001:864.628   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:870.177 - 5.636ms returns 0x400
+T2F54 001:870.200 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:870.208   Data:  88 47 00 BF 00 20 A3 E7 08 8A 00 00 73 65 6D 20 ...
+T2F54 001:870.224   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:872.047 - 1.863ms returns 0x108
+T2F54 001:872.082 JLINK_HasError()
+T2F54 001:872.185 JLINK_WriteReg(R0, 0x00005000)
+T2F54 001:872.204 - 0.022ms returns 0
+T2F54 001:872.213 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:872.220 - 0.009ms returns 0
+T2F54 001:872.228 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:872.238 - 0.015ms returns 0
+T2F54 001:872.248 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:872.255 - 0.009ms returns 0
+T2F54 001:872.263 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:872.269 - 0.009ms returns 0
+T2F54 001:872.276 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:872.283 - 0.009ms returns 0
+T2F54 001:872.290 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:872.296 - 0.009ms returns 0
+T2F54 001:872.304 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:872.310 - 0.009ms returns 0
+T2F54 001:872.318 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:872.324 - 0.009ms returns 0
+T2F54 001:872.331 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:872.338 - 0.009ms returns 0
+T2F54 001:872.345 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:872.351 - 0.009ms returns 0
+T2F54 001:872.359 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:872.365 - 0.009ms returns 0
+T2F54 001:872.373 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:872.379 - 0.009ms returns 0
+T2F54 001:872.387 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:872.393 - 0.009ms returns 0
+T2F54 001:872.401 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:872.407 - 0.009ms returns 0
+T2F54 001:872.415 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:872.421 - 0.009ms returns 0
+T2F54 001:872.429 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:872.435 - 0.009ms returns 0
+T2F54 001:872.442 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:872.449 - 0.009ms returns 0
+T2F54 001:872.456 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:872.462 - 0.009ms returns 0
+T2F54 001:872.470 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:872.476 - 0.009ms returns 0
+T2F54 001:872.484 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:872.492 - 0.011ms returns 0x00000029
+T2F54 001:872.501 JLINK_Go()
+T2F54 001:872.516   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:876.706 - 4.223ms
+T2F54 001:876.736 JLINK_IsHalted()
+T2F54 001:880.244   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:880.614 - 3.904ms returns TRUE
+T2F54 001:880.650 JLINK_ReadReg(R15 (PC))
+T2F54 001:880.660 - 0.013ms returns 0x20000000
+T2F54 001:880.669 JLINK_ClrBPEx(BPHandle = 0x00000029)
+T2F54 001:880.676 - 0.009ms returns 0x00
+T2F54 001:880.684 JLINK_ReadReg(R0)
+T2F54 001:880.707 - 0.025ms returns 0x00006000
+T2F54 001:881.701 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:881.729   Data:  48 72 0B 49 14 A0 FD F7 A3 FE 30 46 FE F7 E8 FA ...
+T2F54 001:881.762   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:885.962 - 4.294ms returns 0x2F8
+T2F54 001:886.009 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:886.016   Data:  2C B9 4F F4 52 72 0C 49 0C A0 FD F7 25 FD 15 B9 ...
+T2F54 001:886.034   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:891.807 - 5.815ms returns 0x400
+T2F54 001:891.836 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:891.843   Data:  48 46 E8 E7 10 B5 00 22 0A 49 08 68 88 42 0E D0 ...
+T2F54 001:891.863   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:897.375 - 5.556ms returns 0x400
+T2F54 001:897.426 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:897.434   Data:  FD F7 2A F9 F9 F7 9A FB 05 46 20 46 00 F0 86 F8 ...
+T2F54 001:897.453   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:903.304 - 5.894ms returns 0x400
+T2F54 001:903.338 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:903.346   Data:  05 E0 00 BF 05 48 FD F7 12 FF 00 28 AB D0 00 BF ...
+T2F54 001:903.366   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:905.629 - 2.308ms returns 0x108
+T2F54 001:905.664 JLINK_HasError()
+T2F54 001:905.674 JLINK_WriteReg(R0, 0x00006000)
+T2F54 001:905.686 - 0.015ms returns 0
+T2F54 001:905.695 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:905.702 - 0.009ms returns 0
+T2F54 001:905.710 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:905.716 - 0.009ms returns 0
+T2F54 001:905.729 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:905.736 - 0.009ms returns 0
+T2F54 001:905.745 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:905.751 - 0.009ms returns 0
+T2F54 001:905.761 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:905.767 - 0.009ms returns 0
+T2F54 001:905.776 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:905.782 - 0.008ms returns 0
+T2F54 001:905.800 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:905.809 - 0.011ms returns 0
+T2F54 001:905.816 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:905.823 - 0.009ms returns 0
+T2F54 001:905.830 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:905.836 - 0.008ms returns 0
+T2F54 001:905.844 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:905.850 - 0.009ms returns 0
+T2F54 001:905.857 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:905.863 - 0.009ms returns 0
+T2F54 001:905.874 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:905.880 - 0.009ms returns 0
+T2F54 001:905.888 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:905.895 - 0.009ms returns 0
+T2F54 001:905.904 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:905.910 - 0.009ms returns 0
+T2F54 001:905.918 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:905.924 - 0.009ms returns 0
+T2F54 001:905.932 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:905.938 - 0.008ms returns 0
+T2F54 001:905.945 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:905.951 - 0.009ms returns 0
+T2F54 001:905.959 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:905.965 - 0.008ms returns 0
+T2F54 001:905.975 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:905.981 - 0.009ms returns 0
+T2F54 001:905.991 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:905.999 - 0.010ms returns 0x0000002A
+T2F54 001:906.009 JLINK_Go()
+T2F54 001:906.023   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:909.965 - 3.973ms
+T2F54 001:910.031 JLINK_IsHalted()
+T2F54 001:913.140   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:913.544 - 3.522ms returns TRUE
+T2F54 001:913.583 JLINK_ReadReg(R15 (PC))
+T2F54 001:913.594 - 0.014ms returns 0x20000000
+T2F54 001:913.605 JLINK_ClrBPEx(BPHandle = 0x0000002A)
+T2F54 001:913.612 - 0.010ms returns 0x00
+T2F54 001:913.625 JLINK_ReadReg(R0)
+T2F54 001:913.632 - 0.009ms returns 0x00007000
+T2F54 001:914.591 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:914.608   Data:  2C B9 4F F4 86 72 15 49 15 A0 FC F7 A1 FE 20 46 ...
+T2F54 001:914.627   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:918.972 - 4.391ms returns 0x2F8
+T2F54 001:918.991 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:918.998   Data:  F5 12 17 49 17 A0 FC F7 27 FD 20 46 FE F7 C6 FA ...
+T2F54 001:919.013   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:924.846 - 5.877ms returns 0x400
+T2F54 001:924.880 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:924.940   Data:  4F F0 FF 31 28 46 02 9B FF F7 56 FE 3E BD 00 20 ...
+T2F54 001:924.992   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:930.470 - 5.613ms returns 0x400
+T2F54 001:930.504 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:930.511   Data:  9D FE 04 46 14 B9 06 20 BD E8 F8 83 01 2E 6D D1 ...
+T2F54 001:930.530   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:936.047 - 5.560ms returns 0x400
+T2F54 001:936.075 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:936.082   Data:  69 67 75 72 65 20 21 3D 20 52 54 5F 4E 55 4C 4C ...
+T2F54 001:936.100   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:938.260 - 2.202ms returns 0x108
+T2F54 001:938.293 JLINK_HasError()
+T2F54 001:938.303 JLINK_WriteReg(R0, 0x00007000)
+T2F54 001:938.315 - 0.014ms returns 0
+T2F54 001:938.323 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:938.330 - 0.009ms returns 0
+T2F54 001:938.429 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:938.447 - 0.021ms returns 0
+T2F54 001:938.456 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:938.463 - 0.009ms returns 0
+T2F54 001:938.470 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:938.477 - 0.009ms returns 0
+T2F54 001:938.484 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:938.490 - 0.008ms returns 0
+T2F54 001:938.498 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:938.504 - 0.008ms returns 0
+T2F54 001:938.511 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:938.517 - 0.008ms returns 0
+T2F54 001:938.524 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:938.531 - 0.009ms returns 0
+T2F54 001:938.538 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:938.544 - 0.008ms returns 0
+T2F54 001:938.552 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:938.557 - 0.008ms returns 0
+T2F54 001:938.565 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:938.575 - 0.014ms returns 0
+T2F54 001:938.584 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:938.590 - 0.008ms returns 0
+T2F54 001:938.598 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:938.605 - 0.044ms returns 0
+T2F54 001:938.648 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:938.654 - 0.009ms returns 0
+T2F54 001:938.662 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:938.668 - 0.009ms returns 0
+T2F54 001:938.675 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:938.681 - 0.009ms returns 0
+T2F54 001:938.689 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:938.695 - 0.008ms returns 0
+T2F54 001:938.702 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:938.708 - 0.008ms returns 0
+T2F54 001:938.716 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:938.722 - 0.008ms returns 0
+T2F54 001:938.730 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:938.738 - 0.011ms returns 0x0000002B
+T2F54 001:938.746 JLINK_Go()
+T2F54 001:938.760   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:942.329 - 3.608ms
+T2F54 001:942.364 JLINK_IsHalted()
+T2F54 001:945.533   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:945.895 - 3.565ms returns TRUE
+T2F54 001:945.939 JLINK_ReadReg(R15 (PC))
+T2F54 001:945.950 - 0.013ms returns 0x20000000
+T2F54 001:945.959 JLINK_ClrBPEx(BPHandle = 0x0000002B)
+T2F54 001:945.966 - 0.010ms returns 0x00
+T2F54 001:945.987 JLINK_ReadReg(R0)
+T2F54 001:945.994 - 0.009ms returns 0x00008000
+T2F54 001:948.010 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:948.029   Data:  5F 55 46 53 52 3A 30 78 25 30 32 58 20 00 00 00 ...
+T2F54 001:948.050   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:952.241 - 4.247ms returns 0x2F8
+T2F54 001:952.267 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:952.274   Data:  04 00 00 00 34 00 00 00 12 00 00 00 00 20 01 40 ...
+T2F54 001:952.297   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:957.706 - 5.450ms returns 0x400
+T2F54 001:957.726 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:957.734   Data:  05 00 00 00 38 00 00 00 52 00 00 00 00 80 01 40 ...
+T2F54 001:957.750   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:963.098 - 5.408ms returns 0x400
+T2F54 001:963.145 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:963.152   Data:  76 00 72 74 5F 65 76 65 6E 74 5F 63 6F 6E 74 72 ...
+T2F54 001:963.172   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 001:968.771 - 5.651ms returns 0x400
+T2F54 001:968.832 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 001:968.853   Data:  61 63 6B 5F 63 68 65 63 6B 00 72 74 5F 73 63 68 ...
+T2F54 001:968.874   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 001:971.105 - 2.304ms returns 0x108
+T2F54 001:971.173 JLINK_HasError()
+T2F54 001:971.197 JLINK_WriteReg(R0, 0x00008000)
+T2F54 001:971.228 - 0.042ms returns 0
+T2F54 001:971.255 JLINK_WriteReg(R1, 0x00001000)
+T2F54 001:971.270 - 0.021ms returns 0
+T2F54 001:971.289 JLINK_WriteReg(R2, 0x20000108)
+T2F54 001:971.307 - 0.029ms returns 0
+T2F54 001:971.330 JLINK_WriteReg(R3, 0x00000000)
+T2F54 001:971.341 - 0.014ms returns 0
+T2F54 001:971.353 JLINK_WriteReg(R4, 0x00000000)
+T2F54 001:971.361 - 0.012ms returns 0
+T2F54 001:971.373 JLINK_WriteReg(R5, 0x00000000)
+T2F54 001:971.381 - 0.011ms returns 0
+T2F54 001:971.512 JLINK_WriteReg(R6, 0x00000000)
+T2F54 001:971.549 - 0.040ms returns 0
+T2F54 001:971.573 JLINK_WriteReg(R7, 0x00000000)
+T2F54 001:971.598 - 0.028ms returns 0
+T2F54 001:971.629 JLINK_WriteReg(R8, 0x00000000)
+T2F54 001:971.640 - 0.014ms returns 0
+T2F54 001:971.649 JLINK_WriteReg(R9, 0x20000104)
+T2F54 001:971.673 - 0.028ms returns 0
+T2F54 001:971.682 JLINK_WriteReg(R10, 0x00000000)
+T2F54 001:971.689 - 0.010ms returns 0
+T2F54 001:971.698 JLINK_WriteReg(R11, 0x00000000)
+T2F54 001:971.718 - 0.023ms returns 0
+T2F54 001:971.745 JLINK_WriteReg(R12, 0x00000000)
+T2F54 001:971.752 - 0.009ms returns 0
+T2F54 001:971.760 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 001:971.782 - 0.025ms returns 0
+T2F54 001:971.809 JLINK_WriteReg(R14, 0x20000001)
+T2F54 001:971.815 - 0.009ms returns 0
+T2F54 001:971.824 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 001:971.848 - 0.048ms returns 0
+T2F54 001:971.878 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 001:971.887 - 0.012ms returns 0
+T2F54 001:971.896 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 001:971.915 - 0.022ms returns 0
+T2F54 001:971.945 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 001:971.951 - 0.022ms returns 0
+T2F54 001:971.971 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 001:971.977 - 0.008ms returns 0
+T2F54 001:971.985 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 001:972.013 - 0.030ms returns 0x0000002C
+T2F54 001:972.021 JLINK_Go()
+T2F54 001:972.051   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 001:975.548 - 3.536ms
+T2F54 001:975.565 JLINK_IsHalted()
+T2F54 001:975.953 - 0.395ms returns FALSE
+T2F54 001:975.969 JLINK_HasError()
+T2F54 001:978.361 JLINK_IsHalted()
+T2F54 001:981.428   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 001:981.870 - 3.527ms returns TRUE
+T2F54 001:981.902 JLINK_ReadReg(R15 (PC))
+T2F54 001:981.919 - 0.020ms returns 0x20000000
+T2F54 001:981.929 JLINK_ClrBPEx(BPHandle = 0x0000002C)
+T2F54 001:981.935 - 0.009ms returns 0x00
+T2F54 001:981.943 JLINK_ReadReg(R0)
+T2F54 001:981.950 - 0.009ms returns 0x00009000
+T2F54 001:982.777 JLINK_WriteMem(0x20000108, 0x2F8 Bytes, ...)
+T2F54 001:982.793   Data:  4E 65 74 77 6F 72 6B 20 49 6E 74 65 72 66 61 63 ...
+T2F54 001:982.813   CPU_WriteMem(760 bytes @ 0x20000108)
+T2F54 001:987.240 - 4.488ms returns 0x2F8
+T2F54 001:987.289 JLINK_WriteMem(0x20000400, 0x400 Bytes, ...)
+T2F54 001:987.312   Data:  6C 69 73 74 20 65 76 65 6E 74 20 69 6E 20 73 79 ...
+T2F54 001:987.347   CPU_WriteMem(1024 bytes @ 0x20000400)
+T2F54 001:992.730 - 5.452ms returns 0x400
+T2F54 001:992.751 JLINK_WriteMem(0x20000800, 0x400 Bytes, ...)
+T2F54 001:992.758   Data:  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
+T2F54 001:992.772   CPU_WriteMem(1024 bytes @ 0x20000800)
+T2F54 001:998.311 - 5.576ms returns 0x400
+T2F54 001:998.344 JLINK_WriteMem(0x20000C00, 0x400 Bytes, ...)
+T2F54 001:998.352   Data:  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
+T2F54 001:998.371   CPU_WriteMem(1024 bytes @ 0x20000C00)
+T2F54 002:003.843 - 5.516ms returns 0x400
+T2F54 002:003.891 JLINK_WriteMem(0x20001000, 0x108 Bytes, ...)
+T2F54 002:003.923   Data:  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ...
+T2F54 002:003.946   CPU_WriteMem(264 bytes @ 0x20001000)
+T2F54 002:005.907 - 2.025ms returns 0x108
+T2F54 002:005.944 JLINK_HasError()
+T2F54 002:006.132 JLINK_WriteReg(R0, 0x00009000)
+T2F54 002:006.167 - 0.038ms returns 0
+T2F54 002:006.176 JLINK_WriteReg(R1, 0x000006C4)
+T2F54 002:006.183 - 0.009ms returns 0
+T2F54 002:006.212 JLINK_WriteReg(R2, 0x20000108)
+T2F54 002:006.233 - 0.024ms returns 0
+T2F54 002:006.241 JLINK_WriteReg(R3, 0x00000000)
+T2F54 002:006.263 - 0.025ms returns 0
+T2F54 002:006.271 JLINK_WriteReg(R4, 0x00000000)
+T2F54 002:006.296 - 0.027ms returns 0
+T2F54 002:006.303 JLINK_WriteReg(R5, 0x00000000)
+T2F54 002:006.310 - 0.009ms returns 0
+T2F54 002:006.331 JLINK_WriteReg(R6, 0x00000000)
+T2F54 002:006.337 - 0.022ms returns 0
+T2F54 002:006.358 JLINK_WriteReg(R7, 0x00000000)
+T2F54 002:006.381 - 0.025ms returns 0
+T2F54 002:006.388 JLINK_WriteReg(R8, 0x00000000)
+T2F54 002:006.394 - 0.027ms returns 0
+T2F54 002:006.421 JLINK_WriteReg(R9, 0x20000104)
+T2F54 002:006.427 - 0.009ms returns 0
+T2F54 002:006.435 JLINK_WriteReg(R10, 0x00000000)
+T2F54 002:006.454 - 0.022ms returns 0
+T2F54 002:006.462 JLINK_WriteReg(R11, 0x00000000)
+T2F54 002:006.482 - 0.022ms returns 0
+T2F54 002:006.489 JLINK_WriteReg(R12, 0x00000000)
+T2F54 002:006.512 - 0.025ms returns 0
+T2F54 002:006.519 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 002:006.545 - 0.029ms returns 0
+T2F54 002:006.553 JLINK_WriteReg(R14, 0x20000001)
+T2F54 002:006.559 - 0.009ms returns 0
+T2F54 002:006.567 JLINK_WriteReg(R15 (PC), 0x200000E0)
+T2F54 002:006.573 - 0.009ms returns 0
+T2F54 002:006.581 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 002:006.603 - 0.025ms returns 0
+T2F54 002:006.630 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 002:006.636 - 0.009ms returns 0
+T2F54 002:006.644 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 002:006.653 - 0.013ms returns 0
+T2F54 002:006.662 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 002:006.668 - 0.009ms returns 0
+T2F54 002:006.693 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 002:006.720 - 0.030ms returns 0x0000002D
+T2F54 002:006.728 JLINK_Go()
+T2F54 002:006.742   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 002:010.029 - 3.309ms
+T2F54 002:010.045 JLINK_IsHalted()
+T2F54 002:013.011   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 002:013.476 - 3.438ms returns TRUE
+T2F54 002:013.493 JLINK_ReadReg(R15 (PC))
+T2F54 002:013.502 - 0.012ms returns 0x20000000
+T2F54 002:013.511 JLINK_ClrBPEx(BPHandle = 0x0000002D)
+T2F54 002:013.517 - 0.009ms returns 0x00
+T2F54 002:013.527 JLINK_ReadReg(R0)
+T2F54 002:013.534 - 0.009ms returns 0x000096C4
+T2F54 002:014.168 JLINK_HasError()
+T2F54 002:014.186 JLINK_WriteReg(R0, 0x00000003)
+T2F54 002:014.196 - 0.013ms returns 0
+T2F54 002:014.204 JLINK_WriteReg(R1, 0x000006C4)
+T2F54 002:014.211 - 0.009ms returns 0
+T2F54 002:014.218 JLINK_WriteReg(R2, 0x20000108)
+T2F54 002:014.224 - 0.008ms returns 0
+T2F54 002:014.232 JLINK_WriteReg(R3, 0x00000000)
+T2F54 002:014.238 - 0.008ms returns 0
+T2F54 002:014.246 JLINK_WriteReg(R4, 0x00000000)
+T2F54 002:014.252 - 0.008ms returns 0
+T2F54 002:014.259 JLINK_WriteReg(R5, 0x00000000)
+T2F54 002:014.265 - 0.008ms returns 0
+T2F54 002:014.272 JLINK_WriteReg(R6, 0x00000000)
+T2F54 002:014.278 - 0.008ms returns 0
+T2F54 002:014.286 JLINK_WriteReg(R7, 0x00000000)
+T2F54 002:014.291 - 0.008ms returns 0
+T2F54 002:014.299 JLINK_WriteReg(R8, 0x00000000)
+T2F54 002:014.305 - 0.008ms returns 0
+T2F54 002:014.312 JLINK_WriteReg(R9, 0x20000104)
+T2F54 002:014.318 - 0.008ms returns 0
+T2F54 002:014.326 JLINK_WriteReg(R10, 0x00000000)
+T2F54 002:014.331 - 0.008ms returns 0
+T2F54 002:014.339 JLINK_WriteReg(R11, 0x00000000)
+T2F54 002:014.345 - 0.008ms returns 0
+T2F54 002:014.352 JLINK_WriteReg(R12, 0x00000000)
+T2F54 002:014.358 - 0.008ms returns 0
+T2F54 002:014.366 JLINK_WriteReg(R13 (SP), 0x20004000)
+T2F54 002:014.372 - 0.009ms returns 0
+T2F54 002:014.380 JLINK_WriteReg(R14, 0x20000001)
+T2F54 002:014.386 - 0.008ms returns 0
+T2F54 002:014.393 JLINK_WriteReg(R15 (PC), 0x20000044)
+T2F54 002:014.399 - 0.009ms returns 0
+T2F54 002:014.407 JLINK_WriteReg(XPSR, 0x01000000)
+T2F54 002:014.413 - 0.008ms returns 0
+T2F54 002:014.420 JLINK_WriteReg(MSP, 0x20004000)
+T2F54 002:014.426 - 0.008ms returns 0
+T2F54 002:014.433 JLINK_WriteReg(PSP, 0x20004000)
+T2F54 002:014.439 - 0.008ms returns 0
+T2F54 002:014.447 JLINK_WriteReg(CFBP, 0x00000000)
+T2F54 002:014.453 - 0.008ms returns 0
+T2F54 002:014.460 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2)
+T2F54 002:014.467 - 0.010ms returns 0x0000002E
+T2F54 002:014.475 JLINK_Go()
+T2F54 002:014.489   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 002:018.378 - 3.916ms
+T2F54 002:018.401 JLINK_IsHalted()
+T2F54 002:021.658   CPU_ReadMem(2 bytes @ 0x20000000)
+T2F54 002:022.035 - 3.641ms returns TRUE
+T2F54 002:022.052 JLINK_ReadReg(R15 (PC))
+T2F54 002:022.061 - 0.012ms returns 0x20000000
+T2F54 002:022.070 JLINK_ClrBPEx(BPHandle = 0x0000002E)
+T2F54 002:022.076 - 0.009ms returns 0x00
+T2F54 002:022.084 JLINK_ReadReg(R0)
+T2F54 002:022.091 - 0.009ms returns 0x00000000
+T2F54 002:078.749 JLINK_WriteMemEx(0x20000000, 0x00000002 Bytes, Flags = 0x02000000)
+T2F54 002:078.771   Data:  FE E7
+T2F54 002:078.812   CPU_WriteMem(2 bytes @ 0x20000000)
+T2F54 002:079.271 - 0.531ms returns 0x2
+T2F54 002:079.288 JLINK_HasError()
+T2F54 002:079.297 JLINK_HasError()
+T2F54 002:079.304 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL)
+T2F54 002:079.310 - 0.008ms returns JLINKARM_CM3_RESET_TYPE_NORMAL
+T2F54 002:079.318 JLINK_Reset()
+T2F54 002:079.337   CPU_WriteMem(4 bytes @ 0xE000EDF0)
+T2F54 002:079.757   CPU_WriteMem(4 bytes @ 0xE000EDFC)
+T2F54 002:086.859   Reset: Halt core after reset via DEMCR.VC_CORERESET.
+T2F54 002:091.524   Reset: Reset device via AIRCR.SYSRESETREQ.
+T2F54 002:091.553   CPU_WriteMem(4 bytes @ 0xE000ED0C)
+T2F54 002:144.847   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 002:145.254   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 002:145.646   CPU_WriteMem(4 bytes @ 0xE000EDF0)
+T2F54 002:146.062   CPU_WriteMem(4 bytes @ 0xE000EDFC)
+T2F54 002:152.126   CPU_ReadMem(4 bytes @ 0xE000EDF0)
+T2F54 002:156.120   CPU_WriteMem(4 bytes @ 0xE0002000)
+T2F54 002:156.709   CPU_ReadMem(4 bytes @ 0xE000EDFC)
+T2F54 002:157.372   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 002:157.958 - 78.646ms
+T2F54 002:157.978 JLINK_Go()
+T2F54 002:157.992   CPU_ReadMem(4 bytes @ 0xE0001000)
+T2F54 002:158.720   CPU_WriteMem(4 bytes @ 0xE0002008)
+T2F54 002:158.736   CPU_WriteMem(4 bytes @ 0xE000200C)
+T2F54 002:158.745   CPU_WriteMem(4 bytes @ 0xE0002010)
+T2F54 002:158.753   CPU_WriteMem(4 bytes @ 0xE0002014)
+T2F54 002:158.761   CPU_WriteMem(4 bytes @ 0xE0002018)
+T2F54 002:158.770   CPU_WriteMem(4 bytes @ 0xE000201C)
+T2F54 002:160.368   CPU_WriteMem(4 bytes @ 0xE0001004)
+T2F54 002:161.327 - 3.376ms
+T2F54 002:178.237 JLINK_Close()
+T2F54 002:178.722   CPU is running
+T2F54 002:178.775   CPU_WriteMem(4 bytes @ 0xE0002008)
+T2F54 002:179.118   CPU is running
+T2F54 002:179.147   CPU_WriteMem(4 bytes @ 0xE000200C)
+T2F54 002:179.540   CPU is running
+T2F54 002:179.554   CPU_WriteMem(4 bytes @ 0xE0002010)
+T2F54 002:179.941   CPU is running
+T2F54 002:179.954   CPU_WriteMem(4 bytes @ 0xE0002014)
+T2F54 002:180.335   CPU is running
+T2F54 002:180.349   CPU_WriteMem(4 bytes @ 0xE0002018)
+T2F54 002:180.732   CPU is running
+T2F54 002:180.749   CPU_WriteMem(4 bytes @ 0xE000201C)
+T2F54 002:217.960 - 39.744ms
+T2F54 002:217.987   
+T2F54 002:217.995   Closed

bsp/swm320/JLinkSettings.ini

@@ -0,0 +1,40 @@
+[BREAKPOINTS]
+ForceImpTypeAny = 0
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+MonModeVTableAddr = 0xFFFFFFFF
+MonModeDebug = 0
+MaxNumAPs = 0
+LowPowerHandlingMode = 0
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+EraseType = 0x00
+CacheExcludeSize = 0x00
+CacheExcludeAddr = 0x00
+MinNumBytesFlashDL = 0
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 1
+Device="Cortex-M4"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+RAMUsageLimit = 0x00
+[SWO]
+SWOLogFile=""
+[MEM]
+RdOverrideOrMask = 0x00
+RdOverrideAndMask = 0xFFFFFFFF
+RdOverrideAddr = 0xFFFFFFFF
+WrOverrideOrMask = 0x00
+WrOverrideAndMask = 0xFFFFFFFF
+WrOverrideAddr = 0xFFFFFFFF

bsp/swm320/README.md

@@ -119,7 +119,7 @@
 
 - 使用 Jlink 连接开发板到 PC （需要 Jlink 驱动）
 
-将串口 0 引脚为：`[PA2/PA3]`和 USB 转串口模块 P2 相连，串口配置方式为115200-N-8-1。
+将串口 1 引脚为：`[PC2/PC3]`和 USB 转串口模块 J11 相连，串口配置方式为115200-N-8-1。
 
 当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后，可以使用 ISP 的方式来烧写到设备中。
 

bsp/swm320/applications/main.c

@@ -10,7 +10,7 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
-#define LED_PIN 21
+#define LED_PIN 32
 
 int main(void)
 {
@@ -29,7 +29,7 @@ int main(void)
 }
 
 // #ifdef RT_USING_PIN
-// #define KEY1_PIN 25
+// #define KEY1_PIN 31
 // void key1_cb(void *args)
 // {
 //     rt_kprintf("key1 irq!\n");
@@ -46,7 +46,7 @@ int main(void)
 // #endif
 
 #ifdef RT_USING_ADC
-#define ADC_DEV_NAME "adc0"
+#define ADC_DEV_NAME "adc1"
 #define ADC_DEV_CHANNEL 0
 #define REFER_VOLTAGE 330
 #define CONVERT_BITS (1 << 12)
@@ -64,16 +64,15 @@ static int adc_vol_sample(int argc, char *argv[])
         return RT_ERROR;
     }
 
-    while (1)
-    {
-        ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
-        value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
-        rt_kprintf("the value is :%d,", value);
-        vol = value * REFER_VOLTAGE / CONVERT_BITS;
-        rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
-        rt_thread_mdelay(500);
-        ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
-    }
+    ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
+    
+    value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
+    rt_kprintf("the value is :%d,", value);
+    
+    vol = value * REFER_VOLTAGE / CONVERT_BITS;
+    rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
+    
+    ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
 
     return ret;
 }
@@ -143,17 +142,17 @@ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
 #endif
 
 #ifdef RT_USING_PWM
-#define PWM_DEV_NAME "pwm0" /* PWM???? */
-#define PWM_DEV_CHANNEL 0   /* PWM?? */
+#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */
+#define PWM_DEV_CHANNEL 0   /* PWM通道 */
 
-struct rt_device_pwm *pwm_dev; /* PWM???? */
+struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */
 
 static int pwm_sample(int argc, char *argv[])
 {
     rt_uint32_t period, pulse;
 
-    period = 500000; /* ???0.5ms,?????ns */
-    pulse = 250000;  /* PWM?????,?????ns */
+    period = 500000; /* 周期为0.5ms,单位为纳秒ns */
+    pulse = 250000;  /* PWM脉冲宽度值,单位为纳秒ns */
 
     pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
     if (pwm_dev == RT_NULL)
@@ -170,26 +169,27 @@ MSH_CMD_EXPORT(pwm_sample, pwm sample);
 #endif
 
 #ifdef RT_USING_RTC
+#include <time.h>
 static int rtc_sample(int argc, char *argv[])
 {
     rt_err_t ret = RT_EOK;
     time_t now;
 
-    ret = set_date(2020, 6, 15);
+    ret = set_date(2020, 2, 28);
     if (ret != RT_EOK)
     {
         rt_kprintf("set RTC date failed\n");
         return ret;
     }
 
-    ret = set_time(11, 15, 50);
+    ret = set_time(23, 59, 55);
     if (ret != RT_EOK)
     {
         rt_kprintf("set RTC time failed\n");
         return ret;
     }
 
-    rt_thread_mdelay(3000);
+    //rt_thread_mdelay(3000);
     now = time(RT_NULL);
     rt_kprintf("%s\n", ctime(&now));
 
@@ -205,7 +205,7 @@ static rt_device_t wdg_dev;
 
 static void idle_hook(void)
 {
-    rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL);
+    rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
     rt_kprintf("feed the dog!\n ");
 }
 
@@ -264,7 +264,7 @@ MSH_CMD_EXPORT(wdt_sample, wdt sample);
 
 static int rt_hw_spi_flash_init(void)
 {
-    rt_hw_spi_device_attach("spi0", "spi00", GPIOA, PIN12);
+    rt_hw_spi_device_attach("spi0", "spi00", GPIOP, PIN22);
 
     if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME))
     {
@@ -273,7 +273,6 @@ static int rt_hw_spi_flash_init(void)
 
     return RT_EOK;
 }
-/* ???????? */
 INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
 
 static void spi_w25q_sample(int argc, char *argv[])
@@ -292,12 +291,12 @@ static void spi_w25q_sample(int argc, char *argv[])
         rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX);
     }
 
-    /* ?? spi ???????? */
+    /* 查找 spi 设备获取设备句柄 */
     spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name);
     struct rt_spi_configuration cfg;
     cfg.data_width = 8;
     cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB;
-    cfg.max_hz = 20 * 1000 * 1000; /* 20M */
+    cfg.max_hz = 30 * 1000 * 1000; /* 20M */
 
     rt_spi_configure(spi_dev_w25q, &cfg);
     if (!spi_dev_w25q)
@@ -306,11 +305,11 @@ static void spi_w25q_sample(int argc, char *argv[])
     }
     else
     {
-        /* ??1:?? rt_spi_send_then_recv()??????ID */
+        /* 方式1：使用 rt_spi_send_then_recv()发送命令读取ID */
         rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5);
         rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]);
 
-        /* ??2:?? rt_spi_transfer_message()??????ID */
+        /* 方式2：使用 rt_spi_transfer_message()发送命令读取ID */
         struct rt_spi_message msg1, msg2;
 
         msg1.send_buf = &w25x_read_id;
@@ -352,7 +351,6 @@ static void spi_flash_elmfat_sample(void)
 
     rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
 
-    /* ????????????,??????????????*/
     fd = open("/user/test.txt", O_WRONLY | O_CREAT);
     if (fd >= 0)
     {
@@ -362,7 +360,6 @@ static void spi_flash_elmfat_sample(void)
         close(fd);
     }
 
-    /* ????????? */
     fd = open("/user/test.txt", O_RDONLY);
     if (fd >= 0)
     {
@@ -397,7 +394,7 @@ MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
 //{
 //    int fd, size;
 //    struct statfs elm_stat;
-//    char str[] = "elmfat mount to sdcard.\r\n", buf[80];
+//    char str[] = "elmfat mount to sdcard.", buf[80];
 
 //    if (dfs_mkfs("elm", SDCARD_NAME) == 0)
 //        rt_kprintf("make elmfat filesystem success.\n");

bsp/swm320/drivers/Kconfig

@@ -245,11 +245,11 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_SPI
         if BSP_USING_SPI
             config BSP_USING_SPI0
-                bool "Enable SPI0 BUS(CS/A12,MISO/A11,MOSI/A10,CLK/A9)"
+                bool "Enable SPI0 BUS(CS/P22,MISO/P19,MOSI/P18,CLK/P23)"
                 default n
 
             config BSP_USING_SPI1
-                bool "Enable SPI1 BUS(CS/C4,MISO/C5,MOSI/C6,CLK/C7)"
+                bool "Enable SPI1 BUS(CS/B6,MISO/B3,MOSI/B2,CLK/B1)"
                 default n
         endif
 

bsp/swm320/drivers/board.c

@@ -17,6 +17,7 @@ static void bsp_clock_config(void)
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
     SysTick->CTRL |= 0x00000004UL;
 }
+
 void SysTick_Handler(void)
 {
     /* enter interrupt */
@@ -28,6 +29,41 @@ void SysTick_Handler(void)
     rt_interrupt_leave();
 }
 
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
 void rt_hw_board_init()
 {
     bsp_clock_config();

bsp/swm320/drivers/drv_crypto.c

@@ -21,11 +21,6 @@ struct swm_hwcrypto_device
 
 #ifdef BSP_USING_CRC
 
-struct hash_ctx_des
-{
-    struct swm_crc_cfg contex;
-};
-
 static struct hwcrypto_crc_cfg crc_backup_cfg;
 
 static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
@@ -108,6 +103,7 @@ static const struct hwcrypto_crc_ops crc_ops =
     {
         .update = _crc_update,
 };
+#endif /* BSP_USING_CRC */
 
 static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
 {
@@ -170,7 +166,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
     case HWCRYPTO_TYPE_CRC:
         if (des->contex && src->contex)
         {
-            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+            rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg));
         }
         break;
 #endif /* BSP_USING_CRC */
@@ -226,5 +222,5 @@ int rt_hw_crypto_init(void)
 }
 INIT_BOARD_EXPORT(rt_hw_crypto_init);
 
-#endif /* BSP_USING_WDT */
-#endif /* RT_USING_WDT */
+
+#endif /* RT_USING_HWCRYPTO */

bsp/swm320/drivers/drv_gpio.c

@@ -475,6 +475,7 @@ static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
         }
     }
 }
+
 void GPIOA_Handler(void)
 {
     rt_interrupt_enter();

bsp/swm320/drivers/drv_rtc.c

@@ -10,6 +10,7 @@
  */
 
 #include "drv_rtc.h"
+#include <sys/time.h>
 
 #ifdef RT_USING_RTC
 #ifdef BSP_USING_RTC
@@ -18,8 +19,6 @@
 #define LOG_TAG "drv.rtc"
 #include <drv_log.h>
 
-static struct rt_device rtc_device;
-
 static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date)
 {
     uint32_t i, cnt = 0;
@@ -55,8 +54,8 @@ static time_t swm_get_rtc_time_stamp(void)
     tm_new.tm_min = get_datetime.Minute;
     tm_new.tm_hour = get_datetime.Hour;
     tm_new.tm_mday = get_datetime.Date;
-    tm_new.tm_mon = get_datetime.Month - 1;
-    tm_new.tm_year = get_datetime.Year - 1900;
+    tm_new.tm_mon = get_datetime.Month;
+    tm_new.tm_year = get_datetime.Year;
 
     LOG_D("get rtc time.");
     return mktime(&tm_new);
@@ -72,9 +71,9 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
     set_datetime.Minute = p_tm->tm_min;
     set_datetime.Hour = p_tm->tm_hour;
     set_datetime.Date = p_tm->tm_mday;
-    set_datetime.Month = p_tm->tm_mon + 1;
-    set_datetime.Year = p_tm->tm_year + 1900;
-    //    datetime.Day = p_tm->tm_wday;
+    set_datetime.Month = p_tm->tm_mon;
+    set_datetime.Year = p_tm->tm_year;
+    // set_datetime.Day = p_tm->tm_wday;
 
     RTC_Stop(RTC);
     while (RTC->CFGABLE == 0)
@@ -86,7 +85,7 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
     RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date)
                    << RTC_MONDAY_DAY_Pos) |
                   ((set_datetime.Month) << RTC_MONDAY_MON_Pos);
-    RTC->YEAR = set_datetime.Year - 1901;
+    RTC->YEAR = set_datetime.Year;
     RTC->LOAD = 1 << RTC_LOAD_TIME_Pos;
     RTC_Start(RTC);
 
@@ -94,43 +93,7 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
     return RT_EOK;
 }
 
-static rt_err_t swm_rtc_control(rt_device_t rtc_device, int cmd, void *args)
-{
-    rt_err_t result = RT_EOK;
-    RT_ASSERT(rtc_device != RT_NULL);
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_RTC_GET_TIME:
-        *(rt_uint32_t *)args = swm_get_rtc_time_stamp();
-        LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
-        break;
-    case RT_DEVICE_CTRL_RTC_SET_TIME:
-        if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
-        {
-            result = -RT_ERROR;
-        }
-        LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
-        break;
-    default:
-        break;
-    }
-
-    return result;
-}
-
-#ifdef RT_USING_DEVICE_OPS
-const static struct rt_device_ops swm_rtc_ops =
-    {
-        RT_NULL,
-        RT_NULL,
-        RT_NULL,
-        RT_NULL,
-        RT_NULL,
-        swm_rtc_control};
-#endif
-
-static void swm_rtc_init(void)
+static rt_err_t swm_rtc_init(void)
 {
     RTC_InitStructure rtc_initstruct;
 
@@ -144,37 +107,50 @@ static void swm_rtc_init(void)
     rtc_initstruct.MinuteIEn = 0;
     RTC_Init(RTC, &rtc_initstruct);
     RTC_Start(RTC);
+    
+    return RT_EOK;
+}
+
+static rt_err_t swm_rtc_get_secs(void *args)
+{
+    *(rt_uint32_t *)args = swm_get_rtc_time_stamp();
+    LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+
+    return RT_EOK;
 }
 
-static rt_err_t rt_hw_rtc_register(rt_device_t rtc_device, const char *name, rt_uint32_t flag)
+static rt_err_t swm_rtc_set_secs(void *args)
 {
-    RT_ASSERT(rtc_device != RT_NULL);
-
-    swm_rtc_init();
-
-#ifdef RT_USING_DEVICE_OPS
-    rtc_device->ops = &swm_rtc_ops;
-#else
-    rtc_device->init = RT_NULL;
-    rtc_device->open = RT_NULL;
-    rtc_device->close = RT_NULL;
-    rtc_device->read = RT_NULL;
-    rtc_device->write = RT_NULL;
-    rtc_device->control = swm_rtc_control;
-#endif
-    rtc_device->type = RT_Device_Class_RTC;
-    rtc_device->rx_indicate = RT_NULL;
-    rtc_device->tx_complete = RT_NULL;
-    rtc_device->user_data = RT_NULL;
-
-    /* register a character device */
-    return rt_device_register(rtc_device, name, flag);
+    rt_err_t result = RT_EOK;
+
+    if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
+    {
+        result = -RT_ERROR;
+    }
+    LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+
+    return result;
 }
 
+static const struct rt_rtc_ops swm_rtc_ops =
+{
+    swm_rtc_init,
+    swm_rtc_get_secs,
+    swm_rtc_set_secs,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+};
+
+static rt_rtc_dev_t swm_rtc_device;
+
 int rt_hw_rtc_init(void)
 {
     rt_err_t result;
-    result = rt_hw_rtc_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
+    
+    swm_rtc_device.ops = &swm_rtc_ops;
+    result = rt_hw_rtc_register(&swm_rtc_device, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL);
     if (result != RT_EOK)
     {
         LOG_E("rtc register err code: %d", result);

bsp/swm320/drivers/drv_sdio.c

@@ -47,7 +47,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
     SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
 
     if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
-                      rt_tick_from_millisecond(5000), &status) != RT_EOK)
+                      rt_tick_from_millisecond(1000), &status) != RT_EOK)
     {
         LOG_E("wait completed timeout");
         cmd->err = -RT_ETIMEOUT;

bsp/swm320/drivers/drv_spi.c

@@ -279,15 +279,15 @@ int rt_hw_spi_init(void)
     rt_err_t result;
 
 #ifdef BSP_USING_SPI0
-    PORT_Init(PORTA, PIN9, FUNMUX1_SPI0_SCLK, 0);
-    PORT_Init(PORTA, PIN10, FUNMUX0_SPI0_MOSI, 0);
-    PORT_Init(PORTA, PIN11, FUNMUX1_SPI0_MISO, 1);
+    PORT_Init(PORTP, PIN23, FUNMUX1_SPI0_SCLK, 0);
+    PORT_Init(PORTP, PIN18, FUNMUX0_SPI0_MOSI, 0);
+    PORT_Init(PORTP, PIN19, FUNMUX1_SPI0_MISO, 1);
 #endif //BSP_USING_SPI0
 
 #ifdef BSP_USING_SPI1
-    PORT_Init(PORTC, PIN7, FUNMUX1_SPI1_SCLK, 0);
-    PORT_Init(PORTC, PIN6, FUNMUX0_SPI1_MOSI, 0);
-    PORT_Init(PORTC, PIN5, FUNMUX1_SPI1_MISO, 1);
+    PORT_Init(PORTB, PIN1, FUNMUX1_SPI1_SCLK, 0);
+    PORT_Init(PORTB, PIN2, FUNMUX0_SPI1_MOSI, 0);
+    PORT_Init(PORTB, PIN3, FUNMUX1_SPI1_MISO, 1);
 #endif //BSP_USING_SPI1
     for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++)
     {

bsp/swm320/drivers/linker_scripts/link.lds

@@ -1,71 +1,137 @@
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Specify the memory areas */
+/* Program Entry, set to mark it as "used" and avoid gc */
 MEMORY
 {
-	ROM   (arx) : ORIGIN = 0x00000000,    LENGTH = 0x00080000 /* 512k */
-    RAM   (arw) : ORIGIN = 0x20000000,    LENGTH = 0x00020000 /* 128k */
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 1024KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  128k /* 128K sram */
 }
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
 
-/* Define output sections */
 SECTIONS
 {
-    . = ORIGIN(ROM);
     .text :
     {
-        KEEP(*(.isr_vector))
-
-        *(.text)
-        *(.text*)
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
         *(.rodata*)
-    } > ROM
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
 
-    . = ALIGN(4);
-    __data_load__ = LOADADDR(.data);
+    /* .data section which is used for initialized data */
 
-    . = ALIGN(4);
-    .data :
+    .data : AT (_sidata)
     {
-        __data_start__ = .;
-	    
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
         *(.data)
-        *(.data*)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
 
+    .stack : 
+    {
+        . = . + _system_stack_size;
         . = ALIGN(4);
-        __data_end__ = .;
-    } > RAM AT> ROM
+        _estack = .;
+    } >DATA
 
-    . = ALIGN(4);
+    __bss_start = .;
     .bss :
     {
-        __bss_start__ = .;
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
 
         *(.bss)
-        *(.bss*)
+        *(.bss.*)
         *(COMMON)
 
         . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-    . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
 
-    .heap :
-    {
-        end = .;
-        __HeapBase = .;
-
-        *(.heap)
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols.
-     * It is only used for linker to calculate size of stack sections */
-    .stack_dummy :
-    {
-        *(.stack)
-    } > RAM
+    _end = .;
 
-    __StackTop   = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
 }

bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h

@@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
 extern const float32_t twiddleCoef_rfft_2048[2048];
 extern const float32_t twiddleCoef_rfft_4096[4096];
 
-
 /* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
 #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
 #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
 #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
@@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG
 extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
 
 /* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
 #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
 #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
 

bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h

@@ -46,34 +46,34 @@
 #include "arm_math.h"
 #include "arm_common_tables.h"
 
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
 
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
 
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
 
 #endif

bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h

@@ -1,4 +1,4 @@
-/**************************************************************************//**
+/**************************************************************************/ /**
  * @file     core_cm0.h
  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
  * @version  V4.00
@@ -34,16 +34,16 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
 #endif
 
 #ifndef __CORE_CM0_H_GENERIC
 #define __CORE_CM0_H_GENERIC
 
 #ifdef __cplusplus
- extern "C" {
+extern "C"
+{
 #endif
 
 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
@@ -59,7 +59,6 @@
      Function-like macros are used to allow more efficient code.
  */
 
-
 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
@@ -68,85 +67,84 @@
  */
 
 /*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB (0x00)  /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                             __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core                    */
+
+#if defined(__CC_ARM)
+#define __ASM __asm       /*!< asm keyword for ARM Compiler          */
+#define __INLINE __inline /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__GNUC__)
+#define __ASM __asm     /*!< asm keyword for GNU Compiler          */
+#define __INLINE inline /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE static inline
+
+#elif defined(__ICCARM__)
+#define __ASM __asm     /*!< asm keyword for IAR Compiler          */
+#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TMS470__)
+#define __ASM __asm /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE static inline
+
+#elif defined(__TASKING__)
+#define __ASM __asm     /*!< asm keyword for TASKING Compiler      */
+#define __INLINE inline /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE static inline
+
+#elif defined(__CSMC__)
+#define __packed
+#define __ASM _asm      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE static inline
 
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
+#endif
 
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED 0
 
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
+#if defined(__CC_ARM)
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
+#elif defined(__GNUC__)
+#if defined(__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
+#elif defined(__ICCARM__)
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
+#elif defined(__TMS470__)
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 
+#elif defined(__TASKING__)
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 #endif
 
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
+#elif defined(__CSMC__) /* Cosmic */
+#if (__CSMC__ & 0x400)  // FPU present for parser
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
 #endif
 
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <stdint.h>       /* standard types definitions                      */
+#include <core_cmInstr.h> /* Core Instruction Access                         */
+#include <core_cmFunc.h>  /* Core Function Access                            */
 
 #ifdef __cplusplus
 }
@@ -160,25 +158,26 @@
 #define __CORE_CM0_H_DEPENDANT
 
 #ifdef __cplusplus
- extern "C" {
+extern "C"
+{
 #endif
 
 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
+#ifndef __CM0_REV
+#define __CM0_REV 0x0000
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
 #endif
 
 /* IO definitions (access restrictions to peripheral registers) */
@@ -190,18 +189,16 @@
     \li for automatic generation of peripheral register debug information.
 */
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#define __I volatile /*!< Defines 'read only' permissions                 */
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#define __I volatile const /*!< Defines 'read only' permissions                 */
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
+#define __O volatile  /*!< Defines 'write only' permissions                */
+#define __IO volatile /*!< Defines 'read / write' permissions              */
 
+    /*@} end of group Cortex_M0 */
 
-/*******************************************************************************
+    /*******************************************************************************
  *                 Register Abstraction
   Core Register contain:
   - Core Register
@@ -209,275 +206,268 @@
   - Core SCB Register
   - Core SysTick Register
  ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
+    /** \defgroup CMSIS_core_register Defines and Type Definitions
     \brief Type definitions and defines for Cortex-M processor based devices.
 */
 
-/** \ingroup    CMSIS_core_register
+    /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_CORE  Status and Control Registers
     \brief  Core Register type definitions.
   @{
  */
 
-/** \brief  Union type to access the Application Program Status Register (APSR).
+    /** \brief  Union type to access the Application Program Status Register (APSR).
  */
-typedef union
-{
-  struct
-  {
+    typedef union
+    {
+        struct
+        {
 #if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+            uint32_t _reserved0 : 27; /*!< bit:  0..26  Reserved                           */
 #else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+        uint32_t _reserved0 : 16; /*!< bit:  0..15  Reserved                           */
+        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1 : 7;  /*!< bit: 20..26  Reserved                           */
 #endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+            uint32_t Q : 1; /*!< bit:     27  Saturation condition flag          */
+            uint32_t V : 1; /*!< bit:     28  Overflow condition code flag       */
+            uint32_t C : 1; /*!< bit:     29  Carry condition code flag          */
+            uint32_t Z : 1; /*!< bit:     30  Zero condition code flag           */
+            uint32_t N : 1; /*!< bit:     31  Negative condition code flag       */
+        } b;                /*!< Structure used for bit  access                  */
+        uint32_t w;         /*!< Type      used for word access                  */
+    } APSR_Type;
+
+    /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
  */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+    typedef union
+    {
+        struct
+        {
+            uint32_t ISR : 9;         /*!< bit:  0.. 8  Exception number                   */
+            uint32_t _reserved0 : 23; /*!< bit:  9..31  Reserved                           */
+        } b;                          /*!< Structure used for bit  access                  */
+        uint32_t w;                   /*!< Type      used for word access                  */
+    } IPSR_Type;
+
+    /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
  */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    typedef union
+    {
+        struct
+        {
+            uint32_t ISR : 9; /*!< bit:  0.. 8  Exception number                   */
 #if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+            uint32_t _reserved0 : 15; /*!< bit:  9..23  Reserved                           */
 #else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+        uint32_t _reserved0 : 7;  /*!< bit:  9..15  Reserved                           */
+        uint32_t GE : 4;          /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1 : 4;  /*!< bit: 20..23  Reserved                           */
 #endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
+            uint32_t T : 1;  /*!< bit:     24  Thumb bit        (read 0)          */
+            uint32_t IT : 2; /*!< bit: 25..26  saved IT state   (read 0)          */
+            uint32_t Q : 1;  /*!< bit:     27  Saturation condition flag          */
+            uint32_t V : 1;  /*!< bit:     28  Overflow condition code flag       */
+            uint32_t C : 1;  /*!< bit:     29  Carry condition code flag          */
+            uint32_t Z : 1;  /*!< bit:     30  Zero condition code flag           */
+            uint32_t N : 1;  /*!< bit:     31  Negative condition code flag       */
+        } b;                 /*!< Structure used for bit  access                  */
+        uint32_t w;          /*!< Type      used for word access                  */
+    } xPSR_Type;
+
+    /** \brief  Union type to access the Control Registers (CONTROL).
  */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
+    typedef union
+    {
+        struct
+        {
+            uint32_t nPRIV : 1;       /*!< bit:      0  Execution privilege in Thread mode */
+            uint32_t SPSEL : 1;       /*!< bit:      1  Stack to be used                   */
+            uint32_t FPCA : 1;        /*!< bit:      2  FP extension active flag           */
+            uint32_t _reserved0 : 29; /*!< bit:  3..31  Reserved                           */
+        } b;                          /*!< Structure used for bit  access                  */
+        uint32_t w;                   /*!< Type      used for word access                  */
+    } CONTROL_Type;
+
+    /*@} end of group CMSIS_CORE */
+
+    /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
     \brief      Type definitions for the NVIC Registers
   @{
  */
 
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+    /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
  */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
+    typedef struct
+    {
+        __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+        uint32_t RESERVED0[31];
+        __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+        uint32_t RSERVED1[31];
+        __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+        uint32_t RESERVED2[31];
+        __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+        uint32_t RESERVED3[31];
+        uint32_t RESERVED4[64];
+        __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+    } NVIC_Type;
+
+    /*@} end of group CMSIS_NVIC */
+
+    /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SCB     System Control Block (SCB)
     \brief      Type definitions for the System Control Block Registers
   @{
  */
 
-/** \brief  Structure type to access the System Control Block (SCB).
+    /** \brief  Structure type to access the System Control Block (SCB).
  */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
+    typedef struct
+    {
+        __I uint32_t CPUID; /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+        __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+        uint32_t RESERVED0;
+        __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+        __IO uint32_t SCR;   /*!< Offset: 0x010 (R/W)  System Control Register                               */
+        __IO uint32_t CCR;   /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+        uint32_t RESERVED1;
+        __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+        __IO uint32_t SHCSR;  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    } SCB_Type;
 
 /* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+#define SCB_CPUID_IMPLEMENTER_Pos 24                                    /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
 
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+#define SCB_CPUID_VARIANT_Pos 20                               /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
 
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+#define SCB_CPUID_ARCHITECTURE_Pos 16                                    /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
 
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+#define SCB_CPUID_PARTNO_Pos 4                                 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
 
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Pos 0                                 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
 
 /* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+#define SCB_ICSR_NMIPENDSET_Pos 31                               /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
 
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+#define SCB_ICSR_PENDSVSET_Pos 28                              /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
 
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+#define SCB_ICSR_PENDSVCLR_Pos 27                              /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
 
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+#define SCB_ICSR_PENDSTSET_Pos 26                              /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
 
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+#define SCB_ICSR_PENDSTCLR_Pos 25                              /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
 
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+#define SCB_ICSR_ISRPREEMPT_Pos 23                               /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
 
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+#define SCB_ICSR_ISRPENDING_Pos 22                               /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
 
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+#define SCB_ICSR_VECTPENDING_Pos 12                                    /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
 
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Pos 0                                    /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
 
 /* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+#define SCB_AIRCR_VECTKEY_Pos 16                                  /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
 
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16                                      /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
 
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+#define SCB_AIRCR_ENDIANESS_Pos 15                               /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
 
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+#define SCB_AIRCR_SYSRESETREQ_Pos 2                                  /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
 
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1                                    /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
 
 /* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+#define SCB_SCR_SEVONPEND_Pos 4                              /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
 
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+#define SCB_SCR_SLEEPDEEP_Pos 2                              /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
 
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+#define SCB_SCR_SLEEPONEXIT_Pos 1                                /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
 
 /* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+#define SCB_CCR_STKALIGN_Pos 9                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
 
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+#define SCB_CCR_UNALIGN_TRP_Pos 3                                /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
 
 /* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15                                  /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
 
+    /*@} end of group CMSIS_SCB */
 
-/** \ingroup  CMSIS_core_register
+    /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
     \brief      Type definitions for the System Timer Registers.
   @{
  */
 
-/** \brief  Structure type to access the System Timer (SysTick).
+    /** \brief  Structure type to access the System Timer (SysTick).
  */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
+    typedef struct
+    {
+        __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+        __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+        __IO uint32_t VAL;  /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+        __I uint32_t CALIB; /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+    } SysTick_Type;
 
 /* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+#define SysTick_CTRL_COUNTFLAG_Pos 16                                  /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
 
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+#define SysTick_CTRL_CLKSOURCE_Pos 2                                   /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
 
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+#define SysTick_CTRL_TICKINT_Pos 1                                 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
 
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Pos 0                                /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
 
 /* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Pos 0                                       /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
 
 /* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Pos 0                                       /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
 
 /* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+#define SysTick_CALIB_NOREF_Pos 31                               /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
 
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+#define SysTick_CALIB_SKEW_Pos 30                              /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
 
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Pos 0                                       /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
 
 /*@} end of group CMSIS_SysTick */
 
-
 /** \ingroup  CMSIS_core_register
     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
     \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
@@ -487,7 +477,6 @@ typedef struct
  */
 /*@} end of group CMSIS_CoreDebug */
 
-
 /** \ingroup    CMSIS_core_register
     \defgroup   CMSIS_core_base     Core Definitions
     \brief      Definitions for base addresses, unions, and structures.
@@ -495,20 +484,17 @@ typedef struct
  */
 
 /* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define SCS_BASE (0xE000E000UL)            /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address              */
+#define NVIC_BASE (SCS_BASE + 0x0100UL)    /*!< NVIC Base Address                 */
+#define SCB_BASE (SCS_BASE + 0x0D00UL)     /*!< System Control Block Base Address */
 
+#define SCB ((SCB_Type *)SCB_BASE)             /*!< SCB configuration struct           */
+#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct       */
+#define NVIC ((NVIC_Type *)NVIC_BASE)          /*!< NVIC configuration struct          */
 
 /*@} */
 
-
-
 /*******************************************************************************
  *                Hardware Abstraction Layer
   Core Function Interface contains:
@@ -519,8 +505,6 @@ typedef struct
 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 */
 
-
-
 /* ##########################   NVIC functions  #################################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
@@ -530,36 +514,33 @@ typedef struct
 
 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
 /* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8)
+#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2))
+#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2))
 
-
-/** \brief  Enable External Interrupt
+    /** \brief  Enable External Interrupt
 
     The function enables a device-specific interrupt in the NVIC interrupt controller.
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
+    __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+    {
+        NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
+    }
 
-
-/** \brief  Disable External Interrupt
+    /** \brief  Disable External Interrupt
 
     The function disables a device-specific interrupt in the NVIC interrupt controller.
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
+    __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+    {
+        NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
+    }
 
-
-/** \brief  Get Pending Interrupt
+    /** \brief  Get Pending Interrupt
 
     The function reads the pending register in the NVIC and returns the pending bit
     for the specified interrupt.
@@ -569,37 +550,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
     \return             0  Interrupt status is not pending.
     \return             1  Interrupt status is pending.
  */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
+    __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+    {
+        return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0));
+    }
 
-
-/** \brief  Set Pending Interrupt
+    /** \brief  Set Pending Interrupt
 
     The function sets the pending bit of an external interrupt.
 
     \param [in]      IRQn  Interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
+    __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+    {
+        NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F));
+    }
 
-/** \brief  Clear Pending Interrupt
+    /** \brief  Clear Pending Interrupt
 
     The function clears the pending bit of an external interrupt.
 
     \param [in]      IRQn  External interrupt number. Value cannot be negative.
  */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
+    __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+    {
+        NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
+    }
 
-/** \brief  Set Interrupt Priority
+    /** \brief  Set Interrupt Priority
 
     The function sets the priority of an interrupt.
 
@@ -608,18 +586,21 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
     \param [in]      IRQn  Interrupt number.
     \param [in]  priority  Priority to set.
  */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
+    __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+    {
+        if (IRQn < 0)
+        {
+            SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                       (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+        }
+        else
+        {
+            NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                      (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+        }
+    }
+
+    /** \brief  Get Interrupt Priority
 
     The function reads the priority of an interrupt. The interrupt
     number can be positive to specify an external (device specific)
@@ -630,36 +611,38 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
     \return             Interrupt Priority. Value is aligned automatically to the implemented
                         priority bits of the microcontroller.
  */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
+    __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+    {
 
+        if (IRQn < 0)
+        {
+            return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+        } /* get priority for Cortex-M0 system interrupts */
+        else
+        {
+            return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+        } /* get priority for device specific interrupts  */
+    }
 
-/** \brief  System Reset
+    /** \brief  System Reset
 
     The function initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
+    __STATIC_INLINE void NVIC_SystemReset(void)
+    {
+        __DSB(); /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
+        SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                      SCB_AIRCR_SYSRESETREQ_Msk);
+        __DSB(); /* Ensure completion of memory access */
+        while (1)
+            ; /* wait until reset */
+    }
 
-/*@} end of CMSIS_Core_NVICFunctions */
+    /*@} end of CMSIS_Core_NVICFunctions */
 
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
+    /* ##################################    SysTick function  ############################################ */
+    /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
     \brief      Functions that configure the System.
   @{
@@ -667,7 +650,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
 
 #if (__Vendor_SysTickConfig == 0)
 
-/** \brief  System Tick Configuration
+    /** \brief  System Tick Configuration
 
     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
     Counter is in free running mode to generate periodic interrupts.
@@ -682,25 +665,23 @@ __STATIC_INLINE void NVIC_SystemReset(void)
     must contain a vendor-specific implementation of this function.
 
  */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
+    __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+    {
+        if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
+            return (1); /* Reload value impossible */
+
+        SysTick->LOAD = ticks - 1;                                   /* set reload register */
+        NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+        SysTick->VAL = 0;                                            /* Load the SysTick Counter Value */
+        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk |
+                        SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+        return (0);                              /* Function successful */
+    }
 
 #endif
 
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
+    /*@} end of CMSIS_Core_SysTickFunctions */
 
 #ifdef __cplusplus
 }

bsp/swm320/libraries/CMSIS/CoreSupport/core_cmFunc.h

@@ -1,4 +1,4 @@
-/**************************************************************************//**
+/**************************************************************************/ /**
  * @file     core_cmFunc.h
  * @brief    CMSIS Cortex-M Core Function Access Header File
  * @version  V4.00
@@ -34,22 +34,20 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #ifndef __CORE_CMFUNC_H
 #define __CORE_CMFUNC_H
 
-
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface
     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
   @{
  */
 
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
 #if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* intrinsic void __enable_irq();     */
@@ -63,11 +61,10 @@
  */
 __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
+    register uint32_t __regControl __ASM("control");
+    return (__regControl);
 }
 
-
 /** \brief  Set Control Register
 
     This function writes the given value to the Control Register.
@@ -76,11 +73,10 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
  */
 __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
+    register uint32_t __regControl __ASM("control");
+    __regControl = control;
 }
 
-
 /** \brief  Get IPSR Register
 
     This function returns the content of the IPSR Register.
@@ -89,11 +85,10 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
  */
 __STATIC_INLINE uint32_t __get_IPSR(void)
 {
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
+    register uint32_t __regIPSR __ASM("ipsr");
+    return (__regIPSR);
 }
 
-
 /** \brief  Get APSR Register
 
     This function returns the content of the APSR Register.
@@ -102,11 +97,10 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
  */
 __STATIC_INLINE uint32_t __get_APSR(void)
 {
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
+    register uint32_t __regAPSR __ASM("apsr");
+    return (__regAPSR);
 }
 
-
 /** \brief  Get xPSR Register
 
     This function returns the content of the xPSR Register.
@@ -115,11 +109,10 @@ __STATIC_INLINE uint32_t __get_APSR(void)
  */
 __STATIC_INLINE uint32_t __get_xPSR(void)
 {
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
+    register uint32_t __regXPSR __ASM("xpsr");
+    return (__regXPSR);
 }
 
-
 /** \brief  Get Process Stack Pointer
 
     This function returns the current value of the Process Stack Pointer (PSP).
@@ -128,11 +121,10 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
  */
 __STATIC_INLINE uint32_t __get_PSP(void)
 {
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
+    register uint32_t __regProcessStackPointer __ASM("psp");
+    return (__regProcessStackPointer);
 }
 
-
 /** \brief  Set Process Stack Pointer
 
     This function assigns the given value to the Process Stack Pointer (PSP).
@@ -141,11 +133,10 @@ __STATIC_INLINE uint32_t __get_PSP(void)
  */
 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
+    register uint32_t __regProcessStackPointer __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
 }
 
-
 /** \brief  Get Main Stack Pointer
 
     This function returns the current value of the Main Stack Pointer (MSP).
@@ -154,11 +145,10 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  */
 __STATIC_INLINE uint32_t __get_MSP(void)
 {
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
+    register uint32_t __regMainStackPointer __ASM("msp");
+    return (__regMainStackPointer);
 }
 
-
 /** \brief  Set Main Stack Pointer
 
     This function assigns the given value to the Main Stack Pointer (MSP).
@@ -167,11 +157,10 @@ __STATIC_INLINE uint32_t __get_MSP(void)
  */
 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
+    register uint32_t __regMainStackPointer __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
 }
 
-
 /** \brief  Get Priority Mask
 
     This function returns the current state of the priority mask bit from the Priority Mask Register.
@@ -180,11 +169,10 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  */
 __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
+    register uint32_t __regPriMask __ASM("primask");
+    return (__regPriMask);
 }
 
-
 /** \brief  Set Priority Mask
 
     This function assigns the given value to the Priority Mask Register.
@@ -193,28 +181,25 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
  */
 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
+    register uint32_t __regPriMask __ASM("primask");
+    __regPriMask = (priMask);
 }
 
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
 
 /** \brief  Enable FIQ
 
     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-#define __enable_fault_irq                __enable_fiq
-
+#define __enable_fault_irq __enable_fiq
 
 /** \brief  Disable FIQ
 
     This function disables FIQ interrupts by setting the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-#define __disable_fault_irq               __disable_fiq
-
+#define __disable_fault_irq __disable_fiq
 
 /** \brief  Get Base Priority
 
@@ -222,13 +207,12 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 
     \return               Base Priority register value
  */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
 {
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
+    register uint32_t __regBasePri __ASM("basepri");
+    return (__regBasePri);
 }
 
-
 /** \brief  Set Base Priority
 
     This function assigns the given value to the Base Priority register.
@@ -237,11 +221,10 @@ __STATIC_INLINE uint32_t  __get_BASEPRI(void)
  */
 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
 {
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
+    register uint32_t __regBasePri __ASM("basepri");
+    __regBasePri = (basePri & 0xff);
 }
 
-
 /** \brief  Get Fault Mask
 
     This function returns the current value of the Fault Mask register.
@@ -250,11 +233,10 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  */
 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
+    register uint32_t __regFaultMask __ASM("faultmask");
+    return (__regFaultMask);
 }
 
-
 /** \brief  Set Fault Mask
 
     This function assigns the given value to the Fault Mask register.
@@ -263,14 +245,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  */
 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
+    register uint32_t __regFaultMask __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1);
 }
 
 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
 
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
 
 /** \brief  Get FPSCR
 
@@ -281,14 +262,13 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
+    register uint32_t __regfpscr __ASM("fpscr");
+    return (__regfpscr);
 #else
-   return(0);
+    return (0);
 #endif
 }
 
-
 /** \brief  Set FPSCR
 
     This function assigns the given value to the Floating Point Status/Control register.
@@ -298,15 +278,14 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
+    register uint32_t __regfpscr __ASM("fpscr");
+    __regfpscr = (fpscr);
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
 
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /** \brief  Enable IRQ Interrupts
@@ -314,257 +293,277 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
   This function enables IRQ interrupts by clearing the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
 {
-  __ASM volatile ("cpsie i" : : : "memory");
+    __ASM volatile("cpsie i"
+                   :
+                   :
+                   : "memory");
 }
 
-
 /** \brief  Disable IRQ Interrupts
 
   This function disables IRQ interrupts by setting the I-bit in the CPSR.
   Can only be executed in Privileged modes.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
 {
-  __ASM volatile ("cpsid i" : : : "memory");
+    __ASM volatile("cpsid i"
+                   :
+                   :
+                   : "memory");
 }
 
-
 /** \brief  Get Control Register
 
     This function returns the content of the Control Register.
 
     \return               Control Register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, control"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Set Control Register
 
     This function writes the given value to the Control Register.
 
     \param [in]    control  Control Register value to set
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
 {
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+    __ASM volatile("MSR control, %0"
+                   :
+                   : "r"(control)
+                   : "memory");
 }
 
-
 /** \brief  Get IPSR Register
 
     This function returns the content of the IPSR Register.
 
     \return               IPSR Register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, ipsr"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Get APSR Register
 
     This function returns the content of the APSR Register.
 
     \return               APSR Register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, apsr"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Get xPSR Register
 
     This function returns the content of the xPSR Register.
 
     \return               xPSR Register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, xpsr"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Get Process Stack Pointer
 
     This function returns the current value of the Process Stack Pointer (PSP).
 
     \return               PSP Register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
 {
-  register uint32_t result;
+    register uint32_t result;
 
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, psp\n"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Set Process Stack Pointer
 
     This function assigns the given value to the Process Stack Pointer (PSP).
 
     \param [in]    topOfProcStack  Process Stack Pointer value to set
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
 {
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+    __ASM volatile("MSR psp, %0\n"
+                   :
+                   : "r"(topOfProcStack)
+                   : "sp");
 }
 
-
 /** \brief  Get Main Stack Pointer
 
     This function returns the current value of the Main Stack Pointer (MSP).
 
     \return               MSP Register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
 {
-  register uint32_t result;
+    register uint32_t result;
 
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, msp\n"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Set Main Stack Pointer
 
     This function assigns the given value to the Main Stack Pointer (MSP).
 
     \param [in]    topOfMainStack  Main Stack Pointer value to set
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
 {
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+    __ASM volatile("MSR msp, %0\n"
+                   :
+                   : "r"(topOfMainStack)
+                   : "sp");
 }
 
-
 /** \brief  Get Priority Mask
 
     This function returns the current state of the priority mask bit from the Priority Mask Register.
 
     \return               Priority Mask value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, primask"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Set Priority Mask
 
     This function assigns the given value to the Priority Mask Register.
 
     \param [in]    priMask  Priority Mask
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
 {
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+    __ASM volatile("MSR primask, %0"
+                   :
+                   : "r"(priMask)
+                   : "memory");
 }
 
-
-#if       (__CORTEX_M >= 0x03)
+#if (__CORTEX_M >= 0x03)
 
 /** \brief  Enable FIQ
 
     This function enables FIQ interrupts by clearing the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
 {
-  __ASM volatile ("cpsie f" : : : "memory");
+    __ASM volatile("cpsie f"
+                   :
+                   :
+                   : "memory");
 }
 
-
 /** \brief  Disable FIQ
 
     This function disables FIQ interrupts by setting the F-bit in the CPSR.
     Can only be executed in Privileged modes.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
 {
-  __ASM volatile ("cpsid f" : : : "memory");
+    __ASM volatile("cpsid f"
+                   :
+                   :
+                   : "memory");
 }
 
-
 /** \brief  Get Base Priority
 
     This function returns the current value of the Base Priority register.
 
     \return               Base Priority register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, basepri_max"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Set Base Priority
 
     This function assigns the given value to the Base Priority register.
 
     \param [in]    basePri  Base Priority value to set
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
 {
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+    __ASM volatile("MSR basepri, %0"
+                   :
+                   : "r"(value)
+                   : "memory");
 }
 
-
 /** \brief  Get Fault Mask
 
     This function returns the current value of the Fault Mask register.
 
     \return               Fault Mask register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
+    __ASM volatile("MRS %0, faultmask"
+                   : "=r"(result));
+    return (result);
 }
 
-
 /** \brief  Set Fault Mask
 
     This function assigns the given value to the Fault Mask register.
 
     \param [in]    faultMask  Fault Mask value to set
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
 {
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+    __ASM volatile("MSR faultmask, %0"
+                   :
+                   : "r"(faultMask)
+                   : "memory");
 }
 
 #endif /* (__CORTEX_M >= 0x03) */
 
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
 
 /** \brief  Get FPSCR
 
@@ -572,52 +571,52 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t
 
     \return               Floating Point Status/Control register value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
+    uint32_t result;
+
+    /* Empty asm statement works as a scheduling barrier */
+    __ASM volatile("");
+    __ASM volatile("VMRS %0, fpscr"
+                   : "=r"(result));
+    __ASM volatile("");
+    return (result);
 #else
-   return(0);
+    return (0);
 #endif
 }
 
-
 /** \brief  Set FPSCR
 
     This function assigns the given value to the Floating Point Status/Control register.
 
     \param [in]    fpscr  Floating Point Status/Control value to set
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 {
 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
+    /* Empty asm statement works as a scheduling barrier */
+    __ASM volatile("");
+    __ASM volatile("VMSR fpscr, %0"
+                   :
+                   : "r"(fpscr)
+                   : "vfpcc");
+    __ASM volatile("");
 #endif
 }
 
 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
 
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
@@ -625,8 +624,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
  * Including the CMSIS ones.
  */
 
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
 /* Cosmic specific functions */
 #include <cmsis_csm.h>
 

bsp/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h

@@ -1,4 +1,4 @@
-/**************************************************************************//**
+/**************************************************************************/ /**
  * @file     core_cmInstr.h
  * @brief    CMSIS Cortex-M Core Instruction Access Header File
  * @version  V4.00
@@ -34,54 +34,47 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
 #ifndef __CORE_CMINSTR_H
 #define __CORE_CMINSTR_H
 
-
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions
   @{
 */
 
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
 
 #if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 
-
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
  */
-#define __NOP                             __nop
-
+#define __NOP __nop
 
 /** \brief  Wait For Interrupt
 
     Wait For Interrupt is a hint instruction that suspends execution
     until one of a number of events occurs.
  */
-#define __WFI                             __wfi
-
+#define __WFI __wfi
 
 /** \brief  Wait For Event
 
     Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
-#define __WFE                             __wfe
-
+#define __WFE __wfe
 
 /** \brief  Send Event
 
     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
-#define __SEV                             __sev
-
+#define __SEV __sev
 
 /** \brief  Instruction Synchronization Barrier
 
@@ -89,24 +82,21 @@
     so that all instructions following the ISB are fetched from cache or
     memory, after the instruction has been completed.
  */
-#define __ISB()                           __isb(0xF)
-
+#define __ISB() __isb(0xF)
 
 /** \brief  Data Synchronization Barrier
 
     This function acts as a special kind of Data Memory Barrier.
     It completes when all explicit memory accesses before this instruction complete.
  */
-#define __DSB()                           __dsb(0xF)
-
+#define __DSB() __dsb(0xF)
 
 /** \brief  Data Memory Barrier
 
     This function ensures the apparent order of the explicit memory operations before
     and after the instruction, without ensuring their completion.
  */
-#define __DMB()                           __dmb(0xF)
-
+#define __DMB() __dmb(0xF)
 
 /** \brief  Reverse byte order (32 bit)
 
@@ -115,8 +105,7 @@
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#define __REV                             __rev
-
+#define __REV __rev
 
 /** \brief  Reverse byte order (16 bit)
 
@@ -128,8 +117,8 @@
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
 {
-  rev16 r0, r0
-  bx lr
+    rev16 r0, r0
+                  bx lr
 }
 #endif
 
@@ -143,12 +132,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
 {
-  revsh r0, r0
-  bx lr
+    revsh r0, r0
+                  bx lr
 }
 #endif
 
-
 /** \brief  Rotate Right in unsigned value (32 bit)
 
     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -157,8 +145,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  Number of Bits to rotate
     \return               Rotated value
  */
-#define __ROR                             __ror
-
+#define __ROR __ror
 
 /** \brief  Breakpoint
 
@@ -168,10 +155,9 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  is ignored by the processor.
                    If required, a debugger can use it to store additional information about the breakpoint.
  */
-#define __BKPT(value)                       __breakpoint(value)
+#define __BKPT(value) __breakpoint(value)
 
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
 
 /** \brief  Reverse bit order of value
 
@@ -180,8 +166,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-#define __RBIT                            __rbit
-
+#define __RBIT __rbit
 
 /** \brief  LDR Exclusive (8 bit)
 
@@ -190,8 +175,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
+#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
 
 /** \brief  LDR Exclusive (16 bit)
 
@@ -200,8 +184,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
+#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
 
 /** \brief  LDR Exclusive (32 bit)
 
@@ -210,8 +193,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
+#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
 
 /** \brief  STR Exclusive (8 bit)
 
@@ -222,8 +204,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \return          0  Function succeeded
     \return          1  Function failed
  */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
+#define __STREXB(value, ptr) __strex(value, ptr)
 
 /** \brief  STR Exclusive (16 bit)
 
@@ -234,8 +215,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \return          0  Function succeeded
     \return          1  Function failed
  */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
+#define __STREXH(value, ptr) __strex(value, ptr)
 
 /** \brief  STR Exclusive (32 bit)
 
@@ -246,16 +226,14 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \return          0  Function succeeded
     \return          1  Function failed
  */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
+#define __STREXW(value, ptr) __strex(value, ptr)
 
 /** \brief  Remove the exclusive lock
 
     This function removes the exclusive lock which is created by LDREX.
 
  */
-#define __CLREX                           __clrex
-
+#define __CLREX __clrex
 
 /** \brief  Signed Saturate
 
@@ -265,8 +243,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    sat  Bit position to saturate to (1..32)
     \return             Saturated value
  */
-#define __SSAT                            __ssat
-
+#define __SSAT __ssat
 
 /** \brief  Unsigned Saturate
 
@@ -276,8 +253,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]    sat  Bit position to saturate to (0..31)
     \return             Saturated value
  */
-#define __USAT                            __usat
-
+#define __USAT __usat
 
 /** \brief  Count leading zeros
 
@@ -286,8 +262,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
     \param [in]  value  Value to count the leading zeros
     \return             number of leading zeros in value
  */
-#define __CLZ                             __clz
-
+#define __CLZ __clz
 
 /** \brief  Rotate Right with Extend (32 bit)
 
@@ -299,12 +274,11 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
 #ifndef __NO_EMBEDDED_ASM
 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
 {
-  rrx r0, r0
-  bx lr
+    rrx r0, r0
+                bx lr
 }
 #endif
 
-
 /** \brief  LDRT Unprivileged (8 bit)
 
     This function executes a Unprivileged LDRT instruction for 8 bit value.
@@ -312,8 +286,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
+#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
 
 /** \brief  LDRT Unprivileged (16 bit)
 
@@ -322,8 +295,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
+#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
 
 /** \brief  LDRT Unprivileged (32 bit)
 
@@ -332,8 +304,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
+#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
 
 /** \brief  STRT Unprivileged (8 bit)
 
@@ -342,8 +313,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
+#define __STRBT(value, ptr) __strt(value, ptr)
 
 /** \brief  STRT Unprivileged (16 bit)
 
@@ -352,8 +322,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
+#define __STRHT(value, ptr) __strt(value, ptr)
 
 /** \brief  STRT Unprivileged (32 bit)
 
@@ -362,101 +331,93 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-#define __STRT(value, ptr)                __strt(value, ptr)
+#define __STRT(value, ptr) __strt(value, ptr)
 
 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
 
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
 
 /* Define macros for porting to both thumb1 and thumb2.
  * For thumb1, use low register (r0-r7), specified by constrant "l"
  * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#if defined(__thumb__) && !defined(__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l"(r)
+#define __CMSIS_GCC_USE_REG(r) "l"(r)
 #else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#define __CMSIS_GCC_OUT_REG(r) "=r"(r)
+#define __CMSIS_GCC_USE_REG(r) "r"(r)
 #endif
 
 /** \brief  No Operation
 
     No Operation does nothing. This instruction can be used for code alignment purposes.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
 {
-  __ASM volatile ("nop");
+    __ASM volatile("nop");
 }
 
-
 /** \brief  Wait For Interrupt
 
     Wait For Interrupt is a hint instruction that suspends execution
     until one of a number of events occurs.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
 {
-  __ASM volatile ("wfi");
+    __ASM volatile("wfi");
 }
 
-
 /** \brief  Wait For Event
 
     Wait For Event is a hint instruction that permits the processor to enter
     a low-power state until one of a number of events occurs.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
 {
-  __ASM volatile ("wfe");
+    __ASM volatile("wfe");
 }
 
-
 /** \brief  Send Event
 
     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
 {
-  __ASM volatile ("sev");
+    __ASM volatile("sev");
 }
 
-
 /** \brief  Instruction Synchronization Barrier
 
     Instruction Synchronization Barrier flushes the pipeline in the processor,
     so that all instructions following the ISB are fetched from cache or
     memory, after the instruction has been completed.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
 {
-  __ASM volatile ("isb");
+    __ASM volatile("isb");
 }
 
-
 /** \brief  Data Synchronization Barrier
 
     This function acts as a special kind of Data Memory Barrier.
     It completes when all explicit memory accesses before this instruction complete.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
 {
-  __ASM volatile ("dsb");
+    __ASM volatile("dsb");
 }
 
-
 /** \brief  Data Memory Barrier
 
     This function ensures the apparent order of the explicit memory operations before
     and after the instruction, without ensuring their completion.
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
 {
-  __ASM volatile ("dmb");
+    __ASM volatile("dmb");
 }
 
-
 /** \brief  Reverse byte order (32 bit)
 
     This function reverses the byte order in integer value.
@@ -464,19 +425,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
 {
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
+    return __builtin_bswap32(value);
 #else
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
+    __ASM volatile("rev %0, %1"
+                   : __CMSIS_GCC_OUT_REG(result)
+                   : __CMSIS_GCC_USE_REG(value));
+    return (result);
 #endif
 }
 
-
 /** \brief  Reverse byte order (16 bit)
 
     This function reverses the byte order in two unsigned short values.
@@ -484,15 +446,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
+    __ASM volatile("rev16 %0, %1"
+                   : __CMSIS_GCC_OUT_REG(result)
+                   : __CMSIS_GCC_USE_REG(value));
+    return (result);
 }
 
-
 /** \brief  Reverse byte order in signed short value
 
     This function reverses the byte order in a signed short value with sign extension to integer.
@@ -500,19 +463,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
 {
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
+    return (short)__builtin_bswap16(value);
 #else
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
+    __ASM volatile("revsh %0, %1"
+                   : __CMSIS_GCC_OUT_REG(result)
+                   : __CMSIS_GCC_USE_REG(value));
+    return (result);
 #endif
 }
 
-
 /** \brief  Rotate Right in unsigned value (32 bit)
 
     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@@ -521,12 +485,11 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
     \param [in]    value  Number of Bits to rotate
     \return               Rotated value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
-  return (op1 >> op2) | (op1 << (32 - op2)); 
+    return (op1 >> op2) | (op1 << (32 - op2));
 }
 
-
 /** \brief  Breakpoint
 
     This function causes the processor to enter Debug state.
@@ -535,10 +498,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
     \param [in]    value  is ignored by the processor.
                    If required, a debugger can use it to store additional information about the breakpoint.
  */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
+#define __BKPT(value) __ASM volatile("bkpt " #value)
 
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
 
 /** \brief  Reverse bit order of value
 
@@ -547,15 +509,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
     \param [in]    value  Value to reverse
     \return               Reversed value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
 {
-  uint32_t result;
+    uint32_t result;
 
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
+    __ASM volatile("rbit %0, %1"
+                   : "=r"(result)
+                   : "r"(value));
+    return (result);
 }
 
-
 /** \brief  LDR Exclusive (8 bit)
 
     This function executes a exclusive LDR instruction for 8 bit value.
@@ -563,22 +526,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+    __ASM volatile("ldrexb %0, %1"
+                   : "=r"(result)
+                   : "Q"(*addr));
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+    __ASM volatile("ldrexb %0, [%1]"
+                   : "=r"(result)
+                   : "r"(addr)
+                   : "memory");
 #endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
+    return ((uint8_t)result); /* Add explicit type cast here */
 }
 
-
 /** \brief  LDR Exclusive (16 bit)
 
     This function executes a exclusive LDR instruction for 16 bit values.
@@ -586,22 +553,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+    __ASM volatile("ldrexh %0, %1"
+                   : "=r"(result)
+                   : "Q"(*addr));
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+    __ASM volatile("ldrexh %0, [%1]"
+                   : "=r"(result)
+                   : "r"(addr)
+                   : "memory");
 #endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
+    return ((uint16_t)result); /* Add explicit type cast here */
 }
 
-
 /** \brief  LDR Exclusive (32 bit)
 
     This function executes a exclusive LDR instruction for 32 bit values.
@@ -609,15 +580,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
 {
     uint32_t result;
 
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
+    __ASM volatile("ldrex %0, %1"
+                   : "=r"(result)
+                   : "Q"(*addr));
+    return (result);
 }
 
-
 /** \brief  STR Exclusive (8 bit)
 
     This function executes a exclusive STR instruction for 8 bit values.
@@ -627,15 +599,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
     \return          0  Function succeeded
     \return          1  Function failed
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 {
-   uint32_t result;
+    uint32_t result;
 
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
+    __ASM volatile("strexb %0, %2, %1"
+                   : "=&r"(result), "=Q"(*addr)
+                   : "r"((uint32_t)value));
+    return (result);
 }
 
-
 /** \brief  STR Exclusive (16 bit)
 
     This function executes a exclusive STR instruction for 16 bit values.
@@ -645,15 +618,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
     \return          0  Function succeeded
     \return          1  Function failed
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 {
-   uint32_t result;
+    uint32_t result;
 
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
+    __ASM volatile("strexh %0, %2, %1"
+                   : "=&r"(result), "=Q"(*addr)
+                   : "r"((uint32_t)value));
+    return (result);
 }
 
-
 /** \brief  STR Exclusive (32 bit)
 
     This function executes a exclusive STR instruction for 32 bit values.
@@ -663,26 +637,27 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
     \return          0  Function succeeded
     \return          1  Function failed
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 {
-   uint32_t result;
+    uint32_t result;
 
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
+    __ASM volatile("strex %0, %2, %1"
+                   : "=&r"(result), "=Q"(*addr)
+                   : "r"(value));
+    return (result);
 }
 
-
 /** \brief  Remove the exclusive lock
 
     This function removes the exclusive lock which is created by LDREX.
 
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
 {
-  __ASM volatile ("clrex" ::: "memory");
+    __ASM volatile("clrex" ::
+                       : "memory");
 }
 
-
 /** \brief  Signed Saturate
 
     This function saturates a signed value.
@@ -691,13 +666,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
     \param [in]    sat  Bit position to saturate to (1..32)
     \return             Saturated value
  */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
+#define __SSAT(ARG1, ARG2)                   \
+    (                                        \
+        {                                    \
+            uint32_t __RES, __ARG1 = (ARG1); \
+            __ASM("ssat %0, %1, %2"          \
+                  : "=r"(__RES)              \
+                  : "I"(ARG2), "r"(__ARG1)); \
+            __RES;                           \
+        })
 
 /** \brief  Unsigned Saturate
 
@@ -707,13 +684,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
     \param [in]    sat  Bit position to saturate to (0..31)
     \return             Saturated value
  */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
+#define __USAT(ARG1, ARG2)                   \
+    (                                        \
+        {                                    \
+            uint32_t __RES, __ARG1 = (ARG1); \
+            __ASM("usat %0, %1, %2"          \
+                  : "=r"(__RES)              \
+                  : "I"(ARG2), "r"(__ARG1)); \
+            __RES;                           \
+        })
 
 /** \brief  Count leading zeros
 
@@ -722,15 +701,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
     \param [in]  value  Value to count the leading zeros
     \return             number of leading zeros in value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-   return ((uint8_t) result);    /* Add explicit type cast here */
+    __ASM volatile("clz %0, %1"
+                   : "=r"(result)
+                   : "r"(value));
+    return ((uint8_t)result); /* Add explicit type cast here */
 }
 
-
 /** \brief  Rotate Right with Extend (32 bit)
 
     This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
@@ -738,15 +718,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
     \param [in]    value  Value to rotate
     \return               Rotated value
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
+    __ASM volatile("rrx %0, %1"
+                   : __CMSIS_GCC_OUT_REG(result)
+                   : __CMSIS_GCC_USE_REG(value));
+    return (result);
 }
 
-
 /** \brief  LDRT Unprivileged (8 bit)
 
     This function executes a Unprivileged LDRT instruction for 8 bit value.
@@ -754,22 +735,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value
     \param [in]    ptr  Pointer to data
     \return             value of type uint8_t at (*ptr)
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+    __ASM volatile("ldrbt %0, %1"
+                   : "=r"(result)
+                   : "Q"(*addr));
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+    __ASM volatile("ldrbt %0, [%1]"
+                   : "=r"(result)
+                   : "r"(addr)
+                   : "memory");
 #endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
+    return ((uint8_t)result); /* Add explicit type cast here */
 }
 
-
 /** \brief  LDRT Unprivileged (16 bit)
 
     This function executes a Unprivileged LDRT instruction for 16 bit values.
@@ -777,22 +762,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint
     \param [in]    ptr  Pointer to data
     \return        value of type uint16_t at (*ptr)
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
 {
     uint32_t result;
 
 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+    __ASM volatile("ldrht %0, %1"
+                   : "=r"(result)
+                   : "Q"(*addr));
 #else
     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
        accepted by assembler. So has to use following less efficient pattern.
     */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+    __ASM volatile("ldrht %0, [%1]"
+                   : "=r"(result)
+                   : "r"(addr)
+                   : "memory");
 #endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
+    return ((uint16_t)result); /* Add explicit type cast here */
 }
 
-
 /** \brief  LDRT Unprivileged (32 bit)
 
     This function executes a Unprivileged LDRT instruction for 32 bit values.
@@ -800,15 +789,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uin
     \param [in]    ptr  Pointer to data
     \return        value of type uint32_t at (*ptr)
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
 {
     uint32_t result;
 
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
+    __ASM volatile("ldrt %0, %1"
+                   : "=r"(result)
+                   : "Q"(*addr));
+    return (result);
 }
 
-
 /** \brief  STRT Unprivileged (8 bit)
 
     This function executes a Unprivileged STRT instruction for 8 bit values.
@@ -816,12 +806,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
 {
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+    __ASM volatile("strbt %1, %0"
+                   : "=Q"(*addr)
+                   : "r"((uint32_t)value));
 }
 
-
 /** \brief  STRT Unprivileged (16 bit)
 
     This function executes a Unprivileged STRT instruction for 16 bit values.
@@ -829,12 +820,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, v
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
 {
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+    __ASM volatile("strht %1, %0"
+                   : "=Q"(*addr)
+                   : "r"((uint32_t)value));
 }
 
-
 /** \brief  STRT Unprivileged (32 bit)
 
     This function executes a Unprivileged STRT instruction for 32 bit values.
@@ -842,25 +834,24 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value,
     \param [in]  value  Value to store
     \param [in]    ptr  Pointer to location
  */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
 {
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+    __ASM volatile("strt %1, %0"
+                   : "=Q"(*addr)
+                   : "r"(value));
 }
 
 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
 
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /*
  * The CMSIS functions have been implemented as intrinsics in the compiler.
@@ -868,8 +859,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, v
  * Including the CMSIS ones.
  */
 
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
 /* Cosmic specific functions */
 #include <cmsis_csm.h>
 

bsp/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h

@@ -1,4 +1,4 @@
-/**************************************************************************//**
+/**************************************************************************/ /**
  * @file     core_cmSimd.h
  * @brief    CMSIS Cortex-M SIMD Header File
  * @version  V4.00
@@ -34,661 +34,794 @@
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
 
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
+#if defined(__ICCARM__)
+#pragma system_include /* treat file as system include file for MISRA check */
 #endif
 
 #ifndef __CORE_CMSIMD_H
 #define __CORE_CMSIMD_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C"
+{
 #endif
 
-
-/*******************************************************************************
+    /*******************************************************************************
  *                Hardware Abstraction Layer
  ******************************************************************************/
 
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+    /* ###################  Compiler specific Intrinsics  ########################### */
+    /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
   Access to dedicated SIMD instructions
   @{
 */
 
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
 /* ARM armcc specific functions */
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | \
+                                   ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL))
+
+#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | \
+                                   ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL))
+
+#define __SMMLA(ARG1, ARG2, ARG3) ((int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                              ((int64_t)(ARG3) << 32)) >>  \
+                                             32))
+
+#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
 /* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("sadd8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qadd8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("shadd8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uadd8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uqadd8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uhadd8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("ssub8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qsub8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("shsub8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("usub8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uqsub8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uhsub8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("sadd16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qadd16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("shadd16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uadd16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uqadd16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uhadd16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("ssub16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qsub16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("shsub16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("usub16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uqsub16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uhsub16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("sasx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qasx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("shasx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uasx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uqasx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uhasx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("ssax %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qsax %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("shsax %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("usax %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uqsax %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uhsax %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("usad8 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
+    __ASM volatile("usada8 %0, %1, %2, %3"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
 }
 
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
+#define __SSAT16(ARG1, ARG2)                 \
+    (                                        \
+        {                                    \
+            uint32_t __RES, __ARG1 = (ARG1); \
+            __ASM("ssat16 %0, %1, %2"        \
+                  : "=r"(__RES)              \
+                  : "I"(ARG2), "r"(__ARG1)); \
+            __RES;                           \
+        })
 
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
+#define __USAT16(ARG1, ARG2)                 \
+    (                                        \
+        {                                    \
+            uint32_t __RES, __ARG1 = (ARG1); \
+            __ASM("usat16 %0, %1, %2"        \
+                  : "=r"(__RES)              \
+                  : "I"(ARG2), "r"(__ARG1)); \
+            __RES;                           \
+        })
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
+    __ASM volatile("uxtb16 %0, %1"
+                   : "=r"(result)
+                   : "r"(op1));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("uxtab16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
+    __ASM volatile("sxtb16 %0, %1"
+                   : "=r"(result)
+                   : "r"(op1));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("sxtab16 %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("smuad %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("smuadx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
+    __ASM volatile("smlad %0, %1, %2, %3"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
+    __ASM volatile("smladx %0, %1, %2, %3"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc)
 {
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#ifndef __ARMEB__ // Little endian
+    __ASM volatile("smlald %0, %1, %2, %3"
+                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else             // Big endian
+    __ASM volatile("smlald %0, %1, %2, %3"
+                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
 #endif
 
-  return(llr.w64);
+    return (llr.w64);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc)
 {
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#ifndef __ARMEB__ // Little endian
+    __ASM volatile("smlaldx %0, %1, %2, %3"
+                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else             // Big endian
+    __ASM volatile("smlaldx %0, %1, %2, %3"
+                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
 #endif
 
-  return(llr.w64);
+    return (llr.w64);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("smusd %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("smusdx %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
+    __ASM volatile("smlsd %0, %1, %2, %3"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
+    __ASM volatile("smlsdx %0, %1, %2, %3"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc)
 {
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#ifndef __ARMEB__ // Little endian
+    __ASM volatile("smlsld %0, %1, %2, %3"
+                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else             // Big endian
+    __ASM volatile("smlsld %0, %1, %2, %3"
+                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
 #endif
 
-  return(llr.w64);
+    return (llr.w64);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc)
 {
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
+    union llreg_u
+    {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#ifndef __ARMEB__ // Little endian
+    __ASM volatile("smlsldx %0, %1, %2, %3"
+                   : "=r"(llr.w32[0]), "=r"(llr.w32[1])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
+#else             // Big endian
+    __ASM volatile("smlsldx %0, %1, %2, %3"
+                   : "=r"(llr.w32[1]), "=r"(llr.w32[0])
+                   : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
 #endif
 
-  return(llr.w64);
+    return (llr.w64);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("sel %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qadd %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
 {
-  uint32_t result;
+    uint32_t result;
 
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
+    __ASM volatile("qsub %0, %1, %2"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2));
+    return (result);
 }
 
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
+#define __PKHBT(ARG1, ARG2, ARG3)                             \
+    (                                                         \
+        {                                                     \
+            uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+            __ASM("pkhbt %0, %1, %2, lsl %3"                  \
+                  : "=r"(__RES)                               \
+                  : "r"(__ARG1), "r"(__ARG2), "I"(ARG3));     \
+            __RES;                                            \
+        })
 
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
+#define __PKHTB(ARG1, ARG2, ARG3)                             \
+    (                                                         \
+        {                                                     \
+            uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+            if (ARG3 == 0)                                    \
+                __ASM("pkhtb %0, %1, %2"                      \
+                      : "=r"(__RES)                           \
+                      : "r"(__ARG1), "r"(__ARG2));            \
+            else                                              \
+                __ASM("pkhtb %0, %1, %2, asr %3"              \
+                      : "=r"(__RES)                           \
+                      : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \
+            __RES;                                            \
+        })
 
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
 {
- int32_t result;
+    int32_t result;
 
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
+    __ASM volatile("smmla %0, %1, %2, %3"
+                   : "=r"(result)
+                   : "r"(op1), "r"(op2), "r"(op3));
+    return (result);
 }
 
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
 /* IAR iccarm specific functions */
 #include <cmsis_iar.h>
 
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
 /* TI CCS specific functions */
 #include <cmsis_ccs.h>
 
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
 /* TASKING carm specific functions */
 /* not yet supported */
 
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
 /* Cosmic specific functions */
 #include <cmsis_csm.h>
 
 #endif
 
-/*@} end of group CMSIS_SIMD_intrinsics */
-
+    /*@} end of group CMSIS_SIMD_intrinsics */
 
 #ifdef __cplusplus
 }

bsp/swm320/libraries/CMSIS/DeviceSupport/SWM320.h

@@ -327,9 +327,9 @@ typedef struct
 #define SYS_PLLCR_OFF_Pos 2
 #define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos)
 
-#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack分频寄存器                           \
-                               //VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \
-                               //PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
+#define SYS_PLLDIV_FBDIV_Pos 0 /*   PLL FeedBack分频寄存器                           \
+                                    VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \
+                                    PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV   */
 #define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos)
 #define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟
 #define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos)
@@ -364,8 +364,8 @@ typedef struct
 
 typedef struct
 {
-    __IO uint32_t PORTA_SEL; //给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能
-                             //当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设
+    __IO uint32_t PORTA_SEL; /*给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能
+                             当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 */
     __IO uint32_t PORTB_SEL;
 
     __IO uint32_t PORTC_SEL;
@@ -1182,447 +1182,6 @@ typedef struct
     __IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用
 } GPIO_TypeDef;
 
-#define GPIO_DATA_PIN0_Pos 0
-#define GPIO_DATA_PIN0_Msk (0x01 << GPIO_DATA_PIN0_Pos)
-#define GPIO_DATA_PIN1_Pos 1
-#define GPIO_DATA_PIN1_Msk (0x01 << GPIO_DATA_PIN1_Pos)
-#define GPIO_DATA_PIN2_Pos 2
-#define GPIO_DATA_PIN2_Msk (0x01 << GPIO_DATA_PIN2_Pos)
-#define GPIO_DATA_PIN3_Pos 3
-#define GPIO_DATA_PIN3_Msk (0x01 << GPIO_DATA_PIN3_Pos)
-#define GPIO_DATA_PIN4_Pos 4
-#define GPIO_DATA_PIN4_Msk (0x01 << GPIO_DATA_PIN4_Pos)
-#define GPIO_DATA_PIN5_Pos 5
-#define GPIO_DATA_PIN5_Msk (0x01 << GPIO_DATA_PIN5_Pos)
-#define GPIO_DATA_PIN6_Pos 6
-#define GPIO_DATA_PIN6_Msk (0x01 << GPIO_DATA_PIN6_Pos)
-#define GPIO_DATA_PIN7_Pos 7
-#define GPIO_DATA_PIN7_Msk (0x01 << GPIO_DATA_PIN7_Pos)
-#define GPIO_DATA_PIN8_Pos 8
-#define GPIO_DATA_PIN8_Msk (0x01 << GPIO_DATA_PIN8_Pos)
-#define GPIO_DATA_PIN9_Pos 9
-#define GPIO_DATA_PIN9_Msk (0x01 << GPIO_DATA_PIN9_Pos)
-#define GPIO_DATA_PIN10_Pos 10
-#define GPIO_DATA_PIN10_Msk (0x01 << GPIO_DATA_PIN10_Pos)
-#define GPIO_DATA_PIN11_Pos 11
-#define GPIO_DATA_PIN11_Msk (0x01 << GPIO_DATA_PIN11_Pos)
-#define GPIO_DATA_PIN12_Pos 12
-#define GPIO_DATA_PIN12_Msk (0x01 << GPIO_DATA_PIN12_Pos)
-#define GPIO_DATA_PIN13_Pos 13
-#define GPIO_DATA_PIN13_Msk (0x01 << GPIO_DATA_PIN13_Pos)
-#define GPIO_DATA_PIN14_Pos 14
-#define GPIO_DATA_PIN14_Msk (0x01 << GPIO_DATA_PIN14_Pos)
-#define GPIO_DATA_PIN15_Pos 15
-#define GPIO_DATA_PIN15_Msk (0x01 << GPIO_DATA_PIN15_Pos)
-#define GPIO_DATA_PIN16_Pos 16
-#define GPIO_DATA_PIN16_Msk (0x01 << GPIO_DATA_PIN16_Pos)
-#define GPIO_DATA_PIN17_Pos 17
-#define GPIO_DATA_PIN17_Msk (0x01 << GPIO_DATA_PIN17_Pos)
-#define GPIO_DATA_PIN18_Pos 18
-#define GPIO_DATA_PIN18_Msk (0x01 << GPIO_DATA_PIN18_Pos)
-#define GPIO_DATA_PIN19_Pos 19
-#define GPIO_DATA_PIN19_Msk (0x01 << GPIO_DATA_PIN19_Pos)
-#define GPIO_DATA_PIN20_Pos 20
-#define GPIO_DATA_PIN20_Msk (0x01 << GPIO_DATA_PIN20_Pos)
-#define GPIO_DATA_PIN21_Pos 21
-#define GPIO_DATA_PIN21_Msk (0x01 << GPIO_DATA_PIN21_Pos)
-#define GPIO_DATA_PIN22_Pos 22
-#define GPIO_DATA_PIN22_Msk (0x01 << GPIO_DATA_PIN22_Pos)
-#define GPIO_DATA_PIN23_Pos 23
-#define GPIO_DATA_PIN23_Msk (0x01 << GPIO_DATA_PIN23_Pos)
-
-#define GPIO_DIR_PIN0_Pos 0
-#define GPIO_DIR_PIN0_Msk (0x01 << GPIO_DIR_PIN0_Pos)
-#define GPIO_DIR_PIN1_Pos 1
-#define GPIO_DIR_PIN1_Msk (0x01 << GPIO_DIR_PIN1_Pos)
-#define GPIO_DIR_PIN2_Pos 2
-#define GPIO_DIR_PIN2_Msk (0x01 << GPIO_DIR_PIN2_Pos)
-#define GPIO_DIR_PIN3_Pos 3
-#define GPIO_DIR_PIN3_Msk (0x01 << GPIO_DIR_PIN3_Pos)
-#define GPIO_DIR_PIN4_Pos 4
-#define GPIO_DIR_PIN4_Msk (0x01 << GPIO_DIR_PIN4_Pos)
-#define GPIO_DIR_PIN5_Pos 5
-#define GPIO_DIR_PIN5_Msk (0x01 << GPIO_DIR_PIN5_Pos)
-#define GPIO_DIR_PIN6_Pos 6
-#define GPIO_DIR_PIN6_Msk (0x01 << GPIO_DIR_PIN6_Pos)
-#define GPIO_DIR_PIN7_Pos 7
-#define GPIO_DIR_PIN7_Msk (0x01 << GPIO_DIR_PIN7_Pos)
-#define GPIO_DIR_PIN8_Pos 8
-#define GPIO_DIR_PIN8_Msk (0x01 << GPIO_DIR_PIN8_Pos)
-#define GPIO_DIR_PIN9_Pos 9
-#define GPIO_DIR_PIN9_Msk (0x01 << GPIO_DIR_PIN9_Pos)
-#define GPIO_DIR_PIN10_Pos 10
-#define GPIO_DIR_PIN10_Msk (0x01 << GPIO_DIR_PIN10_Pos)
-#define GPIO_DIR_PIN11_Pos 11
-#define GPIO_DIR_PIN11_Msk (0x01 << GPIO_DIR_PIN11_Pos)
-#define GPIO_DIR_PIN12_Pos 12
-#define GPIO_DIR_PIN12_Msk (0x01 << GPIO_DIR_PIN12_Pos)
-#define GPIO_DIR_PIN13_Pos 13
-#define GPIO_DIR_PIN13_Msk (0x01 << GPIO_DIR_PIN13_Pos)
-#define GPIO_DIR_PIN14_Pos 14
-#define GPIO_DIR_PIN14_Msk (0x01 << GPIO_DIR_PIN14_Pos)
-#define GPIO_DIR_PIN15_Pos 15
-#define GPIO_DIR_PIN15_Msk (0x01 << GPIO_DIR_PIN15_Pos)
-#define GPIO_DIR_PIN16_Pos 16
-#define GPIO_DIR_PIN16_Msk (0x01 << GPIO_DIR_PIN16_Pos)
-#define GPIO_DIR_PIN17_Pos 17
-#define GPIO_DIR_PIN17_Msk (0x01 << GPIO_DIR_PIN17_Pos)
-#define GPIO_DIR_PIN18_Pos 18
-#define GPIO_DIR_PIN18_Msk (0x01 << GPIO_DIR_PIN18_Pos)
-#define GPIO_DIR_PIN19_Pos 19
-#define GPIO_DIR_PIN19_Msk (0x01 << GPIO_DIR_PIN19_Pos)
-#define GPIO_DIR_PIN20_Pos 20
-#define GPIO_DIR_PIN20_Msk (0x01 << GPIO_DIR_PIN20_Pos)
-#define GPIO_DIR_PIN21_Pos 21
-#define GPIO_DIR_PIN21_Msk (0x01 << GPIO_DIR_PIN21_Pos)
-#define GPIO_DIR_PIN22_Pos 22
-#define GPIO_DIR_PIN22_Msk (0x01 << GPIO_DIR_PIN22_Pos)
-#define GPIO_DIR_PIN23_Pos 23
-#define GPIO_DIR_PIN23_Msk (0x01 << GPIO_DIR_PIN23_Pos)
-
-#define GPIO_INTLVLTRG_PIN0_Pos 0
-#define GPIO_INTLVLTRG_PIN0_Msk (0x01 << GPIO_INTLVLTRG_PIN0_Pos)
-#define GPIO_INTLVLTRG_PIN1_Pos 1
-#define GPIO_INTLVLTRG_PIN1_Msk (0x01 << GPIO_INTLVLTRG_PIN1_Pos)
-#define GPIO_INTLVLTRG_PIN2_Pos 2
-#define GPIO_INTLVLTRG_PIN2_Msk (0x01 << GPIO_INTLVLTRG_PIN2_Pos)
-#define GPIO_INTLVLTRG_PIN3_Pos 3
-#define GPIO_INTLVLTRG_PIN3_Msk (0x01 << GPIO_INTLVLTRG_PIN3_Pos)
-#define GPIO_INTLVLTRG_PIN4_Pos 4
-#define GPIO_INTLVLTRG_PIN4_Msk (0x01 << GPIO_INTLVLTRG_PIN4_Pos)
-#define GPIO_INTLVLTRG_PIN5_Pos 5
-#define GPIO_INTLVLTRG_PIN5_Msk (0x01 << GPIO_INTLVLTRG_PIN5_Pos)
-#define GPIO_INTLVLTRG_PIN6_Pos 6
-#define GPIO_INTLVLTRG_PIN6_Msk (0x01 << GPIO_INTLVLTRG_PIN6_Pos)
-#define GPIO_INTLVLTRG_PIN7_Pos 7
-#define GPIO_INTLVLTRG_PIN7_Msk (0x01 << GPIO_INTLVLTRG_PIN7_Pos)
-#define GPIO_INTLVLTRG_PIN8_Pos 8
-#define GPIO_INTLVLTRG_PIN8_Msk (0x01 << GPIO_INTLVLTRG_PIN8_Pos)
-#define GPIO_INTLVLTRG_PIN9_Pos 9
-#define GPIO_INTLVLTRG_PIN9_Msk (0x01 << GPIO_INTLVLTRG_PIN9_Pos)
-#define GPIO_INTLVLTRG_PIN10_Pos 10
-#define GPIO_INTLVLTRG_PIN10_Msk (0x01 << GPIO_INTLVLTRG_PIN10_Pos)
-#define GPIO_INTLVLTRG_PIN11_Pos 11
-#define GPIO_INTLVLTRG_PIN11_Msk (0x01 << GPIO_INTLVLTRG_PIN11_Pos)
-#define GPIO_INTLVLTRG_PIN12_Pos 12
-#define GPIO_INTLVLTRG_PIN12_Msk (0x01 << GPIO_INTLVLTRG_PIN12_Pos)
-#define GPIO_INTLVLTRG_PIN13_Pos 13
-#define GPIO_INTLVLTRG_PIN13_Msk (0x01 << GPIO_INTLVLTRG_PIN13_Pos)
-#define GPIO_INTLVLTRG_PIN14_Pos 14
-#define GPIO_INTLVLTRG_PIN14_Msk (0x01 << GPIO_INTLVLTRG_PIN14_Pos)
-#define GPIO_INTLVLTRG_PIN15_Pos 15
-#define GPIO_INTLVLTRG_PIN15_Msk (0x01 << GPIO_INTLVLTRG_PIN15_Pos)
-#define GPIO_INTLVLTRG_PIN16_Pos 16
-#define GPIO_INTLVLTRG_PIN16_Msk (0x01 << GPIO_INTLVLTRG_PIN16_Pos)
-#define GPIO_INTLVLTRG_PIN17_Pos 17
-#define GPIO_INTLVLTRG_PIN17_Msk (0x01 << GPIO_INTLVLTRG_PIN17_Pos)
-#define GPIO_INTLVLTRG_PIN18_Pos 18
-#define GPIO_INTLVLTRG_PIN18_Msk (0x01 << GPIO_INTLVLTRG_PIN18_Pos)
-#define GPIO_INTLVLTRG_PIN19_Pos 19
-#define GPIO_INTLVLTRG_PIN19_Msk (0x01 << GPIO_INTLVLTRG_PIN19_Pos)
-#define GPIO_INTLVLTRG_PIN20_Pos 20
-#define GPIO_INTLVLTRG_PIN20_Msk (0x01 << GPIO_INTLVLTRG_PIN20_Pos)
-#define GPIO_INTLVLTRG_PIN21_Pos 21
-#define GPIO_INTLVLTRG_PIN21_Msk (0x01 << GPIO_INTLVLTRG_PIN21_Pos)
-#define GPIO_INTLVLTRG_PIN22_Pos 22
-#define GPIO_INTLVLTRG_PIN22_Msk (0x01 << GPIO_INTLVLTRG_PIN22_Pos)
-#define GPIO_INTLVLTRG_PIN23_Pos 23
-#define GPIO_INTLVLTRG_PIN23_Msk (0x01 << GPIO_INTLVLTRG_PIN23_Pos)
-
-#define GPIO_INTBE_PIN0_Pos 0
-#define GPIO_INTBE_PIN0_Msk (0x01 << GPIO_INTBE_PIN0_Pos)
-#define GPIO_INTBE_PIN1_Pos 1
-#define GPIO_INTBE_PIN1_Msk (0x01 << GPIO_INTBE_PIN1_Pos)
-#define GPIO_INTBE_PIN2_Pos 2
-#define GPIO_INTBE_PIN2_Msk (0x01 << GPIO_INTBE_PIN2_Pos)
-#define GPIO_INTBE_PIN3_Pos 3
-#define GPIO_INTBE_PIN3_Msk (0x01 << GPIO_INTBE_PIN3_Pos)
-#define GPIO_INTBE_PIN4_Pos 4
-#define GPIO_INTBE_PIN4_Msk (0x01 << GPIO_INTBE_PIN4_Pos)
-#define GPIO_INTBE_PIN5_Pos 5
-#define GPIO_INTBE_PIN5_Msk (0x01 << GPIO_INTBE_PIN5_Pos)
-#define GPIO_INTBE_PIN6_Pos 6
-#define GPIO_INTBE_PIN6_Msk (0x01 << GPIO_INTBE_PIN6_Pos)
-#define GPIO_INTBE_PIN7_Pos 7
-#define GPIO_INTBE_PIN7_Msk (0x01 << GPIO_INTBE_PIN7_Pos)
-#define GPIO_INTBE_PIN8_Pos 8
-#define GPIO_INTBE_PIN8_Msk (0x01 << GPIO_INTBE_PIN8_Pos)
-#define GPIO_INTBE_PIN9_Pos 9
-#define GPIO_INTBE_PIN9_Msk (0x01 << GPIO_INTBE_PIN9_Pos)
-#define GPIO_INTBE_PIN10_Pos 10
-#define GPIO_INTBE_PIN10_Msk (0x01 << GPIO_INTBE_PIN10_Pos)
-#define GPIO_INTBE_PIN11_Pos 11
-#define GPIO_INTBE_PIN11_Msk (0x01 << GPIO_INTBE_PIN11_Pos)
-#define GPIO_INTBE_PIN12_Pos 12
-#define GPIO_INTBE_PIN12_Msk (0x01 << GPIO_INTBE_PIN12_Pos)
-#define GPIO_INTBE_PIN13_Pos 13
-#define GPIO_INTBE_PIN13_Msk (0x01 << GPIO_INTBE_PIN13_Pos)
-#define GPIO_INTBE_PIN14_Pos 14
-#define GPIO_INTBE_PIN14_Msk (0x01 << GPIO_INTBE_PIN14_Pos)
-#define GPIO_INTBE_PIN15_Pos 15
-#define GPIO_INTBE_PIN15_Msk (0x01 << GPIO_INTBE_PIN15_Pos)
-#define GPIO_INTBE_PIN16_Pos 16
-#define GPIO_INTBE_PIN16_Msk (0x01 << GPIO_INTBE_PIN16_Pos)
-#define GPIO_INTBE_PIN17_Pos 17
-#define GPIO_INTBE_PIN17_Msk (0x01 << GPIO_INTBE_PIN17_Pos)
-#define GPIO_INTBE_PIN18_Pos 18
-#define GPIO_INTBE_PIN18_Msk (0x01 << GPIO_INTBE_PIN18_Pos)
-#define GPIO_INTBE_PIN19_Pos 19
-#define GPIO_INTBE_PIN19_Msk (0x01 << GPIO_INTBE_PIN19_Pos)
-#define GPIO_INTBE_PIN20_Pos 20
-#define GPIO_INTBE_PIN20_Msk (0x01 << GPIO_INTBE_PIN20_Pos)
-#define GPIO_INTBE_PIN21_Pos 21
-#define GPIO_INTBE_PIN21_Msk (0x01 << GPIO_INTBE_PIN21_Pos)
-#define GPIO_INTBE_PIN22_Pos 22
-#define GPIO_INTBE_PIN22_Msk (0x01 << GPIO_INTBE_PIN22_Pos)
-#define GPIO_INTBE_PIN23_Pos 23
-#define GPIO_INTBE_PIN23_Msk (0x01 << GPIO_INTBE_PIN23_Pos)
-
-#define GPIO_INTRISEEN_PIN0_Pos 0
-#define GPIO_INTRISEEN_PIN0_Msk (0x01 << GPIO_INTRISEEN_PIN0_Pos)
-#define GPIO_INTRISEEN_PIN1_Pos 1
-#define GPIO_INTRISEEN_PIN1_Msk (0x01 << GPIO_INTRISEEN_PIN1_Pos)
-#define GPIO_INTRISEEN_PIN2_Pos 2
-#define GPIO_INTRISEEN_PIN2_Msk (0x01 << GPIO_INTRISEEN_PIN2_Pos)
-#define GPIO_INTRISEEN_PIN3_Pos 3
-#define GPIO_INTRISEEN_PIN3_Msk (0x01 << GPIO_INTRISEEN_PIN3_Pos)
-#define GPIO_INTRISEEN_PIN4_Pos 4
-#define GPIO_INTRISEEN_PIN4_Msk (0x01 << GPIO_INTRISEEN_PIN4_Pos)
-#define GPIO_INTRISEEN_PIN5_Pos 5
-#define GPIO_INTRISEEN_PIN5_Msk (0x01 << GPIO_INTRISEEN_PIN5_Pos)
-#define GPIO_INTRISEEN_PIN6_Pos 6
-#define GPIO_INTRISEEN_PIN6_Msk (0x01 << GPIO_INTRISEEN_PIN6_Pos)
-#define GPIO_INTRISEEN_PIN7_Pos 7
-#define GPIO_INTRISEEN_PIN7_Msk (0x01 << GPIO_INTRISEEN_PIN7_Pos)
-#define GPIO_INTRISEEN_PIN8_Pos 8
-#define GPIO_INTRISEEN_PIN8_Msk (0x01 << GPIO_INTRISEEN_PIN8_Pos)
-#define GPIO_INTRISEEN_PIN9_Pos 9
-#define GPIO_INTRISEEN_PIN9_Msk (0x01 << GPIO_INTRISEEN_PIN9_Pos)
-#define GPIO_INTRISEEN_PIN10_Pos 10
-#define GPIO_INTRISEEN_PIN10_Msk (0x01 << GPIO_INTRISEEN_PIN10_Pos)
-#define GPIO_INTRISEEN_PIN11_Pos 11
-#define GPIO_INTRISEEN_PIN11_Msk (0x01 << GPIO_INTRISEEN_PIN11_Pos)
-#define GPIO_INTRISEEN_PIN12_Pos 12
-#define GPIO_INTRISEEN_PIN12_Msk (0x01 << GPIO_INTRISEEN_PIN12_Pos)
-#define GPIO_INTRISEEN_PIN13_Pos 13
-#define GPIO_INTRISEEN_PIN13_Msk (0x01 << GPIO_INTRISEEN_PIN13_Pos)
-#define GPIO_INTRISEEN_PIN14_Pos 14
-#define GPIO_INTRISEEN_PIN14_Msk (0x01 << GPIO_INTRISEEN_PIN14_Pos)
-#define GPIO_INTRISEEN_PIN15_Pos 15
-#define GPIO_INTRISEEN_PIN15_Msk (0x01 << GPIO_INTRISEEN_PIN15_Pos)
-#define GPIO_INTRISEEN_PIN16_Pos 16
-#define GPIO_INTRISEEN_PIN16_Msk (0x01 << GPIO_INTRISEEN_PIN16_Pos)
-#define GPIO_INTRISEEN_PIN17_Pos 17
-#define GPIO_INTRISEEN_PIN17_Msk (0x01 << GPIO_INTRISEEN_PIN17_Pos)
-#define GPIO_INTRISEEN_PIN18_Pos 18
-#define GPIO_INTRISEEN_PIN18_Msk (0x01 << GPIO_INTRISEEN_PIN18_Pos)
-#define GPIO_INTRISEEN_PIN19_Pos 19
-#define GPIO_INTRISEEN_PIN19_Msk (0x01 << GPIO_INTRISEEN_PIN19_Pos)
-#define GPIO_INTRISEEN_PIN20_Pos 20
-#define GPIO_INTRISEEN_PIN20_Msk (0x01 << GPIO_INTRISEEN_PIN20_Pos)
-#define GPIO_INTRISEEN_PIN21_Pos 21
-#define GPIO_INTRISEEN_PIN21_Msk (0x01 << GPIO_INTRISEEN_PIN21_Pos)
-#define GPIO_INTRISEEN_PIN22_Pos 22
-#define GPIO_INTRISEEN_PIN22_Msk (0x01 << GPIO_INTRISEEN_PIN22_Pos)
-#define GPIO_INTRISEEN_PIN23_Pos 23
-#define GPIO_INTRISEEN_PIN23_Msk (0x01 << GPIO_INTRISEEN_PIN23_Pos)
-
-#define GPIO_INTEN_PIN0_Pos 0
-#define GPIO_INTEN_PIN0_Msk (0x01 << GPIO_INTEN_PIN0_Pos)
-#define GPIO_INTEN_PIN1_Pos 1
-#define GPIO_INTEN_PIN1_Msk (0x01 << GPIO_INTEN_PIN1_Pos)
-#define GPIO_INTEN_PIN2_Pos 2
-#define GPIO_INTEN_PIN2_Msk (0x01 << GPIO_INTEN_PIN2_Pos)
-#define GPIO_INTEN_PIN3_Pos 3
-#define GPIO_INTEN_PIN3_Msk (0x01 << GPIO_INTEN_PIN3_Pos)
-#define GPIO_INTEN_PIN4_Pos 4
-#define GPIO_INTEN_PIN4_Msk (0x01 << GPIO_INTEN_PIN4_Pos)
-#define GPIO_INTEN_PIN5_Pos 5
-#define GPIO_INTEN_PIN5_Msk (0x01 << GPIO_INTEN_PIN5_Pos)
-#define GPIO_INTEN_PIN6_Pos 6
-#define GPIO_INTEN_PIN6_Msk (0x01 << GPIO_INTEN_PIN6_Pos)
-#define GPIO_INTEN_PIN7_Pos 7
-#define GPIO_INTEN_PIN7_Msk (0x01 << GPIO_INTEN_PIN7_Pos)
-#define GPIO_INTEN_PIN8_Pos 8
-#define GPIO_INTEN_PIN8_Msk (0x01 << GPIO_INTEN_PIN8_Pos)
-#define GPIO_INTEN_PIN9_Pos 9
-#define GPIO_INTEN_PIN9_Msk (0x01 << GPIO_INTEN_PIN9_Pos)
-#define GPIO_INTEN_PIN10_Pos 10
-#define GPIO_INTEN_PIN10_Msk (0x01 << GPIO_INTEN_PIN10_Pos)
-#define GPIO_INTEN_PIN11_Pos 11
-#define GPIO_INTEN_PIN11_Msk (0x01 << GPIO_INTEN_PIN11_Pos)
-#define GPIO_INTEN_PIN12_Pos 12
-#define GPIO_INTEN_PIN12_Msk (0x01 << GPIO_INTEN_PIN12_Pos)
-#define GPIO_INTEN_PIN13_Pos 13
-#define GPIO_INTEN_PIN13_Msk (0x01 << GPIO_INTEN_PIN13_Pos)
-#define GPIO_INTEN_PIN14_Pos 14
-#define GPIO_INTEN_PIN14_Msk (0x01 << GPIO_INTEN_PIN14_Pos)
-#define GPIO_INTEN_PIN15_Pos 15
-#define GPIO_INTEN_PIN15_Msk (0x01 << GPIO_INTEN_PIN15_Pos)
-#define GPIO_INTEN_PIN16_Pos 16
-#define GPIO_INTEN_PIN16_Msk (0x01 << GPIO_INTEN_PIN16_Pos)
-#define GPIO_INTEN_PIN17_Pos 17
-#define GPIO_INTEN_PIN17_Msk (0x01 << GPIO_INTEN_PIN17_Pos)
-#define GPIO_INTEN_PIN18_Pos 18
-#define GPIO_INTEN_PIN18_Msk (0x01 << GPIO_INTEN_PIN18_Pos)
-#define GPIO_INTEN_PIN19_Pos 19
-#define GPIO_INTEN_PIN19_Msk (0x01 << GPIO_INTEN_PIN19_Pos)
-#define GPIO_INTEN_PIN20_Pos 20
-#define GPIO_INTEN_PIN20_Msk (0x01 << GPIO_INTEN_PIN20_Pos)
-#define GPIO_INTEN_PIN21_Pos 21
-#define GPIO_INTEN_PIN21_Msk (0x01 << GPIO_INTEN_PIN21_Pos)
-#define GPIO_INTEN_PIN22_Pos 22
-#define GPIO_INTEN_PIN22_Msk (0x01 << GPIO_INTEN_PIN22_Pos)
-#define GPIO_INTEN_PIN23_Pos 23
-#define GPIO_INTEN_PIN23_Msk (0x01 << GPIO_INTEN_PIN23_Pos)
-
-#define GPIO_INTRAWSTAT_PIN0_Pos 0
-#define GPIO_INTRAWSTAT_PIN0_Msk (0x01 << GPIO_INTRAWSTAT_PIN0_Pos)
-#define GPIO_INTRAWSTAT_PIN1_Pos 1
-#define GPIO_INTRAWSTAT_PIN1_Msk (0x01 << GPIO_INTRAWSTAT_PIN1_Pos)
-#define GPIO_INTRAWSTAT_PIN2_Pos 2
-#define GPIO_INTRAWSTAT_PIN2_Msk (0x01 << GPIO_INTRAWSTAT_PIN2_Pos)
-#define GPIO_INTRAWSTAT_PIN3_Pos 3
-#define GPIO_INTRAWSTAT_PIN3_Msk (0x01 << GPIO_INTRAWSTAT_PIN3_Pos)
-#define GPIO_INTRAWSTAT_PIN4_Pos 4
-#define GPIO_INTRAWSTAT_PIN4_Msk (0x01 << GPIO_INTRAWSTAT_PIN4_Pos)
-#define GPIO_INTRAWSTAT_PIN5_Pos 5
-#define GPIO_INTRAWSTAT_PIN5_Msk (0x01 << GPIO_INTRAWSTAT_PIN5_Pos)
-#define GPIO_INTRAWSTAT_PIN6_Pos 6
-#define GPIO_INTRAWSTAT_PIN6_Msk (0x01 << GPIO_INTRAWSTAT_PIN6_Pos)
-#define GPIO_INTRAWSTAT_PIN7_Pos 7
-#define GPIO_INTRAWSTAT_PIN7_Msk (0x01 << GPIO_INTRAWSTAT_PIN7_Pos)
-#define GPIO_INTRAWSTAT_PIN8_Pos 8
-#define GPIO_INTRAWSTAT_PIN8_Msk (0x01 << GPIO_INTRAWSTAT_PIN8_Pos)
-#define GPIO_INTRAWSTAT_PIN9_Pos 9
-#define GPIO_INTRAWSTAT_PIN9_Msk (0x01 << GPIO_INTRAWSTAT_PIN9_Pos)
-#define GPIO_INTRAWSTAT_PIN10_Pos 10
-#define GPIO_INTRAWSTAT_PIN10_Msk (0x01 << GPIO_INTRAWSTAT_PIN10_Pos)
-#define GPIO_INTRAWSTAT_PIN11_Pos 11
-#define GPIO_INTRAWSTAT_PIN11_Msk (0x01 << GPIO_INTRAWSTAT_PIN11_Pos)
-#define GPIO_INTRAWSTAT_PIN12_Pos 12
-#define GPIO_INTRAWSTAT_PIN12_Msk (0x01 << GPIO_INTRAWSTAT_PIN12_Pos)
-#define GPIO_INTRAWSTAT_PIN13_Pos 13
-#define GPIO_INTRAWSTAT_PIN13_Msk (0x01 << GPIO_INTRAWSTAT_PIN13_Pos)
-#define GPIO_INTRAWSTAT_PIN14_Pos 14
-#define GPIO_INTRAWSTAT_PIN14_Msk (0x01 << GPIO_INTRAWSTAT_PIN14_Pos)
-#define GPIO_INTRAWSTAT_PIN15_Pos 15
-#define GPIO_INTRAWSTAT_PIN15_Msk (0x01 << GPIO_INTRAWSTAT_PIN15_Pos)
-#define GPIO_INTRAWSTAT_PIN16_Pos 16
-#define GPIO_INTRAWSTAT_PIN16_Msk (0x01 << GPIO_INTRAWSTAT_PIN16_Pos)
-#define GPIO_INTRAWSTAT_PIN17_Pos 17
-#define GPIO_INTRAWSTAT_PIN17_Msk (0x01 << GPIO_INTRAWSTAT_PIN17_Pos)
-#define GPIO_INTRAWSTAT_PIN18_Pos 18
-#define GPIO_INTRAWSTAT_PIN18_Msk (0x01 << GPIO_INTRAWSTAT_PIN18_Pos)
-#define GPIO_INTRAWSTAT_PIN19_Pos 19
-#define GPIO_INTRAWSTAT_PIN19_Msk (0x01 << GPIO_INTRAWSTAT_PIN19_Pos)
-#define GPIO_INTRAWSTAT_PIN20_Pos 20
-#define GPIO_INTRAWSTAT_PIN20_Msk (0x01 << GPIO_INTRAWSTAT_PIN20_Pos)
-#define GPIO_INTRAWSTAT_PIN21_Pos 21
-#define GPIO_INTRAWSTAT_PIN21_Msk (0x01 << GPIO_INTRAWSTAT_PIN21_Pos)
-#define GPIO_INTRAWSTAT_PIN22_Pos 22
-#define GPIO_INTRAWSTAT_PIN22_Msk (0x01 << GPIO_INTRAWSTAT_PIN22_Pos)
-#define GPIO_INTRAWSTAT_PIN23_Pos 23
-#define GPIO_INTRAWSTAT_PIN23_Msk (0x01 << GPIO_INTRAWSTAT_PIN23_Pos)
-
-#define GPIO_INTSTAT_PIN0_Pos 0
-#define GPIO_INTSTAT_PIN0_Msk (0x01 << GPIO_INTSTAT_PIN0_Pos)
-#define GPIO_INTSTAT_PIN1_Pos 1
-#define GPIO_INTSTAT_PIN1_Msk (0x01 << GPIO_INTSTAT_PIN1_Pos)
-#define GPIO_INTSTAT_PIN2_Pos 2
-#define GPIO_INTSTAT_PIN2_Msk (0x01 << GPIO_INTSTAT_PIN2_Pos)
-#define GPIO_INTSTAT_PIN3_Pos 3
-#define GPIO_INTSTAT_PIN3_Msk (0x01 << GPIO_INTSTAT_PIN3_Pos)
-#define GPIO_INTSTAT_PIN4_Pos 4
-#define GPIO_INTSTAT_PIN4_Msk (0x01 << GPIO_INTSTAT_PIN4_Pos)
-#define GPIO_INTSTAT_PIN5_Pos 5
-#define GPIO_INTSTAT_PIN5_Msk (0x01 << GPIO_INTSTAT_PIN5_Pos)
-#define GPIO_INTSTAT_PIN6_Pos 6
-#define GPIO_INTSTAT_PIN6_Msk (0x01 << GPIO_INTSTAT_PIN6_Pos)
-#define GPIO_INTSTAT_PIN7_Pos 7
-#define GPIO_INTSTAT_PIN7_Msk (0x01 << GPIO_INTSTAT_PIN7_Pos)
-#define GPIO_INTSTAT_PIN8_Pos 8
-#define GPIO_INTSTAT_PIN8_Msk (0x01 << GPIO_INTSTAT_PIN8_Pos)
-#define GPIO_INTSTAT_PIN9_Pos 9
-#define GPIO_INTSTAT_PIN9_Msk (0x01 << GPIO_INTSTAT_PIN9_Pos)
-#define GPIO_INTSTAT_PIN10_Pos 10
-#define GPIO_INTSTAT_PIN10_Msk (0x01 << GPIO_INTSTAT_PIN10_Pos)
-#define GPIO_INTSTAT_PIN11_Pos 11
-#define GPIO_INTSTAT_PIN11_Msk (0x01 << GPIO_INTSTAT_PIN11_Pos)
-#define GPIO_INTSTAT_PIN12_Pos 12
-#define GPIO_INTSTAT_PIN12_Msk (0x01 << GPIO_INTSTAT_PIN12_Pos)
-#define GPIO_INTSTAT_PIN13_Pos 13
-#define GPIO_INTSTAT_PIN13_Msk (0x01 << GPIO_INTSTAT_PIN13_Pos)
-#define GPIO_INTSTAT_PIN14_Pos 14
-#define GPIO_INTSTAT_PIN14_Msk (0x01 << GPIO_INTSTAT_PIN14_Pos)
-#define GPIO_INTSTAT_PIN15_Pos 15
-#define GPIO_INTSTAT_PIN15_Msk (0x01 << GPIO_INTSTAT_PIN15_Pos)
-#define GPIO_INTSTAT_PIN16_Pos 16
-#define GPIO_INTSTAT_PIN16_Msk (0x01 << GPIO_INTSTAT_PIN16_Pos)
-#define GPIO_INTSTAT_PIN17_Pos 17
-#define GPIO_INTSTAT_PIN17_Msk (0x01 << GPIO_INTSTAT_PIN17_Pos)
-#define GPIO_INTSTAT_PIN18_Pos 18
-#define GPIO_INTSTAT_PIN18_Msk (0x01 << GPIO_INTSTAT_PIN18_Pos)
-#define GPIO_INTSTAT_PIN19_Pos 19
-#define GPIO_INTSTAT_PIN19_Msk (0x01 << GPIO_INTSTAT_PIN19_Pos)
-#define GPIO_INTSTAT_PIN20_Pos 20
-#define GPIO_INTSTAT_PIN20_Msk (0x01 << GPIO_INTSTAT_PIN20_Pos)
-#define GPIO_INTSTAT_PIN21_Pos 21
-#define GPIO_INTSTAT_PIN21_Msk (0x01 << GPIO_INTSTAT_PIN21_Pos)
-#define GPIO_INTSTAT_PIN22_Pos 22
-#define GPIO_INTSTAT_PIN22_Msk (0x01 << GPIO_INTSTAT_PIN22_Pos)
-#define GPIO_INTSTAT_PIN23_Pos 23
-#define GPIO_INTSTAT_PIN23_Msk (0x01 << GPIO_INTSTAT_PIN23_Pos)
-
-#define GPIO_INTCLR_PIN0_Pos 0
-#define GPIO_INTCLR_PIN0_Msk (0x01 << GPIO_INTCLR_PIN0_Pos)
-#define GPIO_INTCLR_PIN1_Pos 1
-#define GPIO_INTCLR_PIN1_Msk (0x01 << GPIO_INTCLR_PIN1_Pos)
-#define GPIO_INTCLR_PIN2_Pos 2
-#define GPIO_INTCLR_PIN2_Msk (0x01 << GPIO_INTCLR_PIN2_Pos)
-#define GPIO_INTCLR_PIN3_Pos 3
-#define GPIO_INTCLR_PIN3_Msk (0x01 << GPIO_INTCLR_PIN3_Pos)
-#define GPIO_INTCLR_PIN4_Pos 4
-#define GPIO_INTCLR_PIN4_Msk (0x01 << GPIO_INTCLR_PIN4_Pos)
-#define GPIO_INTCLR_PIN5_Pos 5
-#define GPIO_INTCLR_PIN5_Msk (0x01 << GPIO_INTCLR_PIN5_Pos)
-#define GPIO_INTCLR_PIN6_Pos 6
-#define GPIO_INTCLR_PIN6_Msk (0x01 << GPIO_INTCLR_PIN6_Pos)
-#define GPIO_INTCLR_PIN7_Pos 7
-#define GPIO_INTCLR_PIN7_Msk (0x01 << GPIO_INTCLR_PIN7_Pos)
-#define GPIO_INTCLR_PIN8_Pos 8
-#define GPIO_INTCLR_PIN8_Msk (0x01 << GPIO_INTCLR_PIN8_Pos)
-#define GPIO_INTCLR_PIN9_Pos 9
-#define GPIO_INTCLR_PIN9_Msk (0x01 << GPIO_INTCLR_PIN9_Pos)
-#define GPIO_INTCLR_PIN10_Pos 10
-#define GPIO_INTCLR_PIN10_Msk (0x01 << GPIO_INTCLR_PIN10_Pos)
-#define GPIO_INTCLR_PIN11_Pos 11
-#define GPIO_INTCLR_PIN11_Msk (0x01 << GPIO_INTCLR_PIN11_Pos)
-#define GPIO_INTCLR_PIN12_Pos 12
-#define GPIO_INTCLR_PIN12_Msk (0x01 << GPIO_INTCLR_PIN12_Pos)
-#define GPIO_INTCLR_PIN13_Pos 13
-#define GPIO_INTCLR_PIN13_Msk (0x01 << GPIO_INTCLR_PIN13_Pos)
-#define GPIO_INTCLR_PIN14_Pos 14
-#define GPIO_INTCLR_PIN14_Msk (0x01 << GPIO_INTCLR_PIN14_Pos)
-#define GPIO_INTCLR_PIN15_Pos 15
-#define GPIO_INTCLR_PIN15_Msk (0x01 << GPIO_INTCLR_PIN15_Pos)
-#define GPIO_INTCLR_PIN16_Pos 16
-#define GPIO_INTCLR_PIN16_Msk (0x01 << GPIO_INTCLR_PIN16_Pos)
-#define GPIO_INTCLR_PIN17_Pos 17
-#define GPIO_INTCLR_PIN17_Msk (0x01 << GPIO_INTCLR_PIN17_Pos)
-#define GPIO_INTCLR_PIN18_Pos 18
-#define GPIO_INTCLR_PIN18_Msk (0x01 << GPIO_INTCLR_PIN18_Pos)
-#define GPIO_INTCLR_PIN19_Pos 19
-#define GPIO_INTCLR_PIN19_Msk (0x01 << GPIO_INTCLR_PIN19_Pos)
-#define GPIO_INTCLR_PIN20_Pos 20
-#define GPIO_INTCLR_PIN20_Msk (0x01 << GPIO_INTCLR_PIN20_Pos)
-#define GPIO_INTCLR_PIN21_Pos 21
-#define GPIO_INTCLR_PIN21_Msk (0x01 << GPIO_INTCLR_PIN21_Pos)
-#define GPIO_INTCLR_PIN22_Pos 22
-#define GPIO_INTCLR_PIN22_Msk (0x01 << GPIO_INTCLR_PIN22_Pos)
-#define GPIO_INTCLR_PIN23_Pos 23
-#define GPIO_INTCLR_PIN23_Msk (0x01 << GPIO_INTCLR_PIN23_Pos)
-
 typedef struct
 {
     __IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数
@@ -1790,10 +1349,10 @@ typedef struct
 #define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos)
 #define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零
 #define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos)
-#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位           脉宽计算波特率，要求发送端发送0xFF \
+#define UART_BAUD_ABRBIT_Pos 24 /*Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位           脉宽计算波特率，要求发送端发送0xFF \
                                 //                                             1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE          \
                                 //                                             1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8          \
-                                //                                             1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80
+                                //                                             1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 */
 #define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos)
 #define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功     1 自动波特率校准失败
 #define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos)
@@ -2724,22 +2283,12 @@ typedef struct
             uint32_t RESERVED[5];
         } FILTER;
 
-        union
+        struct
         { //在正常工作模式下可读写，复位时不可访问
-            struct
-            {
-                __O uint32_t INFO;
-
-                __O uint32_t DATA[12];
-            } TXFRAME;
-
-            struct
-            {
-                __I uint32_t INFO;
+            __IO uint32_t INFO;
 
-                __I uint32_t DATA[12];
-            } RXFRAME;
-        };
+            __IO uint32_t DATA[12];
+        } FRAME;
     };
 
     __I uint32_t RMCNT; //Receive Message Count
@@ -2877,11 +2426,11 @@ typedef struct
 #define LCD_START_BURST_Pos 2
 #define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos)
 
-#define LCD_CR0_VPIX_Pos 0 //当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \
-                           //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767
+#define LCD_CR0_VPIX_Pos 0 /*当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \
+                           //当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 */
 #define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos)
-#define LCD_CR0_HPIX_Pos 10 //当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \
-                            //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023
+#define LCD_CR0_HPIX_Pos 10 /*当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \
+                            //当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 */
 #define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos)
 #define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转    1 DOTCLK在空闲时停在1
 #define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos)
@@ -3121,7 +2670,7 @@ typedef struct
 {
     __IO uint32_t DATA;
     __IO uint32_t ADDR;
-    __IO uint32_t ERASE;
+    __IO uint32_t SWM_ERASE;
     __IO uint32_t CACHE;
     __IO uint32_t CFG0;
     __IO uint32_t CFG1;
@@ -3376,8 +2925,8 @@ typedef struct
 #define RTC_TRIM_DEC_Pos 8
 #define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos)
 
-#define RTC_TRIMM_CYCLE_Pos 0 //用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \
-                              //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推
+#define RTC_TRIMM_CYCLE_Pos 0 /* 用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \
+                              //cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 */
 #define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos)
 #define RTC_TRIMM_INC_Pos 3
 #define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos)

bsp/swm320/libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s

@@ -79,7 +79,7 @@ __Vectors       DCD     __initial_sp               ; Top of Stack
                 DCD     GPIOA5_Handler
                 DCD     GPIOA6_Handler
                 DCD     GPIOA7_Handler
-                DCD     GPIOB0_Handler
+				DCD     GPIOB0_Handler
                 DCD     GPIOB1_Handler
                 DCD     GPIOB2_Handler
                 DCD     GPIOB3_Handler
@@ -157,262 +157,262 @@ Reset_Handler    PROC
 ; Dummy Exception Handlers (infinite loops which can be modified)
 
 NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
+                EXPORT  NMI_Handler             [WEAK]
                 B       .
                 ENDP
 
 HardFault_Handler PROC
-                EXPORT  HardFault_Handler          [WEAK]
+                EXPORT  HardFault_Handler       [WEAK]
                 B       .
                 ENDP
 
 MemManage_Handler PROC
-                EXPORT  MemManage_Handler          [WEAK]
+                EXPORT  MemManage_Handler       [WEAK]
                 B       .
                 ENDP
 
 BusFault_Handler PROC
-                EXPORT  BusFault_Handler           [WEAK]
+                EXPORT  BusFault_Handler        [WEAK]
                 B       .
                 ENDP
 
 UsageFault_Handler PROC
-                EXPORT  UsageFault_Handler         [WEAK]
+                EXPORT  UsageFault_Handler      [WEAK]
                 B       .
                 ENDP
 
 SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
+                EXPORT  SVC_Handler             [WEAK]
                 B       .
                 ENDP
 
 DebugMon_Handler PROC
-                EXPORT  DebugMon_Handler           [WEAK]
+                EXPORT  DebugMon_Handler        [WEAK]
                 B       .
                 ENDP
 
 PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
+                EXPORT  PendSV_Handler          [WEAK]
                 B       .
                 ENDP
 
 SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
+                EXPORT  SysTick_Handler         [WEAK]
                 B       .
                 ENDP
 
 GPIOA0_Handler PROC
-                EXPORT  GPIOA0_Handler            [WEAK]
+                EXPORT  GPIOA0_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA1_Handler PROC
-                EXPORT  GPIOA1_Handler            [WEAK]
+                EXPORT  GPIOA1_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA2_Handler PROC
-                EXPORT  GPIOA2_Handler            [WEAK]
+                EXPORT  GPIOA2_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA3_Handler PROC
-                EXPORT  GPIOA3_Handler            [WEAK]
+                EXPORT  GPIOA3_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA4_Handler PROC
-                EXPORT  GPIOA4_Handler            [WEAK]
+                EXPORT  GPIOA4_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA5_Handler PROC
-                EXPORT  GPIOA5_Handler            [WEAK]
+                EXPORT  GPIOA5_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA6_Handler PROC
-                EXPORT  GPIOA6_Handler            [WEAK]
+                EXPORT  GPIOA6_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOA7_Handler PROC
-                EXPORT  GPIOA7_Handler            [WEAK]
+                EXPORT  GPIOA7_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB0_Handler PROC
-                EXPORT  GPIOB0_Handler            [WEAK]
+                EXPORT  GPIOB0_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB1_Handler PROC
-                EXPORT  GPIOB1_Handler            [WEAK]
+                EXPORT  GPIOB1_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB2_Handler PROC
-                EXPORT  GPIOB2_Handler            [WEAK]
+                EXPORT  GPIOB2_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB3_Handler PROC
-                EXPORT  GPIOB3_Handler            [WEAK]
+                EXPORT  GPIOB3_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB4_Handler PROC
-                EXPORT  GPIOB4_Handler            [WEAK]
+                EXPORT  GPIOB4_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB5_Handler PROC
-                EXPORT  GPIOB5_Handler            [WEAK]
+                EXPORT  GPIOB5_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB6_Handler PROC
-                EXPORT  GPIOB6_Handler            [WEAK]
+                EXPORT  GPIOB6_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOB7_Handler PROC
-                EXPORT  GPIOB7_Handler            [WEAK]
+                EXPORT  GPIOB7_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC0_Handler PROC
-                EXPORT  GPIOC0_Handler            [WEAK]
+                EXPORT  GPIOC0_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC1_Handler PROC
-                EXPORT  GPIOC1_Handler            [WEAK]
+                EXPORT  GPIOC1_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC2_Handler PROC
-                EXPORT  GPIOC2_Handler            [WEAK]
+                EXPORT  GPIOC2_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC3_Handler PROC
-                EXPORT  GPIOC3_Handler            [WEAK]
+                EXPORT  GPIOC3_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC4_Handler PROC
-                EXPORT  GPIOC4_Handler            [WEAK]
+                EXPORT  GPIOC4_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC5_Handler PROC
-                EXPORT  GPIOC5_Handler            [WEAK]
+                EXPORT  GPIOC5_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC6_Handler PROC
-                EXPORT  GPIOC6_Handler            [WEAK]
+                EXPORT  GPIOC6_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOC7_Handler PROC
-                EXPORT  GPIOC7_Handler            [WEAK]
+                EXPORT  GPIOC7_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM0_Handler PROC
-                EXPORT  GPIOM0_Handler            [WEAK]
+                EXPORT  GPIOM0_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM1_Handler PROC
-                EXPORT  GPIOM1_Handler            [WEAK]
+                EXPORT  GPIOM1_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM2_Handler PROC
-                EXPORT  GPIOM2_Handler            [WEAK]
+                EXPORT  GPIOM2_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM3_Handler PROC
-                EXPORT  GPIOM3_Handler            [WEAK]
+                EXPORT  GPIOM3_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM4_Handler PROC
-                EXPORT  GPIOM4_Handler            [WEAK]
+                EXPORT  GPIOM4_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM5_Handler PROC
-                EXPORT  GPIOM5_Handler            [WEAK]
+                EXPORT  GPIOM5_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM6_Handler PROC
-                EXPORT  GPIOM6_Handler            [WEAK]
+                EXPORT  GPIOM6_Handler          [WEAK]
                 B       .
                 ENDP
 
 GPIOM7_Handler PROC
-                EXPORT  GPIOM7_Handler            [WEAK]
+                EXPORT  GPIOM7_Handler          [WEAK]
                 B       .
                 ENDP
 
 DMA_Handler PROC
-                EXPORT  DMA_Handler            [WEAK]
+                EXPORT  DMA_Handler             [WEAK]
                 B       .
                 ENDP
 
 LCD_Handler PROC
-                EXPORT  LCD_Handler            [WEAK]
+                EXPORT  LCD_Handler             [WEAK]
                 B       .
                 ENDP
 
 NORFLC_Handler PROC
-                EXPORT  NORFLC_Handler            [WEAK]
+                EXPORT  NORFLC_Handler          [WEAK]
                 B       .
                 ENDP
 
 CAN_Handler PROC
-                EXPORT  CAN_Handler            [WEAK]
+                EXPORT  CAN_Handler             [WEAK]
                 B       .
                 ENDP
 
 PULSE_Handler PROC
-                EXPORT  PULSE_Handler          [WEAK]
+                EXPORT  PULSE_Handler           [WEAK]
                 B       .
                 ENDP
 
 WDT_Handler PROC
-                EXPORT  WDT_Handler            [WEAK]
+                EXPORT  WDT_Handler             [WEAK]
                 B       .
                 ENDP
 
 PWM_Handler PROC
-                EXPORT  PWM_Handler            [WEAK]
+                EXPORT  PWM_Handler             [WEAK]
                 B       .
                 ENDP
 
 UART0_Handler PROC
-                EXPORT  UART0_Handler            [WEAK]
+                EXPORT  UART0_Handler           [WEAK]
                 B       .
                 ENDP
 
 UART1_Handler PROC
-                EXPORT  UART1_Handler            [WEAK]
+                EXPORT  UART1_Handler           [WEAK]
                 B       .
                 ENDP
 
 UART2_Handler PROC
-                EXPORT  UART2_Handler            [WEAK]
+                EXPORT  UART2_Handler           [WEAK]
                 B       .
                 ENDP
 
 UART3_Handler PROC
-                EXPORT  UART3_Handler            [WEAK]
+                EXPORT  UART3_Handler           [WEAK]
                 B       .
                 ENDP
 
@@ -437,12 +437,12 @@ ADC0_Handler PROC
                 ENDP
 
 RTC_Handler PROC
-                EXPORT  RTC_Handler            [WEAK]
+                EXPORT  RTC_Handler             [WEAK]
                 B       .
                 ENDP
 
 BOD_Handler PROC
-                EXPORT  BOD_Handler            [WEAK]
+                EXPORT  BOD_Handler             [WEAK]
                 B       .
                 ENDP
 
@@ -452,32 +452,32 @@ SDIO_Handler PROC
                 ENDP
 
 GPIOA_Handler PROC
-                EXPORT  GPIOA_Handler            [WEAK]
+                EXPORT  GPIOA_Handler           [WEAK]
                 B       .
                 ENDP
 
 GPIOB_Handler PROC
-                EXPORT  GPIOB_Handler            [WEAK]
+                EXPORT  GPIOB_Handler           [WEAK]
                 B       .
                 ENDP
 
 GPIOC_Handler PROC
-                EXPORT  GPIOC_Handler            [WEAK]
+                EXPORT  GPIOC_Handler           [WEAK]
                 B       .
                 ENDP
 
 GPIOM_Handler PROC
-                EXPORT  GPIOM_Handler            [WEAK]
+                EXPORT  GPIOM_Handler           [WEAK]
                 B       .
                 ENDP
 
 GPION_Handler PROC
-                EXPORT  GPION_Handler            [WEAK]
+                EXPORT  GPION_Handler           [WEAK]
                 B       .
                 ENDP
 
 GPIOP_Handler PROC
-                EXPORT  GPIOP_Handler            [WEAK]
+                EXPORT  GPIOP_Handler           [WEAK]
                 B       .
                 ENDP
 
@@ -487,7 +487,7 @@ ADC1_Handler PROC
                 ENDP
 
 FPU_Handler PROC
-                EXPORT  FPU_Handler            [WEAK]
+                EXPORT  FPU_Handler             [WEAK]
                 B       .
                 ENDP
 

bsp/swm320/libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s

@@ -1,242 +1,406 @@
-    .syntax unified
-    .arch armv7-m
-	.thumb
-
-/* Memory Model
-   The HEAP starts at the end of the DATA section and grows upward.
-   
-   The STACK starts at the end of the RAM and grows downward     */
-    .section .stack
-    .align 3
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    0x4000
-__StackTop:
-
-
-    .section .heap
-    .align 3
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .space    0x4000
-__HeapLimit:
-
-
-    .section .isr_vector
-    .align 2
-    .globl __isr_vector
-__isr_vector:
-    .long    __StackTop            
-    .long    Reset_Handler         
-    .long    NMI_Handler          
-    .long    HardFault_Handler     
-    .long    MemManage_Handler     
-    .long    BusFault_Handler      
-    .long    UsageFault_Handler   
-    .long    0                    
-    .long    0                    
-    .long    0                    
-    .long    0                     
-    .long    SVC_Handler          
-    .long    DebugMon_Handler     
-    .long    0                     
-    .long    PendSV_Handler           
-    .long    SysTick_Handler         
-
-    /* External interrupts */
-    .long     GPIOA0_Handler
-    .long     GPIOA1_Handler
-    .long     GPIOA2_Handler
-    .long     GPIOA3_Handler
-    .long     GPIOA4_Handler
-    .long     GPIOA5_Handler
-    .long     GPIOA6_Handler
-    .long     GPIOA7_Handler
-    .long     GPIOB0_Handler
-    .long     GPIOB1_Handler
-    .long     GPIOB2_Handler
-    .long     GPIOB3_Handler
-    .long     GPIOB4_Handler
-    .long     GPIOB5_Handler
-    .long     GPIOB6_Handler
-    .long     GPIOB7_Handler
-    .long     GPIOC0_Handler
-    .long     GPIOC1_Handler
-    .long     GPIOC2_Handler
-    .long     GPIOC3_Handler
-    .long     GPIOC4_Handler
-    .long     GPIOC5_Handler
-    .long     GPIOC6_Handler
-    .long     GPIOC7_Handler                                 
-    .long     GPIOM0_Handler
-    .long     GPIOM1_Handler
-    .long     GPIOM2_Handler
-    .long     GPIOM3_Handler
-    .long     GPIOM4_Handler
-    .long     GPIOM5_Handler
-    .long     GPIOM6_Handler
-    .long     GPIOM7_Handler                                            
-    .long     DMA_Handler
-    .long     LCD_Handler
-    .long     NORFLC_Handler
-    .long     CAN_Handler
-    .long     PULSE_Handler
-    .long     WDT_Handler
-    .long     PWM_Handler
-    .long     UART0_Handler
-    .long     UART1_Handler
-    .long     UART2_Handler
-    .long     UART3_Handler
-    .long     Default_Handler
-    .long     I2C0_Handler
-    .long     I2C1_Handler
-    .long     SPI0_Handler
-    .long     ADC0_Handler
-    .long     RTC_Handler
-    .long     BOD_Handler
-    .long     SDIO_Handler
-    .long     GPIOA_Handler
-    .long     GPIOB_Handler
-    .long     GPIOC_Handler
-    .long     GPIOM_Handler
-    .long     GPION_Handler
-    .long     GPIOP_Handler
-    .long     ADC1_Handler
-    .long     FPU_Handler
-    .long     SPI1_Handler
-    .long     TIMR0_Handler
-    .long     TIMR1_Handler
-    .long     TIMR2_Handler
-    .long     TIMR3_Handler
-    .long     TIMR4_Handler
-    .long     TIMR5_Handler
-
-    .section .text.Reset_Handler
-    .align 2
-    .globl    Reset_Handler
-    .type     Reset_Handler, %function
-Reset_Handler:
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by symbols evaluated in linker script.  */
-    ldr    sp, =__StackTop    		 /* set stack pointer */
-
-    ldr    r1, =__data_load__
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-.Lflash_to_ram_loop:
-    cmp     r2, r3
-    ittt    lo
-    ldrlo   r0, [r1], #4
-    strlo   r0, [r2], #4
-    blo    .Lflash_to_ram_loop
-
-
-    ldr    r2, =__bss_start__
-    ldr    r3, =__bss_end__
-
-.Lbss_to_ram_loop:
-    cmp     r2, r3
-    ittt    lo
-    movlo   r0, #0
-    strlo   r0, [r2], #4
-    blo    .Lbss_to_ram_loop
-
-    ldr    r0, =main
-    bx     r0
-    .pool    
-
-
-    .text
-/* Macro to define default handlers. 
-   Default handler will be weak symbol and just dead loops. */
-    .macro    def_default_handler    handler_name
-    .align 1
-    .thumb_func
-    .weak    \handler_name
-    .type    \handler_name, %function
-\handler_name :
-    b    .
-    .endm
-
-    def_default_handler    NMI_Handler
-    def_default_handler    HardFault_Handler
-    def_default_handler    MemManage_Handler
-    def_default_handler    BusFault_Handler
-    def_default_handler    UsageFault_Handler
-    def_default_handler    SVC_Handler
-    def_default_handler    DebugMon_Handler
-    def_default_handler    PendSV_Handler
-    def_default_handler    SysTick_Handler
-
-    def_default_handler    GPIOA0_Handler
-    def_default_handler    GPIOA1_Handler
-    def_default_handler    GPIOA2_Handler
-    def_default_handler    GPIOA3_Handler
-    def_default_handler    GPIOA4_Handler
-    def_default_handler    GPIOA5_Handler
-    def_default_handler    GPIOA6_Handler
-    def_default_handler    GPIOA7_Handler
-    def_default_handler    GPIOB0_Handler
-    def_default_handler    GPIOB1_Handler
-    def_default_handler    GPIOB2_Handler
-    def_default_handler    GPIOB3_Handler
-    def_default_handler    GPIOB4_Handler
-    def_default_handler    GPIOB5_Handler
-    def_default_handler    GPIOB6_Handler
-    def_default_handler    GPIOB7_Handler
-    def_default_handler    GPIOC0_Handler
-    def_default_handler    GPIOC1_Handler
-    def_default_handler    GPIOC2_Handler
-    def_default_handler    GPIOC3_Handler
-    def_default_handler    GPIOC4_Handler
-    def_default_handler    GPIOC5_Handler
-    def_default_handler    GPIOC6_Handler
-    def_default_handler    GPIOC7_Handler                                 
-    def_default_handler    GPIOM0_Handler
-    def_default_handler    GPIOM1_Handler
-    def_default_handler    GPIOM2_Handler
-    def_default_handler    GPIOM3_Handler
-    def_default_handler    GPIOM4_Handler
-    def_default_handler    GPIOM5_Handler
-    def_default_handler    GPIOM6_Handler
-    def_default_handler    GPIOM7_Handler                                            
-    def_default_handler    DMA_Handler
-    def_default_handler    LCD_Handler
-    def_default_handler    NORFLC_Handler
-    def_default_handler    CAN_Handler
-    def_default_handler    PULSE_Handler
-    def_default_handler    WDT_Handler
-    def_default_handler    PWM_Handler
-    def_default_handler    UART0_Handler
-    def_default_handler    UART1_Handler
-    def_default_handler    UART2_Handler
-    def_default_handler    UART3_Handler
-    def_default_handler    I2C0_Handler
-    def_default_handler    I2C1_Handler
-    def_default_handler    SPI0_Handler
-    def_default_handler    ADC0_Handler
-    def_default_handler    RTC_Handler
-    def_default_handler    BOD_Handler
-    def_default_handler    SDIO_Handler
-    def_default_handler    GPIOA_Handler
-    def_default_handler    GPIOB_Handler
-    def_default_handler    GPIOC_Handler
-    def_default_handler    GPIOM_Handler
-    def_default_handler    GPION_Handler
-    def_default_handler    GPIOP_Handler
-    def_default_handler    ADC1_Handler
-    def_default_handler    FPU_Handler
-    def_default_handler    SPI1_Handler
-    def_default_handler    TIMR0_Handler
-    def_default_handler    TIMR1_Handler
-    def_default_handler    TIMR2_Handler
-    def_default_handler    TIMR3_Handler
-    def_default_handler    TIMR4_Handler
-    def_default_handler    TIMR5_Handler
-
-    def_default_handler    Default_Handler
-
-    .end
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack    		 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+/* Call the application's entry point.*/
+  bl  entry
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b  Infinite_Loop
+    .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+    .section  .isr_vector,"a",%progbits
+    .type  g_pfnVectors, %object
+    .size  g_pfnVectors, .-g_pfnVectors
+    
+g_pfnVectors:
+    .word  _estack
+    .word  Reset_Handler
+    .word  NMI_Handler
+    .word  HardFault_Handler
+    .word  MemManage_Handler
+    .word  BusFault_Handler
+    .word  UsageFault_Handler
+    .word  0
+    .word  0
+    .word  0
+    .word  0
+    .word  SVC_Handler
+    .word  DebugMon_Handler
+    .word  0
+    .word  PendSV_Handler
+    .word  SysTick_Handler
+  
+    /* External Interrupts */
+    .word     GPIOA0_Handler
+    .word     GPIOA1_Handler
+    .word     GPIOA2_Handler
+    .word     GPIOA3_Handler
+    .word     GPIOA4_Handler
+    .word     GPIOA5_Handler
+    .word     GPIOA6_Handler
+    .word     GPIOA7_Handler
+    .word     GPIOB0_Handler
+    .word     GPIOB1_Handler
+    .word     GPIOB2_Handler
+    .word     GPIOB3_Handler
+    .word     GPIOB4_Handler
+    .word     GPIOB5_Handler
+    .word     GPIOB6_Handler
+    .word     GPIOB7_Handler
+    .word     GPIOC0_Handler
+    .word     GPIOC1_Handler
+    .word     GPIOC2_Handler
+    .word     GPIOC3_Handler
+    .word     GPIOC4_Handler
+    .word     GPIOC5_Handler
+    .word     GPIOC6_Handler
+    .word     GPIOC7_Handler                                 
+    .word     GPIOM0_Handler
+    .word     GPIOM1_Handler
+    .word     GPIOM2_Handler
+    .word     GPIOM3_Handler
+    .word     GPIOM4_Handler
+    .word     GPIOM5_Handler
+    .word     GPIOM6_Handler
+    .word     GPIOM7_Handler                                            
+    .word     DMA_Handler
+    .word     LCD_Handler
+    .word     NORFLC_Handler
+    .word     CAN_Handler
+    .word     PULSE_Handler
+    .word     WDT_Handler
+    .word     PWM_Handler
+    .word     UART0_Handler
+    .word     UART1_Handler
+    .word     UART2_Handler
+    .word     UART3_Handler
+    .word     0
+    .word     I2C0_Handler
+    .word     I2C1_Handler
+    .word     SPI0_Handler
+    .word     ADC0_Handler
+    .word     RTC_Handler
+    .word     ANAC_Handler
+    .word     SDIO_Handler
+    .word     GPIOA_Handler
+    .word     GPIOB_Handler
+    .word     GPIOC_Handler
+    .word     GPIOM_Handler
+    .word     GPION_Handler
+    .word     GPIOP_Handler
+    .word     ADC1_Handler
+    .word     FPU_Handler
+    .word     SPI1_Handler
+    .word     TIMR0_Handler
+    .word     TIMR1_Handler
+    .word     TIMR2_Handler
+    .word     TIMR3_Handler
+    .word     TIMR4_Handler
+    .word     TIMR5_Handler  
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+    .weak      NMI_Handler
+    .thumb_set NMI_Handler,Default_Handler
+
+    .weak      HardFault_Handler
+    .thumb_set HardFault_Handler,Default_Handler
+
+    .weak      MemManage_Handler
+    .thumb_set MemManage_Handler,Default_Handler
+
+    .weak      BusFault_Handler
+    .thumb_set BusFault_Handler,Default_Handler
+
+    .weak      UsageFault_Handler
+    .thumb_set UsageFault_Handler,Default_Handler
+
+    .weak      SVC_Handler
+    .thumb_set SVC_Handler,Default_Handler
+
+    .weak      DebugMon_Handler
+    .thumb_set DebugMon_Handler,Default_Handler
+
+    .weak      PendSV_Handler
+    .thumb_set PendSV_Handler,Default_Handler
+
+    .weak      SysTick_Handler
+    .thumb_set SysTick_Handler,Default_Handler              
+
+    .weak      GPIOA0_Handler                   
+    .thumb_set GPIOA0_Handler,Default_Handler      
+
+    .weak      GPIOA1_Handler      
+    .thumb_set GPIOA1_Handler,Default_Handler
+
+    .weak      GPIOA2_Handler            
+    .thumb_set GPIOA2_Handler,Default_Handler
+
+    .weak      GPIOA3_Handler                  
+    .thumb_set GPIOA3_Handler,Default_Handler
+
+    .weak      GPIOA4_Handler         
+    .thumb_set GPIOA4_Handler,Default_Handler
+
+    .weak      GPIOA5_Handler      
+    .thumb_set GPIOA5_Handler,Default_Handler
+
+    .weak      GPIOA6_Handler         
+    .thumb_set GPIOA6_Handler,Default_Handler
+
+    .weak      GPIOA7_Handler         
+    .thumb_set GPIOA7_Handler,Default_Handler
+
+    .weak      GPIOB0_Handler         
+    .thumb_set GPIOB0_Handler,Default_Handler 
+
+    .weak      GPIOB1_Handler         
+    .thumb_set GPIOB1_Handler,Default_Handler
+
+    .weak      GPIOB2_Handler         
+    .thumb_set GPIOB2_Handler,Default_Handler
+
+    .weak      GPIOB3_Handler               
+    .thumb_set GPIOB3_Handler,Default_Handler
+
+    .weak      GPIOB4_Handler               
+    .thumb_set GPIOB4_Handler,Default_Handler
+
+    .weak      GPIOB5_Handler               
+    .thumb_set GPIOB5_Handler,Default_Handler
+
+    .weak      GPIOB6_Handler               
+    .thumb_set GPIOB6_Handler,Default_Handler 
+
+    .weak      GPIOB7_Handler              
+    .thumb_set GPIOB7_Handler,Default_Handler
+
+    .weak      GPIOC0_Handler               
+    .thumb_set GPIOC0_Handler,Default_Handler
+
+    .weak      GPIOC1_Handler               
+    .thumb_set GPIOC1_Handler,Default_Handler
+
+    .weak      GPIOC2_Handler      
+    .thumb_set GPIOC2_Handler,Default_Handler
+
+    .weak      GPIOC3_Handler   
+    .thumb_set GPIOC3_Handler,Default_Handler
+
+    .weak      GPIOC4_Handler            
+    .thumb_set GPIOC4_Handler,Default_Handler
+
+    .weak      GPIOC5_Handler            
+    .thumb_set GPIOC5_Handler,Default_Handler
+
+    .weak      GPIOC6_Handler      
+    .thumb_set GPIOC6_Handler,Default_Handler
+
+    .weak      GPIOC7_Handler   
+    .thumb_set GPIOC7_Handler,Default_Handler
+
+    .weak      GPIOM0_Handler            
+    .thumb_set GPIOM0_Handler,Default_Handler
+
+    .weak      GPIOM1_Handler            
+    .thumb_set GPIOM1_Handler,Default_Handler
+
+    .weak      GPIOM2_Handler            
+    .thumb_set GPIOM2_Handler,Default_Handler
+
+    .weak      GPIOM3_Handler   
+    .thumb_set GPIOM3_Handler,Default_Handler
+
+    .weak      GPIOM4_Handler   
+    .thumb_set GPIOM4_Handler,Default_Handler
+
+    .weak      GPIOM5_Handler   
+    .thumb_set GPIOM5_Handler,Default_Handler
+
+    .weak      GPIOM6_Handler   
+    .thumb_set GPIOM6_Handler,Default_Handler
+        
+    .weak      GPIOM7_Handler            
+    .thumb_set GPIOM7_Handler,Default_Handler
+
+    .weak      DMA_Handler            
+    .thumb_set DMA_Handler,Default_Handler
+
+    .weak      LCD_Handler      
+    .thumb_set LCD_Handler,Default_Handler
+
+    .weak      NORFLC_Handler      
+    .thumb_set NORFLC_Handler,Default_Handler
+                
+    .weak      CAN_Handler               
+    .thumb_set CAN_Handler,Default_Handler
+
+    .weak      PULSE_Handler               
+    .thumb_set PULSE_Handler,Default_Handler
+
+    .weak      WDT_Handler         
+    .thumb_set WDT_Handler,Default_Handler
+
+    .weak      PWM_Handler               
+    .thumb_set PWM_Handler,Default_Handler
+
+    .weak      UART0_Handler            
+    .thumb_set UART0_Handler,Default_Handler
+
+    .weak      UART1_Handler            
+    .thumb_set UART1_Handler,Default_Handler
+
+    .weak      UART2_Handler            
+    .thumb_set UART2_Handler,Default_Handler
+
+    .weak      UART3_Handler               
+    .thumb_set UART3_Handler,Default_Handler
+
+    .weak      I2C0_Handler               
+    .thumb_set I2C0_Handler,Default_Handler
+
+    .weak      I2C1_Handler               
+    .thumb_set I2C1_Handler,Default_Handler
+
+    .weak      SPI0_Handler               
+    .thumb_set SPI0_Handler,Default_Handler
+
+    .weak      ADC0_Handler               
+    .thumb_set ADC0_Handler,Default_Handler
+
+    .weak      RTC_Handler      
+    .thumb_set RTC_Handler,Default_Handler
+
+    .weak      ANAC_Handler               
+    .thumb_set ANAC_Handler,Default_Handler
+
+    .weak      SDIO_Handler               
+    .thumb_set SDIO_Handler,Default_Handler
+
+    .weak      GPIOA_Handler               
+    .thumb_set GPIOA_Handler,Default_Handler
+
+    .weak      GPIOB_Handler      
+    .thumb_set GPIOB_Handler,Default_Handler
+
+    .weak      GPIOC_Handler   
+    .thumb_set GPIOC_Handler,Default_Handler
+
+    .weak      GPIOM_Handler   
+    .thumb_set GPIOM_Handler,Default_Handler
+
+    .weak      GPION_Handler                  
+    .thumb_set GPION_Handler,Default_Handler  
+
+    .weak      GPIOP_Handler                  
+    .thumb_set GPIOP_Handler,Default_Handler 
+
+    .weak      ADC1_Handler                  
+    .thumb_set ADC1_Handler,Default_Handler 
+
+    .weak      FPU_Handler                  
+    .thumb_set FPU_Handler,Default_Handler 
+
+    .weak      SPI1_Handler                  
+    .thumb_set SPI1_Handler,Default_Handler 
+
+    .weak      TIMR0_Handler                  
+    .thumb_set TIMR0_Handler,Default_Handler 
+
+    .weak      TIMR1_Handler                  
+    .thumb_set TIMR1_Handler,Default_Handler 
+
+    .weak      TIMR2_Handler                  
+    .thumb_set TIMR2_Handler,Default_Handler 
+
+    .weak      TIMR3_Handler                  
+    .thumb_set TIMR3_Handler,Default_Handler 
+
+    .weak      TIMR4_Handler                  
+    .thumb_set TIMR4_Handler,Default_Handler 
+
+    .weak      TIMR5_Handler                  
+    .thumb_set TIMR5_Handler,Default_Handler 
+

bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.c

@@ -43,7 +43,8 @@
 
 /********************************** PLL 设定 **********************************************
  * VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV
- * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV         
+ * PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV    
+ * 注意：VCO输出频率需要在 [600MHz, 1200MHz] 之间
  *****************************************************************************************/
 #define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL
 
@@ -173,15 +174,29 @@ void SystemInit(void)
     }
 }
 
-void switchCLK_20MHz(void)
+static void delay_3ms(void)
 {
     uint32_t i;
 
+    if (((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) &&
+        ((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz
+    {
+        for (i = 0; i < 20; i++)
+            __NOP();
+    }
+    else
+    {
+        for (i = 0; i < 20000; i++)
+            __NOP();
+    }
+}
+
+void switchCLK_20MHz(void)
+{
     SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
                  (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
 
-    for (i = 0; i < 1000; i++)
-        __NOP();
+    delay_3ms();
 
     SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk;      //HFCK  <=  HRC
     SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK  <= HFCK
@@ -189,13 +204,10 @@ void switchCLK_20MHz(void)
 
 void switchCLK_40MHz(void)
 {
-    uint32_t i;
-
     SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
                  (1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz
 
-    for (i = 0; i < 1000; i++)
-        __NOP();
+    delay_3ms();
 
     SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk;      //HFCK  <=  HRC
     SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK  <= HFCK
@@ -203,14 +215,11 @@ void switchCLK_40MHz(void)
 
 void switchCLK_32KHz(void)
 {
-    uint32_t i;
-
     SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos);
 
     SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos);
 
-    for (i = 0; i < 100; i++)
-        __NOP();
+    delay_3ms();
 
     SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK  <=  LRC
     SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk;  //SYS_CLK  <= LFCK
@@ -218,12 +227,10 @@ void switchCLK_32KHz(void)
 
 void switchCLK_XTAL(void)
 {
-    uint32_t i;
-
     SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
 
-    for (i = 0; i < 1000; i++)
-        __NOP();
+    delay_3ms();
+    delay_3ms();
 
     SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK  <=  XTAL
     SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos);  //SYS_CLK  <= HFCK
@@ -231,13 +238,9 @@ void switchCLK_XTAL(void)
 
 void switchCLK_PLL(void)
 {
-    uint32_t i;
-
     PLLInit();
-    SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
 
-    for (i = 0; i < 10000; i++)
-        __NOP();
+    SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
 
     SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK  <=  PLL
     SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk;        //SYS_CLK  <= LFCK
@@ -245,15 +248,12 @@ void switchCLK_PLL(void)
 
 void PLLInit(void)
 {
-    uint32_t i;
-
     if (SYS_PLL_SRC == SYS_CLK_20MHz)
     {
         SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
                      (0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
 
-        for (i = 0; i < 1000; i++)
-            __NOP();
+        delay_3ms();
 
         SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC
     }
@@ -261,8 +261,8 @@ void PLLInit(void)
     {
         SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
 
-        for (i = 0; i < 20000; i++)
-            ;
+        delay_3ms();
+        delay_3ms();
 
         SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL
     }

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.c

@@ -126,32 +126,32 @@ void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[
 
     if (format == CAN_FRAME_STD)
     {
-        CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) |
-                             (0 << CAN_INFO_RTR_Pos) |
-                             (size << CAN_INFO_DLC_Pos);
+        CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
+                           (0 << CAN_INFO_RTR_Pos) |
+                           (size << CAN_INFO_DLC_Pos);
 
-        CANx->TXFRAME.DATA[0] = id >> 3;
-        CANx->TXFRAME.DATA[1] = id << 5;
+        CANx->FRAME.DATA[0] = id >> 3;
+        CANx->FRAME.DATA[1] = id << 5;
 
         for (i = 0; i < size; i++)
         {
-            CANx->TXFRAME.DATA[i + 2] = data[i];
+            CANx->FRAME.DATA[i + 2] = data[i];
         }
     }
     else //if(format == CAN_FRAME_EXT)
     {
-        CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) |
-                             (0 << CAN_INFO_RTR_Pos) |
-                             (size << CAN_INFO_DLC_Pos);
+        CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
+                           (0 << CAN_INFO_RTR_Pos) |
+                           (size << CAN_INFO_DLC_Pos);
 
-        CANx->TXFRAME.DATA[0] = id >> 21;
-        CANx->TXFRAME.DATA[1] = id >> 13;
-        CANx->TXFRAME.DATA[2] = id >> 5;
-        CANx->TXFRAME.DATA[3] = id << 3;
+        CANx->FRAME.DATA[0] = id >> 21;
+        CANx->FRAME.DATA[1] = id >> 13;
+        CANx->FRAME.DATA[2] = id >> 5;
+        CANx->FRAME.DATA[3] = id << 3;
 
         for (i = 0; i < size; i++)
         {
-            CANx->TXFRAME.DATA[i + 4] = data[i];
+            CANx->FRAME.DATA[i + 4] = data[i];
         }
     }
 
@@ -186,23 +186,23 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32
 {
     if (format == CAN_FRAME_STD)
     {
-        CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) |
-                             (1 << CAN_INFO_RTR_Pos) |
-                             (0 << CAN_INFO_DLC_Pos);
+        CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
+                           (1 << CAN_INFO_RTR_Pos) |
+                           (0 << CAN_INFO_DLC_Pos);
 
-        CANx->TXFRAME.DATA[0] = id >> 3;
-        CANx->TXFRAME.DATA[1] = id << 5;
+        CANx->FRAME.DATA[0] = id >> 3;
+        CANx->FRAME.DATA[1] = id << 5;
     }
     else //if(format == CAN_FRAME_EXT)
     {
-        CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) |
-                             (1 << CAN_INFO_RTR_Pos) |
-                             (0 << CAN_INFO_DLC_Pos);
-
-        CANx->TXFRAME.DATA[0] = id >> 21;
-        CANx->TXFRAME.DATA[1] = id >> 13;
-        CANx->TXFRAME.DATA[2] = id >> 5;
-        CANx->TXFRAME.DATA[3] = id << 3;
+        CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
+                           (1 << CAN_INFO_RTR_Pos) |
+                           (0 << CAN_INFO_DLC_Pos);
+
+        CANx->FRAME.DATA[0] = id >> 21;
+        CANx->FRAME.DATA[1] = id >> 13;
+        CANx->FRAME.DATA[2] = id >> 5;
+        CANx->FRAME.DATA[3] = id << 3;
     }
 
     if (once == 0)
@@ -226,27 +226,27 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32
 void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg)
 {
     uint32_t i;
-    msg->format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos;
+    msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos;
 
-    msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos;
-    msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos;
+    msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos;
+    msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos;
 
     if (msg->format == CAN_FRAME_STD)
     {
-        msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5);
+        msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5);
 
         for (i = 0; i < msg->size; i++)
         {
-            msg->data[i] = CANx->RXFRAME.DATA[i + 2];
+            msg->data[i] = CANx->FRAME.DATA[i + 2];
         }
     }
     else //if(msg->format == CAN_FRAME_EXT)
     {
-        msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3);
+        msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3);
 
         for (i = 0; i < msg->size; i++)
         {
-            msg->data[i] = CANx->RXFRAME.DATA[i + 4];
+            msg->data[i] = CANx->FRAME.DATA[i + 4];
         }
     }
 

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c

@@ -23,8 +23,8 @@
 
 /****************************************************************************************************************************************** 
 * 函数名称: GPIO_Init()
-* 功能说明:	引脚初始化，包含引脚方向、上拉电阻、下拉电阻、开漏输出
-* 输    入: GPIO_TypeDef * GPIOx	    指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP	
+* 功能说明:	引脚初始化，包含引脚方向、上拉电阻、下拉电阻
+* 输    入: GPIO_TypeDef * GPIOx	    指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP
 *			uint32_t n		       指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23
 *			uint32_t dir	       引脚方向，0 输入        1 输出
 *			uint32_t pull_up	   上拉电阻，0 关闭上拉    1 开启上拉

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h

@@ -20,8 +20,8 @@ uint32_t NORFL_Read(uint32_t addr);
 uint16_t NORFL_ReadID(uint32_t id_addr);
 
 /* 当前版本总线读只支持字读
-#define NORFL_Read8(addr)			*((volatile uint8_t  *)(NORFLM_BASE + addr))
-#define NORFL_Read16(addr)			*((volatile uint16_t *)(NORFLM_BASE + addr))    */
+#define NORFL_Read8(addr)   *((volatile uint8_t  *)(NORFLM_BASE + addr))
+#define NORFL_Read16(addr)  *((volatile uint16_t *)(NORFLM_BASE + addr))    */
 #define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr))
 
 #define NORFL_CMD_READ 0

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c

@@ -53,7 +53,7 @@ void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct)
     RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) |
                    (initStruct->Month << RTC_MONDAY_MON_Pos);
 
-    RTCx->YEAR = initStruct->Year - 1901;
+    RTCx->YEAR = initStruct->Year;
 
     RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos;
 
@@ -105,7 +105,7 @@ void RTC_Stop(RTC_TypeDef *RTCx)
 ******************************************************************************************************************************************/
 void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime)
 {
-    dateTime->Year = RTCx->YEAR + 1901;
+    dateTime->Year = RTCx->YEAR;
     dateTime->Month = (RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos;
     dateTime->Date = (RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos;
     dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos);

bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c

@@ -28,7 +28,7 @@
 *			uint32_t peroid			取值0--4294967295，单位为单片机系统时钟周期
 *			uint32_t mode			WDT_MODE_RESET 超时产生复位    WDT_MODE_INTERRUPT 超时产生中断
 * 输    出: 无
-* 注意事项: 复位使能时中断不起作用，因为计数周期结束时芯片直接复位了，无法响应中断
+* 注意事项: 无
 ******************************************************************************************************************************************/
 void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode)
 {
@@ -36,16 +36,18 @@ void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode)
 
     WDT_Stop(WDTx); //设置前先关闭
 
-    WDTx->LOAD = peroid;
-
     if (mode == WDT_MODE_RESET)
     {
+        WDTx->LOAD = peroid / 2; //第一个计数周期置位中断标志、第二个计数周期将芯片复位
+
         NVIC_DisableIRQ(WDT_IRQn);
 
         WDTx->CR |= (1 << WDT_CR_RSTEN_Pos);
     }
     else //mode == WDT_MODE_INTERRUPT
     {
+        WDTx->LOAD = peroid;
+
         NVIC_EnableIRQ(WDT_IRQn);
 
         WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos);

bsp/swm320/project.uvoptx

@@ -207,8 +207,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
-      <FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\libcpu\arm\common\showmem.c</PathWithFileName>
+      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -231,8 +231,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\libcpu\arm\common\showmem.c</PathWithFileName>
-      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
+      <FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -311,8 +311,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\dataqueue.c</PathWithFileName>
-      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
+      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -323,8 +323,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\pipe.c</PathWithFileName>
-      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
+      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -335,8 +335,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
-      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\pipe.c</PathWithFileName>
+      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -347,8 +347,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
-      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\waitqueue.c</PathWithFileName>
+      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -359,8 +359,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\drivers\src\waitqueue.c</PathWithFileName>
-      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\drivers\src\dataqueue.c</PathWithFileName>
+      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -391,8 +391,8 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>drivers\board.c</PathWithFileName>
-      <FilenameWithoutPath>board.c</FilenameWithoutPath>
+      <PathWithFileName>drivers\drv_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -415,15 +415,15 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>drivers\drv_gpio.c</PathWithFileName>
-      <FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
+      <PathWithFileName>drivers\board.c</PathWithFileName>
+      <FilenameWithoutPath>board.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
   </Group>
 
   <Group>
-    <GroupName>finsh</GroupName>
+    <GroupName>Finsh</GroupName>
     <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
@@ -447,18 +447,6 @@
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\cmd.c</PathWithFileName>
-      <FilenameWithoutPath>cmd.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>21</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
       <PathWithFileName>..\..\components\finsh\msh.c</PathWithFileName>
       <FilenameWithoutPath>msh.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
@@ -466,121 +454,13 @@
     </File>
     <File>
       <GroupNumber>5</GroupNumber>
-      <FileNumber>22</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_compiler.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_compiler.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>23</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_error.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_error.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>24</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_heap.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_heap.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>25</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_init.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_init.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>26</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_node.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_node.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>27</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_ops.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_ops.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>28</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_parser.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_parser.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>29</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_var.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_var.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>30</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_vm.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_vm.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>5</GroupNumber>
-      <FileNumber>31</FileNumber>
+      <FileNumber>21</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\finsh\finsh_token.c</PathWithFileName>
-      <FilenameWithoutPath>finsh_token.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\finsh\cmd.c</PathWithFileName>
+      <FilenameWithoutPath>cmd.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -594,157 +474,157 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>32</FileNumber>
+      <FileNumber>22</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\clock.c</PathWithFileName>
-      <FilenameWithoutPath>clock.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\mempool.c</PathWithFileName>
+      <FilenameWithoutPath>mempool.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>33</FileNumber>
+      <FileNumber>23</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\components.c</PathWithFileName>
-      <FilenameWithoutPath>components.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\thread.c</PathWithFileName>
+      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>34</FileNumber>
+      <FileNumber>24</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\device.c</PathWithFileName>
-      <FilenameWithoutPath>device.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\idle.c</PathWithFileName>
+      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>35</FileNumber>
+      <FileNumber>25</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\idle.c</PathWithFileName>
-      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\ipc.c</PathWithFileName>
+      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>36</FileNumber>
+      <FileNumber>26</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\ipc.c</PathWithFileName>
-      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\irq.c</PathWithFileName>
+      <FilenameWithoutPath>irq.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>37</FileNumber>
+      <FileNumber>27</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\irq.c</PathWithFileName>
-      <FilenameWithoutPath>irq.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\timer.c</PathWithFileName>
+      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>38</FileNumber>
+      <FileNumber>28</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\kservice.c</PathWithFileName>
-      <FilenameWithoutPath>kservice.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\device.c</PathWithFileName>
+      <FilenameWithoutPath>device.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>39</FileNumber>
+      <FileNumber>29</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\memheap.c</PathWithFileName>
-      <FilenameWithoutPath>memheap.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\kservice.c</PathWithFileName>
+      <FilenameWithoutPath>kservice.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>40</FileNumber>
+      <FileNumber>30</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\mempool.c</PathWithFileName>
-      <FilenameWithoutPath>mempool.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\components.c</PathWithFileName>
+      <FilenameWithoutPath>components.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>41</FileNumber>
+      <FileNumber>31</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\object.c</PathWithFileName>
-      <FilenameWithoutPath>object.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
+      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>42</FileNumber>
+      <FileNumber>32</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\scheduler.c</PathWithFileName>
-      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\object.c</PathWithFileName>
+      <FilenameWithoutPath>object.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>43</FileNumber>
+      <FileNumber>33</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\thread.c</PathWithFileName>
-      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\memheap.c</PathWithFileName>
+      <FilenameWithoutPath>memheap.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>44</FileNumber>
+      <FileNumber>34</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\src\timer.c</PathWithFileName>
-      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\src\clock.c</PathWithFileName>
+      <FilenameWithoutPath>clock.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -758,61 +638,61 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>45</FileNumber>
+      <FileNumber>35</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\libc.c</PathWithFileName>
-      <FilenameWithoutPath>libc.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\libc\compilers\armlibc\mem_std.c</PathWithFileName>
+      <FilenameWithoutPath>mem_std.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>46</FileNumber>
+      <FileNumber>36</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\mem_std.c</PathWithFileName>
-      <FilenameWithoutPath>mem_std.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
+      <FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>47</FileNumber>
+      <FileNumber>37</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
-      <FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\libc\compilers\armlibc\libc.c</PathWithFileName>
+      <FilenameWithoutPath>libc.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>48</FileNumber>
+      <FileNumber>38</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\common\stdlib.c</PathWithFileName>
-      <FilenameWithoutPath>stdlib.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\libc\compilers\common\time.c</PathWithFileName>
+      <FilenameWithoutPath>time.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>49</FileNumber>
+      <FileNumber>39</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>..\..\components\libc\compilers\common\time.c</PathWithFileName>
-      <FilenameWithoutPath>time.c</FilenameWithoutPath>
+      <PathWithFileName>..\..\components\libc\compilers\common\stdlib.c</PathWithFileName>
+      <FilenameWithoutPath>stdlib.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
@@ -826,127 +706,127 @@
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>50</FileNumber>
+      <FileNumber>40</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\CMSIS\DeviceSupport\system_SWM320.c</PathWithFileName>
-      <FilenameWithoutPath>system_SWM320.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_wdt.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>51</FileNumber>
+      <FileNumber>41</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_adc.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\CMSIS\DeviceSupport\system_SWM320.c</PathWithFileName>
+      <FilenameWithoutPath>system_SWM320.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>52</FileNumber>
+      <FileNumber>42</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_can.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_spi.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>53</FileNumber>
+      <FileNumber>43</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_crc.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_flash.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>54</FileNumber>
+      <FileNumber>44</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_dma.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_sdram.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>55</FileNumber>
+      <FileNumber>45</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_exti.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_pwm.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>56</FileNumber>
+      <FileNumber>46</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_flash.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_sram.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>57</FileNumber>
+      <FileNumber>47</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_gpio.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_lcd.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>58</FileNumber>
+      <FileNumber>48</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_i2c.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_gpio.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>59</FileNumber>
+      <FileNumber>49</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_lcd.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_timr.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>60</FileNumber>
+      <FileNumber>50</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -958,133 +838,133 @@
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>61</FileNumber>
-      <FileType>1</FileType>
+      <FileNumber>51</FileNumber>
+      <FileType>2</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_port.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</PathWithFileName>
+      <FilenameWithoutPath>startup_SWM320.s</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>62</FileNumber>
+      <FileNumber>52</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_pwm.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_can.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>63</FileNumber>
+      <FileNumber>53</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_rtc.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_i2c.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>64</FileNumber>
+      <FileNumber>54</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_sdio.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_port.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>65</FileNumber>
+      <FileNumber>55</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_sdram.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_uart.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>66</FileNumber>
+      <FileNumber>56</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_spi.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_dma.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>67</FileNumber>
+      <FileNumber>57</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_sram.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_crc.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>68</FileNumber>
+      <FileNumber>58</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_timr.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_sdio.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>69</FileNumber>
+      <FileNumber>59</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_uart.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_rtc.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>70</FileNumber>
+      <FileNumber>60</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</PathWithFileName>
-      <FilenameWithoutPath>SWM320_wdt.c</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_exti.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
     <File>
       <GroupNumber>8</GroupNumber>
-      <FileNumber>71</FileNumber>
-      <FileType>2</FileType>
+      <FileNumber>61</FileNumber>
+      <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
       <bDave2>0</bDave2>
-      <PathWithFileName>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</PathWithFileName>
-      <FilenameWithoutPath>startup_SWM320.s</FilenameWithoutPath>
+      <PathWithFileName>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</PathWithFileName>
+      <FilenameWithoutPath>SWM320_adc.c</FilenameWithoutPath>
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>

bsp/swm320/project.uvprojx

@@ -10,13 +10,13 @@
       <TargetName>rtthread</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
       <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>SWM320xE</Device>
           <Vendor>Synwit</Vendor>
-          <PackID>Synwit.SWM32_DFP.1.11.3</PackID>
+          <PackID>Synwit.SWM32_DFP.1.16.6</PackID>
           <PackURL>http://www.synwit.com/pack</PackURL>
           <Cpu>IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
@@ -339,7 +339,7 @@
               <MiscControls></MiscControls>
               <Define>RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
               <Undefine></Undefine>
-              <IncludePath>applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;libraries\CMSIS\CoreSupport;libraries\CMSIS\DeviceSupport;libraries\SWM320_StdPeriph_Driver</IncludePath>
+              <IncludePath>applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;libraries\CMSIS\CoreSupport;libraries\CMSIS\DeviceSupport;libraries\SWM320_StdPeriph_Driver;..\..\examples\utest\testcases\kernel</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -394,9 +394,9 @@
           <GroupName>CPU</GroupName>
           <Files>
             <File>
-              <FileName>backtrace.c</FileName>
+              <FileName>showmem.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
             </File>
             <File>
               <FileName>div0.c</FileName>
@@ -404,9 +404,9 @@
               <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
             </File>
             <File>
-              <FileName>showmem.c</FileName>
+              <FileName>backtrace.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
             <File>
               <FileName>cpuport.c</FileName>
@@ -439,14 +439,9 @@
               <FilePath>..\..\components\drivers\src\completion.c</FilePath>
             </File>
             <File>
-              <FileName>dataqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
-            </File>
-            <File>
-              <FileName>pipe.c</FileName>
+              <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
             </File>
             <File>
               <FileName>ringblk_buf.c</FileName>
@@ -454,15 +449,20 @@
               <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
             </File>
             <File>
-              <FileName>ringbuffer.c</FileName>
+              <FileName>pipe.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
             </File>
             <File>
               <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
             </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
             <File>
               <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
@@ -474,9 +474,9 @@
           <GroupName>Drivers</GroupName>
           <Files>
             <File>
-              <FileName>board.c</FileName>
+              <FileName>drv_gpio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\board.c</FilePath>
+              <FilePath>drivers\drv_gpio.c</FilePath>
             </File>
             <File>
               <FileName>drv_uart.c</FileName>
@@ -484,79 +484,29 @@
               <FilePath>drivers\drv_uart.c</FilePath>
             </File>
             <File>
-              <FileName>drv_gpio.c</FileName>
+              <FileName>board.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_gpio.c</FilePath>
+              <FilePath>drivers\board.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>finsh</GroupName>
+          <GroupName>Finsh</GroupName>
           <Files>
             <File>
               <FileName>shell.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\components\finsh\shell.c</FilePath>
             </File>
-            <File>
-              <FileName>cmd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\cmd.c</FilePath>
-            </File>
             <File>
               <FileName>msh.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\components\finsh\msh.c</FilePath>
             </File>
             <File>
-              <FileName>finsh_compiler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_error.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_heap.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_init.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_init.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_node.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_node.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_ops.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_parser.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_var.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_var.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_vm.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
-            </File>
-            <File>
-              <FileName>finsh_token.c</FileName>
+              <FileName>cmd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_token.c</FilePath>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -564,19 +514,14 @@
           <GroupName>Kernel</GroupName>
           <Files>
             <File>
-              <FileName>clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>components.c</FileName>
+              <FileName>mempool.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\components.c</FilePath>
+              <FilePath>..\..\src\mempool.c</FilePath>
             </File>
             <File>
-              <FileName>device.c</FileName>
+              <FileName>thread.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
+              <FilePath>..\..\src\thread.c</FilePath>
             </File>
             <File>
               <FileName>idle.c</FileName>
@@ -594,24 +539,24 @@
               <FilePath>..\..\src\irq.c</FilePath>
             </File>
             <File>
-              <FileName>kservice.c</FileName>
+              <FileName>timer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\kservice.c</FilePath>
+              <FilePath>..\..\src\timer.c</FilePath>
             </File>
             <File>
-              <FileName>memheap.c</FileName>
+              <FileName>device.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\memheap.c</FilePath>
+              <FilePath>..\..\src\device.c</FilePath>
             </File>
             <File>
-              <FileName>mempool.c</FileName>
+              <FileName>kservice.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\mempool.c</FilePath>
+              <FilePath>..\..\src\kservice.c</FilePath>
             </File>
             <File>
-              <FileName>object.c</FileName>
+              <FileName>components.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
+              <FilePath>..\..\src\components.c</FilePath>
             </File>
             <File>
               <FileName>scheduler.c</FileName>
@@ -619,25 +564,25 @@
               <FilePath>..\..\src\scheduler.c</FilePath>
             </File>
             <File>
-              <FileName>thread.c</FileName>
+              <FileName>object.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
+              <FilePath>..\..\src\object.c</FilePath>
             </File>
             <File>
-              <FileName>timer.c</FileName>
+              <FileName>memheap.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
+              <FilePath>..\..\src\memheap.c</FilePath>
+            </File>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
           <GroupName>libc</GroupName>
           <Files>
-            <File>
-              <FileName>libc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
-            </File>
             <File>
               <FileName>mem_std.c</FileName>
               <FileType>1</FileType>
@@ -649,54 +594,64 @@
               <FilePath>..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
             </File>
             <File>
-              <FileName>stdlib.c</FileName>
+              <FileName>libc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\libc\compilers\common\stdlib.c</FilePath>
+              <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
             </File>
             <File>
               <FileName>time.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\components\libc\compilers\common\time.c</FilePath>
             </File>
+            <File>
+              <FileName>stdlib.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\common\stdlib.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
           <GroupName>Libraries</GroupName>
           <Files>
+            <File>
+              <FileName>SWM320_wdt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</FilePath>
+            </File>
             <File>
               <FileName>system_SWM320.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\CMSIS\DeviceSupport\system_SWM320.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_adc.c</FileName>
+              <FileName>SWM320_spi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_can.c</FileName>
+              <FileName>SWM320_flash.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_crc.c</FileName>
+              <FileName>SWM320_sdram.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_dma.c</FileName>
+              <FileName>SWM320_pwm.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_exti.c</FileName>
+              <FileName>SWM320_sram.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_flash.c</FileName>
+              <FileName>SWM320_lcd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</FilePath>
             </File>
             <File>
               <FileName>SWM320_gpio.c</FileName>
@@ -704,14 +659,9 @@
               <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_i2c.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</FilePath>
-            </File>
-            <File>
-              <FileName>SWM320_lcd.c</FileName>
+              <FileName>SWM320_timr.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</FilePath>
             </File>
             <File>
               <FileName>SWM320_norflash.c</FileName>
@@ -719,59 +669,59 @@
               <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_port.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</FilePath>
+              <FileName>startup_SWM320.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</FilePath>
             </File>
             <File>
-              <FileName>SWM320_pwm.c</FileName>
+              <FileName>SWM320_can.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_rtc.c</FileName>
+              <FileName>SWM320_i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_sdio.c</FileName>
+              <FileName>SWM320_port.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_sdram.c</FileName>
+              <FileName>SWM320_uart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_spi.c</FileName>
+              <FileName>SWM320_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_sram.c</FileName>
+              <FileName>SWM320_crc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_timr.c</FileName>
+              <FileName>SWM320_sdio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_uart.c</FileName>
+              <FileName>SWM320_rtc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</FilePath>
             </File>
             <File>
-              <FileName>SWM320_wdt.c</FileName>
+              <FileName>SWM320_exti.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</FilePath>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</FilePath>
             </File>
             <File>
-              <FileName>startup_SWM320.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</FilePath>
+              <FileName>SWM320_adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/swm320/rtconfig.h

@@ -16,6 +16,9 @@
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
 
@@ -39,8 +42,8 @@
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart0"
-#define RT_VER_NUM 0x40003
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
 #define ARCH_ARM
 #define RT_USING_CPU_FFS
 #define ARCH_ARM_CORTEX_M
@@ -59,16 +62,17 @@
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -79,6 +83,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 
@@ -88,6 +93,7 @@
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
+#define RT_LIBC_DEFAULT_TIMEZONE 8
 
 /* Network */
 
@@ -109,6 +115,9 @@
 /* Utilities */
 
 
+/* RT-Thread Utestcases */
+
+
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
@@ -139,6 +148,8 @@
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
@@ -146,13 +157,15 @@
 /* peripheral libraries and drivers */
 
 
-/* miscellaneous packages */
+/* AI packages */
 
 
+/* miscellaneous packages */
+
 /* samples: kernel and components samples */
 
 
-/* games: games run on RT-Thread console */
+/* entertainment: terminal games and other interesting software packages */
 
 
 /* Hardware Drivers Config */
@@ -162,7 +175,7 @@
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_UART
-#define BSP_USING_UART0
+#define BSP_USING_UART1
 #define BSP_USING_GPIO
 
 /* Onboard Peripheral Drivers */