Merge branch 'master' into comp

bsp/bluetrum/ab32vg1-ab-prougen/README.md

@@ -68,6 +68,8 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
 
 本 BSP 为开发者提供 GCC 开发环境。下面介绍如何将系统运行起来。
 
+教学视频：https://www.bilibili.com/video/BV1RV411v75P/
+
 #### 硬件连接
 
 使用数据线连接开发板到 PC，打开电源开关。
@@ -94,13 +96,12 @@ msh >
 此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
 
 1. 在 bsp 下打开 env 工具。
-
 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
-
 3. 输入`pkgs --update`命令更新软件包。
-
 4. 输入`scons` 命令重新编译工程。
 
+更多细节请参见使用指南：https://ab32vg1-example.readthedocs.io/zh/latest/introduction.html
+
 ## 注意事项
 
 波特率默认为 1.5M，需要使用 [Downloader](https://github.com/BLUETRUM/Downloader) 下载 `.dcf` 到芯片，需要编译后自动下载，需要在 `Downloader` 中的下载的下拉窗中选择 `自动`；目前暂时屏蔽 uart1 打印

bsp/bluetrum/ab32vg1-ab-prougen/board/board.h

@@ -12,7 +12,13 @@
 #define BOARD_H__
 
 #include <rtthread.h>
-#include "ab32vgx.h"
-#include "drv_gpio.h"
+#include <ab32vgx.h>
+#ifdef RT_USING_PIN
+#include <drv_gpio.h>
+#endif
+#ifdef RT_USING_WDT
+#include <drv_wdt.h>
+#endif
+
 
 #endif

bsp/bluetrum/libraries/hal_drivers/drv_common.h

@@ -15,4 +15,6 @@
 #include <rthw.h>
 #include <rtdevice.h>
 
+#define GET_PIN(PORTx,PIN) (uint8_t)__AB32_GET_PIN_##PORTx(PIN)
+
 #endif // DRV_COMMON_H__

bsp/bluetrum/libraries/hal_drivers/drv_gpio.h

@@ -15,6 +15,10 @@
 #include "board.h"
 
 #define __AB32_PORT(port)   GPIO##port
+#define __AB32_GET_PIN_A(PIN)  PIN
+#define __AB32_GET_PIN_B(PIN)  8 + PIN
+#define __AB32_GET_PIN_E(PIN)  13 + PIN
+#define __AB32_GET_PIN_F(PIN)  21 + PIN
 
 int rt_hw_pin_init(void);
 

bsp/bluetrum/libraries/hal_drivers/drv_wdt.c

@@ -12,6 +12,8 @@
 
 #ifdef RT_USING_WDT
 
+#include <drv_wdt.h>
+
 // #define DRV_DEBUG
 #define LOG_TAG             "drv.wdt"
 #include <drv_log.h>
@@ -49,35 +51,35 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
 
         switch (*((rt_uint32_t *)arg))
         {
-        case 0:
+        case AB32_WDT_TIMEOUT_1MS:
             LOG_I("The watchdog timeout is set to 1ms");
             tmp |= (0xa << 24) | (0x00 << 20);
             break;
-        case 1:
+        case AB32_WDT_TIMEOUT_256MS:
             LOG_I("The watchdog timeout is set to 256ms");
             tmp |= (0xa << 24) | (0x01 << 20);
             break;
-        case 2:
+        case AB32_WDT_TIMEOUT_512MS:
             LOG_I("The watchdog timeout is set to 512ms");
             tmp |= (0xa << 24) | (0x02 << 20);
             break;
-        case 3:
+        case AB32_WDT_TIMEOUT_1024MS:
             LOG_I("The watchdog timeout is set to 1024ms");
             tmp |= (0xa << 24) | (0x03 << 20);
             break;
-        case 4:
+        case AB32_WDT_TIMEOUT_2048MS:
             LOG_I("The watchdog timeout is set to 2048ms");
             tmp |= (0xa << 24) | (0x04 << 20);
             break;
-        case 5:
+        case AB32_WDT_TIMEOUT_4096MS:
             LOG_I("The watchdog timeout is set to 4096ms");
             tmp |= (0xa << 24) | (0x05 << 20);
             break;
-        case 6:
+        case AB32_WDT_TIMEOUT_8192MS:
             LOG_I("The watchdog timeout is set to 8192ms");
             tmp |= (0xa << 24) | (0x06 << 20);
             break;
-        case 7:
+        case AB32_WDT_TIMEOUT_16384MS:
             LOG_I("The watchdog timeout is set to 16384ms");
             tmp |= (0xa << 24) | (0x07 << 20);
             break;
@@ -92,28 +94,28 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
     case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
         switch ((WDTCON >> 20) & 0x7)
         {
-        case 0:
+        case AB32_WDT_TIMEOUT_1MS:
             LOG_D("The watchdog timeout is set to 1ms");
             break;
-        case 1:
+        case AB32_WDT_TIMEOUT_256MS:
             LOG_D("The watchdog timeout is set to 256ms");
             break;
-        case 2:
+        case AB32_WDT_TIMEOUT_512MS:
             LOG_D("The watchdog timeout is set to 512ms");
             break;
-        case 3:
+        case AB32_WDT_TIMEOUT_1024MS:
             LOG_D("The watchdog timeout is set to 1024ms");
             break;
-        case 4:
+        case AB32_WDT_TIMEOUT_2048MS:
             LOG_D("The watchdog timeout is set to 2048ms");
             break;
-        case 5:
+        case AB32_WDT_TIMEOUT_4096MS:
             LOG_D("The watchdog timeout is set to 4096ms");
             break;
-        case 6:
+        case AB32_WDT_TIMEOUT_8192MS:
             LOG_D("The watchdog timeout is set to 8192ms");
             break;
-        case 7:
+        case AB32_WDT_TIMEOUT_16384MS:
             LOG_D("The watchdog timeout is set to 16384ms");
             break;
         default:

bsp/bluetrum/libraries/hal_drivers/drv_wdt.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020-2021, Bluetrum Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-03-11     Meco Man          first version
+ */
+
+#ifndef DRV_WDT_H__
+#define DRV_WDT_H__
+
+#define AB32_WDT_TIMEOUT_1MS        0
+#define AB32_WDT_TIMEOUT_256MS      1
+#define AB32_WDT_TIMEOUT_512MS      2
+#define AB32_WDT_TIMEOUT_1024MS     3
+#define AB32_WDT_TIMEOUT_2048MS     4
+#define AB32_WDT_TIMEOUT_4096MS     5
+#define AB32_WDT_TIMEOUT_8192MS     6
+#define AB32_WDT_TIMEOUT_16384MS    7
+
+#endif

bsp/gd32103c-eval/drivers/drv_gpio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32303e-eval/drivers/board.c

@@ -79,7 +79,7 @@ void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-#ifdef RT_USING_HEAP   
+#ifdef RT_USING_HEAP
     rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
 }

bsp/gd32303e-eval/drivers/board.h

@@ -19,7 +19,7 @@
 #include <gd32f30x.h>
 
 // <o> Internal SRAM memory size[Kbytes] <8-64>
-//	<i>Default: 64
+//  <i>Default: 64
 #ifdef __ICCARM__
 // Use *.icf ram symbal, to avoid hardcode.
 extern char __ICFEDIT_region_RAM_end__;

bsp/gd32303e-eval/drivers/drv_gpio.c

@@ -261,7 +261,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     /* GPIO Periph clock enable */
     rcu_periph_clock_enable(index->clk);
     pin_mode = GPIO_MODE_OUT_PP;
-    
+
    switch(mode)
    {
    case PIN_MODE_OUTPUT:
@@ -442,7 +442,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
             return RT_EINVAL;
         }
         irqmap = &pin_irq_map[hdr_index];
-   
+
         switch (pin_irq_hdr_tab[hdr_index].mode)
         {
             case PIN_IRQ_MODE_RISING:
@@ -463,14 +463,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
 
         /* enable and set interrupt priority */
         nvic_irq_enable(irqmap->irqno, 5U, 0U);
-        
+
         /* connect EXTI line to  GPIO pin */
         gpio_exti_source_select(index->port_src, index->pin_src);
 
         /* configure EXTI line */
         exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
         exti_interrupt_flag_clear((exti_line_enum)(index->pin));
-        
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
@@ -505,7 +505,7 @@ int rt_hw_pin_init(void)
     int result;
 
     result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_pin_init);
@@ -524,7 +524,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
     {
         pin_irq_hdr(exti_line);
         exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
-    } 
+    }
 }
 void EXTI0_IRQHandler(void)
 {

bsp/gd32303e-eval/drivers/drv_i2c.c

@@ -168,7 +168,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u
             *p_buffer = i2c_data_receive(i2c_periph);
 
             /* point to the next location where the byte read will be saved */
-            p_buffer++; 
+            p_buffer++;
 
             /* decrement the read bytes counter */
             data_byte--;
@@ -277,7 +277,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg
             }
         }
     }
-    
+
     ret = i;
 
 out:
@@ -287,7 +287,7 @@ out:
 }
 
 static const struct rt_i2c_bus_device_ops i2c_ops =
-{ 
+{
     gd32_i2c_xfer,
     RT_NULL,
     RT_NULL
@@ -324,7 +324,7 @@ int rt_hw_i2c_init(void)
 
         i2c_device.priv = (void *)&_i2c_bit_ops;
         rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
-    } 
+    }
 
 #else   /* register hardware I2C */
 

bsp/gd32303e-eval/drivers/drv_spi.c

@@ -119,7 +119,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
             spi_init_struct.prescale = SPI_PSC_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -135,7 +135,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
         break;
     }
-    
+
     /* MSB or LSB */
     if(configuration->mode & RT_SPI_MSB)
     {
@@ -145,7 +145,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
     {
         spi_init_struct.endian = SPI_ENDIAN_LSB;
     }
-    
+
     spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
     spi_init_struct.device_mode = SPI_MASTER;
     spi_init_struct.nss = SPI_NSS_SOFT;
@@ -181,7 +181,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -192,7 +192,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by gd32f3 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
@@ -267,8 +267,8 @@ int gd32_hw_spi_init(void)
     rcu_periph_clock_enable(RCU_SPI0);
     /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
     gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
-    gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); 
-    
+    gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
+
 #endif
 #ifdef RT_USING_SPI1
     static struct rt_spi_bus spi_bus1;
@@ -287,7 +287,7 @@ int gd32_hw_spi_init(void)
     static struct rt_spi_bus spi_bus2;
     spi_bus2.parent.user_data = (void *)SPI2;
 
-    result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); 
+    result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops);
 
     rcu_periph_clock_enable(RCU_SPI2);
     rcu_periph_clock_enable(RCU_GPIOB);

bsp/gd32303e-eval/drivers/drv_spi_flash.c

@@ -30,7 +30,7 @@ static int rt_hw_gd25q40_init(void)
     static rt_base_t gd25q_cs_pin;                       /* SPI设备CS片选引脚 */
 
     gd25q_cs_pin = GD25Q_SPI_CS_PIN;
-    
+
     rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP);
 
     res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin);

bsp/gd32303e-eval/drivers/drv_usart.c

@@ -44,7 +44,7 @@ struct gd32_uart
     uint32_t tx_port;
     uint16_t tx_pin;
     uint32_t rx_port;
-    uint16_t rx_pin; 
+    uint16_t rx_pin;
 
     struct rt_serial_device * serial;
     char *device_name;
@@ -143,7 +143,7 @@ static const struct gd32_uart uarts[] = {
         "uart0",
     },
     #endif
-    
+
     #ifdef RT_USING_USART1
     {
         USART1,                                 // uart peripheral index
@@ -155,7 +155,7 @@ static const struct gd32_uart uarts[] = {
         "uart1",
     },
     #endif
-    
+
     #ifdef RT_USING_USART2
     {
         USART2,                                 // uart peripheral index
@@ -167,7 +167,7 @@ static const struct gd32_uart uarts[] = {
         "uart2",
     },
     #endif
-    
+
     #ifdef RT_USING_UART3
     {
         UART3,                                 // uart peripheral index
@@ -179,7 +179,7 @@ static const struct gd32_uart uarts[] = {
         "uart3",
     },
     #endif
-    
+
     #ifdef RT_USING_UART4
     {
         UART4,                                 // uart peripheral index
@@ -228,9 +228,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (struct gd32_uart *)serial->parent.user_data;
-    
+
     gd32_uart_gpio_init(uart);
-    
+
     usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
 
     switch (cfg->data_bits)
@@ -310,7 +310,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
 
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-    
+
     return 1;
 }
 

bsp/gd32303e-eval/drivers/gd32f303e_eval.c

@@ -23,15 +23,15 @@ static uint32_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
 static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM1_GPIO_PORT, EVAL_COM2_GPIO_PORT};
 static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM1_GPIO_CLK, EVAL_COM2_GPIO_CLK};
 
-static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK, 
+static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK,
                                          LED4_GPIO_CLK, LED5_GPIO_CLK};
 
-static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT, 
+static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT,
                                   TAMPER_KEY_GPIO_PORT,
                                   USER_KEY1_GPIO_PORT,
                                   USER_KEY2_GPIO_PORT};
 static uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN, TAMPER_KEY_PIN,USER_KEY1_PIN,USER_KEY2_PIN};
-static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK, 
+static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK,
                                         TAMPER_KEY_GPIO_CLK,
                                         USER_KEY1_GPIO_CLK,
                                         USER_KEY2_GPIO_CLK};
@@ -47,7 +47,7 @@ static uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE,
                                        TAMPER_KEY_EXTI_PIN_SOURCE,
                                        USER_KEY1_EXTI_PIN_SOURCE,
                                        USER_KEY2_EXTI_PIN_SOURCE};
-static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn, 
+static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn,
                                  TAMPER_KEY_EXTI_IRQn,
                                  USER_KEY1_EXTI_IRQn,
                                  USER_KEY2_EXTI_IRQn};
@@ -66,7 +66,7 @@ void  gd_eval_led_init (led_typedef_enum lednum)
 {
     /* enable the led clock */
     rcu_periph_clock_enable(GPIO_CLK[lednum]);
-    /* configure led GPIO port */ 
+    /* configure led GPIO port */
     gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,GPIO_PIN[lednum]);
 
     GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
@@ -114,7 +114,7 @@ void gd_eval_led_off(led_typedef_enum lednum)
 */
 void gd_eval_led_toggle(led_typedef_enum lednum)
 {
-    gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], 
+    gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum],
                     (bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum])));
 }
 
@@ -184,7 +184,7 @@ void gd_eval_com_init(uint32_t com)
     }else if(EVAL_COM2 == com){
         com_id = 1U;
     }
-    
+
     /* enable GPIO clock */
     rcu_periph_clock_enable(COM_GPIO_CLK[com_id]);
 

bsp/gd32303e-eval/drivers/gd32f303e_eval.h

@@ -17,9 +17,9 @@
 #endif
 
 #include "gd32f30x.h"
-     
+
 /* exported types */
-typedef enum 
+typedef enum
 {
     LED2 = 0,
     LED3 = 1,
@@ -27,7 +27,7 @@ typedef enum
     LED5 = 3
 } led_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_WAKEUP = 0,
     KEY_TAMPER = 1,
@@ -35,7 +35,7 @@ typedef enum
     KEY_USER2 = 3
 } key_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_MODE_GPIO = 0,
     KEY_MODE_EXTI = 1
@@ -47,15 +47,15 @@ typedef enum
 #define LED2_PIN                         GPIO_PIN_0
 #define LED2_GPIO_PORT                   GPIOF
 #define LED2_GPIO_CLK                    RCU_GPIOF
-  
+
 #define LED3_PIN                         GPIO_PIN_1
 #define LED3_GPIO_PORT                   GPIOF
 #define LED3_GPIO_CLK                    RCU_GPIOF
-  
+
 #define LED4_PIN                         GPIO_PIN_2
 #define LED4_GPIO_PORT                   GPIOF
 #define LED4_GPIO_CLK                    RCU_GPIOF
-  
+
 #define LED5_PIN                         GPIO_PIN_3
 #define LED5_GPIO_PORT                   GPIOF
 #define LED5_GPIO_CLK                    RCU_GPIOF
@@ -85,7 +85,7 @@ typedef enum
 #define WAKEUP_KEY_EXTI_LINE             EXTI_0
 #define WAKEUP_KEY_EXTI_PORT_SOURCE      GPIO_PORT_SOURCE_GPIOA
 #define WAKEUP_KEY_EXTI_PIN_SOURCE       GPIO_PIN_SOURCE_0
-#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn  
+#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn
 
 /* tamper push-button */
 #define TAMPER_KEY_PIN                   GPIO_PIN_13

bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c

@@ -15,7 +15,7 @@
 
 /*!
     \brief      lcd peripheral initialize
-    \param[in]  none 
+    \param[in]  none
     \param[out] none
     \retval     none
 */
@@ -37,15 +37,15 @@ void exmc_lcd_init(void)
     gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
                                                          GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
 
-    /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), 
+    /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9),
        PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */
-    gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | 
-                                                         GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | 
+    gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
+                                                         GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
                                                          GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
 
-    /* configure PE2(EXMC_A23) */ 
+    /* configure PE2(EXMC_A23) */
     gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
-    
+
     /* configure NOE and NWE */
     gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5);
 
@@ -106,7 +106,7 @@ uint16_t lcd_register_read(uint8_t register_id)
 {
     uint16_t data;
     *(__IO uint16_t *) (BANK0_LCD_C)= register_id;
-    data = *(__IO uint16_t *) (BANK0_LCD_D); 
+    data = *(__IO uint16_t *) (BANK0_LCD_D);
     return  data;
 }
 
@@ -154,13 +154,13 @@ void lcd_gram_write(uint16_t rgb_code)
 uint16_t lcd_gram_read(void)
 {
   uint16_t data;
-    
+
   /* write GRAM register (R22h) */
   *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022;
   /* dummy read (invalid data) */
-  *(__IO uint16_t *) (BANK0_LCD_D); 
+  *(__IO uint16_t *) (BANK0_LCD_D);
 
-  data = *(__IO uint16_t *) (BANK0_LCD_D); 
+  data = *(__IO uint16_t *) (BANK0_LCD_D);
   return data;
 }
 
@@ -219,7 +219,7 @@ void lcd_init(void)
     }else{
         return;
     }
-    
+
     for(i=50000;i>0;i--);
 }
 
@@ -277,16 +277,16 @@ void lcd_point_set(uint16_t x,uint16_t y,uint16_t point)
     \param[in]  x: the row-coordinate
     \param[in]  y: the column-coordinate
     \param[out] none
-    \retval     GRAM value of point 
+    \retval     GRAM value of point
 */
 uint16_t lcd_point_get(uint16_t x,uint16_t y)
 {
     uint16_t data;
-    
+
     if ((x > 240)||(y > 320)){
         return 0;
     }
-    
+
     lcd_cursor_set(x,y);
     data = lcd_gram_read();
 
@@ -410,7 +410,7 @@ void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t
     y = start_y;
 
     total = (end_x - start_x + 1) * (end_y - start_y + 1);
-    
+
     for(i = 0; i < total; i ++){
         /* set point according to the specified position and color */
         lcd_point_set(x,y,*picturepointer++);
@@ -441,7 +441,7 @@ void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_forma
     uint16_t i = 0, j = 0;
     uint8_t temp_char = 0;
     uint16_t temp_char_16 = 0;
-    
+
     if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */
         for (i = 0; i < 16; i++) {
             temp_char = ascii_8x16[((c - 0x20) * 16) + i];

bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h

@@ -155,7 +155,7 @@
 
 /* char format struct definitions */
 typedef struct
-{   
+{
     uint16_t font;              /*!< the type of font */
     uint16_t direction;         /*!< the direction of char */
     uint16_t char_color;        /*!< the color of char */

bsp/gd32450z-eval/drivers/board.h

@@ -22,7 +22,7 @@
 #define EXT_SDRAM_END      (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
 
 // <o> Internal SRAM memory size[Kbytes] <8-64>
-//	<i>Default: 64
+//  <i>Default: 64
 #ifdef __ICCARM__
 // Use *.icf ram symbal, to avoid hardcode.
 extern char __ICFEDIT_region_RAM_end__;

bsp/gd32450z-eval/drivers/drv_enet.c

@@ -35,16 +35,16 @@
 //#define EMAC_TX_DUMP
 
 #ifdef EMAC_DEBUG
-#define EMAC_TRACE	        rt_kprintf
+#define EMAC_TRACE          rt_kprintf
 #else
 #define EMAC_TRACE(...)
 #endif
 
-#define EMAC_RXBUFNB        	4
-#define EMAC_TXBUFNB        	2
+#define EMAC_RXBUFNB            4
+#define EMAC_TXBUFNB            2
 
-#define EMAC_PHY_AUTO		    0
-#define EMAC_PHY_10MBIT		    1
+#define EMAC_PHY_AUTO           0
+#define EMAC_PHY_10MBIT         1
 #define EMAC_PHY_100MBIT        2
 
 #define MAX_ADDR_LEN 6
@@ -55,14 +55,14 @@ struct gd32_emac
 
     rt_uint8_t phy_mode;
     /* interface address info. */
-    rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 
     struct rt_synopsys_eth * ETHERNET_MAC;
     IRQn_Type ETHER_MAC_IRQ;
-    
+
     EMAC_DMADESCTypeDef  *DMATxDescToSet;
     EMAC_DMADESCTypeDef  *DMARxDescToGet;
-    
+
 #pragma pack(4)
     EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB];
 #pragma pack(4)
@@ -71,7 +71,7 @@ struct gd32_emac
     rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
 #pragma pack(4)
     rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
-    
+
     struct rt_semaphore tx_buf_free;
 };
 
@@ -548,14 +548,14 @@ static void enet_gpio_config(void)
     rcu_periph_clock_enable(RCU_GPIOG);
     rcu_periph_clock_enable(RCU_GPIOH);
     rcu_periph_clock_enable(RCU_GPIOI);
-  
+
     gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8);
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
     gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8);
-  
+
     /* enable SYSCFG clock */
     rcu_periph_clock_enable(RCU_SYSCFG);
-  
+
     /* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */
     rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4);
     syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII);
@@ -563,31 +563,31 @@ static void enet_gpio_config(void)
     /* PA1: ETH_RMII_REF_CLK */
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
     gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1);
-    
+
     /* PA2: ETH_MDIO */
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2);
     gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2);
-    
+
     /* PA7: ETH_RMII_CRS_DV */
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7);
-    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);   
-    
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);
+
     gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1);
     gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2);
     gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7);
-    
+
     /* PB11: ETH_RMII_TX_EN */
     gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11);
     gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11);
-    
+
     /* PB12: ETH_RMII_TXD0 */
     gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
     gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12);
-    
+
     /* PB13: ETH_RMII_TXD1 */
     gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
-    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);   
-    
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);
+
     gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11);
     gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12);
     gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13);
@@ -599,11 +599,11 @@ static void enet_gpio_config(void)
     /* PC4: ETH_RMII_RXD0 */
     gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4);
     gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4);
-    
+
     /* PC5: ETH_RMII_RXD1 */
     gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5);
-    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); 
-    
+    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5);
+
     gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1);
     gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4);
     gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5);
@@ -613,17 +613,17 @@ static void enet_gpio_config(void)
 int rt_hw_gd32_eth_init(void)
 {
     rt_kprintf("rt_gd32_eth_init...\n");
-    
+
     /* enable ethernet clock  */
     rcu_periph_clock_enable(RCU_ENET);
     rcu_periph_clock_enable(RCU_ENETTX);
     rcu_periph_clock_enable(RCU_ENETRX);
-    
+
     nvic_configuration();
-  
+
     /* configure the GPIO ports for ethernet pins */
     enet_gpio_config();
-    
+
     /* set autonegotiation mode */
     gd32_emac_device0.phy_mode = EMAC_PHY_AUTO;
     gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0;
@@ -638,16 +638,16 @@ int rt_hw_gd32_eth_init(void)
     gd32_emac_device0.dev_addr[4] = 0x34;
     gd32_emac_device0.dev_addr[5] = 0x56;
 
-    gd32_emac_device0.parent.parent.init		 = gd32_emac_init;
-    gd32_emac_device0.parent.parent.open		 = gd32_emac_open;
-    gd32_emac_device0.parent.parent.close	 = gd32_emac_close;
-    gd32_emac_device0.parent.parent.read		 = gd32_emac_read;
-    gd32_emac_device0.parent.parent.write	 = gd32_emac_write;
-    gd32_emac_device0.parent.parent.control	 = gd32_emac_control;
+    gd32_emac_device0.parent.parent.init         = gd32_emac_init;
+    gd32_emac_device0.parent.parent.open         = gd32_emac_open;
+    gd32_emac_device0.parent.parent.close    = gd32_emac_close;
+    gd32_emac_device0.parent.parent.read         = gd32_emac_read;
+    gd32_emac_device0.parent.parent.write    = gd32_emac_write;
+    gd32_emac_device0.parent.parent.control  = gd32_emac_control;
     gd32_emac_device0.parent.parent.user_data = RT_NULL;
 
-    gd32_emac_device0.parent.eth_rx			 = gd32_emac_rx;
-    gd32_emac_device0.parent.eth_tx			 = gd32_emac_tx;
+    gd32_emac_device0.parent.eth_rx          = gd32_emac_rx;
+    gd32_emac_device0.parent.eth_tx          = gd32_emac_tx;
 
     /* init tx buffer free semaphore */
     rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);

bsp/gd32450z-eval/drivers/drv_exmc_sdram.c

@@ -47,7 +47,7 @@ static void delay_1ms(volatile uint32_t count)
 
 /*!
     \brief      sdram peripheral initialize
-    \param[in]  sdram_device: specifie the SDRAM device 
+    \param[in]  sdram_device: specifie the SDRAM device
     \param[out] none
     \retval     none
 */
@@ -71,7 +71,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     rcu_periph_clock_enable(RCU_GPIOH);
 
     /* common GPIO configuration */
-    /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */ 
+    /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */
     gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
     gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
     gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
@@ -107,11 +107,11 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
                                                                      GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
 
     /* A10(PG0),A11(PG1),A12(PG2),A14(PG4),A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */
-    gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | 
+    gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
                                    GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
-    gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | 
+    gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
                                                          GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
-    gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | 
+    gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
                                                                      GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
 
     /* specify which SDRAM to read and write */
@@ -126,7 +126,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     /* LMRD: 2 clock cycles */
     sdram_timing_init_struct.load_mode_register_delay = 2;
     /* XSRD: min = 67ns */
-    sdram_timing_init_struct.exit_selfrefresh_delay = 7; 
+    sdram_timing_init_struct.exit_selfrefresh_delay = 7;
     /* RASD: min=42ns , max=120k (ns) */
     sdram_timing_init_struct.row_address_select_delay = 5;
     /* ARFD: min=60ns */
@@ -144,9 +144,9 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13;
     sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B;
     sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK;
-    sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK; 
+    sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK;
     sdram_init_struct.write_protection = DISABLE;
-    sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK;  
+    sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK;
     sdram_init_struct.brust_read_switch = ENABLE;
     sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_HCLK;
     sdram_init_struct.timing  = &sdram_timing_init_struct;
@@ -158,7 +158,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.bank_select = bank_select;
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
     sdram_command_init_struct.mode_register_content = 0;
-    /* wait until the SDRAM controller is ready */ 
+    /* wait until the SDRAM controller is ready */
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -174,7 +174,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
     sdram_command_init_struct.mode_register_content = 0;
     /* wait until the SDRAM controller is ready */
-    timeout = SDRAM_TIMEOUT; 
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -186,8 +186,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.bank_select = bank_select;
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK;
     sdram_command_init_struct.mode_register_content = 0;
-    /* wait until the SDRAM controller is ready */ 
-    timeout = SDRAM_TIMEOUT; 
+    /* wait until the SDRAM controller is ready */
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -207,8 +207,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
     sdram_command_init_struct.mode_register_content = command_content;
 
-    /* wait until the SDRAM controller is ready */ 
-    timeout = SDRAM_TIMEOUT; 
+    /* wait until the SDRAM controller is ready */
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -221,8 +221,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     /* (7.81 us * SDCLK_Freq) - 20 */
     exmc_sdram_refresh_count_set(761);
 
-    /* wait until the SDRAM controller is ready */ 
-    timeout = SDRAM_TIMEOUT; 
+    /* wait until the SDRAM controller is ready */
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -258,20 +258,20 @@ void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t offset)
 void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writeaddr, uint32_t numbytetowrite)
 {
     uint32_t temp_addr;
-    
+
     /* Select the base address according to EXMC_Bank */
     if(sdram_device == EXMC_SDRAM_DEVICE0){
         temp_addr = SDRAM_DEVICE0_ADDR;
     }else{
         temp_addr = SDRAM_DEVICE1_ADDR;
     }
-    
+
      /* While there is data to write */
     for(; numbytetowrite != 0; numbytetowrite--) {
         /* Transfer data to the memory */
         *(uint8_t *) (temp_addr + writeaddr) = *pbuffer++;
 
-        /* Increment the address*/  
+        /* Increment the address*/
         writeaddr += 1;
     }
 }
@@ -288,19 +288,19 @@ void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writea
 void sdram_readbuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t readaddr, uint32_t numbytetoread)
 {
     uint32_t temp_addr;
-    
+
     /* select the base address according to EXMC_Bank */
     if(sdram_device == EXMC_SDRAM_DEVICE0){
         temp_addr = SDRAM_DEVICE0_ADDR;
     }else{
         temp_addr = SDRAM_DEVICE1_ADDR;
     }
-    
+
     /* while there is data to read */
     for(; numbytetoread != 0; numbytetoread--){
         /* read a byte from the memory */
         *pbuffer++ = *(uint8_t*) (temp_addr + readaddr);
-    
+
         /* increment the address */
         readaddr += 1;
     }

bsp/gd32450z-eval/drivers/drv_lcd.c

@@ -41,7 +41,7 @@ static struct rt_device_graphic_info _lcd_info;
 static struct rt_device lcd;
 
 /*!
-    \brief      configure TLI GPIO  
+    \brief      configure TLI GPIO
     \param[in]  none
     \param[out] none
     \retval     none
@@ -57,34 +57,34 @@ static void tli_gpio_config(void)
     rcu_periph_clock_enable(RCU_GPIOG);
 
     /* configure HSYNC(PC6), VSYNC(PA4), PCLK(PG7), DE(PF10) */
-    /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), 
+    /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0),
                  LCD_G7(PD3), LCD_G6(PC7), LCD_G5(PB11), LCD_G4(PB10), LCD_G3(PG10), LCD_G2(PA6),
                  LCD_B7(PB9), LCD_B6(PB8), LCD_B5(PA3), LCD_B4(PG12), LCD_B3(PG11) */
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3);  
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3);
     gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_4);
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6);  
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); 
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11);  
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); 
-    
-    gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);  
-    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);     
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6);
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12);
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11);
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8);
+
+    gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);
+    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);
     //gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11);
-    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);     
+    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);
     gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9);
-    
-    gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6);     
+
+    gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6);
     gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7);
-    
-    gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3);     
 
-    gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10);     
-    
-    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6);     
+    gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3);
+
+    gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10);
+
+    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6);
     gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_7);
     gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_10);
-    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11);     
-    gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12);    
+    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11);
+    gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12);
 
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_6
     |GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12);
@@ -123,15 +123,15 @@ static void lcd_config(void)
     lcd_ctrl_line_config();
     lcd_disable();
     lcd_enable();
-    
+
     /* configure the GPIO of TLI */
     tli_gpio_config();
     /* configure the LCD_SPI */
-    lcd_spi_config(); 
+    lcd_spi_config();
 
     /* power on the LCD */
     //lcd_power_on();
-	lcd_power_on3();  //New Version 3.5" TFT RGB Hardware needs use this initilize funtion  ---By xufei 2016.10.21
+    lcd_power_on3();  //New Version 3.5" TFT RGB Hardware needs use this initilize funtion  ---By xufei 2016.10.21
 }
 
 /*!
@@ -144,7 +144,7 @@ static void tli_config(void)
 {
     tli_parameter_struct               tli_init_struct;
     tli_layer_parameter_struct         tli_layer_init_struct;
- 
+
     rcu_periph_clock_enable(RCU_TLI);
 
     /* configure the PLLSAI clock to generate lcd clock */
@@ -156,52 +156,52 @@ static void tli_config(void)
     if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){
         while(1);
     }
-    
+
     /* TLI initialization */
     tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW;
     tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW;
     tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW;
     tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI;
-    
+
     /* LCD display timing configuration */
     tli_init_struct.synpsz_hpsz   = LCD_480_320_HSYNC;
     tli_init_struct.synpsz_vpsz   = LCD_480_320_VSYNC;
-    tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; 
-    tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;  
+    tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP;
+    tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;
     tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP;
     tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP;
-    tli_init_struct.totalsz_htsz  = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; 
+    tli_init_struct.totalsz_htsz  = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP;
     tli_init_struct.totalsz_vtsz  = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP;
-    
+
     /* LCD background color configure*/
     tli_init_struct.backcolor_red   = 0x00;
     tli_init_struct.backcolor_green = 0x00;
-    tli_init_struct.backcolor_blue  = 0x00; 
+    tli_init_struct.backcolor_blue  = 0x00;
     tli_init(&tli_init_struct);
-    
+
     lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
     RT_ASSERT(lcd_framebuffer != NULL);
     rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT);
 
     /* TLI layer0 configuration */
     tli_layer_init_struct.layer_window_leftpos          = tli_init_struct.backpsz_hbpsz + 1;
-    tli_layer_init_struct.layer_window_rightpos         = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; 
+    tli_layer_init_struct.layer_window_rightpos         = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH;
     tli_layer_init_struct.layer_window_toppos           = tli_init_struct.backpsz_vbpsz + 1;
     tli_layer_init_struct.layer_window_bottompos        = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT;
-    
+
     tli_layer_init_struct.layer_ppf                     = LAYER_PPF_RGB565;
     tli_layer_init_struct.layer_sa                      = 0xFF;
-    tli_layer_init_struct.layer_default_blue            = 0x00;        
-    tli_layer_init_struct.layer_default_green           = 0x00;       
-    tli_layer_init_struct.layer_default_red             = 0x00;         
+    tli_layer_init_struct.layer_default_blue            = 0x00;
+    tli_layer_init_struct.layer_default_green           = 0x00;
+    tli_layer_init_struct.layer_default_red             = 0x00;
     tli_layer_init_struct.layer_default_alpha           = 0x00;
-    tli_layer_init_struct.layer_acf1                    = LAYER_ACF1_PASA;    
+    tli_layer_init_struct.layer_acf1                    = LAYER_ACF1_PASA;
     tli_layer_init_struct.layer_acf2                    = LAYER_ACF2_PASA;
-    tli_layer_init_struct.layer_frame_bufaddr           = (uint32_t)lcd_framebuffer;    
-    tli_layer_init_struct.layer_frame_line_length       = ((RT_HW_LCD_WIDTH * 2) + 3); 
+    tli_layer_init_struct.layer_frame_bufaddr           = (uint32_t)lcd_framebuffer;
+    tli_layer_init_struct.layer_frame_line_length       = ((RT_HW_LCD_WIDTH * 2) + 3);
     tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2);
-    tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; 
-    
+    tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT;
+
     tli_layer_init(LAYER0, &tli_layer_init_struct);
 }
 
@@ -210,21 +210,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
     switch (cmd)
     {
     case RTGRAPHIC_CTRL_RECT_UPDATE:
-    {        
+    {
         memcpy((void *)lcd_framebuffer, _rt_framebuffer, sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
     }
     break;
-    
+
     case RTGRAPHIC_CTRL_POWERON:
         break;
-    
+
     case RTGRAPHIC_CTRL_POWEROFF:
         break;
-    
+
     case RTGRAPHIC_CTRL_GET_INFO:
         memcpy(args, &_lcd_info, sizeof(_lcd_info));
         break;
-    
+
     case RTGRAPHIC_CTRL_SET_MODE:
         break;
     }
@@ -235,21 +235,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
 int gd32_hw_lcd_init(void)
 {
     _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, 32);
-    if (_rt_framebuffer == RT_NULL) 
+    if (_rt_framebuffer == RT_NULL)
         return -1; /* no memory yet */
-    
+
     lcd_config();
     tli_config();
-    tli_layer_enable(LAYER0);  
+    tli_layer_enable(LAYER0);
     tli_reload_config(TLI_FRAME_BLANK_RELOAD_EN);
     tli_enable();
-    
+
     _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
     _lcd_info.pixel_format   = RTGRAPHIC_PIXEL_FORMAT_RGB565;
     _lcd_info.framebuffer    = (void *)_rt_framebuffer;
     _lcd_info.width          = RT_HW_LCD_WIDTH;
     _lcd_info.height         = RT_HW_LCD_HEIGHT;
-    
+
     lcd.type    = RT_Device_Class_Graphic;
     lcd.init    = NULL;
     lcd.open    = NULL;
@@ -258,10 +258,10 @@ int gd32_hw_lcd_init(void)
     lcd.write   = NULL;
     lcd.control = rt_lcd_control;
     lcd.user_data = (void *)&_lcd_info;
-    
+
     /* register lcd device to RT-Thread */
     rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
-    
+
     return 0;
 }
 INIT_DEVICE_EXPORT(gd32_hw_lcd_init);

bsp/gd32450z-eval/drivers/drv_spi.c

@@ -11,7 +11,7 @@
  * Date           Author       Notes
  * 2017-06-05     tanek        first implementation.
  */
- 
+
 #include "drv_spi.h"
 
 #include <board.h>
@@ -32,7 +32,7 @@
 #ifdef DEBUG
 #define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
 #else
-#define DEBUG_PRINTF(...)   
+#define DEBUG_PRINTF(...)
 #endif
 
 /* private rt-thread spi ops function */
@@ -48,16 +48,16 @@ static struct rt_spi_ops gd32_spi_ops =
 static rt_err_t configure(struct rt_spi_device* device,
                           struct rt_spi_configuration* configuration)
 {
-    struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;	
+    struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
     struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data;
-    
+
     spi_parameter_struct spi_init_struct;
 
     uint32_t spi_periph = f4_spi->spi_periph;
 
 
-	RT_ASSERT(device != RT_NULL);
-	RT_ASSERT(configuration != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
 
     /* data_width */
     if(configuration->data_width <= 8)
@@ -129,7 +129,7 @@ static rt_err_t configure(struct rt_spi_device* device,
             spi_init_struct.prescale = SPI_PSC_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -137,15 +137,15 @@ static rt_err_t configure(struct rt_spi_device* device,
         break;
     case RT_SPI_MODE_1:
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
-        break;        
+        break;
     case RT_SPI_MODE_2:
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
-        break;    
+        break;
     case RT_SPI_MODE_3:
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
         break;
     }
-    
+
     /* MSB or LSB */
     if(configuration->mode & RT_SPI_MSB)
     {
@@ -155,18 +155,18 @@ static rt_err_t configure(struct rt_spi_device* device,
     {
         spi_init_struct.endian = SPI_ENDIAN_LSB;
     }
-    
+
     spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
     spi_init_struct.device_mode = SPI_MASTER;
     spi_init_struct.nss = SPI_NSS_SOFT;
-    
+
     spi_crc_off(spi_periph);
 
     /* init SPI */
     spi_init(spi_periph, &spi_init_struct);
     /* Enable SPI_MASTER */
-	spi_enable(spi_periph);
-    
+    spi_enable(spi_periph);
+
     return RT_EOK;
 };
 
@@ -178,9 +178,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
     struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
     uint32_t spi_periph = f4_spi->spi_periph;
 
-	RT_ASSERT(device != NULL);
-	RT_ASSERT(message != NULL);
-	
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+
     /* take CS */
     if(message->cs_take)
     {
@@ -194,7 +194,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -205,12 +205,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by gd32f4 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
                 // Send the byte
-				spi_i2s_data_transmit(spi_periph, data);
+                spi_i2s_data_transmit(spi_periph, data);
 
                 //Wait until a data is received
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@@ -242,7 +242,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
                 // Send the byte
-				spi_i2s_data_transmit(spi_periph, data);
+                spi_i2s_data_transmit(spi_periph, data);
 
                 //Wait until a data is received
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@@ -260,7 +260,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
     /* release CS */
     if(message->cs_release)
     {
-		gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
+        gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
         DEBUG_PRINTF("spi release cs\n");
     }
 
@@ -274,7 +274,7 @@ static const struct gd32f4_spi spis[] = {
 #ifdef RT_USING_SPI0
     {SPI0, RCU_SPI0, &spi_bus[0]},
 #endif
-    
+
 #ifdef RT_USING_SPI1
     {SPI1, RCU_SPI1, &spi_bus[1]},
 #endif
@@ -286,11 +286,11 @@ static const struct gd32f4_spi spis[] = {
 #ifdef RT_USING_SPI3
     {SPI3, RCU_SPI3, &spi_bus[3]},
 #endif
-    
+
 #ifdef RT_USING_SPI4
     {SPI4, RCU_SPI4, &spi_bus[4]},
 #endif
-    
+
 #ifdef RT_USING_SPI5
     {SPI5, RCU_SPI5, &spi_bus[5]},
 #endif
@@ -310,9 +310,9 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
                             const char * spi_bus_name)
 {
     int i;
-    
+
     RT_ASSERT(spi_bus_name != RT_NULL);
-    
+
     for (i = 0; i < ARR_LEN(spis); i++)
     {
         if (spi_periph == spis[i].spi_periph)
@@ -323,7 +323,7 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
             return RT_EOK;
         }
     }
-    
+
     return RT_ERROR;
 }
 #endif

bsp/gd32450z-eval/drivers/drv_spi.h

@@ -36,7 +36,7 @@ struct gd32_spi_cs
 
 /* public function */
 rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
-								//struct gd32_spi_bus * gd32_spi,
-								const char * spi_bus_name);
+                                //struct gd32_spi_bus * gd32_spi,
+                                const char * spi_bus_name);
 
 #endif // gd32F20X_40X_SPI_H_INCLUDED

bsp/gd32450z-eval/drivers/drv_spi_flash.c

@@ -32,8 +32,8 @@ static int rt_hw_spi5_init(void)
 {
     /* register spi bus */
     {
-		rt_err_t result;
-        
+        rt_err_t result;
+
         rcu_periph_clock_enable(RCU_GPIOG);
         rcu_periph_clock_enable(RCU_SPI5);
 
@@ -42,36 +42,36 @@ static int rt_hw_spi5_init(void)
         gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
         gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
 
-		result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
+        result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
         if (result != RT_EOK)
-		{
-			return result;
-		}
+        {
+            return result;
+        }
     }
 
     /* attach cs */
     {
         static struct rt_spi_device spi_device;
         static struct gd32_spi_cs  spi_cs;
-		rt_err_t result;
-        
+        rt_err_t result;
+
         spi_cs.GPIOx = GPIOG;
         spi_cs.GPIO_Pin = GPIO_PIN_9;
-        
+
         /* SPI5_CS(PG9) GPIO pin configuration */
         gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9);
         gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
-        
+
         gpio_bit_set(GPIOG,GPIO_PIN_9);
 
         result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
-		if (result != RT_EOK)
-		{
-			return result;
-		}
+        if (result != RT_EOK)
+        {
+            return result;
+        }
     }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rt_hw_spi5_init);
 
@@ -83,7 +83,7 @@ static int rt_hw_spi_flash_with_sfud_init(void)
         return RT_ERROR;
     };
 
-	return RT_EOK;
+    return RT_EOK;
 }
 INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
 #endif

bsp/gd32450z-eval/drivers/drv_usart.c

@@ -37,7 +37,7 @@
 struct gd32_uart
 {
     uint32_t uart_periph;           //Todo: 3bits
-    IRQn_Type irqn;                 //Todo: 7bits    
+    IRQn_Type irqn;                 //Todo: 7bits
     rcu_periph_enum per_clk;        //Todo: 5bits
     rcu_periph_enum tx_gpio_clk;    //Todo: 5bits
     rcu_periph_enum rx_gpio_clk;    //Todo: 5bits
@@ -48,7 +48,7 @@ struct gd32_uart
     uint16_t rx_af;                 //Todo: 4bits
     uint16_t rx_pin;                //Todo: 4bits
 
-    struct rt_serial_device * serial;    
+    struct rt_serial_device * serial;
     char *device_name;
 };
 
@@ -193,7 +193,7 @@ static const struct gd32_uart uarts[] = {
         "uart0",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART1
     {
         USART1,                                 // uart peripheral index
@@ -205,7 +205,7 @@ static const struct gd32_uart uarts[] = {
         "uart1",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART2
     {
         USART2,                                 // uart peripheral index
@@ -217,7 +217,7 @@ static const struct gd32_uart uarts[] = {
         "uart2",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART3
     {
         UART3,                                 // uart peripheral index
@@ -229,7 +229,7 @@ static const struct gd32_uart uarts[] = {
         "uart3",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART4
     {
         UART4,                                 // uart peripheral index
@@ -253,7 +253,7 @@ static const struct gd32_uart uarts[] = {
         "uart5",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART6
     {
         UART6,                                 // uart peripheral index
@@ -309,7 +309,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
     /* configure USART Rx as alternate function push-pull */
     gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin);
     gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin);
-    
+
     NVIC_SetPriority(uart->irqn, 0);
     NVIC_EnableIRQ(uart->irqn);
 }
@@ -322,9 +322,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (struct gd32_uart *)serial->parent.user_data;
-    
+
     gd32_uart_gpio_init(uart);
-    
+
     usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
 
     switch (cfg->data_bits)
@@ -404,7 +404,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
 
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-    
+
     return 1;
 }
 
@@ -456,7 +456,7 @@ int gd32_hw_usart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     int i;
 
-    
+
     for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
     {
         uarts[i].serial->ops    = &gd32_uart_ops;

bsp/gd32450z-eval/drivers/gd32f450z_eval.h

@@ -17,23 +17,23 @@
 #endif
 
 #include "gd32f4xx.h"
-     
+
 /* exported types */
-typedef enum 
+typedef enum
 {
     LED1 = 0,
     LED2 = 1,
     LED3 = 2
 } led_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_WAKEUP = 0,
     KEY_TAMPER = 1,
     KEY_USER = 2
 } key_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_MODE_GPIO = 0,
     KEY_MODE_EXTI = 1
@@ -45,11 +45,11 @@ typedef enum
 #define LED1_PIN                         GPIO_PIN_4
 #define LED1_GPIO_PORT                   GPIOD
 #define LED1_GPIO_CLK                    RCU_GPIOD
-  
+
 #define LED2_PIN                         GPIO_PIN_5
 #define LED2_GPIO_PORT                   GPIOD
 #define LED2_GPIO_CLK                    RCU_GPIOD
-  
+
 #define LED3_PIN                         GPIO_PIN_3
 #define LED3_GPIO_PORT                   GPIOG
 #define LED3_GPIO_CLK                    RCU_GPIOG
@@ -83,7 +83,7 @@ typedef enum
 #define WAKEUP_KEY_EXTI_LINE             EXTI_0
 #define WAKEUP_KEY_EXTI_PORT_SOURCE      EXTI_SOURCE_GPIOA
 #define WAKEUP_KEY_EXTI_PIN_SOURCE       EXTI_SOURCE_PIN0
-#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn  
+#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn
 
 /* user push-button */
 #define USER_KEY_PIN                     GPIO_PIN_14

bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c

@@ -108,8 +108,8 @@ void lcd_spi_config(void)
     gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13|GPIO_PIN_14);
     gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13|GPIO_PIN_14);
     spi_i2s_deinit(SPI5);
-    
-    if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){    
+
+    if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){
         spi_init_struct.trans_mode           = SPI_TRANSMODE_FULLDUPLEX;
         spi_init_struct.device_mode          = SPI_MASTER;
         spi_init_struct.frame_size           = SPI_FRAMESIZE_8BIT;
@@ -155,7 +155,7 @@ void lcd_data_write(uint8_t value)
     /* set LCD_RS to send data */
     lcd_ctrl_line_set(LCD_RS_GPIO_PORT, LCD_RS_PIN);
 
-    /* reset LCD control line and send data */  
+    /* reset LCD control line and send data */
     lcd_disable();
     while(RESET == spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TBE)) ;
 
@@ -228,80 +228,80 @@ void lcd_power_on(void)
 }
 /**
   * @brief  New Version 3.5" TFT RGB Hardware needs add this initilize funtion  ---By xufei 2016.10.21
-						Modified by GAO HAIYANG, test pass, 17, Nov, 2016
+                        Modified by GAO HAIYANG, test pass, 17, Nov, 2016
   * @param  None
   * @retval None
   */
 void lcd_power_on3(void)
 {
-		lcd_command_write(0xC0);//power control1 command/w/
-		lcd_data_write(0x0A); // P-Gamma level//4.1875v
-		lcd_data_write(0x0A); // N-Gamma level
-		lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
-		lcd_data_write(0x41);
-		lcd_data_write(0x07); // VCI1 = 2.5V
-		lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
-		lcd_data_write(0x33);
-		lcd_command_write(0xC5);//VCOM control
-		lcd_data_write(0x00);  //NV memory is not programmed
-		lcd_data_write(0x42); // VCM Setting
-		lcd_data_write(0x80); // VCM Register Enable
-		lcd_command_write(0xB0);      //interface mode control //Polarity Setting
-		lcd_data_write(0x02);
-		lcd_command_write(0xB1);//frame rate control for normal mode
-		lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
-		lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
-		lcd_command_write(0xB4);//dispaly inversion control
-		lcd_data_write(0x00); // disable Z-inversion , column inversion
-		lcd_command_write(0xB6); //display function control// RM.DM Setting
-		lcd_data_write(0x70);////0xF0
-		lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
-		lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
-		lcd_command_write(0xB7); // Entry Mode
-		lcd_data_write(0x07); // disable low voltage detection, normal display, 
-		lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
-		lcd_data_write(0x36);
-		lcd_data_write(0xA5);
-		lcd_data_write(0xD3);
-		lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
-		lcd_data_write(0x80);
-		lcd_command_write(0xE5); // Page 1
-		lcd_data_write(0x01);
-		lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
-		lcd_data_write(0x00);
-		lcd_command_write(0xE5); // Page 0
-		lcd_data_write(0x00);
-		lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
-		lcd_data_write(0x36);
-		lcd_data_write(0xA5);
-		lcd_data_write(0x53);
-		lcd_command_write(0xE0); // Gamma setting
-		//y fine adjustment register for positive polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x35);
-		lcd_data_write(0x33);
-		//y gradient adjustment register for positive polarity
-		lcd_data_write(0x00);
-		//y amplitude adjustment register for positive polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x00);
-		//y fine adjustment register for negative polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x35);
-		lcd_data_write(0x33);
-		//y gradient adjustment register for negative polarity
-		lcd_data_write(0x00);
-		//y amplitude adjustment register for negative polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x00);
-		lcd_command_write(0x36); // memory data access control //
-		lcd_data_write(0x48);//
-		lcd_command_write(0x3A); // interface pixel format setting
-		lcd_data_write(0x55);//16-bits
-		lcd_command_write(0x11); // Exit sleep mode
-		lcd_command_write(0x29); // Display on 
+        lcd_command_write(0xC0);//power control1 command/w/
+        lcd_data_write(0x0A); // P-Gamma level//4.1875v
+        lcd_data_write(0x0A); // N-Gamma level
+        lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
+        lcd_data_write(0x41);
+        lcd_data_write(0x07); // VCI1 = 2.5V
+        lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
+        lcd_data_write(0x33);
+        lcd_command_write(0xC5);//VCOM control
+        lcd_data_write(0x00);  //NV memory is not programmed
+        lcd_data_write(0x42); // VCM Setting
+        lcd_data_write(0x80); // VCM Register Enable
+        lcd_command_write(0xB0);      //interface mode control //Polarity Setting
+        lcd_data_write(0x02);
+        lcd_command_write(0xB1);//frame rate control for normal mode
+        lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
+        lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
+        lcd_command_write(0xB4);//dispaly inversion control
+        lcd_data_write(0x00); // disable Z-inversion , column inversion
+        lcd_command_write(0xB6); //display function control// RM.DM Setting
+        lcd_data_write(0x70);////0xF0
+        lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
+        lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
+        lcd_command_write(0xB7); // Entry Mode
+        lcd_data_write(0x07); // disable low voltage detection, normal display,
+        lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
+        lcd_data_write(0x36);
+        lcd_data_write(0xA5);
+        lcd_data_write(0xD3);
+        lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
+        lcd_data_write(0x80);
+        lcd_command_write(0xE5); // Page 1
+        lcd_data_write(0x01);
+        lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
+        lcd_data_write(0x00);
+        lcd_command_write(0xE5); // Page 0
+        lcd_data_write(0x00);
+        lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
+        lcd_data_write(0x36);
+        lcd_data_write(0xA5);
+        lcd_data_write(0x53);
+        lcd_command_write(0xE0); // Gamma setting
+        //y fine adjustment register for positive polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x35);
+        lcd_data_write(0x33);
+        //y gradient adjustment register for positive polarity
+        lcd_data_write(0x00);
+        //y amplitude adjustment register for positive polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x00);
+        //y fine adjustment register for negative polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x35);
+        lcd_data_write(0x33);
+        //y gradient adjustment register for negative polarity
+        lcd_data_write(0x00);
+        //y amplitude adjustment register for negative polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x00);
+        lcd_command_write(0x36); // memory data access control //
+        lcd_data_write(0x48);//
+        lcd_command_write(0x3A); // interface pixel format setting
+        lcd_data_write(0x55);//16-bits
+        lcd_command_write(0x11); // Exit sleep mode
+        lcd_command_write(0x29); // Display on
 
-		delay(10);
+        delay(10);
 }
 /*!
     \brief      insert a delay time

bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h

@@ -13,10 +13,10 @@
 #define GD32F450Z_LCD_EVAL_H
 
 #include "gd32f450z_eval.h"
-   
+
 #define LCD_CS_PIN                   GPIO_PIN_11
 #define LCD_CS_GPIO_PORT             GPIOD
-#define LCD_CS_GPIO_CLK              RCU_GPIOD 
+#define LCD_CS_GPIO_CLK              RCU_GPIOD
 
 #define LCD_RS_PIN                   GPIO_PIN_3
 #define LCD_RS_GPIO_PORT             GPIOE
@@ -28,7 +28,7 @@
 
 #define LCD_SPI_MOSI_PIN             GPIO_PIN_14
 #define LCD_SPI_MOSI_GPIO_PORT       GPIOG
-#define LCD_SPI_MOSI_GPIO_CLK        RCU_GPIOG 
+#define LCD_SPI_MOSI_GPIO_CLK        RCU_GPIOG
 
 #define LCD_SPI                      SPI5
 #define LCD_SPI_CLK                  RCU_SPI5
@@ -52,4 +52,4 @@ void lcd_data_write(uint8_t value);
 /* configure the LCD based on the power on sequence */
 void lcd_power_on(void);
 void lcd_power_on3(void);
-#endif /* GD32F450Z_LCD_EVAL_H */ 
+#endif /* GD32F450Z_LCD_EVAL_H */

bsp/gd32450z-eval/drivers/synopsys_emac.h

@@ -22,7 +22,7 @@
 #define __SYNOPSYS_EMAC_H__
 
 #include <rtthread.h>
-     
+
 
 /******************************************************************************/
 /*                Ethernet MAC Registers bits definitions                     */
@@ -48,8 +48,8 @@
 #define EMAC_MACCR_RD           ((rt_uint32_t)0x00000200)  /* Retry disable */
 #define EMAC_MACCR_APCS         ((rt_uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
 #define EMAC_MACCR_BL           ((rt_uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-															a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define EMAC_MACCR_BL_10     	((rt_uint32_t)0x00000000)  /* k = min (n, 10) */
+                                                            a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define EMAC_MACCR_BL_10        ((rt_uint32_t)0x00000000)  /* k = min (n, 10) */
 #define EMAC_MACCR_BL_8         ((rt_uint32_t)0x00000020)  /* k = min (n, 8) */
 #define EMAC_MACCR_BL_4         ((rt_uint32_t)0x00000040)  /* k = min (n, 4) */
 #define EMAC_MACCR_BL_1         ((rt_uint32_t)0x00000060)  /* k = min (n, 1) */
@@ -60,45 +60,45 @@
 /* Bit definition for Ethernet MAC Frame Filter Register */
 #define EMAC_MACFFR_RA          ((rt_uint32_t)0x80000000)  /* Receive all */
 #define EMAC_MACFFR_HPF         ((rt_uint32_t)0x00000400)  /* Hash or perfect filter */
-#define EMAC_MACFFR_SAF      	((rt_uint32_t)0x00000200)  /* Source address filter enable */
+#define EMAC_MACFFR_SAF         ((rt_uint32_t)0x00000200)  /* Source address filter enable */
 #define EMAC_MACFFR_SAIF        ((rt_uint32_t)0x00000100)  /* SA inverse filtering */
 #define EMAC_MACFFR_PCF         ((rt_uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
 #define EMAC_MACFFR_PCF_BlockAll                ((rt_uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
 #define EMAC_MACFFR_PCF_ForwardAll              ((rt_uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
 #define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
 #define EMAC_MACFFR_BFD         ((rt_uint32_t)0x00000020)  /* Broadcast frame disable */
-#define EMAC_MACFFR_PAM       	((rt_uint32_t)0x00000010)  /* Pass all mutlicast */
+#define EMAC_MACFFR_PAM         ((rt_uint32_t)0x00000010)  /* Pass all mutlicast */
 #define EMAC_MACFFR_DAIF        ((rt_uint32_t)0x00000008)  /* DA Inverse filtering */
-#define EMAC_MACFFR_HM     	    ((rt_uint32_t)0x00000004)  /* Hash multicast */
-#define EMAC_MACFFR_HU     	    ((rt_uint32_t)0x00000002)  /* Hash unicast */
-#define EMAC_MACFFR_PM     	    ((rt_uint32_t)0x00000001)  /* Promiscuous mode */
+#define EMAC_MACFFR_HM          ((rt_uint32_t)0x00000004)  /* Hash multicast */
+#define EMAC_MACFFR_HU          ((rt_uint32_t)0x00000002)  /* Hash unicast */
+#define EMAC_MACFFR_PM          ((rt_uint32_t)0x00000001)  /* Promiscuous mode */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
-#define EMAC_MACHTHR_HTH   	    ((rt_uint32_t)0xFFFFFFFF)  /* Hash table high */
+#define EMAC_MACHTHR_HTH        ((rt_uint32_t)0xFFFFFFFF)  /* Hash table high */
 
 /* Bit definition for Ethernet MAC Hash Table Low Register */
-#define EMAC_MACHTLR_HTL  	    ((rt_uint32_t)0xFFFFFFFF)  /* Hash table low */
+#define EMAC_MACHTLR_HTL        ((rt_uint32_t)0xFFFFFFFF)  /* Hash table low */
 
 /* Bit definition for Ethernet MAC MII Address Register */
-#define EMAC_MACMIIAR_PA  	    ((rt_uint32_t)0x0000F800)  /* Physical layer address */
-#define EMAC_MACMIIAR_MR 	   	((rt_uint32_t)0x000007C0)  /* MII register in the selected PHY */
-#define EMAC_MACMIIAR_CR 	    ((rt_uint32_t)0x0000001C)  /* CR clock range: 6 cases */
+#define EMAC_MACMIIAR_PA        ((rt_uint32_t)0x0000F800)  /* Physical layer address */
+#define EMAC_MACMIIAR_MR        ((rt_uint32_t)0x000007C0)  /* MII register in the selected PHY */
+#define EMAC_MACMIIAR_CR        ((rt_uint32_t)0x0000001C)  /* CR clock range: 6 cases */
 #define EMAC_MACMIIAR_CR_Div42  ((rt_uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
 #define EMAC_MACMIIAR_CR_Div62  ((rt_uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
 #define EMAC_MACMIIAR_CR_Div16  ((rt_uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
 #define EMAC_MACMIIAR_CR_Div26  ((rt_uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
 #define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010)  /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
 #define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014)  /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
-#define EMAC_MACMIIAR_MW   	  	((rt_uint32_t)0x00000002)  /* MII write */
-#define EMAC_MACMIIAR_MB   		((rt_uint32_t)0x00000001)  /* MII busy */
+#define EMAC_MACMIIAR_MW        ((rt_uint32_t)0x00000002)  /* MII write */
+#define EMAC_MACMIIAR_MB        ((rt_uint32_t)0x00000001)  /* MII busy */
 
 /* Bit definition for Ethernet MAC MII Data Register */
-#define EMAC_MACMIIDR_MD  	 	((rt_uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+#define EMAC_MACMIIDR_MD        ((rt_uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
 
 /* Bit definition for Ethernet MAC Flow Control Register */
-#define EMAC_MACFCR_PT    		((rt_uint32_t)0xFFFF0000)  /* Pause time */
-#define EMAC_MACFCR_ZQPD   		((rt_uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define EMAC_MACFCR_PLT    		((rt_uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+#define EMAC_MACFCR_PT          ((rt_uint32_t)0xFFFF0000)  /* Pause time */
+#define EMAC_MACFCR_ZQPD        ((rt_uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define EMAC_MACFCR_PLT         ((rt_uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
 #define EMAC_MACFCR_PLT_Minus4   ((rt_uint32_t)0x00000000)  /* Pause time minus 4 slot times */
 #define EMAC_MACFCR_PLT_Minus28  ((rt_uint32_t)0x00000010)  /* Pause time minus 28 slot times */
 #define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020)  /* Pause time minus 144 slot times */
@@ -441,7 +441,7 @@
 #define EMAC_DMACHRBAR_HRBAP  ((rt_uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
 
 //typedef enum {
-//	RESET = 0, SET = !RESET
+//  RESET = 0, SET = !RESET
 //} FlagStatus, ITStatus;
 //typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 
@@ -450,165 +450,165 @@
  */
 typedef struct
 {
-	/**
-	 * MAC
-	 */
-	rt_uint32_t             EMAC_AutoNegotiation;           /* Selects or not the AutoNegotiation mode for the external PHY
-															The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
-															and the mode (half/full-duplex).
-															This parameter can be a value of @ref EMAC_AutoNegotiation */
+    /**
+     * MAC
+     */
+    rt_uint32_t             EMAC_AutoNegotiation;           /* Selects or not the AutoNegotiation mode for the external PHY
+                                                            The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                            and the mode (half/full-duplex).
+                                                            This parameter can be a value of @ref EMAC_AutoNegotiation */
 
-	rt_uint32_t             EMAC_Watchdog;                  /* Selects or not the Watchdog timer
-															When enabled, the MAC allows no more then 2048 bytes to be received.
-															When disabled, the MAC can receive up to 16384 bytes.
-															This parameter can be a value of @ref EMAC_watchdog */
+    rt_uint32_t             EMAC_Watchdog;                  /* Selects or not the Watchdog timer
+                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                            When disabled, the MAC can receive up to 16384 bytes.
+                                                            This parameter can be a value of @ref EMAC_watchdog */
 
-	rt_uint32_t             EMAC_Jabber;                    /* Selects or not Jabber timer
-															When enabled, the MAC allows no more then 2048 bytes to be sent.
-															When disabled, the MAC can send up to 16384 bytes.
-															This parameter can be a value of @ref EMAC_Jabber */
+    rt_uint32_t             EMAC_Jabber;                    /* Selects or not Jabber timer
+                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                            When disabled, the MAC can send up to 16384 bytes.
+                                                            This parameter can be a value of @ref EMAC_Jabber */
 
-	rt_uint32_t             EMAC_InterFrameGap;             /* Selects the minimum IFG between frames during transmission
-															This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
+    rt_uint32_t             EMAC_InterFrameGap;             /* Selects the minimum IFG between frames during transmission
+                                                            This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
 
-	rt_uint32_t             EMAC_CarrierSense;              /* Selects or not the Carrier Sense
-															This parameter can be a value of @ref EMAC_Carrier_Sense */
+    rt_uint32_t             EMAC_CarrierSense;              /* Selects or not the Carrier Sense
+                                                            This parameter can be a value of @ref EMAC_Carrier_Sense */
 
-	rt_uint32_t             EMAC_Speed;                     /* Sets the Ethernet speed: 10/100 Mbps
-															This parameter can be a value of @ref EMAC_Speed */
+    rt_uint32_t             EMAC_Speed;                     /* Sets the Ethernet speed: 10/100 Mbps
+                                                            This parameter can be a value of @ref EMAC_Speed */
 
-	rt_uint32_t             EMAC_ReceiveOwn;                /* Selects or not the ReceiveOwn
-															ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
-															in Half-Duplex mode
-															This parameter can be a value of @ref EMAC_Receive_Own */
+    rt_uint32_t             EMAC_ReceiveOwn;                /* Selects or not the ReceiveOwn
+                                                            ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                            in Half-Duplex mode
+                                                            This parameter can be a value of @ref EMAC_Receive_Own */
 
-	rt_uint32_t             EMAC_LoopbackMode;              /* Selects or not the internal MAC MII Loopback mode
-															This parameter can be a value of @ref EMAC_Loop_Back_Mode */
+    rt_uint32_t             EMAC_LoopbackMode;              /* Selects or not the internal MAC MII Loopback mode
+                                                            This parameter can be a value of @ref EMAC_Loop_Back_Mode */
 
-	rt_uint32_t             EMAC_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
-															This parameter can be a value of @ref EMAC_Duplex_Mode */
+    rt_uint32_t             EMAC_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                            This parameter can be a value of @ref EMAC_Duplex_Mode */
 
-	rt_uint32_t             EMAC_ChecksumOffload;           /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
-															This parameter can be a value of @ref EMAC_Checksum_Offload */
+    rt_uint32_t             EMAC_ChecksumOffload;           /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                            This parameter can be a value of @ref EMAC_Checksum_Offload */
 
-	rt_uint32_t             EMAC_RetryTransmission;         /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
-															when a colision occurs (Half-Duplex mode)
-															This parameter can be a value of @ref EMAC_Retry_Transmission */
+    rt_uint32_t             EMAC_RetryTransmission;         /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                            when a colision occurs (Half-Duplex mode)
+                                                            This parameter can be a value of @ref EMAC_Retry_Transmission */
 
-	rt_uint32_t             EMAC_AutomaticPadCRCStrip;      /* Selects or not the Automatic MAC Pad/CRC Stripping
-															This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
+    rt_uint32_t             EMAC_AutomaticPadCRCStrip;      /* Selects or not the Automatic MAC Pad/CRC Stripping
+                                                            This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
 
-	rt_uint32_t             EMAC_BackOffLimit;              /* Selects the BackOff limit value
-															This parameter can be a value of @ref EMAC_Back_Off_Limit */
+    rt_uint32_t             EMAC_BackOffLimit;              /* Selects the BackOff limit value
+                                                            This parameter can be a value of @ref EMAC_Back_Off_Limit */
 
-	rt_uint32_t             EMAC_DeferralCheck;             /* Selects or not the deferral check function (Half-Duplex mode)
-															This parameter can be a value of @ref EMAC_Deferral_Check */
+    rt_uint32_t             EMAC_DeferralCheck;             /* Selects or not the deferral check function (Half-Duplex mode)
+                                                            This parameter can be a value of @ref EMAC_Deferral_Check */
 
-	rt_uint32_t             EMAC_ReceiveAll;                /* Selects or not all frames reception by the MAC (No fitering)
-															This parameter can be a value of @ref EMAC_Receive_All */
+    rt_uint32_t             EMAC_ReceiveAll;                /* Selects or not all frames reception by the MAC (No fitering)
+                                                            This parameter can be a value of @ref EMAC_Receive_All */
 
-	rt_uint32_t             EMAC_SourceAddrFilter;          /* Selects the Source Address Filter mode
-															This parameter can be a value of @ref EMAC_Source_Addr_Filter */
+    rt_uint32_t             EMAC_SourceAddrFilter;          /* Selects the Source Address Filter mode
+                                                            This parameter can be a value of @ref EMAC_Source_Addr_Filter */
 
-	rt_uint32_t             EMAC_PassControlFrames;         /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
-															This parameter can be a value of @ref EMAC_Pass_Control_Frames */
+    rt_uint32_t             EMAC_PassControlFrames;         /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+                                                            This parameter can be a value of @ref EMAC_Pass_Control_Frames */
 
-	rt_uint32_t             EMAC_BroadcastFramesReception;  /* Selects or not the reception of Broadcast Frames
-															This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
+    rt_uint32_t             EMAC_BroadcastFramesReception;  /* Selects or not the reception of Broadcast Frames
+                                                            This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
 
-	rt_uint32_t             EMAC_DestinationAddrFilter;     /* Sets the destination filter mode for both unicast and multicast frames
-															This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
+    rt_uint32_t             EMAC_DestinationAddrFilter;     /* Sets the destination filter mode for both unicast and multicast frames
+                                                            This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
 
-	rt_uint32_t             EMAC_PromiscuousMode;           /* Selects or not the Promiscuous Mode
-															This parameter can be a value of @ref EMAC_Promiscuous_Mode */
+    rt_uint32_t             EMAC_PromiscuousMode;           /* Selects or not the Promiscuous Mode
+                                                            This parameter can be a value of @ref EMAC_Promiscuous_Mode */
 
-	rt_uint32_t             EMAC_MulticastFramesFilter;     /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
-															This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
+    rt_uint32_t             EMAC_MulticastFramesFilter;     /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                            This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
 
-	rt_uint32_t             EMAC_UnicastFramesFilter;       /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
-															This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
+    rt_uint32_t             EMAC_UnicastFramesFilter;       /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                            This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
 
-	rt_uint32_t             EMAC_HashTableHigh;             /* This field holds the higher 32 bits of Hash table.  */
+    rt_uint32_t             EMAC_HashTableHigh;             /* This field holds the higher 32 bits of Hash table.  */
 
-	rt_uint32_t             EMAC_HashTableLow;              /* This field holds the lower 32 bits of Hash table.  */
+    rt_uint32_t             EMAC_HashTableLow;              /* This field holds the lower 32 bits of Hash table.  */
 
-	rt_uint32_t             EMAC_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the
-															transmit control frame */
+    rt_uint32_t             EMAC_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the
+                                                            transmit control frame */
 
-	rt_uint32_t             EMAC_ZeroQuantaPause;           /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
-															This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
+    rt_uint32_t             EMAC_ZeroQuantaPause;           /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
+                                                            This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
 
-	rt_uint32_t             EMAC_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for
-															automatic retransmission of PAUSE Frame
-															This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
+    rt_uint32_t             EMAC_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for
+                                                            automatic retransmission of PAUSE Frame
+                                                            This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
 
-	rt_uint32_t             EMAC_UnicastPauseFrameDetect;   /* Selects or not the MAC detection of the Pause frames (with MAC Address0
-															unicast address and unique multicast address)
-															This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
+    rt_uint32_t             EMAC_UnicastPauseFrameDetect;   /* Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                            unicast address and unique multicast address)
+                                                            This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
 
-	rt_uint32_t             EMAC_ReceiveFlowControl;        /* Enables or disables the MAC to decode the received Pause frame and
-															disable its transmitter for a specified time (Pause Time)
-															This parameter can be a value of @ref EMAC_Receive_Flow_Control */
+    rt_uint32_t             EMAC_ReceiveFlowControl;        /* Enables or disables the MAC to decode the received Pause frame and
+                                                            disable its transmitter for a specified time (Pause Time)
+                                                            This parameter can be a value of @ref EMAC_Receive_Flow_Control */
 
-	rt_uint32_t             EMAC_TransmitFlowControl;       /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
-															or the MAC back-pressure operation (Half-Duplex mode)
-															This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
+    rt_uint32_t             EMAC_TransmitFlowControl;       /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                            or the MAC back-pressure operation (Half-Duplex mode)
+                                                            This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
 
-	rt_uint32_t             EMAC_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
-															comparison and filtering
-															This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
+    rt_uint32_t             EMAC_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                            comparison and filtering
+                                                            This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
 
-	rt_uint32_t             EMAC_VLANTagIdentifier;         /* Holds the VLAN tag identifier for receive frames */
+    rt_uint32_t             EMAC_VLANTagIdentifier;         /* Holds the VLAN tag identifier for receive frames */
 
-	/**
-	 * DMA
-	 */
+    /**
+     * DMA
+     */
 
-	rt_uint32_t             EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
-															  This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
+    rt_uint32_t             EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
+                                                              This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
 
-	rt_uint32_t             EMAC_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
-															  This parameter can be a value of @ref EMAC_Receive_Store_Forward */
+    rt_uint32_t             EMAC_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
+                                                              This parameter can be a value of @ref EMAC_Receive_Store_Forward */
 
-	rt_uint32_t             EMAC_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
-															  This parameter can be a value of @ref EMAC_Flush_Received_Frame */
+    rt_uint32_t             EMAC_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
+                                                              This parameter can be a value of @ref EMAC_Flush_Received_Frame */
 
-	rt_uint32_t             EMAC_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
-															  This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
+    rt_uint32_t             EMAC_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
+                                                              This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
 
-	rt_uint32_t             EMAC_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
-															  This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
+    rt_uint32_t             EMAC_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
+                                                              This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
 
-	rt_uint32_t             EMAC_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
-															  This parameter can be a value of @ref EMAC_Forward_Error_Frames */
+    rt_uint32_t             EMAC_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
+                                                              This parameter can be a value of @ref EMAC_Forward_Error_Frames */
 
-	rt_uint32_t             EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
-															  and length less than 64 bytes) including pad-bytes and CRC)
-															  This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
+    rt_uint32_t             EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                              and length less than 64 bytes) including pad-bytes and CRC)
+                                                              This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
 
-	rt_uint32_t             EMAC_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
-															  This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
+    rt_uint32_t             EMAC_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
+                                                              This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
 
-	rt_uint32_t             EMAC_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
-															  frame of Transmit data even before obtaining the status for the first frame.
-															  This parameter can be a value of @ref EMAC_Second_Frame_Operate */
+    rt_uint32_t             EMAC_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                              frame of Transmit data even before obtaining the status for the first frame.
+                                                              This parameter can be a value of @ref EMAC_Second_Frame_Operate */
 
-	rt_uint32_t             EMAC_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
-															  This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
+    rt_uint32_t             EMAC_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
+                                                              This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
 
-	rt_uint32_t             EMAC_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
-															  This parameter can be a value of @ref EMAC_Fixed_Burst */
+    rt_uint32_t             EMAC_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
+                                                              This parameter can be a value of @ref EMAC_Fixed_Burst */
 
-	rt_uint32_t             EMAC_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
-															  This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
+    rt_uint32_t             EMAC_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+                                                              This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
 
-	rt_uint32_t             EMAC_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
-															  This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
+    rt_uint32_t             EMAC_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+                                                              This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
 
-	rt_uint32_t             EMAC_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained int (Ring mode) */
+    rt_uint32_t             EMAC_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained int (Ring mode) */
 
-	rt_uint32_t             EMAC_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
-															  This parameter can be a value of @ref EMAC_DMA_Arbitration */
+    rt_uint32_t             EMAC_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
+                                                              This parameter can be a value of @ref EMAC_DMA_Arbitration */
 } EMAC_InitTypeDef;
 
 /**--------------------------------------------------------------------------**/
@@ -622,10 +622,10 @@ typedef struct
  */
 typedef struct
 {
-	rt_uint32_t   Status;                /* Status */
-	rt_uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
-	rt_uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
-	rt_uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
+    rt_uint32_t   Status;                /* Status */
+    rt_uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
+    rt_uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
+    rt_uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
 } EMAC_DMADESCTypeDef;
 
 /**--------------------------------------------------------------------------**/
@@ -634,14 +634,14 @@ typedef struct
  */
 /**--------------------------------------------------------------------------**/
 
-#define EMAC_MAX_PACKET_SIZE    	1520    /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
-#define EMAC_HEADER               	14    	/* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define EMAC_CRC                   	4    	/* Ethernet CRC */
-#define EMAC_EXTRA                 	2    	/* Extra bytes in some cases */
-#define VLAN_TAG                  	4    	/* optional 802.1q VLAN Tag */
-#define MIN_EMAC_PAYLOAD          	46    	/* Minimum Ethernet payload size */
-#define MAX_EMAC_PAYLOAD        	1500    /* Maximum Ethernet payload size */
-#define JUMBO_FRAME_PAYLOAD    		9000    /* Jumbo frame payload size */
+#define EMAC_MAX_PACKET_SIZE        1520    /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
+#define EMAC_HEADER                 14      /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define EMAC_CRC                    4       /* Ethernet CRC */
+#define EMAC_EXTRA                  2       /* Extra bytes in some cases */
+#define VLAN_TAG                    4       /* optional 802.1q VLAN Tag */
+#define MIN_EMAC_PAYLOAD            46      /* Minimum Ethernet payload size */
+#define MAX_EMAC_PAYLOAD            1500    /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD         9000    /* Jumbo frame payload size */
 
 /**--------------------------------------------------------------------------**/
 /**
@@ -1098,7 +1098,7 @@ struct rt_synopsys_eth
     volatile rt_uint32_t FCR;
     volatile rt_uint32_t VTR;
                rt_uint8_t RESERVED0[8];
-    
+
     volatile rt_uint32_t RWFFR;
     volatile rt_uint32_t PMTR;
     volatile rt_uint32_t LPICSR;

bsp/gd32e230k-start/applications/main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32e230k-start/drivers/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -75,7 +75,7 @@ void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-#ifdef RT_USING_HEAP   
+#ifdef RT_USING_HEAP
     rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
 }

bsp/gd32e230k-start/drivers/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 #include <gd32e230.h>
 
 // <o> Internal SRAM memory size[Kbytes] <8-64>
-//	<i>Default: 64
+//  <i>Default: 64
 #ifdef __ICCARM__
 // Use *.icf ram symbal, to avoid hardcode.
 extern char __ICFEDIT_region_RAM_end__;

bsp/gd32e230k-start/drivers/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,8 +29,8 @@ struct pin_index
     rcu_periph_enum clk;
     rt_uint32_t gpio_periph;
     rt_uint32_t pin;
-	  rt_uint32_t port_src;
-	  rt_uint32_t pin_src;
+      rt_uint32_t port_src;
+      rt_uint32_t pin_src;
 };
 
 static const struct pin_index pins[] =
@@ -38,8 +38,8 @@ static const struct pin_index pins[] =
     __GD32_PIN_DEFAULT,
     __GD32_PIN(2, F, 0),
     __GD32_PIN(3, F, 1),
-	  __GD32_PIN_DEFAULT,
-		__GD32_PIN_DEFAULT,
+      __GD32_PIN_DEFAULT,
+        __GD32_PIN_DEFAULT,
     __GD32_PIN(6, A, 0),
     __GD32_PIN(7, A, 1),
     __GD32_PIN(8, A, 2),
@@ -51,7 +51,7 @@ static const struct pin_index pins[] =
     __GD32_PIN(14, B, 0),
     __GD32_PIN(15, B, 1),
     __GD32_PIN(16, B, 2),
-		__GD32_PIN_DEFAULT,
+        __GD32_PIN_DEFAULT,
     __GD32_PIN(18, A, 8),
     __GD32_PIN(19, A, 9),
     __GD32_PIN(20, A, 10),
@@ -136,8 +136,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
-	  rt_uint32_t otype;
-	  rt_uint32_t pull_up_down;
+      rt_uint32_t otype;
+      rt_uint32_t pull_up_down;
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -147,9 +147,9 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     /* GPIO Periph clock enable */
     rcu_periph_clock_enable(index->clk);
     pin_mode = GPIO_MODE_OUTPUT;
-		otype = GPIO_OTYPE_PP;
-		pull_up_down = GPIO_PUPD_NONE;
-    
+        otype = GPIO_OTYPE_PP;
+        pull_up_down = GPIO_PUPD_NONE;
+
    switch(mode)
    {
    case PIN_MODE_OUTPUT:
@@ -157,7 +157,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         break;
    case PIN_MODE_OUTPUT_OD:
         /* output setting: od. */
-		    otype = GPIO_OTYPE_OD;
+            otype = GPIO_OTYPE_OD;
         break;
    case PIN_MODE_INPUT:
         /* input setting: not pull. */
@@ -166,20 +166,20 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
    case PIN_MODE_INPUT_PULLUP:
         /* input setting: pull up. */
         pin_mode = GPIO_MODE_INPUT;
-	      pull_up_down = GPIO_PUPD_PULLUP;
+          pull_up_down = GPIO_PUPD_PULLUP;
         break;
    case PIN_MODE_INPUT_PULLDOWN:
         /* input setting: pull down. */
-	      pin_mode = GPIO_MODE_INPUT;
-	      pull_up_down = GPIO_PUPD_PULLDOWN;
+          pin_mode = GPIO_MODE_INPUT;
+          pull_up_down = GPIO_PUPD_PULLDOWN;
         break;
    default:
         break;
    }
 
-	  gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
+      gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
     gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin);
-	 
+
 }
 
 void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
@@ -333,7 +333,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
             return RT_EINVAL;
         }
         irqmap = &pin_irq_map[hdr_index];
-   
+
         switch (pin_irq_hdr_tab[hdr_index].mode)
         {
             case PIN_IRQ_MODE_RISING:
@@ -354,14 +354,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
 
         /* enable and set interrupt priority */
         nvic_irq_enable(irqmap->irqno, 5U);
-        
+
         /* connect EXTI line to  GPIO pin */
-				syscfg_exti_line_config(index->port_src, index->pin_src);
+                syscfg_exti_line_config(index->port_src, index->pin_src);
 
         /* configure EXTI line */
         exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
         exti_interrupt_flag_clear((exti_line_enum)(index->pin));
-        
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
@@ -396,7 +396,7 @@ int rt_hw_pin_init(void)
     int result;
 
     result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_pin_init);
@@ -415,7 +415,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
     {
         pin_irq_hdr(exti_line);
         exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
-    } 
+    }
 }
 void EXTI0_IRQHandler(void)
 {

bsp/gd32e230k-start/drivers/drv_gpio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32e230k-start/drivers/drv_i2c.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -155,7 +155,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u
             *p_buffer = i2c_data_receive(i2c_periph);
 
             /* point to the next location where the byte read will be saved */
-            p_buffer++; 
+            p_buffer++;
 
             /* decrement the read bytes counter */
             data_byte--;
@@ -264,7 +264,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg
             }
         }
     }
-    
+
     ret = i;
 
 out:
@@ -274,7 +274,7 @@ out:
 }
 
 static const struct rt_i2c_bus_device_ops i2c_ops =
-{ 
+{
     gd32_i2c_xfer,
     RT_NULL,
     RT_NULL
@@ -311,7 +311,7 @@ int rt_hw_i2c_init(void)
 
         i2c_device.priv = (void *)&_i2c_bit_ops;
         rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
-    } 
+    }
 
 #else   /* register hardware I2C */
 

bsp/gd32e230k-start/drivers/drv_i2c.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32e230k-start/drivers/drv_spi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -115,7 +115,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
             spi_init_struct.prescale = SPI_PSC_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -131,7 +131,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
         break;
     }
-    
+
     /* MSB or LSB */
     if(configuration->mode & RT_SPI_MSB)
     {
@@ -141,7 +141,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
     {
         spi_init_struct.endian = SPI_ENDIAN_LSB;
     }
-    
+
     spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
     spi_init_struct.device_mode = SPI_MASTER;
     spi_init_struct.nss = SPI_NSS_SOFT;
@@ -177,7 +177,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -188,7 +188,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by gd32f3 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));

bsp/gd32e230k-start/drivers/drv_spi.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32e230k-start/drivers/drv_usart.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,7 +41,7 @@ struct gd32_uart
     uint16_t tx_pin;
     uint32_t rx_port;
     uint32_t rx_af;
-    uint16_t rx_pin; 
+    uint16_t rx_pin;
 
     struct rt_serial_device * serial;
     char *device_name;
@@ -93,7 +93,7 @@ static const struct gd32_uart uarts[] = {
         "uart0",
     },
     #endif
-    
+
     #ifdef RT_USING_USART1
     {
         USART1,                                 // uart peripheral index
@@ -122,18 +122,18 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
     /* enable USART clock */
     rcu_periph_clock_enable(uart->tx_gpio_clk);
     rcu_periph_clock_enable(uart->rx_gpio_clk);
-    rcu_periph_clock_enable(uart->per_clk);    
+    rcu_periph_clock_enable(uart->per_clk);
 
     /* connect port to USARTx_Tx */
     gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin);
     gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->tx_pin);
     gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->tx_pin);
-	
+
     /* connect port to USARTx_Rx */
     gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin);
     gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->rx_pin);
     gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->rx_pin);
-	
+
     NVIC_SetPriority(uart->irqn, 0);
     NVIC_EnableIRQ(uart->irqn);
 }
@@ -146,9 +146,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (struct gd32_uart *)serial->parent.user_data;
-    
+
     gd32_uart_gpio_init(uart);
-    
+
     usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
 
     switch (cfg->data_bits)
@@ -228,7 +228,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
 
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-    
+
     return 1;
 }
 

bsp/gd32e230k-start/drivers/drv_usart.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32e230k-start/drivers/gd32e230_libopt.h

@@ -1,7 +1,7 @@
 /*!
     \file    gd32e230_libopt.h
     \brief   library optional for gd32e230
-    
+
     \version 2018-06-19, V1.0.0, firmware for GD32E230
 */
 
@@ -10,27 +10,27 @@
 
     All rights reserved.
 
-    Redistribution and use in source and binary forms, with or without modification, 
+    Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
 
-    1. Redistributions of source code must retain the above copyright notice, this 
+    1. Redistributions of source code must retain the above copyright notice, this
        list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
        and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
        specific prior written permission.
 
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 OF SUCH DAMAGE.
 */
 

bsp/gd32vf103v-eval/applications/main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32vf103v-eval/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32vf103v-eval/board/board.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/gd32vf103v-eval/board/gd32vf103_libopt.h

@@ -8,27 +8,27 @@
 /*
  Copyright (c) 2019, GigaDevice Semiconductor Inc.
 
- Redistribution and use in source and binary forms, with or without modification, 
+ Redistribution and use in source and binary forms, with or without modification,
  are permitted provided that the following conditions are met:
 
- 1. Redistributions of source code must retain the above copyright notice, this 
+ 1. Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice, 
- this list of conditions and the following disclaimer in the documentation 
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
  and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors 
- may be used to endorse or promote products derived from this software without 
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
  specific prior written permission.
 
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
- IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
- NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  OF SUCH DAMAGE.
  */
 

bsp/gd32vf103v-eval/drivers/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 
 #define EXTI_(x)  BIT(x)
 
-static const struct pin_index pins[] = 
+static const struct pin_index pins[] =
 {
 #if defined(GPIOA)
     __GD32VF_PIN(0 ,  A, 0 ),
@@ -126,7 +126,7 @@ static const struct pin_irq_map pin_irq_map[] =
     {GPIO_PIN_12, EXTI10_15_IRQn},
     {GPIO_PIN_13, EXTI10_15_IRQn},
     {GPIO_PIN_14, EXTI10_15_IRQn},
-    {GPIO_PIN_15, EXTI10_15_IRQn}, 
+    {GPIO_PIN_15, EXTI10_15_IRQn},
 };
 
 static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
@@ -406,11 +406,11 @@ static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         gpio_bit_reset(index->gpio_periph, index->pin);
 
         pin_irq_enable_mask &= ~irqmap->pinbit;
- 
+
         eclic_irq_disable(irqmap->irqno);
         exti_interrupt_flag_clear(EXTI_(index->pin));
-         
-        rt_hw_interrupt_enable(level);  
+
+        rt_hw_interrupt_enable(level);
     }
     else
     {

bsp/gd32vf103v-eval/drivers/drv_gpio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,4 +38,4 @@ int rt_hw_gpio_init(void);
 
 #endif /* __DRV_GPIO__H__ */
 
-/******************* end of file *******************/
+/******************* end of file *******************/

bsp/gd32vf103v-eval/drivers/drv_usart.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
     && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
     #error "Please define at least one BSP_USING_UARTx"
-    /* this driver can be disabled at menuconfig ¡ú RT-Thread Components ¡ú Device Drivers */
+    /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
 #endif
 
 struct gd32_usart {

bsp/nuvoton/README.md

@@ -1,4 +1,4 @@
-# Nuvoton BSP descriptions
+ï»? Nuvoton BSP descriptions
 Current supported BSP shown in below table:
 
 | **BSP folder** | **Board name** |
@@ -6,4 +6,5 @@ Current supported BSP shown in below table:
 | [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 |
 | [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
 | [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
-| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
+| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
+| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |

bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/NuMicro.h

@@ -9,6 +9,7 @@
 #ifndef __NUMICRO_H__
 #define __NUMICRO_H__
 
+#include "nutool_clkcfg.h"
 #include "M2354.h"
 
 #endif  /* __NUMICRO_H__ */

bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/system_M2354.h

@@ -49,11 +49,21 @@ extern "C" {
 /*----------------------------------------------------------------------------
   Define SYSCLK
  *----------------------------------------------------------------------------*/
+#ifndef __HXT
 #define __HXT       (12000000UL)    /*!< External Crystal Clock Frequency     */
+#endif
+
 #define __LIRC      (32000UL)       /*!< Internal 32K RC Oscillator Frequency */
 #define __HIRC      (12000000UL)    /*!< Internal 12M RC Oscillator Frequency */
+
+#ifndef __LXT
 #define __LXT       (32768UL)       /*!< External Crystal Clock Frequency 32.768KHz */
+#endif
+
+#ifndef __HSI
 #define __HSI       (48000000UL)    /*!< PLL Output Clock Frequency */
+#endif
+
 #define __HIRC48    (48000000UL)    /*!< Internal 48M RC Oscillator Frequency */
 #define __LIRC32    (32000UL)       /*!< Internal 32K RC Oscillator Frequency */
 #define __MIRC      (4000000UL)     /*!< Internal 4M RC Oscillator Frequency */
@@ -93,7 +103,7 @@ extern uint32_t __PC(void);         /*!< Return the current program counter valu
  */
 #define ASSERT_PARAM(expr)  { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
 
-void AssertError(uint8_t* file, uint32_t line);
+void AssertError(uint8_t *file, uint32_t line);
 #else
 #define ASSERT_PARAM(expr)
 #endif

bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.ewp

@@ -348,6 +348,7 @@
                     <state>$PROJ_DIR$\..\..\Device\Nuvoton\M2354\Include</state>
                     <state>$PROJ_DIR$\..\..\CMSIS\Include</state>
                     <state>$PROJ_DIR$\..\inc</state>
+                    <state>$PROJ_DIR$</state>
                 </option>
                 <option>
                     <name>CCStdIncCheck</name>
@@ -1385,6 +1386,7 @@
                     <state>$PROJ_DIR$\..\..\Device\Nuvoton\M2354\Include</state>
                     <state>$PROJ_DIR$\..\..\CMSIS\Include</state>
                     <state>$PROJ_DIR$\..\inc</state>
+                    <state>$PROJ_DIR$</state>
                 </option>
                 <option>
                     <name>CCStdIncCheck</name>

bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.uvprojx

@@ -338,7 +338,7 @@
               <MiscControls></MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath>..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M2354\Include</IncludePath>
+              <IncludePath>..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M2354\Include;.</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>

bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm_capture.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_BPWM_CAPTURE)
 #if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private typedef --------------------------------------------------------------*/
 typedef struct _bpwm_dev

bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private Define ---------------------------------------------------------------*/
 #define RX_MSG_ID_INDEX        16

bsp/nuvoton/libraries/m2354/rtt_port/drv_clk.c

@@ -18,7 +18,7 @@
 #include <rtdbg.h>
 #include <stdint.h>
 #include <string.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 
 /* Private define ---------------------------------------------------------------*/

bsp/nuvoton/numaker-m2354/board/board.c → bsp/nuvoton/libraries/m2354/rtt_port/drv_common.c

@@ -12,7 +12,7 @@
 
 #include <rtconfig.h>
 #include <rtthread.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <nu_bitutil.h>
 #include "drv_uart.h"
 #include "board.h"
@@ -24,7 +24,7 @@
 /**
  * This function will initial M487 board.
  */
-void rt_hw_board_init(void)
+RT_WEAK void rt_hw_board_init(void)
 {
     /* Init System/modules clock */
     nutool_modclkcfg_init();
@@ -67,6 +67,41 @@ void rt_hw_board_init(void)
 #endif
 }
 
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
 /**
  * This is the timer interrupt service routine.
  *

bsp/nuvoton/libraries/m2354/rtt_port/drv_eadc.c

@@ -11,7 +11,7 @@
 
 #include <rtconfig.h>
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #ifdef BSP_USING_EADC
 

bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.h

@@ -13,7 +13,7 @@
 #define __DRV_EBI_H___
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /**
   * @brief      Initialize EBI for specify Bank

bsp/nuvoton/libraries/m2354/rtt_port/drv_ecap.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_ECAP)
 #if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #define ECAP_CH0_POS    (0)
 #define ECAP_CH1_POS    (1)

bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm_capture.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_EPWM_CAPTURE)
 #if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #define EPWM_CH0CH1_POS    (0)
 #define EPWM_CH2CH3_POS    (2)

bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.h

@@ -14,7 +14,7 @@
 #define __DRV_FMC_H__
 
 #include <rtthread.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 int nu_fmc_read(long offset, uint8_t *buf, size_t size);
 int nu_fmc_write(long offset, const uint8_t *buf, size_t size);

bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <nu_bitutil.h>
 #include <drv_gpio.h>
 #include <stdlib.h>

bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c

@@ -14,7 +14,7 @@
 
 #ifdef BSP_USING_I2C
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG         "drv.i2c"

bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.c

@@ -220,7 +220,8 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
         }
 
         /* Set MCLK and enable MCLK */
-        I2S_EnableMCLK(psNuI2s->i2s_base, __HXT);
+        /* The target MCLK is related to audio codec setting. */
+        I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
 
         /* Set unmute */
         if (pNuACodecOps->nu_acodec_mixer_control)

bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.h

@@ -14,7 +14,7 @@
 #define __DRV_I2S_H__
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <drv_pdma.h>
 
 #if !defined(NU_I2S_DMA_FIFO_SIZE)

bsp/nuvoton/libraries/m2354/rtt_port/drv_otg.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_OTG)
 #include <rtdevice.h>
 #include <rtdbg.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* This delay must be at least 10 us */
 static void _usb_init_delay(void)

bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.h

@@ -15,7 +15,7 @@
 
 #include <rtconfig.h>
 #include <rtthread.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #ifndef NU_PDMA_SGTBL_POOL_SIZE
     #define NU_PDMA_SGTBL_POOL_SIZE (16)

bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c

@@ -14,7 +14,8 @@
 #if defined (BSP_USING_RTC)
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include <sys/time.h>
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 
@@ -184,8 +185,8 @@ static rt_err_t nu_rtc_is_date_valid(const time_t *const t)
 
     if (!initialised)
     {
-        t_upper = mktime((struct tm *)&tm_upper);
-        t_lower = mktime((struct tm *)&tm_lower);
+        t_upper = timegm((struct tm *)&tm_upper);
+        t_lower = timegm((struct tm *)&tm_lower);
         initialised = RT_TRUE;
     }
 
@@ -226,13 +227,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
         tm_out.tm_hour = hw_time.u32Hour;
         tm_out.tm_min = hw_time.u32Minute;
         tm_out.tm_sec = hw_time.u32Second;
-        *time = mktime(&tm_out);
+        *time = timegm(&tm_out);
         break;
 
     case RT_DEVICE_CTRL_RTC_SET_TIME:
 
         time = (time_t *) args;
-        tm_in = localtime(time);
+        tm_in = gmtime(time);
 
         if (nu_rtc_is_date_valid(time) != RT_EOK)
             return RT_ERROR;

bsp/nuvoton/libraries/m2354/rtt_port/drv_scuart.c

@@ -14,7 +14,7 @@
 
 #if defined(BSP_USING_SCUART)
 
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <rtdevice.h>
 #include <rthw.h>
 

bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c

@@ -15,7 +15,7 @@
 #if defined(BSP_USING_SDH)
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <drv_pdma.h>
 #include <string.h>
 

bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <drv_slcd.h>
 
 /* Private define ---------------------------------------------------------------*/

bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.h

@@ -14,7 +14,7 @@
 #define __DRV_SLCD_H__
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 struct nu_slcd_pixel
 {

bsp/nuvoton/libraries/m2354/rtt_port/drv_softi2c.c

@@ -17,7 +17,7 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG          "drv.softi2c"
@@ -65,7 +65,6 @@ struct nu_soft_i2c
 };
 
 /* Private functions ------------------------------------------------------------*/
-static void nu_soft_i2c_udelay(rt_uint32_t us);
 static void nu_soft_i2c_set_sda(void *data, rt_int32_t state);
 static void nu_soft_i2c_set_scl(void *data, rt_int32_t state);
 static rt_int32_t nu_soft_i2c_get_sda(void *data);
@@ -91,48 +90,13 @@ static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops =
     .set_scl  = nu_soft_i2c_set_scl,
     .get_sda  = nu_soft_i2c_get_sda,
     .get_scl  = nu_soft_i2c_get_scl,
-    .udelay   = nu_soft_i2c_udelay,
+    .udelay   = rt_hw_us_delay,
     .delay_us = 1,
     .timeout  = 100
 };
 
 /* Functions define ------------------------------------------------------------*/
 
-/**
- * The time delay function.
- *
- * @param microseconds.
- */
-static void nu_soft_i2c_udelay(rt_uint32_t us)
-{
-    rt_uint32_t ticks;
-    rt_uint32_t told, tnow, tcnt = 0;
-    rt_uint32_t reload = SysTick->LOAD;
-
-    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
-    told = SysTick->VAL;
-    while (1)
-    {
-        tnow = SysTick->VAL;
-        if (tnow != told)
-        {
-            if (tnow < told)
-            {
-                tcnt += told - tnow;
-            }
-            else
-            {
-                tcnt += reload - tnow + told;
-            }
-            told = tnow;
-            if (tcnt >= ticks)
-            {
-                break;
-            }
-        }
-    }
-}
-
 /**
  * This function initializes the soft i2c pin.
  *
@@ -163,9 +127,9 @@ static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg)
         while (i++ < 9)
         {
             rt_pin_write(cfg->scl, PIN_HIGH);
-            nu_soft_i2c_udelay(100);
+            rt_hw_us_delay(100);
             rt_pin_write(cfg->scl, PIN_LOW);
-            nu_soft_i2c_udelay(100);
+            rt_hw_us_delay(100);
         }
     }
     if (PIN_LOW == rt_pin_read(cfg->sda))

bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.h

@@ -16,7 +16,7 @@
 #include <rtconfig.h>
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <nu_bitutil.h>
 
 #if defined(BSP_USING_SPI_PDMA)

bsp/nuvoton/libraries/m2354/rtt_port/drv_spii2s.c

@@ -282,7 +282,8 @@ static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configu
         LOG_I("Open SPII2S.");
 
         /* Set MCLK and enable MCLK */
-        SPII2S_EnableMCLK(spii2s_base, __HXT);
+        /* The target MCLK is related to audio codec setting. */
+        SPII2S_EnableMCLK(spii2s_base, 12000000);
 
         /* Set un-mute */
         if (pNuACodecOps->nu_acodec_mixer_control)

bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c

@@ -15,7 +15,7 @@
 #if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER))
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define NU_TIMER_DEVICE(timer) (nu_timer_t *)(timer)

bsp/nuvoton/libraries/m2354/rtt_port/drv_timer_capture.c

@@ -21,7 +21,7 @@
     defined(BSP_USING_TIMER5_CAPTURE)
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private typedef --------------------------------------------------------------*/
 typedef struct _timer

bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <drv_uart.h>
 
 #if defined(RT_SERIAL_USING_DMA)

bsp/nuvoton/libraries/m2354/rtt_port/drv_ui2c.c

@@ -15,7 +15,7 @@
 #if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C))
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG          "drv.ui2c"

bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c

@@ -15,7 +15,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #include "usb.h"
 #include "usbh_lib.h"

bsp/nuvoton/libraries/m2354/rtt_port/drv_uspi.c

@@ -24,7 +24,7 @@
 #include <rtdevice.h>
 #include <rtdef.h>
 
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <nu_bitutil.h>
 
 #if defined(BSP_USING_USPI_PDMA)

bsp/nuvoton/libraries/m2354/rtt_port/drv_uuart.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #if defined(RT_SERIAL_USING_DMA)
     #include <drv_pdma.h>

bsp/nuvoton/libraries/m2354/rtt_port/drv_wdt.c

@@ -16,7 +16,7 @@
 #include <rthw.h>
 #include <rtdevice.h>
 #include <rtdbg.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /*-------------------------------------------------------------------------------*/
 /* watchdog timer timeout look up table                                          */

bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_BPWM_CAPTURE)
 #if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private typedef --------------------------------------------------------------*/
 typedef struct _bpwm_dev

bsp/nuvoton/libraries/m480/rtt_port/drv_can.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private Define ---------------------------------------------------------------*/
 #define RX_MSG_ID_INDEX        16

bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c

@@ -18,7 +18,7 @@
 #include <rtdbg.h>
 #include <stdint.h>
 #include <string.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 
 /* Private define ---------------------------------------------------------------*/

bsp/nuvoton/numaker-iot-m487/board/board.c → bsp/nuvoton/libraries/m480/rtt_port/drv_common.c

@@ -12,7 +12,7 @@
 
 #include <rtconfig.h>
 #include <rtthread.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include "drv_uart.h"
 #include "board.h"
 #include "nutool_pincfg.h"
@@ -20,9 +20,9 @@
 
 
 /**
- * This function will initial M487 board.
+ * This function will initial.
  */
-void rt_hw_board_init(void)
+RT_WEAK void rt_hw_board_init(void)
 {
     /* Init System/modules clock */
     nutool_modclkcfg_init();
@@ -67,6 +67,41 @@ void rt_hw_board_init(void)
 #endif
 }
 
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
 /**
  * This is the timer interrupt service routine.
  *
@@ -89,7 +124,7 @@ void rt_hw_cpu_reset(void)
     SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
 }
 
-int reboot(int argc, char** argv)
+int reboot(int argc, char **argv)
 {
     rt_hw_cpu_reset();
     return 0;

bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c

@@ -11,7 +11,7 @@
 
 #include <rtconfig.h>
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #ifdef BSP_USING_EADC
 

bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h

@@ -13,7 +13,7 @@
 #define __DRV_EBI_H___
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /**
   * @brief      Initialize EBI for specify Bank

bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_ECAP)
 #if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #define ECAP_CH0_POS    (0)
 #define ECAP_CH1_POS    (1)

bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c

@@ -17,7 +17,7 @@
 #if defined(RT_USING_LWIP)
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <netif/ethernetif.h>
 #include <netif/etharp.h>
 #include <lwip/icmp.h>

bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_EPWM_CAPTURE)
 #if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 #define EPWM_CH0CH1_POS    (0)
 #define EPWM_CH2CH3_POS    (2)

bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h

@@ -14,7 +14,7 @@
 #define __DRV_FMC_H__
 
 #include <rtthread.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 int nu_fmc_read(long offset, uint8_t *buf, size_t size);
 int nu_fmc_write(long offset, const uint8_t *buf, size_t size);

bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c

@@ -16,7 +16,7 @@
 
 #include <rtdevice.h>
 #include <rthw.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <nu_bitutil.h>
 #include <drv_gpio.h>
 #include <stdlib.h>

bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c

@@ -14,7 +14,7 @@
 #if defined(BSP_USING_HSOTG)
 #include <rtdevice.h>
 #include <rtdbg.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 
 /* This delay must be at least 10 us */

bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c

@@ -14,7 +14,7 @@
 
 #ifdef BSP_USING_I2C
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG         "drv.i2c"

bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c

@@ -220,7 +220,8 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
         }
 
         /* Set MCLK and enable MCLK */
-        I2S_EnableMCLK(psNuI2s->i2s_base, __HXT);
+        /* The target MCLK is related to audio codec setting. */
+        I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
 
         /* Set unmute */
         if (pNuACodecOps->nu_acodec_mixer_control)

bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h

@@ -14,7 +14,7 @@
 #define __DRV_I2S_H__
 
 #include <rtdevice.h>
-#include <NuMicro.h>
+#include "NuMicro.h"
 #include <drv_pdma.h>
 
 #if !defined(NU_I2S_DMA_FIFO_SIZE)