使用 AStyle.exe 统一代码格式

bsp/apm32/apm32f103xe-minibroard/board/SConscript

@@ -15,13 +15,13 @@ path =  [cwd]
 
 startup_path_prefix = SDK_LIB
 
-if rtconfig.CROSS_TOOL == 'keil':
+if rtconfig.PLATFORM in ['armcc', 'armclang']:
     src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/arm/startup_apm32f10x_hd.s']
 
-if rtconfig.CROSS_TOOL == 'iar':
+if rtconfig.PLATFORM in ['iccarm']:
     src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/iar/startup_apm32f10x_hd.s']
 
-if rtconfig.CROSS_TOOL == 'gcc':
+if rtconfig.PLATFORM in ['gcc']:
     src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/gcc/startup_apm32f10x_hd.s']
 
 # You can select chips from the list above

bsp/apm32/apm32f103xe-minibroard/project.uvoptx

@@ -73,11 +73,11 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
-      <CpuCode>0</CpuCode>
+      <CpuCode>255</CpuCode>
       <DebugOpt>
         <uSim>0</uSim>
         <uTrg>1</uTrg>
@@ -175,11 +175,747 @@
   </Target>
 
   <Group>
-    <GroupName>Source Group 1</GroupName>
+    <GroupName>Applications</GroupName>
+    <tvExp>1</tvExp>
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+    <cbSel>0</cbSel>
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+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
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+    <tvExpOptDlg>0</tvExpOptDlg>
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+      <tvExp>0</tvExp>
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+      <bDave2>0</bDave2>
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+      <FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
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+      <bShared>0</bShared>
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+      <tvExp>0</tvExp>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
+      <FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
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+      <bShared>0</bShared>
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+    <File>
+      <GroupNumber>2</GroupNumber>
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+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
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+      <PathWithFileName>..\..\..\components\libc\compilers\common\cctype.c</PathWithFileName>
+      <FilenameWithoutPath>cctype.c</FilenameWithoutPath>
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+      <bShared>0</bShared>
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+      <tvExpOptDlg>0</tvExpOptDlg>
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+      <bShared>0</bShared>
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+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
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+      <bShared>0</bShared>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\common\cstring.c</PathWithFileName>
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+
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     <tvExp>0</tvExp>
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     <cbSel>0</cbSel>
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   </Group>
 
 </ProjectOpt>

bsp/apm32/apm32f103xe-minibroard/project.uvprojx

@@ -1,7 +1,10 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
 <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
   <SchemaVersion>2.1</SchemaVersion>
+
   <Header>### uVision Project, (C) Keil Software</Header>
+
   <Targets>
     <Target>
       <TargetName>rt-thread</TargetName>
@@ -13,31 +16,31 @@
         <TargetCommonOption>
           <Device>APM32F103ZE</Device>
           <Vendor>Geehy</Vendor>
-          <PackID>Geehy.APM32F1xx_DFP.1.0.8</PackID>
+          <PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID>
           <PackURL>https://www.geehy.com/uploads/tool/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec />
-          <StartupFile />
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
           <RegisterFile>$$Device:APM32F103ZE$Device\Include\apm32f10x.h</RegisterFile>
-          <MemoryEnv />
-          <Cmp />
-          <Asm />
-          <Linker />
-          <OHString />
-          <InfinionOptionDll />
-          <SLE66CMisc />
-          <SLE66AMisc />
-          <SLE66LinkerMisc />
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
           <SFDFile>$$Device:APM32F103ZE$SVD\APM32F103xx.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
-          <BinPath />
-          <IncludePath />
-          <LibPath />
-          <RegisterFilePath />
-          <DBRegisterFilePath />
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -59,8 +62,8 @@
           <BeforeCompile>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopU1X>0</nStopU1X>
@@ -69,8 +72,8 @@
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopB1X>0</nStopB1X>
@@ -80,14 +83,14 @@
             <RunUserProg1>1</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
             <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
-            <UserProg2Name />
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString />
+          <SVCSIdString></SVCSIdString>
         </TargetCommonOption>
         <CommonProperty>
           <UseCPPCompiler>0</UseCPPCompiler>
@@ -101,8 +104,8 @@
           <AssembleAssemblyFile>0</AssembleAssemblyFile>
           <PublicsOnly>0</PublicsOnly>
           <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument />
-          <IncludeLibraryModules />
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
           <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
@@ -111,7 +114,7 @@
           <SimDlgDll>DCM.DLL</SimDlgDll>
           <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
           <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments />
+          <TargetDllArguments></TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
           <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
         </DllOption>
@@ -135,11 +138,11 @@
           </Flash1>
           <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3 />
-          <Flash4 />
-          <pFcarmOut />
-          <pFcarmGrp />
-          <pFcArmRoot />
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
           <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
@@ -172,7 +175,7 @@
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M3"</AdsCpuType>
-            <RvctDeviceName />
+            <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
             <uocRam>0</uocRam>
@@ -305,7 +308,7 @@
                 <Size>0x0</Size>
               </OCR_RVCT10>
             </OnChipMemories>
-            <RvctStartVector />
+            <RvctStartVector></RvctStartVector>
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
@@ -332,9 +335,9 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls />
+              <MiscControls></MiscControls>
               <Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC, APM32F10X_HD</Define>
-              <Undefine />
+              <Undefine></Undefine>
               <IncludePath>applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Include;..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\inc;..\libraries\APM32F10x_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
             </VariousControls>
           </Cads>
@@ -350,10 +353,10 @@
             <useXO>0</useXO>
             <uClangAs>0</uClangAs>
             <VariousControls>
-              <MiscControls />
-              <Define />
-              <Undefine />
-              <IncludePath />
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -365,13 +368,13 @@
             <useFile>0</useFile>
             <TextAddressRange>0x08000000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase />
+            <pXoBase></pXoBase>
             <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
-            <IncludeLibs />
-            <IncludeLibsPath />
-            <Misc />
-            <LinkerInputFile />
-            <DisabledWarnings />
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
           </LDads>
         </TargetArmAds>
       </TargetOption>
@@ -394,50 +397,36 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>syscalls.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cctype.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstdio.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstdlib.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstring.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ctime.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cwchar.c</FileName>
               <FileType>1</FileType>
@@ -453,29 +442,21 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>div0.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>showmem.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>context_rvds.S</FileName>
               <FileType>2</FileType>
               <FilePath>..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cpuport.c</FileName>
               <FileType>1</FileType>
@@ -491,57 +472,41 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>pipe.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ringblk_buf.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>pin.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>serial.c</FileName>
               <FileType>1</FileType>
@@ -557,29 +522,21 @@
               <FileType>1</FileType>
               <FilePath>board\board.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>startup_apm32f10x_hd.s</FileName>
               <FileType>2</FileType>
               <FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\arm\startup_apm32f10x_hd.s</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>drv_common.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\Drivers\drv_common.c</FilePath>
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-          </Files>
-          <Files>
             <File>
               <FileName>drv_gpio.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>drv_usart.c</FileName>
               <FileType>1</FileType>
@@ -595,22 +552,16 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\dfs\src\dfs_posix.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dfs_fs.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\dfs\src\dfs_fs.c</FilePath>
             </File>
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             <File>
               <FileName>dfs.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\dfs\src\dfs.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dfs_file.c</FileName>
               <FileType>1</FileType>
@@ -626,29 +577,21 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>msh.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cmd.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>msh_file.c</FileName>
               <FileType>1</FileType>
@@ -664,85 +607,61 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\src\clock.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>components.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\components.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>device.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\device.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>idle.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\idle.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ipc.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\ipc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>irq.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\irq.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>kservice.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\kservice.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>mem.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\mem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>mempool.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\mempool.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>object.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\object.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\scheduler.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>thread.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\thread.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>timer.c</FileName>
               <FileType>1</FileType>
@@ -758,36 +677,26 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F10x_Library\Device\Geehy\APM32F10x\Source\system_apm32f10x.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f10x_rcm.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_rcm.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f10x_misc.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_misc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f10x_usart.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_usart.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f10x_eint.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F10x_Library\APM32F10x_StdPeriphDriver\src\apm32f10x_eint.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f10x_gpio.c</FileName>
               <FileType>1</FileType>
@@ -798,9 +707,11 @@
       </Groups>
     </Target>
   </Targets>
+
   <RTE>
-    <apis />
-    <components />
-    <files />
+    <apis/>
+    <components/>
+    <files/>
   </RTE>
+
 </Project>

bsp/apm32/apm32f407ig-minibroard/board/board.c

@@ -23,14 +23,14 @@ void apm32_usart_init(void)
     GPIO_ConfigStruct.otype = GPIO_OTYPE_PP;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
     GPIO_Config(GPIOA, &GPIO_ConfigStruct);
-    GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_9,GPIO_AF_USART1);
+    GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_9, GPIO_AF_USART1);
 
     GPIO_ConfigStruct.mode = GPIO_MODE_IN;
     GPIO_ConfigStruct.pin = GPIO_PIN_10;
     GPIO_ConfigStruct.pupd = GPIO_PUPD_UP;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
     GPIO_Config(GPIOA, &GPIO_ConfigStruct);
-    GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_10,GPIO_AF_USART1);
+    GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_10, GPIO_AF_USART1);
 #endif
 
 #ifdef BSP_USING_UART2
@@ -42,13 +42,13 @@ void apm32_usart_init(void)
     GPIO_ConfigStruct.otype = GPIO_OTYPE_PP;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
     GPIO_Config(GPIOA, &GPIO_ConfigStruct);
-    GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_2,GPIO_AF_USART2);
+    GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_2, GPIO_AF_USART2);
 
     GPIO_ConfigStruct.mode = GPIO_MODE_IN;
     GPIO_ConfigStruct.pin = GPIO_PIN_3;
     GPIO_ConfigStruct.pupd = GPIO_PUPD_UP;
     GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
     GPIO_Config(GPIOA, &GPIO_ConfigStruct);
-    GPIO_ConfigPinAF(GPIOA,GPIO_PIN_SOURCE_3,GPIO_AF_USART2);
+    GPIO_ConfigPinAF(GPIOA, GPIO_PIN_SOURCE_3, GPIO_AF_USART2);
 #endif
 }

bsp/apm32/apm32f407ig-minibroard/project.uvoptx

@@ -175,11 +175,747 @@
   </Target>
 
   <Group>
-    <GroupName>Source Group 1</GroupName>
+    <GroupName>Applications</GroupName>
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+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Compiler</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</PathWithFileName>
+      <FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
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+      <FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\libc\compilers\common\cctype.c</PathWithFileName>
+      <FilenameWithoutPath>cctype.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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   </Group>
 
 </ProjectOpt>

bsp/apm32/apm32f407ig-minibroard/project.uvprojx

@@ -1,7 +1,10 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
 <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
   <SchemaVersion>2.1</SchemaVersion>
+
   <Header>### uVision Project, (C) Keil Software</Header>
+
   <Targets>
     <Target>
       <TargetName>rt-thread</TargetName>
@@ -16,28 +19,28 @@
           <PackID>Geehy.APM32F4xx_DFP.1.0.1</PackID>
           <PackURL>https://www.geehy.com/uploads/tool/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec />
-          <StartupFile />
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F4xx_1024 -FS08000000 -FL080000 -FP0($$Device:APM32F407IG$Flash\APM32F4xx_1024.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
-          <RegisterFile />
-          <MemoryEnv />
-          <Cmp />
-          <Asm />
-          <Linker />
-          <OHString />
-          <InfinionOptionDll />
-          <SLE66CMisc />
-          <SLE66AMisc />
-          <SLE66LinkerMisc />
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
           <SFDFile>$$Device:APM32F407IG$SVD\APM32F40x.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
-          <BinPath />
-          <IncludePath />
-          <LibPath />
-          <RegisterFilePath />
-          <DBRegisterFilePath />
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -59,8 +62,8 @@
           <BeforeCompile>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopU1X>0</nStopU1X>
@@ -69,8 +72,8 @@
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopB1X>0</nStopB1X>
@@ -80,14 +83,14 @@
             <RunUserProg1>1</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
             <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
-            <UserProg2Name />
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString />
+          <SVCSIdString></SVCSIdString>
         </TargetCommonOption>
         <CommonProperty>
           <UseCPPCompiler>0</UseCPPCompiler>
@@ -101,8 +104,8 @@
           <AssembleAssemblyFile>0</AssembleAssemblyFile>
           <PublicsOnly>0</PublicsOnly>
           <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument />
-          <IncludeLibraryModules />
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
           <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
@@ -135,11 +138,11 @@
           </Flash1>
           <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3 />
-          <Flash4 />
-          <pFcarmOut />
-          <pFcarmGrp />
-          <pFcArmRoot />
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
           <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
@@ -172,7 +175,7 @@
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M4"</AdsCpuType>
-            <RvctDeviceName />
+            <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
             <uocRam>0</uocRam>
@@ -305,7 +308,7 @@
                 <Size>0x10000</Size>
               </OCR_RVCT10>
             </OnChipMemories>
-            <RvctStartVector />
+            <RvctStartVector></RvctStartVector>
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
@@ -332,9 +335,9 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls />
+              <MiscControls></MiscControls>
               <Define>__STDC_LIMIT_MACROS, USE_STDPERIPH_DRIVER, RT_USING_LIBC, APM32F40X, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARM_LIBC</Define>
-              <Undefine />
+              <Undefine></Undefine>
               <IncludePath>applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\Drivers;..\libraries\Drivers\config;..\..\..\components\dfs\include;..\..\..\components\finsh;.;..\..\..\include;..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Include;..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\inc;..\libraries\APM32F4xx_Library\CMSIS\Include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc</IncludePath>
             </VariousControls>
           </Cads>
@@ -350,10 +353,10 @@
             <useXO>0</useXO>
             <uClangAs>0</uClangAs>
             <VariousControls>
-              <MiscControls />
-              <Define />
-              <Undefine />
-              <IncludePath />
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -365,13 +368,13 @@
             <useFile>0</useFile>
             <TextAddressRange>0x08000000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase />
+            <pXoBase></pXoBase>
             <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
-            <IncludeLibs />
-            <IncludeLibsPath />
-            <Misc />
-            <LinkerInputFile />
-            <DisabledWarnings />
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
           </LDads>
         </TargetArmAds>
       </TargetOption>
@@ -394,50 +397,36 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>syscalls.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cctype.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstdio.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstdlib.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cstring.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ctime.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cwchar.c</FileName>
               <FileType>1</FileType>
@@ -453,29 +442,21 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>div0.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>showmem.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>context_rvds.S</FileName>
               <FileType>2</FileType>
               <FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cpuport.c</FileName>
               <FileType>1</FileType>
@@ -491,57 +472,41 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>pipe.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ringblk_buf.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>pin.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>serial.c</FileName>
               <FileType>1</FileType>
@@ -557,29 +522,21 @@
               <FileType>1</FileType>
               <FilePath>board\board.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>startup_apm32f40x.s</FileName>
               <FileType>2</FileType>
               <FilePath>..\libraries\APM32F4xx_Library\Device\Geehy\APM32F4xx\Source\arm\startup_apm32f40x.s</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>drv_common.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\Drivers\drv_common.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>drv_gpio.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\Drivers\drv_gpio.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>drv_usart.c</FileName>
               <FileType>1</FileType>
@@ -595,22 +552,16 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\dfs\src\dfs_posix.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dfs_fs.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\dfs\src\dfs_fs.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dfs.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\dfs\src\dfs.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>dfs_file.c</FileName>
               <FileType>1</FileType>
@@ -626,29 +577,21 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\shell.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>msh.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\msh.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>msh_parse.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>cmd.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>msh_file.c</FileName>
               <FileType>1</FileType>
@@ -664,85 +607,61 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\src\clock.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>components.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\components.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>device.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\device.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>idle.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\idle.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ipc.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\ipc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>irq.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\irq.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>kservice.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\kservice.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>mem.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\mem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>mempool.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\mempool.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>object.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\object.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\scheduler.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>thread.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\thread.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>timer.c</FileName>
               <FileType>1</FileType>
@@ -758,36 +677,26 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_usart.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f4xx_rcm.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_rcm.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f4xx_eint.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_eint.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f4xx_misc.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_misc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>apm32f4xx_gpio.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\APM32F4xx_Library\APM32F4xx_StdPeriphDriver\src\apm32f4xx_gpio.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>system_apm32f4xx.c</FileName>
               <FileType>1</FileType>
@@ -798,9 +707,11 @@
       </Groups>
     </Target>
   </Targets>
+
   <RTE>
-    <apis />
-    <components />
-    <files />
+    <apis/>
+    <components/>
+    <files/>
   </RTE>
+
 </Project>

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_adc.c

@@ -47,14 +47,14 @@
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Reset(ADC_T* adc)
+void ADC_Reset(ADC_T *adc)
 {
-    if(adc == ADC1)
+    if (adc == ADC1)
     {
         RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
         RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC1);
     }
-    else if(adc == ADC2)
+    else if (adc == ADC2)
     {
         RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2);
         RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_ADC2);
@@ -77,7 +77,7 @@ void ADC_Reset(ADC_T* adc)
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
+void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
 {
     uint32_t reg;
 
@@ -107,7 +107,7 @@ void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
  *
  * @retval      None
  */
-void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
+void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
 {
     adcConfig->mode = ADC_MODE_INDEPENDENT;
     adcConfig->scanConvMode = DISABLE;
@@ -126,7 +126,7 @@ void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
  *
  * @note        adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Enable(ADC_T* adc)
+void ADC_Enable(ADC_T *adc)
 {
     adc->CTRL2_B.ADCEN = BIT_SET;
 }
@@ -140,7 +140,7 @@ void ADC_Enable(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_Disable(ADC_T* adc)
+void ADC_Disable(ADC_T *adc)
 {
     adc->CTRL2_B.ADCEN = BIT_RESET;
 }
@@ -154,7 +154,7 @@ void ADC_Disable(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableDMA(ADC_T* adc)
+void ADC_EnableDMA(ADC_T *adc)
 {
     adc->CTRL2_B.DMAEN = BIT_SET;
 }
@@ -168,7 +168,7 @@ void ADC_EnableDMA(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableDMA(ADC_T* adc)
+void ADC_DisableDMA(ADC_T *adc)
 {
     adc->CTRL2_B.DMAEN = BIT_RESET;
 }
@@ -182,7 +182,7 @@ void ADC_DisableDMA(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ResetCalibration(ADC_T* adc)
+void ADC_ResetCalibration(ADC_T *adc)
 {
     adc->CTRL2_B.CALRST = BIT_SET;
 }
@@ -196,7 +196,7 @@ void ADC_ResetCalibration(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc)
+uint8_t ADC_ReadResetCalibrationStatus(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.CALRST) ? BIT_SET : BIT_RESET;
@@ -212,7 +212,7 @@ uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_StartCalibration(ADC_T* adc)
+void ADC_StartCalibration(ADC_T *adc)
 {
     adc->CTRL2_B.CAL = BIT_SET;
 }
@@ -226,7 +226,7 @@ void ADC_StartCalibration(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc)
+uint8_t ADC_ReadCalibrationStartFlag(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.CAL) ? BIT_SET : BIT_RESET;
@@ -242,7 +242,7 @@ uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableSoftwareStartConv(ADC_T* adc)
+void ADC_EnableSoftwareStartConv(ADC_T *adc)
 {
     adc->CTRL2 |= 0x00500000;
 }
@@ -256,7 +256,7 @@ void ADC_EnableSoftwareStartConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableSoftwareStartConv(ADC_T* adc)
+void ADC_DisableSoftwareStartConv(ADC_T *adc)
 {
     adc->CTRL2 &= 0xFFAFFFFF;
 }
@@ -270,7 +270,7 @@ void ADC_DisableSoftwareStartConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.REGSWSC) ? BIT_SET : BIT_RESET;
@@ -289,7 +289,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number)
+void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
 {
     adc->CTRL1_B.DISCNUMCFG |= number - 1;
 }
@@ -303,7 +303,7 @@ void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableDiscMode(ADC_T* adc)
+void ADC_EnableDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_SET;
 }
@@ -317,7 +317,7 @@ void ADC_EnableDiscMode(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableDiscMode(ADC_T* adc)
+void ADC_DisableDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_RESET;
 }
@@ -366,11 +366,11 @@ void ADC_DisableDiscMode(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
-    if(channel > ADC_CHANNEL_9)
+    if (channel > ADC_CHANNEL_9)
     {
         temp1 = adc->SMPTIM1;
         temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10));
@@ -389,7 +389,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t
         adc->SMPTIM2 = temp1;
     }
 
-    if(rank < 7)
+    if (rank < 7)
     {
         temp1 = adc->REGSEQ3;
         temp2 = REGSEQC_SET_REGSEQ3 << (5 * (rank - 1));
@@ -398,7 +398,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t
         temp1 |= temp2;
         adc->REGSEQ3 = temp1;
     }
-    else if(rank < 13)
+    else if (rank < 13)
     {
         temp1 = adc->REGSEQ2;
         temp2 = REGSEQC_SET_REGSEQ2 << (5 * (rank - 7));
@@ -427,7 +427,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableExternalTrigConv(ADC_T* adc)
+void ADC_EnableExternalTrigConv(ADC_T *adc)
 {
     adc->CTRL2_B.REGEXTTRGEN = BIT_SET;
 }
@@ -441,7 +441,7 @@ void ADC_EnableExternalTrigConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableExternalTrigConv(ADC_T* adc)
+void ADC_DisableExternalTrigConv(ADC_T *adc)
 {
     adc->CTRL2_B.REGEXTTRGEN = BIT_RESET;
 }
@@ -455,7 +455,7 @@ void ADC_DisableExternalTrigConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint16_t ADC_ReadConversionValue(ADC_T* adc)
+uint16_t ADC_ReadConversionValue(ADC_T *adc)
 {
     return (uint16_t) adc->REGDATA;
 }
@@ -469,7 +469,7 @@ uint16_t ADC_ReadConversionValue(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc)
+uint32_t ADC_ReadDualModeConversionValue(ADC_T *adc)
 {
     return (*(__IOM uint32_t *) RDG_ADDRESS);
 }
@@ -483,7 +483,7 @@ uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableAutoInjectedConv(ADC_T* adc)
+void ADC_EnableAutoInjectedConv(ADC_T *adc)
 {
     adc->CTRL1_B.INJGACEN = BIT_SET;
 }
@@ -497,7 +497,7 @@ void ADC_EnableAutoInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableAutoInjectedConv(ADC_T* adc)
+void ADC_DisableAutoInjectedConv(ADC_T *adc)
 {
     adc->CTRL1_B.INJGACEN = BIT_RESET;
 }
@@ -511,7 +511,7 @@ void ADC_DisableAutoInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInjectedDiscMode(ADC_T* adc)
+void ADC_EnableInjectedDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_SET;
 }
@@ -525,7 +525,7 @@ void ADC_EnableInjectedDiscMode(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInjectedDiscMode(ADC_T* adc)
+void ADC_DisableInjectedDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_RESET;
 }
@@ -558,7 +558,7 @@ void ADC_DisableInjectedDiscMode(ADC_T* adc)
  *
  * @note    adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
+void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
 {
     adc->CTRL2_B.INJGEXTTRGSEL = RESET;
     adc->CTRL2_B.INJGEXTTRGSEL |= extTrigInjecConv;
@@ -573,7 +573,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T ex
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableExternalTrigInjectedConv(ADC_T* adc)
+void ADC_EnableExternalTrigInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
 }
@@ -587,7 +587,7 @@ void ADC_EnableExternalTrigInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableExternalTrigInjectedConv(ADC_T* adc)
+void ADC_DisableExternalTrigInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
 }
@@ -601,7 +601,7 @@ void ADC_DisableExternalTrigInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
+void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_SET;
     adc->CTRL2_B.INJSWSC = BIT_SET;
@@ -616,7 +616,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc)
+void ADC_DisableSoftwareStartInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJEXTTRGEN = BIT_RESET;
     adc->CTRL2_B.INJSWSC = BIT_RESET;
@@ -631,7 +631,7 @@ void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
 {
     uint8_t ret;
     ret = (adc->CTRL2_B.INJSWSC) ? BIT_SET : BIT_RESET;
@@ -682,7 +682,7 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
@@ -690,9 +690,9 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
     if (channel > ADC_CHANNEL_9)
     {
         temp1 = adc->SMPTIM1;
-        temp2 = SMPCYCCFG_SET_SMPTIM1 << (3*(channel - 10));
+        temp2 = SMPCYCCFG_SET_SMPTIM1 << (3 * (channel - 10));
         temp1 &= ~temp2;
-        temp2 = (uint32_t)sampleTime << (3*(channel - 10));
+        temp2 = (uint32_t)sampleTime << (3 * (channel - 10));
         temp1 |= temp2;
         adc->SMPTIM1 = temp1;
     }
@@ -706,7 +706,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
         adc->SMPTIM2 = temp1;
     }
     temp1 = adc->INJSEQ;
-    temp3 =  (temp1 & INJSEQ_SET_INJSEQLEN)>> 20;
+    temp3 = (temp1 & INJSEQ_SET_INJSEQLEN) >> 20;
     temp2 = INJSEQ_SET_INJSEQC << (5 * (uint8_t)((rank + 3) - (temp3 + 1)));
     temp1 &= ~temp2;
     temp2 = (uint32_t)channel << (5 * (uint8_t)((rank + 3) - (temp3 + 1)));
@@ -726,7 +726,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
  *
  * @note     adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
+void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
 {
     adc->INJSEQ_B.INJSEQLEN = RESET;
     adc->INJSEQ_B.INJSEQLEN |= length - 1;
@@ -751,7 +751,7 @@ void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
+void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet)
 {
     __IOM uint32_t tmp = 0;
 
@@ -777,14 +777,14 @@ void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel)
+uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel)
 {
     __IOM uint32_t temp = 0;
 
     temp = (uint32_t)adc;
     temp += channel + INJDATA_OFFSET;
 
-    return (uint16_t) (*(__IOM uint32_t*)  temp);
+    return (uint16_t)(*(__IOM uint32_t *)  temp);
 }
 
 /*!
@@ -806,7 +806,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog)
+void ADC_EnableAnalogWatchdog(ADC_T *adc, uint32_t analogWatchdog)
 {
     adc->CTRL1 &= 0xFF3FFDFF;
     adc->CTRL1 |= analogWatchdog;
@@ -821,7 +821,7 @@ void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableAnalogWatchdog(ADC_T* adc)
+void ADC_DisableAnalogWatchdog(ADC_T *adc)
 {
     adc->CTRL1 &= 0xFF3FFDFF;
 }
@@ -841,7 +841,7 @@ void ADC_DisableAnalogWatchdog(ADC_T* adc)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold)
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold)
 {
     adc->AWDHT = highThreshold;
     adc->AWDLT = lowThreshold;
@@ -877,7 +877,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
 {
     adc->CTRL1_B.AWDCHSEL = BIT_RESET;
     adc->CTRL1 |= channel;
@@ -892,7 +892,7 @@ void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableTempSensorVrefint(ADC_T* adc)
+void ADC_EnableTempSensorVrefint(ADC_T *adc)
 {
     adc->CTRL2_B.TSVREFEN = BIT_SET;
 }
@@ -906,7 +906,7 @@ void ADC_EnableTempSensorVrefint(ADC_T* adc)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableTempSensorVrefint(ADC_T* adc)
+void ADC_DisableTempSensorVrefint(ADC_T *adc)
 {
     adc->CTRL2_B.TSVREFEN = BIT_RESET;
 }
@@ -926,7 +926,7 @@ void ADC_DisableTempSensorVrefint(ADC_T* adc)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt)
+void ADC_EnableInterrupt(ADC_T *adc, uint16_t interrupt)
 {
     uint8_t mask;
 
@@ -949,7 +949,7 @@ void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt)
+void ADC_DisableInterrupt(ADC_T *adc, uint16_t interrupt)
 {
     uint8_t mask;
 
@@ -974,7 +974,7 @@ void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
+uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
 {
     return (adc->STS & flag) ? SET : RESET;
 }
@@ -996,7 +996,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
  *
  * @note      adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag)
+void ADC_ClearStatusFlag(ADC_T *adc, uint8_t flag)
 {
     adc->STS = ~(uint32_t)flag;
 }
@@ -1016,7 +1016,7 @@ void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag)
+uint8_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_T flag)
 {
     uint8_t bitStatus = RESET;
     uint32_t itmask = 0;
@@ -1051,7 +1051,7 @@ uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T flag)
  *
  * @note         adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ClearIntFlag(ADC_T* adc, uint16_t flag)
+void ADC_ClearIntFlag(ADC_T *adc, uint16_t flag)
 {
     uint8_t mask = 0;
 

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_bakpr.c

@@ -128,16 +128,19 @@ void BAKPR_DisableInterrupt(void)
  */
 void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure)
 {
-    if(soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
+    if (soure == BAKPR_RTC_OUTPUT_SOURCE_NONE)
     {
         BAKPR->CLKCAL = RESET;
-    } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
+    }
+    else if (soure == BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK)
     {
         BAKPR->CLKCAL_B.CALCOEN = BIT_SET;
-    } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
+    }
+    else if (soure == BAKPR_RTC_OUTPUT_SOURCE_ALARM)
     {
         BAKPR->CLKCAL_B.ASPOEN = BIT_SET;
-    } else if(soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
+    }
+    else if (soure == BAKPR_RTC_OUTPUT_SOURCE_SECOND)
     {
         BAKPR->CLKCAL_B.ASPOSEL = BIT_SET;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_can.c

@@ -47,7 +47,7 @@
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_Reset(CAN_T* can)
+void CAN_Reset(CAN_T *can)
 {
     if (can == CAN1)
     {
@@ -72,7 +72,7 @@ void CAN_Reset(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
+uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
 {
     uint8_t  initStatus = ERROR;
     uint32_t wait_ack = 0x00000000;
@@ -83,18 +83,18 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
     can->MCTRL_B.INITREQ = BIT_SET;
 
     /** Wait the acknowledge */
-    while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
+    while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
     {
         wait_ack++;
     }
     /** Check acknowledge */
-    if(((can->MSTS_B.INITFLG) != BIT_SET))
+    if (((can->MSTS_B.INITFLG) != BIT_SET))
     {
         initStatus = ERROR;
     }
     else
     {
-        if(canConfig->autoBusOffManage == ENABLE)
+        if (canConfig->autoBusOffManage == ENABLE)
         {
             can->MCTRL_B.ALBOFFM = BIT_SET;
         }
@@ -103,7 +103,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.ALBOFFM = BIT_RESET;
         }
 
-        if(canConfig->autoWakeUpMode == ENABLE)
+        if (canConfig->autoWakeUpMode == ENABLE)
         {
             can->MCTRL_B.AWUPCFG = BIT_SET;
         }
@@ -112,7 +112,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.AWUPCFG = BIT_RESET;
         }
 
-        if(canConfig->nonAutoRetran == ENABLE)
+        if (canConfig->nonAutoRetran == ENABLE)
         {
             can->MCTRL_B.ARTXMD = BIT_SET;
         }
@@ -121,7 +121,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.ARTXMD = BIT_RESET;
         }
 
-        if(canConfig->rxFIFOLockMode == ENABLE)
+        if (canConfig->rxFIFOLockMode == ENABLE)
         {
             can->MCTRL_B.RXFLOCK = BIT_SET;
         }
@@ -130,7 +130,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.RXFLOCK = BIT_RESET;
         }
 
-        if(canConfig->txFIFOPriority == ENABLE)
+        if (canConfig->txFIFOPriority == ENABLE)
         {
             can->MCTRL_B.TXFPCFG = BIT_SET;
         }
@@ -152,12 +152,12 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
 
         wait_ack = 0;
         /** Wait the acknowledge */
-        while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
+        while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
         {
             wait_ack++;
         }
         /** Check acknowledge */
-        if(((can->MSTS_B.INITFLG) != BIT_RESET))
+        if (((can->MSTS_B.INITFLG) != BIT_RESET))
         {
             initStatus = ERROR;
         }
@@ -180,14 +180,14 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
+void CAN_ConfigFilter(CAN_T *can, CAN_FilterConfig_T *filterConfig)
 {
     can->FCTRL_B.FINITEN = BIT_SET;
 
     can->FACT &= ~(1 << filterConfig->filterNumber);
 
     /** Filter Scale */
-    if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
     {
         /** 16-bit scale for the filter */
         can->FSCFG &= ~(1 << filterConfig->filterNumber);
@@ -201,7 +201,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
             (0x0000FFFF & filterConfig->filterIdHigh);
     }
 
-    if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
     {
         can->FSCFG |= (1 << filterConfig->filterNumber);
 
@@ -215,7 +215,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
     }
 
     /** Filter Mode */
-    if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
+    if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
     {
         can->FMCFG &= ~(1 << filterConfig->filterNumber);
     }
@@ -225,17 +225,17 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
     }
 
     /** Filter FIFO assignment */
-    if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
     {
         can->FFASS &= ~(1 << filterConfig->filterNumber);
     }
-    if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
     {
         can->FFASS |= (1 << filterConfig->filterNumber);
     }
 
     /** Filter activation */
-    if(filterConfig->filterActivation == ENABLE)
+    if (filterConfig->filterActivation == ENABLE)
     {
         can->FACT |= (1 << filterConfig->filterNumber);
     }
@@ -251,7 +251,7 @@ void CAN_ConfigFilter(CAN_T* can, CAN_FilterConfig_T* filterConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ConfigStructInit(CAN_Config_T* canConfig)
+void CAN_ConfigStructInit(CAN_Config_T *canConfig)
 {
     canConfig->autoBusOffManage = DISABLE;
     canConfig->autoWakeUpMode   = DISABLE;
@@ -274,7 +274,7 @@ void CAN_ConfigStructInit(CAN_Config_T* canConfig)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_EnableDBGFreeze(CAN_T* can)
+void CAN_EnableDBGFreeze(CAN_T *can)
 {
     can->MCTRL_B.DBGFRZE = ENABLE;
 }
@@ -288,7 +288,7 @@ void CAN_EnableDBGFreeze(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableDBGFreeze(CAN_T* can)
+void CAN_DisableDBGFreeze(CAN_T *can)
 {
     can->MCTRL_B.DBGFRZE = DISABLE;
 }
@@ -300,7 +300,7 @@ void CAN_DisableDBGFreeze(CAN_T* can)
  *
  * @retval    None
  */
-void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum)
+void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
 {
     can->FCTRL_B.FINITEN = SET;
     can->FCTRL_B.CAN2BN  = bankNum;
@@ -318,33 +318,35 @@ void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
+uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
 {
     uint8_t transmit_milbox = 0;
 
     /** Select one empty transmit mailbox */
-    if((can->TXSTS & 0x04000000) == 0x04000000)
+    if ((can->TXSTS & 0x04000000) == 0x04000000)
     {
         transmit_milbox = 0;
     }
-    else if((can->TXSTS & 0x08000000) == 0x08000000)
+    else if ((can->TXSTS & 0x08000000) == 0x08000000)
     {
         transmit_milbox = 1;
     }
-    else if((can->TXSTS & 0x10000000) == 0x10000000)
+    else if ((can->TXSTS & 0x10000000) == 0x10000000)
     {
         transmit_milbox = 2;
-    } else
+    }
+    else
     {
         return 3;  //!< No mailbox is empty
     }
 
     /** Set up the Id */
     can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001;
-    if(TxMessage->typeID == CAN_TYPEID_STD)
+    if (TxMessage->typeID == CAN_TYPEID_STD)
     {
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq);
-    } else
+    }
+    else
     {
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq);
     }
@@ -378,45 +380,53 @@ uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
+uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
 {
     uint32_t state = 0;
 
     switch (TxMailbox)
     {
-        case (CAN_TX_MAILBIX_0):
-            state =   can->TXSTS &  (0x00000001 | 0x00000002 | 0x04000000);
+    case (CAN_TX_MAILBIX_0):
+        state =   can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
         break;
-        case (CAN_TX_MAILBIX_1):
-            state =   can->TXSTS &  (0x00000100 | 0x00000200 | 0x08000000);
+    case (CAN_TX_MAILBIX_1):
+        state =   can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
         break;
-        case (CAN_TX_MAILBIX_2):
-            state =   can->TXSTS &  (0x00010000 | 0x00020000 | 0x10000000);
+    case (CAN_TX_MAILBIX_2):
+        state =   can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
         break;
-        default:
-            state = 0;
+    default:
+        state = 0;
         break;
     }
     switch (state)
     {
-        /** Transmit pending  */
-        case (0x0): state = 2;
+    /** Transmit pending  */
+    case (0x0):
+        state = 2;
         break;
-        /** Transmit failed  */
-        case (0x00000001 | 0x04000000): state = 0;
+    /** Transmit failed  */
+    case (0x00000001 | 0x04000000):
+        state = 0;
         break;
-        case (0x00000100 | 0x08000000): state = 0;
+    case (0x00000100 | 0x08000000):
+        state = 0;
         break;
-        case (0x00010000 | 0x10000000): state = 0;
+    case (0x00010000 | 0x10000000):
+        state = 0;
         break;
-        /** Transmit succeeded  */
-        case (0x00000001 | 0x00000002 | 0x04000000):state = 1;
+    /** Transmit succeeded  */
+    case (0x00000001 | 0x00000002 | 0x04000000):
+        state = 1;
         break;
-        case (0x00000100 | 0x00000200 | 0x08000000):state = 1;
+    case (0x00000100 | 0x00000200 | 0x08000000):
+        state = 1;
         break;
-        case (0x00010000 | 0x00020000 | 0x10000000):state = 1;
+    case (0x00010000 | 0x00020000 | 0x10000000):
+        state = 1;
         break;
-        default: state = 0;
+    default:
+        state = 0;
         break;
     }
     return (uint8_t) state;
@@ -437,7 +447,7 @@ uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
+void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
 {
     switch (TxMailbox)
     {
@@ -471,11 +481,11 @@ void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage)
+void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage)
 {
     /** Get the Id */
     RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID));
-    if(RxMessage->typeID == CAN_TYPEID_STD)
+    if (RxMessage->typeID == CAN_TYPEID_STD)
     {
         RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF;
     }
@@ -497,7 +507,7 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMess
     RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6;
     RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7;
 
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         can->RXF0_B.RFOM0 = BIT_SET;
     }
@@ -521,9 +531,9 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMess
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
+void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
 {
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         can->RXF0_B.RFOM0 = BIT_SET;
     }
@@ -547,9 +557,9 @@ void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
+uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
 {
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         return  can->RXF0 & 0x03;
     }
@@ -576,53 +586,53 @@ uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
+uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
 {
     uint8_t states = 0;
     uint32_t time_out = 0x0000FFFF;
 
-    if(operatingMode == CAN_OPERATING_MODE_INIT)
+    if (operatingMode == CAN_OPERATING_MODE_INIT)
     {
         can->MCTRL_B.SLEEPREQ = BIT_RESET;
         can->MCTRL_B.INITREQ = BIT_SET;
 
-        while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
+        if ((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
         {
             states = 1;
         }
     }
-    else if(operatingMode == CAN_OPERATING_MODE_NORMAL)
+    else if (operatingMode == CAN_OPERATING_MODE_NORMAL)
     {
         can->MCTRL_B.SLEEPREQ = BIT_RESET;
         can->MCTRL_B.INITREQ = BIT_RESET;
 
         time_out = 0x0000FFFF;
 
-        while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
+        if ((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
         {
             states = 1;
         }
     }
-    else if(operatingMode == CAN_OPERATING_MODE_SLEEP)
+    else if (operatingMode == CAN_OPERATING_MODE_SLEEP)
     {
         can->MCTRL_B.SLEEPREQ = BIT_SET;
         can->MCTRL_B.INITREQ = BIT_RESET;
 
         time_out = 0x0000FFFF;
 
-        while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
+        if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
         {
             states = 1;
         }
@@ -641,12 +651,12 @@ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_SleepMode(CAN_T* can)
+uint8_t CAN_SleepMode(CAN_T *can)
 {
     can->MCTRL_B.SLEEPREQ = BIT_SET;
     can->MCTRL_B.INITREQ = BIT_RESET;
 
-    if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
+    if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
     {
         return 1;
     }
@@ -664,16 +674,16 @@ uint8_t CAN_SleepMode(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_WakeUpMode(CAN_T* can)
+uint8_t CAN_WakeUpMode(CAN_T *can)
 {
     uint32_t time_out = 0x0000FFFF;
 
     can->MCTRL_B.SLEEPREQ = BIT_RESET;
-    while((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+    while ((can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
     {
         time_out --;
     }
-    if(can->MSTS_B.SLEEPFLG == BIT_RESET)
+    if (can->MSTS_B.SLEEPFLG == BIT_RESET)
     {
         return 1;
     }
@@ -689,7 +699,7 @@ uint8_t CAN_WakeUpMode(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadLastErrorCode(CAN_T* can)
+uint8_t CAN_ReadLastErrorCode(CAN_T *can)
 {
     return can->ERRSTS_B.LERRC;
 }
@@ -703,7 +713,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
+uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
 {
     return can->ERRSTS_B.RXERRCNT;
 }
@@ -717,7 +727,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
 {
     return can->ERRSTS_B.TXERRCNT;
 }
@@ -748,7 +758,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
+void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
 {
     can->INTEN |= interrupts;
 }
@@ -779,7 +789,7 @@ void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
+void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
 {
     can->INTEN &= ~interrupts;
 }
@@ -811,13 +821,13 @@ void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
+uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
 {
     uint8_t status = 0;
 
-    if((flag & 0x00F00000) != RESET )
+    if ((flag & 0x00F00000) != RESET)
     {
-        if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
+        if ((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -826,9 +836,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET;
         }
     }
-    else if((flag & 0x01000000) != RESET )
+    else if ((flag & 0x01000000) != RESET)
     {
-        if((can->MSTS & (flag & 0x000FFFFF)) != RESET )
+        if ((can->MSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -837,9 +847,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET ;
         }
     }
-    else if((flag & 0x08000000) != RESET )
+    else if ((flag & 0x08000000) != RESET)
     {
-        if((can->TXSTS & (flag & 0x000FFFFF)) != RESET )
+        if ((can->TXSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -848,9 +858,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET;
         }
     }
-    else if((flag & 0x02000000) != RESET )
+    else if ((flag & 0x02000000) != RESET)
     {
-        if((can->RXF0 & (flag & 0x000FFFFF)) != RESET )
+        if ((can->RXF0 & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -861,7 +871,7 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
     }
     else
     {
-        if((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
+        if ((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -895,27 +905,27 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
+void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
 {
     uint32_t flagtmp = 0;
 
     /** ERRSTS register */
-    if(flag == 0x30F00070)
+    if (flag == 0x30F00070)
     {
         can->ERRSTS = RESET;
     }
     else
     {
         flagtmp = flag & 0x000FFFFF;
-        if((flag & 0x02000000) != RESET)
+        if ((flag & 0x02000000) != RESET)
         {
             can->RXF0 = flagtmp;
         }
-        else if((flag & 0x04000000) != RESET)
+        else if ((flag & 0x04000000) != RESET)
         {
             can->RXF1 = flagtmp;
         }
-        else if((flag & 0x08000000) != RESET)
+        else if ((flag & 0x08000000) != RESET)
         {
             can->TXSTS = flagtmp;
         }
@@ -952,11 +962,11 @@ void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
+uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
 {
     uint8_t status = 0;
 
-    if((can->INTEN & flag) != RESET)
+    if ((can->INTEN & flag) != RESET)
     {
         switch (flag)
         {
@@ -1040,7 +1050,7 @@ uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
  *
  * @note      CAN2 applies only to APM32F103xC device.
  */
-void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag)
+void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag)
 {
     switch (flag)
     {

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_crc.c

@@ -75,7 +75,7 @@ uint32_t CRC_CalculateCRC(uint32_t data)
  */
 uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
 {
-    while(bufLen--)
+    while (bufLen--)
     {
         CRC->DATA = *buf++;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dac.c

@@ -63,7 +63,7 @@ void DAC_Reset(void)
  *
  * @retval       None
  */
-void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
+void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
 {
     uint32_t tmp1 = 0, tmp2 = 0;
 
@@ -88,7 +88,7 @@ void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
  *
  * @retval       None
  */
-void DAC_ConfigStructInit(DAC_Config_T* dacConfig)
+void DAC_ConfigStructInit(DAC_Config_T *dacConfig)
 {
     /** Initialize the DAC_Trigger member */
     dacConfig->trigger = DAC_TRIGGER_NONE;
@@ -403,7 +403,7 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
     tmp += 0x0000002C + ((uint32_t)channel >> 2);
 
     /** Returns the DAC channel data output register value */
-    return (uint16_t) (*(__IO uint32_t*) tmp);
+    return (uint16_t)(*(__IO uint32_t *) tmp);
 }
 
 /**@} end of group DAC_Fuctions*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dbgmcu.c

@@ -46,7 +46,7 @@
  */
 uint32_t DBGMCU_ReadDEVID(void)
 {
-   return(DBGMCU->IDCODE_B.EQR);
+    return (DBGMCU->IDCODE_B.EQR);
 }
 
 /*!
@@ -58,7 +58,7 @@ uint32_t DBGMCU_ReadDEVID(void)
  */
 uint32_t DBGMCU_ReadREVID(void)
 {
-   return(DBGMCU->IDCODE_B.WVR);
+    return (DBGMCU->IDCODE_B.WVR);
 }
 
 /*!

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dma.c

@@ -54,51 +54,51 @@ void DMA_Reset(DMA_Channel_T *channel)
     channel->CHMADDR = 0;
     channel->CHPADDR = 0;
 
-    if(channel == DMA1_Channel1)
+    if (channel == DMA1_Channel1)
     {
         DMA1->INTFCLR |= 0xFFFFFFF0;
     }
-    else if(channel == DMA1_Channel2)
+    else if (channel == DMA1_Channel2)
     {
         DMA1->INTFCLR |= 0xFFFFFF0F;
     }
-    else if(channel == DMA1_Channel3)
+    else if (channel == DMA1_Channel3)
     {
         DMA1->INTFCLR |= 0xFFFFF0FF;
     }
-    else if(channel == DMA1_Channel4)
+    else if (channel == DMA1_Channel4)
     {
         DMA1->INTFCLR |= 0xFFFF0FFF;
     }
-    else if(channel == DMA1_Channel5)
+    else if (channel == DMA1_Channel5)
     {
         DMA1->INTFCLR |= 0xFFF0FFFF;
     }
-    else if(channel == DMA1_Channel6)
+    else if (channel == DMA1_Channel6)
     {
         DMA1->INTFCLR |= 0xFF0FFFFF;
     }
-    else if(channel == DMA1_Channel7)
+    else if (channel == DMA1_Channel7)
     {
         DMA1->INTFCLR |= 0xF0FFFFFF;
     }
-    else if(channel == DMA2_Channel1)
+    else if (channel == DMA2_Channel1)
     {
         DMA2->INTFCLR |= 0xFFFFFFF0;
     }
-    else if(channel == DMA2_Channel2)
+    else if (channel == DMA2_Channel2)
     {
         DMA2->INTFCLR |= 0xFFFFFF0F;
     }
-    else if(channel == DMA2_Channel3)
+    else if (channel == DMA2_Channel3)
     {
         DMA2->INTFCLR |= 0xFFFFF0FF;
     }
-    else if(channel == DMA2_Channel4)
+    else if (channel == DMA2_Channel4)
     {
         DMA2->INTFCLR |= 0xFFFF0FFF;
     }
-    else if(channel == DMA2_Channel5)
+    else if (channel == DMA2_Channel5)
     {
         DMA2->INTFCLR |= 0xFFF0FFFF;
     }
@@ -115,7 +115,7 @@ void DMA_Reset(DMA_Channel_T *channel)
  *
  * @note      DMA2 Channel only for APM32 High density devices.
  */
-void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
+void DMA_Config(DMA_Channel_T *channel, DMA_Config_T *dmaConfig)
 {
     channel->CHCFG_B.DIRCFG = dmaConfig->dir;
     channel->CHCFG_B.CIRMODE = dmaConfig->loopMode;
@@ -138,7 +138,7 @@ void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig)
  *
  * @retval    None
  */
-void DMA_ConfigStructInit( DMA_Config_T* dmaConfig)
+void DMA_ConfigStructInit(DMA_Config_T *dmaConfig)
 {
     dmaConfig->peripheralBaseAddr = 0;
     dmaConfig->memoryBaseAddr = 0;
@@ -312,22 +312,24 @@ void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt)
  */
 uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
 {
-    if((flag & 0x10000000) != RESET )
+    if ((flag & 0x10000000) != RESET)
     {
-        if((DMA2->INTSTS & flag ) != RESET )
+        if ((DMA2->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
     }
     else
     {
-        if((DMA1->INTSTS & flag ) != RESET )
+        if ((DMA1->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
@@ -395,10 +397,11 @@ uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag)
  */
 void DMA_ClearStatusFlag(uint32_t flag)
 {
-    if((flag & 0x10000000) != RESET)
+    if ((flag & 0x10000000) != RESET)
     {
         DMA2->INTFCLR = flag;
-    } else
+    }
+    else
     {
         DMA1->INTFCLR = flag;
     }
@@ -465,21 +468,24 @@ void DMA_ClearStatusFlag(uint32_t flag)
  */
 uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
 {
-    if((flag & 0x10000000) != RESET )
+    if ((flag & 0x10000000) != RESET)
     {
-        if((DMA2->INTSTS & flag ) != RESET )
+        if ((DMA2->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
-    } else
+    }
+    else
     {
-        if((DMA1->INTSTS & flag ) != RESET )
+        if ((DMA1->INTSTS & flag) != RESET)
         {
             return SET ;
-        } else
+        }
+        else
         {
             return RESET ;
         }
@@ -546,10 +552,11 @@ uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag)
  */
 void DMA_ClearIntFlag(uint32_t flag)
 {
-    if((flag & 0x10000000) != RESET)
+    if ((flag & 0x10000000) != RESET)
     {
         DMA2->INTFCLR = flag;
-    } else
+    }
+    else
     {
         DMA1->INTFCLR = flag;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_dmc.c

@@ -45,10 +45,10 @@
  *
  * @retval      None
  */
-void DMC_Config(DMC_Config_T * dmcConfig)
+void DMC_Config(DMC_Config_T *dmcConfig)
 {
     DMC->SW_B.MCSW = 1;
-    while(!DMC->CTRL1_B.INIT);
+    while (!DMC->CTRL1_B.INIT);
 
     DMC->CFG_B.BAWCFG = dmcConfig->bankWidth;
     DMC->CFG_B.RAWCFG = dmcConfig->rowWidth;
@@ -60,7 +60,7 @@ void DMC_Config(DMC_Config_T * dmcConfig)
     DMC_ConfigTiming(&dmcConfig->timing);
 
     DMC->CTRL1_B.MODESET = 1;
-    while(!DMC->CTRL1_B.MODESET);
+    while (!DMC->CTRL1_B.MODESET);
 
     DMC->CTRL2_B.RDDEN = 1;
     DMC->CTRL2_B.RDDCFG = 7;
@@ -73,7 +73,7 @@ void DMC_Config(DMC_Config_T * dmcConfig)
  *
  * @retval      None
  */
-void DMC_ConfigStructInit(DMC_Config_T * dmcConfig)
+void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
 {
     dmcConfig->bankWidth   = DMC_BANK_WIDTH_2;
     dmcConfig->clkPhase    = DMC_CLK_PHASE_REVERSE;
@@ -91,7 +91,7 @@ void DMC_ConfigStructInit(DMC_Config_T * dmcConfig)
  *
  * @retval      None
  */
-void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig)
+void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
 {
     DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
     DMC->TIM0_B.DTIMSEL    = timingConfig->tRCD;
@@ -116,7 +116,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T * timingConfig)
  *
  * @retval      None
  */
-void DMC_ConfigTimingStructInit(DMC_TimingConfig_T * timingConfig)
+void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig)
 {
     timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
     timingConfig->tARP = DMC_AUTO_REFRESH_10;

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_eint.c

@@ -60,12 +60,12 @@ void EINT_Reset(void)
  *
  * @retval       None
  */
-void EINT_Config(EINT_Config_T* eintConfig)
+void EINT_Config(EINT_Config_T *eintConfig)
 {
     uint32_t temp = 0;
     temp = (uint32_t)EINT_BASE;
 
-    if(eintConfig->lineCmd != DISABLE)
+    if (eintConfig->lineCmd != DISABLE)
     {
         EINT->IMASK &= ~eintConfig->line;
         EINT->EMASK &= ~eintConfig->line;
@@ -104,7 +104,7 @@ void EINT_Config(EINT_Config_T* eintConfig)
  *
  * @retval       None
  */
-void EINT_ConfigStructInit(EINT_Config_T* eintConfig)
+void EINT_ConfigStructInit(EINT_Config_T *eintConfig)
 {
     eintConfig->line = EINT_LINENONE;
     eintConfig->mode = EINT_MODE_INTERRUPT;
@@ -137,7 +137,7 @@ uint8_t EINT_ReadStatusFlag(EINT_LINE_T line)
 {
     uint8_t status = RESET;
 
-    if((EINT->IPEND & line) != (uint32_t)RESET)
+    if ((EINT->IPEND & line) != (uint32_t)RESET)
     {
         status = SET;
     }
@@ -176,7 +176,7 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line)
 
     enablestatus = EINT->IMASK & line;
 
-    if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
     {
         status = SET;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_emmc.c

@@ -53,7 +53,7 @@
 void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
 {
     /** EMMC_BANK1_NORSRAM_1 */
-    if(bank == EMMC_BANK1_NORSRAM_1)
+    if (bank == EMMC_BANK1_NORSRAM_1)
     {
         EMMC_Bank1->SNCTRL_T[bank] = 0x000030DB;
     }
@@ -78,7 +78,7 @@ void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank)
  */
 void EMMC_ResetNAND(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         /** Set the EMMC_Bank2 registers to their reset values */
         EMMC_Bank2->CTRL2 = 0x00000018;
@@ -121,7 +121,7 @@ void EMMC_ResetPCCard(void)
  *
  * @retval    None
  */
-void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
+void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
 {
     /** Bank1 NOR/SRAM control register configuration */
     EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] =
@@ -138,7 +138,7 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
         emmcNORSRAMConfig->extendedMode |
         emmcNORSRAMConfig->writeBurst;
 
-    if(emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
+    if (emmcNORSRAMConfig->memoryType == EMMC_MEMORY_TYPE_NOR)
     {
         EMMC_Bank1->SNCTRL_T[emmcNORSRAMConfig->bank] |= 0x00000040;
     }
@@ -154,7 +154,7 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
         emmcNORSRAMConfig->readWriteTimingStruct->accessMode;
 
     /** Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
-    if(emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
+    if (emmcNORSRAMConfig->extendedMode == EMMC_EXTENDEN_MODE_ENABLE)
     {
         EMMC_Bank1E->WRTTIM[emmcNORSRAMConfig->bank] =
             (uint32_t)emmcNORSRAMConfig->writeTimingStruct->addressSetupTime |
@@ -177,7 +177,7 @@ void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
+void EMMC_ConfigNAND(EMMC_NANDConfig_T *emmcNANDConfig)
 {
     uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
 
@@ -201,7 +201,7 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
               (emmcNANDConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
               (emmcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
 
-    if(emmcNANDConfig->bank == EMMC_BANK2_NAND)
+    if (emmcNANDConfig->bank == EMMC_BANK2_NAND)
     {
         /** EMMC_BANK2_NAND registers configuration */
         EMMC_Bank2->CTRL2 = tmppcr;
@@ -225,30 +225,30 @@ void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig)
+void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T *emmcPCCardConfig)
 {
     /** Set the PCR4 register value according to EMMC_PCCARDInitStruct parameters */
     EMMC_Bank4->CTRL4 = (uint32_t)emmcPCCardConfig->waitFeature | EMMC_MEMORY_DATA_WIDTH_16BIT |
-                          (emmcPCCardConfig->TCLRSetupTime << 9) |
-                          (emmcPCCardConfig->TARSetupTime << 13);
+                        (emmcPCCardConfig->TCLRSetupTime << 9) |
+                        (emmcPCCardConfig->TARSetupTime << 13);
 
     /** Set PMEM4 register value according to EMMC_CommonSpaceTimingStructure parameters */
     EMMC_Bank4->CMSTIM4 = (uint32_t)emmcPCCardConfig->commonSpaceTimingStruct->setupTime |
-                        (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
-                        (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
-                        (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
+                          (emmcPCCardConfig->commonSpaceTimingStruct->waitSetupTime << 8) |
+                          (emmcPCCardConfig->commonSpaceTimingStruct->holdSetupTime << 16) |
+                          (emmcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime << 24);
 
     /** Set PATT4 register value according to EMMC_AttributeSpaceTimingStructure parameters */
     EMMC_Bank4->AMSTIM4 = (uint32_t)emmcPCCardConfig->attributeSpaceTimingStruct->setupTime |
-                        (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
-                        (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
-                        (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
+                          (emmcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime << 8) |
+                          (emmcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime << 16) |
+                          (emmcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime << 24);
 
     /** Set PIO4 register value according to EMMC_IOSpaceTimingStructure parameters */
     EMMC_Bank4->IOSTIM4 = (uint32_t)emmcPCCardConfig->IOSpaceTimingStruct->setupTime |
-                        (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
-                        (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
-                        (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
+                          (emmcPCCardConfig->IOSpaceTimingStruct->waitSetupTime << 8) |
+                          (emmcPCCardConfig->IOSpaceTimingStruct->holdSetupTime << 16) |
+                          (emmcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime << 24);
 }
 
 /*!
@@ -258,7 +258,7 @@ void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
+void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T *emmcNORSRAMConfig)
 {
     /** Reset NOR/SRAM Init structure parameters values */
     emmcNORSRAMConfig->bank = EMMC_BANK1_NORSRAM_1;
@@ -298,7 +298,7 @@ void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig)
+void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T *emmcNANDConfig)
 {
     /** Reset NAND Init structure parameters values */
     emmcNANDConfig->bank = EMMC_BANK2_NAND;
@@ -325,7 +325,7 @@ void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig)
  *
  * @retval    None
  */
-void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig)
+void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T *emmcPCCardConfig)
 {
     /** Reset PCCARD Init structure parameters values */
     emmcPCCardConfig->waitFeature = EMMC_WAIT_FEATURE_DISABLE;
@@ -391,7 +391,7 @@ void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank)
  */
 void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2_B.MBKEN = BIT_SET;
     }
@@ -413,7 +413,7 @@ void EMMC_EnableNAND(EMMC_BANK_NAND_T bank)
  */
 void EMMC_DisableNAND(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2_B.MBKEN = BIT_RESET;
     }
@@ -459,7 +459,7 @@ void EMMC_DisablePCCARD(void)
  */
 void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2 |= 0x00000040;
     }
@@ -482,7 +482,7 @@ void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank)
  */
 void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->CTRL2 &= 0x000FFFBF;
     }
@@ -506,7 +506,7 @@ uint32_t  EMMC_ReadECC(EMMC_BANK_NAND_T bank)
 {
     uint32_t eccval = 0x00000000;
 
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         eccval = EMMC_Bank2->ECCRS2;
     }
@@ -536,11 +536,11 @@ uint32_t  EMMC_ReadECC(EMMC_BANK_NAND_T bank)
  */
 void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 |= interrupt;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 |= interrupt;
     }
@@ -569,11 +569,11 @@ void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
  */
 void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 &= ~interrupt;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 &= ~interrupt;
     }
@@ -606,11 +606,11 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
 {
     uint32_t tmpsr = 0x00000000;
 
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         tmpsr = EMMC_Bank2->STSINT2;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         tmpsr = EMMC_Bank3->STSINT3;
     }
@@ -619,7 +619,7 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
         tmpsr = EMMC_Bank4->STSINT4;
     }
     /** Get the flag status */
-    if((tmpsr & flag) != RESET)
+    if ((tmpsr & flag) != RESET)
     {
         return SET;
     }
@@ -648,11 +648,11 @@ uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag)
  */
 void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 &= ~flag;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 &= ~flag;
     }
@@ -683,11 +683,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
 {
     uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
 
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         tmpsr = EMMC_Bank2->STSINT2;
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         tmpsr = EMMC_Bank3->STSINT3;
     }
@@ -699,7 +699,7 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
     itstatus = tmpsr & flag;
     itenable = tmpsr & (flag >> 3);
 
-    if((itstatus != RESET) && (itenable != RESET))
+    if ((itstatus != RESET) && (itenable != RESET))
     {
         return SET;
     }
@@ -728,11 +728,11 @@ uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag)
  */
 void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag)
 {
-    if(bank == EMMC_BANK2_NAND)
+    if (bank == EMMC_BANK2_NAND)
     {
         EMMC_Bank2->STSINT2 &= ~(flag >> 3);
     }
-    else if(bank == EMMC_BANK3_NAND)
+    else if (bank == EMMC_BANK3_NAND)
     {
         EMMC_Bank3->STSINT3 &= ~(flag >> 3);
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_fmc.c

@@ -140,7 +140,7 @@ FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr)
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
     status = FMC_WaitForLastOperation(0x000B0000);
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PAGEERA = BIT_SET;
         FMC->ADDR = pageAddr;
@@ -168,7 +168,7 @@ FMC_STATUS_T FMC_EraseAllPage(void)
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
     status = FMC_WaitForLastOperation(0x000B0000);
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.MASSERA = BIT_SET;
         FMC->CTRL2_B.STA = BIT_SET;
@@ -195,12 +195,12 @@ FMC_STATUS_T FMC_EraseOptionBytes(void)
     uint16_t rdtemp = 0x00A5;
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
-    if(FMC_GetReadProtectionStatus() != RESET)
+    if (FMC_GetReadProtectionStatus() != RESET)
     {
         rdtemp = 0x00;
     }
     status = FMC_WaitForLastOperation(0x000B0000);
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -210,18 +210,18 @@ FMC_STATUS_T FMC_EraseOptionBytes(void)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
             OB->RDP = rdtemp;
             status = FMC_WaitForLastOperation(0x000B0000);
-            if(status != FMC_STATUS_TIMEOUT)
+            if (status != FMC_STATUS_TIMEOUT)
             {
                 FMC->CTRL2_B.OBP = BIT_RESET;
             }
         }
-        else if(status != FMC_STATUS_TIMEOUT)
+        else if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -247,13 +247,13 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
     __IOM uint32_t temp = 0;
 
-    #ifdef APM32F10X_HD
-          __set_PRIMASK(1);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(1);
+#endif
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PG = BIT_SET;
 
@@ -261,11 +261,11 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             temp = address + 2;
 
-            *(__IOM uint16_t*) temp = data >> 16;
+            *(__IOM uint16_t *) temp = data >> 16;
 
             status = FMC_WaitForLastOperation(0x000B0000);
             FMC->CTRL2_B.PG = BIT_RESET;
@@ -276,9 +276,9 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
         }
     }
 
-    #ifdef APM32F10X_HD
-        __set_PRIMASK(0);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(0);
+#endif
 
     return status;
 }
@@ -300,13 +300,13 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
-    #ifdef APM32F10X_HD
-        __set_PRIMASK(1);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(1);
+#endif
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.PG = BIT_SET;
         *(__IOM uint16_t *)address = data;
@@ -314,9 +314,9 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
         FMC->CTRL2_B.PG = BIT_RESET;
     }
 
-    #ifdef APM32F10X_HD
-        __set_PRIMASK(0);
-    #endif
+#ifdef APM32F10X_HD
+    __set_PRIMASK(0);
+#endif
 
     return status;
 }
@@ -340,7 +340,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -348,7 +348,7 @@ FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data)
         FMC->CTRL2_B.OBP = BIT_SET;
         *(__IOM uint16_t *)address = data;
         status = FMC_WaitForLastOperation(0x000B0000);
-        if(status == FMC_STATUS_TIMEOUT)
+        if (status == FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -388,34 +388,34 @@ FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
         FMC->CTRL2_B.OBP = BIT_SET;
 
-        if(WPP0_Data != 0xFF)
+        if (WPP0_Data != 0xFF)
         {
             OB->WRP0 = WPP0_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
-        if((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
+        if ((status == FMC_STATUS_COMPLETE) && (WPP1_Data != 0xFF))
         {
             OB->WRP1 = WPP1_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
-        if((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
+        if ((status == FMC_STATUS_COMPLETE) && (WPP2_Data != 0xFF))
         {
             OB->WRP2 = WPP2_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
-        if((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
+        if ((status == FMC_STATUS_COMPLETE) && (WPP3_Data != 0xFF))
         {
             OB->WRP3 = WPP3_Data;
             status = FMC_WaitForLastOperation(0x000B0000);
         }
 
-        if(status != FMC_STATUS_TIMEOUT)
+        if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -440,7 +440,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -450,7 +450,7 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
@@ -458,12 +458,12 @@ FMC_STATUS_T FMC_EnableReadOutProtection(void)
 
             status = FMC_WaitForLastOperation(0x000B0000);
 
-            if(status != FMC_STATUS_TIMEOUT)
+            if (status != FMC_STATUS_TIMEOUT)
             {
                 FMC->CTRL2_B.OBP = BIT_RESET;
             }
         }
-        else if(status != FMC_STATUS_TIMEOUT)
+        else if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
         }
@@ -488,7 +488,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->OBKEY = 0x45670123;
         FMC->OBKEY = 0xCDEF89AB;
@@ -497,7 +497,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
 
         status = FMC_WaitForLastOperation(0x000B0000);
 
-        if(status == FMC_STATUS_COMPLETE)
+        if (status == FMC_STATUS_COMPLETE)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
             FMC->CTRL2_B.OBP = BIT_SET;
@@ -505,12 +505,12 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
 
             status = FMC_WaitForLastOperation(0x000B0000);
 
-            if(status != FMC_STATUS_TIMEOUT)
+            if (status != FMC_STATUS_TIMEOUT)
             {
                 FMC->CTRL2_B.OBP = BIT_RESET;
             }
         }
-        else if(status != FMC_STATUS_TIMEOUT)
+        else if (status != FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBE = BIT_RESET;
         }
@@ -529,7 +529,7 @@ FMC_STATUS_T FMC_DisableReadOutProtection(void)
  *                 @arg FMC_STATUS_COMPLETE
  *                 @arg FMC_STATUS_TIMEOUT
  */
-FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
+FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T *userConfig)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
@@ -538,14 +538,14 @@ FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig)
 
     status = FMC_WaitForLastOperation(0x000B0000);
 
-    if(status == FMC_STATUS_COMPLETE)
+    if (status == FMC_STATUS_COMPLETE)
     {
         FMC->CTRL2_B.OBP = BIT_SET;
         OB->USER = (uint32_t)userConfig->iwdtSet | \
                    (uint32_t)userConfig->stopSet | \
                    (uint32_t)userConfig->stdbySet | 0xF8;
         status = FMC_WaitForLastOperation(0x000B0000);
-        if(status == FMC_STATUS_TIMEOUT)
+        if (status == FMC_STATUS_TIMEOUT)
         {
             FMC->CTRL2_B.OBP = BIT_RESET;
         }
@@ -588,7 +588,7 @@ uint8_t FMC_GetReadProtectionStatus(void)
 {
     uint8_t flagstatus = RESET;
 
-    if(FMC->OBCS_B.READPROT != RESET)
+    if (FMC->OBCS_B.READPROT != RESET)
     {
         flagstatus = SET;
     }
@@ -623,7 +623,7 @@ uint8_t FMC_ReadPrefetchBufferStatus(void)
  */
 void FMC_EnableInterrupt(FMC_INT_T interrupt)
 {
-    if(interrupt == FMC_INT_ERR)
+    if (interrupt == FMC_INT_ERR)
     {
         FMC->CTRL2_B.ERRIE = ENABLE;
     }
@@ -645,7 +645,7 @@ void FMC_EnableInterrupt(FMC_INT_T interrupt)
  */
 void FMC_DisableInterrupt(FMC_INT_T interrupt)
 {
-    if(interrupt == FMC_INT_ERR)
+    if (interrupt == FMC_INT_ERR)
     {
         FMC->CTRL2_B.ERRIE = DISABLE;
     }
@@ -670,11 +670,11 @@ void FMC_DisableInterrupt(FMC_INT_T interrupt)
  */
 uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag)
 {
-    if(flag == FMC_FLAG_OBE)
+    if (flag == FMC_FLAG_OBE)
     {
         return FMC->OBCS_B.OBE;
     }
-    else if((FMC->STS & flag ) != RESET)
+    else if ((FMC->STS & flag) != RESET)
     {
         return SET;
     }
@@ -713,15 +713,15 @@ FMC_STATUS_T  FMC_ReadStatus(void)
 {
     FMC_STATUS_T status = FMC_STATUS_COMPLETE;
 
-    if(FMC->STS_B.BUSYF == BIT_SET)
+    if (FMC->STS_B.BUSYF == BIT_SET)
     {
         status = FMC_STATUS_BUSY;
     }
-    else if(FMC->STS_B.PEF == BIT_SET)
+    else if (FMC->STS_B.PEF == BIT_SET)
     {
         status = FMC_STATUS_ERROR_PG;
     }
-    else if(FMC->STS_B.WPEF == BIT_SET)
+    else if (FMC->STS_B.WPEF == BIT_SET)
     {
         status = FMC_STATUS_ERROR_WRP;
     }
@@ -751,12 +751,12 @@ FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut)
     status = FMC_ReadStatus();
 
     /** Wait for a Flash operation to complete or a TIMEOUT to occur */
-    while((status == FMC_STATUS_BUSY) && (timeOut !=0))
+    while ((status == FMC_STATUS_BUSY) && (timeOut != 0))
     {
         status = FMC_ReadStatus();
         timeOut--;
     }
-    if(timeOut == 0x00)
+    if (timeOut == 0x00)
     {
         status = FMC_STATUS_TIMEOUT;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_gpio.c

@@ -46,7 +46,7 @@
  *
  * @retval    None
  */
-void GPIO_Reset(GPIO_T* port)
+void GPIO_Reset(GPIO_T *port)
 {
     RCM_APB2_PERIPH_T APB2Periph;
 
@@ -106,7 +106,7 @@ void GPIO_AFIOReset(void)
  *
  * @retval    None
  */
-void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
+void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
 {
     uint8_t i;
     uint32_t mode;
@@ -181,7 +181,7 @@ void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
  *
  * @retval    None
  */
-void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
+void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
 {
     gpioConfig->pin  = GPIO_PIN_ALL;
     gpioConfig->speed = GPIO_SPEED_20MHz;
@@ -199,7 +199,7 @@ void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
  *
  * @retval    The input port pin value
  */
-uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
+uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
 {
     uint8_t ret;
 
@@ -216,7 +216,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    GPIO input data port value
  */
-uint16_t GPIO_ReadInputPort(GPIO_T* port)
+uint16_t GPIO_ReadInputPort(GPIO_T *port)
 {
     return ((uint16_t)port->IDATA);
 }
@@ -232,7 +232,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T* port)
  *
  * @retval    The output port pin value
  */
-uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
+uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
 {
 
     uint8_t ret;
@@ -250,7 +250,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    output data port value
  */
-uint16_t GPIO_ReadOutputPort(GPIO_T* port)
+uint16_t GPIO_ReadOutputPort(GPIO_T *port)
 {
     return ((uint16_t)port->ODATA);
 }
@@ -266,7 +266,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T* port)
  *
  * @retval    None
  */
-void GPIO_SetBit(GPIO_T* port, uint16_t pin)
+void GPIO_SetBit(GPIO_T *port, uint16_t pin)
 {
     port->BSC = (uint32_t)pin;
 }
@@ -282,7 +282,7 @@ void GPIO_SetBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
+void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
 {
     port->BC = (uint32_t)pin;
 }
@@ -304,7 +304,7 @@ void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
+void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
 {
     if (bitVal != BIT_RESET)
     {
@@ -326,7 +326,7 @@ void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
  *
  * @retval    None
  */
-void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
+void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
 {
     port->ODATA = (uint32_t)portValue;
 }
@@ -342,7 +342,7 @@ void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
  *
  * @retval    None
  */
-void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
+void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin)
 {
     uint32_t val = 0x00010000;
 
@@ -471,7 +471,7 @@ void GPIO_ConfigPinRemap(GPIO_REMAP_T remap)
         regVal = AFIO->REMAP1;
     }
 
-    if(remap >> 8 == 0x18)
+    if (remap >> 8 == 0x18)
     {
         regVal &= 0xF0FFFFFF;
         AFIO->REMAP1 &= 0xF0FFFFFF;
@@ -514,28 +514,28 @@ void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSou
     if (pinSource <= GPIO_PIN_SOURCE_3)
     {
         shift = pinSource << 2;
-        AFIO->EINTSEL1 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL1 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL1 |=  portSource << shift;
     }
 
     else if (pinSource <= GPIO_PIN_SOURCE_7)
     {
         shift = (pinSource - GPIO_PIN_SOURCE_4) << 2;
-        AFIO->EINTSEL2 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL2 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL2 |=  portSource << shift;
     }
 
     else if (pinSource <= GPIO_PIN_SOURCE_11)
     {
         shift = (pinSource - GPIO_PIN_SOURCE_8) << 2;
-        AFIO->EINTSEL3 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL3 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL3 |=  portSource << shift;
     }
 
     else if (pinSource <= GPIO_PIN_SOURCE_15)
     {
         shift = (pinSource - GPIO_PIN_SOURCE_12) << 2;
-        AFIO->EINTSEL4 &= (uint32_t )~(0x0f << shift);
+        AFIO->EINTSEL4 &= (uint32_t)~(0x0f << shift);
         AFIO->EINTSEL4 |=  portSource << shift;
     }
 }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_i2c.c

@@ -45,9 +45,9 @@
  *
  * @retval    None
  */
-void I2C_Reset(I2C_T* i2c)
+void I2C_Reset(I2C_T *i2c)
 {
-    if(i2c == I2C1)
+    if (i2c == I2C1)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
@@ -68,7 +68,7 @@ void I2C_Reset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
+void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
 {
     uint16_t tmpreg = 0, freqrange = 0;
     uint32_t PCLK1 = 8000000, PCLK2 = 0;
@@ -79,15 +79,15 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
     /** I2C CTRL2 Configuration */
     RCM_ReadPCLKFreq(&PCLK1, &PCLK2);
     freqrange = PCLK1 / 1000000;
-    i2c->CTRL2_B.CLKFCFG= freqrange;
+    i2c->CTRL2_B.CLKFCFG = freqrange;
 
     /** I2C CLKCTRL Configuration */
     i2c->CTRL1_B.I2CEN = BIT_RESET;
 
-    if(i2cConfig->clockSpeed <= 100000)
+    if (i2cConfig->clockSpeed <= 100000)
     {
         result = (PCLK1 / (i2cConfig->clockSpeed << 1));
-        if(result < 0x04)
+        if (result < 0x04)
         {
             result = 0x04;
         }
@@ -97,7 +97,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
     /** Configure speed in fast mode */
     else
     {
-        if(i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
+        if (i2cConfig->dutyCycle == I2C_DUTYCYCLE_2)
         {
             result = (PCLK1 / (i2cConfig->clockSpeed * 3));
         }
@@ -107,7 +107,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
             result |= I2C_DUTYCYCLE_16_9;
         }
 
-        if((result & 0x0FFF) == 0)
+        if ((result & 0x0FFF) == 0)
         {
             result |= 0x0001;
         }
@@ -136,7 +136,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
  *
  * @retval    None
  */
-void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
+void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
 {
     i2cConfig->clockSpeed = 5000;
     i2cConfig->mode = I2C_MODE_I2C;
@@ -153,7 +153,7 @@ void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
  *
  * @retval    None
  */
-void I2C_Enable(I2C_T* i2c)
+void I2C_Enable(I2C_T *i2c)
 {
     i2c->CTRL1_B.I2CEN = ENABLE;
 }
@@ -165,7 +165,7 @@ void I2C_Enable(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Disable(I2C_T* i2c)
+void I2C_Disable(I2C_T *i2c)
 {
     i2c->CTRL1_B.I2CEN = DISABLE;
 }
@@ -177,7 +177,7 @@ void I2C_Disable(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStart(I2C_T* i2c)
+void I2C_EnableGenerateStart(I2C_T *i2c)
 {
     i2c->CTRL1_B.START = BIT_SET;
 }
@@ -189,7 +189,7 @@ void I2C_EnableGenerateStart(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStart(I2C_T* i2c)
+void I2C_DisableGenerateStart(I2C_T *i2c)
 {
     i2c->CTRL1_B.START = BIT_RESET;
 }
@@ -201,7 +201,7 @@ void I2C_DisableGenerateStart(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStop(I2C_T* i2c)
+void I2C_EnableGenerateStop(I2C_T *i2c)
 {
     i2c->CTRL1_B.STOP = BIT_SET;
 }
@@ -213,7 +213,7 @@ void I2C_EnableGenerateStop(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStop(I2C_T* i2c)
+void I2C_DisableGenerateStop(I2C_T *i2c)
 {
     i2c->CTRL1_B.STOP = BIT_RESET;
 }
@@ -225,7 +225,7 @@ void I2C_DisableGenerateStop(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableAcknowledge(I2C_T* i2c)
+void I2C_EnableAcknowledge(I2C_T *i2c)
 {
     i2c->CTRL1_B.ACKEN = ENABLE;
 }
@@ -237,7 +237,7 @@ void I2C_EnableAcknowledge(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableAcknowledge(I2C_T* i2c)
+void I2C_DisableAcknowledge(I2C_T *i2c)
 {
     i2c->CTRL1_B.ACKEN = DISABLE;
 }
@@ -251,7 +251,7 @@ void I2C_DisableAcknowledge(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
+void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
 {
     i2c->SADDR2_B.ADDR2 = address;
 }
@@ -263,7 +263,7 @@ void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
  *
  * @retval    None
  */
-void I2C_EnableDualAddress(I2C_T* i2c)
+void I2C_EnableDualAddress(I2C_T *i2c)
 {
     i2c->SADDR2_B.ADDRNUM = ENABLE;
 }
@@ -275,7 +275,7 @@ void I2C_EnableDualAddress(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDualAddress(I2C_T* i2c)
+void I2C_DisableDualAddress(I2C_T *i2c)
 {
     i2c->SADDR2_B.ADDRNUM = DISABLE;
 }
@@ -287,7 +287,7 @@ void I2C_DisableDualAddress(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGeneralCall(I2C_T* i2c)
+void I2C_EnableGeneralCall(I2C_T *i2c)
 {
     i2c->CTRL1_B.SRBEN = ENABLE;
 }
@@ -299,7 +299,7 @@ void I2C_EnableGeneralCall(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGeneralCall(I2C_T* i2c)
+void I2C_DisableGeneralCall(I2C_T *i2c)
 {
     i2c->CTRL1_B.SRBEN = DISABLE;
 }
@@ -313,7 +313,7 @@ void I2C_DisableGeneralCall(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_TxData(I2C_T* i2c, uint8_t data)
+void I2C_TxData(I2C_T *i2c, uint8_t data)
 {
     i2c->DATA_B.DATA = data;
 }
@@ -325,7 +325,7 @@ void I2C_TxData(I2C_T* i2c, uint8_t data)
  *
  * @retval    received data
  */
-uint8_t I2C_RxData(I2C_T* i2c)
+uint8_t I2C_RxData(I2C_T *i2c)
 {
     return i2c->DATA_B.DATA;
 }
@@ -343,9 +343,9 @@ uint8_t I2C_RxData(I2C_T* i2c)
  *              @arg I2C_DIRECTION_RX: Receiver mode
  * @retval    None
  */
-void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
+void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
 {
-    if(direction != I2C_DIRECTION_TX)
+    if (direction != I2C_DIRECTION_TX)
     {
         i2c->DATA_B.DATA = address | 0x0001;
     }
@@ -375,7 +375,7 @@ void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
  *
  * @retval    The value of the read register
  */
-uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
+uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
 {
     switch (i2cRegister)
     {
@@ -411,7 +411,7 @@ uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
  *
  * @retval    None
  */
-void I2C_EnableSoftwareReset(I2C_T* i2c)
+void I2C_EnableSoftwareReset(I2C_T *i2c)
 {
     i2c->CTRL1_B.SWRST = ENABLE;
 }
@@ -423,7 +423,7 @@ void I2C_EnableSoftwareReset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableSoftwareReset(I2C_T* i2c)
+void I2C_DisableSoftwareReset(I2C_T *i2c)
 {
     i2c->CTRL1_B.SWRST = DISABLE;
 }
@@ -437,9 +437,9 @@ void I2C_DisableSoftwareReset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
+void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
 {
-    if(NACKPosition == I2C_NACK_POSITION_NEXT)
+    if (NACKPosition == I2C_NACK_POSITION_NEXT)
     {
         i2c->CTRL1_B.ACKPOS = BIT_SET;
     }
@@ -460,9 +460,9 @@ void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
  *              @arg I2C_SMBUSALER_HIGH: SMBus Alert pin high
  * @retval    None
  */
-void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
+void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
 {
-    if(SMBusState == I2C_SMBUSALER_LOW)
+    if (SMBusState == I2C_SMBUSALER_LOW)
     {
         i2c->CTRL1_B.ALERTEN = BIT_SET;
     }
@@ -479,7 +479,7 @@ void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
  *
  * @retval    None
  */
-void I2C_EnablePECTransmit(I2C_T* i2c)
+void I2C_EnablePECTransmit(I2C_T *i2c)
 {
     i2c->CTRL1_B.PEC = BIT_SET;
 }
@@ -491,7 +491,7 @@ void I2C_EnablePECTransmit(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisablePECTransmit(I2C_T* i2c)
+void I2C_DisablePECTransmit(I2C_T *i2c)
 {
     i2c->CTRL1_B.PEC = BIT_RESET;
 }
@@ -507,9 +507,9 @@ void I2C_DisablePECTransmit(I2C_T* i2c)
  *              @arg I2C_PEC_POSITION_CURRENT: indicates that current byte is PEC
  * @retval    None
  */
-void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
+void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
 {
-    if(PECPosition == I2C_PEC_POSITION_NEXT)
+    if (PECPosition == I2C_PEC_POSITION_NEXT)
     {
         i2c->CTRL1_B.ACKPOS = BIT_SET;
     }
@@ -526,7 +526,7 @@ void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
  *
  * @retval    None
  */
-void I2C_EnablePEC(I2C_T* i2c)
+void I2C_EnablePEC(I2C_T *i2c)
 {
     i2c->CTRL1_B.PECEN = BIT_SET;
 }
@@ -538,7 +538,7 @@ void I2C_EnablePEC(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisablePEC(I2C_T* i2c)
+void I2C_DisablePEC(I2C_T *i2c)
 {
     i2c->CTRL1_B.PECEN = BIT_RESET;
 }
@@ -550,7 +550,7 @@ void I2C_DisablePEC(I2C_T* i2c)
  *
  * @retval    value of PEC
  */
-uint8_t I2C_ReadPEC(I2C_T* i2c)
+uint8_t I2C_ReadPEC(I2C_T *i2c)
 {
     return i2c->STS2_B.PECVALUE;
 }
@@ -562,7 +562,7 @@ uint8_t I2C_ReadPEC(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableARP(I2C_T* i2c)
+void I2C_EnableARP(I2C_T *i2c)
 {
     i2c->CTRL1_B.ARPEN = BIT_SET;
 }
@@ -574,7 +574,7 @@ void I2C_EnableARP(I2C_T* i2c)
 *
 * @retval     None
 */
-void I2C_DisableARP(I2C_T* i2c)
+void I2C_DisableARP(I2C_T *i2c)
 {
     i2c->CTRL1_B.ARPEN = BIT_RESET;
 }
@@ -586,7 +586,7 @@ void I2C_DisableARP(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableStretchClock(I2C_T* i2c)
+void I2C_EnableStretchClock(I2C_T *i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = BIT_RESET;
 }
@@ -598,7 +598,7 @@ void I2C_EnableStretchClock(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableStretchClock(I2C_T* i2c)
+void I2C_DisableStretchClock(I2C_T *i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = BIT_SET;
 }
@@ -614,9 +614,9 @@ void I2C_DisableStretchClock(I2C_T* i2c)
  *              @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
  * @retval    None
  */
-void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
+void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
 {
-    if(dutyCycle == I2C_DUTYCYCLE_16_9)
+    if (dutyCycle == I2C_DUTYCYCLE_16_9)
     {
         i2c->CLKCTRL_B.FDUTYCFG = BIT_SET;
     }
@@ -633,7 +633,7 @@ void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
  *
  * @retval    None
  */
-void I2C_EnableDMA(I2C_T* i2c)
+void I2C_EnableDMA(I2C_T *i2c)
 {
     i2c->CTRL2_B.DMAEN = ENABLE;
 }
@@ -645,7 +645,7 @@ void I2C_EnableDMA(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMA(I2C_T* i2c)
+void I2C_DisableDMA(I2C_T *i2c)
 {
     i2c->CTRL2_B.DMAEN = DISABLE;
 }
@@ -657,7 +657,7 @@ void I2C_DisableDMA(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableDMALastTransfer(I2C_T* i2c)
+void I2C_EnableDMALastTransfer(I2C_T *i2c)
 {
     i2c->CTRL2_B.LTCFG = BIT_SET;
 }
@@ -669,7 +669,7 @@ void I2C_EnableDMALastTransfer(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMALastTransfer(I2C_T* i2c)
+void I2C_DisableDMALastTransfer(I2C_T *i2c)
 {
     i2c->CTRL2_B.LTCFG = BIT_RESET;
 }
@@ -687,7 +687,7 @@ void I2C_DisableDMALastTransfer(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
+void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
 {
     i2c->CTRL2 |= interrupt;
 }
@@ -705,7 +705,7 @@ void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
  *
  * @retval    None
  */
-void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
+void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
 {
     i2c->CTRL2 &= ~interrupt;
 }
@@ -736,7 +736,7 @@ void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
  *
  * @retval    Status: SUCCESS or ERROR
  */
-uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
+uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -747,7 +747,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
 
     lastevent = (flag1 | flag2) & 0x00FFFFFF;
 
-    if((lastevent & i2cEvent) == i2cEvent)
+    if ((lastevent & i2cEvent) == i2cEvent)
     {
         return SUCCESS;
     }
@@ -761,7 +761,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
  *
  * @retval    The last event
  */
-uint32_t I2C_ReadLastEvent(I2C_T* i2c)
+uint32_t I2C_ReadLastEvent(I2C_T *i2c)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -806,7 +806,7 @@ uint32_t I2C_ReadLastEvent(I2C_T* i2c)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
+uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
 {
 
     uint8_t status = 0;
@@ -914,7 +914,7 @@ uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadStatusFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
+void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
 {
     switch (flag)
     {
@@ -968,13 +968,13 @@ void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
+uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
 {
     uint32_t enablestatus = 0;
 
     enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2);
     flag &= 0x00FFFFFF;
-    if(((i2c->STS1 & flag) != RESET) && enablestatus)
+    if (((i2c->STS1 & flag) != RESET) && enablestatus)
     {
         return SET;
     }
@@ -1014,7 +1014,7 @@ uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadIntFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag)
+void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag)
 {
     i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF);
 }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_iwdt.c

@@ -132,7 +132,7 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag)
 {
     uint8_t bitStatus = RESET;
 
-    if((IWDT->STS & flag) != (uint32_t)RESET)
+    if ((IWDT->STS & flag) != (uint32_t)RESET)
     {
         bitStatus = SET;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_misc.c

@@ -62,7 +62,7 @@
  */
 void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
 {
-   SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
 }
 
 /*!
@@ -79,53 +79,53 @@ void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
  */
 void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t subPriority)
 {
-   uint32_t tempPriority, tempPrePri, tempSubPri;
-   uint32_t priorityGrp;
-
-   /** Get priority group */
-   priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
-
-   /** get pre-emption priority and subpriority */
-   switch(priorityGrp)
-   {
-      case NVIC_PRIORITY_GROUP_0:
-         tempPrePri = 0;
-         tempSubPri = 4;
-         break;
-
-      case NVIC_PRIORITY_GROUP_1:
-         tempPrePri = 1;
-         tempSubPri = 3;
-         break;
-
-      case NVIC_PRIORITY_GROUP_2:
-         tempPrePri = 2;
-         tempSubPri = 2;
-         break;
-
-      case NVIC_PRIORITY_GROUP_3:
-         tempPrePri = 3;
-         tempSubPri = 1;
-         break;
-
-      case NVIC_PRIORITY_GROUP_4:
-         tempPrePri = 4;
-         tempSubPri = 0;
-         break;
-
-      default:
-         NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
-         tempPrePri = 0;
-         tempSubPri = 4;
-         break;
-   }
-
-   tempPrePri = 4 - tempPrePri;
-   tempSubPri = 4 - tempSubPri;
-   tempPriority = preemptionPriority << tempPrePri;
-   tempPriority |= subPriority & (0x0f >> tempSubPri);
-   tempPriority <<= 4;
-   NVIC->IP[irq] = (uint8_t)tempPriority;
+    uint32_t tempPriority, tempPrePri, tempSubPri;
+    uint32_t priorityGrp;
+
+    /** Get priority group */
+    priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
+
+    /** get pre-emption priority and subpriority */
+    switch (priorityGrp)
+    {
+    case NVIC_PRIORITY_GROUP_0:
+        tempPrePri = 0;
+        tempSubPri = 4;
+        break;
+
+    case NVIC_PRIORITY_GROUP_1:
+        tempPrePri = 1;
+        tempSubPri = 3;
+        break;
+
+    case NVIC_PRIORITY_GROUP_2:
+        tempPrePri = 2;
+        tempSubPri = 2;
+        break;
+
+    case NVIC_PRIORITY_GROUP_3:
+        tempPrePri = 3;
+        tempSubPri = 1;
+        break;
+
+    case NVIC_PRIORITY_GROUP_4:
+        tempPrePri = 4;
+        tempSubPri = 0;
+        break;
+
+    default:
+        NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
+        tempPrePri = 0;
+        tempSubPri = 4;
+        break;
+    }
+
+    tempPrePri = 4 - tempPrePri;
+    tempSubPri = 4 - tempSubPri;
+    tempPriority = preemptionPriority << tempPrePri;
+    tempPriority |= subPriority & (0x0f >> tempSubPri);
+    tempPriority <<= 4;
+    NVIC->IP[irq] = (uint8_t)tempPriority;
 
     /** enable the selected IRQ */
     NVIC->ISER[irq >> 0x05U] = (uint32_t)0x01U << (irq & (uint8_t)0x1FU);
@@ -174,7 +174,7 @@ void NVIC_ConfigVectorTable(NVIC_VECT_TAB_T vectTab, uint32_t offset)
  */
 void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
 {
-   SCB->SCR |= lowPowerMode;
+    SCB->SCR |= lowPowerMode;
 }
 
 /*!
@@ -190,7 +190,7 @@ void NVIC_SetSystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
  */
 void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
 {
-   SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
+    SCB->SCR &= (uint32_t)(~(uint32_t)lowPowerMode);
 }
 
 /*!
@@ -205,14 +205,14 @@ void NVIC_ResetystemLowPower(NVIC_LOWPOWER_T lowPowerMode)
  */
 void SysTick_ConfigCLKSource(SYSTICK_CLK_SOURCE_T clkSource)
 {
-   if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
-   {
-      SysTick->CTRL |= (uint32_t)BIT2;
-   }
-   else
-   {
-      SysTick->CTRL &= (uint32_t)(~BIT2);
-   }
+    if (clkSource == SYSTICK_CLK_SOURCE_HCLK)
+    {
+        SysTick->CTRL |= (uint32_t)BIT2;
+    }
+    else
+    {
+        SysTick->CTRL &= (uint32_t)(~BIT2);
+    }
 }
 
 /**@} end of group MISC_Fuctions*/

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_pmu.c

@@ -171,9 +171,9 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
     /** Set LPDSCFG bit according to regulator value */
     PMU->CTRL_B.LPDSCFG = regulator;
     /** Set Cortex System Control Register */
-    SCB->SCR |= (uint32_t )0x04;
+    SCB->SCR |= (uint32_t)0x04;
     /** Select STOP mode entry*/
-    if(entry == PMU_STOP_ENTRY_WFI)
+    if (entry == PMU_STOP_ENTRY_WFI)
     {
         /** Request Wait For Interrupt */
         __WFI();
@@ -202,7 +202,7 @@ void PMU_EnterSTANDBYMode(void)
     /** Select STANDBY mode */
     PMU->CTRL_B.PDDSCFG = BIT_SET;
     /** Set Cortex System Control Register */
-    SCB->SCR |= (uint32_t )0x04;
+    SCB->SCR |= (uint32_t)0x04;
 #if defined ( __CC_ARM   )
     __force_stores();
 #endif
@@ -226,15 +226,15 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
 {
     uint8_t BitStatus = BIT_RESET;
 
-    if(flag == PMU_FLAG_WUE)
+    if (flag == PMU_FLAG_WUE)
     {
         BitStatus = PMU->CSTS_B.WUEFLG;
     }
-    else if(flag == PMU_FLAG_SB)
+    else if (flag == PMU_FLAG_SB)
     {
         BitStatus = PMU->CSTS_B.SBFLG;
     }
-    else if(flag == PMU_FLAG_PVDO)
+    else if (flag == PMU_FLAG_PVDO)
     {
         BitStatus = PMU->CSTS_B.PVDOFLG;
     }
@@ -253,11 +253,11 @@ uint8_t PMU_ReadStatusFlag(PMU_FLAG_T flag)
  */
 void PMU_ClearStatusFlag(PMU_FLAG_T flag)
 {
-    if(flag == PMU_FLAG_WUE)
+    if (flag == PMU_FLAG_WUE)
     {
         PMU->CTRL_B.WUFLGCLR = BIT_SET;
     }
-    else if(flag == PMU_FLAG_SB)
+    else if (flag == PMU_FLAG_SB)
     {
         PMU->CTRL_B.SBFLGCLR = BIT_SET;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_qspi.c

@@ -73,7 +73,7 @@ void QSPI_Reset(void)
  *
  * @retval      None
  */
-void QSPI_Config(QSPI_Config_T * qspiConfig)
+void QSPI_Config(QSPI_Config_T *qspiConfig)
 {
     QSPI->CTRL1_B.CPHA = qspiConfig->clockPhase;
     QSPI->CTRL1_B.CPOL = qspiConfig->clockPolarity;
@@ -585,19 +585,19 @@ void QSPI_ClearIntFlag(uint32_t flag)
 {
     volatile uint32_t dummy = 0;
 
-    if(flag & QSPI_INT_FLAG_TFO)
+    if (flag & QSPI_INT_FLAG_TFO)
     {
         dummy = QSPI->TFOIC;
     }
-    else if(flag & QSPI_INT_FLAG_RFO)
+    else if (flag & QSPI_INT_FLAG_RFO)
     {
         dummy = QSPI->RFOIC;
     }
-    else if(flag & QSPI_INT_FLAG_RFU)
+    else if (flag & QSPI_INT_FLAG_RFU)
     {
         dummy = QSPI->RFUIC;
     }
-    else if(flag & QSPI_INT_FLAG_MST)
+    else if (flag & QSPI_INT_FLAG_MST)
     {
         dummy = QSPI->MIC;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rcm.c

@@ -490,43 +490,43 @@ uint32_t RCM_ReadSYSCLKFreq(void)
 
     switch (sysClock)
     {
-        /** sys clock is HSI */
-        case RCM_SYSCLK_SEL_HSI:
-            sysClock = HSI_VALUE;
-            break;
-
-        /** sys clock is HSE */
-        case RCM_SYSCLK_SEL_HSE:
-            sysClock = HSE_VALUE;
-            break;
-
-        /** sys clock is PLL */
-        case RCM_SYSCLK_SEL_PLL:
-            pllMull = RCM->CFG_B.PLLMULCFG + 2;
-            pllSource = RCM->CFG_B.PLLSRCSEL;
-
-            /** PLL entry clock source is HSE */
-            if (pllSource == BIT_SET)
-            {
-                sysClock = HSE_VALUE * pllMull;
+    /** sys clock is HSI */
+    case RCM_SYSCLK_SEL_HSI:
+        sysClock = HSI_VALUE;
+        break;
+
+    /** sys clock is HSE */
+    case RCM_SYSCLK_SEL_HSE:
+        sysClock = HSE_VALUE;
+        break;
+
+    /** sys clock is PLL */
+    case RCM_SYSCLK_SEL_PLL:
+        pllMull = RCM->CFG_B.PLLMULCFG + 2;
+        pllSource = RCM->CFG_B.PLLSRCSEL;
+
+        /** PLL entry clock source is HSE */
+        if (pllSource == BIT_SET)
+        {
+            sysClock = HSE_VALUE * pllMull;
 
-                /** HSE clock divided by 2 */
-                if (pllSource == RCM->CFG_B.PLLHSEPSC)
-                {
-                    sysClock >>= 1;
-                }
-            }
-            /** PLL entry clock source is HSI/2 */
-            else
+            /** HSE clock divided by 2 */
+            if (pllSource == RCM->CFG_B.PLLHSEPSC)
             {
-                sysClock = (HSI_VALUE >> 1) * pllMull;
+                sysClock >>= 1;
             }
+        }
+        /** PLL entry clock source is HSI/2 */
+        else
+        {
+            sysClock = (HSI_VALUE >> 1) * pllMull;
+        }
 
-            break;
+        break;
 
-        default:
-            sysClock  = HSI_VALUE;
-            break;
+    default:
+        sysClock  = HSI_VALUE;
+        break;
     }
 
     return sysClock;
@@ -561,7 +561,7 @@ uint32_t RCM_ReadHCLKFreq(void)
  *
  * @retval    None
  */
-void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2)
+void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
 {
     uint32_t hclk, divider;
     uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@@ -992,20 +992,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
 
     switch (reg)
     {
-        case 0:
-            reg = RCM->CTRL;
-            break;
+    case 0:
+        reg = RCM->CTRL;
+        break;
 
-        case 1:
-            reg = RCM->BDCTRL;
-            break;
+    case 1:
+        reg = RCM->BDCTRL;
+        break;
 
-        case 2:
-            reg = RCM->CSTS;
-            break;
+    case 2:
+        reg = RCM->CSTS;
+        break;
 
-        default:
-            break;
+    default:
+        break;
     }
 
     if (reg & bit)
@@ -1048,7 +1048,7 @@ void RCM_ClearStatusFlag(void)
  */
 uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
 {
-    return (RCM->INT& flag) ? SET : RESET;
+    return (RCM->INT &flag) ? SET : RESET;
 }
 
 /*!

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_rtc.c

@@ -144,7 +144,7 @@ uint32_t RTC_ReadDivider(void)
  */
 void RTC_WaitForLastTask(void)
 {
-    while(RTC->CSTS_B.OCFLG == BIT_RESET)
+    while (RTC->CSTS_B.OCFLG == BIT_RESET)
     {
     }
 }
@@ -159,7 +159,7 @@ void RTC_WaitForLastTask(void)
 void RTC_WaitForSynchro(void)
 {
     RTC->CSTS_B.RSYNCFLG = BIT_RESET;
-    while(RTC->CSTS_B.RSYNCFLG == BIT_RESET);
+    while (RTC->CSTS_B.RSYNCFLG == BIT_RESET);
 }
 
 /*!
@@ -189,7 +189,7 @@ void RTC_EnableInterrupt(uint16_t interrupt)
  */
 void RTC_DisableInterrupt(uint16_t interrupt)
 {
-    RTC->CTRL &= (uint32_t )~interrupt;
+    RTC->CTRL &= (uint32_t)~interrupt;
 }
 
 /*!
@@ -207,7 +207,7 @@ void RTC_DisableInterrupt(uint16_t interrupt)
  */
 uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag)
 {
-    return  (RTC->CSTS & flag) ? SET : RESET;
+    return (RTC->CSTS & flag) ? SET : RESET;
 }
 
 /*!

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sci2c.c

@@ -47,7 +47,7 @@
  */
 void SCI2C_Reset(SCI2C_T *i2c)
 {
-    if(i2c == I2C3)
+    if (i2c == I2C3)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_I2C1);
@@ -78,7 +78,7 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
 
     i2c->CTRL2_B.I2CEN = BIT_RESET;
 
-    if(sci2cConfig->mode == SCI2C_MODE_MASTER)
+    if (sci2cConfig->mode == SCI2C_MODE_MASTER)
     {
         i2c->CTRL1_B.MST = BIT_SET;
         i2c->CTRL1_B.SLADIS = BIT_SET;
@@ -98,17 +98,17 @@ void SCI2C_Config(SCI2C_T *i2c, SCI2C_Config_T *sci2cConfig)
     i2c->CTRL1_B.SAM = sci2cConfig->addrMode;
     i2c->SLAADDR = sci2cConfig->slaveAddr;
 
-    if(sci2cConfig->speed == SCI2C_SPEED_STANDARD)
+    if (sci2cConfig->speed == SCI2C_SPEED_STANDARD)
     {
         i2c->SSCLC = sci2cConfig->clkLowPeriod;
         i2c->SSCHC = sci2cConfig->clkHighPeriod;
     }
-    else if(sci2cConfig->speed == SCI2C_SPEED_FAST)
+    else if (sci2cConfig->speed == SCI2C_SPEED_FAST)
     {
         i2c->FSCLC = sci2cConfig->clkLowPeriod;
         i2c->FSCHC = sci2cConfig->clkHighPeriod;
     }
-    else if(sci2cConfig->speed == SCI2C_SPEED_HIGH)
+    else if (sci2cConfig->speed == SCI2C_SPEED_HIGH)
     {
         i2c->HSCLC = sci2cConfig->clkLowPeriod;
         i2c->HSCHC = sci2cConfig->clkHighPeriod;
@@ -159,7 +159,7 @@ uint8_t SCI2C_ReadStatusFlag(SCI2C_T *i2c, SCI2C_FLAG_T flag)
 {
     uint8_t ret = RESET;
 
-    if(flag & BIT8)
+    if (flag & BIT8)
     {
         ret = i2c->STS2 & flag ? SET : RESET;
     }
@@ -228,47 +228,47 @@ void SCI2C_ClearIntFlag(SCI2C_T *i2c, SCI2C_INT_T flag)
 {
     volatile uint32_t dummy = 0;
 
-    if(flag == SCI2C_INT_ALL)
+    if (flag == SCI2C_INT_ALL)
     {
         dummy = i2c->INTCLR;
     }
-    else if(flag == SCI2C_INT_RFU)
+    else if (flag == SCI2C_INT_RFU)
     {
         dummy = i2c->RFUIC;
     }
-    else if(flag == SCI2C_INT_RFO)
+    else if (flag == SCI2C_INT_RFO)
     {
         dummy = i2c->RFOIC;
     }
-    else if(flag == SCI2C_INT_TFO)
+    else if (flag == SCI2C_INT_TFO)
     {
         dummy = i2c->TFOIC;
     }
-    else if(flag == SCI2C_INT_RR)
+    else if (flag == SCI2C_INT_RR)
     {
         dummy = i2c->RRIC;
     }
-    else if(flag == SCI2C_INT_TA)
+    else if (flag == SCI2C_INT_TA)
     {
         dummy = i2c->TAIC;
     }
-    else if(flag == SCI2C_INT_RD)
+    else if (flag == SCI2C_INT_RD)
     {
         dummy = i2c->RDIC;
     }
-    else if(flag == SCI2C_INT_ACT)
+    else if (flag == SCI2C_INT_ACT)
     {
         dummy = i2c->AIC;
     }
-    else if(flag == SCI2C_INT_STPD)
+    else if (flag == SCI2C_INT_STPD)
     {
         dummy = i2c->STPDIC;
     }
-    else if(flag == SCI2C_INT_STAD)
+    else if (flag == SCI2C_INT_STAD)
     {
         dummy = i2c->STADIC;
     }
-    else if(flag == SCI2C_INT_GC)
+    else if (flag == SCI2C_INT_GC)
     {
         dummy = i2c->GCIC;
     }
@@ -731,17 +731,17 @@ void SCI2C_BlockTxCmd(SCI2C_T *i2c, uint8_t enable)
  */
 void SCI2C_ConfigClkPeriod(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint16_t highPeriod, uint16_t lowPeriod)
 {
-    if(speed == SCI2C_SPEED_STANDARD)
+    if (speed == SCI2C_SPEED_STANDARD)
     {
         i2c->SSCLC = lowPeriod;
         i2c->SSCHC = highPeriod;
     }
-    else if(speed == SCI2C_SPEED_FAST)
+    else if (speed == SCI2C_SPEED_FAST)
     {
         i2c->FSCLC = lowPeriod;
         i2c->FSCHC = highPeriod;
     }
-    else if(speed == SCI2C_SPEED_HIGH)
+    else if (speed == SCI2C_SPEED_HIGH)
     {
         i2c->HSCLC = lowPeriod;
         i2c->HSCHC = highPeriod;
@@ -895,7 +895,7 @@ void SCI2C_ConfigDMARxDataLevel(SCI2C_T *i2c, uint8_t cnt)
  */
 void SCI2C_ConfigSpikeSuppressionLimit(SCI2C_T *i2c, SCI2C_SPEED_T speed, uint8_t limit)
 {
-    if(speed == SCI2C_SPEED_HIGH)
+    if (speed == SCI2C_SPEED_HIGH)
     {
         i2c->HSSSL = limit;
     }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_sdio.c

@@ -65,7 +65,7 @@ void SDIO_Reset(void)
  *
  * @retval       None
  */
-void SDIO_Config(SDIO_Config_T* sdioConfig)
+void SDIO_Config(SDIO_Config_T *sdioConfig)
 {
     uint32_t tmp = 0;
 
@@ -73,7 +73,7 @@ void SDIO_Config(SDIO_Config_T* sdioConfig)
     tmp &= 0xFFFF8100;
 
     tmp |= (sdioConfig->clockDiv  | sdioConfig->clockPowerSave | sdioConfig->clockBypass | sdioConfig->busWide |
-    sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
+            sdioConfig->clockEdge | sdioConfig->hardwareFlowControl);
 
     SDIO->CLKCTRL = tmp;
 }
@@ -85,14 +85,14 @@ void SDIO_Config(SDIO_Config_T* sdioConfig)
  *
  * @retval       None
  */
-void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig)
+void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig)
 {
-  sdioConfig->clockDiv = 0x00;
-  sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
-  sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
-  sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
-  sdioConfig->busWide = SDIO_BUS_WIDE_1B;
-  sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+    sdioConfig->clockDiv = 0x00;
+    sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
+    sdioConfig->clockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+    sdioConfig->clockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+    sdioConfig->busWide = SDIO_BUS_WIDE_1B;
+    sdioConfig->hardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
 }
 
 /*!
@@ -188,7 +188,7 @@ void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
     tmpreg = SDIO->CMD;
     tmpreg &= 0xFFFFF800;
     tmpreg |= (uint32_t)cmdConfig->cmdIndex | cmdConfig->response
-           | cmdConfig->wait | cmdConfig->CPSM;
+              | cmdConfig->wait | cmdConfig->CPSM;
     SDIO->CMD = tmpreg;
 }
 
@@ -200,13 +200,13 @@ void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
  * @retval       None
  *
  */
-void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig)
+void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig)
 {
-  cmdConfig->argument = 0x00;
-  cmdConfig->cmdIndex = 0x00;
-  cmdConfig->response = SDIO_RESPONSE_NO;
-  cmdConfig->wait = SDIO_WAIT_NO;
-  cmdConfig->CPSM = SDIO_CPSM_DISABLE;
+    cmdConfig->argument = 0x00;
+    cmdConfig->cmdIndex = 0x00;
+    cmdConfig->response = SDIO_RESPONSE_NO;
+    cmdConfig->wait = SDIO_WAIT_NO;
+    cmdConfig->CPSM = SDIO_CPSM_DISABLE;
 }
 
 /*!
@@ -236,11 +236,11 @@ uint8_t SDIO_ReadCommandResponse(void)
  */
 uint32_t SDIO_ReadResponse(SDIO_RES_T res)
 {
-  __IO uint32_t tmp = 0;
+    __IO uint32_t tmp = 0;
 
-  tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
+    tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
 
-  return (*(__IO uint32_t *) tmp);
+    return (*(__IO uint32_t *) tmp);
 }
 
 /*!
@@ -250,7 +250,7 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res)
  *
  * @retval       None
  */
-void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
+void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
 {
     uint32_t tmpreg = 0;
 
@@ -263,7 +263,7 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
     tmpreg &= 0xFFFFFF08;
 
     tmpreg |= (uint32_t)dataConfig->dataBlockSize | dataConfig->transferDir
-           | dataConfig->transferMode | dataConfig->DPSM;
+              | dataConfig->transferMode | dataConfig->DPSM;
 
     SDIO->DCTRL = tmpreg;
 }
@@ -275,14 +275,14 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
  *
  * @retval       None
  */
-void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig)
+void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig)
 {
-  dataConfig->dataTimeOut = 0xFFFFFFFF;
-  dataConfig->dataLength = 0x00;
-  dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
-  dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD;
-  dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
-  dataConfig->DPSM = SDIO_DPSM_DISABLE;
+    dataConfig->dataTimeOut = 0xFFFFFFFF;
+    dataConfig->dataLength = 0x00;
+    dataConfig->dataBlockSize = SDIO_DATA_BLOCKSIZE_1B;
+    dataConfig->transferDir = SDIO_TRANSFER_DIR_TO_CARD;
+    dataConfig->transferMode = SDIO_TRANSFER_MODE_BLOCK;
+    dataConfig->DPSM = SDIO_DPSM_DISABLE;
 }
 
 /*!
@@ -394,7 +394,7 @@ void SDIO_DisableStartReadWait(void)
  */
 void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
 {
-  *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
+    *(__IO uint32_t *) DCTRL_RDWAIT_BB = readWaitMode;
 }
 /*!
  * @brief        Enables SDIO SD I/O Mode Operation
@@ -405,7 +405,7 @@ void SDIO_ConfigSDIOReadWaitMode(SDIO_READ_WAIT_MODE_T readWaitMode)
  */
 void SDIO_EnableSDIO(void)
 {
-  *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
+    *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)SET;
 }
 
 /*!
@@ -417,7 +417,7 @@ void SDIO_EnableSDIO(void)
  */
 void SDIO_DisableSDIO(void)
 {
-  *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
+    *(__IO uint32_t *) DCTRL_SDIOF_BB = (uint32_t)RESET;
 }
 
 /*!

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_spi.c

@@ -45,19 +45,19 @@
  *
  * @retval    None
  */
-void SPI_I2S_Reset(SPI_T* spi)
+void SPI_I2S_Reset(SPI_T *spi)
 {
-    if(spi == SPI1)
+    if (spi == SPI1)
     {
         RCM_EnableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
         RCM_DisableAPB2PeriphReset(RCM_APB2_PERIPH_SPI1);
     }
-    else if(spi == SPI2)
+    else if (spi == SPI2)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI2);
     }
-    else if(spi == SPI3)
+    else if (spi == SPI3)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_SPI3);
@@ -73,13 +73,13 @@ void SPI_I2S_Reset(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
+void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
 {
     spi->CTRL1 &= 0x3040;
     spi->CTRL1 |= (uint16_t)((uint32_t)spiConfig->direction | spiConfig->mode |
-                   spiConfig->length | spiConfig->polarity |
-                   spiConfig->phase | spiConfig->nss |
-                   spiConfig->baudrateDiv | spiConfig->firstBit);
+                             spiConfig->length | spiConfig->polarity |
+                             spiConfig->phase | spiConfig->nss |
+                             spiConfig->baudrateDiv | spiConfig->firstBit);
     spi->CRCPOLY = spiConfig->crcPolynomial;
 }
 
@@ -92,7 +92,7 @@ void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
  *
  * @retval    None
  */
-void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
+void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
 {
     uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1;
     uint32_t tmp = 0;
@@ -102,14 +102,14 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
     spi->I2SCFG &= 0xF040;
     spi->I2SPSC = 0x0002;
 
-    if(i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
+    if (i2sConfig->audioDiv == I2S_AUDIO_DIV_DEFAULT)
     {
         spi->I2SPSC_B.ODDPSC = 0;
         spi->I2SPSC_B.I2SPSC = 2;
     }
     else
     {
-        if(i2sConfig->length == I2S_DATA_LENGHT_16B)
+        if (i2sConfig->length == I2S_DATA_LENGHT_16B)
         {
             packetSize = 1;
         }
@@ -120,13 +120,13 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
 
         sysClock = RCM_ReadSYSCLKFreq();
 
-        if(i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
+        if (i2sConfig->MCLKOutput == I2S_MCLK_OUTPUT_ENABLE)
         {
             tmp = (uint16_t)(((((sysClock / 256) * 10) / i2sConfig ->audioDiv)) + 5);
         }
         else
         {
-            tmp = (uint16_t)(((((sysClock / (32 * packetSize)) *10 ) / i2sConfig ->audioDiv )) + 5);
+            tmp = (uint16_t)(((((sysClock / (32 * packetSize)) * 10) / i2sConfig ->audioDiv)) + 5);
         }
         tmp = tmp / 10;
 
@@ -160,7 +160,7 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
+void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
 {
     spiConfig->direction = SPI_DIRECTION_2LINES_FULLDUPLEX;
     spiConfig->mode = SPI_MODE_SLAVE;
@@ -180,7 +180,7 @@ void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
  *
  * @retval    None
  */
-void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
+void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
 {
     i2sConfig->mode = I2S_MODE_SLAVE_TX;
     i2sConfig->standard = I2S_STANDARD_PHILLIPS;
@@ -196,7 +196,7 @@ void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_Enable(SPI_T* spi)
+void SPI_Enable(SPI_T *spi)
 {
     spi->CTRL1_B.SPIEN = BIT_SET;
 }
@@ -208,7 +208,7 @@ void SPI_Enable(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_Disable(SPI_T* spi)
+void SPI_Disable(SPI_T *spi)
 {
     spi->CTRL1_B.SPIEN = BIT_RESET;
 }
@@ -220,7 +220,7 @@ void SPI_Disable(SPI_T* spi)
  *
  * @retval    None
  */
-void I2S_Enable(SPI_T* spi)
+void I2S_Enable(SPI_T *spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_SET;
 }
@@ -232,7 +232,7 @@ void I2S_Enable(SPI_T* spi)
  *
  * @retval    None
  */
-void I2S_Disable(SPI_T* spi)
+void I2S_Disable(SPI_T *spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_RESET;
 }
@@ -248,9 +248,9 @@ void I2S_Disable(SPI_T* spi)
  *                     @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
  * @retval    None
  */
-void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
-    if(dmaReq == SPI_I2S_DMA_REQ_TX)
+    if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
         spi->CTRL2_B.TXDEN = ENABLE;
     }
@@ -271,9 +271,9 @@ void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
  *                     @arg SPI_I2S_DMA_REQ_RX: Rx buffer DMA transfer request
  * @retval    None
  */
-void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
-    if(dmaReq == SPI_I2S_DMA_REQ_TX)
+    if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
         spi->CTRL2_B.TXDEN = DISABLE;
     }
@@ -292,7 +292,7 @@ void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
  *
  * @retval    None
  */
-void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
+void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
 {
     spi->DATA = data;
 }
@@ -306,7 +306,7 @@ void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
  *
  * @retval    None
  */
-uint16_t SPI_I2S_RxData(SPI_T* spi)
+uint16_t SPI_I2S_RxData(SPI_T *spi)
 {
     return spi->DATA;
 }
@@ -318,7 +318,7 @@ uint16_t SPI_I2S_RxData(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_SetSoftwareNSS(SPI_T* spi)
+void SPI_SetSoftwareNSS(SPI_T *spi)
 {
     spi->CTRL1_B.ISSEL = BIT_SET;
 }
@@ -330,7 +330,7 @@ void SPI_SetSoftwareNSS(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_ResetSoftwareNSS(SPI_T* spi)
+void SPI_ResetSoftwareNSS(SPI_T *spi)
 {
     spi->CTRL1_B.ISSEL = BIT_RESET;
 }
@@ -342,7 +342,7 @@ void SPI_ResetSoftwareNSS(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableSSOutput(SPI_T* spi)
+void SPI_EnableSSOutput(SPI_T *spi)
 {
     spi->CTRL2_B.SSOEN = BIT_SET;
 }
@@ -354,7 +354,7 @@ void SPI_EnableSSOutput(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_DisableSSOutput(SPI_T* spi)
+void SPI_DisableSSOutput(SPI_T *spi)
 {
     spi->CTRL2_B.SSOEN = BIT_RESET;
 }
@@ -371,7 +371,7 @@ void SPI_DisableSSOutput(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
+void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
 {
     spi->CTRL1_B.DFLSEL = BIT_RESET;
     spi->CTRL1 |= length;
@@ -384,7 +384,7 @@ void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
  *
  * @retval    None
  */
-void SPI_TxCRC(SPI_T* spi)
+void SPI_TxCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCNXT = BIT_SET;
 }
@@ -396,7 +396,7 @@ void SPI_TxCRC(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableCRC(SPI_T* spi)
+void SPI_EnableCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCEN = BIT_SET;
 }
@@ -407,7 +407,7 @@ void SPI_EnableCRC(SPI_T* spi)
  * @param     spi: The SPIx can be 1,2,3
  *
  */
-void SPI_DisableCRC(SPI_T* spi)
+void SPI_DisableCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCEN = BIT_RESET;
 }
@@ -419,7 +419,7 @@ void SPI_DisableCRC(SPI_T* spi)
  *
  * @retval    The SPI transmit CRC register value
  */
-uint16_t SPI_ReadTxCRC(SPI_T* spi)
+uint16_t SPI_ReadTxCRC(SPI_T *spi)
 {
     return spi->TXCRC_B.TXCRC;
 }
@@ -431,7 +431,7 @@ uint16_t SPI_ReadTxCRC(SPI_T* spi)
  *
  * @retval    The SPI receive CRC register value
  */
-uint16_t SPI_ReadRxCRC(SPI_T* spi)
+uint16_t SPI_ReadRxCRC(SPI_T *spi)
 {
     return spi->RXCRC_B.RXCRC;
 }
@@ -443,7 +443,7 @@ uint16_t SPI_ReadRxCRC(SPI_T* spi)
  *
  * @retval    The SPI CRC Polynomial register value
  */
-uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
+uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
 {
     return spi->CRCPOLY_B.CRCPOLY;
 }
@@ -459,9 +459,9 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
  *                     @arg SPI_DIRECTION_TX: Selects Tx transmission direction
  * @retval    None
  */
-void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
+void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
 {
-    if(direction == SPI_DIRECTION_TX)
+    if (direction == SPI_DIRECTION_TX)
     {
         spi->CTRL1 |= SPI_DIRECTION_TX;
     }
@@ -483,9 +483,9 @@ void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
  *                     @arg SPI_I2S_INT_ERR: Error interrupt
  * @retval       None
  */
-void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
+void SPI_I2S_EnableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
 {
-     spi->CTRL2 |= (interrupt >> 8);
+    spi->CTRL2 |= (interrupt >> 8);
 }
 
 /*!
@@ -500,9 +500,9 @@ void SPI_I2S_EnableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
  *                     @arg SPI_I2S_INT_ERR: Error interrupt
  * @retval    None
  */
-void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
+void SPI_I2S_DisableInterrupt(SPI_T *spi, SPI_I2S_INT_T interrupt)
 {
-         spi->CTRL2 &= ~(interrupt >> 8);
+    spi->CTRL2 &= ~(interrupt >> 8);
 }
 
 /*!
@@ -523,9 +523,9 @@ void SPI_I2S_DisableInterrupt(SPI_T* spi, SPI_I2S_INT_T interrupt)
  *
  * @retval     SET or RESET
  */
-uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
+uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 {
-    if((spi->STS & flag) != RESET)
+    if ((spi->STS & flag) != RESET)
     {
         return SET;
     }
@@ -553,7 +553,7 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
+void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 {
     spi->STS_B.CRCEFLG = BIT_RESET;
 }
@@ -574,12 +574,12 @@ void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
  *
  * @retval       SET or RESET
  */
-uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
+uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 {
     uint32_t intEnable;
     uint32_t intStatus;
 
-    intEnable = (uint32_t)(spi->CTRL2 & (flag>>8));
+    intEnable = (uint32_t)(spi->CTRL2 & (flag >> 8));
     intStatus = (uint32_t)(spi->STS & flag);
 
     if (intEnable && intStatus)
@@ -608,7 +608,7 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
+void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 {
     spi->STS_B.CRCEFLG = BIT_RESET;
 }

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_tmr.c

@@ -38,10 +38,10 @@
   @{
 */
 
-static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
-static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
-static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
-static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
 
 /*!
  * @brief     Deinitializes the TMRx peripheral registers to their default reset values.
@@ -51,7 +51,7 @@ static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  * @retval    None
  *
  */
-void TMR_Reset(TMR_T* tmr)
+void TMR_Reset(TMR_T *tmr)
 {
     if (tmr == TMR1)
     {
@@ -104,12 +104,12 @@ void TMR_Reset(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig)
+void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig)
 {
     uint16_t temp;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         temp = tmr->CTRL1;
         temp &= 0x038F;
@@ -141,7 +141,7 @@ void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC1EN = BIT_RESET;
 
@@ -173,7 +173,7 @@ void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC2EN = BIT_RESET;
 
@@ -210,7 +210,7 @@ void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC3EN = BIT_RESET;
 
@@ -246,7 +246,7 @@ void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC4EN = BIT_RESET;
 
@@ -275,7 +275,7 @@ void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig)
+void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig)
 {
     if (ICConfig->channel == TMR_CHANNEL_1)
     {
@@ -308,15 +308,15 @@ void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig)
  *
  * @retval    None
  */
-void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig)
+void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig)
 {
-    tmr->BDT = (BDTConfig->IMOS)<<10 |\
-               (BDTConfig->RMOS)<<11 |\
-               (BDTConfig->lockLevel)<<8 |\
-               (BDTConfig->deadTime) |\
-               (BDTConfig->BRKState)<<12 |\
-               (BDTConfig->BRKPolarity)<<13 |\
-               (BDTConfig->automaticOutput)<<14;
+    tmr->BDT = (BDTConfig->IMOS) << 10 | \
+               (BDTConfig->RMOS) << 11 | \
+               (BDTConfig->lockLevel) << 8 | \
+               (BDTConfig->deadTime) | \
+               (BDTConfig->BRKState) << 12 | \
+               (BDTConfig->BRKPolarity) << 13 | \
+               (BDTConfig->automaticOutput) << 14;
 }
 
 /*!
@@ -326,7 +326,7 @@ void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig)
  *
  * @retval    None
  */
-void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig)
+void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig)
 {
     baseConfig->period = 0xFFFF;
     baseConfig->division = 0x0000;
@@ -342,7 +342,7 @@ void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig)
 {
     OCConfig->mode = TMR_OC_MODE_TMRING;
     OCConfig->outputState = TMR_OC_STATE_DISABLE;
@@ -361,7 +361,7 @@ void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig)
+void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig)
 {
     ICConfig->channel = TMR_CHANNEL_1;
     ICConfig->polarity = TMR_IC_POLARITY_RISING;
@@ -377,7 +377,7 @@ void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig)
  *
  * @retval    None
  */
-void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig)
+void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig)
 {
     BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE;
     BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE;
@@ -395,7 +395,7 @@ void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig)
  *
  * @retval    None
  */
-void TMR_Enable(TMR_T* tmr)
+void TMR_Enable(TMR_T *tmr)
 {
     tmr->CTRL1_B.CNTEN = ENABLE;
 }
@@ -407,7 +407,7 @@ void TMR_Enable(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_Disable(TMR_T* tmr)
+void TMR_Disable(TMR_T *tmr)
 {
     tmr->CTRL1_B.CNTEN = DISABLE;
 }
@@ -421,7 +421,7 @@ void TMR_Disable(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig)
+void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig)
 {
     uint16_t icpolarity = TMR_IC_POLARITY_RISING;
     uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI;
@@ -467,7 +467,7 @@ void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig)
  *
  * @retval    None
  */
-void TMR_EnablePWMOutputs(TMR_T* tmr)
+void TMR_EnablePWMOutputs(TMR_T *tmr)
 {
     tmr->BDT_B.MOEN = ENABLE;
 }
@@ -479,7 +479,7 @@ void TMR_EnablePWMOutputs(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisablePWMOutputs(TMR_T* tmr)
+void TMR_DisablePWMOutputs(TMR_T *tmr)
 {
     tmr->BDT_B.MOEN = DISABLE;
 }
@@ -495,7 +495,7 @@ void TMR_DisablePWMOutputs(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
+void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
 {
     tmr->DCTRL = (uint32_t)baseAddress | (uint32_t)burstLength;
 }
@@ -517,7 +517,7 @@ void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T
  * @retval    None
  *
  */
-void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource)
+void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource)
 {
     tmr->DIEN |= dmaSource;
 }
@@ -539,7 +539,7 @@ void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource)
  * @retval    None
  *
  */
-void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource)
+void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource)
 {
     tmr->DIEN &= ~dmaSource;
 }
@@ -551,7 +551,7 @@ void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource)
  *
  * @retval    None
  */
-void TMR_ConfigInternalClock(TMR_T* tmr)
+void TMR_ConfigInternalClock(TMR_T *tmr)
 {
     tmr->SMCTRL_B.SMFSEL = DISABLE;
 }
@@ -569,7 +569,7 @@ void TMR_ConfigInternalClock(TMR_T* tmr)
  *                   @arg TMR_TRIGGER_SOURCE_ITR3: TMR Internal Trigger 3
  * @retval    None
  */
-void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
+void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
 {
     TMR_SelectInputTrigger(tmr, triggerSource);
     tmr->SMCTRL_B.SMFSEL = 0x07;
@@ -595,8 +595,8 @@ void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSour
  *
  * @retval    None
  */
-void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
-                                TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
+void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
+                                 TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
 {
     if (triggerSource == 0x06)
     {
@@ -632,7 +632,7 @@ void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
  *
  * @retval    None
  */
-void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter)
 {
     TMR_ConfigETR(tmr, prescaler, polarity, filter);
@@ -662,7 +662,7 @@ void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
  *
  * @retval    None
  */
-void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter)
 {
     TMR_ConfigETR(tmr, prescaler, polarity, filter);
@@ -689,7 +689,7 @@ void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
  *
  * @retval    None
  */
-void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                    TMR_EXTTRG_POL_T polarity, uint16_t filter)
 {
     tmr->SMCTRL &= 0x00FF;
@@ -711,7 +711,7 @@ void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
  *                     @arg TMR_PSC_RELOAD_IMMEDIATE: The Prescaler is loaded immediately
  * @retval    None
  */
-void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode)
+void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscReloadMode)
 {
     tmr->PSC = prescaler;
     tmr->CEG_B.UEG = pscReloadMode;
@@ -731,7 +731,7 @@ void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t prescaler, TMR_PSC_RELOAD_T pscRel
  *                     @arg TMR_COUNTER_MODE_CENTERALIGNED3: Timer Center Aligned Mode3
  * @retval   None
  */
-void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode)
+void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode)
 {
     tmr->CTRL1_B.CNTDIR = BIT_RESET;
     tmr->CTRL1_B.CAMSEL = BIT_RESET;
@@ -756,7 +756,7 @@ void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode)
  *
  * @retval    None
  */
-void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
+void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
 {
     tmr->SMCTRL_B.TRGSEL = BIT_RESET;
     tmr->SMCTRL_B.TRGSEL = triggerSource;
@@ -785,7 +785,7 @@ void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
  *                     @arg TMR_IC_POLARITY_FALLING: TMR IC polarity falling
  * @retval    None
  */
-void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
+void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
                                TMR_IC_POLARITY_T IC2Polarity)
 {
     tmr->SMCTRL_B.SMFSEL = BIT_RESET;
@@ -812,7 +812,7 @@ void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC
  *                     @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF
  * @retval    None
  */
-void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM1_COMPARE_B.OC1MOD = BIT_RESET;
     tmr->CCM1_COMPARE_B.OC1MOD = forcesAction;
@@ -829,7 +829,7 @@ void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *                     @arg TMR_FORCED_ACTION_INACTIVE: Force inactive level on OC1REF
  * @retval    None
  */
-void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM1_COMPARE_B.OC2MOD = BIT_RESET;
     tmr->CCM1_COMPARE_B.OC2MOD = forcesAction;
@@ -847,7 +847,7 @@ void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM2_COMPARE_B.OC3MOD = BIT_RESET;
     tmr->CCM2_COMPARE_B.OC3MOD = forcesAction;
@@ -865,7 +865,7 @@ void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM2_COMPARE_B.OC4MOD = BIT_RESET;
     tmr->CCM2_COMPARE_B.OC4MOD = forcesAction;
@@ -878,7 +878,7 @@ void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_EnableAutoReload(TMR_T* tmr)
+void TMR_EnableAutoReload(TMR_T *tmr)
 {
     tmr->CTRL1_B.ARPEN = ENABLE;
 }
@@ -890,7 +890,7 @@ void TMR_EnableAutoReload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableAutoReload(TMR_T* tmr)
+void TMR_DisableAutoReload(TMR_T *tmr)
 {
     tmr->CTRL1_B.ARPEN = DISABLE;
 }
@@ -902,7 +902,7 @@ void TMR_DisableAutoReload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_EnableSelectCOM(TMR_T* tmr)
+void TMR_EnableSelectCOM(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCUSEL = ENABLE;
 }
@@ -913,7 +913,7 @@ void TMR_EnableSelectCOM(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableSelectCOM(TMR_T* tmr)
+void TMR_DisableSelectCOM(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCUSEL = DISABLE;
 }
@@ -925,7 +925,7 @@ void TMR_DisableSelectCOM(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_EnableCCDMA(TMR_T* tmr)
+void TMR_EnableCCDMA(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCDSEL = ENABLE;
 }
@@ -937,7 +937,7 @@ void TMR_EnableCCDMA(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableCCDMA(TMR_T* tmr)
+void TMR_DisableCCDMA(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCDSEL = DISABLE;
 }
@@ -949,7 +949,7 @@ void TMR_DisableCCDMA(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_EnableCCPreload(TMR_T* tmr)
+void TMR_EnableCCPreload(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCPEN = ENABLE;
 }
@@ -961,7 +961,7 @@ void TMR_EnableCCPreload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableCCPreload(TMR_T* tmr)
+void TMR_DisableCCPreload(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCPEN = DISABLE;
 }
@@ -977,7 +977,7 @@ void TMR_DisableCCPreload(TMR_T* tmr)
  *                     @arg TMR_OC_PRELOAD_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM1_COMPARE_B.OC1PEN = OCPreload;
 }
@@ -993,7 +993,7 @@ void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *                     @arg TMR_OC_PRELOAD_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM1_COMPARE_B.OC2PEN = OCPreload;
 }
@@ -1009,7 +1009,7 @@ void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *                     @arg TMR_OC_PRELOAD_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM2_COMPARE_B.OC3PEN = OCPreload;
 }
@@ -1025,7 +1025,7 @@ void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *                     @arg TMR_OC_PRELOAD_ENABLE
  * @retval    Nonee
  */
-void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM2_COMPARE_B.OC4PEN = OCPreload;
 }
@@ -1041,7 +1041,7 @@ void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *                     @arg TMR_OC_FAST_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM1_COMPARE_B.OC1FEN = OCFast;
 }
@@ -1057,7 +1057,7 @@ void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *                     @arg TMR_OC_FAST_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM1_COMPARE_B.OC2FEN = OCFast;
 }
@@ -1073,7 +1073,7 @@ void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *                     @arg TMR_OC_FAST_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM2_COMPARE_B.OC3FEN = OCFast;
 }
@@ -1089,7 +1089,7 @@ void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *                     @arg TMR_OC_FAST_ENABLE
  * @retval    None
  */
-void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM2_COMPARE_B.OC4FEN = OCFast;
 }
@@ -1105,7 +1105,7 @@ void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *                     @arg TMR_OC_CLEAR_ENABLE
  * @retval    None
  */
-void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM1_COMPARE_B.OC1CEN = OCClear;
 }
@@ -1121,7 +1121,7 @@ void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *                     @arg TMR_OC_CLEAR_ENABLE
  * @retval    None
  */
-void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM1_COMPARE_B.OC2CEN = OCClear;
 }
@@ -1137,7 +1137,7 @@ void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *                     @arg TMR_OC_CLEAR_ENABLE
  * @retval    None
  */
-void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM2_COMPARE_B.OC3CEN = OCClear;
 }
@@ -1153,7 +1153,7 @@ void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *                     @arg TMR_OC_CLEAR_ENABLE
  * @retval    None
  */
-void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM2_COMPARE_B.OC4CEN = OCClear;
 }
@@ -1169,7 +1169,7 @@ void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *                     @arg TMR_OC_POLARITY_LOW: Output Compare active low
  * @retval    Nonee
  */
-void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC1POL = polarity;
 }
@@ -1185,7 +1185,7 @@ void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *                     @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
  * @retval    None
  */
-void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
+void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
 {
     tmr->CCEN_B.CC1NPOL = nPolarity;
 }
@@ -1201,7 +1201,7 @@ void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
  *                     @arg TMR_OC_POLARITY_LOW: Output Compare active low
  * @retval    None
  */
-void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC2POL = polarity;
 }
@@ -1217,7 +1217,7 @@ void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *                     @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
  * @retval    None
  */
-void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
+void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
 {
     tmr->CCEN_B.CC2NPOL = nPolarity;
 }
@@ -1233,7 +1233,7 @@ void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
  *                     @arg TMR_OC_POLARITY_LOW: Output Compare active low
  * @retval    None
  */
-void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC3POL = polarity;
 }
@@ -1249,7 +1249,7 @@ void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *                     @arg TMR_OC_NPOLARITY_LOW: Output Compare active low
  * @retval    None
  */
-void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
+void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
 {
     tmr->CCEN_B.CC3NPOL = nPolarity;
 }
@@ -1265,7 +1265,7 @@ void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
  *                     @arg TMR_OC_POLARITY_LOW: Output Compare active low
  * @retval    None
  */
-void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC4POL = polarity;
 }
@@ -1283,7 +1283,7 @@ void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *                     @arg TMR_CHANNEL_4: Timer Channel 4
  * @retval    None
  */
-void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     tmr->CCEN |= BIT_SET << channel;
 }
@@ -1301,7 +1301,7 @@ void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *                     @arg TMR_CHANNEL_4: Timer Channel 4
  * @retval    None
  */
-void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     tmr->CCEN &= BIT_RESET << channel;
 }
@@ -1318,7 +1318,7 @@ void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *                     @arg TMR_CHANNEL_3: Timer Channel 3
  * @retval    None
  */
-void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     tmr->CCEN |= 0x04 << channel;
 }
@@ -1335,7 +1335,7 @@ void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *                     @arg TMR_CHANNEL_3: Timer Channel 3
  * @retval    None
  */
-void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     tmr->CCEN &= BIT_RESET << channel;
 }
@@ -1364,7 +1364,7 @@ void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *                     @arg TMR_OC_MODE_PWM2
  * @retval    None
  */
-void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
+void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
 {
     tmr->CCEN &= BIT_RESET << channel;
 
@@ -1393,7 +1393,7 @@ void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
  *
  * @retval    None
  */
-void TMR_EnableUpdate(TMR_T* tmr)
+void TMR_EnableUpdate(TMR_T *tmr)
 {
     tmr->CTRL1_B.UD = DISABLE;
 }
@@ -1405,7 +1405,7 @@ void TMR_EnableUpdate(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableUpdate(TMR_T* tmr)
+void TMR_DisableUpdate(TMR_T *tmr)
 {
     tmr->CTRL1_B.UD = ENABLE;
 }
@@ -1421,7 +1421,7 @@ void TMR_DisableUpdate(TMR_T* tmr)
  *                     @arg TMR_UPDATE_SOURCE_REGULAR
  * @retval    None
  */
-void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource)
+void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource)
 {
     if (updateSource != TMR_UPDATE_SOURCE_GLOBAL)
     {
@@ -1440,7 +1440,7 @@ void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource)
  *
  * @retval    None
  */
-void TMR_EnableHallSensor(TMR_T* tmr)
+void TMR_EnableHallSensor(TMR_T *tmr)
 {
     tmr->CTRL2_B.TI1SEL = ENABLE;
 }
@@ -1452,7 +1452,7 @@ void TMR_EnableHallSensor(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableHallSensor(TMR_T* tmr)
+void TMR_DisableHallSensor(TMR_T *tmr)
 {
     tmr->CTRL2_B.TI1SEL = DISABLE;
 }
@@ -1468,7 +1468,7 @@ void TMR_DisableHallSensor(TMR_T* tmr)
  *                     @arg TMR_SPM_SINGLE
  * @retval    None
  */
-void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode)
+void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode)
 {
     tmr->CTRL1_B.SPMEN = singlePulseMode;
 }
@@ -1491,7 +1491,7 @@ void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode)
  *                     @arg TMR_TRGO_SOURCE_OC4REF
  * @retval    None
  */
-void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource)
+void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource)
 {
     tmr->CTRL2_B.MMSEL = TRGOSource;
 }
@@ -1509,7 +1509,7 @@ void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource)
  *                     @arg TMR_SLAVE_MODE_EXTERNAL1
  * @retval    None
  */
-void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode)
+void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode)
 {
     tmr->SMCTRL_B.SMFSEL = slaveMode;
 }
@@ -1521,7 +1521,7 @@ void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode)
  *
  * @retval    None
  */
-void TMR_EnableMasterSlaveMode(TMR_T* tmr)
+void TMR_EnableMasterSlaveMode(TMR_T *tmr)
 {
     tmr->SMCTRL_B.MSMEN = ENABLE;
 }
@@ -1533,7 +1533,7 @@ void TMR_EnableMasterSlaveMode(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableMasterSlaveMode(TMR_T* tmr)
+void TMR_DisableMasterSlaveMode(TMR_T *tmr)
 {
     tmr->SMCTRL_B.MSMEN = DISABLE;
 }
@@ -1547,7 +1547,7 @@ void TMR_DisableMasterSlaveMode(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter)
+void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter)
 {
     tmr->CNT = counter;
 }
@@ -1561,7 +1561,7 @@ void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter)
  *
  * @retval    None
  */
-void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload)
+void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload)
 {
     tmr->AUTORLD = autoReload;
 }
@@ -1575,7 +1575,7 @@ void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload)
  *
  * @retval    None
  */
-void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1)
+void TMR_ConfigCompare1(TMR_T *tmr, uint16_t compare1)
 {
     tmr->CC1 = compare1;
 }
@@ -1589,7 +1589,7 @@ void TMR_ConfigCompare1(TMR_T* tmr, uint16_t compare1)
  *
  * @retval    None
  */
-void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2)
+void TMR_ConfigCompare2(TMR_T *tmr, uint16_t compare2)
 {
     tmr->CC2 = compare2;
 }
@@ -1603,7 +1603,7 @@ void TMR_ConfigCompare2(TMR_T* tmr, uint16_t compare2)
  *
  * @retval    None
  */
-void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3)
+void TMR_ConfigCompare3(TMR_T *tmr, uint16_t compare3)
 {
     tmr->CC3 = compare3;
 }
@@ -1617,7 +1617,7 @@ void TMR_ConfigCompare3(TMR_T* tmr, uint16_t compare3)
  *
  * @retval    None
  */
-void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4)
+void TMR_ConfigCompare4(TMR_T *tmr, uint16_t compare4)
 {
     tmr->CC4 = compare4;
 }
@@ -1635,7 +1635,7 @@ void TMR_ConfigCompare4(TMR_T* tmr, uint16_t compare4)
  *                     @arg TMR_IC_PSC_8: capture is done once every 8 events
  * @retval    None
  */
-void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC1Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM1_CAPTURE_B.IC1PSC = BIT_RESET;
     tmr->CCM1_CAPTURE_B.IC1PSC = prescaler;
@@ -1653,7 +1653,7 @@ void TMR_ConfigIC1Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *                     @arg TMR_IC_PSC_8: capture is done once every 8 events
  * @retval    None
  */
-void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC2Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM1_CAPTURE_B.IC2PSC = BIT_RESET;
     tmr->CCM1_CAPTURE_B.IC2PSC = prescaler;
@@ -1672,7 +1672,7 @@ void TMR_ConfigIC2Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *                     @arg TMR_IC_PSC_8: capture is done once every 8 events
  * @retval    None
  */
-void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC3Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM2_CAPTURE_B.IC3PSC = BIT_RESET;
     tmr->CCM2_CAPTURE_B.IC3PSC = prescaler;
@@ -1691,7 +1691,7 @@ void TMR_ConfigIC3Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *                     @arg TMR_IC_PSC_8: capture is done once every 8 events
  * @retval    None
  */
-void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC4Prescal(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM2_CAPTURE_B.IC4PSC = BIT_RESET;
     tmr->CCM2_CAPTURE_B.IC4PSC = prescaler;
@@ -1709,7 +1709,7 @@ void TMR_ConfigIC4Prescal(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *                     @arg TMR_CLOCK_DIV_4: TDTS = 4*Tck_tim
  * @retval    None
  */
-void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision)
+void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision)
 {
     tmr->CTRL1_B.CLKDIV = clockDivision;
 }
@@ -1721,7 +1721,7 @@ void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision)
  *
  * @retval    Capture Compare 1 Register value.
  */
-uint16_t TMR_ReadCaputer1(TMR_T* tmr)
+uint16_t TMR_ReadCaputer1(TMR_T *tmr)
 {
     return tmr->CC1;
 }
@@ -1733,7 +1733,7 @@ uint16_t TMR_ReadCaputer1(TMR_T* tmr)
  *
  * @retval    Capture Compare 2 Register value.
  */
-uint16_t TMR_ReadCaputer2(TMR_T* tmr)
+uint16_t TMR_ReadCaputer2(TMR_T *tmr)
 {
     return tmr->CC2;
 }
@@ -1745,7 +1745,7 @@ uint16_t TMR_ReadCaputer2(TMR_T* tmr)
  *
  * @retval    Capture Compare 3 Register value.
  */
-uint16_t TMR_ReadCaputer3(TMR_T* tmr)
+uint16_t TMR_ReadCaputer3(TMR_T *tmr)
 {
     return tmr->CC3;
 }
@@ -1757,7 +1757,7 @@ uint16_t TMR_ReadCaputer3(TMR_T* tmr)
  *
  * @retval    Capture Compare 4 Register value.
  */
-uint16_t TMR_ReadCaputer4(TMR_T* tmr)
+uint16_t TMR_ReadCaputer4(TMR_T *tmr)
 {
     return tmr->CC4;
 }
@@ -1769,7 +1769,7 @@ uint16_t TMR_ReadCaputer4(TMR_T* tmr)
  *
  * @retval    Counter Register value.
  */
-uint16_t TMR_ReadCounter(TMR_T* tmr)
+uint16_t TMR_ReadCounter(TMR_T *tmr)
 {
     return tmr->CNT;
 }
@@ -1781,7 +1781,7 @@ uint16_t TMR_ReadCounter(TMR_T* tmr)
  *
  * @retval    Prescaler Register value.
  */
-uint16_t TMR_ReadPrescaler(TMR_T* tmr)
+uint16_t TMR_ReadPrescaler(TMR_T *tmr)
 {
     return tmr->PSC;
 }
@@ -1805,7 +1805,7 @@ uint16_t TMR_ReadPrescaler(TMR_T* tmr)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt)
+void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt)
 {
     tmr->DIEN |= interrupt;
 }
@@ -1829,7 +1829,7 @@ void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt)
+void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt)
 {
     tmr->DIEN &= ~interrupt;
 }
@@ -1853,7 +1853,7 @@ void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE.
  */
-void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources)
+void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources)
 {
     tmr->CEG = eventSources;
 }
@@ -1881,7 +1881,7 @@ void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
  */
-uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag)
+uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag)
 {
     return (tmr->STS & flag) ? SET : RESET;
 }
@@ -1909,7 +1909,7 @@ uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
  */
-void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag)
+void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag)
 {
     tmr->STS = ~flag;
 }
@@ -1933,9 +1933,9 @@ void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag)
+uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag)
 {
-    if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET))
+    if (((tmr->STS & flag) != RESET) && ((tmr->DIEN & flag) != RESET))
     {
         return SET;
     }
@@ -1964,7 +1964,7 @@ uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-void TMR_ClearIntFlag(TMR_T* tmr,  uint16_t flag)
+void TMR_ClearIntFlag(TMR_T *tmr,  uint16_t flag)
 {
     tmr->STS = ~flag;
 }
@@ -1982,7 +1982,7 @@ void TMR_ClearIntFlag(TMR_T* tmr,  uint16_t flag)
  *
  * @retval    None
  */
-static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 
@@ -1994,7 +1994,7 @@ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
     tmr->CCM1_CAPTURE_B.IC1F   = ICfilter;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         tmr->CCEN_B.CC1POL = BIT_RESET;
         tmr->CCEN_B.CC1EN  = BIT_SET;
@@ -2026,7 +2026,7 @@ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @retval    None
  */
-static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 
@@ -2038,7 +2038,7 @@ static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
     tmr->CCM1_CAPTURE_B.IC2F   = ICfilter;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         tmr->CCEN_B.CC2POL = BIT_RESET;
         tmr->CCEN_B.CC2EN  = BIT_SET;
@@ -2070,7 +2070,7 @@ static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @retval    None
  */
-static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 
@@ -2082,7 +2082,7 @@ static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
     tmr->CCM2_CAPTURE_B.IC3F   = ICfilter;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         tmr->CCEN_B.CC3POL = BIT_RESET;
         tmr->CCEN_B.CC3EN  = BIT_SET;
@@ -2114,7 +2114,7 @@ static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @retval    None
  */
-static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_usart.c

@@ -47,7 +47,7 @@
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Reset(USART_T* usart)
+void USART_Reset(USART_T *usart)
 {
     if (USART1 == usart)
     {
@@ -87,7 +87,7 @@ void USART_Reset(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
+void USART_Config(USART_T *uart, USART_Config_T *usartConfig)
 {
     uint32_t temp, fCLK, intDiv, fractionalDiv;
 
@@ -132,7 +132,7 @@ void USART_Config(USART_T* uart, USART_Config_T* usartConfig)
  *
  * @retval    None
  */
-void USART_ConfigStructInit(USART_Config_T* usartConfig)
+void USART_ConfigStructInit(USART_Config_T *usartConfig)
 {
     usartConfig->baudRate = 9600;
     usartConfig->wordLength = USART_WORD_LEN_8B;
@@ -153,7 +153,7 @@ void USART_ConfigStructInit(USART_Config_T* usartConfig)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
+void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
 {
     usart->CTRL2_B.CLKEN   = clockConfig->clock;
     usart->CTRL2_B.CPHA    = clockConfig->phase;
@@ -169,7 +169,7 @@ void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
  * @retval    None
  *
  */
-void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
+void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
 {
     clockConfig->clock     = USART_CLKEN_DISABLE;
     clockConfig->phase     = USART_CLKPHA_1EDGE;
@@ -186,7 +186,7 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Enable(USART_T* usart)
+void USART_Enable(USART_T *usart)
 {
     usart->CTRL1_B.UEN = BIT_SET;
 }
@@ -200,7 +200,7 @@ void USART_Enable(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Disable(USART_T* usart)
+void USART_Disable(USART_T *usart)
 {
     usart->CTRL1_B.UEN = BIT_RESET;
 }
@@ -220,7 +220,7 @@ void USART_Disable(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
+void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3 |= dmaReq;
 }
@@ -240,7 +240,7 @@ void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
+void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3 &= (uint32_t)~dmaReq;
 }
@@ -256,7 +256,7 @@ void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_Address(USART_T* usart, uint8_t address)
+void USART_Address(USART_T *usart, uint8_t address)
 {
     usart->CTRL2_B.ADDR = address;
 }
@@ -275,7 +275,7 @@ void USART_Address(USART_T* usart, uint8_t address)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
+void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
 {
     usart->CTRL1_B.WUPMCFG = wakeup;
 }
@@ -289,7 +289,7 @@ void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableMuteMode(USART_T* usart)
+void USART_EnableMuteMode(USART_T *usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_SET;
 }
@@ -303,7 +303,7 @@ void USART_EnableMuteMode(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableMuteMode(USART_T* usart)
+void USART_DisableMuteMode(USART_T *usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_RESET;
 }
@@ -322,7 +322,7 @@ void USART_DisableMuteMode(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
+void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
 {
     usart->CTRL2_B.LBDLCFG = length;
 }
@@ -336,7 +336,7 @@ void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableLIN(USART_T* usart)
+void USART_EnableLIN(USART_T *usart)
 {
     usart->CTRL2_B.LINMEN = BIT_SET;
 }
@@ -350,7 +350,7 @@ void USART_EnableLIN(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableLIN(USART_T* usart)
+void USART_DisableLIN(USART_T *usart)
 {
     usart->CTRL2_B.LINMEN = BIT_RESET;
 }
@@ -364,7 +364,7 @@ void USART_DisableLIN(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableTx(USART_T* usart)
+void USART_EnableTx(USART_T *usart)
 {
     usart->CTRL1_B.TXEN = BIT_SET;
 }
@@ -378,7 +378,7 @@ void USART_EnableTx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableTx(USART_T* usart)
+void USART_DisableTx(USART_T *usart)
 {
     usart->CTRL1_B.TXEN = BIT_RESET;
 }
@@ -392,7 +392,7 @@ void USART_DisableTx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableRx(USART_T* usart)
+void USART_EnableRx(USART_T *usart)
 {
     usart->CTRL1_B.RXEN = BIT_SET;
 }
@@ -406,7 +406,7 @@ void USART_EnableRx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableRx(USART_T* usart)
+void USART_DisableRx(USART_T *usart)
 {
     usart->CTRL1_B.RXEN = BIT_RESET;
 }
@@ -422,7 +422,7 @@ void USART_DisableRx(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_TxData(USART_T* usart, uint16_t data)
+void USART_TxData(USART_T *usart, uint16_t data)
 {
     usart->DATA_B.DATA = data;
 }
@@ -436,7 +436,7 @@ void USART_TxData(USART_T* usart, uint16_t data)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint16_t USART_RxData(USART_T* usart)
+uint16_t USART_RxData(USART_T *usart)
 {
     return (uint16_t)(usart->DATA_B.DATA);
 }
@@ -450,7 +450,7 @@ uint16_t USART_RxData(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_TxBreak(USART_T* usart)
+void USART_TxBreak(USART_T *usart)
 {
     usart->CTRL1_B.TXBF = BIT_SET;
 }
@@ -466,7 +466,7 @@ void USART_TxBreak(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
+void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime)
 {
     usart->GTPSC_B.GRDT = guardTime;
 }
@@ -482,7 +482,7 @@ void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
  *
  * @note      The usart can be USART1, USART2, USART3
  */
-void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
+void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
 {
     usart->GTPSC_B.PSC = div;
 }
@@ -496,7 +496,7 @@ void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCard(USART_T* usart)
+void USART_EnableSmartCard(USART_T *usart)
 {
     usart->CTRL3_B.SCEN = BIT_SET;
 }
@@ -510,7 +510,7 @@ void USART_EnableSmartCard(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCard(USART_T* usart)
+void USART_DisableSmartCard(USART_T *usart)
 {
     usart->CTRL3_B.SCEN = BIT_RESET;
 }
@@ -524,7 +524,7 @@ void USART_DisableSmartCard(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCardNACK(USART_T* usart)
+void USART_EnableSmartCardNACK(USART_T *usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_SET;
 }
@@ -538,7 +538,7 @@ void USART_EnableSmartCardNACK(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCardNACK(USART_T* usart)
+void USART_DisableSmartCardNACK(USART_T *usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_RESET;
 }
@@ -552,7 +552,7 @@ void USART_DisableSmartCardNACK(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableHalfDuplex(USART_T* usart)
+void USART_EnableHalfDuplex(USART_T *usart)
 {
     usart->CTRL3_B.HDEN = BIT_SET;
 }
@@ -566,7 +566,7 @@ void USART_EnableHalfDuplex(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableHalfDuplex(USART_T* usart)
+void USART_DisableHalfDuplex(USART_T *usart)
 {
     usart->CTRL3_B.HDEN = BIT_RESET;
 }
@@ -584,7 +584,7 @@ void USART_DisableHalfDuplex(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
+void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
 {
     usart->CTRL3_B.IRLPEN = IrDAMode;
 }
@@ -598,7 +598,7 @@ void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableIrDA(USART_T* usart)
+void USART_EnableIrDA(USART_T *usart)
 {
     usart->CTRL3_B.IREN = BIT_SET;
 }
@@ -612,7 +612,7 @@ void USART_EnableIrDA(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableIrDA(USART_T* usart)
+void USART_DisableIrDA(USART_T *usart)
 {
     usart->CTRL3_B.IREN = BIT_RESET;
 }
@@ -637,7 +637,7 @@ void USART_DisableIrDA(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
+void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
@@ -679,7 +679,7 @@ void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
+void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
@@ -723,7 +723,7 @@ void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
+uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag)
 {
     return (usart->STS & flag) ? SET : RESET;
 }
@@ -744,7 +744,7 @@ uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
+void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
 {
     usart->STS &= (uint32_t)~flag;
 }
@@ -771,7 +771,7 @@ void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
+uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
 {
     uint32_t itFlag, srFlag;
 
@@ -816,7 +816,7 @@ uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4 and UART5
  */
-void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag)
+void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag)
 {
     uint32_t srFlag;
 

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/apm32f10x_wwdt.c

@@ -139,7 +139,7 @@ void WWDT_Enable(uint8_t counter)
  */
 uint8_t WWDT_ReadFlag(void)
 {
-    return (uint8_t) (WWDT->STS);
+    return (uint8_t)(WWDT->STS);
 }
 
 /*!

bsp/apm32/libraries/APM32F10x_Library/Device/Geehy/APM32F10x/Source/system_apm32f10x.c

@@ -43,38 +43,38 @@
 #define VECT_TAB_OFFSET     0x00
 
 #ifdef SYSTEM_CLOCK_HSE
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_HSE;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_HSE;
 #elif defined SYSTEM_CLOCK_24MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_24MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_24MHz;
 #elif defined SYSTEM_CLOCK_36MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_36MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_36MHz;
 #elif defined SYSTEM_CLOCK_48MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_48MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_48MHz;
 #elif defined SYSTEM_CLOCK_56MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_56MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_56MHz;
 #elif defined SYSTEM_CLOCK_72MHz
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_72MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_72MHz;
 #else
-uint32_t SystemCoreClock         = SYSTEM_CLOCK_96MHz;
+    uint32_t SystemCoreClock         = SYSTEM_CLOCK_96MHz;
 #endif
 
 
 static void SystemClockConfig(void);
 
 #ifdef SYSTEM_CLOCK_HSE
-static void SystemClockHSE(void);
+    static void SystemClockHSE(void);
 #elif defined SYSTEM_CLOCK_24MHz
-static void SystemClock24M(void);
+    static void SystemClock24M(void);
 #elif defined SYSTEM_CLOCK_36MHz
-static void SystemClock36M(void);
+    static void SystemClock36M(void);
 #elif defined SYSTEM_CLOCK_48MHz
-static void SystemClock48M(void);
+    static void SystemClock48M(void);
 #elif defined SYSTEM_CLOCK_56MHz
-static void SystemClock56M(void);
+    static void SystemClock56M(void);
 #elif defined SYSTEM_CLOCK_72MHz
-static void SystemClock72M(void);
+    static void SystemClock72M(void);
 #elif defined SYSTEM_CLOCK_96MHz
-static void SystemClock96M(void);
+    static void SystemClock96M(void);
 #endif
 
 /*!
@@ -85,7 +85,7 @@ static void SystemClock96M(void);
  * @retval      None
  *
  */
-void SystemInit (void)
+void SystemInit(void)
 {
     /** Set HSIEN bit */
     RCM->CTRL_B.HSIEN = BIT_SET;
@@ -118,50 +118,50 @@ void SystemInit (void)
  * @retval      None
  *
  */
-void SystemCoreClockUpdate (void)
+void SystemCoreClockUpdate(void)
 {
     uint32_t sysClock, pllMull, pllSource, Prescaler;
     uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
     sysClock = RCM->CFG_B.SCLKSELSTS;
 
-    switch(sysClock)
+    switch (sysClock)
     {
-        /** sys clock is HSI */
-        case 0:
-            SystemCoreClock = HSI_VALUE;
+    /** sys clock is HSI */
+    case 0:
+        SystemCoreClock = HSI_VALUE;
         break;
 
-        /** sys clock is HSE */
-        case 1:
-            SystemCoreClock = HSE_VALUE;
+    /** sys clock is HSE */
+    case 1:
+        SystemCoreClock = HSE_VALUE;
         break;
 
-        /** sys clock is PLL */
-        case 2:
-            pllMull = RCM->CFG_B.PLLMULCFG + 2;
-            pllSource = RCM->CFG_B.PLLSRCSEL;
+    /** sys clock is PLL */
+    case 2:
+        pllMull = RCM->CFG_B.PLLMULCFG + 2;
+        pllSource = RCM->CFG_B.PLLSRCSEL;
 
-            /** PLL entry clock source is HSE */
-            if(pllSource == BIT_SET)
-            {
-                SystemCoreClock = HSE_VALUE * pllMull;
+        /** PLL entry clock source is HSE */
+        if (pllSource == BIT_SET)
+        {
+            SystemCoreClock = HSE_VALUE * pllMull;
 
-                /** HSE clock divided by 2 */
-                if(pllSource == RCM->CFG_B.PLLHSEPSC)
-                {
-                    SystemCoreClock >>= 1;
-                }
-            }
-            /** PLL entry clock source is HSI/2 */
-            else
+            /** HSE clock divided by 2 */
+            if (pllSource == RCM->CFG_B.PLLHSEPSC)
             {
-                SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
+                SystemCoreClock >>= 1;
             }
-            break;
+        }
+        /** PLL entry clock source is HSI/2 */
+        else
+        {
+            SystemCoreClock = (HSI_VALUE >> 1) * pllMull;
+        }
+        break;
 
-        default:
-            SystemCoreClock  = HSI_VALUE;
+    default:
+        SystemCoreClock  = HSI_VALUE;
         break;
     }
 
@@ -209,17 +209,17 @@ static void SystemClockHSE(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -227,9 +227,9 @@ static void SystemClockHSE(void)
         FMC->CTRL1_B.WS = 0;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
@@ -237,7 +237,7 @@ static void SystemClockHSE(void)
         RCM->CFG_B.SCLKSEL = 1;
 
         /** Wait till HSE is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS!= 0x01);
+        while (RCM->CFG_B.SCLKSELSTS != 0x01);
     }
 }
 
@@ -255,17 +255,17 @@ static void SystemClock24M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -273,9 +273,9 @@ static void SystemClock24M(void)
         FMC->CTRL1_B.WS = 0;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
@@ -287,12 +287,12 @@ static void SystemClock24M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
         /** Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
         /** Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS!= 0x02);
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -309,17 +309,17 @@ static void SystemClock36M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -327,9 +327,9 @@ static void SystemClock36M(void)
         FMC->CTRL1_B.WS = 1;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK */
         RCM->CFG_B.APB1PSC = 0;
 
@@ -341,12 +341,12 @@ static void SystemClock36M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
         /** Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
         /** Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS != 0x02);
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -363,17 +363,17 @@ static void SystemClock48M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -381,9 +381,9 @@ static void SystemClock48M(void)
         FMC->CTRL1_B.WS = 1;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
@@ -394,12 +394,12 @@ static void SystemClock48M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
         /** Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
         /** Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS!= 0x02);
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -416,17 +416,17 @@ static void SystemClock56M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -434,9 +434,9 @@ static void SystemClock56M(void)
         FMC->CTRL1_B.WS = 2;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
@@ -447,12 +447,12 @@ static void SystemClock56M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
         /** Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
         /** Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS!= 0x02);
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 
@@ -469,17 +469,17 @@ static void SystemClock72M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -487,9 +487,9 @@ static void SystemClock72M(void)
         FMC->CTRL1_B.WS = 2;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
@@ -500,12 +500,12 @@ static void SystemClock72M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
         /** Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
         /** Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS!= 0x02);
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 
 }
@@ -523,17 +523,17 @@ static void SystemClock96M(void)
 {
     __IO uint32_t i;
 
-    RCM->CTRL_B.HSEEN= BIT_SET;
+    RCM->CTRL_B.HSEEN = BIT_SET;
 
-    for(i = 0; i < HSE_STARTUP_TIMEOUT; i++)
+    for (i = 0; i < HSE_STARTUP_TIMEOUT; i++)
     {
-        if(RCM->CTRL_B.HSERDYFLG)
+        if (RCM->CTRL_B.HSERDYFLG)
         {
             break;
         }
     }
 
-    if(RCM->CTRL_B.HSERDYFLG)
+    if (RCM->CTRL_B.HSERDYFLG)
     {
         /** Enable Prefetch Buffer */
         FMC->CTRL1_B.PBEN = BIT_SET;
@@ -541,9 +541,9 @@ static void SystemClock96M(void)
         FMC->CTRL1_B.WS = 3;
 
         /** HCLK = SYSCLK */
-        RCM->CFG_B.AHBPSC= 0X00;
+        RCM->CFG_B.AHBPSC = 0X00;
         /** PCLK2 = HCLK */
-        RCM->CFG_B.APB2PSC= 0;
+        RCM->CFG_B.APB2PSC = 0;
         /** PCLK1 = HCLK / 2 */
         RCM->CFG_B.APB1PSC = 4;
 
@@ -554,12 +554,12 @@ static void SystemClock96M(void)
         /** Enable PLL */
         RCM->CTRL_B.PLLEN = 1;
         /** Wait PLL Ready */
-        while(RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
+        while (RCM->CTRL_B.PLLRDYFLG == BIT_RESET);
 
         /** Select PLL as system clock source */
         RCM->CFG_B.SCLKSEL = 2;
         /** Wait till PLL is used as system clock source */
-        while(RCM->CFG_B.SCLKSELSTS!= 0x02);
+        while (RCM->CFG_B.SCLKSELSTS != 0x02);
     }
 }
 #endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/inc/usbd_class_cdc.h

@@ -1,33 +0,0 @@
-/*!
- * @file        usbd_class_cdc.h
- *
- * @brief       CDC Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __CDC_CLASS_
-#define __CDC_CLASS_
-
-#include "usbd_core.h"
-
-void USBD_ClassHandler(USBD_DevReqData_T* reqData);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/CDC/src/usbd_class_cdc.c

@@ -1,71 +0,0 @@
-/*!
- * @file        usbd_class_cdc.c
- *
- * @brief       CDC Class handler file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_cdc.h"
-
-static uint8_t cmdBuf[8] = {0};
-
-/*!
- * @brief       USB CDC Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_ClassHandler(USBD_DevReqData_T* reqData)
-{
-    uint16_t length = ((uint16_t)reqData->byte.wLength[1] << 8) | \
-                     reqData->byte.wLength[0] ;
-
-    if (!length)
-    {
-        if (!reqData->byte.bmRequestType.bit.dir)
-        {
-            USBD_CtrlTxStatus();
-        }
-        else
-        {
-            USBD_CtrlRxStatus();
-        }
-    }
-    else
-    {
-        switch (reqData->byte.bRequest)
-        {
-
-            case 0x20:
-                USBD_CtrlOutData(cmdBuf, length);
-                break;
-            case 0x21:
-                USBD_CtrlInData(cmdBuf, length);
-                break;
-            case 0x22:
-                USBD_CtrlOutData(cmdBuf, length);
-                break;
-            default:
-                break;
-        }
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/inc/usbd_class_hid.h

@@ -1,37 +0,0 @@
-/*!
- * @file        usbd_class_hid.h
- *
- * @brief       HID Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-
-#define HID_CLASS_REQ_SET_PROTOCOL          0x0B
-#define HID_CLASS_REQ_GET_PROTOCOL          0x03
-
-#define HID_CLASS_REQ_SET_IDLE              0x0A
-#define HID_CLASS_REQ_GET_IDLE              0x02
-
-#define HID_CLASS_REQ_SET_REPORT            0x09
-#define HID_CLASS_REQ_GET_REPORT            0x01
-
-void USBD_ClassHandler(USBD_DevReqData_T* reqData);

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/HID/src/usbd_class_hid.c

@@ -1,63 +0,0 @@
-/*!
- * @file        usbd_class_hid.c
- *
- * @brief       HID Class handler file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_hid.h"
-
-static uint8_t s_hidIdleState;
-static uint8_t s_hidProtocol;
-
-/*!
- * @brief       USB HID Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_ClassHandler(USBD_DevReqData_T* reqData)
-{
-    switch (reqData->byte.bRequest)
-    {
-        case HID_CLASS_REQ_SET_IDLE:
-            s_hidIdleState = reqData->byte.wValue[1];
-            USBD_CtrlInData(NULL, 0);
-            break;
-
-        case HID_CLASS_REQ_GET_IDLE:
-            USBD_CtrlInData(&s_hidIdleState, 1);
-            break;
-
-        case HID_CLASS_REQ_SET_PROTOCOL:
-            s_hidProtocol = reqData->byte.wValue[0];
-            USBD_CtrlInData(NULL, 0);
-            break;
-
-        case HID_CLASS_REQ_GET_PROTOCOL:
-            USBD_CtrlInData(&s_hidProtocol, 1);
-            break;
-
-        default:
-            break;
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_class_msc.h

@@ -1,37 +0,0 @@
-/*!
- * @file        usbd_class_msc.h
- *
- * @brief       MSC Class handler file head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_CLASS_MSC
-#define __USBD_CLASS_MSC
-
-#include "usbd_core.h"
-
-
-#define BOT_GET_MAX_LUN              0xFE
-#define BOT_RESET                    0xFF
-
-void USBD_MSC_ClassHandler(USBD_DevReqData_T* reqData);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_bot.h

@@ -1,106 +0,0 @@
-/*!
- * @file        usbd_msc_bot.h
- *
- * @brief       MSC BOT protocol core functions
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-
-#ifndef __USBD_MSC_BOT_H
-#define __USBD_MSC_BOT_H
-
-#define MSC_BOT_CBW_SIGNATURE             (uint32_t)(0x43425355)
-#define MSC_BOT_CBW_LENGTH                31
-
-#define MSC_BOT_CSW_SIGNATURE             (uint32_t)(0x53425355)
-#define MSC_BOT_CSW_LENGTH                13
-
-typedef enum
-{
-    BOT_STATE_IDLE,          //!< Idle state
-    BOT_STATE_DATA_OUT,      //!< Data Out state
-    BOT_STATE_DATA_IN,       //!< Data In state
-    BOT_STATE_LAST_DATA_IN,  //!< Last Data In Last
-    BOT_STATE_SEND_DATA      //!< Send Immediate data
-} BOT_STATE_T;
-
-typedef enum
-{
-    BOT_STATUS_NORMAL,
-    BOT_STATUS_RECOVERY,
-    BOT_STATUS_ERROR
-} BOT_STATUS_T;
-
-typedef enum
-{
-    BOT_CSW_STATUS_CMD_OK,
-    BOT_CSW_STATUS_CMD_FAIL,
-    BOT_CSW_STATUS_PHASE_ERROR
-} BOT_CSW_STATUS_T;
-
-
-/**
- * @brief   Command Block Wrapper
- */
-typedef struct
-{
-    uint32_t dSignature;
-    uint32_t dTag;
-    uint32_t dDataXferLen;
-    uint8_t  bmFlags;
-    uint8_t  bLUN;
-    uint8_t  bCBLen;
-    uint8_t  CB[16];
-} BOT_CBW_T;
-
-/**
- * @brief   Command Status Wrapper
- */
-typedef struct
-{
-    uint32_t dSignature;
-    uint32_t dTag;
-    uint32_t dDataResidue;
-    uint8_t  bStatus;
-} BOT_CSW_T;
-
-typedef struct
-{
-    uint8_t   state;
-    uint8_t   status;
-    uint16_t  dataLen;
-    BOT_CBW_T CBW;
-    BOT_CSW_T CSW;
-    uint8_t   data[MSC_MEDIA_PACKET];
-} BOT_Info_T;
-
-extern BOT_Info_T g_BOTInfo;
-
-void USBD_MSC_BOT_Reset(void);
-void USBD_MSC_BOT_Init(void);
-void USBD_MSC_BOT_OutData(uint8_t ep);
-void USBD_MSC_BOT_InData(uint8_t ep);
-void USBD_MSC_BOT_TxCSW(uint8_t cswStatus);
-void USBD_MSC_BOT_Stall(void);
-void USBD_MSV_BOT_ClearFeatureHandler(void);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/inc/usbd_msc_scsi.h

@@ -1,131 +0,0 @@
-/*!
- * @file        usbd_msc_scsi.h
- *
- * @brief       MSC scsi
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-#ifndef __USBD_MSC_SCSI_H_
-#define __USBD_MSC_SCSI_H_
-
-/**
- * @brief   SCSI function status
- */
-enum
-{
-    SCSI_OK,
-    SCSI_FAIL
-};
-
-/**
- * @brief   SCSI Sense Key
- */
-typedef enum
-{
-    SCSI_SKEY_NO_SENSE,
-    SCSI_SKEY_RECOVERED_ERROR,
-    SCSI_SKEY_NOT_READY,
-    SCSI_SKEY_MEDIUM_ERROR,
-    SCSI_SKEY_HARDWARE_ERROR,
-    SCSI_SKEY_ILLEGAL_REQUEST,
-    SCSI_SKEY_UNIT_ATTENTION,
-    SCSI_SKEY_DATA_PROTECT,
-    SCSI_SKEY_BLANK_CHECK,
-    SCSI_SKEY_VENDOR_SPECIFIC,
-    SCSI_SKEY_COPY_ABORTED,
-    SCSI_SKEY_ABORTED_COMMAND,
-    SCSI_SKEY_VOLUME_OVERFLOW = 13,
-    SCSI_SKEY_MISCOMPARE      = 14
-} SCSI_SKEY_T;
-
-/**
- * @brief   SCSI Sense
- */
-typedef struct {
-    uint8_t sensekey;
-    uint8_t ASC;
-    uint8_t ASCQ;
-} SCSI_Sense_T;
-
-
-#define SCSI_SENSE_LIST_NUMBER                      4
-#define SCSI_INQUIRY_LENGTH                         36
-
-/** SCSI Commands */
-#define SCSI_CMD_FORMAT_UNIT                        ((uint8_t)0x04)
-#define SCSI_CMD_INQUIRY                            ((uint8_t)0x12)
-#define SCSI_CMD_MODE_SELECT_6                      ((uint8_t)0x15)
-#define SCSI_CMD_MODE_SELECT_10                     ((uint8_t)0x55)
-#define SCSI_CMD_MODE_SENSE_6                       ((uint8_t)0x1A)
-#define SCSI_CMD_MODE_SENSE_10                      ((uint8_t)0x5A)
-#define SCSI_CMD_ALLOW_MEDIUM_REMOVAL               ((uint8_t)0x1E)
-#define SCSI_CMD_READ_6                             ((uint8_t)0x08)
-#define SCSI_CMD_READ_10                            ((uint8_t)0x28)
-#define SCSI_CMD_READ_12                            ((uint8_t)0xA8)
-#define SCSI_CMD_READ_16                            ((uint8_t)0x88)
-
-#define SCSI_CMD_READ_CAPACITY_10                   ((uint8_t)0x25)
-#define SCSI_CMD_READ_CAPACITY_16                   ((uint8_t)0x9E)
-
-#define SCSI_CMD_REQUEST_SENSE                      ((uint8_t)0x03)
-#define SCSI_CMD_START_STOP_UNIT                    ((uint8_t)0x1B)
-#define SCSI_CMD_TEST_UNIT_READY                    ((uint8_t)0x00)
-#define SCSI_CMD_WRITE6                             ((uint8_t)0x0A)
-#define SCSI_CMD_WRITE10                            ((uint8_t)0x2A)
-#define SCSI_CMD_WRITE12                            ((uint8_t)0xAA)
-#define SCSI_CMD_WRITE16                            ((uint8_t)0x8A)
-
-#define SCSI_CMD_VERIFY_10                          ((uint8_t)0x2F)
-#define SCSI_CMD_VERIFY_12                          ((uint8_t)0xAF)
-#define SCSI_CMD_VERIFY_16                          ((uint8_t)0x8F)
-
-#define SCSI_CMD_SEND_DIAGNOSTIC                    ((uint8_t)0x1D)
-#define SCSI_CMD_READ_FORMAT_CAPACITIES             ((uint8_t)0x23)
-
-
-#define SCSI_ASC_INVALID_CDB                         0x20
-#define SCSI_ASC_INVALID_FIELED_IN_COMMAND           0x24
-#define SCSI_ASC_PARAMETER_LIST_LENGTH_ERROR         0x1A
-#define SCSI_ASC_INVALID_FIELD_IN_PARAMETER_LIST     0x26
-#define SCSI_ASC_ADDRESS_OUT_OF_RANGE                0x21
-#define SCSI_ASC_MEDIUM_NOT_PRESENT                  0x3A
-#define SCSI_ASC_MEDIUM_HAVE_CHANGED                 0x28
-#define SCSI_ASC_WRITE_PROTECTED                     0x27
-#define SCSI_ASC_UNRECOVERED_READ_ERROR              0x11
-#define SCSI_ASC_WRITE_FAULT                         0x03
-
-#define SCSI_READ_FORMAT_CAPACITY_DATA_LEN           0x0C
-#define SCSI_READ_CAPACITY10_DATA_LEN                0x08
-#define SCSI_MODE_SENSE10_DATA_LEN                   0x08
-#define SCSI_MODE_SENSE6_DATA_LEN                    0x04
-#define SCSI_REQUEST_SENSE_DATA_LEN                  0x12
-#define SCSI_STANDARD_INQUIRY_DATA_LEN               0x24
-#define SCSI_BLKVFY                                  0x04
-
-extern SCSI_Sense_T g_scsiSense[SCSI_SENSE_LIST_NUMBER];
-extern uint8_t g_senseTxCnt;
-extern uint8_t g_sensePutCnt;
-
-uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t *cmd);
-void   SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_class_msc.c

@@ -1,79 +0,0 @@
-/*!
- * @file        usbd_class_msc.c
- *
- * @brief       MSC Class file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_class_msc.h"
-#include "usbd_msc_bot.h"
-
-static uint8_t s_mscMaxLen = 0;
-
-/*!
- * @brief       USB MSC Class request handler
- *
- * @param       reqData : point to USBD_DevReqData_T structure
- *
- * @retval      None
- */
-void USBD_MSC_ClassHandler(USBD_DevReqData_T* reqData)
-{
-    uint16_t wValue = ((uint16_t)reqData->byte.wValue[1] << 8) | \
-                                 reqData->byte.wValue[0];
-    uint16_t wLength = ((uint16_t)reqData->byte.wLength[1] << 8) | \
-                                 reqData->byte.wLength[0];
-
-    switch (reqData->byte.bRequest)
-    {
-        case BOT_GET_MAX_LUN :
-            if ((wValue == 0) && (wLength == 1) && \
-                (reqData->byte.bmRequestType.bit.dir == 1))
-            {
-                s_mscMaxLen = STORAGE_MAX_LUN - 1;
-
-                USBD_CtrlInData(&s_mscMaxLen, 1);
-            }
-            else
-            {
-                USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-            }
-            break;
-        case BOT_RESET :
-            if ((wValue == 0) && (wLength == 0) && \
-                (reqData->byte.bmRequestType.bit.dir == 0))
-            {
-                USBD_CtrlInData(NULL, 0);
-                /** Reset */
-                USBD_MSC_BOT_Reset();
-            }
-            else
-            {
-                USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-            }
-
-            break;
-
-        default:
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-            break;
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_bot.c

@@ -1,242 +0,0 @@
-/*!
- * @file        usbd_msv_bot.c
- *
- * @brief       MSC BOT protocol core functions
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_msc_bot.h"
-#include "usbd_core.h"
-#include "usbd_storage_disk.h"
-#include "usbd_msc_scsi.h"
-
-BOT_Info_T g_BOTInfo;
-
-static void USBD_MSC_BOT_DecodeCBW(void);
-static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len);
-static void USBD_MSC_BOT_Stall(void);
-
-/*!
- * @brief       BOT Process Reset.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSC_BOT_Reset(void)
-{
-    g_BOTInfo.state = BOT_STATE_IDLE;
-    g_BOTInfo.status = BOT_STATUS_RECOVERY;
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       BOT Process initialization.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSC_BOT_Init(void)
-{
-    g_BOTInfo.state = BOT_STATE_IDLE;
-    g_BOTInfo.status = BOT_STATUS_NORMAL;
-
-    g_storageCallBack.Init(0);
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW, MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       Bulk OUT data handler.
- *
- * @param       ep : OUT endpoint
- *
- * @retval      None
- */
-void USBD_MSC_BOT_OutData(uint8_t ep)
-{
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        USBD_MSC_BOT_DecodeCBW();
-    }
-    else if (g_BOTInfo.state == BOT_STATE_DATA_OUT)
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-        }
-    }
-}
-
-/*!
- * @brief       Bulk IN data handler.
- *
- * @param       ep : IN endpoint
- *
- * @retval      None
- */
-void USBD_MSC_BOT_InData(uint8_t ep)
-{
-    if (g_BOTInfo.state == BOT_STATE_DATA_IN)
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-        }
-    }
-    else if ((g_BOTInfo.state == BOT_STATE_SEND_DATA) || \
-             (g_BOTInfo.state == BOT_STATE_LAST_DATA_IN))
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-    }
-}
-
-/*!
- * @brief       Decode CBW.
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_DecodeCBW(void)
-{
-    uint32_t xferCnt = g_usbDev.outBuf[MSC_OUT_EP & 0x7f].xferCnt;
-
-    g_BOTInfo.CSW.dTag = g_BOTInfo.CBW.dTag;
-    g_BOTInfo.CSW.dDataResidue = g_BOTInfo.CBW.dDataXferLen;
-
-    if ((xferCnt != MSC_BOT_CBW_LENGTH) || \
-        (g_BOTInfo.CBW.dSignature != MSC_BOT_CBW_SIGNATURE) || \
-        (g_BOTInfo.CBW.bLUN > 1) || (g_BOTInfo.CBW.bCBLen < 1) || \
-        (g_BOTInfo.CBW.bCBLen > 16))
-    {
-        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_CDB, 0);
-
-        g_BOTInfo.status = BOT_STATUS_ERROR;
-    }
-    else
-    {
-        if (SCSI_CmdHandler(g_BOTInfo.CBW.bLUN, g_BOTInfo.CBW.CB) != SCSI_OK)
-        {
-            USBD_MSC_BOT_Stall();
-        }
-        else if ((g_BOTInfo.state == BOT_STATE_IDLE) || \
-                 (g_BOTInfo.state == BOT_STATE_SEND_DATA))
-        {
-            if (g_BOTInfo.dataLen)
-            {
-                USBD_MSC_BOT_TxData(g_BOTInfo.data, g_BOTInfo.dataLen);
-            }
-            else
-            {
-                USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-            }
-        }
-    }
-}
-
-/*!
- * @brief       MSC send data.
- *
- * @param       txBuf : buffer to send
- *
- * @param       len : buffer length
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_TxData(uint8_t *txBuf, uint16_t len)
-{
-    len = USB_MIN(len, g_BOTInfo.CBW.dDataXferLen);
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-    g_BOTInfo.CSW.bStatus = BOT_CSW_STATUS_CMD_OK;
-    g_BOTInfo.state = BOT_STATE_SEND_DATA;
-
-    USBD_TxData(MSC_IN_EP & 0x7f, txBuf, len);
-}
-
-/*!
- * @brief       Send CSW.
- *
- * @param       cswStatus : status of CSW
- *
- * @retval      None
- */
-void USBD_MSC_BOT_TxCSW(uint8_t cswStatus)
-{
-    g_BOTInfo.CSW.dSignature = MSC_BOT_CSW_SIGNATURE;
-    g_BOTInfo.CSW.bStatus = cswStatus;
-    g_BOTInfo.state = BOT_STATE_IDLE;
-
-    USBD_TxData(MSC_IN_EP & 0x7f, (uint8_t*)&g_BOTInfo.CSW,
-                MSC_BOT_CSW_LENGTH);
-
-    USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t*)&g_BOTInfo.CBW,
-                MSC_BOT_CBW_LENGTH);
-}
-
-/*!
- * @brief       handler clearFeature in standard request.
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_MSV_BOT_ClearFeatureHandler(void)
-{
-    if (g_BOTInfo.status == BOT_STATUS_ERROR)
-    {
-        USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_NAK);
-        g_BOTInfo.status = BOT_STATUS_NORMAL;
-    }
-    else if (((g_usbDev.reqData.byte.wIndex[0] & 0x80) == 0x80) && \
-             g_BOTInfo.status != BOT_STATUS_RECOVERY)
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_FAIL);
-    }
-}
-
-/*!
- * @brief       Stall MSC.
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_MSC_BOT_Stall(void)
-{
-    if ((g_BOTInfo.CBW.bmFlags == 0) && (g_BOTInfo.CBW.dDataXferLen != 0) && \
-        (g_BOTInfo.status == BOT_STATUS_NORMAL))
-    {
-        USBD_SetEPRxStatus(MSC_OUT_EP & 0x7f, USBD_EP_STATUS_STALL);
-    }
-
-    USBD_SetEPTxStatus(MSC_IN_EP & 0x7f, USBD_EP_STATUS_STALL);
-
-    if (g_BOTInfo.status == BOT_STATUS_ERROR)
-    {
-        USBD_RxData(MSC_OUT_EP & 0x7f, (uint8_t *)&g_BOTInfo.CBW,
-                    MSC_BOT_CBW_LENGTH);
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Class/MSC/src/usbd_msc_scsi.c

@@ -1,701 +0,0 @@
-/*!
- * @file        usbd_msc_scsi.c
- *
- * @brief       MSC scsi
- *
- * @version     V1.0.0
- *
- * @date        2021-12-25
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_msc_bot.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_storage_disk.h"
-
-SCSI_Sense_T g_scsiSenseCode[SCSI_SENSE_LIST_NUMBER];
-uint8_t g_senseTxCnt;
-uint8_t g_sensePutCnt;
-
-static uint32_t  s_blkSize;
-static uint32_t  s_blkNbr;
-
-static uint32_t  s_blkAddr;
-static uint32_t  s_blkLen;
-
-/** USB Mass storage Page 0 Inquiry Data */
-static const uint8_t  s_page00InquiryData[] =
-{
-    0x00,
-    0x00,
-    0x00,
-    (7 - 4),
-    0x00,
-    0x80,
-    0x83
-};
-/** USB Mass storage sense 6 Data */
-static const uint8_t  s_modeSense6Data[] =
-{
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00
-};
-/** USB Mass storage sense 10 Data */
-static const uint8_t  s_modeSense10Data[] =
-{
-    0x00,
-    0x06,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00,
-    0x00
-};
-
-static uint8_t SCSI_TestUnitReady(uint8_t lun);
-static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t* command);
-static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t* command);
-
-static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t* command);
-static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t* command);
-static uint8_t SCSI_Read10(uint8_t lun, uint8_t* command);
-static uint8_t SCSI_Write10(uint8_t lun, uint8_t* command);
-static uint8_t SCSI_Verify10(uint8_t lun, uint8_t* command);
-
-static uint8_t SCSI_StartStopUnit(void);
-static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t* command);
-static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t* command);
-
-static uint8_t SCSI_Read(uint8_t lun);
-static uint8_t SCSI_Write(uint8_t lun);
-static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr);
-
-/*!
- * @brief       SCSI command handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: Command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-uint8_t SCSI_CmdHandler(uint8_t lun, uint8_t* command)
-{
-    uint8_t ret = SCSI_OK;
-
-    switch (command[0])
-    {
-        case SCSI_CMD_TEST_UNIT_READY:
-            ret = SCSI_TestUnitReady(lun);
-            break;
-
-        case SCSI_CMD_INQUIRY:
-            ret = SCSI_Inquiry(lun, command);
-            break;
-
-        case SCSI_CMD_REQUEST_SENSE:
-            ret = SCSI_RequestSense(lun, command);
-            break;
-
-        case SCSI_CMD_READ_FORMAT_CAPACITIES:
-            ret = SCSI_ReadFormatCapacity(lun, command);
-            break;
-
-        case SCSI_CMD_READ_CAPACITY_10:
-            ret = SCSI_ReadCapacity10(lun, command);
-            break;
-
-        case SCSI_CMD_READ_10:
-            ret = SCSI_Read10(lun, command);
-            break;
-
-        case SCSI_CMD_WRITE10:
-            ret = SCSI_Write10(lun, command);
-            break;
-
-        case SCSI_CMD_VERIFY_10:
-            ret = SCSI_Verify10(lun, command);
-            break;
-        case SCSI_CMD_ALLOW_MEDIUM_REMOVAL:
-        case SCSI_CMD_START_STOP_UNIT:
-            ret = SCSI_StartStopUnit();
-            break;
-
-        case SCSI_CMD_MODE_SENSE_6:
-            ret = SCSI_ModeSense6 (lun, command);
-            break;
-
-        case SCSI_CMD_MODE_SENSE_10:
-            ret = SCSI_ModeSense10 (lun, command);
-            break;
-
-        default:
-            SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
-                                        SCSI_ASC_INVALID_CDB, 0);
-            ret = SCSI_FAIL;
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       Put the sense code to array.
- *
- * @param       sKey: sense Key
- *
- * @param       ASC: Additional Sense Code
- *
- * @param       ASCQ: Additional Sense Code Qualifier
- *
- * @retval      None
- */
-void SCSI_PutSenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC, uint8_t ASCQ)
-{
-    g_scsiSenseCode[g_sensePutCnt].sensekey = sKey;
-    g_scsiSenseCode[g_sensePutCnt].ASC = ASC;
-    g_scsiSenseCode[g_sensePutCnt].ASCQ = ASCQ;
-
-    if ((++g_sensePutCnt) == SCSI_SENSE_LIST_NUMBER)
-    {
-        g_sensePutCnt = 0;
-    }
-}
-
-/*!
- * @brief       SCSI Test Unit Ready handler.
- *
- * @param       lun: Logical unit number
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_TestUnitReady(uint8_t lun)
-{
-    if (g_BOTInfo.CBW.dDataXferLen)
-    {
-        SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_INVALID_CDB, 0);
-
-        return SCSI_FAIL;
-    }
-    else if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-        return SCSI_FAIL;
-    }
-    else
-    {
-        g_BOTInfo.dataLen = 0;
-        return SCSI_OK;
-    }
-}
-
-/*!
- * @brief       SCSI Inquiry handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Inquiry(uint8_t lun, uint8_t* command)
-{
-    uint16_t i;
-    uint8_t* pInquiryData;
-
-    if (command[1] & 0x01)
-    {
-        pInquiryData = (uint8_t*)s_page00InquiryData;
-        g_BOTInfo.dataLen = s_page00InquiryData[3] + 4;
-    }
-    else
-    {
-        pInquiryData = &g_storageCallBack.pInquiryData[lun * SCSI_INQUIRY_LENGTH];
-
-        g_BOTInfo.dataLen = USB_MIN((pInquiryData[4] + 5), command[4]);
-    }
-
-    for (i = 0; i < g_BOTInfo.dataLen; i++)
-    {
-        g_BOTInfo.data[i] = pInquiryData[i];
-    }
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Request Sense handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_RequestSense(uint8_t lun, uint8_t* command)
-{
-    uint8_t i = 0;
-
-    while (i < SCSI_REQUEST_SENSE_DATA_LEN)
-    {
-        g_BOTInfo.data[i++] = 0;
-    }
-
-    g_BOTInfo.data[0] = 0x70;
-    g_BOTInfo.data[7] = SCSI_REQUEST_SENSE_DATA_LEN - 6;
-
-    if (g_senseTxCnt != g_sensePutCnt)
-    {
-        g_BOTInfo.data[2] = g_scsiSenseCode[g_senseTxCnt].sensekey;
-        g_BOTInfo.data[12] = g_scsiSenseCode[g_senseTxCnt].ASC;
-        g_BOTInfo.data[13] = g_scsiSenseCode[g_senseTxCnt].ASCQ;
-
-        if ((++g_senseTxCnt) == SCSI_SENSE_LIST_NUMBER)
-        {
-            g_senseTxCnt = 0;
-        }
-    }
-
-    g_BOTInfo.dataLen = (SCSI_REQUEST_SENSE_DATA_LEN < command[4]) ? \
-                         SCSI_REQUEST_SENSE_DATA_LEN : command[4];
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Read Format Capacity handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t* command)
-{
-    uint16_t i = 0;
-    uint32_t blkSize;
-    uint32_t blkNbr;
-
-    while (i < 12)
-    {
-        g_BOTInfo.data[i++] = 0;
-    }
-
-    if (g_storageCallBack.ReadCapacity(lun, &blkNbr, &blkSize) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                          SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-        return SCSI_FAIL;
-    }
-    else
-    {
-        blkNbr--;
-
-        g_BOTInfo.data[3] = 0x08;
-        g_BOTInfo.data[4] = (uint8_t)(blkNbr >> 24);
-        g_BOTInfo.data[5] = (uint8_t)(blkNbr >> 16);
-        g_BOTInfo.data[6] = (uint8_t)(blkNbr >> 8);
-        g_BOTInfo.data[7] = (uint8_t)(blkNbr);
-        g_BOTInfo.data[8] = 0x02;
-        g_BOTInfo.data[9] = (uint8_t)(blkSize >> 16);
-        g_BOTInfo.data[10] = (uint8_t)(blkSize >> 8);
-        g_BOTInfo.data[11] = (uint8_t)blkSize;
-
-        g_BOTInfo.dataLen = 12;
-
-        return SCSI_OK;
-    }
-}
-
-/*!
- * @brief       SCSI Read Capacity10 handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t* command)
-{
-    if (g_storageCallBack.ReadCapacity(lun, &s_blkNbr, &s_blkSize) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                        SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-        return SCSI_FAIL;
-    }
-    else
-    {
-        g_BOTInfo.data[0] = (uint8_t)((s_blkNbr - 1) >> 24);
-        g_BOTInfo.data[1] = (uint8_t)((s_blkNbr - 1) >> 16);
-        g_BOTInfo.data[2] = (uint8_t)((s_blkNbr - 1) >>  8);
-        g_BOTInfo.data[3] = (uint8_t)(s_blkNbr - 1);
-        g_BOTInfo.data[4] = (uint8_t)(s_blkSize >>  24);
-        g_BOTInfo.data[5] = (uint8_t)(s_blkSize >>  16);
-        g_BOTInfo.data[6] = (uint8_t)(s_blkSize >>  8);
-        g_BOTInfo.data[7] = (uint8_t)(s_blkSize);
-
-        g_BOTInfo.dataLen = 8;
-
-        return SCSI_OK;
-    }
-}
-
-/*!
- * @brief       SCSI Read10 handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Read10(uint8_t lun, uint8_t* command)
-{
-    uint8_t ret = SCSI_OK;
-
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        if ((g_BOTInfo.CBW.bmFlags & 0x80) != 0x80)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                            SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-        if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
-        {
-            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                        SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-            return SCSI_FAIL;
-        }
-
-        s_blkAddr = ((uint32_t)command[2] << 24) | \
-                    ((uint32_t)command[3] << 16) | \
-                    ((uint32_t)command[4] << 8)  | \
-                     (uint32_t)command[5];
-
-        s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t )command[8]);
-
-        if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
-        {
-            return SCSI_FAIL;
-        }
-
-        g_BOTInfo.state = BOT_STATE_DATA_IN;
-        s_blkAddr *= s_blkSize;
-        s_blkLen *= s_blkSize;
-
-        if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                            SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-    }
-
-    g_BOTInfo.dataLen = MSC_MEDIA_PACKET;
-
-    ret = SCSI_Read(lun);
-
-    return ret;
-}
-
-/*!
- * @brief       SCSI write10 handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Write10(uint8_t lun, uint8_t* command)
-{
-    uint8_t ret = SCSI_OK;
-    uint32_t len;
-
-    if (g_BOTInfo.state == BOT_STATE_IDLE)
-    {
-        if (g_BOTInfo.CBW.bmFlags & 0x80)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                            SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-        if (g_storageCallBack.CheckReady(lun) != SCSI_OK)
-        {
-            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                           SCSI_ASC_MEDIUM_NOT_PRESENT, 0);
-
-            return SCSI_FAIL;
-        }
-
-        if (g_storageCallBack.CheckWPR(lun) != SCSI_OK)
-        {
-            SCSI_PutSenseCode(lun, SCSI_SKEY_NOT_READY,
-                              SCSI_ASC_WRITE_PROTECTED, 0);
-
-            return SCSI_FAIL;
-        }
-
-        s_blkAddr = ((uint32_t)command[2] << 24) | \
-                    ((uint32_t)command[3] << 16) | \
-                    ((uint32_t)command[4] << 8)  | \
-                     (uint32_t)command[5];
-
-        s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t )command[8]);
-
-        if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
-        {
-            return SCSI_FAIL;
-        }
-
-        s_blkAddr *= s_blkSize;
-        s_blkLen  *= s_blkSize;
-
-        if (g_BOTInfo.CBW.dDataXferLen != s_blkLen)
-        {
-            SCSI_PutSenseCode(g_BOTInfo.CBW.bLUN, SCSI_SKEY_ILLEGAL_REQUEST,
-                            SCSI_ASC_INVALID_CDB, 0);
-
-            return SCSI_FAIL;
-        }
-
-        g_BOTInfo.state = BOT_STATE_DATA_OUT;
-        len = USB_MIN(s_blkLen, MSC_MEDIA_PACKET);
-
-        USBD_RxData(MSC_OUT_EP & 0x7F, g_BOTInfo.data, len);
-
-    }
-    else
-    {
-        ret = SCSI_Write(lun);
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       SCSI Verify10 Handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Verify10(uint8_t lun, uint8_t* command)
-{
-    if (command[1] & 0x02)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
-                      SCSI_ASC_INVALID_FIELED_IN_COMMAND, 0);
-
-        return SCSI_FAIL;
-    }
-
-    s_blkAddr = ((uint32_t)command[2] << 24) | \
-                ((uint32_t)command[3] << 16) | \
-                ((uint32_t)command[4] << 8)  | \
-                 (uint32_t)command[5];
-
-    s_blkLen = ((uint16_t)command[7] << 8 | (uint8_t )command[8]);
-
-    if (SCSI_CheckAddress(lun, s_blkAddr, s_blkLen) != SCSI_OK)
-    {
-        return SCSI_FAIL;
-    }
-
-    g_BOTInfo.dataLen = 0;
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Start Stop Unit Handler.
- *
- * @param       None
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_StartStopUnit(void)
-{
-    g_BOTInfo.dataLen = 0;
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Mode Sense6 Handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ModeSense6(uint8_t lun, uint8_t* command)
-{
-    for (uint16_t i = 0; i < 8; i++)
-    {
-        g_BOTInfo.data[i] = s_modeSense6Data[i];
-    }
-
-    g_BOTInfo.dataLen = 8;
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Mode Sense10 Handler.
- *
- * @param       lun: Logical unit number
- *
- * @param       command: command pointer
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_ModeSense10(uint8_t lun, uint8_t* command)
-{
-    for (uint16_t i = 0; i < 8; i++)
-    {
-        g_BOTInfo.data[i] = s_modeSense10Data[i];
-    }
-
-    g_BOTInfo.dataLen = 8;
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Read Process.
- *
- * @param       lun: Logical unit number
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Read(uint8_t lun)
-{
-    uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
-
-    if (g_storageCallBack.ReadData(len, g_BOTInfo.data, (s_blkAddr / s_blkSize),
-                                  (len / s_blkSize)) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR,
-                        SCSI_ASC_UNRECOVERED_READ_ERROR, 0);
-
-        return SCSI_FAIL;
-    }
-
-    USBD_TxData(MSC_IN_EP & 0x7F, g_BOTInfo.data, len);
-
-    s_blkAddr += len;
-    s_blkLen  -= len;
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-
-    if (s_blkLen == 0)
-    {
-        g_BOTInfo.state = BOT_STATE_LAST_DATA_IN;
-    }
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Write Process.
- *
- * @param       lun: Logical unit number
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_Write(uint8_t lun)
-{
-    uint32_t len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
-
-    if (s_blkLen - len)
-    {
-        __NOP();
-    }
-    if (g_storageCallBack.WriteData(lun, g_BOTInfo.data, s_blkAddr / s_blkSize,
-                                    len / s_blkSize) != SCSI_OK)
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_HARDWARE_ERROR, SCSI_ASC_WRITE_FAULT, 0);
-
-        return SCSI_FAIL;
-    }
-
-    s_blkAddr += len;
-    s_blkLen  -= len;
-
-    g_BOTInfo.CSW.dDataResidue -= len;
-
-    if (s_blkLen)
-    {
-        len = USB_MIN(MSC_MEDIA_PACKET, s_blkLen);
-
-        USBD_RxData(MSC_OUT_EP & 0x7f, g_BOTInfo.data, len);
-    }
-    else
-    {
-        USBD_MSC_BOT_TxCSW(BOT_CSW_STATUS_CMD_OK);
-    }
-
-    return SCSI_OK;
-}
-
-/*!
- * @brief       SCSI Check Address Range.
- *
- * @param       lun: Logical unit number
- *
- * @param       blkOffset: first block address
- *
- * @param       blkNbr: number of block to be processed
- *
- * @retval      SCSI_OK or SCSI_FAILL
- */
-static uint8_t SCSI_CheckAddress(uint8_t lun, uint32_t blkOffset, uint16_t blkNbr)
-{
-    if (s_blkNbr < (blkNbr + blkOffset))
-    {
-        SCSI_PutSenseCode(lun, SCSI_SKEY_ILLEGAL_REQUEST,
-                          SCSI_ASC_ADDRESS_OUT_OF_RANGE, 0);
-
-        return SCSI_FAIL;
-    }
-
-    return SCSI_OK;
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_core.h

@@ -1,312 +0,0 @@
-/*!
- * @file        usbd_core.h
- *
- * @brief       USB protocol core handler head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_CORE_H_
-#define __USBD_CORE_H_
-
-#include "drv_usb_device.h"
-
-/** Get minimum value */
-#define USB_MIN(a, b)      (a >= b ? b : a)
-
-/** Get maximum value */
-#define USB_MAX(a, b)      (a >= b ? a : b)
-
-/**
- * @brief   USB request type
- */
-enum
-{
-    USBD_REQ_TYPE_STANDARD   = 0,
-    USBD_REQ_TYPE_CLASS      = 1,
-    USBD_REQ_TYPE_VENDOR     = 2,
-    USBD_REQ_TYPE_RESERVED   = 3
-};
-
-/**
- * @brief   USB recipient
- */
-enum
-{
-    USBD_RECIPIENT_DEVICE    = 0,
-    USBD_RECIPIENT_INTERFACE = 1,
-    USBD_RECIPIENT_ENDPOINT  = 2,
-    USBD_RECIPIENT_OTHER     = 3,
-};
-
-/**
- * @brief   USB standard device requests
- */
-enum
-{
-    USBD_GET_STATUS          = 0,
-    USBD_CLEAR_FEATURE       = 1,
-    USBD_SET_FEATURE         = 3,
-    USBD_SET_ADDRESS         = 5,
-    USBD_GET_DESCRIPTOR      = 6,
-    USBD_SET_DESCRIPTOR      = 7,
-    USBD_GET_CONFIGURATION   = 8,
-    USBD_SET_CONFIGURATION   = 9,
-    USBD_GET_INTERFACE       = 10,
-    USBD_SET_INTERFACE       = 11,
-    USBD_SYNCH_FRAME         = 12,
-};
-
-/**
- * @brief   USB descriptor types
- */
-enum
-{
-    USBD_DESC_DEVICE             = 1,
-    USBD_DESC_CONFIGURATION      = 2,
-    USBD_DESC_STRING             = 3,
-    USBD_DESC_INTERFACE          = 4,
-    USBD_DESC_ENDPOINT           = 5,
-    USBD_DESC_DEVICE_QUALIFIER   = 6,
-    USBD_DESC_OTHER_SPEED        = 7,
-    USBD_INTERFACE_POWER         = 8,
-};
-
-/**
- * @brief   USB standard feature
- */
-enum
-{
-    USBD_FEATURE_ENDPOINT_HALT   = 0,
-    USBD_FEATURE_REMOTE_WAKEUP   = 1,
-    USBD_FEATURE_TEST_MODE       = 2
-};
-
-/**
- * @brief   USB internal state machine
- */
-typedef enum
-{
-    USBD_CTRL_STATE_WAIT_SETUP,
-    USBD_CTRL_STATE_DATA_IN,
-    USBD_CTRL_STATE_DATA_OUT,
-    USBD_CTRL_STATE_WAIT_STATUS_IN,
-    USBD_CTRL_STATE_WAIT_STATUS_OUT,
-    USBD_CTRL_STATE_STALLED,
-}USBD_CTRL_STATE_T;
-
-/**
- * @brief   USBD Endpoint type for USB protocol
- */
-typedef enum
-{
-    USBD_EP_TYPE_CONTROL,
-    USBD_EP_TYPE_ISO,
-    USBD_EP_TYPE_BULK,
-    USBD_EP_TYPE_INTERRUPT
-}USBD_EP_TYPE_T;
-
-/**
- * @brief   USB request type
- */
-typedef union
-{
-    uint8_t byte;
-
-    struct
-    {
-        uint8_t recipient       : 5;
-        uint8_t type            : 2;
-        uint8_t dir             : 1;
-    }bit;
-}USBD_REQ_TYPE_T;
-
-/**
- * @brief   USB device request data
- */
-typedef struct
-{
-    union
-    {
-        uint8_t pack[8];
-
-        struct
-        {
-            USBD_REQ_TYPE_T bmRequestType;
-            uint8_t         bRequest;
-            uint8_t         wValue[2];
-            uint8_t         wIndex[2];
-            uint8_t         wLength[2];
-        } byte;
-    };
-} USBD_DevReqData_T;
-
-/**
- * @brief   Descriptor structure
- */
-typedef struct
-{
-    const uint8_t *pDesc;
-    uint8_t size;
-}USBD_Descriptor_T;
-
-/** USB standard request callback handler */
-typedef void (*USBD_StdReqHandler_T)(void);
-
-/** USB request handler */
-typedef void (*USBD_ReqHandler_T)(USBD_DevReqData_T *);
-
-/** Ctrl Tx Status handler function define */
-typedef void (*USBD_CtrlTxStatusHandler_T)(void);
-
-/** Ctrl Rx Status handler function define */
-typedef void (*USBD_CtrlRxStatusHandler_T)(void);
-
-/** Endpoint handler */
-typedef void (*USBD_EPHandler_T)(uint8_t ep);
-
-/** Reset handler */
-typedef void (*USBD_ResetHandler_T)(void);
-
-/** Interrupt handler function define */
-typedef void (*USBD_InterruptHandler_T)(void);
-
-/**
- * @brief   USB Class Request handler
- */
-typedef struct
-{
-    USBD_StdReqHandler_T getConfigurationHandler;
-    USBD_StdReqHandler_T getDescriptorHandler;
-    USBD_StdReqHandler_T getInterfaceHandler;
-    USBD_StdReqHandler_T getStatusHandler;
-    USBD_StdReqHandler_T setAddressHandler;
-
-    USBD_StdReqHandler_T setConfigurationHandler;
-    USBD_StdReqHandler_T setDescriptorHandler;
-    USBD_StdReqHandler_T setFeatureHandler;
-    USBD_StdReqHandler_T setInterfaceHandler;
-    USBD_StdReqHandler_T clearFeatureHandler;
-} USBD_StdReqCallback_T;
-
-/**
- * @brief   Control transfer buffer
- */
-typedef struct
-{
-    uint8_t *pBuf;         //!< Data buffer
-    uint32_t bufLen;       //!< Length of the data buffer
-    uint8_t  packNum;      //!< Packet number of the data
-    uint8_t  zeroPackFill; //!< Fill a zero pack for IN transfer or not
-    uint16_t maxPackSize;  //!< Max pack size of this endpoint
-    uint32_t xferCnt;      //!< Data count of one pack on from tansfer
-} USBD_CtrlBuf_T;
-
-/**
- * @brief   USB init parameter
- */
-typedef struct
-{
-    USBD_Descriptor_T *pDeviceDesc;              //!< Device descriptor pointer
-    USBD_Descriptor_T *pConfigurationDesc;       //!< Configuration descriptor pointer
-    USBD_Descriptor_T *pStringDesc;              //!< String descriptor pointer
-    USBD_Descriptor_T *pQualifierDesc;           //!< Device Qualifier descriptor pointer
-    USBD_Descriptor_T *pHidReportDesc;           //!< HID report descriptor pointer
-
-
-    USBD_StdReqCallback_T *pStdReqCallback;
-    USBD_ReqHandler_T stdReqExceptionHandler;    //!< Standard request exception handler
-    USBD_ReqHandler_T classReqHandler;           //!< Class request handler
-    USBD_ReqHandler_T vendorReqHandler;          //!< vendor request handler
-
-    USBD_CtrlTxStatusHandler_T txStatusHandler;  //!< Send IN status early handler
-    USBD_CtrlRxStatusHandler_T rxStatusHandler;  //!< Receive OUT status early handler
-
-    USBD_EPHandler_T    outEpHandler;            //!< OUT EP transfer done handler except EP0
-    USBD_EPHandler_T    inEpHandler;             //!< IN EP transfer done handler except EP0
-    USBD_ResetHandler_T resetHandler;            //!< Reset handler
-    USBD_InterruptHandler_T intHandler;          //!< Hadler the rest of interrupt.
-} USBD_InitParam_T;
-
-/**
- * @brief   USB infomation
- */
-typedef struct
-{
-    USBD_CTRL_STATE_T ctrlState;
-
-    uint8_t curFeature;
-    uint8_t curInterface;
-    uint8_t curAlternateSetting;
-    uint8_t curConfiguration;
-    uint8_t configurationNum;
-
-    /** Setup request data buffer */
-    USBD_DevReqData_T reqData;
-
-    /** Endpoint buffer management */
-    USBD_CtrlBuf_T inBuf[USB_EP_MAX_NUM];
-    USBD_CtrlBuf_T outBuf[USB_EP_MAX_NUM];
-
-    /** Descriptor pointer */
-    USBD_Descriptor_T *pDeviceDesc;
-    USBD_Descriptor_T *pConfigurationDesc;
-    USBD_Descriptor_T *pStringDesc;
-    USBD_Descriptor_T *pQualifierDesc;
-    USBD_Descriptor_T *pHidReportDesc;
-
-    /** Setup request callback handler */
-    USBD_StdReqCallback_T *pStdReqCallback;
-    USBD_ReqHandler_T     stdReqExceptionHandler;
-    USBD_ReqHandler_T     classReqHandler;
-    USBD_ReqHandler_T     vendorReqHandler;
-
-    /** Control transfer status stage handler */
-    USBD_CtrlTxStatusHandler_T txStatusHandler;
-    USBD_CtrlRxStatusHandler_T rxStatusHandler;
-
-    /** Endpoint transfer done handler */
-    USBD_EPHandler_T      outEpHandler;
-    USBD_EPHandler_T      inEpHandler;
-
-    USBD_ResetHandler_T   resetHandler;
-    USBD_InterruptHandler_T intHandler;
-} USBD_Info_T;
-
-extern USBD_Info_T g_usbDev;
-
-/** control status function */
-#define USBD_CtrlTxStatus()         USBD_CtrlInData(NULL, 0);
-#define USBD_CtrlRxStatus()         USBD_CtrlOutData(NULL, 0)
-
-/** Handler Endpoint 0 control transfer */
-void USBD_SetupProcess(void);
-void USBD_CtrlInProcess(void);
-void USBD_CtrlOutProcess(void);
-void USBD_CtrlOutData(uint8_t *buf, uint32_t len);
-void USBD_CtrlInData(uint8_t *buf, uint32_t len);
-
-/** Handler other Endpoint data transfer */
-void USBD_DataInProcess(USBD_EP_T ep);
-void USBD_DataOutProcess(USBD_EP_T ep);
-void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len);
-void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_init.h

@@ -1,64 +0,0 @@
-/*!
- * @file        usbd_init.h
- *
- * @brief       USB initialization management head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef USBD_INIT_H_
-#define USBD_INIT_H_
-
-#include "usbd_core.h"
-
-/**
- * @brief   Endpoint Configuration Info
- */
-typedef struct
-{
-    USBD_EP_T      epNum;      //!< endpoint number
-    USBD_EP_TYPE_T epType;     //!< endpoint type
-    uint8_t        epKind;     /**
-                                * Which could be ENABLE or DISABLE, it is valid only for
-                                * control and bulk Endpoint. The mean of ENABLE for them like :
-                                * 1. Control endpoint : Only for OUT status which is zero data.
-                                * 2. Bulk endpoint : Enable the double-buffer feature
-                               */
-    USBD_EP_STATUS_T epStatus; //!< Endpoint status
-    uint16_t epBufAddr;        //!< buffer address for the endpoint
-    uint16_t maxPackSize;      //!< max packet size for the endpoint
-} USBD_EPConfig_T;
-
-/** USB init */
-void USBD_Init(USBD_InitParam_T *param);
-void USBD_InitParamStructInit(USBD_InitParam_T *param);
-
-/** power */
-void USBD_PowerOn(void);
-void USBD_PowerOff(void);
-
-/** Endpoint init */
-void USBD_OpenOutEP(USBD_EPConfig_T *epConfig);
-void USBD_OpenInEP(USBD_EPConfig_T *epConfig);
-
-void USBD_CloseOutEP(USBD_EP_T ep);
-void USBD_CloseInEP(USBD_EP_T ep);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_interrupt.h

@@ -1,31 +0,0 @@
-/*!
- * @file        usbd_interrupt.h
- *
- * @brief       USB interrupt service routine header file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_INTERRUPT_H_
-#define __USBD_INTERRUPT_H_
-
-#include "apm32f10x.h"
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/inc/usbd_stdReq.h

@@ -1,31 +0,0 @@
-/*!
- * @file        usbd_stdReq.h
- *
- * @brief       USB standard request process head file
- *
- * @version     V1.0.0
- *
- * @date        2021-12-30
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __USBD_STDREQ_H_
-#define __USBD_STDREQ_H_
-
-void USBD_StandardReqeust(void);
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_core.c

@@ -1,405 +0,0 @@
-/*!
- * @file        usbd_core.c
- *
- * @brief       USB protocol core handler
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_core.h"
-#include "usbd_stdReq.h"
-
-/** USB information */
-USBD_Info_T g_usbDev;
-
-/*!
- * @brief       Endpoint 0 Setup process
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_SetupProcess(void)
-{
-    uint8_t reqType;
-    uint8_t dataBuf[8];
-    USBD_DevReqData_T *pReqData = &g_usbDev.reqData;
-    uint16_t xferLen = USBD_ReadEPRxCnt(USBD_EP_0);
-
-    if (xferLen)
-    {
-        USBD_ReadDataFromEP(USBD_EP_0, (uint8_t *)dataBuf, xferLen);
-    }
-    else
-    {
-        return;
-    }
-
-    pReqData->byte.bmRequestType.byte = dataBuf[0];
-    pReqData->byte.bRequest = dataBuf[1];
-    pReqData->byte.wValue[0] = dataBuf[2];
-    pReqData->byte.wValue[1] = dataBuf[3];
-    pReqData->byte.wIndex[0] = dataBuf[4];
-    pReqData->byte.wIndex[1] = dataBuf[5];
-    pReqData->byte.wLength[0] = dataBuf[6];
-    pReqData->byte.wLength[1] = dataBuf[7];
-
-    reqType = pReqData->byte.bmRequestType.bit.type;
-
-    if(reqType == USBD_REQ_TYPE_STANDARD)
-    {
-        USBD_StandardReqeust();
-    }
-    else if(reqType == USBD_REQ_TYPE_CLASS)
-    {
-        if(g_usbDev.classReqHandler)
-        {
-            g_usbDev.classReqHandler(pReqData);
-        }
-    }
-    else if(reqType == USBD_REQ_TYPE_VENDOR)
-    {
-        if(g_usbDev.vendorReqHandler)
-        {
-            g_usbDev.vendorReqHandler(pReqData);
-        }
-    }
-    else
-    {
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-    }
-}
-
-
-/*!
- * @brief       Endpoint 0 USB Control in process
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_CtrlInProcess(void)
-{
-    uint32_t tmp;
-
-    if(g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_IN)
-    {
-        if(g_usbDev.inBuf[0].packNum)
-        {
-            tmp = USB_MIN(g_usbDev.inBuf[0].bufLen, g_usbDev.inBuf[0].maxPackSize);
-
-            USBD_WriteDataToEP(USBD_EP_0, g_usbDev.inBuf[0].pBuf, tmp);
-            USBD_SetEPTxCnt(USBD_EP_0, tmp);
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
-
-            g_usbDev.inBuf[0].pBuf += tmp;
-            g_usbDev.inBuf[0].bufLen -= tmp;
-            g_usbDev.inBuf[0].packNum--;
-        }
-        else
-        {
-            if (g_usbDev.inBuf[USBD_EP_0].zeroPackFill)
-            {
-                USBD_SetEPTxCnt(USBD_EP_0, 0);
-                USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID);
-                g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 0;
-            }
-            else
-            {
-                if (g_usbDev.rxStatusHandler)
-                {
-                    g_usbDev.rxStatusHandler();
-                }
-
-                g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT;
-                USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
-            }
-
-        }
-    }
-    else if(g_usbDev.ctrlState == USBD_CTRL_STATE_WAIT_STATUS_IN)
-    {
-        if(g_usbDev.reqData.byte.bRequest == USBD_SET_ADDRESS)
-        {
-            USBD_SetDeviceAddr(g_usbDev.reqData.byte.wValue[0]);
-        }
-    }
-}
-
-/*!
- * @brief       Endpoint 0 USB Control out process
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_CtrlOutProcess(void)
-{
-    uint32_t len;
-
-    if(g_usbDev.ctrlState == USBD_CTRL_STATE_DATA_OUT)
-    {
-        if(g_usbDev.outBuf[0].packNum)
-        {
-            len = USB_MIN(g_usbDev.outBuf[0].bufLen, g_usbDev.outBuf[0].maxPackSize);
-
-            USBD_ReadDataFromEP(USBD_EP_0, g_usbDev.outBuf[0].pBuf, len);
-
-            g_usbDev.outBuf[0].bufLen -= len;
-            g_usbDev.outBuf[0].pBuf += len;
-            g_usbDev.outBuf[0].packNum--;
-
-            if (g_usbDev.outBuf[0].packNum)
-            {
-                USBD_CtrlOutData(g_usbDev.outBuf[0].pBuf, g_usbDev.outBuf[0].bufLen);
-            }
-            else
-            {
-                USBD_CtrlTxStatus();
-            }
-        }
-        else
-        {
-            if (g_usbDev.txStatusHandler)
-            {
-                g_usbDev.txStatusHandler();
-            }
-
-            USBD_CtrlTxStatus();
-        }
-    }
-}
-
-/*!
- * @brief       Send data or status in control in transation
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_CtrlInData(uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.inBuf[0].maxPackSize;
-    uint16_t reqLen = *(uint16_t*)g_usbDev.reqData.byte.wLength;
-
-    if(len)
-    {
-        if ((len < reqLen) && ((len % maxPackSize) == 0))
-        {
-            g_usbDev.inBuf[USBD_EP_0].zeroPackFill = 1;
-        }
-
-        if(len >= g_usbDev.inBuf[0].maxPackSize)
-        {
-            /** Send a packet */
-            USBD_WriteDataToEP(USBD_EP_0, buf, g_usbDev.inBuf[0].maxPackSize);
-            USBD_SetEPTxCnt(USBD_EP_0, g_usbDev.inBuf[0].maxPackSize);
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
-
-            /** deal with buffer */
-            g_usbDev.inBuf[0].bufLen = len - g_usbDev.inBuf[0].maxPackSize;
-            g_usbDev.inBuf[0].pBuf = buf + g_usbDev.inBuf[0].maxPackSize;
-            g_usbDev.inBuf[0].packNum = (g_usbDev.inBuf[0].bufLen + (maxPackSize - 1)) / maxPackSize;
-
-            g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_IN;
-        }
-        else
-        {
-            USBD_WriteDataToEP(USBD_EP_0, buf, len);
-            USBD_SetEPTxCnt(USBD_EP_0, len);
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_VALID, USBD_EP_STATUS_NAK);
-
-            g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \
-                                                     USBD_CTRL_STATE_DATA_IN : \
-                                                     USBD_CTRL_STATE_WAIT_STATUS_IN;
-        }
-    }
-    else
-    {
-        USBD_SetEPTxCnt(USBD_EP_0, 0);
-        USBD_SetEPTxStatus(USBD_EP_0, USBD_EP_STATUS_VALID);
-
-        g_usbDev.ctrlState = g_usbDev.reqData.byte.bmRequestType.bit.dir ? \
-                                                 USBD_CTRL_STATE_DATA_IN : \
-                                                 USBD_CTRL_STATE_WAIT_STATUS_IN;
-    }
-}
-
-/*!
- * @brief       Read data or status in control out transation
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_CtrlOutData(uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize;
-
-    if (len)
-    {
-        g_usbDev.outBuf[USBD_EP_0].pBuf = buf;
-        g_usbDev.outBuf[USBD_EP_0].bufLen = len;
-        g_usbDev.outBuf[USBD_EP_0].packNum = (len + (maxPackSize - 1)) / maxPackSize;
-
-        len = USB_MIN(g_usbDev.outBuf[0].bufLen, maxPackSize);
-
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
-
-        g_usbDev.ctrlState = USBD_CTRL_STATE_DATA_OUT;
-    }
-    else
-    {
-        g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_STATUS_OUT;
-    }
-
-    USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_VALID);
-}
-
-/*!
- * @brief       USB Data in process except endpoint 0
- *
- * @param       ep : endpoint Number except endpoint 0
- *
- * @retval      None
- */
-void USBD_DataInProcess(USBD_EP_T ep)
-{
-    uint16_t len;
-
-    if (g_usbDev.inBuf[ep].packNum)
-    {
-        len = g_usbDev.inBuf[ep].bufLen > g_usbDev.inBuf[ep].maxPackSize ? \
-              g_usbDev.inBuf[ep].maxPackSize : g_usbDev.inBuf[ep].bufLen;
-
-
-        USBD_WriteDataToEP(ep, g_usbDev.inBuf[ep].pBuf, len);
-        USBD_SetEPTxCnt(ep, len);
-        USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
-
-        g_usbDev.inBuf[ep].pBuf += len;
-        g_usbDev.inBuf[ep].bufLen -= len;
-        g_usbDev.inBuf[ep].packNum--;
-    }
-    else
-    {
-        if(g_usbDev.inEpHandler)
-        {
-            g_usbDev.inEpHandler(ep);
-        }
-    }
-}
-
-/*!
- * @brief       USB Data out process except endpoint 0
- *
- * @param       ep : endpoint Number except endpoint 0
- *
- * @retval      None
- */
-void USBD_DataOutProcess(USBD_EP_T ep)
-{
-    if (g_usbDev.outBuf[ep].packNum)
-    {
-            g_usbDev.outBuf[ep].xferCnt = USBD_ReadEPRxCnt(ep);
-
-            if ((g_usbDev.outBuf[ep].xferCnt != 0) && (g_usbDev.outBuf[ep].pBuf != NULL))
-            {
-                USBD_ReadDataFromEP(ep, g_usbDev.outBuf[ep].pBuf, g_usbDev.outBuf[ep].xferCnt);
-
-                g_usbDev.outBuf[ep].bufLen -= g_usbDev.outBuf[ep].xferCnt;
-                g_usbDev.outBuf[ep].pBuf += g_usbDev.outBuf[ep].xferCnt;
-                g_usbDev.outBuf[ep].packNum--;
-            }
-            if (g_usbDev.outBuf[ep].packNum)
-            {
-                USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID);
-            }
-    }
-
-    if(g_usbDev.outEpHandler && !g_usbDev.outBuf[ep].packNum)
-    {
-        g_usbDev.outEpHandler(ep);
-    }
-}
-
-/*!
- * @brief       Transfer data to host(except endpoint 0)
- *
- * @param       ep:     Endpoint number except endpoint 0
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_TxData(uint8_t ep, uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.inBuf[ep].maxPackSize;
-
-    if (len >= maxPackSize)
-    {
-        USBD_WriteDataToEP(ep, buf, maxPackSize);
-        USBD_SetEPTxCnt(ep, maxPackSize);
-        USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
-
-        g_usbDev.inBuf[ep].pBuf = buf + maxPackSize;
-        g_usbDev.inBuf[ep].bufLen = len - maxPackSize;
-        g_usbDev.inBuf[ep].packNum =(g_usbDev.inBuf[ep].bufLen + (maxPackSize - 1)) / maxPackSize;
-    }
-    else
-    {
-        USBD_WriteDataToEP(ep, buf, len);
-        USBD_SetEPTxCnt(ep, len);
-        USBD_SetEPTxStatus(ep, USBD_EP_STATUS_VALID);
-
-        g_usbDev.inBuf[ep].packNum = 0;
-        g_usbDev.inBuf[ep].bufLen = 0;
-    }
-}
-
-/*!
- * @brief       Receive data from host(except endpoint 0)
- *
- * @param       ep:     Endpoint number except endpoint 0
- *
- * @param       buf:    Buffer pointer
- *
- * @param       len:    Buffer length
- *
- * @retval      None
- */
-void USBD_RxData(uint8_t ep, uint8_t *buf, uint32_t len)
-{
-    uint16_t maxPackSize = g_usbDev.outBuf[ep].maxPackSize;
-
-    g_usbDev.outBuf[ep].pBuf = buf;
-    g_usbDev.outBuf[ep].bufLen = len;
-    g_usbDev.outBuf[ep].packNum = (len + (maxPackSize - 1)) / maxPackSize;
-
-    USBD_SetEPRxCnt(ep, USB_MIN(len, maxPackSize));
-
-    USBD_SetEPRxStatus(ep, USBD_EP_STATUS_VALID);
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_init.c

@@ -1,237 +0,0 @@
-/*!
- * @file        usbd_init.c
- *
- * @brief       USB initialization management
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_init.h"
-#include "usb_bsp.h"
-
-static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType);
-
-/*!
- * @brief       USB initialization
- *
- * @param       param: Initialization parameter
- *
- * @retval      None
- */
-void USBD_Init(USBD_InitParam_T *param)
-{
-    g_usbDev.pDeviceDesc = param->pDeviceDesc;
-    g_usbDev.pConfigurationDesc = param->pConfigurationDesc;
-    g_usbDev.pStringDesc = param->pStringDesc;
-    g_usbDev.pQualifierDesc = param->pQualifierDesc;
-    g_usbDev.pHidReportDesc = param->pHidReportDesc;
-
-    g_usbDev.pStdReqCallback = param->pStdReqCallback;
-    g_usbDev.classReqHandler = param->classReqHandler;
-    g_usbDev.vendorReqHandler = param->vendorReqHandler;
-    g_usbDev.stdReqExceptionHandler = param->stdReqExceptionHandler;
-
-    g_usbDev.txStatusHandler = param->txStatusHandler;
-    g_usbDev.rxStatusHandler = param->rxStatusHandler;
-
-    g_usbDev.inEpHandler = param->inEpHandler;
-    g_usbDev.outEpHandler = param->outEpHandler;
-
-    g_usbDev.resetHandler = param->resetHandler;
-    g_usbDev.intHandler = param->intHandler;
-
-    USBD_HardWareInit();
-
-#ifndef APM32F0xx_USB
-#if USB_SELECT == USB1
-    USBD2_Disable();
-#else
-    USB2_Enable();
-#endif
-#endif
-
-    USBD_PowerOn();
-}
-
-/*!
- * @brief       Init parameter in param
- *
- * @param       param: Initialization parameter
- *
- * @retval      None
- */
-void USBD_InitParamStructInit(USBD_InitParam_T *param)
-{
-    param->pStdReqCallback = NULL;
-    param->stdReqExceptionHandler = NULL;
-    param->classReqHandler = NULL;
-    param->vendorReqHandler = NULL;
-
-    param->txStatusHandler = NULL;
-    param->rxStatusHandler = NULL;
-
-    param->outEpHandler = NULL;
-    param->inEpHandler = NULL;
-
-    param->resetHandler = NULL;
-    param->intHandler = NULL;
-}
-
-/*!
- * @brief       USB Power on
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_PowerOn(void)
-{
-    USBD_ResetPowerDown();
-
-    USBD_SetForceReset();
-    USBD_ResetForceReset();
-
-    USBD_DisableInterrupt(USBD_INT_ALL);
-    USBD_ClearIntFlag(USBD_INT_ALL);
-
-    USBD_EnableInterrupt(USB_INT_SOURCE);
-}
-
-/*!
- * @brief       USB Power off
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_PowerOff(void)
-{
-    USBD_DisableInterrupt(USBD_INT_ALL);
-    USBD_ClearIntFlag(USBD_INT_ALL);
-
-    /** Power down and Force USB Reset */
-    USBD_SetRegCTRL(0X03);
-}
-
-
-/*!
- * @brief       Open OUT endpoint.
- *
- * @param       epConfig: Point to USBD_EPConfig_T structure
- *
- * @retval      None
- */
-void USBD_OpenOutEP(USBD_EPConfig_T *epConfig)
-{
-    g_usbDev.outBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize;
-
-    USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType));
-
-    if (epConfig->epKind)
-    {
-        USBD_SetEPKind(epConfig->epNum);
-    }
-    else
-    {
-        USBD_ResetEPKind(epConfig->epNum);
-    }
-
-    USBD_SetEPRxAddr(epConfig->epNum, epConfig->epBufAddr);
-    USBD_SetEPRxCnt(epConfig->epNum, epConfig->maxPackSize);
-    USBD_SetEPRxStatus(epConfig->epNum, epConfig->epStatus);
-}
-
-/*!
- * @brief       Open IN endpoint.
- *
- * @param       epConfig: Point to USBD_EPConfig_T structure
- *
- * @retval      None
- */
-void USBD_OpenInEP(USBD_EPConfig_T *epConfig)
-{
-    g_usbDev.inBuf[epConfig->epNum].maxPackSize = epConfig->maxPackSize;
-
-    USBD_SetEPType(epConfig->epNum, USBD_ConvertEPType(epConfig->epType));
-
-    if (epConfig->epKind)
-    {
-        USBD_SetEPKind(epConfig->epNum);
-    }
-    else
-    {
-        USBD_ResetEPKind(epConfig->epNum);
-    }
-
-    USBD_SetEPTxAddr(epConfig->epNum, epConfig->epBufAddr);
-    USBD_SetEPTxStatus(epConfig->epNum, epConfig->epStatus);
-}
-
-/*!
- * @brief       Close OUT endpoint.
- *
- * @param       ep: OUT endpoint Number
- *
- * @retval      None
- */
-void USBD_CloseOutEP(USBD_EP_T ep)
-{
-    g_usbDev.outBuf[ep].maxPackSize = 0;
-
-    USBD_SetEPRxStatus(ep, USBD_EP_STATUS_DISABLE);
-}
-
-/*!
- * @brief       Close IN endpoint.
- *
- * @param       ep: IN endpoint Number
- *
- * @retval      None
- */
-void USBD_CloseInEP(USBD_EP_T ep)
-{
-    g_usbDev.inBuf[ep].maxPackSize = 0;
-
-    USBD_SetEPTxStatus(ep, USBD_EP_STATUS_DISABLE);
-}
-
-/*!
- * @brief       Convert endpoint Type.
- *
- * @param       epType: endpoint type
- *
- * @retval      Value of USBD_REG_EP_TYPE_T
- */
-static USBD_REG_EP_TYPE_T USBD_ConvertEPType(USBD_EP_TYPE_T epType)
-{
-    switch (epType)
-    {
-        case USBD_EP_TYPE_CONTROL :
-            return USBD_REG_EP_TYPE_CONTROL;
-        case USBD_EP_TYPE_ISO :
-            return USBD_REG_EP_TYPE_ISO;
-        case USBD_EP_TYPE_BULK :
-            return USBD_REG_EP_TYPE_BULK;
-        case USBD_EP_TYPE_INTERRUPT :
-            return USBD_REG_EP_TYPE_INTERRUPT;
-        default :
-            return USBD_REG_EP_TYPE_CONTROL;
-    }
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_interrupt.c

@@ -1,349 +0,0 @@
-/*!
- * @file        usbd_interrupt.c
- *
- * @brief       USB interrupt service routine
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_init.h"
-
-static void USBD_LowPriorityProc(void);
-
-static void USBD_ResetIsrHandler(void);
-static void USBD_SuspendIsrHandler(void);
-static void USBD_ResumeIsrHandler(void);
-
-/*!
- * @brief       USB interrupt service routine
- *
- * @param       None
- *
- * @retval      None
- */
-#ifdef APM32F0xx_USB
-void USB_IRQHandler(void)
-
-#else //!< APM32F10x_USB
-#if USB_SELECT == USB1
-void USBD1_LP_CAN1_RX0_IRQHandler(void)
-#else
-void USB2_LP_IRQHandler(void)
-#endif
-#endif
-{
-#if (USB_INT_SOURCE & USBD_INT_CTR)
-    if(USBD_ReadIntFlag(USBD_INT_CTR))
-    {
-        USBD_LowPriorityProc();
-    }
-#endif
-
-#if (USB_INT_SOURCE & USBD_INT_RST)
-    if(USBD_ReadIntFlag(USBD_INT_RST))
-    {
-        USBD_ClearIntFlag(USBD_INT_RST);
-        USBD_ResetIsrHandler();
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_PMAOU
-    if(USB_ReadIntFlag(USB_INT_PMAOU))
-    {
-        USB_ClearIntFlag(USB_INT_PMAOU);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_ERR
-
-    if(USB_ReadIntFlag(USB_INT_ERROR))
-    {
-        USB_ClearIntFlag(USB_INT_ERROR);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_WKUP
-    if(USBD_ReadIntFlag(USBD_INT_WKUP))
-    {
-        USBD_ResumeIsrHandler();
-        USBD_ClearIntFlag(USBD_INT_WKUP);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_SUS
-    if(USBD_ReadIntFlag(USBD_INT_SUS))
-    {
-        USBD_SuspendIsrHandler();
-        USBD_ClearIntFlag(USBD_INT_SUS);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_SOF
-    if(USB_ReadIntFlag(USB_INT_SOF))
-    {
-        USB_ClearIntFlag(USB_INT_SOF);
-    }
-#endif
-
-#if USB_INT_SOURCE & USBD_INT_ESOF
-    if(USB_ReadIntFlag(USB_INT_ESOF))
-    {
-        USB_ClearIntFlag(USB_INT_ESOF);
-    }
-#endif
-}
-
-/*!
- * @brief       USB low priority process
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_LowPriorityProc(void)
-{
-    USBD_EP_T ep;
-
-    while(USBD_ReadIntFlag(USBD_INT_CTR))
-    {
-        ep = (USBD_EP_T)USBD_ReadEP();
-
-        /** Endpoint 0 */
-        if(ep == 0)
-        {
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_NAK, USBD_EP_STATUS_NAK);
-
-            /** Control in */
-            if(USBD_ReadDir() == 0)
-            {
-                USBD_ResetEPTxFlag(USBD_EP_0);
-                USBD_CtrlInProcess();
-            }
-            else
-            {
-                /** Setup */
-                if(USBD_ReadEPSetup(USBD_EP_0) == SET)
-                {
-                    USBD_ResetEPRxFlag(USBD_EP_0);
-                    USBD_SetupProcess();
-                }
-                /** Control out */
-                else
-                {
-                    USBD_ResetEPRxFlag(USBD_EP_0);
-                    USBD_CtrlOutProcess();
-                }
-            }
-        }
-        /** Transfer Handler Except endpoint 0 */
-        else
-        {
-            if (USBD_ReadEPRxFlag(ep))
-            {
-                USBD_ResetEPRxFlag(ep);
-                USBD_DataOutProcess(ep);
-            }
-
-            if (USBD_ReadEPTxFlag(ep))
-            {
-                USBD_ResetEPTxFlag(ep);
-                USBD_DataInProcess(ep);
-            }
-        }
-    }
-}
-
-
-/*!
- * @brief      USB Device Reset
- *
- * @param      None
- *
- * @retval     None
- */
-static void USBD_ResetIsrHandler(void)
-{
-    uint8_t i;
-    USBD_EPConfig_T epConfig;
-
-    g_usbDev.configurationNum = USB_CONFIGURATION_NUM;
-    g_usbDev.curConfiguration = 0;
-    g_usbDev.curInterface = 0;
-    g_usbDev.curAlternateSetting = 0;
-    g_usbDev.curFeature = 0;
-    g_usbDev.ctrlState = USBD_CTRL_STATE_WAIT_SETUP;
-
-    g_usbDev.inBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE;
-    g_usbDev.outBuf[USBD_EP_0].maxPackSize = USB_EP0_PACKET_SIZE;
-
-    USBD_SetBufferTable(USB_BUFFER_TABLE_ADDR);
-
-    /** Endpoint 0 IN */
-    epConfig.epNum = USBD_EP_0;
-    epConfig.epType = USBD_EP_TYPE_CONTROL;
-    epConfig.epKind = DISABLE;
-    epConfig.epBufAddr = USB_EP0_TX_ADDR;
-    epConfig.maxPackSize = g_usbDev.inBuf[USBD_EP_0].maxPackSize;
-    epConfig.epStatus = USBD_EP_STATUS_NAK;
-    USBD_OpenInEP(&epConfig);
-
-    /** Endpoint 0 OUT */
-    epConfig.epBufAddr = USB_EP0_RX_ADDR;
-    epConfig.maxPackSize = g_usbDev.outBuf[USBD_EP_0].maxPackSize;
-    epConfig.epStatus = USBD_EP_STATUS_VALID;
-    USBD_OpenOutEP(&epConfig);
-
-    if(g_usbDev.resetHandler)
-    {
-        g_usbDev.resetHandler();
-    }
-
-    for(i = 0; i < USB_EP_MAX_NUM; i++)
-    {
-        USBD_SetEpAddr((USBD_EP_T)i, i);
-    }
-
-    USBD_SetDeviceAddr(0);
-    USBD_Enable();
-}
-
-/*!
- * @brief       USB Suspend
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_SuspendIsrHandler(void)
-{
-    uint8_t i;
-    uint16_t bakEP[8];
-#if USB_LOW_POWER_SWITCH
-    uint32_t bakPwrCR;
-    uint32_t tmp;
-#endif
-
-    for(i = 0; i < 8; i++)
-    {
-        bakEP[i] = (uint16_t)USBD->EP[i].EP;
-    }
-
-    USBD_EnableInterrupt(USBD_INT_RST);
-
-    USBD_SetForceReset();
-    USBD_ResetForceReset();
-
-    while(USBD_ReadIntFlag(USBD_INT_RST) == RESET);
-
-    for(i = 0; i < 8; i++)
-    {
-        USBD->EP[i].EP = bakEP[i];
-    }
-
-    USBD_SetForceSuspend();
-
-#if USB_LOW_POWER_SWITCH
-    USBD_SetLowerPowerMode();
-
-    bakPwrCR = PMU->CTRL;
-    tmp = PMU->CTRL;
-    tmp &= (uint32_t)0xfffffffc;
-    tmp |= PMU_REGULATOR_LOWPOWER;
-    PMU->CTRL = tmp;
-
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-    if(USBD_ReadIntFlag(USBD_INT_WKUP) == RESET)
-    {
-        __WFI();
-        SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-    }
-    else
-    {
-        USBD_ClearIntFlag(USBD_INT_WKUP);
-        USBD_ResetForceSuspend();
-        PMU->CTRL = bakPwrCR;
-        SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-    }
-#endif
-}
-
-/*!
- * @brief       Resume
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_ResumeIsrHandler(void)
-{
-#if USB_LOW_POWER_SWITCH
-    USBD_ResetLowerPowerMode();
-#endif
-
-    SystemInit();
-
-    USBD_SetRegCTRL(USB_INT_SOURCE);
-}
-
-#ifndef APM32F0xx_USB
-/*!
- * @brief       USB High priority process
- *
- * @param       None
- *
- * @retval      None
- */
-static void USBD_HighPriorityProc(void)
-{
-    USBD_EP_T ep;
-
-    while(USBD_ReadIntFlag(USBD_INT_CTR))
-    {
-        USBD_ClearIntFlag(USBD_INT_CTR);
-
-        ep = USBD_ReadEP();
-
-        if(USBD_ReadEPRxFlag(ep))
-        {
-            USBD_ResetEPRxFlag(ep);
-
-            g_usbDev.outEpHandler(ep);
-        }
-
-        if(USBD_ReadEPTxFlag(ep))
-        {
-            USBD_ResetEPTxFlag(ep);
-
-            g_usbDev.inEpHandler(ep);
-        }
-    }
-}
-
-#if USB_SELECT == USB1
-void USBD1_HP_CAN1_TX_IRQHandler(void)
-#else
-void USB2_HP_IRQHandler(void)
-#endif
-{
-    USBD_HighPriorityProc();
-}
-
-#endif

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Core_Device/Standard/src/usbd_stdReq.c

@@ -1,369 +0,0 @@
-/*!
- * @file        usbd_stdReq.c
- *
- * @brief       USB standard request process
- *
- * @version     V1.0.0
- *
- * @date        2021-12-30
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "usbd_stdReq.h"
-#include "usbd_core.h"
-#include "usbd_descriptor.h"
-
-static uint8_t USBD_StandardGetConfiguration(void);
-static uint8_t USBD_StandardGetDescriptor(void);
-static uint8_t USBD_StandardGetInterface(void);
-static uint8_t USBD_StandardGetStatus(void);
-
-static uint8_t USBD_StandardSetAddress(void);
-static uint8_t USBD_StandardSetConfiguration(void);
-static uint8_t USBD_StandardSetDescriptor(void);
-static uint8_t USBD_StandardSetFeature(void);
-static uint8_t USBD_StandardSetInterface(void);
-
-static uint8_t USBD_StandardClearFeature(void);
-
-
-/*!
- * @brief       USB request standard request
- *
- * @param       None
- *
- * @retval      None
- */
-void USBD_StandardReqeust(void)
-{
-    uint8_t result = 1;
-
-    uint8_t bRequest = g_usbDev.reqData.byte.bRequest;
-
-    switch(bRequest)
-    {
-        case USBD_GET_CONFIGURATION:
-            result = USBD_StandardGetConfiguration();
-        break;
-
-        case USBD_GET_DESCRIPTOR:
-            result = USBD_StandardGetDescriptor();
-        break;
-
-        case USBD_GET_INTERFACE:
-            result = USBD_StandardGetInterface();
-        break;
-
-        case USBD_GET_STATUS:
-            result = USBD_StandardGetStatus();
-        break;
-
-        case USBD_SET_ADDRESS:
-            result = USBD_StandardSetAddress();
-        break;
-
-        case USBD_SET_CONFIGURATION:
-            result = USBD_StandardSetConfiguration();
-        break;
-
-        case USBD_SET_DESCRIPTOR:
-            result = USBD_StandardSetDescriptor();
-        break;
-
-        case USBD_SET_FEATURE:
-            result = USBD_StandardSetFeature();
-        break;
-
-        case USBD_SET_INTERFACE:
-            result = USBD_StandardSetInterface();
-
-        break;
-
-        case USBD_CLEAR_FEATURE:
-            result = USBD_StandardClearFeature();
-        break;
-
-        default:
-
-            break;
-    }
-
-    if(!result)
-    {
-        if(g_usbDev.stdReqExceptionHandler != NULL)
-        {
-            g_usbDev.stdReqExceptionHandler(&g_usbDev.reqData);
-        }
-    }
-}
-
-/*!
- * @brief       Standard request get configuration
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardGetConfiguration(void)
-{
-    uint8_t recipient = g_usbDev.reqData.byte.bmRequestType.bit.recipient;
-
-    if(recipient == USBD_RECIPIENT_DEVICE)
-    {
-        USBD_CtrlInData(&g_usbDev.curConfiguration, 1);
-
-        if (g_usbDev.pStdReqCallback->getConfigurationHandler)
-        {
-            g_usbDev.pStdReqCallback->getConfigurationHandler();
-        }
-
-
-        return SUCCESS;
-    }
-
-    return ERROR;
-}
-
-/*!
- * @brief       Standard request get descriptor
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardGetDescriptor(void)
-{
-    uint8_t ret = SUCCESS;
-    uint32_t len = 0;
-    uint8_t wValue0 = g_usbDev.reqData.byte.wValue[0];
-    uint8_t wValue1 = g_usbDev.reqData.byte.wValue[1];
-
-    if(wValue1 == USBD_DESC_DEVICE)
-    {
-        len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pDeviceDesc->size);
-        USBD_CtrlInData((uint8_t *)g_usbDev.pDeviceDesc->pDesc, len);
-    }
-    else if(wValue1 == USBD_DESC_CONFIGURATION)
-    {
-        len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pConfigurationDesc->size);
-        USBD_CtrlInData((uint8_t *)g_usbDev.pConfigurationDesc->pDesc, len);
-    }
-    else if(wValue1 == USBD_DESC_STRING)
-    {
-        if (wValue0 < SRTING_DESC_NUM)
-        {
-            len = USB_MIN(*(uint16_t *)g_usbDev.reqData.byte.wLength, g_usbDev.pStringDesc[wValue0].size);
-            USBD_CtrlInData((uint8_t *)g_usbDev.pStringDesc[wValue0].pDesc, len);
-        }
-        else
-        {
-            ret = ERROR;
-            USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-        }
-
-    }
-    else
-    {
-        ret = ERROR;
-        USBD_SetEPTxRxStatus(USBD_EP_0, USBD_EP_STATUS_STALL, USBD_EP_STATUS_STALL);
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       Standard request get interface
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardGetInterface(void)
-{
-
-    return ERROR;
-}
-
-/*!
- * @brief       Standard request get status
- *
- * @param       None
- *
- * @retval      ERROR: 0; SUCCESS : 1
- */
-static uint8_t USBD_StandardGetStatus(void)
-{
-    uint8_t ret = 1;
-
-
-    uint8_t status[2] = {0, 0};
-
-    if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_DEVICE)
-    {
-        if(g_usbDev.curFeature & (1 << 5))
-        {
-            status[0] |= 0x02;
-        }
-
-        if(g_usbDev.curFeature & (1 << 6))
-        {
-            status[0] |= 0x01;
-        }
-
-        USBD_CtrlInData(status, 2);
-
-
-    }
-
-    else if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_INTERFACE)
-    {
-        USBD_CtrlInData(status, 2);
-
-
-    }
-
-    else if((g_usbDev.reqData.byte.bmRequestType.bit.recipient) == USBD_RECIPIENT_ENDPOINT)
-    {
-
-        if(g_usbDev.reqData.byte.wIndex[0] & 0x80)
-        {
-            if(USBD_ReadEPTxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL)
-            {
-                status[0] |= 0x01;
-            }
-        }
-        else
-        {
-            if(USBD_ReadEPRxStatus(g_usbDev.reqData.byte.wIndex[0] & 0x0f) == USBD_EP_STATUS_STALL)
-            {
-                status[0] |= 0x01;
-            }
-
-        }
-        USBD_CtrlInData(status, 2);
-
-    }
-    else
-    {
-        ret = 0;
-    }
-
-    return ret;
-}
-
-/*!
- * @brief       Standard request set address
- *
- * @param       None
- *
- * @retval      ERROR: 0; SUCCESS : 1
- */
-static uint8_t USBD_StandardSetAddress(void)
-{
-    USBD_DevReqData_T *reqData = &g_usbDev.reqData;
-
-    if((reqData->byte.wValue[0] < 127) && (reqData->byte.wValue[1] == 0) &&
-        (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE))
-    {
-        USBD_CtrlInData((void *)0, 0);
-
-        return 1;
-    }
-
-    return 0;
-}
-
-/*!
- * @brief       Standard request set configuration
- *
- * @param       None
- *
- * @retval      ERROR: 0;  SUCCESS : 1
- */
-static uint8_t USBD_StandardSetConfiguration(void)
-{
-    USBD_DevReqData_T *reqData = &g_usbDev.reqData;
-
-    if((reqData->byte.wValue[0] <= g_usbDev.configurationNum) && \
-       (reqData->byte.bmRequestType.bit.recipient == USBD_RECIPIENT_DEVICE))
-    {
-        g_usbDev.curConfiguration = reqData->byte.wValue[0];
-
-        if (g_usbDev.pStdReqCallback->setConfigurationHandler)
-        {
-            g_usbDev.pStdReqCallback->setConfigurationHandler();
-        }
-
-        USBD_CtrlInData((void *)0, 0);
-
-        return 1;
-    }
-
-    return 0;
-}
-
-/*!
- * @brief       Standard request set descriptor
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardSetDescriptor(void)
-{
-
-    return ERROR;
-}
-
-/*!
- * @brief       Standard request set feature
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardSetFeature(void)
-{
-    uint8_t ret = 1;
-
-    return ret;
-}
-
-/*!
- * @brief       Standard request set interface
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardSetInterface(void)
-{
-
-    return 0;
-}
-
-/*!
- * @brief       Standard request clear feature
- *
- * @param       None
- *
- * @retval      0: Failed; 1: Success
- */
-static uint8_t USBD_StandardClearFeature(void)
-{
-    return 0;
-}

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/inc/drv_usb_device.h

@@ -1,942 +0,0 @@
-/*!
- * @file        drv_usb_device.h
- *
- * @brief       This file contains all the prototypes,enumeration and macros for USBD peripheral
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#ifndef __DRV_USB_DEVICE_H_
-#define __DRV_USB_DEVICE_H_
-
-#ifdef __cplusplus
-  extern "C" {
-#endif
-
-#if defined(APM32F070xB) || defined(APM32F072x8) || defined(APM32F072xB)
-#define APM32F0xx_USB
-#else
-#define APM32F10x_USB
-#endif
-
-#ifdef APM32F0xx_USB
-#include "apm32f0xx.h"
-#include "apm32f0xx_pmu.h"
-#include "apm32f0xx_eint.h"
-#include "apm32f0xx_gpio.h"
-#include "apm32f0xx_rcm.h"
-#include "apm32f0xx_misc.h"
-#include "usb_config.h"
-#else
-#include "apm32f10x.h"
-#include "apm32f10x_pmu.h"
-#include "apm32f10x_eint.h"
-#include "apm32f10x_gpio.h"
-#include "apm32f10x_rcm.h"
-#include "apm32f10x_misc.h"
-#include "usb_config.h"
-#endif
-
-/** @addtogroup Peripherals_Library Standard Peripheral Library
-  @{
-*/
-
-/** @addtogroup USBD_Driver USBD Driver
-  @{
-*/
-
-/** @addtogroup USBD_Enumerations Enumerations
-  @{
-*/
-
-/**
- * @brief   USBD Endpoint register bit definition
- */
-typedef enum
-{
-    USBD_EP_BIT_ADDR     = (uint32_t)(BIT0 | BIT1 | BIT2 | BIT3),
-    USBD_EP_BIT_TXSTS    = (uint32_t)(BIT4 | BIT5),
-    USBD_EP_BIT_TXDTOG   = (uint32_t)(BIT6),
-    USBD_EP_BIT_CTFT     = (uint32_t)(BIT7),
-    USBD_EP_BIT_KIND     = (uint32_t)(BIT8),
-    USBD_EP_BIT_TYPE     = (uint32_t)(BIT9 | BIT10),
-    USBD_EP_BIT_SETUP    = (uint32_t)(BIT11),
-    USBD_EP_BIT_RXSTS    = (uint32_t)(BIT12 | BIT13),
-    USBD_EP_BIT_RXDTOG   = (uint32_t)(BIT14),
-    USBD_EP_BIT_CTFR     = (uint32_t)(BIT15)
-}USBD_EP_BIT_T;
-
-/**
- * @brief   Endpoint id
- */
-typedef enum
-{
-    USBD_EP_0,
-    USBD_EP_1,
-    USBD_EP_2,
-    USBD_EP_3,
-    USBD_EP_4,
-    USBD_EP_5,
-    USBD_EP_6,
-    USBD_EP_7,
-}USBD_EP_T;
-
-/**
- * @brief   Endpoint status
- */
-typedef enum
-{
-    USBD_EP_STATUS_DISABLE   = ((uint32_t)0),
-    USBD_EP_STATUS_STALL     = ((uint32_t)1),
-    USBD_EP_STATUS_NAK       = ((uint32_t)2),
-    USBD_EP_STATUS_VALID     = ((uint32_t)3),
-}USBD_EP_STATUS_T;
-
-/**
- * @brief   USBD Endpoint type for register
- */
-typedef enum
-{
-    USBD_REG_EP_TYPE_BULK,
-    USBD_REG_EP_TYPE_CONTROL,
-    USBD_REG_EP_TYPE_ISO,
-    USBD_REG_EP_TYPE_INTERRUPT
-}USBD_REG_EP_TYPE_T;
-
-/**@} end of group USBD_Enumerations*/
-
-
-/** @addtogroup USBD_Macros Macros
-  @{
-*/
-
-/** USBD packet memory area base address */
-#define USBD_PMA_ADDR            (0x40006000L)
-
-/** Endpoint register mask value default */
-#define USBD_EP_MASK_DEFAULT     (USBD_EP_BIT_CTFR | USBD_EP_BIT_SETUP | USBD_EP_BIT_TYPE | USBD_EP_BIT_KIND | USBD_EP_BIT_CTFT |USBD_EP_BIT_ADDR)
-
-/**
- * @brief   USBD interrupt source
- */
-#define USBD_INT_ESOF            0X100
-#define USBD_INT_SOF             0X200
-#define USBD_INT_RST             0X400
-#define USBD_INT_SUS             0x800
-#define USBD_INT_WKUP            0X1000
-#define USBD_INT_ERR             0X2000
-#define USBD_INT_PMAOU           0X4000
-#define USBD_INT_CTR             0X8000
-#define USBD_INT_ALL             0XFF00
-
-/**@} end of group USBD_Macros*/
-
-
-/** @addtogroup USBD_Fuctions Fuctions
-  @{
-*/
-
-/*!
- * @brief       Set CTRL register
- *
- * @param       val:    Register value
- *
- * @retval      None
- *
- */
-#define USBD_SetRegCTRL(val)         (USBD->CTRL = val)
-
-/*!
- * @brief       Set INTSTS register
- *
- * @param       val:    Register value
- *
- * @retval      None
- */
-#define USBD_SetRegINTSTS(val)       (USBD->INTSTS = val)
-
-/*!
- * @brief       Set force reset
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetForceReset()         (USBD->CTRL_B.FORRST = BIT_SET)
-
-/*!
- * @brief       Reset force reset
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetForceReset()       (USBD->CTRL_B.FORRST = BIT_RESET)
-
-/*!
- * @brief       Set power down
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetPowerDown()          (USBD->CTRL_B.PWRDOWN = BIT_SET)
-
-/*!
- * @brief       Reset power down
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetPowerDown()        (USBD->CTRL_B.PWRDOWN = BIT_RESET)
-
-/*!
- * @brief       Set low power mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetLowerPowerMode()     (USBD->CTRL_B.LPWREN = BIT_SET)
-
-/*!
- * @brief       Ret low power mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetLowerPowerMode()   (USBD->CTRL_B.LPWREN = BIT_RESET)
-
-/*!
- * @brief       Set force suspend
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetForceSuspend()       (USBD->CTRL_B.FORSUS = BIT_SET)
-
-/*!
- * @brief       Reset force suspend
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetForceSuspend()     (USBD->CTRL_B.FORSUS = BIT_RESET)
-
-/*!
- * @brief       Read force suspend status
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ReadForceSuspend()      (USBD->CTRL_B.FORSUS)
-
-/*!
- * @brief       Set resume
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_SetResume()             (USBD->CTRL_B.WUPREQ = BIT_SET)
-
-/*!
- * @brief       Reset resume
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_ResetResume()           (USBD->CTRL_B.WUPREQ = BIT_RESET)
-
-/*!
- * @brief       Enable interrupt
- *
- * @param       int:    Interrupt source
- *
- * @retval      None
- */
-#define USBD_EnableInterrupt(int)    (USBD->CTRL |= int)
-
-/*!
- * @brief       Disable interrupt
- *
- * @param       int:    Interrupt source
- *
- * @retval      None
- */
-#define USBD_DisableInterrupt(int)   (USBD->CTRL &= (uint32_t)~int)
-
-/*!
- * @brief       Read the specified interrupt flag status
- *
- * @param       int:    Interrupt source
- *
- * @retval      Flag status.0 or not 0
- */
-#define USBD_ReadIntFlag(int)        (USBD->INTSTS & int)
-
-/*!
- * @brief       Clear the specified interrupt flag status
- *
- * @param       int:    Interrupt source
- *
- * @retval      None
- */
-#define USBD_ClearIntFlag(int)       (USBD->INTSTS &= (uint32_t)~int)
-
-/*!
- * @brief       Read DOT field value in INTSTS rigister
- *
- * @param       None
- *
- * @retval      DOT field value
- */
-#define USBD_ReadDir()               (USBD->INTSTS_B.DOT)
-
-/*!
- * @brief       Read EPID field value in INTSTS rigister
- *
- * @param       None
- *
- * @retval      EPIDfield value
- */
-#define USBD_ReadEP()                ((USBD_EP_T)(USBD->INTSTS_B.EPID))
-
-/*!
- * @brief       Read EP type
- *
- * @param       ep:     EP number
- *
- * @retval      EP type
- */
-#define USBD_ReadEPType(ep)          (USBD->EP[ep].EP_B.TYPE)
-
-/*!
- * @brief       Read EP Tx status
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx status
- */
-#define USBD_ReadEPTxStatus(ep)      ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.TXSTS))
-
-/*!
- * @brief       Read EP Rx status
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx status
- */
-#define USBD_ReadEPRxStatus(ep)      ((USBD_EP_STATUS_T)(USBD->EP[ep].EP_B.RXSTS))
-
-/*!
- * @brief       Read SETUP field value in EP register
- *
- * @param       ep:     EP number
- *
- * @retval      SETUP field value
- */
-#define USBD_ReadEPSetup(ep)         (USBD->EP[ep].EP_B.SETUP)
-
-/*!
- * @brief       Set buffer table value
- *
- * @param       tab:    Buffer table value
- *
- * @retval      None
- */
-#define USBD_SetBufferTable(tab)     (USBD->BUFFTB_B.BUFFTB = tab)
-
-/*!
- * @brief       Set device address
- *
- * @param       addr:   Device address
- *
- * @retval      None
- */
-#define USBD_SetDeviceAddr(addr)     (USBD->ADDR_B.ADDR = addr)
-
-/*!
- * @brief       Read CTFR field value in EP register
- *
- * @param       ep: Endpoint number
- *
- * @retval      CTFR field value
- */
-#define USBD_ReadEPRxFlag(ep)        (USBD->EP[ep].EP_B.CTFR)
-
-/*!
- * @brief       Read CTFT field value in EP register
- *
- * @param       ep: Endpoint number
- *
- * @retval      CTFT field value
- */
-#define USBD_ReadEPTxFlag(ep)        (USBD->EP[ep].EP_B.CTFT)
-
-/*!
- * @brief       Enable USBD peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_Enable()                (USBD->ADDR_B.USBDEN = BIT_SET)
-
-/*!
- * @brief       Disable USBD peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_Disable()               (USBD->ADDR_B.USBDEN = BIT_RESET)
-
-/*!
- * @brief       Enable USBD2 peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD2_Enable()               (USBD->SWITCH = BIT_SET)
-
-/*!
- * @brief       Disable USBD2 peripheral
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD2_Disable()              (USBD->SWITCH = BIT_RESET)
-
-/*!
- * @brief       Read RXDPSTS field value in FRANUM register
- *
- * @param       None
- *
- * @retval      RXDPSTS field value
- */
-#define USBD_ReadRDPS()              (USBD->FRANUM_B.RXDPSTS)
-
-/*!
- * @brief       Read RXDMSTS field value in FRANUM register
- *
- * @param       None
- *
- * @retval      RXDMSTS field value
- */
-#define USBD_ReadRDMS()              (USBD->FRANUM_B.RXDMSTS)
-
-/*!
- * @brief       Read LOCK field value in FRANUM register
- *
- * @param       None
- *
- * @retval      LOCK field value
- */
-#define USBD_ReadLOCK()              (USBD->FRANUM_B.LOCK)
-
-/*!
- * @brief       Read LSOFNUM field value in FRANUM register
- *
- * @param       None
- *
- * @retval      LSOFNUM field value
- */
-#define USBD_ReadLSOF()              (USBD->FRANUM_B.LSOFNUM)
-
-/*!
- * @brief       Read FRANUM field value in FRANUM register
- *
- * @param       None
- *
- * @retval      FRANUM field value
- */
-#define USBD_ReadFRANUM()              (USBD->FRANUM_B.FRANUM)
-
-#ifdef APM32F0xx_USB
-/*!
- * @brief       Read EP Tx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx address pointer
- */
-#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Tx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count pointer
- */
-#define USBD_ReadEPTxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx address pointer
- */
-#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count pointer
- */
-#define USBD_ReadEPRxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Tx addr
- *
- * @retval      None
- */
-#define USBD_SetEPTxAddr(ep, addr)   (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Set EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Rx addr
- *
- * @retval      None
- */
-#define USBD_SetEPRxAddr(ep, addr)   (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Read EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx addr
- */
-#define USBD_ReadEPTxAddr(ep)        ((uint16_t)*USBD_ReadEPTxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx addr
- */
-#define USBD_ReadEPRxAddr(ep)        ((uint16_t)*USBD_ReadEPRxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Tx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx Buffer Pointer
- */
-#define USBD_ReadEPTxBufferPointer(ep)   (uint16_t *)(USBD_ReadEPTxAddr(ep) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx Buffer Pointer
- */
-#define USBD_ReadEPRxBufferPointer(ep)   (uint16_t *)(USBD_ReadEPRxAddr(ep) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx Count
- *
- * @param       ep:     EP number
- *
- * @param       cnt:    Tx count
- *
- * @retval      None
- */
-#define USBD_SetEPTxCnt(ep, cnt)     (*USBD_ReadEPTxCntPointer(ep) = cnt)
-
-/*!
- * @brief       Read EP Tx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count
- */
-#define USBD_ReadEPTxCnt(ep)        ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff)
-
-/*!
- * @brief       Read EP Rx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count
- */
-#define USBD_ReadEPRxCnt(ep)        ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff)
-
-/*!
- * @brief       Set BESL Value
- *
- * @param       val: 4-bits BESL Value to be set
- *
- * @retval      None
- */
-#define USBD_SetBESL(val)            (USBD->LPMCTRLSTS_B.BESL = val)
-
-/*!
- * @brief       Set bRemoteWakew Value
- *
- * @param       val: 1-bit bRemoteWakew Value to be set
- *
- * @retval      None
- */
-#define USBD_SetRemoteWakeVal(val)   (USBD->LPMCTRLSTS_B.REMWAKE = val)
-
-/*!
- * @brief       Enable LPM ACK
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableAckLPM()          (USBD->LPMCTRLSTS_B.LPMACKEN = 1)
-
-/*!
- * @brief       Disable LPM ACK
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableAckLPM()         (USBD->LPMCTRLSTS_B.LPMACKEN = 0)
-
-/*!
- * @brief       Disable LPM
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableLPM()             (USBD->LPMCTRLSTS_B.LPMEN = 1)
-
-/*!
- * @brief       Disable LPM
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableLPM()            (USBD->LPMCTRLSTS_B.LPMEN = 0)
-
-/*!
- * @brief       Enable Pull-up of DP line
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnablePullUpDP()        (USBD->BCD_B.DPPUCTRL = 1)
-
-/*!
- * @brief       Disable Pull-up of DP line
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisablePullUpDP()       (USBD->BCD_B.DPPUCTRL = 0)
-
-/*!
- * @brief       Read DM Pull-up Detection Status Flag
- *
- * @param       None
- *
- * @retval      DM Pull-up Detection Status Flag
- */
-#define USBD_DMPullUpStatus()        (USBD->BCD_B.DMPUDFLG)
-
-/*!
- * @brief       Read Secondary Detection Status Flag
- *
- * @param       None
- *
- * @retval      Secondary Detection Status Flag
- */
-#define USBD_SDStatus()              (USBD->BCD_B.SDFLG)
-
-/*!
- * @brief       Read Primary Detection Status Flag
- *
- * @param       None
- *
- * @retval      Primary Detection Status Flag
- */
-#define USBD_PDStatus()              (USBD->BCD_B.PDFLG)
-
-/*!
- * @brief       Read Data Contact Detection Status Flag
- *
- * @param       None
- *
- * @retval      Data Contact Detection Status Flag
- */
-#define USBD_DCDStatus()             (USBD->BCD_B.DCDFLG)
-
-/*!
- * @brief       Enable Secondary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableSDMode()          (USBD->BCD_B.SDEN = 1)
-
-/*!
- * @brief       Disable Secondary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableSDMode()         (USBD->BCD_B.SDEN = 0)
-
-/*!
- * @brief       Enable Primary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnablePDMode()          (USBD->BCD_B.PDEN = 1)
-
-/*!
- * @brief       Disable Primary Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisablePDMode()         (USBD->BCD_B.PDEN = 0)
-
-/*!
- * @brief       Enable Data Contact Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableDCDMode()         (USBD->BCD_B.DCDEN = 1)
-
-/*!
- * @brief       Disable Data Contact Detection Mode
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableDCDMode()        (USBD->BCD_B.DCDEN = 0)
-
-/*!
- * @brief       Enable Battery Charging Detector
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_EnableBCD()             (USBD->BCD_B.BCDEN = 1)
-
-/*!
- * @brief       Disable Battery Charging Detector
- *
- * @param       None
- *
- * @retval      None
- */
-#define USBD_DisableBCD()            (USBD->BCD_B.BCDEN = 0)
-
-#else //!< APM32F10x_USB
-/*!
- * @brief       Read EP Tx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx address pointer
- */
-#define USBD_ReadEPTxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Tx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count pointer
- */
-#define USBD_ReadEPTxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 2) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx address pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx address pointer
- */
-#define USBD_ReadEPRxAddrPointer(ep) (uint16_t *)((USBD->BUFFTB + ep * 8 + 4) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx count pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count pointer
- */
-#define USBD_ReadEPRxCntPointer(ep)  (uint16_t *)((USBD->BUFFTB + ep * 8 + 6) * 2 + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Tx addr
- *
- * @retval      None
- */
-#define USBD_SetEPTxAddr(ep, addr)   (*USBD_ReadEPTxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Set EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @param       addr:   Rx addr
- *
- * @retval      None
- */
-#define USBD_SetEPRxAddr(ep, addr)   (*USBD_ReadEPRxAddrPointer(ep) = (addr >> 1) << 1)
-
-/*!
- * @brief       Read EP Tx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx addr
- */
-#define USBD_ReadEPTxAddr(ep)        ((uint16_t)*USBD_ReadEPTxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Rx addr
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx addr
- */
-#define USBD_ReadEPRxAddr(ep)        ((uint16_t)*USBD_ReadEPRxAddrPointer(ep))
-
-/*!
- * @brief       Read EP Tx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx Buffer Pointer
- */
-#define USBD_ReadEPTxBufferPointer(ep)   (uint32_t *)(((uint32_t)USBD_ReadEPTxAddr(ep) << 1) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Read EP Rx Buffer Pointer
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx Buffer Pointer
- */
-#define USBD_ReadEPRxBufferPointer(ep)   (uint32_t *)(((uint32_t)USBD_ReadEPRxAddr(ep) << 1) + USBD_PMA_ADDR)
-
-/*!
- * @brief       Set EP Tx Count
- *
- * @param       ep:     EP number
- *
- * @param       cnt:    Tx count
- *
- * @retval      None
- */
-#define USBD_SetEPTxCnt(ep, cnt)     (*USBD_ReadEPTxCntPointer(ep) = cnt)
-
-/*!
- * @brief       Read EP Tx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Tx count
- */
-#define USBD_ReadEPTxCnt(ep)        ((uint16_t)*USBD_ReadEPTxCntPointer(ep) & 0x3ff)
-
-/*!
- * @brief       Read EP Rx count
- *
- * @param       ep:     EP number
- *
- * @retval      EP Rx count
- */
-#define USBD_ReadEPRxCnt(ep)        ((uint16_t)*USBD_ReadEPRxCntPointer(ep) & 0x3ff)
-
-#endif
-void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type);
-
-void USBD_SetEPKind(uint8_t ep);
-void USBD_ResetEPKind(uint8_t ep);
-
-void USBD_ResetEPRxFlag(uint8_t ep);
-void USBD_ResetEPTxFlag(uint8_t ep);
-
-void USBD_ToggleTx(uint8_t ep);
-void USBD_ToggleRx(uint8_t ep);
-void USBD_ResetTxToggle(uint8_t ep);
-void USBD_ResetRxToggle(uint8_t ep);
-
-void USBD_SetEpAddr(uint8_t ep, uint8_t addr);
-
-void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status);
-void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status);
-void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus);
-
-void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt);
-
-void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen);
-void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen);
-
-/**@} end of group USBD_Fuctions*/
-/**@} end of group USBD_Driver*/
-/**@} end of group Peripherals_Library*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DRV_USB_DEVICE_H */

bsp/apm32/libraries/APM32F10x_Library/USB_Device_Lib/Driver/src/drv_usb_device.c

@@ -1,403 +0,0 @@
-/*!
- * @file        drv_usb_device.c
- *
- * @brief       This file contains all the functions for the USBD peripheral
- *
- * @version     V1.0.0
- *
- * @date        2021-12-06
- *
- * @attention
- *
- *  Copyright (C) 2020-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "drv_usb_device.h"
-
-/*!
- * @brief       Set Endpoint type
- *
- * @param       ep: Endpoint number
- *
- * @param       type: Endpoint type
- *
- * @retval      None
- */
-void USBD_SetEPType(uint8_t ep, USBD_REG_EP_TYPE_T type)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_TYPE;
-    reg |= type << 9;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP kind
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_SetEPKind(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg |= USBD_EP_BIT_KIND;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Reset EP kind
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetEPKind(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_KIND;
-
-    USBD->EP[ep].EP = reg;
-}
-
-
-/*!
- * @brief       Reset EP CTFR bit
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetEPRxFlag(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_CTFR;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Reset EP CTFT bit
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetEPTxFlag(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_CTFT;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Toggle Tx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ToggleTx(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg |= USBD_EP_BIT_TXDTOG;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Toggle Rx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ToggleRx(uint8_t ep)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg |= USBD_EP_BIT_RXDTOG;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Reset Toggle Tx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetTxToggle(uint8_t ep)
-{
-    if(USBD->EP[ep].EP_B.TXDTOG)
-    {
-        USBD_ToggleTx(ep);
-    }
-}
-
-/*!
- * @brief       Reset Toggle Rx DTOG
- *
- * @param       ep: Endpoint number
- *
- * @retval      None
- */
-void USBD_ResetRxToggle(uint8_t ep)
-{
-    if(USBD->EP[ep].EP_B.RXDTOG)
-    {
-        USBD_ToggleRx(ep);
-    }
-}
-
-/*!
- * @brief       Set EP address
- *
- * @param       ep: Endpoint number
- *
- * @param       addr: Address
- *
- * @retval      None
- */
-void USBD_SetEpAddr(uint8_t ep, uint8_t addr)
-{
-    __IOM uint32_t reg;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT);
-    reg &= ~USBD_EP_BIT_ADDR;
-    reg |= addr;
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP Tx status
- *
- * @param       ep: Endpoint number
- *
- * @param       status: status
- *
- * @retval      None
- */
-void USBD_SetEPTxStatus(uint8_t ep, USBD_EP_STATUS_T status)
-{
-    __IOM uint32_t reg;
-
-    status <<= 4;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_TXSTS);
-    reg ^= ((uint32_t)status & (uint32_t)USBD_EP_BIT_TXSTS);
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP Rx status
- *
- * @param       ep: Endpoint number
- *
- * @param       status: status
- *
- * @retval      None
- */
-void USBD_SetEPRxStatus(uint8_t ep, USBD_EP_STATUS_T status)
-{
-    __IOM uint32_t reg;
-    uint32_t tmp;
-
-    tmp = status << 12;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS);
-    reg ^= (tmp & USBD_EP_BIT_RXSTS);
-
-    USBD->EP[ep].EP = reg;
-}
-
-
-/*!
- * @brief       Set EP Tx and Rx status
- *
- * @param       ep: Endpoint number
- *
- * @param       status: status
- *
- * @retval      None
- */
-void USBD_SetEPTxRxStatus(uint8_t ep, USBD_EP_STATUS_T txStatus, USBD_EP_STATUS_T rxStatus)
-{
-    __IOM uint32_t reg;
-    uint32_t tmp;
-
-    reg = USBD->EP[ep].EP;
-
-    reg &= (uint32_t)(USBD_EP_MASK_DEFAULT | USBD_EP_BIT_RXSTS | USBD_EP_BIT_TXSTS);
-
-    tmp = rxStatus << 12;
-    reg ^= (tmp & USBD_EP_BIT_RXSTS);
-
-    tmp = txStatus << 4;
-    reg ^= (tmp & USBD_EP_BIT_TXSTS);
-
-    USBD->EP[ep].EP = reg;
-}
-
-/*!
- * @brief       Set EP Rx Count
- *
- * @param       ep: Endpoint number
- *
- * @param       cnt: Rx count
- *
- * @retval      None
- */
-void USBD_SetEPRxCnt(uint8_t ep, uint32_t cnt)
-{
-    __IOM uint16_t *p;
-    __IOM uint16_t block = 0;
-
-    p = USBD_ReadEPRxCntPointer(ep);
-
-    if(cnt > 62)
-    {
-        block = cnt >> 5;
-
-        if(!(cnt & 0x1f))
-        {
-            block -= 1;
-        }
-
-        *p = (block << 10) | 0x8000;
-    }
-    else
-    {
-        block = cnt >> 1;
-
-        if(cnt & 0x01)
-        {
-            block += 1;
-        }
-
-        *p = (block << 10);
-    }
-}
-
-/*!
- * @brief       Write a buffer of data to a selected endpoint
- *
- * @param       ep:   Endpoint number
- *
- * @retval      wBuf: The pointer to the buffer of data to be written to the endpoint
- *
- * @param       wLen: Number of data to be written (in bytes)
- *
- * @retval      None
- */
-void USBD_WriteDataToEP(uint8_t ep, uint8_t *wBuf, uint32_t wLen)
-{
-    uint32_t i;
-#ifdef APM32F0xx_USB
-    uint16_t *epAddr;
-    uint16_t tmp;
-#else
-    uint32_t *epAddr;
-    uint32_t tmp;
-#endif
-
-    wLen = (wLen + 1) >> 1;
-
-    epAddr = USBD_ReadEPTxBufferPointer(ep);
-
-    for(i = 0; i < wLen; i++)
-    {
-        tmp = *wBuf++;
-        tmp = ((*wBuf++) << 8) | tmp;
-
-        *epAddr++ = tmp;
-    }
-}
-
-/*!
- * @brief       Read a buffer of data to a selected endpoint
- *
- * @param       ep:   Endpoint number
- *
- * @retval      wBuf: The pointer to the buffer of data to be read to the endpoint
- *
- * @param       wLen: Number of data to be read (in bytes)
- *
- * @retval      None
- */
-void USBD_ReadDataFromEP(uint8_t ep, uint8_t *rBuf, uint32_t rLen)
-{
-#ifdef APM32F0xx_USB
-    uint16_t *epAddr;
-#else
-    uint32_t *epAddr;
-#endif
-    uint32_t i, tmp, cnt;
-
-    cnt = rLen >> 1;
-
-    epAddr = USBD_ReadEPRxBufferPointer(ep);
-
-    for(i = 0; i < cnt; i++)
-    {
-        tmp = *epAddr++;
-        *rBuf++ = tmp & 0xFF;
-        *rBuf++ = (tmp >> 8) & 0xFF;
-    }
-
-    if (rLen & 1)
-    {
-        tmp = *epAddr;
-        *rBuf = tmp & 0xFF;
-    }
-}

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/inc/apm32f4xx_eth.h

@@ -1,1424 +0,0 @@
-/*!
- * @file        apm32f4xx_eth.c
- *
- * @brief       This file provides all the ETH firmware functions
- *
- * @version     V1.0.2
- *
- * @date        2022-06-23
- *
- * @attention
- *
- *  Copyright (C) 2021-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-/* Define to prevent recursive inclusion */
-#ifndef __APM32F4xx_ETH_H
-#define __APM32F4xx_ETH_H
-
-#ifdef __cplusplus
-  extern "C" {
-#endif
-
-/* Includes */
-#include "apm32f4xx.h"
-
-/** @addtogroup APM32F4xx_ETHDriver
-  @{
-*/
-
-/** @addtogroup ETH_Driver
-  @{
-*/
-
-/** @defgroup ETH_Enumerations
-  @{
-*/
-
-/**
- * @brief    ETH AutoNegotiation
- */
-typedef enum
-{
-    ETH_AUTONEGOTIATION_DISABLE,    /*!< Disable negotiation */
-    ETH_AUTONEGOTIATION_ENABLE      /*!< Enable negotiation */
-} ETH_AUTONEGOTIATION_T;
-
-/**
- * @brief    ETH Watchdog
- */
-typedef enum
-{
-    ETH_WATCHDOG_ENABLE,    /*!< Enable watch dog */
-    ETH_WATCHDOG_DISABLE    /*!< Disable watch dog */
-} ETH_WATCHDOG_T;
-
-/**
- * @brief    ETH Jabber
- */
-typedef enum
-{
-    ETH_JABBER_ENABLE,  /*!< Enable jabber */
-    ETH_JABBER_DISABLE  /*!< Disable jabber */
-} ETH_JABBER_T;
-
-/**
- * @brief    ETH Inter Frame Gap
- */
-typedef enum
-{
-    ETH_INTERFRAMEGAP_96BIT = 0x00, /*!< Inter-Frame gap = 96-bit */
-    ETH_INTERFRAMEGAP_88BIT = 0x01, /*!< Inter-Frame gap = 88-bit */
-    ETH_INTERFRAMEGAP_80BIT = 0x02, /*!< Inter-Frame gap = 80-bit */
-    ETH_INTERFRAMEGAP_72BIT = 0x03, /*!< Inter-Frame gap = 72-bit */
-    ETH_INTERFRAMEGAP_64BIT = 0x04, /*!< Inter-Frame gap = 64-bit */
-    ETH_INTERFRAMEGAP_56BIT = 0x05, /*!< Inter-Frame gap = 56-bit */
-    ETH_INTERFRAMEGAP_48BIT = 0x06, /*!< Inter-Frame gap = 48-bit */
-    ETH_INTERFRAMEGAP_40BIT = 0x07  /*!< Inter-Frame gap = 40-bit */
-} ETH_INTERFRAMEGAP_T;
-
-/**
- * @brief    ETH Carrier Sense
- */
-typedef enum
-{
-    ETH_CARRIERSENCE_ENABLE,    /*!< Disable carrier sense during transmission */
-    ETH_CARRIERSENCE_DISABLE    /*!< Ignore MII CRS signal */
-} ETH_CARRIERSENCE_T;
-
-/**
- * @brief    ETH Speed
- */
-typedef enum
-{
-    ETH_SPEED_10M,  /*!< 10M speed */
-    ETH_SPEED_100M  /*!< 100M speed */
-} ETH_SPEED_T;
-
-/**
- * @brief    ETH Receive Own
- */
-typedef enum
-{
-    ETH_RECEIVEOWN_ENABLE,  /*!< Enable receive own */
-    ETH_RECEIVEOWN_DISABLE  /*!< Disable receive own */
-} ETH_RECEIVEOWN_T;
-
-/**
- * @brief    ETH Loop Back Mode
- */
-typedef enum
-{
-    ETH_LOOPBACKMODE_DISABLE,   /*!< Disable loopback mode */
-    ETH_LOOPBACKMODE_ENABLE     /*!< Enable loopback mode */
-} ETH_LOOPBACKMODE_T;
-
-/**
- * @brief    ETH Duplex Mode
- */
-typedef enum
-{
-    ETH_MODE_HALFDUPLEX,    /*!< Half-Duplex */
-    ETH_MODE_FULLDUPLEX     /*!< Full-Duplex */
-} ETH_MODE_T;
-
-/**
- * @brief    ETH Checksum Offload
- */
-typedef enum
-{
-    ETH_CHECKSUMOFFLAOD_DISABLE,    /*!< Disable IPv4 checksum offload */
-    ETH_CHECKSUMOFFLAOD_ENABLE      /*!< Enable Ipv4 checksum offload */
-} ETH_CHECKSUMOFFLAOD_T;
-
-/**
- * @brief    ETH Retry Transmission
- */
-typedef enum
-{
-    ETH_RETRYTRANSMISSION_ENABLE,   /*!< Enable retry */
-    ETH_RETRYTRANSMISSION_DISABLE   /*!< Disable retry */
-} ETH_RETRYTRANSMISSION_T;
-
-/**
- * @brief    ETH Automatic Pad CRC Strip
- */
-typedef enum
-{
-    ETH_AUTOMATICPADCRCSTRIP_DISABLE,   /*!< Disable automatic pad or CRC stripping */
-    ETH_AUTOMATICPADCRCSTRIP_ENABLE     /*!< Enable automatic pad or CRC stripping */
-} ETH_AUTOMATICPADCRCSTRIP_T;
-
-/**
- * @brief    ETH Back Off Limit
- */
-typedef enum
-{
-    ETH_BACKOFFLIMIT_10,    /*!< Set back off limit to 10 */
-    ETH_BACKOFFLIMIT_8,     /*!< Set back off limit to 18 */
-    ETH_BACKOFFLIMIT_4,     /*!< Set back off limit to 4 */
-    ETH_BACKOFFLIMIT_1      /*!< Set back off limit to 1 */
-} ETH_BACKOFFLIMIT_T;
-
-/**
- * @brief    ETH Deferral Check
- */
-typedef enum
-{
-    ETH_DEFFERRALCHECK_DISABLE, /*!< Disable deferral check */
-    ETH_DEFFERRALCHECK_ENABLE   /*!< Enable deferral check */
-} ETH_DEFFERRALCHECK_T;
-
-/**
- * @brief    ETH Receive All
- */
-typedef enum
-{
-    ETH_RECEIVEAll_DISABLE, /*!< Disable receive all */
-    ETH_RECEIVEALL_ENABLE   /*!< Enable receive all */
-} ETH_RECEIVEAll_T;
-
-/**
- * @brief    ETH Source Addr Filter
- */
-typedef enum
-{
-    ETH_SOURCEADDRFILTER_DISABLE,                       /*!< Disable source address filter */
-    ETH_SOURCEADDRFILTER_NORMAL_ENABLE = BIT9,          /*!< Enable normal source address filter */
-    ETH_SOURCEADDRFILTER_INVERSE_ENABLE = BIT8 | BIT9,  /*!< Enable inverse source address filter */
-} ETH_SOURCEADDRFILTER_T;
-
-/**
- * @brief    ETH Pass Control Frames
- */
-typedef enum
-{
-    ETH_PASSCONTROLFRAMES_BLOCKALL = 1,             /*!< Even if all control frames except pause frames fail the
-                                                        address filter, MAC forwards them to the application */
-    ETH_PASSCONTROLFRAMES_FORWARDALL,               /*!< MAC forwards control frames to the application even if
-                                                        they do not pass the address filter */
-    ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER   /*!< MAC forwards control frames that pass through the address filter */
-} ETH_PASSCONTROLFRAMES_T;
-
-/**
- * @brief    ETH Broadcast Frames Reception
- */
-typedef enum
-{
-    ETH_BROADCASTFRAMESRECEPTION_ENABLE,    /*!< Enable broadcast frames */
-    ETH_BROADCASTFRAMESRECEPTION_DISABLE    /*!< Disable broadcast frames */
-} ETH_BROADCASTFRAMESRECEPTION_T;
-
-/**
- * @brief    ETH Destination Addr Filter
- */
-typedef enum
-{
-    ETH_DESTINATIONADDRFILTER_NORMAL,   /*!< Normal destination address filter */
-    ETH_DESTINATIONADDRFILTER_INVERSE   /*!< Inverse destination address filter */
-} ETH_DESTINATIONADDRFILTER_T;
-
-/**
- * @brief    ETH Destination Addr Filter
- */
-typedef enum
-{
-    ETH_PROMISCUOUS_MODE_DISABLE,   /*!< Disable promiscuous mode */
-    ETH_PROMISCUOUS_MODE_ENABLE     /*!< Enable promiscuous mode */
-} ETH_PROMISCUOUS_MODE_T;
-
-/**
- * @brief    ETH Multicast Frames Filter
- */
-typedef enum
-{
-    ETH_MULTICASTFRAMESFILTER_PERFECT,                      /*!< Multicast perfect filter */
-    ETH_MULTICASTFRAMESFILTER_NONE = BIT4,                  /*!< Multicast pass all multicast */
-    ETH_MULTICASTFRAMESFILTER_HASHTABLE = BIT2,             /*!< Multicast hash multicast */
-    ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE = BIT2|BIT10 /*!< Multicast perfect hash table */
-} ETH_MULTICASTFRAMESFILTER_T;
-
-/**
- * @brief    ETH Unicast Frames Filter
- */
-typedef enum
-{
-    ETH_UNICASTFRAMESFILTER_PERFECT,                        /*!< Unicast perfect filter */
-    ETH_UNICASTFRAMESFILTER_HASHTABLE = BIT1,               /*!< Unicast hash table */
-    ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE = BIT1|BIT10   /*!< Unicast perfect hash table */
-} ETH_UNICASTFRAMESFILTER_T;
-
-/**
- * @brief    ETH Zero Quanta Pause
- */
-typedef enum
-{
-    ETH_ZEROQUANTAPAUSE_ENABLE,     /*!< Enable zero-quanta pause */
-    ETH_ZEROQUANTAPAUSE_DISABLE     /*!< Disable zero-quanta pause */
-} ETH_ZEROQUANTAPAUSE_T;
-
-/**
- * @brief    ETH Pause Low Threshold
- */
-typedef enum
-{
-    ETH_PAUSELOWTHRESHOLD_MINUS4,   /*!< Minus 4 slot-time */
-    ETH_PAUSELOWTHRESHOLD_MINUS28,  /*!< Minus 28 slot-time */
-    ETH_PAUSELOWTHRESHOLD_MINUS144, /*!< Minus 144 slot-time */
-    ETH_PAUSELOWTHRESHOLD_MINUS256  /*!< Minus 256 slot-time */
-} ETH_PAUSELOWTHRESHOLD_T;
-
-/**
- * @brief    ETH Unicast Pause Frame Detect
- */
-typedef enum
-{
-    ETH_UNICASTPAUSEFRAMEDETECT_DISABLE,    /*!< Disable unicast pause frame detect */
-    ETH_UNICASTPAUSEFRAMEDETECT_ENABLE      /*!< Enable unicast pause frame detect */
-} ETH_UNICASTPAUSEFRAMEDETECT_T;
-
-/**
- * @brief    ETH Receive Flow Control
- */
-typedef enum
-{
-    ETH_RECEIVEFLOWCONTROL_DISABLE, /*!< Disable receive flow control */
-    ETH_RECEIVEFLOWCONTROL_ENABLE   /*!< Enable receive flow control */
-} ETH_RECEIVEFLOWCONTROL_T;
-
-/**
- * @brief    ETH Transmit Flow Control
- */
-typedef enum
-{
-    ETH_TRANSMITFLOWCONTROL_DISABLE,    /*!< Disable transmit flow control */
-    ETH_TRANSMITFLOWCONTROL_ENABLE      /*!< Enable transmit flow control */
-} ETH_TRANSMITFLOWCONTROL_T;
-
-/**
- * @brief    ETH VLAN Tag Comparison
- */
-typedef enum
-{
-    ETH_VLANTAGCOMPARISON_16BIT,    /*!< 16-bit VLAN tag comparison */
-    ETH_VLANTAGCOMPARISON_12BIT     /*!< 12-bit VLAN tag comparison */
-} ETH_VLANTAGCOMPARISON_T;
-
-/**
- * @brief    ETH MAC Flags
- */
-typedef enum
-{
-    ETH_MAC_FLAG_TST  = 0x00000200, /*!< Time stamp trigger flag */
-    ETH_MAC_FLAG_MMCT = 0x00000040, /*!< MMC transmit flag */
-    ETH_MAC_FLAG_MMCR = 0x00000020, /*!< MMC receive flag */
-    ETH_MAC_FLAG_MMC  = 0x00000010, /*!< MMC flag */
-    ETH_MAC_FLAG_PMT  = 0x00000008  /*!< PMT flag */
-} ETH_MAC_FLAG_T;
-
-/**
- * @brief    ETH MAC Interrupts
- */
-typedef enum
-{
-    ETH_MAC_INT_TST  = 0x00000200,  /*!< Time stamp trigger interrupt */
-    ETH_MAC_INT_MMCT = 0x00000040,  /*!< MMC transmit interrupt */
-    ETH_MAC_INT_MMCR = 0x00000020,  /*!< MMC receive interrupt */
-    ETH_MAC_INT_MMC  = 0x00000010,  /*!< MMC interrupt */
-    ETH_MAC_INT_PMT  = 0x00000008   /*!< PMT interrupt */
-} ETH_MAC_INT_T;
-
-/**
- * @brief    ETH MAC Interrupts
- */
-typedef enum
-{
-    ETH_MAC_ADDRESS0 = 0x00000000,  /*!< MAC Address0 */
-    ETH_MAC_ADDRESS1 = 0x00000008,  /*!< MAC Address1 */
-    ETH_MAC_ADDRESS2 = 0x00000010,  /*!< MAC Address2 */
-    ETH_MAC_ADDRESS3 = 0x00000018   /*!< MAC Address3 */
-} ETH_MAC_ADDRESS_T;
-
-/**
- * @brief    ETH MAC addresses filter SA/DA
- */
-typedef enum
-{
-    ETH_MAC_ADDRESSFILTER_SA,           /*!< MAC Address is used to compare with the
-                                            SA fields of the received frame */
-    ETH_MAC_ADDRESSFILTER_DA = BIT30    /*!< MAC Address is used to compare with the
-                                            DA fields of the received frame */
-} ETH_MAC_ADDRESSFILTER_T;
-
-/**
- * @brief    ETH MAC addresses filter Mask bytes
- */
-typedef enum
-{
-    ETH_MAC_ADDRESSMASK_BYTE6 = 0x20000000,  /*!< Mask MAC Address high reg bits [15:8] */
-    ETH_MAC_ADDRESSMASK_BYTE5 = 0x10000000,  /*!< Mask MAC Address high reg bits [7:0] */
-    ETH_MAC_ADDRESSMASK_BYTE4 = 0x08000000,  /*!< Mask MAC Address low reg bits [31:24] */
-    ETH_MAC_ADDRESSMASK_BYTE3 = 0x04000000,  /*!< Mask MAC Address low reg bits [23:16] */
-    ETH_MAC_ADDRESSMASK_BYTE2 = 0x02000000,  /*!< Mask MAC Address low reg bits [15:8] */
-    ETH_MAC_ADDRESSMASK_BYTE1 = 0x01000000   /*!< Mask MAC Address low reg bits [70] */
-} ETH_MAC_ADDRESSMASK_T;
-
-/**
- * @brief    DMA Tx descriptor flags
- */
-typedef enum
-{
-    ETH_DMATXDESC_OWN      = (int)0x80000000,   /*!< Descriptor is owned by DMA engine */
-    ETH_DMATXDESC_INTC     = 0x40000000,        /*!< Interrupt on completion */
-    ETH_DMATXDESC_LS       = 0x20000000,        /*!< Last Segment */
-    ETH_DMATXDESC_FS       = 0x10000000,        /*!< First Segment */
-    ETH_DMATXDESC_DISC     = 0x08000000,        /*!< Disable CRC */
-    ETH_DMATXDESC_DISP     = 0x04000000,        /*!< Disable Pad */
-    ETH_DMATXDESC_TXTSEN   = 0x02000000,        /*!< Transmit Time Stamp Enable */
-    ETH_DMATXDESC_TXENDR   = 0x00200000,        /*!< Transmit End of Ring */
-    ETH_DMATXDESC_TXCH     = 0x00100000,        /*!< Second Address Chained */
-    ETH_DMATXDESC_TXTSS    = 0x00020000,        /*!< Tx Time Stamp Status */
-    ETH_DMATXDESC_IHERR    = 0x00010000,        /*!< IP Header Error */
-    ETH_DMATXDESC_ERRS     = 0x00008000,        /*!< Error summary */
-    ETH_DMATXDESC_JTO      = 0x00004000,        /*!< Jabber Timeout */
-    ETH_DMATXDESC_FF       = 0x00002000,        /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-    ETH_DMATXDESC_IPERR    = 0x00001000,        /*!< Payload Checksum Error */
-    ETH_DMATXDESC_LSC      = 0x00000800,        /*!< Loss of Carrier: carrier lost during transmission */
-    ETH_DMATXDESC_NC       = 0x00000400,        /*!< No Carrier: no carrier signal from the transceiver */
-    ETH_DMATXDESC_LC       = 0x00000200,        /*!< Late Collision: transmission aborted due to collision */
-    ETH_DMATXDESC_EC       = 0x00000100,        /*!< Excessive Collision: transmission aborted after 16 collisions */
-    ETH_DMATXDESC_VLANF    = 0x00000080,        /*!< VLAN Frame */
-    ETH_DMATXDESC_CCNT     = 0x00000078,        /*!< Collision Count */
-    ETH_DMATXDESC_EDEF     = 0x00000004,        /*!< Excessive Deferral */
-    ETH_DMATXDESC_UFERR    = 0x00000002,        /*!< Underflow Error: late data arrival from the memory */
-    ETH_DMATXDESC_DEF      = 0x00000001         /*!< Deferred Bit */
-} ETH_DMATXDESC_FLAG_T;
-
-/**
- * @brief    ETH DMA Tx descriptor segment
- */
-typedef enum
-{
-    ETH_DMATXDESC_LASTSEGMENTS = BIT30, /*!< Actual Tx desc contain last segment */
-    ETH_DMATXDESC_FIRSTSEGMENT = BIT29  /*!< Actual Tx desc contain first segment */
-} ETH_DMATXDESC_SEGMENTS_T;
-
-/**
- * @brief    ETH DMA Tx descriptor Checksum Insertion Control
- */
-typedef enum
-{
-    ETH_DMATXDESC_CHECKSUMBYPASS,                       /*!< Checksum bypass */
-    ETH_DMATXDESC_CHECKSUMIPV4HEADER = BIT22,           /*!< IPv4 header checksum */
-    ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT = BIT23,    /*!< TCP/UDP/ICMP checksum. Pseudo header
-                                                            checksum is assumed to be present */
-    ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL = BIT22|BIT23  /*!< TCP/UDP/ICMP checksum fully in hardware
-                                                            including pseudo header */
-} ETH_DMATXDESC_CHECKSUMB_T;
-
-/**
- * @brief    DMA Rx descriptor status
- */
-typedef enum
-{
-    ETH_DMARXDESC_OWN      =  (int)0x80000000U, /*!< Descriptor is owned by DMA engine */
-    ETH_DMARXDESC_ADDRF    =  0x40000000,       /*!< DA Filter Fail for the rx frame */
-    ETH_DMARXDESC_ERRS     =  0x00008000,       /*!< Error summary */
-    ETH_DMARXDESC_DESERR   =  0x00004000,       /*!< Descriptor error: no more descriptors for receive frame */
-    ETH_DMARXDESC_SADDRF   =  0x00002000,       /*!< SA Filter Fail for the received frame */
-    ETH_DMARXDESC_LERR     =  0x00001000,       /*!< Frame size not matching with length field */
-    ETH_DMARXDESC_OFERR    =  0x00000800,       /*!< Overflow Error: Frame was damaged due to buffer overflow */
-    ETH_DMARXDESC_VLANF    =  0x00000400,       /*!< VLAN Tag: received frame is a VLAN frame */
-    ETH_DMARXDESC_FDES     =  0x00000200,       /*!< First descriptor of the frame */
-    ETH_DMARXDESC_LDES     =  0x00000100,       /*!< Last descriptor of the frame */
-    ETH_DMARXDESC_IPV4HCE  =  0x00000080,       /*!< IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error */
-    ETH_DMARXDESC_LC       =  0x00000040,       /*!< Late collision occurred during reception */
-    ETH_DMARXDESC_FT       =  0x00000020,       /*!< Frame type - Ethernet, otherwise 802.3 */
-    ETH_DMARXDESC_RXWDTTO  =  0x00000010,       /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-    ETH_DMARXDESC_RERR     =  0x00000008,       /*!< Receive error: error reported by MII interface */
-    ETH_DMARXDESC_DERR     =  0x00000004,       /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-    ETH_DMARXDESC_CERR     =  0x00000002,       /*!< CRC error */
-    ETH_DMARXDESC_MAMPCE   =  0x00000001        /*!< Rx MAC Address/Payload Checksum Error:
-                                                    Rx MAC address matched/ Rx Payload Checksum Error */
-} ETH_DMARXDESC_FLAG_T;
-
-/**
- * @brief    DMA Rx descriptor extended flags
- */
-typedef enum
-{
-    ETH_DMAPTPRXDESC_PTPV   =  0x00002000,  /*!< PTP version */
-    ETH_DMAPTPRXDESC_PTPFT  =  0x00001000,  /*!< PTP frame type */
-    ETH_DMAPTPRXDESC_PTPMT  =  0x00000F00,  /*!< PTP message type */
-    ETH_DMAPTPRXDESC_IPV6P  =  0x00000080,  /*!< IPv6 packet received */
-    ETH_DMAPTPRXDESC_IPV4P  =  0x00000040,  /*!< IPv4 packet received */
-    ETH_DMAPTPRXDESC_IPCBP  =  0x00000020,  /*!< IP checksum bypassed */
-    ETH_DMAPTPRXDESC_IPPERR =  0x00000010,  /*!< IP payload error */
-    ETH_DMAPTPRXDESC_IPHERR =  0x00000008,  /*!< IP header error */
-    ETH_DMAPTPRXDESC_IPPT   =  0x00000007   /*!< IP payload type */
-} ETH_DMAPTPRXDESC_FLAG_T;
-
-/**
- * @brief    ETH DMA Rx descriptor buffers
- */
-typedef enum
-{
-    ETH_DMARXDESC_BUFFER1,  /*!< DMA Rx Desc Buffer1 */
-    ETH_DMARXDESC_BUFFER2   /*!< DMA Rx Desc Buffer2 */
-} ETH_DMARXDESC_BUFFER_T;
-
-/**
- * @brief    ETH Drop TCP IP Checksum Error Frame
- */
-typedef enum
-{
-    ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE,     /*!< Enable dropping of TCP/IP checksum error frame */
-    ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE     /*!< Disable dropping of TCP/IP checksum error frame */
-} ETH_DROPTCPIPCHECKSUMERRORFRAME_T;
-
-/**
- * @brief    ETH Receive Store Forward
- */
-typedef enum
-{
-    ETH_RECEIVESTOREFORWARD_DISABLE,    /*!< Disable receive store and forward */
-    ETH_RECEIVESTOREFORWARD_ENABLE      /*!< Enable receive store and forward */
-} ETH_RECEIVESTOREFORWARD_T;
-
-/**
- * @brief    ETH Flush Received Frame
- */
-typedef enum
-{
-    ETH_FLUSHRECEIVEDFRAME_ENABLE,  /*!< Enable flushing of received frames */
-    ETH_FLUSHRECEIVEDFRAME_DISABLE  /*!< Disable flushing of received frames */
-} ETH_FLUSHRECEIVEDFRAME_T;
-
-/**
- * @brief    ETH Transmit Store Forward
- */
-typedef enum
-{
-    ETH_TRANSMITSTOREFORWARD_DISABLE,   /*!< Disable transmit store and forward */
-    ETH_TRANSMITSTOREFORWARD_ENABLE     /*!< Enable transmit store and forward */
-} ETH_TRANSMITSTOREFORWARD_T;
-
-/**
- * @brief    ETH Transmit Threshold Control
- */
-typedef enum
-{
-    ETH_TRANSMITTHRESHOLDCONTROL_64BYTES,   /*!< Select 64 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_128BYTES,  /*!< Select 128 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_192BYTES,  /*!< Select 192 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_256BYTES,  /*!< Select 256 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_40BYTES,   /*!< Select 40 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_32BYTES,   /*!< Select 32 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_24BYTES,   /*!< Select 24 bytes transmit threshild level */
-    ETH_TRANSMITTHRESHOLDCONTROL_16BYTES    /*!< Select 16 bytes transmit threshild level */
-} ETH_TRANSMITTHRESHOLDCONTROL_T;
-
-/**
- * @brief    ETH Forward Error Frames
- */
-typedef enum
-{
-    ETH_FORWARDERRORFRAMES_DISABLE, /*!< Disable forward error frames */
-    ETH_FORWARDERRORFRAMES_ENABLE   /*!< Enable forward error frames */
-} ETH_FORWARDERRORFRAMES_T;
-
-/**
- * @brief    ETH Forward Undersized Good Frames
- */
-typedef enum
-{
-    ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE,    /*!< Disable forward undersized good frames */
-    ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE      /*!< Enable forward undersized good frames */
-} ETH_FORWARDUNDERSIZEDGOODFRAMES_T;
-
-/**
- * @brief    ETH Receive Threshold Control
- */
-typedef enum
-{
-    ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES,   /*!< Select 64 bytes receive threshold level */
-    ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES,   /*!< Select 32 bytes receive threshold level */
-    ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES,   /*!< Select 96 bytes receive threshold level */
-    ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES   /*!< Select 128 bytes receive threshold level */
-} ETH_RECEIVEDTHRESHOLDCONTROL_T;
-
-/**
- * @brief    ETH Second Frame Operate
- */
-typedef enum
-{
-    ETH_SECONDFRAMEOPERARTE_DISABLE,    /*!< Disable second frame operate */
-    ETH_SECONDFRAMEOPERARTE_ENABLE      /*!< Enable second frame operate */
-} ETH_SECONDFRAMEOPERARTE_T;
-
-/**
- * @brief    ETH Address Aligned Beats
- */
-typedef enum
-{
-    ETH_ADDRESSALIGNEDBEATS_DISABLE,    /*!< Disable address aligned beats */
-    ETH_ADDRESSALIGNEDBEATS_ENABLE      /*!< Enable address aligned beats */
-} ETH_ADDRESSALIGNEDBEATS_T;
-
-/**
- * @brief    ETH Fixed Burst
- */
-typedef enum
-{
-    ETH_FIXEDBURST_DISABLE, /*!< Disable fixed burst */
-    ETH_FIXEDBURST_ENABLE   /*!< Enable fixed burst */
-} ETH_FIXEDBURST_T;
-
-/**
- * @brief    ETH Rx DMA Burst Length
- */
-typedef enum
-{
-    ETH_RXDMABURSTLENGTH_1BEAT        = BIT17,          /*!< Maxnum number of Rx DMA transaction = 1 beat */
-    ETH_RXDMABURSTLENGTH_2BEAT        = BIT18,          /*!< Maxnum number of Rx DMA transaction = 2 beat */
-    ETH_RXDMABURSTLENGTH_4BEAT        = BIT19,          /*!< Maxnum number of Rx DMA transaction = 4 beat */
-    ETH_RXDMABURSTLENGTH_8BEAT        = BIT20,          /*!< Maxnum number of Rx DMA transaction = 8 beat */
-    ETH_RXDMABURSTLENGTH_16BEAT       = BIT21,          /*!< Maxnum number of Rx DMA transaction = 16 beat */
-    ETH_RXDMABURSTLENGTH_32BEAT       = BIT22,          /*!< Maxnum number of Rx DMA transaction = 32 beat */
-    ETH_RXDMABURSTLENGTH_4XPBL_4BEAT  = BIT17|BIT24,    /*!< Maxnum number of Rx DMA transaction = 4 beat */
-    ETH_RXDMABURSTLENGTH_4XPBL_8BEAT  = BIT18|BIT24,    /*!< Maxnum number of Rx DMA transaction = 8 beat */
-    ETH_RXDMABURSTLENGTH_4XPBL_16BEAT = BIT19|BIT24,    /*!< Maxnum number of Rx DMA transaction = 16 beat */
-    ETH_RXDMABURSTLENGTH_4XPBL_32BEAT = BIT20|BIT24,    /*!< Maxnum number of Rx DMA transaction = 32 beat */
-    ETH_RXDMABURSTLENGTH_4XPBL_64BEAT = BIT21|BIT24,    /*!< Maxnum number of Rx DMA transaction = 64 beat */
-    ETH_RXDMABURSTLENGTH_4XPBL_128BEAT= BIT22|BIT24     /*!< Maxnum number of Rx DMA transaction = 128 beat */
-} ETH_RXDMABURSTLENGTH_T;
-
-/**
- * @brief    ETH Tx DMA Burst Length
- */
-typedef enum
-{
-    ETH_TXDMABURSTLENGTH_1BEAT        = BIT8,           /*!< Maxnum number of Tx DMA transaction = 1 beat */
-    ETH_TXDMABURSTLENGTH_2BEAT        = BIT9,           /*!< Maxnum number of Tx DMA transaction = 2 beat */
-    ETH_TXDMABURSTLENGTH_4BEAT        = BIT10,          /*!< Maxnum number of Tx DMA transaction = 4 beat */
-    ETH_TXDMABURSTLENGTH_8BEAT        = BIT11,          /*!< Maxnum number of Tx DMA transaction = 8 beat */
-    ETH_TXDMABURSTLENGTH_16BEAT       = BIT12,          /*!< Maxnum number of Tx DMA transaction = 16 beat */
-    ETH_TXDMABURSTLENGTH_32BEAT       = BIT13,          /*!< Maxnum number of Tx DMA transaction = 32 beat */
-    ETH_TXDMABURSTLENGTH_4XPBL_4BEAT  = BIT8|BIT24,     /*!< Maxnum number of Tx DMA transaction = 4 beat */
-    ETH_TXDMABURSTLENGTH_4XPBL_8BEAT  = BIT9|BIT24,     /*!< Maxnum number of Tx DMA transaction = 8 beat */
-    ETH_TXDMABURSTLENGTH_4XPBL_16BEAT = BIT10|BIT24,    /*!< Maxnum number of Tx DMA transaction = 16 beat */
-    ETH_TXDMABURSTLENGTH_4XPBL_32BEAT = BIT11|BIT24,    /*!< Maxnum number of Tx DMA transaction = 32 beat */
-    ETH_TXDMABURSTLENGTH_4XPBL_64BEAT = BIT12|BIT24,    /*!< Maxnum number of Tx DMA transaction = 64 beat */
-    ETH_TXDMABURSTLENGTH_4XPBL_128BEAT= BIT13|BIT24     /*!< Maxnum number of Tx DMA transaction = 128 beat */
-} ETH_TXDMABURSTLENGTH_T;
-
-/**
- * @brief    ETH DMA Arbitration
- */
-typedef enum
-{
-    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1,                 /*!< Priority ratio RX : TX = 1 : 1 */
-    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 = BIT14,         /*!< Priority ratio RX : TX = 2 : 1 */
-    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 = BIT15,         /*!< Priority ratio RX : TX = 3 : 1 */
-    ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 = BIT14|BIT15,   /*!< Priority ratio RX : TX = 4 : 1 */
-    ETH_DMAARBITRATION_RXPRIORTX = BIT1                     /*!< Rx priority ratio higher than Tx */
-} ETH_DMAARBITRATION_T;
-
-/**
- * @brief    ETH DMA Flags
- */
-typedef enum
-{
-    ETH_DMA_FLAG_TST               = 0x20000000,   /*!< Time-stamp trigger interrupt (on DMA) */
-    ETH_DMA_FLAG_PMT               = 0x10000000,   /*!< PMT interrupt (on DMA) */
-    ETH_DMA_FLAG_MMC               = 0x08000000,   /*!< MMC interrupt (on DMA) */
-    ETH_DMA_FLAG_DATATRANSFERERROR = 0x00800000,   /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-    ETH_DMA_FLAG_READWRITEERROR    = 0x01000000,   /*!< Error bits 0-write transfer, 1-read transfer */
-    ETH_DMA_FLAG_ACCESSERROR       = 0x02000000,   /*!< Error bits 0-data buffer, 1-desc. access */
-    ETH_DMA_FLAG_NIS               = 0x00010000,   /*!< Normal interrupt summary flag */
-    ETH_DMA_FLAG_AIS               = 0x00008000,   /*!< Abnormal interrupt summary flag */
-    ETH_DMA_FLAG_ER                = 0x00004000,   /*!< Early receive flag */
-    ETH_DMA_FLAG_FBE               = 0x00002000,   /*!< Fatal bus error flag */
-    ETH_DMA_FLAG_ET                = 0x00000400,   /*!< Early transmit flag */
-    ETH_DMA_FLAG_RWT               = 0x00000200,   /*!< Receive watchdog timeout flag */
-    ETH_DMA_FLAG_RPS               = 0x00000100,   /*!< Receive process stopped flag */
-    ETH_DMA_FLAG_RBU               = 0x00000080,   /*!< Receive buffer unavailable flag */
-    ETH_DMA_FLAG_RX                = 0x00000040,   /*!< Receive flag */
-    ETH_DMA_FLAG_TU                = 0x00000020,   /*!< Underflow flag */
-    ETH_DMA_FLAG_RO                = 0x00000010,   /*!< Overflow flag */
-    ETH_DMA_FLAG_TJT               = 0x00000008,   /*!< Transmit jabber timeout flag */
-    ETH_DMA_FLAG_TBU               = 0x00000004,   /*!< Transmit buffer unavailable flag */
-    ETH_DMA_FLAG_TPS               = 0x00000002,   /*!< Transmit process stopped flag */
-    ETH_DMA_FLAG_TX                = 0x00000001    /*!< Transmit flag */
-} ETH_DMA_FLAG_T;
-
-/**
- * @brief    ETH DMA Interrupts
- */
-typedef enum
-{
-    ETH_DMA_INT_TST   =   0x20000000,   /*!< Time-stamp trigger interrupt (on DMA) */
-    ETH_DMA_INT_PMT   =   0x10000000,   /*!< PMT interrupt (on DMA) */
-    ETH_DMA_INT_MMC   =   0x08000000,   /*!< MMC interrupt (on DMA) */
-    ETH_DMA_INT_NIS   =   0x00010000,   /*!< Normal interrupt summary */
-    ETH_DMA_INT_AIS   =   0x00008000,   /*!< Abnormal interrupt summary */
-    ETH_DMA_INT_ER    =   0x00004000,   /*!< Early receive interrupt */
-    ETH_DMA_INT_FBE   =   0x00002000,   /*!< Fatal bus error interrupt */
-    ETH_DMA_INT_ET    =   0x00000400,   /*!< Early transmit interrupt */
-    ETH_DMA_INT_RWT   =   0x00000200,   /*!< Receive watchdog timeout interrupt */
-    ETH_DMA_INT_RPS   =   0x00000100,   /*!< Receive process stopped interrupt */
-    ETH_DMA_INT_RBU   =   0x00000080,   /*!< Receive buffer unavailable interrupt */
-    ETH_DMA_INT_RX    =   0x00000040,   /*!< Receive interrupt */
-    ETH_DMA_INT_TU    =   0x00000020,   /*!< Underflow interrupt */
-    ETH_DMA_INT_RO    =   0x00000010,   /*!< Overflow interrupt */
-    ETH_DMA_INT_TJT   =   0x00000008,   /*!< Transmit jabber timeout interrupt */
-    ETH_DMA_INT_TBU   =   0x00000004,   /*!< Transmit buffer unavailable interrupt */
-    ETH_DMA_INT_TPS   =   0x00000002,   /*!< Transmit process stopped interrupt */
-    ETH_DMA_INT_TX    =   0x00000001    /*!< Transmit interrupt */
-} ETH_DMA_INT_T;
-
-/**
- * @brief    ETH DMA transmit process state
- */
-typedef enum
-{
-    ETH_DMA_TRANSMITPROCESS_STOPPED,            /*!< Stopped - Reset or Stop Tx Command issued */
-    ETH_DMA_TRANSMITPROCESS_FETCHING,           /*!< Running - fetching the Tx descriptor */
-    ETH_DMA_TRANSMITPROCESS_WAITING,            /*!< Running - waiting for status */
-    ETH_DMA_TRANSMITPROCESS_READING,            /*!< Running - reading the data from host memory */
-    ETH_DMA_TRANSMITPROCESS_SUSPENDED = 0x06,   /*!< Suspended - Tx Descriptor unavailable */
-    ETH_DMA_TRANSMITPROCESS_CLOSING = 0x07,     /*!< Running - closing Rx descriptor */
-} ETH_DMA_TRANSMITPROCESS_T;
-
-/**
- * @brief    ETH DMA receive process state
- */
-typedef enum
-{
-    ETH_DMA_RECEIVEPROCESS_STOPPED,             /*!< Stopped - Reset or Stop Rx Command issued */
-    ETH_DMA_RECEIVEPROCESS_FETCHING  = 0x02,    /*!< Running - fetching the Rx descriptor */
-    ETH_DMA_RECEIVEPROCESS_WAITING   = 0x06,    /*!< Running - waiting for packet */
-    ETH_DMA_RECEIVEPROCESS_SUSPENDED = 0x08,    /*!< Suspended - Rx Descriptor unavailable */
-    ETH_DMA_RECEIVEPROCESS_CLOSING   = 0x0A,    /*!< Running - closing descriptor */
-    ETH_DMA_RECEIVEPROCESS_QUEUING   = 0x0E     /*!< Running - queuing the receive frame into host memory */
-} ETH_DMA_RECEIVEPROCESS_T;
-
-/**
- * @brief    ETH DMA overflow
- */
-typedef enum
-{
-    ETH_DMA_OVERFLOW_RXFIFOCOUNTER = BIT28,     /*!< Overflow for FIFO Overflows Counter */
-    ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER = BIT16 /*!< Overflow for Buffer Unavailable Missed Frame Counter */
-} ETH_DMA_OVERFLOW_T;
-
-/**
- * @brief    ETH PMT Flags
- */
-typedef enum
-{
-    ETH_PMT_FLAG_WUFFRPR = (int)BIT31,  /*!< Wake-Up Frame Filter Register Pointer Reset */
-    ETH_PMT_FLAG_WUFR = BIT6,           /*!< Wake-Up Frame Received */
-    ETH_PMT_FLAG_MPR = BIT5             /*!< Magic Packet Received */
-} ETH_PMT_FLAG_T;
-
-/**
- * @brief    ETH MMC Tx/RX Interrupts
- */
-typedef enum
-{
-    ETH_MMC_INT_TGF    = BIT21,         /*!< When Tx good frame counter reaches half the maximum value */
-    ETH_MMC_INT_TGFMSC = BIT15,         /*!< When Tx good multi col counter reaches half the maximum value */
-    ETH_MMC_INT_TGFSC  = BIT14,         /*!< When Tx good single col counter reaches half the maximum value */
-    ETH_MMC_INT_RGUF   = BIT21|BIT30,   /*!< When Rx good unicast frames counter reaches half the maximum value */
-    ETH_MMC_INT_RFAE   = BIT6|BIT30,    /*!< When Rx alignment error counter reaches half the maximum value */
-    ETH_MMC_INT_RFCE   = BIT5|BIT30     /*!< When Rx crc error counter reaches half the maximum value */
-} ETH_MMC_INT_T;
-
-/**
- * @brief    ETH MMC Registers
- */
-typedef enum
-{
-    ETH_MMC_CTRL       =  0x00000100,   /*!< MMC CTRL register */
-    ETH_MMC_RXINT      =  0x00000104,   /*!< MMC RXINT register */
-    ETH_MMC_TXINT      =  0x00000108,   /*!< MMC TXINT register */
-    ETH_MMC_RXINTMASK  =  0x0000010C,   /*!< MMC RXINTMASK register */
-    ETH_MMC_TXINTMASK  =  0x00000110,   /*!< MMC TXINTMASK register */
-    ETH_MMC_TXGFSCCNT  =  0x0000014C,   /*!< MMC TXGFSCCNT register */
-    ETH_MMC_TXGFMCCNT  =  0x00000150,   /*!< MMC TXGFMCCNT register */
-    ETH_MMC_TXGFCNT    =  0x00000168,   /*!< MMC TXGFCNT register */
-    ETH_MMC_RXFCECNT   =  0x00000194,   /*!< MMC RXFCECNT register */
-    ETH_MMC_RXFAECNT   =  0x00000198,   /*!< MMC RXFAECNT register */
-    ETH_MMC_RXGUNCNT   =  0x000001C4    /*!< MMC RXGUNCNT register */
-} ETH_MMC_REG_T;
-
-/**@} end of group ETH_Enumerations*/
-
-
-/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
-  @{
-  */
-
-/**
-*  DMA Tx Descriptor
-*  -----------------------------------------------------------------------------------------------
-*  TXDES0 | OWN(31) | CTRL[30:25] | Reserved(24) | CTRL[23:20] | Reserved[19:18] | Status[17:0]   |
-*  -----------------------------------------------------------------------------------------------
-*  TXDES1 | Reserved[31:29] | Buffer2 Size[28:16] | Reserved[15:13] | Buffer1 Size[12:0]          |
-*  -----------------------------------------------------------------------------------------------
-*  TXDES2 |                         Buffer1 Address [31:0]                                        |
-*  -----------------------------------------------------------------------------------------------
-*  TXDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]             |
-*  -----------------------------------------------------------------------------------------------
-*/
-
-/**
-  * @brief  Bit definition of TXDES0 register: DMA Tx descriptor status register
-  */
-#define ETH_DMATXDESC_OWN                     0x80000000U   /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_INTC                    0x40000000U   /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS                      0x20000000U   /*!< Last Segment */
-#define ETH_DMATXDESC_FS                      0x10000000U   /*!< First Segment */
-#define ETH_DMATXDESC_DISC                    0x08000000U   /*!< Disable CRC */
-#define ETH_DMATXDESC_DISP                    0x04000000U   /*!< Disable Padding */
-#define ETH_DMATXDESC_TXTSEN                  0x02000000U   /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC                     0x00C00000U   /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS              0x00000000U   /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER          0x00400000U   /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  0x00800000U   /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     0x00C00000U   /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TXENDR                  0x00200000U   /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TXCH                    0x00100000U   /*!< Second Address Chained */
-#define ETH_DMATXDESC_TXTSS                   0x00020000U   /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHERR                   0x00010000U   /*!< IP Header Error */
-#define ETH_DMATXDESC_ERRS                    0x00008000U   /*!< Error summary: OR of the following bits: UFERR || EDEF || EC || LC || NC || LSC || FF || JTO */
-#define ETH_DMATXDESC_JTO                     0x00004000U   /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF                      0x00002000U   /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_IPERR                   0x00001000U   /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LSC                     0x00000800U   /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC                      0x00000400U   /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LC                      0x00000200U   /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC                      0x00000100U   /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VLANF                   0x00000080U   /*!< VLAN Frame */
-#define ETH_DMATXDESC_CCNT                    0x00000078U   /*!< Collision Count */
-#define ETH_DMATXDESC_EDEF                    0x00000004U   /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UFERR                   0x00000002U   /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DEF                     0x00000001U   /*!< Deferred Bit */
-
-/**
-  * @brief  Bit definition of TXDES1 register
-  */
-#define ETH_DMATXDESC_TXBS2  0x1FFF0000U /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TXBS1  0x00001FFFU /*!< Transmit Buffer1 Size */
-
-/**
-  * @brief  Bit definition of TXDES2 register
-  */
-#define ETH_DMATXDESC_B1AP  0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-
-/**
-  * @brief  Bit definition of TXDES3 register
-  */
-#define ETH_DMATXDESC_B2AP  0xFFFFFFFFU /*!< Buffer2 Address Pointer */
-
-/**
-*  ---------------------------------------------------------------------------------------------
-*  TXDES6 |                         Transmit Time Stamp Low [31:0]                               |
-*  ---------------------------------------------------------------------------------------------
-*  TXDES7 |                         Transmit Time Stamp High [31:0]                              |
-*  ----------------------------------------------------------------------------------------------
-*/
-
-/** Bit definition of TXDES6 register */
-#define ETH_DMAPTPTXDESC_TXTSL  0xFFFFFFFFU  /*!< Transmit Time Stamp Low */
-
-/** Bit definition of TXDES7 register */
-#define ETH_DMAPTPTXDESC_TXTSH  0xFFFFFFFFU  /*!< Transmit Time Stamp High */
-
-/**
-  * @}
-  */
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
-  @{
-  */
-
-/**
-  *DMA Rx Descriptor
-  *--------------------------------------------------------------------------------------------------------------------
-  *RXDES0 | OWN(31) |                                             Status [30:0]                                         |
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES1 | CTRL(31) | Reserved[30:29] | Buffer2 Size[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 Size[12:0]          |
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES2 |                                       Buffer1 Address [31:0]                                                |
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                            |
-  *---------------------------------------------------------------------------------------------------------------------
-*/
-
-/**
-  * @brief  Bit definition of RXDES0 register: DMA Rx descriptor status register
-  */
-#define ETH_DMARXDESC_OWN         0x80000000U   /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_ADDRF       0x40000000U   /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL          0x3FFF0000U   /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ERRS        0x00008000U   /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DESERR      0x00004000U   /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SADDRF      0x00002000U   /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LERR        0x00001000U   /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OFERR       0x00000800U   /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLANF       0x00000400U   /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FDES        0x00000200U   /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LDES        0x00000100U   /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE     0x00000080U   /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC          0x00000040U   /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT          0x00000020U   /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RXWWTTO     0x00000010U   /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RERR        0x00000008U   /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DERR        0x00000004U   /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CERR        0x00000002U   /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE      0x00000001U   /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-
-/**
-  * @brief  Bit definition of RXDES1 register
-  */
-#define ETH_DMARXDESC_DINTC  0x80000000U /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RXBS2  0x1FFF0000U /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RXER   0x00008000U /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RXCH   0x00004000U /*!< Second Address Chained */
-#define ETH_DMARXDESC_RXBS1  0x00001FFFU /*!< Receive Buffer1 Size */
-
-/**
-  * @brief  Bit definition of RXDES2 register
-  */
-#define ETH_DMARXDESC_B1AP  0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-
-/**
-  * @brief  Bit definition of RXDES3 register
-  */
-#define ETH_DMARXDESC_B2AP  0xFFFFFFFFU /*!< Buffer2 Address Pointer */
-
-/**
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES4 |                   Reserved[31:14]              |             Extended Status [13:0]                         |
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES5 |                                            Reserved[31:0]                                                   |
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES6 |                                       Receive Time Stamp Low [31:0]                                         |
-  *---------------------------------------------------------------------------------------------------------------------
-  *RXDES7 |                                       Receive Time Stamp High [31:0]                                        |
-  *---------------------------------------------------------------------------------------------------------------------
-*/
-
-/** Bit definition of RXDES4 register */
-#define ETH_DMAPTPRXDESC_PTPV     0x00002000U                           /*!< PTP Version */
-#define ETH_DMAPTPRXDESC_PTPFT    0x00001000U                           /*!< PTP Frame Type */
-#define ETH_DMAPTPRXDESC_PTPMT    0x00000F00U                           /*!< PTP Message Type */
-#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      0x00000100U    /*!< SYNC message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  0x00000200U    /*!< FollowUp message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  0x00000300U    /*!< DelayReq message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 0x00000400U    /*!< DelayResp message (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        0x00000500U    /*!< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          0x00000600U    /*!< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U    /*!< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_IPV6P    0x00000080U                           /*!< IPv6 Packet Received */
-#define ETH_DMAPTPRXDESC_IPV4P    0x00000040U                           /*!< IPv4 Packet Received */
-#define ETH_DMAPTPRXDESC_IPCBP    0x00000020U                           /*!< IP Checksum Bypassed */
-#define ETH_DMAPTPRXDESC_IPPERR   0x00000010U                           /*!< IP Payload Error */
-#define ETH_DMAPTPRXDESC_IPHERR   0x00000008U                           /*!< IP Header Error */
-#define ETH_DMAPTPRXDESC_IPPT     0x00000007U                           /*!< IP Payload Type */
-#define ETH_DMAPTPRXDESC_IPPT_UDP                 0x00000001U           /*!< UDP payload encapsulated in the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_TCP                 0x00000002U           /*!< TCP payload encapsulated in the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_ICMP                0x00000003U           /*!< ICMP payload encapsulated in the IP datagram */
-
-/** Bit definition of RXDES6 register */
-#define ETH_DMAPTPRXDESC_RXTSL  0xFFFFFFFFU  /*!< Receive Time Stamp Low */
-
-/** Bit definition of RXDES7 register */
-#define ETH_DMAPTPRXDESC_RXTSH  0xFFFFFFFFU  /*!< Receive Time Stamp High */
-/**
-  * @}
-  */
-
-
-/** @addtogroup ETH_Macros Macros
-  *@{
-  */
-
-/** ETH Frames defines */
-
-/** Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE  /*!< buffer size for receive */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE  /*!< buffer size for transmit */
-#define ETH_RXBUFNB                    (10U)                /*!< 10 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB                    (10U)                /*!< 10 Tx buffers of size ETH_TX_BUF_SIZE */
-
-/** ETH_Buffers_setting ETH Buffers setting */
-#define ETH_MAX_PACKET_SIZE       1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER                14U   /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC                   4U    /*!< Ethernet CRC */
-#define ETH_EXTRA                 2U    /*!< Extra bytes in some cases */
-#define ETH_VLAN_TAG              4U    /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD       46U   /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD       1500U /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD   9000U /*!< Jumbo frame payload size */
-
-/**
-*  Ethernet driver receive buffers are organized in a chained linked-list, when
-*  an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
-*  to the driver receive buffers memory.
-*
-*  Depending on the size of the received ethernet packet and the size of
-*  each ethernet driver receive buffer, the received packet can take one or more
-*  ethernet driver receive buffer.
-*
-*  In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
-*  and the total count of the driver receive buffers ETH_RXBUFNB.
-*
-*  The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
-*  example, they can be reconfigured in the application layer to fit the application
-*  needs
-*/
-
-/** Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
-*   packet
-*/
-#ifndef ETH_RX_BUF_SIZE
-#define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE
-#endif
-
-/** 5 Ethernet driver receive buffers are used (in a chained linked list)*/
-#ifndef ETH_RXBUFNB
-#define ETH_RXBUFNB             5U  /*!< 5 Rx buffers of size ETH_RX_BUF_SIZE */
-#endif
-
-/**
-*  Ethernet driver transmit buffers are organized in a chained linked-list, when
-*  an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
-*  driver transmit buffers memory to the TxFIFO.
-*
-*  Depending on the size of the Ethernet packet to be transmitted and the size of
-*  each ethernet driver transmit buffer, the packet to be transmitted can take
-*  one or more ethernet driver transmit buffer.
-*
-*  In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
-*  and the total count of the driver transmit buffers ETH_TXBUFNB.
-*
-*  The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
-*  example, they can be reconfigured in the application layer to fit the application
-*  needs
-*/
-
-/** Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
-*   packet
-*/
-#ifndef ETH_TX_BUF_SIZE
-#define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
-#endif
-
-/** 5 ethernet driver transmit buffers are used (in a chained linked list)*/
-#ifndef ETH_TXBUFNB
-#define ETH_TXBUFNB             5U  /*!< 5  Tx buffers of size ETH_TX_BUF_SIZE */
-#endif
-
-/** ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE   (ETH_MAC_BASE + 0x40)      /*!< ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE    (ETH_MAC_BASE + 0x44)     /*!< ETHERNET MAC address low offset */
-
-/** ETHERNET Errors */
-#define  ETH_SUCCESS            1U
-#define  ETH_ERROR              0U
-
-/** ETHERNET DMA Tx descriptors Collision Count Shift */
-#define  ETH_DMATXDESC_COLLISION_COUNTSHIFT        3U
-
-/** ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16U
-
-/** ETHERNET DMA Rx descriptors Frame Length Shift */
-#define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16U
-
-/** ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16U
-
-/** ETHERNET DMA Rx descriptors Frame length Shift */
-#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            16U
-
-/** ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK    0xFFFFFFE3U
-
-/** ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK    0xFF20010FU
-
-/** ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK   0x0000FF41U
-
-/** ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK   0xF8DE3F23U
-
-/** ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH      8U
-
-/** ETHERNET Missed frames counter Shift */
-#define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U
-
-/** PHY registers defines */
-
-/** PHY Read write Timeouts */
-#define PHY_READ_TIMEOUT                ((uint32_t)0x0004FFFF)
-#define PHY_WRITE_TIMEOUT               ((uint32_t)0x0004FFFF)
-
-/** PHY Register address */
-#define PHY_BCR                                      0         /*!< Transceiver Basic Control Register */
-#define PHY_BSR                                      1         /*!< Transceiver Basic Status Register */
-#define PHY_SR                                       16        /*!< Transceiver Status Register for dp83848 */
-
-/** PHY Status Register (PHYSTS), address 0x10 */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)     /*!< for dp83848 ((uint16_t)0x0010) */
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002)     /*!< for dp83848 ((uint16_t)0x0004) */
-
-/** PHY basic status register */
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)     /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)     /*!< Valid link established */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)     /*!< Jabber condition detected */
-
-/** PHY basic Control register */
-#define PHY_RESET                       ((uint16_t)0x8000)     /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)     /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)     /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)     /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)     /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)     /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)     /*!< Enable auto-negotiation function */
-#define PHY_RESTAET_AUTONEGOTIATION     ((uint16_t)0x0200)     /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)     /*!< Select the power down mode */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)     /*!< Isolate PHY from MII */
-
-/** PHY Delay */
-#define PHY_RESET_DELAY                 ((uint32_t)0x000FFFFF) /*!< PHY reset delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00FFFFFF) /*!< PHY configuration delay */
-/** Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY             ((uint32_t)0x0000FFFF)
-
-/** Ethernet MAC MII Address Clock Range*/
-#define ETH_MACMIIAR_CR_DIV42   ((uint8_t)0x00)                 /*!< HCLK:60-100 MHz; MDC clock = HCLK/42 */
-#define ETH_MACMIIAR_CR_DIV62   ((uint8_t)0x01)                 /*!< HCLK:100-150 MHz; MDC clock = HCLK/62 */
-#define ETH_MACMIIAR_CR_DIV16   ((uint8_t)0x02)                 /*!< HCLK:20-35 MHz; MDC clock = HCLK/16 */
-#define ETH_MACMIIAR_CR_DIV26   ((uint8_t)0x03)                 /*!< HCLK:35-60 MHz; MDC clock = HCLK/26 */
-#define ETH_MACMIIAR_CR_DIV102  ((uint8_t)0x04)                 /*!< HCLK:150-168 MHz; MDC clock = HCLK/102 */
-
-/** Control the Enhanced DMA descriptors */
-#define USE_ENHANCED_DMA_DESCRIPTORS     1
-
-/**@} end of group ETH_Macros */
-
-
-/** @addtogroup ETH_Structure Data Structure
-  @{
-*/
-
-/**
- * @brief    ETH MAC Config structure types
- */
-typedef struct
-{
-    /** MAC Configuration */
-    ETH_AUTONEGOTIATION_T           autoNegotiation;            /*!< Selects or not the AutoNegotiation mode for the external PHY
-                                                                    The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
-                                                                    and the mode (half/full-duplex) */
-
-    ETH_WATCHDOG_T                  watchDog;                   /*!< Selects or not the Watchdog timer
-                                                                    When enabled, the MAC allows no more then 2048 bytes to be received.
-                                                                    When disabled, the MAC can receive up to 16384 bytes. */
-
-    ETH_JABBER_T                    jabber;                     /*!< Selects or not Jabber timer
-                                                                    When enabled, the MAC allows no more then 2048 bytes to be sent.
-                                                                    When disabled, the MAC can send up to 16384 bytes. */
-    ETH_INTERFRAMEGAP_T             interFrameGap;              /*!< Selects the minimum IFG between frames during transmission */
-
-    ETH_CARRIERSENCE_T              carrierSense;               /*!< Selects or not the Carrier Sense */
-
-    ETH_SPEED_T                     speed;                      /*!< Sets the Ethernet speed: 10/100 Mbps */
-
-    ETH_RECEIVEOWN_T                receiveOwn;                 /*!< Selects or not the ReceiveOwn
-                                                                    ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
-                                                                    in Half-Duplex mode */
-
-    ETH_LOOPBACKMODE_T              loopbackMode;               /*!< Selects or not the internal MAC MII Loopback mode */
-
-    ETH_MODE_T                      mode;                       /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
-
-    ETH_CHECKSUMOFFLAOD_T           checksumOffload;            /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. */
-
-    ETH_RETRYTRANSMISSION_T         retryTransmission;          /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
-                                                                    when a collision occurs (Half-Duplex mode) */
-
-    ETH_AUTOMATICPADCRCSTRIP_T      automaticPadCRCStrip;       /*!< Selects or not the Automatic MAC Pad/CRC Stripping */
-
-    ETH_BACKOFFLIMIT_T              backOffLimit;               /*!< Selects the BackOff limit value */
-
-    ETH_DEFFERRALCHECK_T            deferralCheck;              /*!< Selects or not the deferral check function (Half-Duplex mode) */
-
-    ETH_RECEIVEAll_T                receiveAll;                 /*!< Selects or not all frames reception by the MAC (No filtering) */
-
-    ETH_SOURCEADDRFILTER_T          sourceAddrFilter;           /*!< Selects the Source Address Filter mode */
-
-    ETH_PASSCONTROLFRAMES_T         passControlFrames;          /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) */
-
-    ETH_BROADCASTFRAMESRECEPTION_T  broadcastFramesReception;   /*!< Selects or not the reception of Broadcast Frames */
-
-    ETH_DESTINATIONADDRFILTER_T     destinationAddrFilter;      /*!< Sets the destination filter mode for both unicast and multicast frames */
-
-    ETH_PROMISCUOUS_MODE_T          promiscuousMode;            /*!< Selects or not the Promiscuous Mode */
-
-    ETH_MULTICASTFRAMESFILTER_T     multicastFramesFilter;      /*!< Selects the Multicast Frames filter mode */
-
-    ETH_UNICASTFRAMESFILTER_T       unicastFramesFilter;        /*!< Selects the Unicast Frames filter mode */
-
-
-    uint32_t                        hashTableHigh;              /*!< This field holds the higher 32 bits of Hash table. */
-
-    uint32_t                        hashTableLow;               /*!< This field holds the lower 32 bits of Hash table. */
-
-    uint32_t                        pauseTime;                  /*!< This field holds the (value<=0xFFFF) to be used in the Pause Time */
-
-    ETH_ZEROQUANTAPAUSE_T           zeroQuantaPause;            /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames */
-
-    ETH_PAUSELOWTHRESHOLD_T         pauseLowThreshold;          /*!< This field configures the threshold of the PAUSE to be checked for
-                                                                    automatic retransmission of PAUSE Frame */
-
-    ETH_UNICASTPAUSEFRAMEDETECT_T   unicastPauseFrameDetect;    /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
-                                                                    unicast address and unique multicast address) */
-
-    ETH_RECEIVEFLOWCONTROL_T        receiveFlowControl;         /*!< Enables or disables the MAC to decode the received Pause frame and
-                                                                    disable its transmitter for a specified time (Pause Time) */
-
-    ETH_TRANSMITFLOWCONTROL_T       transmitFlowControl;        /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
-                                                                    or the MAC back-pressure operation (Half-Duplex mode) */
-
-    ETH_VLANTAGCOMPARISON_T         VLANTagComparison;          /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
-                                                                    comparison and filtering */
-
-    uint32_t                        VLANTagIdentifier;          /*!< Holds the (value <=0xFFFF) VLAN tag identifier for receive frames */
-
-    /** DMA Configuration */
-    ETH_DROPTCPIPCHECKSUMERRORFRAME_T   dropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */
-
-    ETH_RECEIVESTOREFORWARD_T           receiveStoreForward;         /*!< Enables or disables the Receive store and forward mode */
-
-    ETH_FLUSHRECEIVEDFRAME_T            flushReceivedFrame;          /*!< Enables or disables the flushing of received frames */
-
-    ETH_TRANSMITSTOREFORWARD_T          transmitStoreForward;        /*!< Enables or disables Transmit store and forward mode */
-
-    ETH_TRANSMITTHRESHOLDCONTROL_T      transmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control */
-
-    ETH_FORWARDERRORFRAMES_T            forwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames */
-
-    ETH_FORWARDUNDERSIZEDGOODFRAMES_T   forwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
-                                                                        and length less than 64 bytes) including pad-bytes and CRC) */
-
-    ETH_RECEIVEDTHRESHOLDCONTROL_T      receiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO */
-
-    ETH_SECONDFRAMEOPERARTE_T           secondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
-                                                                        frame of Transmit data even before obtaining the status for the first frame. */
-
-    ETH_ADDRESSALIGNEDBEATS_T           addressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats */
-
-    ETH_FIXEDBURST_T                    fixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers */
-
-    ETH_RXDMABURSTLENGTH_T              rxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction */
-
-    ETH_TXDMABURSTLENGTH_T              txDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction */
-
-    uint32_t                            descriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) (value <= 0x1F) */
-
-    ETH_DMAARBITRATION_T                DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration */
-} ETH_Config_T;
-
-/**
-  * @brief  ETH DMA Descriptors data structure types
-  */
-typedef struct
-{
-    __IO uint32_t   Status;                            /*!< Status */
-    uint32_t        ControlBufferSize;                 /*!< Control and Buffer1, Buffer2 lengths */
-    uint32_t        Buffer1Addr;                       /*!< Buffer1 address pointer */
-    uint32_t        Buffer2NextDescAddr;               /*!< Buffer2 or next descriptor address pointer */
-    /* Enhanced ETHERNET DMA PTP Descriptors */
-    #if USE_ENHANCED_DMA_DESCRIPTORS
-    uint32_t        ExtendedStatus;                    /*!< Extended status for PTP receive descriptor */
-    uint32_t        Reserved1;                         /*!< Reserved */
-    uint32_t        TimeStampLow;                      /*!< Time Stamp Low value for transmit and receive */
-    uint32_t        TimeStampHigh;                     /*!< Time Stamp High value for transmit and receive */
-    #endif /* USE_ENHANCED_DMA_DESCRIPTORS */
-} ETH_DMADescConfig_T;
-
-/**
-  * @brief  ETH DMA Descriptors data structure types
-  */
-typedef struct
-{
-    uint32_t        length;                 /*!< Data length */
-    uint32_t        buffer;                 /*!< Data buffer */
-    __IO ETH_DMADescConfig_T *descriptor;   /*!< DMA descriptor */
-} ETH_Frame_T;
-
-/**
-  * @brief  ETH DMA Descriptors Received Frame Informations structure types
-  */
-typedef struct  {
-  __IO ETH_DMADescConfig_T   *FS_RxDesc;              /*!< First Segment Rx Desc */
-  __IO ETH_DMADescConfig_T   *LS_RxDesc;              /*!< Last Segment Rx Desc */
-  __IO uint32_t               segCount;               /*!< Segment count */
-} ETH_DMARxFrameInformations;
-
-/**@} end of group ETH_Structure*/
-
-/** @defgroup ETH_Functions
-  @{
-*/
-
-/* ETH Configuration */
-void ETH_Reset(void);
-void ETH_ConfigStructInit(ETH_Config_T* ethConfig);
-uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr);
-void ETH_SoftwareReset(void);
-uint8_t ETH_ReadSoftwareReset(void);
-void ETH_Start(void);
-void ETH_Stop(void);
-uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T *DMARxDesc);
-#if USE_ENHANCED_DMA_DESCRIPTORS
-void ETH_EnableEnhancedDescriptor(void);
-void ETH_DisableEnhancedDescriptor(void);
-#endif /*!< USE_ENHANCED_DMA_DESCRIPTORS */
-
-/* PHY */
-uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg);
-uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data);
-uint32_t ETH_EnablePHYLoopBack(uint16_t addr);
-uint32_t ETH_DisablePHYLoopBack(uint16_t addr);
-
-/* MAC */
-void ETH_EnableMACTransmission(void);
-void ETH_DisableMACTransmission(void);
-void ETH_EnableMACReceiver(void);
-void ETH_DisableMACReceiver(void);
-uint8_t ETH_ReadFlowControlBusyStatus(void);
-void ETH_SetPauseControlFrame(void);
-void ETH_EnableBackPressureActivation(void);
-void ETH_DisableBackPressureActivation(void);
-uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag);
-void ETH_EnableMACInterrupt(uint32_t interrupt);
-void ETH_DisableMACInterrupt(uint32_t interrupt);
-void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr);
-void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr);
-void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr);
-void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr);
-void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter);
-void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte);
-
-/* DMA descriptors */
-void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T *DMARxDescTab, uint8_t *rxBuff, uint32_t rxBuffcount);
-void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T *DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount);
-uint32_t ETH_CheckReceivedFrame(void);
-uint32_t ETH_Transmit_Descriptors(u16 frameLength);
-ETH_Frame_T ETH_ReadReceivedFrame(void);
-uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_FLAG_T flag);
-uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment);
-void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum);
-void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc);
-void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T *DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2);
-uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_FLAG_T flag);
-#if USE_ENHANCED_DMA_DESCRIPTORS
-uint8_t ETH_ReadDMAPTPRxDescExtendedFlagStatus(ETH_DMADescConfig_T *DMAPTPRxDesc, ETH_DMAPTPRXDESC_FLAG_T flag);
-#endif
-void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T *DMARxDesc);
-uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T *DMARxDesc);
-void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMARxDesc);
-void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMATxDesc);
-uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer);
-ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void);
-
-/* DMA */
-uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag);
-void ETH_ClearDMAFlag(uint32_t flag);
-uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag);
-void ETH_ClearDMAIntFlag(uint32_t flag);
-uint32_t ETH_ReadTransmitProcessState(void);
-uint32_t ETH_ReadReceiveProcessState(void);
-void ETH_FlushTransmitFIFO(void);
-uint8_t ETH_ReadFlushTransmitFIFOStatus(void);
-void ETH_EnableDMATransmission(void);
-void ETH_DisableDMATransmission(void);
-void ETH_EnableDMAReceiver(void);
-void ETH_DisableDMAReceiver(void);
-void ETH_EnableDMAInterrupt(uint32_t interrupt);
-void ETH_DisableDMAInterrupt(uint32_t interrupt);
-uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow);
-uint32_t ETH_ReadRxOverflowMissedFrameCounter(void);
-uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void);
-uint32_t ETH_ReadCurrentTxDescStartAddress(void);
-uint32_t ETH_ReadCurrentRxDescStartAddress(void);
-uint32_t ETH_ReadCurrentTxBufferAddress(void);
-uint32_t ETH_ReadCurrentRxBufferAddress(void);
-void ETH_ResetDMATransmission(void);
-void ETH_ResetDMAReception(void);
-void ETH_ConfigReceiveWatchdogTimer(uint8_t value);
-
-/* PMT */
-void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
-void ETH_ConfigWakeUpFrameFilterRegister(uint32_t *buffer);
-void ETH_EnableGlobalUnicastWakeUp(void);
-void ETH_DisableGlobalUnicastWakeUp(void);
-uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag);
-void ETH_EnableWakeUpFrameDetection(void);
-void ETH_DisableWakeUpFrameDetection(void);
-void ETH_EnableMagicPacketDetection(void);
-void ETH_DisableMagicPacketDetection(void);
-void ETH_EnablePowerDown(void);
-void ETH_DisablePowerDown(void);
-
-/* MMC */
-void ETH_PresetMMCCounterFull(void);
-void ETH_PresetMMCCounterHalf(void);
-void ETH_EnableMMCCounterFreeze(void);
-void ETH_DisableMMCCounterFreeze(void);
-void ETH_EnableMMCResetOnRead(void);
-void ETH_DisableMMCResetOnRead(void);
-void ETH_EnableMMCCounterRollover(void);
-void ETH_DisableMMCCounterRollover(void);
-void ETH_ResetMMCCounters(void);
-void ETH_EnableMMCInterrupt(uint32_t interrupt);
-void ETH_DisableMMCInterrupt(uint32_t interrupt);
-uint8_t ETH_ReadMMCIntFlag(uint32_t flag);
-uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /** __APM32F4xx_ETH_H */
-
-/**@} end of group ETH_Functions */
-/**@} end of group ETH_Driver */
-/**@} end of group APM32F4xx_ETHDriver */

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_ETH_Driver/src/apm32f4xx_eth.c

@@ -1,2303 +0,0 @@
-/*!
- * @file        apm32f4xx_eth.c
- *
- * @brief       This file provides all the ETH firmware functions
- *
- * @version     V1.0.2
- *
- * @date        2022-06-23
- *
- * @attention
- *
- *  Copyright (C) 2021-2022 Geehy Semiconductor
- *
- *  You may not use this file except in compliance with the
- *  GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
- *
- *  The program is only for reference, which is distributed in the hope
- *  that it will be usefull and instructional for customers to develop
- *  their software. Unless required by applicable law or agreed to in
- *  writing, the program is distributed on an "AS IS" BASIS, WITHOUT
- *  ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
- *  and limitations under the License.
- */
-
-#include "apm32f4xx_eth.h"
-#include "apm32f4xx_rcm.h"
-
-/** @addtogroup APM32F4xx_ETHDriver
-  @{
-*/
-
-/** @defgroup ETH_Driver
-  * @brief ETH driver modules
-  @{
-*/
-
-#if defined   (__CC_ARM) /*!< ARM Compiler */
-__align(4)
-ETH_DMADescConfig_T  DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */
-__align(4)
-ETH_DMADescConfig_T  DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */
-__align(4)
-uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];  /*!< Ethernet Receive Buffer */
-__align(4)
-uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];  /*!< Ethernet Transmit Buffer */
-
-#elif defined ( __ICCARM__ )
-
-ETH_DMADescConfig_T  DMARxDscrTab[ETH_RXBUFNB]; /*!< Ethernet Rx MA Descriptor */
-ETH_DMADescConfig_T  DMATxDscrTab[ETH_TXBUFNB]; /*!< Ethernet Tx DMA Descriptor */
-uint8_t Rx_Buff[ETH_RXBUFNB][ETH_RX_BUF_SIZE];  /*!< Ethernet Receive Buffer */
-uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];  /*!< Ethernet Transmit Buffer */
-
-#endif
-
-/** @defgroup Global_Definition
-  @{
-*/
-
-/* Global pointers on Tx and Rx descriptor used to transmit and receive descriptors */
-__IO ETH_DMADescConfig_T  *DMATxDescToSet;
-__IO ETH_DMADescConfig_T  *DMARxDescToGet;
-
-/* Structure used to hold the last received packet descriptors info */
-ETH_DMARxFrameInformations      RxFrameDescriptor;
-__IO ETH_DMARxFrameInformations *DMARxFraminfos;
-__IO uint32_t FrameRxindex;
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Functions
-  @{
-*/
-
-/*!
- * @brief  Inserts a delay time.
- *
- * @param  count: specifies the delay time length.
- *
- * @retval None
- */
-static void ETH_Delay(__IO uint32_t count)
-{
-    __IO uint32_t i = 0;
-    for(i = count; i!= 0; i--)
-    {
-    }
-}
-
-/** ETH Configuration */
-
-/*!
- * @brief  Reset ETH peripheral registers to their default reset values.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_Reset(void)
-{
-    RCM_EnableAHB1PeriphReset(RCM_AHB1_PERIPH_ETH_MAC);
-    RCM_DisableAHB1PeriphReset(RCM_AHB1_PERIPH_ETH_MAC);
-}
-
-/*!
- * @brief  Config ETH_Config_T member with its default value.
- *
- * @param  ethConfig: pointer to a ETH_Config_T structure which will be initialized.
- *
- * @retval None
- */
-void ETH_ConfigStructInit(ETH_Config_T* ethConfig)
-{
-    /* MAC Configuration */
-    ethConfig->autoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
-    ethConfig->watchDog = ETH_WATCHDOG_ENABLE;
-    ethConfig->jabber = ETH_JABBER_ENABLE;
-    ethConfig->interFrameGap = ETH_INTERFRAMEGAP_96BIT;
-    ethConfig->carrierSense = ETH_CARRIERSENCE_ENABLE;
-    ethConfig->speed = ETH_SPEED_100M;
-    ethConfig->receiveOwn = ETH_RECEIVEOWN_ENABLE;
-    ethConfig->loopbackMode = ETH_LOOPBACKMODE_DISABLE;
-    ethConfig->mode = ETH_MODE_FULLDUPLEX;
-    ethConfig->checksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
-    ethConfig->retryTransmission = ETH_RETRYTRANSMISSION_ENABLE;
-    ethConfig->automaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
-    ethConfig->backOffLimit = ETH_BACKOFFLIMIT_10;
-    ethConfig->deferralCheck = ETH_DEFFERRALCHECK_DISABLE;
-    ethConfig->receiveAll = ETH_RECEIVEAll_DISABLE;
-    ethConfig->sourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
-    ethConfig->passControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
-    ethConfig->broadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_DISABLE;
-    ethConfig->destinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
-    ethConfig->promiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
-    ethConfig->multicastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
-    ethConfig->unicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
-    ethConfig->hashTableHigh = 0x0000;
-    ethConfig->hashTableLow = 0x0000;
-    ethConfig->pauseTime = 0x0000;
-    ethConfig->zeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
-    ethConfig->pauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
-    ethConfig->unicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
-    ethConfig->receiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
-    ethConfig->transmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
-    ethConfig->VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
-    ethConfig->VLANTagIdentifier = 0x0000;
-    /* DMA Configuration */
-    ethConfig->dropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE;
-    ethConfig->receiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
-    ethConfig->flushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
-    ethConfig->transmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
-    ethConfig->transmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
-    ethConfig->forwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
-    ethConfig->forwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
-    ethConfig->receiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
-    ethConfig->secondFrameOperate = ETH_SECONDFRAMEOPERARTE_DISABLE;
-    ethConfig->addressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
-    ethConfig->fixedBurst = ETH_FIXEDBURST_ENABLE;
-    ethConfig->rxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
-    ethConfig->txDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
-    ethConfig->descriptorSkipLength = 0x00;
-    ethConfig->DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
-}
-
-/*!
- * @brief  Config the ETH peripheral parameters in the ethConfig.
- *
- * @param  ethConfig: pointer to a ETH_Config_T structure.
- *
- * @param  addr: external PHY address
- *
- * @retval ETH_ERROR: Ethernet initialization error
- *         ETH_SUCCESS: Ethernet initialization success
- */
-uint32_t ETH_Config(ETH_Config_T* ethConfig, uint16_t addr)
-{
-    uint32_t regValue = 0;
-    uint32_t hclk = 60000000;
-    __IO uint32_t timeout = 0, err = ETH_SUCCESS;
-
-    hclk = RCM_ReadHCLKFreq();
-
-    if((hclk >= 20000000) && (hclk <= 35000000))
-    {
-        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV16;
-    }
-    else if((hclk >= 35000000)&&(hclk < 60000000))
-    {
-        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV26;
-    }
-    else if((hclk >= 60000000)&&(hclk < 100000000))
-    {
-        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV42;
-    }
-    else if((hclk >= 100000000)&&(hclk < 150000000))
-    {
-        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV62;
-    }
-    else
-    {
-        ETH->ADDR_B.CR = ETH_MACMIIAR_CR_DIV102;
-    }
-
-    /* PHY initialization and configuration */
-    if(!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_RESET)))
-    {
-    /* Return ERROR in case of write timeout */
-    err = ETH_ERROR;
-    goto error;
-    }
-
-    ETH_Delay(PHY_RESET_DELAY);
-
-    if(ethConfig->autoNegotiation == ETH_AUTONEGOTIATION_ENABLE)
-    {
-        /* Wait for linked status */
-        do
-        {
-            timeout++ ;
-        } while(!(ETH_ReadPHYRegister(addr,PHY_BSR) & PHY_LINKED_STATUS) && (timeout < PHY_READ_TIMEOUT));
-
-        /* Return ERROR in case of timeout */
-        if(timeout == PHY_READ_TIMEOUT)
-        {
-            err = ETH_ERROR;
-            goto error;
-        }
-
-        timeout = 0;
-        /* Enable Auto-Negotiation */
-        if(!(ETH_WritePHYRegister(addr, PHY_BCR, PHY_AUTONEGOTIATION)))
-        {
-            /* Return ERROR in case of write timeout */
-            err = ETH_ERROR;
-        }
-
-        /* Wait until the auto-negotiation will be completed */
-        do
-        {
-        timeout++;
-        } while (!(ETH_ReadPHYRegister(addr, PHY_BSR) & PHY_AUTONEGO_COMPLETE) && (timeout < (uint32_t)PHY_READ_TIMEOUT));
-
-        /* Return ERROR in case of timeout */
-        if(timeout == PHY_READ_TIMEOUT)
-        {
-            err = ETH_ERROR;
-            goto error;
-        }
-
-        timeout = 0;
-        /* Read the result of the auto-negotiation */
-        regValue = ETH_ReadPHYRegister(addr, PHY_SR);
-
-        if((regValue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
-        {
-            ethConfig->mode = ETH_MODE_FULLDUPLEX;
-        }
-        else
-        {
-            ethConfig->mode = ETH_MODE_HALFDUPLEX;
-        }
-        if(regValue & PHY_SPEED_STATUS)
-        {
-            ethConfig->speed = ETH_SPEED_10M;
-        }
-        else
-        {
-            ethConfig->speed = ETH_SPEED_100M;
-        }
-    }
-    else
-    {
-        if(!ETH_WritePHYRegister(addr, PHY_BCR,((uint16_t)(ethConfig->speed << 8) |
-                                                (uint16_t)(ethConfig->mode  << 13))))
-        {
-            err = ETH_ERROR;
-        }
-
-        ETH_Delay(PHY_CONFIG_DELAY);
-    }
-error:
-    if(err == ETH_ERROR)
-    {
-        ethConfig->speed = ETH_SPEED_100M;
-        ethConfig->mode = ETH_MODE_FULLDUPLEX;
-    }
-
-    /* ETHERNET MAC_CFG Configuration */
-    ETH->CFG_B.WDTDIS = ethConfig->watchDog;
-    ETH->CFG_B.JDIS   = ethConfig->jabber;
-    ETH->CFG_B.IFG    = ethConfig->interFrameGap;
-    ETH->CFG_B.DISCRS = ethConfig->carrierSense;
-    ETH->CFG_B.SSEL   = ethConfig->speed;
-    ETH->CFG_B.DISRXO = ethConfig->receiveOwn;
-    ETH->CFG_B.LBM    = ethConfig->loopbackMode;
-    ETH->CFG_B.DM     = ethConfig->mode;
-    ETH->CFG_B.IPC    = ethConfig->checksumOffload;
-    ETH->CFG_B.DISR   = ethConfig->retryTransmission;
-    ETH->CFG_B.ACS    = ethConfig->automaticPadCRCStrip;
-    ETH->CFG_B.BL     = ethConfig->backOffLimit;
-    ETH->CFG_B.DC     = ethConfig->deferralCheck;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-
-    /* ETHERNET MAC_FRAF Configuration */
-    ETH->FRAF_B.RXA    = ethConfig->receiveAll;
-    ETH->FRAF         |= ethConfig->sourceAddrFilter;
-    ETH->FRAF_B.PCTRLF = ethConfig->passControlFrames;
-    ETH->FRAF_B.DISBF  = ethConfig->broadcastFramesReception;
-    ETH->FRAF_B.DAIF   = ethConfig->destinationAddrFilter;
-    ETH->FRAF_B.PR     = ethConfig->promiscuousMode;
-    ETH->FRAF         |= ethConfig->multicastFramesFilter;
-    ETH->FRAF         |= ethConfig->unicastFramesFilter;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-
-    /* ETHERNET MAC_HTH/HTL Configuration */
-    ETH->HTH = ethConfig->hashTableHigh;
-    ETH->HTL = ethConfig->hashTableLow;
-
-    /* ETHERNET MAC_FCTRL Configuration */
-    ETH->FCTRL_B.PT        = ethConfig->pauseTime;
-    ETH->FCTRL_B.ZQPDIS    = ethConfig->zeroQuantaPause;
-    ETH->FCTRL_B.PTSEL     = ethConfig->pauseLowThreshold;
-    ETH->FCTRL_B.UNPFDETE  = ethConfig->unicastPauseFrameDetect;
-    ETH->FCTRL_B.RXFCTRLEN = ethConfig->receiveFlowControl;
-    ETH->FCTRL_B.TXFCTRLEN = ethConfig->transmitFlowControl;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-
-    /* ETHERNET MAC_VLANT Configuration */
-    ETH->VLANT_B.VLANTCOMP = ethConfig->VLANTagComparison;
-    ETH->VLANT_B.VLANTID   = ethConfig->VLANTagIdentifier;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-
-    /* ETHERNET DMA_OPMOD Configuration */
-    ETH->DMAOPMOD_B.DISDT    = ethConfig->dropTCPIPChecksumErrorFrame;
-    ETH->DMAOPMOD_B.RXSF     = ethConfig->receiveStoreForward;
-    ETH->DMAOPMOD_B.DISFRXF  = ethConfig->flushReceivedFrame;
-    ETH->DMAOPMOD_B.TXSF     = ethConfig->transmitStoreForward;
-    ETH->DMAOPMOD_B.TXTHCTRL = ethConfig->transmitThresholdControl;
-    ETH->DMAOPMOD_B.FERRF    = ethConfig->forwardErrorFrames;
-    ETH->DMAOPMOD_B.FUF      = ethConfig->forwardUndersizedGoodFrames;
-    ETH->DMAOPMOD_B.RXTHCTRL = ethConfig->receiveThresholdControl;
-    ETH->DMAOPMOD_B.OSECF    = ethConfig->secondFrameOperate;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-
-    /* ETHERNET DMA_BMOD Configuration */
-    ETH->DMABMOD = RESET;
-    ETH->DMABMOD_B.AAL = ethConfig->addressAlignedBeats;
-    ETH->DMABMOD_B.FB = ethConfig->fixedBurst;
-    ETH->DMABMOD |= ethConfig->rxDMABurstLength;
-    ETH->DMABMOD |= ethConfig->txDMABurstLength;
-    ETH->DMABMOD_B.DSL = ethConfig->descriptorSkipLength;
-    ETH->DMABMOD |= ethConfig->DMAArbitration;
-    ETH->DMABMOD_B.USP = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-
-#if USE_ENHANCED_DMA_DESCRIPTORS
-    ETH->DMABMOD_B.EDFEN = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-#endif
-
-    if(err == ETH_SUCCESS)
-    {
-        return ETH_SUCCESS;
-    }
-    else
-    {
-        return ETH_ERROR;
-    }
-}
-
-/*!
- * @brief  Resets all MAC subsystem internal registers and logic.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_SoftwareReset(void)
-{
-    ETH->DMABMOD_B.SWR = SET;
-}
-
-/*!
- * @brief  Read the ETH software reset bit.
- *
- * @param  None
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadSoftwareReset(void)
-{
-    return ETH->DMABMOD_B.SWR;
-}
-
-/*!
- * @brief     Enables ETH MAC and DMA reception/transmission
- *
- * @param     None
- *
- * @retval    None
- */
-void ETH_Start(void)
-{
-    ETH_EnableMACTransmission();
-    ETH_EnableMACReceiver();
-    ETH_FlushTransmitFIFO();
-    ETH_EnableDMATransmission();
-    ETH_EnableDMAReceiver();
-}
-
-/*!
- * @brief     Disables ETH MAC and DMA reception/transmission
- *
- * @param     None
- *
- * @retval    None
- */
-void ETH_Stop(void)
-{
-    ETH_DisableDMATransmission();
-    ETH_DisableDMAReceiver();
-    ETH_DisableMACReceiver();
-    ETH_FlushTransmitFIFO();
-    ETH_DisableMACTransmission();
-}
-
-/*!
- * @brief  Read the size of the received packet.
- *
- * @param  None
- *
- * @retval frameLength: received packet size
- */
-uint32_t ETH_ReadRxPacketSize(ETH_DMADescConfig_T *DMARxDesc)
-{
-    uint32_t frameLength = 0;
-    if(((DMARxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
-       ((DMARxDesc->Status & ETH_DMARXDESC_ERRS)  == (uint32_t)RESET) &&
-       ((DMARxDesc->Status & ETH_DMARXDESC_LDES)  != (uint32_t)RESET))
-    {
-        frameLength =  ETH_ReadDMARxDescFrameLength(DMARxDesc);
-    }
-    return frameLength;
-}
-
-#if USE_ENHANCED_DMA_DESCRIPTORS
-/*!
- * @brief  Enable the Enhanced descriptor structure.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableEnhancedDescriptor(void)
-{
-     ETH->DMABMOD_B.EDFEN = SET;
-}
-
-/*!
- * @brief  Disable the Enhanced descriptor structure.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableEnhancedDescriptor(void)
-{
-     ETH->DMABMOD_B.EDFEN = RESET;
-}
-#endif /** USE_ENHANCED_DMA_DESCRIPTORS */
-
-/** PHY functions */
-
-/*!
- * @brief  Read a PHY register
- *
- * @param  addr: PHY device address
- *               This parameter can be one of the following values: 0,..,31
- *
- * @param  reg:  PHY register
- *               This parameter can be one of the following values:
- *               @arg PHY_BCR : Transceiver Basic Control Register
- *               @arg PHY_BSR : Transceiver Basic Status Register
- *               @arg PHY_SR  :  Transceiver Status Register
- *
- * @retval ETH_ERROR: in case of timeout
- *         MAC DATA register value: Data read from the selected PHY register
- */
-uint16_t ETH_ReadPHYRegister(uint16_t addr, uint16_t reg)
-{
-    __IO uint32_t timeout = 0;
-
-    ETH->ADDR_B.PA = addr;
-    ETH->ADDR_B.MR = reg;
-    ETH->ADDR_B.MW = RESET;
-    ETH->ADDR_B.MB = SET;
-    /* Check for the Busy flag */
-    do
-    {
-        timeout++ ;
-    } while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_READ_TIMEOUT));
-    /* Return ERROR in case of timeout */
-    if(timeout == PHY_READ_TIMEOUT)
-    {
-        return ETH_ERROR;
-    }
-    /* Return data register value */
-    return (uint16_t)(ETH->DATA);
-}
-
-/*!
- * @brief  Write to a PHY register
- *
- * @param  addr: PHY device address
- *               This parameter can be one of the following values: 0,..,31
-
- * @param  reg:  PHY register
- *               This parameter can be one of the following values:
- *               @arg PHY_BCR : Transceiver Basic Control Register
-
- * @param  data: the data to write
- *
- * @retval ETH_ERROR: write timeout
- *         ETH_SUCCESS: write success
- */
-uint32_t ETH_WritePHYRegister(uint16_t addr, uint16_t reg, uint16_t data)
-{
-    __IO uint32_t timeout = 0;
-
-    ETH->DATA = data;
-    ETH->ADDR_B.PA = addr;
-    ETH->ADDR_B.MR = reg;
-    ETH->ADDR_B.MW = SET;
-    ETH->ADDR_B.MB = SET;
-
-    /* Check for the Busy flag */
-    do
-    {
-        timeout++ ;
-    } while ((ETH->ADDR_B.MB == SET) && (timeout < PHY_WRITE_TIMEOUT));
-    /* Return ERROR in case of timeout */
-    if(timeout == PHY_WRITE_TIMEOUT)
-    {
-        return ETH_ERROR;
-    }
-    /* Return data register value */
-    return ETH_SUCCESS;
-}
-
-/*!
- * @brief  Enable the PHY loopBack mode.
- *
- * @param  addr: PHY device address
- *               This parameter can be one of the following values: 0,..,31
- *
- * @retval ETH_ERROR or ETH_SUCCESS
- */
-uint32_t ETH_EnablePHYLoopBack(uint16_t addr)
-{
-    uint16_t temp = 0;
-
-    temp = ETH_ReadPHYRegister(addr,PHY_BCR);
-    temp |= PHY_LOOPBACK;
-
-    if(ETH_WritePHYRegister(addr,PHY_BCR,temp) == SET)
-    {
-        return ETH_SUCCESS;
-    }
-    else
-    {
-        return ETH_ERROR;
-    }
-}
-
-/*!
- * @brief  Disable the PHY loopBack mode.
- *
- * @param  addr: PHY device address
- *               This parameter can be one of the following values: 0,..,31
- *
- * @retval ETH_ERROR or ETH_SUCCESS
- */
-uint32_t ETH_DisablePHYLoopBack(uint16_t addr)
-{
-    uint16_t temp = 0;
-
-    temp = ETH_ReadPHYRegister(addr,PHY_BCR);
-    temp &= ((uint16_t)~PHY_LOOPBACK);
-
-    if(ETH_WritePHYRegister(addr,PHY_BCR,temp) == SET)
-    {
-        return ETH_SUCCESS;
-    }
-    else
-    {
-        return ETH_ERROR;
-    }
-}
-
-/* MAC functions */
-
-/*!
- * @brief  Enable the MAC transmission.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableMACTransmission(void)
-{
-    ETH->CFG_B.TXEN = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the MAC transmission.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableMACTransmission(void)
-{
-    ETH->CFG_B.TXEN = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Enable the MAC receiver.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableMACReceiver(void)
-{
-    ETH->CFG_B.RXEN = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the MAC receiver.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableMACReceiver(void)
-{
-    ETH->CFG_B.RXEN = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Read the ETH flow control busy status
- *
- * @param  None
- *
- * @retval SET or RESET
- */
-uint8_t ETH_ReadFlowControlBusyStatus(void)
-{
-    return ETH->FCTRL_B.FCTRLB;
-}
-
-/*!
- * @brief  Set a Pause Control Frame (Full-duplex only).
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_SetPauseControlFrame(void)
-{
-    ETH->FCTRL_B.FCTRLB = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Enable the MAC Back Pressure operation activation (Half-duplex only).
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableBackPressureActivation(void)
-{
-    ETH->FCTRL_B.FCTRLB = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the MAC Back Pressure operation activation (Half-duplex only).
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableBackPressureActivation(void)
-{
-    ETH->FCTRL_B.FCTRLB = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Read the specified ETH MAC flag
- *
- * @param  flag: Ethernet MAC flag:
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
- *           @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
- *           @arg ETH_MAC_FLAG_MMCR : MMC receive flag
- *           @arg ETH_MAC_FLAG_MMC  : MMC flag
- *           @arg ETH_MAC_FLAG_PMT  : PMT flag
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadMACFlagStatus(ETH_MAC_FLAG_T flag)
-{
-    return (ETH->ISTS & flag) ? SET : RESET;
-}
-
-/*!
- * @brief  Enable the specified ETH MAC interrupts.
- *
- * @param  interrupt: Ethernet MAC interrupt flag:
- *         This parameter can be any combination of the following values:
- *           @arg ETH_MAC_INT_TST : Time stamp trigger interrupt
- *           @arg ETH_MAC_INT_PMT : PMT interrupt
- *
- * @retval None
- */
-void ETH_EnableMACInterrupt(uint32_t interrupt)
-{
-    ETH->IMASK |= interrupt;
-}
-
-/*!
- * @brief  Disable the specified ETH MAC interrupts.
- *
- * @param  interrupt: Ethernet MAC interrupt flag:
- *         This parameter can be any combination of the following values:
- *           @arg ETH_MAC_INT_TST : Time stamp trigger interrupt
- *           @arg ETH_MAC_INT_PMT : PMT interrupt
- *
- * @retval None
- */
-void ETH_DisableMACInterrupt(uint32_t interrupt)
-{
-    ETH->IMASK &= (~(uint32_t)interrupt);
-}
-
-/*!
- * @brief  Config the MAC address.
- *
- * @param  macAddr: The MAC address.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESS0 : MAC Address0
- *           @arg ETH_MAC_ADDRESS1 : MAC Address1
- *           @arg ETH_MAC_ADDRESS2 : MAC Address2
- *           @arg ETH_MAC_ADDRESS3 : MAC Address3
- *
- * @param  addr: Pointer on MAC address buffer data (6 bytes).
- *
- * @retval None
- */
-void ETH_ConfigMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr)
-{
-    uint32_t temp;
-
-    temp = ((uint32_t)addr[5] << 8) | (uint32_t)addr[4];
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp;
-
-    temp = ((uint32_t)addr[3] << 24) | ((uint32_t)addr[2] << 16) | ((uint32_t)addr[1] << 8) | addr[0];
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + macAddr)) = temp;
-}
-
-/*!
- * @brief  Read the MAC address.
- *
- * @param  macAddr: The MAC address.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESS0 : MAC Address0
- *           @arg ETH_MAC_ADDRESS1 : MAC Address1
- *           @arg ETH_MAC_ADDRESS2 : MAC Address2
- *           @arg ETH_MAC_ADDRESS3 : MAC Address3
- *
- * @param  addr: Pointer on MAC address buffer data (6 bytes).
- *
- * @retval None
- */
-void ETH_ReadMACAddress(ETH_MAC_ADDRESS_T macAddr, uint8_t *addr)
-{
-    uint32_t temp;
-
-    temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr));
-
-    addr[5] = ((temp >> 8) & 0xFF);
-    addr[4] = (temp & 0xFF);
-
-    temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + macAddr));
-    addr[3] = ((temp >> 24) & 0xFF);
-    addr[2] = ((temp >> 16) & 0xFF);
-    addr[1] = ((temp >> 8)  & 0xFF);
-    addr[0] = (temp & 0xFF);
-}
-
-/*!
- * @brief  Enable address filters module uses the MAC address for perfect filtering.
- *
- * @param  macAddr: The MAC address.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESS1 : MAC Address1
- *           @arg ETH_MAC_ADDRESS2 : MAC Address2
- *           @arg ETH_MAC_ADDRESS3 : MAC Address3
- *
- * @retval None
- */
-void ETH_EnableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr)
-{
-    __IO uint32_t temp = 0;
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= BIT31;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp;
-}
-
-/*!
- * @brief  Disable address filters module uses the MAC address for perfect filtering.
- *
- * @param  macAddr: The MAC address.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESS1 : MAC Address1
- *           @arg ETH_MAC_ADDRESS2 : MAC Address2
- *           @arg ETH_MAC_ADDRESS3 : MAC Address3
- *
- * @retval None
- */
-void ETH_DisableMACAddressPerfectFilter(ETH_MAC_ADDRESS_T macAddr)
-{
-    __IO uint32_t temp = 0;
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) &= (~BIT31);
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp;
-}
-
-/*!
- * @brief  Config the filter type for the MAC address
- *
- * @param  macAddr: The MAC address.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESS1 : MAC Address1
- *           @arg ETH_MAC_ADDRESS2 : MAC Address2
- *           @arg ETH_MAC_ADDRESS3 : MAC Address3
- *
- * @param  filter: Comparison with the SA/DA fields of the received frame.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESSFILTER_SA : MAC Address is used to compare with the
- *                                           SA fields of the received frame.
- *           @arg ETH_MAC_ADDRESSFILTER_DA : MAC Address is used to compare with the
- *                                           DA fields of the received frame.
- * @retval None
- */
-void ETH_ConfigMACAddressFilter(ETH_MAC_ADDRESS_T macAddr, ETH_MAC_ADDRESSFILTER_T filter)
-{
-    if(filter == ETH_MAC_ADDRESSFILTER_SA)
-    {
-        (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_SA;
-    }
-    else
-    {
-        (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= ETH_MAC_ADDRESSFILTER_DA;
-    }
-
-}
-
-/*!
- * @brief  Config the filter type for the ETH MAC address.
- *
- * @param  macAddr: The MAC address.
- *         This parameter can be one of the following values:
- *           @arg ETH_MAC_ADDRESS1 : MAC Address1
- *           @arg ETH_MAC_ADDRESS2 : MAC Address2
- *           @arg ETH_MAC_ADDRESS3 : MAC Address3
- *
- * @param  MaskByte: specifies the used address bytes for comparison
- *         This parameter can be any combination of the following values:
- *           @arg ETH_MAC_ADDRESSMASK_BYTE6 : Mask MAC Address high reg bits [15:8].
- *           @arg ETH_MAC_ADDRESSMASK_BYTE5 : Mask MAC Address high reg bits [7:0].
- *           @arg ETH_MAC_ADDRESSMASK_BYTE4 : Mask MAC Address low reg bits [31:24].
- *           @arg ETH_MAC_ADDRESSMASK_BYTE3 : Mask MAC Address low reg bits [23:16].
- *           @arg ETH_MAC_ADDRESSMASK_BYTE2 : Mask MAC Address low reg bits [15:8].
- *           @arg ETH_MAC_ADDRESSMASK_BYTE1 : Mask MAC Address low reg bits [7:0].
- *
- * @retval None
- */
-void ETH_ConfigMACAddressMaskBytesFilter(ETH_MAC_ADDRESS_T macAddr, uint32_t maskByte)
-{
-    __IO uint32_t temp = 0;
-
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) &=(~(uint32_t)0x3F000000);
-
-    temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr));
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp;
-
-    /* Set the selected Filter mask bytes */
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) |= maskByte;
-
-    temp = (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr));
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-    (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + macAddr)) = temp;
-}
-
-/** DMA Descriptors functions */
-
-/*!
- * @brief  Config the DMA Rx descriptors in chain mode.
- *
- * @param  DMARxDescTab: Pointer on the first Rx desc list
- *
- * @param  rxBuff: Pointer on the first RxBuffer list
- *
- * @param  rxBuffcount: Number of the used Rx desc in the list
- *
- * @retval None
- */
-void ETH_ConfigDMARxDescChain(ETH_DMADescConfig_T *DMARxDescTab, uint8_t *rxBuff, uint32_t rxBuffcount)
-{
-    uint32_t i = 0;
-    ETH_DMADescConfig_T *DMARxDesc;
-    DMARxDescToGet = DMARxDescTab;
-
-    for(i=0; i< rxBuffcount; i++)
-    {
-        DMARxDesc = DMARxDescTab+i;
-        DMARxDesc->Status = ETH_DMARXDESC_OWN;
-        DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RXCH | ETH_RX_BUF_SIZE;
-        DMARxDesc->Buffer1Addr = (uint32_t)(&rxBuff[i*ETH_RX_BUF_SIZE]);
-        if(i < (rxBuffcount-1))
-        {
-            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
-        }
-        else
-        {
-            DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
-        }
-    }
-
-
-    ETH->DMARXDLADDR = (uint32_t) DMARxDescTab;
-    DMARxFraminfos =&RxFrameDescriptor;
-}
-
-/*!
- * @brief  Initializes the DMA Tx descriptors in chain mode.
- *
- * @param  DMATxDescTab: Pointer on the first Tx desc list
- *
- * @param  txBuff: Pointer on the first TxBuffer list
- *
- * @param  txBuffcount: Number of the used Tx desc in the list
- *
- * @retval None
-  */
-void ETH_ConfigDMATxDescChain(ETH_DMADescConfig_T *DMATxDescTab, uint8_t* txBuff, uint32_t txBuffcount)
-{
-    uint32_t i = 0;
-    ETH_DMADescConfig_T *DMATxDesc;
-    DMATxDescToSet = DMATxDescTab;
-
-    for(i=0; i< txBuffcount; i++)
-    {
-        DMATxDesc = DMATxDescTab+i;
-        DMATxDesc->Status = ETH_DMATXDESC_TXCH;
-        DMATxDesc->Buffer1Addr = (uint32_t)(&txBuff[i*ETH_TX_BUF_SIZE]);
-        if(i < (txBuffcount-1))
-        {
-            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
-        }
-        else
-        {
-            DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab);
-        }
-    }
-
-    ETH->DMATXDLADDR = (uint32_t) DMATxDescTab;
-}
-
-/*!
- * @brief  This function polls for a frame receiver
- *
- * @param  None
- *
- * @retval Returns 1 when a frame is received, 0 if none.
- */
-uint32_t ETH_CheckReceivedFrame(void)
-{
-    if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
-        ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) != (uint32_t)RESET))
-    {
-        DMARxFraminfos->segCount++;
-        if(DMARxFraminfos->segCount == 1)
-        {
-            DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
-        }
-        DMARxFraminfos->LS_RxDesc = DMARxDescToGet;
-        return 1;
-    }
-    else if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
-             ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET) &&
-             ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
-    {
-        DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
-        DMARxFraminfos->LS_RxDesc = NULL;
-        DMARxFraminfos->segCount  = 1;
-        DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr);
-    }
-    else if(((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) &&
-             ((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET) &&
-             ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
-    {
-        (DMARxFraminfos->segCount) ++;
-        DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr);
-    }
-    return 0;
-}
-
-/*!
- * @brief  Prepares DMA Tx descriptors to transmit an ethernet frame
- *
- * @param  FrameLength : length of the frame to send
- *
- * @retval ETH_ERROR or ETH_SUCCESS
- */
-uint32_t ETH_Transmit_Descriptors(u16 frameLength)
-{
-    uint32_t count=0, size=0, i=0;
-    __IO ETH_DMADescConfig_T  *DMATxDesc;
-
-    if((DMATxDescToSet->Status & ETH_DMATXDESC_OWN) == SET)
-    {
-        return ETH_ERROR;
-    }
-
-    DMATxDesc = DMATxDescToSet;
-
-    if(frameLength > ETH_TX_BUF_SIZE)
-    {
-        count = frameLength/ETH_TX_BUF_SIZE;
-        if(frameLength%ETH_TX_BUF_SIZE) count++;
-    }
-    else count =1;
-
-    if(count == 1)
-    {
-        DMATxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
-        DMATxDesc->ControlBufferSize = (frameLength & ETH_DMATXDESC_TXBS1);
-        DMATxDesc->Status |= ETH_DMATXDESC_OWN;
-        DMATxDesc = (ETH_DMADescConfig_T*) (DMATxDesc->Buffer2NextDescAddr);
-    }
-    else
-    {
-        for(i=0; i<count; i++)
-        {
-            DMATxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
-
-            if(i==0)
-            {
-                DMATxDesc->Status |= ETH_DMATXDESC_FS;
-            }
-            DMATxDesc->ControlBufferSize =(ETH_TX_BUF_SIZE & ETH_DMATXDESC_TXBS1);
-
-            if(i== (count-1))
-            {
-                DMATxDesc->Status |= ETH_DMATXDESC_LS;
-                size = frameLength - (count-1)*ETH_TX_BUF_SIZE;
-                DMATxDesc->ControlBufferSize =(size & ETH_DMATXDESC_TXBS1);
-            }
-
-            DMATxDesc->Status |= ETH_DMATXDESC_OWN;
-            DMATxDesc = (ETH_DMADescConfig_T*) (DMATxDesc->Buffer2NextDescAddr);
-        }
-    }
-    DMATxDescToSet = DMATxDesc;
-
-    if(ETH->DMASTS_B.TXBU == SET)
-    {
-        ETH->DMASTS = BIT2;
-        ETH->DMATXPD = 0;
-    }
-
-    return ETH_SUCCESS;
-}
-
-/*!
- * @brief  Read the received frame.
- *
- * @param  none
- *
- * @retval Structure of type ETH_Frame_T
- */
-ETH_Frame_T ETH_ReadReceivedFrame(void)
-{
-    uint32_t frameLength = 0;
-    ETH_Frame_T frame = {0,0,0};
-
-    frameLength = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
-    frame.length = frameLength;
-
-    frame.descriptor = DMARxFraminfos->FS_RxDesc;
-    frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr;
-    DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr);
-
-    return(frame);
-}
-
-/*!
- * @brief  Read ETH DMA Tx Descriptor flag.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @param  flag: Specifies the flag to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMATXDESC_OWN   : Descriptor is owned by DMA engine
- *           @arg ETH_DMATXDESC_INTC  : Interrupt on completion
- *           @arg ETH_DMATXDESC_LS    : Last Segment
- *           @arg ETH_DMATXDESC_FS    : First Segment
- *           @arg ETH_DMATXDESC_DISC  : Disable CRC
- *           @arg ETH_DMATXDESC_DISP  : Disable Pad
- *           @arg ETH_DMATXDESC_TXTSEN: Transmit Time Stamp Enable
- *           @arg ETH_DMATXDESC_TXENDR: Transmit End of Ring
- *           @arg ETH_DMATXDESC_TXCH  : Second Address Chained
- *           @arg ETH_DMATXDESC_TXTSS : Tx Time Stamp Status
- *           @arg ETH_DMATXDESC_IHERR : IP Header Error
- *           @arg ETH_DMATXDESC_ERRS  : Error summary
- *           @arg ETH_DMATXDESC_JTO   : Jabber Timeout
- *           @arg ETH_DMATXDESC_FF    : Frame Flushed: DMA/MTL flushed the frame due to SW flush
- *           @arg ETH_DMATXDESC_IPERR : Payload Checksum Error
- *           @arg ETH_DMATXDESC_LSC   : Loss of Carrier: carrier lost during transmission
- *           @arg ETH_DMATXDESC_NC    : No Carrier: no carrier signal from the transceiver
- *           @arg ETH_DMATXDESC_LC    : Late Collision: transmission aborted due to collision
- *           @arg ETH_DMATXDESC_EC    : Excessive Collision: transmission aborted after 16 collisions
- *           @arg ETH_DMATXDESC_VLANF : VLAN Frame
- *           @arg ETH_DMATXDESC_CCNT  : Collision Count
- *           @arg ETH_DMATXDESC_EDEF  : Excessive Deferral
- *           @arg ETH_DMATXDESC_UFERR : Underflow Error: late data arrival from the memory
- *           @arg ETH_DMATXDESC_DEF   : Deferred Bit
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadDMATxDescFlagStatus(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_FLAG_T flag)
-{
-    return (DMATxDesc->Status & flag) ? SET : RESET;
-}
-
-/*!
- * @brief  Returns ETH DMA Tx Descriptor collision count.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval The Transmit descriptor collision counter value.
- */
-uint32_t ETH_ReadDMATxDescCollisionCount(ETH_DMADescConfig_T *DMATxDesc)
-{
-    return ((DMATxDesc->Status & ETH_DMATXDESC_CCNT) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
-}
-
-/*!
- * @brief  Config the ETH DMA Tx Descriptor Own bit.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_ConfigDMATxDescOwnBit(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status |= ETH_DMATXDESC_OWN;
-}
-
-/*!
- * @brief  Enable the ETH DMA Tx Descriptor Transmit interrupt.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_EnableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status |= ETH_DMATXDESC_INTC;
-}
-
-/*!
- * @brief  Disable the ETH DMA Tx Descriptor Transmit interrupt.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_DisableDMATxDescTransmitInterrupt(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_INTC);
-}
-
-/*!
- * @brief  Config Tx descriptor as last or first segment
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @param  frameSegment: Tx desc contain last or first segment.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMATXDESC_LASTSEGMENTS : Actual Tx desc contain last segment
- *           @arg ETH_DMATXDESC_FIRSTSEGMENT : Actual Tx desc contain first segment
- *
- * @retval None
- */
-void ETH_ConfigDMATxDescFrameSegment(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_SEGMENTS_T frameSegment)
-{
-    DMATxDesc->Status |= frameSegment;
-}
-/*!
- * @brief  Config ETH DMA Tx Desc Checksum Insertion.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @param  checksum: specifies is the DMA Tx desc checksum insertion.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMATXDESC_CHECKSUMBYPASS              : Checksum bypass
- *           @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER          : IPv4 header checksum
- *           @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT   : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- *           @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL      : TCP/UDP/ICMP checksum fully in hardware including pseudo header
- *
- * @retval None
- */
-void ETH_ConfigDMATxDescChecksumInsertion(ETH_DMADescConfig_T *DMATxDesc, ETH_DMATXDESC_CHECKSUMB_T checksum)
-{
-    DMATxDesc->Status |= checksum;
-}
-
-/*!
- * @brief  Enable the DMA Tx Desc CRC.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_EnableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISC);
-}
-
-/*!
- * @brief  Disable the DMA Tx Desc CRC.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_DisableDMATxDescCRC(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status |= ETH_DMATXDESC_DISC;
-}
-
-/*!
- * @brief  Enable the DMA Tx Desc second address chained.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_EnableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status |= ETH_DMATXDESC_TXCH;
-}
-
-/*!
- * @brief  Disable the DMA Tx Desc second address chained.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_DisableDMATxDescSecondAddressChained(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status &=(~(uint32_t)ETH_DMATXDESC_TXCH);
-}
-
-/*!
- * @brief  Enable the DMA Tx Desc padding for frame shorter than 64 bytes.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_EnableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status &= (~(uint32_t)ETH_DMATXDESC_DISP);
-}
-
-/*!
- * @brief  Disable the DMA Tx Desc padding for frame shorter than 64 bytes.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @retval None
- */
-void ETH_DisableDMATxDescShortFramePadding(ETH_DMADescConfig_T *DMATxDesc)
-{
-    DMATxDesc->Status |= ETH_DMATXDESC_DISP;
-}
-
-/*!
- * @brief  Config the ETH DMA Tx Desc buffer1 and buffer2 sizes.
- *
- * @param  DMATxDesc: pointer on a DMA Tx descriptor
- *
- * @param  bufferSize1: specifies the Tx desc buffer1 size.
- *
- * @param  bufferSize2: specifies the Tx desc buffer2 size.
- *
- * @retval None
- */
-void ETH_ConfigDMATxDescBufferSize(ETH_DMADescConfig_T *DMATxDesc, uint32_t bufferSize1, uint32_t bufferSize2)
-{
-    DMATxDesc->ControlBufferSize |= (bufferSize1 | (bufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
-}
-
-/*!
- * @brief  Checks whether the specified ETHERNET Rx Desc flag is set or not.
- *
- * @param  DMARxDesc: pointer on a DMA Rx descriptor
-
- * @param  flag: specifies the flag to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMARXDESC_OWN    :    Descriptor is owned by DMA engine
- *           @arg ETH_DMARXDESC_ADDRF  :    DA Filter Fail for the rx frame
- *           @arg ETH_DMARXDESC_ERRS   :    Error summary
- *           @arg ETH_DMARXDESC_DESERR :    Descriptor error: no more descriptors for receive frame
- *           @arg ETH_DMARXDESC_SADDRF :    SA Filter Fail for the received frame
- *           @arg ETH_DMARXDESC_LERR   :    Frame size not matching with length field
- *           @arg ETH_DMARXDESC_OFERR  :    Overflow Error: Frame was damaged due to buffer overflow
- *           @arg ETH_DMARXDESC_VLANF  :    VLAN Tag: received frame is a VLAN frame
- *           @arg ETH_DMARXDESC_FDES   :    First descriptor of the frame
- *           @arg ETH_DMARXDESC_LDES   :    Last descriptor of the frame
- *           @arg ETH_DMARXDESC_IPV4HCE:    IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
- *           @arg ETH_DMARXDESC_LC     :    Late collision occurred during reception
- *           @arg ETH_DMARXDESC_FT     :    Frame type - Ethernet, otherwise 802.3
- *           @arg ETH_DMARXDESC_RXWDTTO:    Receive Watchdog Timeout: watchdog timer expired during reception
- *           @arg ETH_DMARXDESC_RERR   :    Receive error: error reported by MII interface
- *           @arg ETH_DMARXDESC_DERR   :    Dribble bit error: frame contains non int multiple of 8 bits
- *           @arg ETH_DMARXDESC_CERR   :    CRC error
- *           @arg ETH_DMARXDESC_MAMPCE :    Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadDMARxDescFlagStatus(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_FLAG_T flag)
-{
-    return (DMARxDesc->Status & flag) ? SET : RESET;
-}
-
-#if USE_ENHANCED_DMA_DESCRIPTORS
-/*!
- * @brief  Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not.
- *
- * @param  DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor
- *
- * @param  flag: specifies the extended flag to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMAPTPRXDESC_PTPV  :  PTP version
- *           @arg ETH_DMAPTPRXDESC_PTPFT :  PTP frame type
- *           @arg ETH_DMAPTPRXDESC_PTPMT :  PTP message type
- *           @arg ETH_DMAPTPRXDESC_IPV6P :  IPv6 packet received
- *           @arg ETH_DMAPTPRXDESC_IPV4P :  IPv4 packet received
- *           @arg ETH_DMAPTPRXDESC_IPCBP :  IP checksum bypassed
- *           @arg ETH_DMAPTPRXDESC_IPPERR:  IP payload error
- *           @arg ETH_DMAPTPRXDESC_IPHERR:  IP header error
- *           @arg ETH_DMAPTPRXDESC_IPPT  :  IP payload type
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadDMAPTPRxDescExtendedFlagStatus(ETH_DMADescConfig_T *DMAPTPRxDesc, ETH_DMAPTPRXDESC_FLAG_T flag)
-{
-    return (DMAPTPRxDesc->Status & flag) ? SET : RESET;
-}
-#endif
-
-/*!
- * @brief  Config the ETH DMA Rx Desc Own bit.
- *
- * @param  DMARxDesc: pointer on a DMA Rx descriptor
- *
- * @retval None
- */
-void ETH_ConfigDMARxDescOwnBit(ETH_DMADescConfig_T *DMARxDesc)
-{
-    DMARxDesc->Status |= ETH_DMARXDESC_OWN;
-}
-
-/*!
- * @brief  Returns the ETH DMA Rx descriptor frame length.
- *
- * @param  DMARxDesc: pointer on a DMA Rx descriptor
- *
- * @retval The Rx descriptor received frame length.
- */
-uint32_t ETH_ReadDMARxDescFrameLength(ETH_DMADescConfig_T *DMARxDesc)
-{
-    return ((DMARxDesc->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
-}
-
-/*!
- * @brief  Enable the ETH DMA Rx Desc receive interrupt.
- *
- * @param  DMARxDesc: pointer on a DMA Rx descriptor
- *
- * @retval None
- */
-void ETH_EnableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMARxDesc)
-{
-    DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DINTC);
-}
-
-/*!
- * @brief  Disable the ETH DMA Rx Desc receive interrupt.
- *
- * @param  DMARxDesc: pointer on a DMA Rx descriptor
- *
- * @retval None
- */
-void ETH_DisableDMARxDescReceiveInterrupt(ETH_DMADescConfig_T *DMARxDesc)
-{
-    DMARxDesc->ControlBufferSize |= ETH_DMARXDESC_DINTC;
-}
-
-/*!
- * @brief  Returns the ETH DMA Rx Desc buffer size.
- *
- * @param  DMARxDesc: pointer on a DMA Rx descriptor
- *
- * @param  buffer: specifies the DMA Rx Desc buffer.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
- *           @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
- *
- * @retval The Receive descriptor frame length.
- */
-uint32_t ETH_ReadDMARxDescBufferSize(ETH_DMADescConfig_T *DMARxDesc, ETH_DMARXDESC_BUFFER_T buffer)
-{
-    if(buffer == ETH_DMARXDESC_BUFFER1)
-    {
-        return (DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS1);
-    }
-    else
-    {
-        return ((DMARxDesc->ControlBufferSize & ETH_DMARXDESC_RXBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
-    }
-}
-
-/*!
- * @brief  Read frame using DMA Receive interrupt.
- *         it allows scanning of Rx descriptors to get the the receive frame
- *
- * @param  None
- *
- * @retval Structure of type ETH_Frame_T
- */
-ETH_Frame_T ETH_ReadReceivedFrameInterrupt(void)
-{
-    __IO uint32_t count = 0;
-    ETH_Frame_T frame = {0,0,0};
-
-    while (((DMARxDescToGet->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)&& (count < ETH_RXBUFNB))
-    {
-        count ++;
-
-        if(((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) != (uint32_t)RESET)&&
-        ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
-        {
-            DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
-            DMARxFraminfos->segCount = 1;
-            DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr);
-        }
-        else if (((DMARxDescToGet->Status & ETH_DMARXDESC_FDES) == (uint32_t)RESET)&&
-                ((DMARxDescToGet->Status & ETH_DMARXDESC_LDES) == (uint32_t)RESET))
-        {
-            (DMARxFraminfos->segCount) ++;
-            DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr);
-        }
-        else
-        {
-            DMARxFraminfos->LS_RxDesc = DMARxDescToGet;
-            (DMARxFraminfos->segCount)++;
-
-            if ((DMARxFraminfos->segCount)==1)
-            DMARxFraminfos->FS_RxDesc = DMARxDescToGet;
-
-            frame.length = ((DMARxDescToGet->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
-
-            if(DMARxFraminfos->segCount >1)
-            {
-                frame.buffer = (DMARxFraminfos->FS_RxDesc)->Buffer1Addr;
-            }
-            else
-            {
-                frame.buffer = DMARxDescToGet->Buffer1Addr;
-            }
-
-            frame.descriptor = DMARxFraminfos->FS_RxDesc;
-            DMARxDescToGet = (ETH_DMADescConfig_T*) (DMARxDescToGet->Buffer2NextDescAddr);
-
-            return (frame);
-        }
-    }
-    return (frame);
-}
-
-/** DMA functions */
-
-/*!
- * @brief  Read the ETH DMA flag.
- *
- * @param  flag: specifies the flag to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMA_FLAG_TST                  : Time-stamp trigger flag
- *           @arg ETH_DMA_FLAG_PMT                  : PMT flag
- *           @arg ETH_DMA_FLAG_MMC                  : MMC flag
- *           @arg ETH_DMA_FLAG_DATATRANSFERERROR    : Error bits 0-data buffer, 1-desc. access
- *           @arg ETH_DMA_FLAG_READWRITEERROR       : Error bits 0-write trnsf, 1-read transfr
- *           @arg ETH_DMA_FLAG_ACCESSERROR          : Error bits 0-Rx DMA, 1-Tx DMA
- *           @arg ETH_DMA_FLAG_NIS                  : Normal interrupt summary flag
- *           @arg ETH_DMA_FLAG_AIS                  : Abnormal interrupt summary flag
- *           @arg ETH_DMA_FLAG_ER                   : Early receive flag
- *           @arg ETH_DMA_FLAG_FBE                  : Fatal bus error flag
- *           @arg ETH_DMA_FLAG_ET                   : Early transmit flag
- *           @arg ETH_DMA_FLAG_RWT                  : Receive watchdog timeout flag
- *           @arg ETH_DMA_FLAG_RPS                  : Receive process stopped flag
- *           @arg ETH_DMA_FLAG_RBU                  : Receive buffer unavailable flag
- *           @arg ETH_DMA_FLAG_RX                   : Receive flag
- *           @arg ETH_DMA_FLAG_TU                   : Underflow flag
- *           @arg ETH_DMA_FLAG_RO                   : Overflow flag
- *           @arg ETH_DMA_FLAG_TJT                  : Transmit jabber timeout flag
- *           @arg ETH_DMA_FLAG_TBU                  : Transmit buffer unavailable flag
- *           @arg ETH_DMA_FLAG_TPS                  : Transmit process stopped flag
- *           @arg ETH_DMA_FLAG_TX                   : Transmit flag
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadDMAFlagStatus(ETH_DMA_FLAG_T flag)
-{
-    return (ETH->DMASTS & flag) ? SET : RESET;
-}
-
-/*!
- * @brief  Clears the ETH DMA flag.
- *
- * @param  flag: specifies the flag to clear.
- *         This parameter can be any combination of the following values:
- *           @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
- *           @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
- *           @arg ETH_DMA_FLAG_ER  : Early receive flag
- *           @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
- *           @arg ETH_DMA_FLAG_ET  : Early transmit flag
- *           @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
- *           @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
- *           @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
- *           @arg ETH_DMA_FLAG_RX  : Receive flag
- *           @arg ETH_DMA_FLAG_TU  : Transmit Underflow flag
- *           @arg ETH_DMA_FLAG_RO  : Receive Overflow flag
- *           @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
- *           @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
- *           @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
- *           @arg ETH_DMA_FLAG_TX  : Transmit flag
- *
- * @retval None
- */
-void ETH_ClearDMAFlag(uint32_t flag)
-{
-    ETH->DMASTS = flag;
-}
-
-/*!
- * @brief  Read the ETH DMA interrupt flag.
- *
- * @param  flag: specifies the interrupt source to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMA_INT_TST : Time-stamp trigger interrupt
- *           @arg ETH_DMA_INT_PMT : PMT interrupt
- *           @arg ETH_DMA_INT_MMC : MMC interrupt
- *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
- *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- *           @arg ETH_DMA_INT_ER  : Early receive interrupt
- *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
- *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- *           @arg ETH_DMA_INT_RX  : Receive interrupt
- *           @arg ETH_DMA_INT_TU  : Underflow interrupt
- *           @arg ETH_DMA_INT_RO  : Overflow interrupt
- *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- *           @arg ETH_DMA_INT_TX  : Transmit interrupt
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadDMAIntFlag(ETH_DMA_INT_T flag)
-{
-    return (ETH->DMASTS & flag) ? SET : RESET;
-}
-
-/*!
- * @brief  Clears the ETH DMA interrupt flag.
- *
- * @param  flag: specifies the interrupt flag to clear.
- *         This parameter can be any combination of the following values:
- *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
- *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- *           @arg ETH_DMA_INT_ER  : Early receive interrupt
- *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
- *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- *           @arg ETH_DMA_INT_RX  : Receive interrupt
- *           @arg ETH_DMA_INT_TU  : Transmit Underflow interrupt
- *           @arg ETH_DMA_INT_RO  : Receive Overflow interrupt
- *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- *           @arg ETH_DMA_INT_TX  : Transmit interrupt
- *
- * @retval None
- */
-void ETH_ClearDMAIntFlag(uint32_t flag)
-{
-    ETH->DMASTS = flag;
-}
-
-/*!
- * @brief  Returns the ETH DMA Transmit Process State.
- *
- * @param  None
-
- * @retval The new ETH DMA Transmit Process State:
- *         This can be one of the following values:
- *           - ETH_DMA_TRANSMITPROCESS_STOPPED   : Stopped - Reset or Stop Tx Command issued
- *           - ETH_DMA_TRANSMITPROCESS_FETCHING  : Running - fetching the Tx descriptor
- *           - ETH_DMA_TRANSMITPROCESS_WAITING   : Running - waiting for status
- *           - ETH_DMA_TRANSMITPROCESS_READING   : Running - reading the data from host memory
- *           - ETH_DMA_TRANSMITPROCESS_SUSPENDED : Suspended - Tx Descriptor unavailable
- *           - ETH_DMA_TRANSMITPROCESS_CLOSING   : Running - closing Rx descriptor
- */
-uint32_t ETH_ReadTransmitProcessState(void)
-{
-    return ((uint32_t)(ETH->DMASTS & BIT0) ? SET : RESET);
-}
-
-/*!
- * @brief  Returns the ETH DMA Receive Process State.
- *
- * @param  None
- *
- * @retval The new ETH DMA Receive Process State:
- *         This can be one of the following values:
- *           - ETH_DMA_RECEIVEPROCESS_STOPPED   : Stopped - Reset or Stop Rx Command issued
- *           - ETH_DMA_RECEIVEPROCESS_FETCHING  : Running - fetching the Rx descriptor
- *           - ETH_DMA_RECEIVEPROCESS_WAITING   : Running - waiting for packet
- *           - ETH_DMA_RECEIVEPROCESS_SUSPENDED : Suspended - Rx Descriptor unavailable
- *           - ETH_DMA_RECEIVEPROCESS_CLOSING   : Running - closing descriptor
- *           - ETH_DMA_RECEIVEPROCESS_QUEUING   : Running - queuing the receive frame into host memory
- */
-uint32_t ETH_ReadReceiveProcessState(void)
-{
-    return ((uint32_t)(ETH->DMASTS & BIT6) ? SET : RESET);
-}
-
-/*!
- * @brief  Flush the ETH transmit FIFO.
- *
- * @param  None
- *
- * @retval None
-  */
-void ETH_FlushTransmitFIFO(void)
-{
-    ETH->DMAOPMOD_B.FTXF = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Read the ETH flush transmit FIFO status.
- *
- * @param  None
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadFlushTransmitFIFOStatus(void)
-{
-    return ETH->DMAOPMOD_B.FTXF;
-}
-
-/*!
- * @brief  Enable the DMA transmission.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableDMATransmission(void)
-{
-    ETH->DMAOPMOD_B.STTX = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the DMA transmission.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableDMATransmission(void)
-{
-    ETH->DMAOPMOD_B.STTX = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Enable the DMA receiver.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableDMAReceiver(void)
-{
-    ETH->DMAOPMOD_B.STRX = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the DMA receiver.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableDMAReceiver(void)
-{
-    ETH->DMAOPMOD_B.STRX = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Enable the ETH DMA interrupts.
- *
- * @param  interrupt: specifies the ETH DMA interrupt sources.
- *         This parameter can be any combination of the following values:
- *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
- *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- *           @arg ETH_DMA_INT_ER  : Early receive interrupt
- *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
- *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- *           @arg ETH_DMA_INT_RX  : Receive interrupt
- *           @arg ETH_DMA_INT_TU  : Underflow interrupt
- *           @arg ETH_DMA_INT_RO  : Overflow interrupt
- *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- *           @arg ETH_DMA_INT_TX  : Transmit interrupt
- *
- * @retval None
- */
-void ETH_EnableDMAInterrupt(uint32_t interrupt)
-{
-    ETH->DMAINTEN |= interrupt;
-}
-
-/*!
- * @brief  Disable the ETH DMA interrupts.
- *
- * @param  interrupt: specifies the ETH DMA interrupt sources.
- *         This parameter can be any combination of the following values:
- *           @arg ETH_DMA_INT_NIS : Normal interrupt summary
- *           @arg ETH_DMA_INT_AIS : Abnormal interrupt summary
- *           @arg ETH_DMA_INT_ER  : Early receive interrupt
- *           @arg ETH_DMA_INT_FBE : Fatal bus error interrupt
- *           @arg ETH_DMA_INT_ET  : Early transmit interrupt
- *           @arg ETH_DMA_INT_RWT : Receive watchdog timeout interrupt
- *           @arg ETH_DMA_INT_RPS : Receive process stopped interrupt
- *           @arg ETH_DMA_INT_RBU : Receive buffer unavailable interrupt
- *           @arg ETH_DMA_INT_RX  : Receive interrupt
- *           @arg ETH_DMA_INT_TU  : Underflow interrupt
- *           @arg ETH_DMA_INT_RO  : Overflow interrupt
- *           @arg ETH_DMA_INT_TJT : Transmit jabber timeout interrupt
- *           @arg ETH_DMA_INT_TBU : Transmit buffer unavailable interrupt
- *           @arg ETH_DMA_INT_TPS : Transmit process stopped interrupt
- *           @arg ETH_DMA_INT_TX  : Transmit interrupt
- *
- * @retval None
- */
-void ETH_DisableDMAInterrupt(uint32_t interrupt)
-{
-    ETH->DMAINTEN &= ((uint32_t)~interrupt);
-}
-
-/*!
- * @brief  Read the ETH DMA overflow flag.
- *
- * @param  overflow: specifies the DMA overflow flag to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER        : Overflow for FIFO Overflows Counter
- *           @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER   : Overflow for Buffer Unavailable Missed Frame Counter
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadDMAOverflowStatus(ETH_DMA_OVERFLOW_T overflow)
-{
-    return (ETH->DMAMFABOCNT & overflow) ? SET : RESET;
-}
-
-/*!
- * @brief  Read the ETH DMA Rx Overflow Missed Frame Counter value.
- *
- * @param  None
- *
- * @retval The value of Rx overflow Missed Frame Counter.
- */
-uint32_t ETH_ReadRxOverflowMissedFrameCounter(void)
-{
-    return (uint32_t)(ETH->DMAMFABOCNT_B.AMISFCNT);
-}
-
-/*!
- * @brief  Read the ETH DMA Buffer Unavailable Missed Frame Counter value.
- *
- * @param  None
- *
- * @retval The value of Buffer unavailable Missed Frame Counter.
- */
-uint32_t ETH_ReadBufferUnavailableMissedFrameCounter(void)
-{
-    return (uint32_t)(ETH->DMAMFABOCNT_B.MISFCNT);
-}
-
-/*!
- * @brief  Read the ETH DMA DMAHTXD register value.
- *
- * @param  None
- *
- * @retval The value of the current Tx desc start address.
- */
-uint32_t ETH_ReadCurrentTxDescStartAddress(void)
-{
-    return ((uint32_t)(ETH->DMAHTXD));
-}
-
-/*!
- * @brief  Read the ETHERNET DMA DMAHRXD register value.
- *
- * @param  None
- *
- * @retval The value of the current Rx desc start address.
- */
-uint32_t ETH_ReadCurrentRxDescStartAddress(void)
-{
-    return ((uint32_t)(ETH->DMAHRXD));
-}
-
-/*!
- * @brief  Read the ETH DMA DMAHTXBADDR register value.
- *
- * @param  None
- *
- * @retval The value of the current transmit descriptor data buffer address.
- */
-uint32_t ETH_ReadCurrentTxBufferAddress(void)
-{
-    return ((uint32_t)(ETH->DMAHTXBADDR));
-}
-
-/*!
- * @brief  Read the ETH DMA DMAHRXBADDR register value.
- *
- * @param  None
- *
- * @retval The value of the current receive descriptor data buffer address.
- */
-uint32_t ETH_ReadCurrentRxBufferAddress(void)
-{
-    return ((uint32_t)(ETH->DMAHRXBADDR));
-}
-
-/*!
- * @brief  Reset the DMA Transmission by writing to the DmaTxPollDemand register
- *
- * @param  None
-
- * @retval None.
- */
-void ETH_ResetDMATransmission(void)
-{
-    ETH->DMATXPD = 0;
-}
-
-/*!
- * @brief  Reset the DMA Transmission by writing to the DmaRxPollDemand register
- *
- * @param  None
- *
- * @retval None.
- */
-void ETH_ResetDMAReception(void)
-{
-    ETH->DMARXPD = 0;
-}
-
-/*!
- * @brief  Config the DMA Receive status watchdog timer register value
- *
- * @param  value: watchdog timer register value
- *
- * @retval None
- */
-void ETH_ConfigReceiveWatchdogTimer(uint8_t value)
-{
-    ETH->DMARXFLGWDT_B.RXWDTCNT = value;
-}
-
-/** Power Management(PMT) functions */
-
-/*!
- * @brief  Reset Wakeup frame filter register pointer.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
-{
-    ETH->PMTCTRLSTS_B.WKUPFRST = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Populates the remote wakeup frame registers.
- *
- * @param  buffer: WakeUp Frame Filter Register buffer data (8 words).
- *
- * @retval None
- */
-void ETH_ConfigWakeUpFrameFilterRegister(uint32_t *buffer)
-{
-    uint32_t i = 0;
-    __IO uint32_t temp = 0;
-
-    for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++)
-    {
-        ETH->WKUPFFL = buffer[i];
-
-        temp = ETH->WKUPFFL;
-        ETH_Delay(ETH_REG_WRITE_DELAY);
-        ETH->WKUPFFL = temp;
-    }
-}
-
-/*!
- * @brief  Enable any unicast packet filtered by the MAC address
- *         recognition to be a wake-up frame.
- *
- * @retval None
- */
-void ETH_EnableGlobalUnicastWakeUp(void)
-{
-    ETH->PMTCTRLSTS_B.GUN = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable any unicast packet filtered by the MAC address
- *         recognition to be a wake-up frame.
- *
- * @retval None
- */
-void ETH_DisableGlobalUnicastWakeUp(void)
-{
-    ETH->PMTCTRLSTS_B.GUN = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Read the ETH PMT flag.
- *
- * @param  flag: specifies the flag to check.
- *         This parameter can be one of the following values:
- *           @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
- *           @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
- *           @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadPMTFlagStatus(ETH_PMT_FLAG_T flag)
-{
-    return (ETH->PMTCTRLSTS & flag) ? SET : RESET;
-}
-
-/*!
- * @brief  Enable the MAC Wake-Up Frame Detection.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableWakeUpFrameDetection(void)
-{
-    ETH->PMTCTRLSTS_B.WKUPFEN = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the MAC Wake-Up Frame Detection.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableWakeUpFrameDetection(void)
-{
-    ETH->PMTCTRLSTS_B.WKUPFEN = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Enable the MAC Magic Packet Detection.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableMagicPacketDetection(void)
-{
-    ETH->PMTCTRLSTS_B.MPEN = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the MAC Magic Packet Detection.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableMagicPacketDetection(void)
-{
-    ETH->PMTCTRLSTS_B.MPEN = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Enable the MAC Power Down.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnablePowerDown(void)
-{
-    ETH->PMTCTRLSTS_B.PD = SET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/*!
- * @brief  Disable the MAC Power Down.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisablePowerDown(void)
-{
-    ETH->PMTCTRLSTS_B.PD = RESET;
-    ETH_Delay(ETH_REG_WRITE_DELAY);
-}
-
-/** MMC functions */
-
-/**
-  * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
-  * @param  None
-  * @retval None
-  */
-void ETH_PresetMMCCounterFull(void)
-{
-    ETH->CTRL_B.MCNTP = SET;
-    ETH->CTRL_B.MCNTVALP = SET;
-}
-
-/**
-  * @brief  Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16)
-  * @param  None
-  * @retval None
-  */
-void ETH_PresetMMCCounterHalf(void)
-{
-    ETH->CTRL_B.MCNTP = SET;
-    ETH->CTRL_B.MCNTVALP = RESET;
-}
-
-/*!
- * @brief  Enable the MMC Counter Freeze.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableMMCCounterFreeze(void)
-{
-    ETH->CTRL_B.MCNTF = SET;
-}
-
-/*!
- * @brief  Disable the MMC Counter Freeze.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableMMCCounterFreeze(void)
-{
-    ETH->CTRL_B.MCNTF = RESET;
-}
-
-/*!
- * @brief  Enable the MMC Reset On Read.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableMMCResetOnRead(void)
-{
-    ETH->CTRL_B.RSTOR = SET;
-}
-
-/*!
- * @brief  Disable the MMC Reset On Read.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableMMCResetOnRead(void)
-{
-    ETH->CTRL_B.RSTOR = RESET;
-}
-
-/*!
- * @brief  Enble the MMC Counter Stop Rollover.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_EnableMMCCounterRollover(void)
-{
-    ETH->CTRL_B.CNTSTOPRO = RESET;
-}
-
-/*!
- * @brief  Disable the MMC Counter Stop Rollover.
- *
- * @param  None
- *
- * @retval None
- */
-void ETH_DisableMMCCounterRollover(void)
-{
-    ETH->CTRL_B.CNTSTOPRO = SET;
-}
-
-/**
-  * @brief  Resets the MMC Counters.
-  * @param  None
-  * @retval None
-  */
-void ETH_ResetMMCCounters(void)
-{
-    ETH->CTRL_B.CNTRST = SET;
-}
-
-/*!
- * @brief  Enable the ETH MMC interrupts.
- *
- * @param  interrupt: specifies the ETH MMC interrupt sources.
- *         This parameter can be any combination of Tx interrupt or
- *         any combination of Rx interrupt (but not both)of the following values:
- *           @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value
- *           @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- *           @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
- *
- * @retval None
- */
-void ETH_EnableMMCInterrupt(uint32_t interrupt)
-{
-   if((interrupt & 0x10000000) == SET)
-   {
-        ETH->RXINTMASK &= (~(uint32_t)interrupt);
-   }
-   else
-   {
-        ETH->TXINTMASK &= (~(uint32_t)interrupt);
-   }
-}
-
-/*!
- * @brief  Disable the ETH MMC interrupts.
- *
- * @param  interrupt: specifies the ETH MMC interrupt sources.
- *         This parameter can be any combination of Tx interrupt or
- *         any combination of Rx interrupt (but not both)of the following values:
- *           @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value
- *           @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- *           @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
- *
- * @retval None
- */
-void ETH_DisableMMCInterrupt(uint32_t interrupt)
-{
-   if((interrupt & 0x10000000) == SET)
-   {
-        ETH->RXINTMASK |= interrupt;
-   }
-   else
-   {
-        ETH->TXINTMASK |= interrupt;
-   }
-}
-
-/*!
- * @brief  Read the ETH MMC interrupt flag.
- *
- * @param  flag: specifies the ETH MMC interrupt.
- *         This parameter can be one of the following values:
- *           @arg ETH_MMC_INT_TGF   : When Tx good frame counter reaches half the maximum value
- *           @arg ETH_MMC_INT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- *           @arg ETH_MMC_INT_TGFSC : When Tx good single col counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RFAE  : When Rx alignment error counter reaches half the maximum value
- *           @arg ETH_MMC_INT_RFCE  : When Rx crc error counter reaches half the maximum value
- *
- * @retval SET or RESET.
- */
-uint8_t ETH_ReadMMCIntFlag(uint32_t flag)
-{
-    if((flag & 0x10000000) == SET)
-    {
-        return ((((ETH->RXINT & flag) != RESET)) && ((ETH->RXINTMASK & flag) == RESET));
-    }
-    else
-    {
-        return ((((ETH->TXINT & flag) != RESET)) && ((ETH->TXINTMASK & flag) == RESET));
-    }
-}
-
-/*!
- * @brief  Read the ETH MMC register value.
- *
- * @param  MMCReg: specifies the ETH MMC register.
- *         This parameter can be one of the following values:
- *           @arg ETH_MMC_CTRL      : MMC CTRL register
- *           @arg ETH_MMC_RXINT     : MMC RXINT register
- *           @arg ETH_MMC_TXINT     : MMC TXINT register
- *           @arg ETH_MMC_RXINTMASK : MMC RXINTMASK register
- *           @arg ETH_MMC_TXINTMASK : MMC TXINTMASK register
- *           @arg ETH_MMC_TXGFSCCNT : MMC TXGFSCCNT register
- *           @arg ETH_MMC_TXGFMCCNT : MMC TXGFMCCNT register
- *           @arg ETH_MMC_TXGFCNT   : MMC TXGFCNT register
- *           @arg ETH_MMC_RXFCECNT  : MMC RXFCECNT register
- *           @arg ETH_MMC_RXFAECNT  : MMC RXFAECNT register
- *           @arg ETH_MMC_RXGUNCNT  : MMC RXGUNCNT register
- *
- * @retval Return ETH MMC Register value.
- */
-uint32_t ETH_ReadMMCRegister(ETH_MMC_REG_T MMCReg)
-{
-    return (*(__IO uint32_t *)(ETH_MAC_BASE + MMCReg));
-}
-
-/**@} end of group ETH_Functions */
-/**@} end of group ETH_Driver */
-/**@} end of group APM32F4xx_ETHDriver */

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_adc.c

@@ -61,7 +61,7 @@ void ADC_Reset(void)
  *
  * @retval    None
  */
-void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
+void ADC_Config(ADC_T *adc, ADC_Config_T *adcConfig)
 {
     adc->CTRL1_B.RESSEL = adcConfig->resolution;
     adc->CTRL1_B.SCANEN = adcConfig->scanConvMode;
@@ -81,7 +81,7 @@ void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig)
  *
  * @retval    None
  */
-void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
+void ADC_ConfigStructInit(ADC_Config_T *adcConfig)
 {
     adcConfig->resolution = ADC_RESOLUTION_12BIT;
     adcConfig->scanConvMode = DISABLE;
@@ -100,7 +100,7 @@ void ADC_ConfigStructInit(ADC_Config_T* adcConfig)
  *
  * @retval    None
  */
-void ADC_CommonConfig(ADC_CommonConfig_T* adcCommonConfig)
+void ADC_CommonConfig(ADC_CommonConfig_T *adcCommonConfig)
 {
     ADC->CCTRL_B.ADCMSEL = adcCommonConfig->mode;
     ADC->CCTRL_B.ADCPRE = adcCommonConfig->prescaler;
@@ -115,7 +115,7 @@ void ADC_CommonConfig(ADC_CommonConfig_T* adcCommonConfig)
  *
  * @retval    None
  */
-void ADC_CommonConfigStructInit(ADC_CommonConfig_T* adccommonconfig)
+void ADC_CommonConfigStructInit(ADC_CommonConfig_T *adccommonconfig)
 {
     adccommonconfig->mode = ADC_MODE_INDEPENDENT;
     adccommonconfig->prescaler = ADC_PRESCALER_DIV2;
@@ -130,7 +130,7 @@ void ADC_CommonConfigStructInit(ADC_CommonConfig_T* adccommonconfig)
  *
  * @retval    None
  */
-void ADC_Enable(ADC_T* adc)
+void ADC_Enable(ADC_T *adc)
 {
     adc->CTRL2_B.ADCEN = BIT_SET;
 }
@@ -142,7 +142,7 @@ void ADC_Enable(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_Disable(ADC_T* adc)
+void ADC_Disable(ADC_T *adc)
 {
     adc->CTRL2_B.ADCEN = BIT_RESET;
 }
@@ -163,7 +163,7 @@ void ADC_Disable(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_EnableAnalogWatchdog(ADC_T* adc, ADC_ANALOG_WATCHDOG_T analogWatchdog)
+void ADC_EnableAnalogWatchdog(ADC_T *adc, ADC_ANALOG_WATCHDOG_T analogWatchdog)
 {
     adc->CTRL1_B.INJAWDEN = analogWatchdog & 0x01;
     adc->CTRL1_B.REGAWDEN = (analogWatchdog >> 1) & 0x01;
@@ -177,7 +177,7 @@ void ADC_EnableAnalogWatchdog(ADC_T* adc, ADC_ANALOG_WATCHDOG_T analogWatchdog)
  *
  * @retval    None
  */
-void ADC_DisableAnalogWatchdog(ADC_T* adc)
+void ADC_DisableAnalogWatchdog(ADC_T *adc)
 {
     adc->CTRL1_B.AWDSGLEN = BIT_RESET;
     adc->CTRL1_B.INJAWDEN = BIT_RESET;
@@ -196,7 +196,7 @@ void ADC_DisableAnalogWatchdog(ADC_T* adc)
  *                           This parameter must be a 12bit value.
  * @retval    None
  */
-void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold)
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T *adc, uint16_t highThreshold, uint16_t lowThreshold)
 {
     adc->AWDHT = highThreshold;
     adc->AWDLT = lowThreshold;
@@ -212,7 +212,7 @@ void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint
  *
  * @retval    None
  */
-void ADC_AnalogWatchdogLowThresholds(ADC_T* adc,  uint16_t lowThreshold)
+void ADC_AnalogWatchdogLowThresholds(ADC_T *adc,  uint16_t lowThreshold)
 {
     adc->AWDLT = lowThreshold;
 }
@@ -248,7 +248,7 @@ void ADC_AnalogWatchdogLowThresholds(ADC_T* adc,  uint16_t lowThreshold)
  *
  * @note       adc can be ADC1, ADC2 or ADC3.
  */
-void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel)
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T *adc, uint8_t channel)
 {
     adc->CTRL1_B.AWDCHSEL = channel;
 }
@@ -345,7 +345,7 @@ void ADC_DisableVbat(void)
  * @retval None
  */
 
-void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigRegularChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
@@ -405,7 +405,7 @@ void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t
  *
  * @retval    None
  */
-void ADC_SoftwareStartConv(ADC_T* adc)
+void ADC_SoftwareStartConv(ADC_T *adc)
 {
     adc->CTRL2_B.REGCHSC = BIT_SET;
 }
@@ -417,7 +417,7 @@ void ADC_SoftwareStartConv(ADC_T* adc)
  *
  * @retval    The new state of ADC software start conversion (SET or RESET).
  */
-uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T *adc)
 {
     return (uint8_t)adc->CTRL2_B.REGCHSC;
 }
@@ -429,7 +429,7 @@ uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_EnableEOCOnEachChannel(ADC_T* adc)
+void ADC_EnableEOCOnEachChannel(ADC_T *adc)
 {
     adc->CTRL2_B.EOCSEL = BIT_SET;
 
@@ -442,7 +442,7 @@ void ADC_EnableEOCOnEachChannel(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_DisableEOCOnEachChannel(ADC_T* adc)
+void ADC_DisableEOCOnEachChannel(ADC_T *adc)
 {
     adc->CTRL2_B.EOCSEL = BIT_RESET;
 }
@@ -454,7 +454,7 @@ void ADC_DisableEOCOnEachChannel(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_EnableContinuousMode(ADC_T* adc)
+void ADC_EnableContinuousMode(ADC_T *adc)
 {
     adc->CTRL2_B.CONTCEN = BIT_SET;
 }
@@ -466,7 +466,7 @@ void ADC_EnableContinuousMode(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_DisableContinuousMode(ADC_T* adc)
+void ADC_DisableContinuousMode(ADC_T *adc)
 {
     adc->CTRL2_B.CONTCEN = BIT_RESET;;
 }
@@ -482,7 +482,7 @@ void ADC_DisableContinuousMode(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number)
+void ADC_ConfigDiscMode(ADC_T *adc, uint8_t number)
 {
     adc->CTRL1_B.DISCNUMCFG = number - 1;
 }
@@ -494,7 +494,7 @@ void ADC_ConfigDiscMode(ADC_T* adc, uint8_t number)
  *
  * @retval    None
  */
-void ADC_EnableDiscMode(ADC_T* adc)
+void ADC_EnableDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.REGDISCEN = BIT_SET;
 }
@@ -506,9 +506,9 @@ void ADC_EnableDiscMode(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_DisableDiscMode(ADC_T* adc)
+void ADC_DisableDiscMode(ADC_T *adc)
 {
-    adc->CTRL1_B.REGDISCEN= BIT_RESET;
+    adc->CTRL1_B.REGDISCEN = BIT_RESET;
 }
 
 /*!
@@ -518,7 +518,7 @@ void ADC_DisableDiscMode(ADC_T* adc)
  *
  * @retval    The Data conversion value.
  */
-uint16_t ADC_ReadConversionValue(ADC_T* adc)
+uint16_t ADC_ReadConversionValue(ADC_T *adc)
 {
     return (uint16_t) adc->REGDATA;
 }
@@ -548,7 +548,7 @@ uint32_t ADC_ReadMultiValue(void)
  *
  * @retval    The Data conversion value.
  */
-void ADC_EnableDMA(ADC_T* adc)
+void ADC_EnableDMA(ADC_T *adc)
 {
     adc->CTRL2_B.DMAEN = BIT_SET;
 }
@@ -560,7 +560,7 @@ void ADC_EnableDMA(ADC_T* adc)
  *
  * @retval    The Data conversion value.
  */
-void ADC_DisableDMA(ADC_T* adc)
+void ADC_DisableDMA(ADC_T *adc)
 {
     adc->CTRL2_B.DMAEN = BIT_RESET;
 }
@@ -571,7 +571,7 @@ void ADC_DisableDMA(ADC_T* adc)
  *
  * @retval    The Data conversion value.
  */
-void ADC_EnableDMARequest(ADC_T* adc)
+void ADC_EnableDMARequest(ADC_T *adc)
 {
     adc->CTRL2_B.DMADISSEL = BIT_SET;
 }
@@ -582,7 +582,7 @@ void ADC_EnableDMARequest(ADC_T* adc)
  *
  * @retval    The Data conversion value.
  */
-void ADC_DisableDMARequest(ADC_T* adc)
+void ADC_DisableDMARequest(ADC_T *adc)
 {
     adc->CTRL2_B.DMADISSEL = BIT_RESET;
 }
@@ -655,7 +655,7 @@ void ADC_DisableMultiModeDMARequest(void)
  * @retval    None
  */
 
-void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
+void ADC_ConfigInjectedChannel(ADC_T *adc, uint8_t channel, uint8_t rank, uint8_t sampleTime)
 {
     uint32_t temp1 = 0;
     uint32_t temp2 = 0;
@@ -697,7 +697,7 @@ void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_
  *
  * @retval    None
  */
-void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
+void ADC_ConfigInjectedSequencerLength(ADC_T *adc, uint8_t length)
 {
     adc->INJSEQ_B.INJSEQLEN = length - 1;
 }
@@ -719,24 +719,24 @@ void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length)
  *
  * @retval    None
  */
-void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offset)
+void ADC_ConfigInjectedOffset(ADC_T *adc, ADC_INJEC_CHANNEL_T channel, uint16_t offset)
 {
     switch ((uint8_t)channel)
     {
-        case 0x01:
-            adc->INJDOF1_B.INJDOF1 = offset;
-            break;
-        case 0x02:
-            adc->INJDOF2_B.INJDOF2 = offset;
-            break;
-        case 0x03:
-            adc->INJDOF3_B.INJDOF3 = offset;
-            break;
-        case 0x04:
-            adc->INJDOF4_B.INJDOF4 = offset;
-            break;
-        default :
-            break;
+    case 0x01:
+        adc->INJDOF1_B.INJDOF1 = offset;
+        break;
+    case 0x02:
+        adc->INJDOF2_B.INJDOF2 = offset;
+        break;
+    case 0x03:
+        adc->INJDOF3_B.INJDOF3 = offset;
+        break;
+    case 0x04:
+        adc->INJDOF4_B.INJDOF4 = offset;
+        break;
+    default :
+        break;
     }
 }
 
@@ -766,7 +766,7 @@ void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t
  *
  * @retval    None
  */
-void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
+void ADC_ConfigExternalTrigInjectedConv(ADC_T *adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv)
 {
     adc->CTRL2_B.INJGEXTTRGSEL = extTrigInjecConv;
 }
@@ -784,7 +784,7 @@ void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T ex
  *
  * @retval    None
  */
-void ADC_ConfigExternalTrigInjectedConvEdge(ADC_T* adc, ADC_EXT_TRIG_INJEC_EDGE_T extTrigInjecConvEdge)
+void ADC_ConfigExternalTrigInjectedConvEdge(ADC_T *adc, ADC_EXT_TRIG_INJEC_EDGE_T extTrigInjecConvEdge)
 {
     adc->CTRL2_B.INJEXTTRGEN = extTrigInjecConvEdge;
 }
@@ -796,7 +796,7 @@ void ADC_ConfigExternalTrigInjectedConvEdge(ADC_T* adc, ADC_EXT_TRIG_INJEC_EDGE_
  *
  * @retval    None
  */
-void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
+void ADC_EnableSoftwareStartInjectedConv(ADC_T *adc)
 {
     adc->CTRL2_B.INJCHSC = BIT_SET;
 }
@@ -808,7 +808,7 @@ void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc)
  *
  * @retval    None
  */
-uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T *adc)
 {
     return (uint8_t)(adc->CTRL2_B.INJCHSC);
 }
@@ -820,9 +820,9 @@ uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_EnableAutoInjectedConv(ADC_T* adc)
+void ADC_EnableAutoInjectedConv(ADC_T *adc)
 {
-    adc->CTRL1_B.INJGACEN= BIT_SET;
+    adc->CTRL1_B.INJGACEN = BIT_SET;
 }
 
 /*!
@@ -832,9 +832,9 @@ void ADC_EnableAutoInjectedConv(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_DisableAutoInjectedConv(ADC_T* adc)
+void ADC_DisableAutoInjectedConv(ADC_T *adc)
 {
-    adc->CTRL1_B.INJGACEN= BIT_RESET;
+    adc->CTRL1_B.INJGACEN = BIT_RESET;
 }
 
 /*!
@@ -844,7 +844,7 @@ void ADC_DisableAutoInjectedConv(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_EnableInjectedDiscMode(ADC_T* adc)
+void ADC_EnableInjectedDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_SET;
 }
@@ -856,7 +856,7 @@ void ADC_EnableInjectedDiscMode(ADC_T* adc)
  *
  * @retval    None
  */
-void ADC_DisableInjectedDiscMode(ADC_T* adc)
+void ADC_DisableInjectedDiscMode(ADC_T *adc)
 {
     adc->CTRL1_B.INJDISCEN = BIT_RESET;
 }
@@ -875,20 +875,20 @@ void ADC_DisableInjectedDiscMode(ADC_T* adc)
  *
  * @retval    The Data conversion value.
  */
-uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel)
+uint16_t ADC_ReadInjectedConversionValue(ADC_T *adc, ADC_INJEC_CHANNEL_T channel)
 {
     switch ((uint8_t)channel)
     {
-        case 0x01:
-            return (uint16_t)adc->INJDATA1_B.INJDATA;
-        case 0x02:
-            return (uint16_t)adc->INJDATA2_B.INJDATA;
-        case 0x03:
-            return (uint16_t)adc->INJDATA3_B.INJDATA;
-        case 0x04:
-            return (uint16_t)adc->INJDATA4_B.INJDATA;
-        default :
-            return 0;
+    case 0x01:
+        return (uint16_t)adc->INJDATA1_B.INJDATA;
+    case 0x02:
+        return (uint16_t)adc->INJDATA2_B.INJDATA;
+    case 0x03:
+        return (uint16_t)adc->INJDATA3_B.INJDATA;
+    case 0x04:
+        return (uint16_t)adc->INJDATA4_B.INJDATA;
+    default :
+        return 0;
     }
 }
 
@@ -906,7 +906,7 @@ uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel
  *
  * @retval    None
  */
-void ADC_EnableInterrupt(ADC_T* adc, uint32_t interrupt)
+void ADC_EnableInterrupt(ADC_T *adc, uint32_t interrupt)
 {
     adc->CTRL1 |= interrupt;
 }
@@ -925,7 +925,7 @@ void ADC_EnableInterrupt(ADC_T* adc, uint32_t interrupt)
  *
  * @retval    None
  */
-void ADC_DisableInterrupt(ADC_T* adc, uint32_t interrupt)
+void ADC_DisableInterrupt(ADC_T *adc, uint32_t interrupt)
 {
     adc->CTRL1 &= (uint32_t)~interrupt;
 }
@@ -946,7 +946,7 @@ void ADC_DisableInterrupt(ADC_T* adc, uint32_t interrupt)
  *
  * @retval    SET or RESET
  */
-uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
+uint8_t ADC_ReadStatusFlag(ADC_T *adc, ADC_FLAG_T flag)
 {
     return (adc->STS & flag) ? SET : RESET;
 }
@@ -967,7 +967,7 @@ uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag)
  *
  * @retval    None
  */
-void ADC_ClearStatusFlag(ADC_T* adc, uint32_t flag)
+void ADC_ClearStatusFlag(ADC_T *adc, uint32_t flag)
 {
     adc->STS = ~(uint32_t)flag;
 }
@@ -986,13 +986,13 @@ void ADC_ClearStatusFlag(ADC_T* adc, uint32_t flag)
  *
  * @retval    SET or RESET
  */
-uint16_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_FLAG_T flag)
+uint16_t ADC_ReadIntFlag(ADC_T *adc, ADC_INT_FLAG_T flag)
 {
     uint32_t itmask = 0;
     uint32_t intStatus = 0;
 
     itmask = (uint32_t)1 << (flag >> 8);
-    intStatus =adc->CTRL1 & itmask;
+    intStatus = adc->CTRL1 & itmask;
 
     if (((adc->STS & (uint32_t)(flag & 0x3F)) != (uint32_t)RESET) && intStatus)
     {
@@ -1018,7 +1018,7 @@ uint16_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_FLAG_T flag)
  *
  * @retval    None
  */
-void ADC_ClearIntFlag(ADC_T* adc, uint32_t flag)
+void ADC_ClearIntFlag(ADC_T *adc, uint32_t flag)
 {
     adc->STS = ~(uint32_t)(flag & 0x3F);
 }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_can.c

@@ -46,14 +46,14 @@
  *
  * @retval    None
  */
-void CAN_Reset(CAN_T* can)
+void CAN_Reset(CAN_T *can)
 {
-  if (can == CAN1)
-  {
+    if (can == CAN1)
+    {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN1);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN1);
-  }
-  else if (can == CAN2)
+    }
+    else if (can == CAN2)
     {
         RCM_EnableAPB1PeriphReset(RCM_APB1_PERIPH_CAN2);
         RCM_DisableAPB1PeriphReset(RCM_APB1_PERIPH_CAN2);
@@ -69,7 +69,7 @@ void CAN_Reset(CAN_T* can)
  *
  * @retval    ERROR or SUCCEESS
  */
-uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
+uint8_t CAN_Config(CAN_T *can, CAN_Config_T *canConfig)
 {
     uint8_t  initStatus = ERROR;
     uint32_t wait_ack = 0x00000000;
@@ -80,18 +80,18 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
     can->MCTRL_B.INITREQ = BIT_SET;
 
     /* Wait the acknowledge */
-    while(((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
+    while (((can->MSTS_B.INITFLG) != BIT_SET) && (wait_ack != 0x0000FFFF))
     {
         wait_ack++;
     }
     /* Check acknowledge */
-    if(((can->MSTS_B.INITFLG) != BIT_SET))
+    if (((can->MSTS_B.INITFLG) != BIT_SET))
     {
         initStatus = ERROR;
     }
     else
     {
-        if(canConfig->autoBusOffManage == ENABLE)
+        if (canConfig->autoBusOffManage == ENABLE)
         {
             can->MCTRL_B.ALBOFFM = BIT_SET;
         }
@@ -100,7 +100,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.ALBOFFM = BIT_RESET;
         }
 
-        if(canConfig->autoWakeUpMode == ENABLE)
+        if (canConfig->autoWakeUpMode == ENABLE)
         {
             can->MCTRL_B.AWUPCFG = BIT_SET;
         }
@@ -109,7 +109,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.AWUPCFG = BIT_RESET;
         }
 
-        if(canConfig->nonAutoRetran == ENABLE)
+        if (canConfig->nonAutoRetran == ENABLE)
         {
             can->MCTRL_B.ARTXMD = BIT_SET;
         }
@@ -118,7 +118,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.ARTXMD = BIT_RESET;
         }
 
-        if(canConfig->rxFIFOLockMode == ENABLE)
+        if (canConfig->rxFIFOLockMode == ENABLE)
         {
             can->MCTRL_B.RXFLOCK = BIT_SET;
         }
@@ -127,7 +127,7 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
             can->MCTRL_B.RXFLOCK = BIT_RESET;
         }
 
-        if(canConfig->txFIFOPriority == ENABLE)
+        if (canConfig->txFIFOPriority == ENABLE)
         {
             can->MCTRL_B.TXFPCFG = BIT_SET;
         }
@@ -149,12 +149,12 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
 
         wait_ack = 0;
         /* Wait the acknowledge */
-        while(((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
+        while (((can->MSTS_B.INITFLG) != BIT_RESET) && (wait_ack != 0x0000FFFF))
         {
             wait_ack++;
         }
         /* Check acknowledge */
-        if(((can->MSTS_B.INITFLG) != BIT_RESET))
+        if (((can->MSTS_B.INITFLG) != BIT_RESET))
         {
             initStatus = ERROR;
         }
@@ -175,14 +175,14 @@ uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig)
  *
  * @retval    None
  */
-void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig)
+void CAN_ConfigFilter(CAN_FilterConfig_T *filterConfig)
 {
     CAN1->FCTRL_B.FINITEN = BIT_SET;
 
     CAN1->FACT &= ~(1 << filterConfig->filterNumber);
 
     /* Filter Scale */
-    if(filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_16BIT)
     {
         /* 16-bit scale for the filter */
         CAN1->FSCFG &= ~(1 << filterConfig->filterNumber);
@@ -196,7 +196,7 @@ void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig)
             (0x0000FFFF & filterConfig->filterIdHigh);
     }
 
-    if(filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
+    if (filterConfig->filterScale == CAN_FILTER_SCALE_32BIT)
     {
         CAN1->FSCFG |= (1 << filterConfig->filterNumber);
 
@@ -210,7 +210,7 @@ void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig)
     }
 
     /* Filter Mode */
-    if(filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
+    if (filterConfig->filterMode == CAN_FILTER_MODE_IDMASK)
     {
         CAN1->FMCFG &= ~(1 << filterConfig->filterNumber);
     }
@@ -220,17 +220,17 @@ void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig)
     }
 
     /* Filter FIFO assignment */
-    if(filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_0)
     {
         CAN1->FFASS &= ~(1 << filterConfig->filterNumber);
     }
-    if(filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
+    if (filterConfig->filterFIFO == CAN_FILTER_FIFO_1)
     {
         CAN1->FFASS |= (1 << filterConfig->filterNumber);
     }
 
     /* Filter activation */
-    if(filterConfig->filterActivation == ENABLE)
+    if (filterConfig->filterActivation == ENABLE)
     {
         CAN1->FACT |= (1 << filterConfig->filterNumber);
     }
@@ -244,7 +244,7 @@ void CAN_ConfigFilter(CAN_FilterConfig_T* filterConfig)
  *
  * @retval    None
  */
-void CAN_ConfigStructInit(CAN_Config_T* canConfig)
+void CAN_ConfigStructInit(CAN_Config_T *canConfig)
 {
     canConfig->autoBusOffManage = DISABLE;
     canConfig->autoWakeUpMode   = DISABLE;
@@ -265,7 +265,7 @@ void CAN_ConfigStructInit(CAN_Config_T* canConfig)
  *
  * @retval    None
  */
-void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum)
+void CAN_SlaveStartBank(CAN_T *can, uint8_t bankNum)
 {
     can->FCTRL_B.FINITEN = SET;
     can->FCTRL_B.CAN2BN  = bankNum;
@@ -281,7 +281,7 @@ void CAN_SlaveStartBank(CAN_T* can, uint8_t bankNum)
  *
  * @note      None
  */
-void CAN_EnableDBGFreeze(CAN_T* can)
+void CAN_EnableDBGFreeze(CAN_T *can)
 {
     can->MCTRL_B.DBGFRZE = ENABLE;
 }
@@ -295,7 +295,7 @@ void CAN_EnableDBGFreeze(CAN_T* can)
  *
  * @note      None
  */
-void CAN_DisableDBGFreeze(CAN_T* can)
+void CAN_DisableDBGFreeze(CAN_T *can)
 {
     can->MCTRL_B.DBGFRZE = DISABLE;
 }
@@ -309,23 +309,24 @@ void CAN_DisableDBGFreeze(CAN_T* can)
  *
  * @retval    The number of the mailbox which is used for transmission or 3 if No mailbox is empty.
  */
-uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
+uint8_t CAN_TxMessage(CAN_T *can, CAN_TxMessage_T *TxMessage)
 {
     uint8_t transmit_milbox = 0;
 
     /* Select one empty transmit mailbox */
-    if((can->TXSTS & 0x04000000) == 0x04000000)
+    if ((can->TXSTS & 0x04000000) == 0x04000000)
     {
         transmit_milbox = 0;
     }
-    else if((can->TXSTS & 0x08000000) == 0x08000000)
+    else if ((can->TXSTS & 0x08000000) == 0x08000000)
     {
         transmit_milbox = 1;
     }
-    else if((can->TXSTS & 0x10000000) == 0x10000000)
+    else if ((can->TXSTS & 0x10000000) == 0x10000000)
     {
         transmit_milbox = 2;
-    } else
+    }
+    else
     {
         /* No mailbox is empty*/
         return 3;
@@ -333,10 +334,11 @@ uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
 
     /* Set up the Id */
     can->sTxMailBox[transmit_milbox].TXMID &= 0x00000001;
-    if(TxMessage->typeID == CAN_TYPEID_STD)
+    if (TxMessage->typeID == CAN_TYPEID_STD)
     {
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->stdID << 21) | (TxMessage->remoteTxReq);
-    } else
+    }
+    else
     {
         can->sTxMailBox[transmit_milbox].TXMID |= (TxMessage->extID << 3) | (TxMessage->typeID) | (TxMessage->remoteTxReq);
     }
@@ -372,45 +374,53 @@ uint8_t CAN_TxMessage(CAN_T* can, CAN_TxMessage_T* TxMessage)
  *                   1: Status of transmission is Ok
  *                   2: transmit pending
  */
-uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
+uint8_t CAN_TxMessageStatus(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
 {
     uint32_t state = 0;
 
     switch (TxMailbox)
     {
-        case (CAN_TX_MAILBIX_0):
-            state =   can->TXSTS &  (0x00000001 | 0x00000002 | 0x04000000);
+    case (CAN_TX_MAILBIX_0):
+        state =   can->TXSTS & (0x00000001 | 0x00000002 | 0x04000000);
         break;
-        case (CAN_TX_MAILBIX_1):
-            state =   can->TXSTS &  (0x00000100 | 0x00000200 | 0x08000000);
+    case (CAN_TX_MAILBIX_1):
+        state =   can->TXSTS & (0x00000100 | 0x00000200 | 0x08000000);
         break;
-        case (CAN_TX_MAILBIX_2):
-            state =   can->TXSTS &  (0x00010000 | 0x00020000 | 0x10000000);
+    case (CAN_TX_MAILBIX_2):
+        state =   can->TXSTS & (0x00010000 | 0x00020000 | 0x10000000);
         break;
-        default:
-            state = 0;
+    default:
+        state = 0;
         break;
     }
     switch (state)
     {
-        /** transmit pending  */
-        case (0x0): state = 2;
+    /** transmit pending  */
+    case (0x0):
+        state = 2;
         break;
-        /* transmit failed  */
-        case (0x00000001 | 0x04000000): state = 0;
+    /* transmit failed  */
+    case (0x00000001 | 0x04000000):
+        state = 0;
         break;
-        case (0x00000100 | 0x08000000): state = 0;
+    case (0x00000100 | 0x08000000):
+        state = 0;
         break;
-        case (0x00010000 | 0x10000000): state = 0;
+    case (0x00010000 | 0x10000000):
+        state = 0;
         break;
-        /* transmit succeeded  */
-        case (0x00000001 | 0x00000002 | 0x04000000):state = 1;
+    /* transmit succeeded  */
+    case (0x00000001 | 0x00000002 | 0x04000000):
+        state = 1;
         break;
-        case (0x00000100 | 0x00000200 | 0x08000000):state = 1;
+    case (0x00000100 | 0x00000200 | 0x08000000):
+        state = 1;
         break;
-        case (0x00010000 | 0x00020000 | 0x10000000):state = 1;
+    case (0x00010000 | 0x00020000 | 0x10000000):
+        state = 1;
         break;
-        default: state = 0;
+    default:
+        state = 0;
         break;
     }
     return (uint8_t) state;
@@ -429,7 +439,7 @@ uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @retval    None
  */
-void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
+void CAN_CancelTxMailbox(CAN_T *can, CAN_TX_MAILBIX_T TxMailbox)
 {
     switch (TxMailbox)
     {
@@ -461,11 +471,11 @@ void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox)
  *
  * @retval    None
  */
-void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMessage)
+void CAN_RxMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T *RxMessage)
 {
     /* Get the Id */
     RxMessage->typeID = ((uint8_t)0x04 & (can->sRxMailBox[FIFONumber].RXMID));
-    if(RxMessage->typeID == CAN_TYPEID_STD)
+    if (RxMessage->typeID == CAN_TYPEID_STD)
     {
         RxMessage->stdID = (can->sRxMailBox[FIFONumber].RXMID >> 21) & 0x000007FF;
     }
@@ -487,7 +497,7 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMess
     RxMessage->data[6] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE6;
     RxMessage->data[7] = can->sRxMailBox[FIFONumber].RXMDH_B.DATABYTE7;
 
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         can->RXF0_B.RFOM0 = BIT_SET;
     }
@@ -509,9 +519,9 @@ void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RxMessage_T* RxMess
  *
  * @retval    None
  */
-void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
+void CAN_ReleaseFIFO(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
 {
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         can->RXF0_B.RFOM0 = BIT_SET;
     }
@@ -533,9 +543,9 @@ void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
  *
  * @retval    The number of pending message.
  */
-uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
+uint8_t CAN_PendingMessage(CAN_T *can, CAN_RX_FIFO_T FIFONumber)
 {
-    if(FIFONumber == CAN_RX_FIFO_0)
+    if (FIFONumber == CAN_RX_FIFO_0)
     {
         return  can->RXF0 & 0x03;
     }
@@ -560,28 +570,28 @@ uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber)
  *                      0:CAN failed entering the specific mode
  *                      1:CAN Succeed entering the specific mode
  */
-uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
+uint8_t CAN_OperatingMode(CAN_T *can, CAN_OPERATING_MODE_T operatingMode)
 {
     uint8_t states = 0;
     uint32_t time_out = 0x0000FFFF;
 
-    if(operatingMode == CAN_OPERATING_MODE_INIT)
+    if (operatingMode == CAN_OPERATING_MODE_INIT)
     {
         /** Request initialisation */
         can->MCTRL_B.SLEEPREQ = BIT_RESET;
         can->MCTRL_B.INITREQ = BIT_SET;
 
         /* Wait the acknowledge */
-        while((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_SET && can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
+        if ((can->MSTS_B.INITFLG == BIT_SET && can->MSTS_B.SLEEPFLG == BIT_RESET))
         {
             states = 1;
         }
     }
-    else if(operatingMode == CAN_OPERATING_MODE_NORMAL)
+    else if (operatingMode == CAN_OPERATING_MODE_NORMAL)
     {
         /** Request leave initialisation and sleep mode  and enter Normal mode */
         can->MCTRL_B.SLEEPREQ = BIT_RESET;
@@ -589,16 +599,16 @@ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
 
         time_out = 0x0000FFFF;
 
-        while((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_RESET || can->MSTS_B.SLEEPFLG != BIT_RESET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
+        if ((can->MSTS_B.INITFLG == BIT_RESET || can->MSTS_B.SLEEPFLG == BIT_RESET))
         {
             states = 1;
         }
     }
-    else if(operatingMode == CAN_OPERATING_MODE_SLEEP)
+    else if (operatingMode == CAN_OPERATING_MODE_SLEEP)
     {
         /** Request Sleep mode */
         can->MCTRL_B.SLEEPREQ = BIT_SET;
@@ -606,11 +616,11 @@ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
 
         time_out = 0x0000FFFF;
 
-        while((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
+        while ((can->MSTS_B.INITFLG != BIT_RESET && can->MSTS_B.SLEEPFLG != BIT_SET) && (time_out != 0))
         {
             time_out --;
         }
-        if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
+        if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
         {
             states = 1;
         }
@@ -627,13 +637,13 @@ uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode)
  *                    0: Enter sleep fail
  *                    1: Enter sleep success
  */
-uint8_t CAN_SleepMode(CAN_T* can)
+uint8_t CAN_SleepMode(CAN_T *can)
 {
     /** Request Sleep mode */
     can->MCTRL_B.SLEEPREQ = BIT_SET;
     can->MCTRL_B.INITREQ = BIT_RESET;
 
-    if((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
+    if ((can->MSTS_B.INITFLG == BIT_RESET && can->MSTS_B.SLEEPFLG == BIT_SET))
     {
         return 1;
     }
@@ -649,17 +659,17 @@ uint8_t CAN_SleepMode(CAN_T* can)
  *                    0: WakeUp CAN fail,
  *                    1: WakeUp CAN success
  */
-uint8_t CAN_WakeUpMode(CAN_T* can)
+uint8_t CAN_WakeUpMode(CAN_T *can)
 {
     uint32_t time_out = 0x0000FFFF;
 
     /** Wake up request */
     can->MCTRL_B.SLEEPREQ = BIT_RESET;
-    while((can->MSTS_B.SLEEPFLG == BIT_SET) && (time_out != 0))
+    while ((can->MSTS_B.SLEEPFLG == BIT_SET) && (time_out != 0))
     {
         time_out --;
     }
-    if(can->MSTS_B.SLEEPFLG != BIT_SET)
+    if (can->MSTS_B.SLEEPFLG != BIT_SET)
     {
         return 1;
     }
@@ -673,7 +683,7 @@ uint8_t CAN_WakeUpMode(CAN_T* can)
  *
  * @retval    The Last Error Code.
  */
-uint8_t CAN_ReadLastErrorCode(CAN_T* can)
+uint8_t CAN_ReadLastErrorCode(CAN_T *can)
 {
     return can->ERRSTS_B.LERRC;
 }
@@ -685,7 +695,7 @@ uint8_t CAN_ReadLastErrorCode(CAN_T* can)
  *
  * @retval    CAN Receive Error Counter.
  */
-uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
+uint8_t CAN_ReadRxErrorCounter(CAN_T *can)
 {
     return can->ERRSTS_B.RXERRCNT;
 }
@@ -697,7 +707,7 @@ uint8_t CAN_ReadRxErrorCounter(CAN_T* can)
  *
  * @retval    Least Significant Byte Of The 9-Bit Transmit Error Counter.
  */
-uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T *can)
 {
     return can->ERRSTS_B.TXERRCNT;
 }
@@ -726,7 +736,7 @@ uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can)
  *
  * @retval    None
  */
-void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
+void CAN_EnableInterrupt(CAN_T *can, uint32_t interrupts)
 {
     can->INTEN |= interrupts;
 }
@@ -755,7 +765,7 @@ void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupts)
  *
  * @retval    None
  */
-void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
+void CAN_DisableInterrupt(CAN_T *can, uint32_t interrupts)
 {
     can->INTEN &= ~interrupts;
 }
@@ -785,13 +795,13 @@ void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupts)
  *
  * @retval    flag staus:  RESET or SET
  */
-uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
+uint8_t CAN_ReadStatusFlag(CAN_T *can, CAN_FLAG_T flag)
 {
     uint8_t status = 0;
 
-    if((flag & 0x00F00000) != RESET )
+    if ((flag & 0x00F00000) != RESET)
     {
-        if((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
+        if ((can->ERRSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -800,9 +810,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET;
         }
     }
-    else if((flag & 0x01000000) != RESET )
+    else if ((flag & 0x01000000) != RESET)
     {
-        if((can->MSTS & (flag & 0x000FFFFF)) != RESET )
+        if ((can->MSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -811,9 +821,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET ;
         }
     }
-    else if((flag & 0x08000000) != RESET )
+    else if ((flag & 0x08000000) != RESET)
     {
-        if((can->TXSTS & (flag & 0x000FFFFF)) != RESET )
+        if ((can->TXSTS & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -822,9 +832,9 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
             status = RESET;
         }
     }
-    else if((flag & 0x02000000) != RESET )
+    else if ((flag & 0x02000000) != RESET)
     {
-        if((can->RXF0 & (flag & 0x000FFFFF)) != RESET )
+        if ((can->RXF0 & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -835,7 +845,7 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
     }
     else
     {
-        if((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
+        if ((can->RXF1 & (flag & 0x000FFFFF)) != RESET)
         {
             status = SET;
         }
@@ -867,27 +877,27 @@ uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag)
  *
  * @retval    None
  */
-void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
+void CAN_ClearStatusFlag(CAN_T *can, CAN_FLAG_T flag)
 {
     uint32_t flagtmp = 0;
 
     /** ERRSTS register */
-    if(flag == 0x30F00070)
+    if (flag == 0x30F00070)
     {
         can->ERRSTS = RESET;
     }
     else
     {
         flagtmp = flag & 0x000FFFFF;
-        if((flag & 0x02000000) != RESET)
+        if ((flag & 0x02000000) != RESET)
         {
             can->RXF0 = flagtmp;
         }
-        else if((flag & 0x04000000) != RESET)
+        else if ((flag & 0x04000000) != RESET)
         {
             can->RXF1 = flagtmp;
         }
-        else if((flag & 0x08000000) != RESET)
+        else if ((flag & 0x08000000) != RESET)
         {
             can->TXSTS = flagtmp;
         }
@@ -922,11 +932,11 @@ void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag)
  *
  * @retval    status : SET or RESET
  */
-uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
+uint8_t CAN_ReadIntFlag(CAN_T *can, CAN_INT_T flag)
 {
     uint8_t status = 0;
 
-    if((can->INTEN & flag) != RESET)
+    if ((can->INTEN & flag) != RESET)
     {
         switch (flag)
         {
@@ -1008,7 +1018,7 @@ uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag)
  *
  * @retval    None
  */
-void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag)
+void CAN_ClearIntFlag(CAN_T *can, CAN_INT_T flag)
 {
     switch (flag)
     {

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_crc.c

@@ -76,7 +76,7 @@ uint32_t CRC_CalculateCRC(uint32_t data)
  */
 uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen)
 {
-    while(bufLen--)
+    while (bufLen--)
     {
         CRC->DATA = *buf++;
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_cryp.c

@@ -59,7 +59,7 @@ void CRYP_Reset(void)
  *
  * @retval    None
  */
-void CRYP_Config(CRYP_Config_T* crypConfig)
+void CRYP_Config(CRYP_Config_T *crypConfig)
 {
     CRYP->CTRL_B.ALGODIRSEL = crypConfig->algoDir;
     CRYP->CTRL_B.ALGOMSEL   = crypConfig->algoMode;
@@ -79,7 +79,7 @@ void CRYP_Config(CRYP_Config_T* crypConfig)
  *
  * @retval    None
  */
-void CRYP_ConfigStructInit(CRYP_Config_T* crypConfig)
+void CRYP_ConfigStructInit(CRYP_Config_T *crypConfig)
 {
     crypConfig->algoDir  = CRYP_ALGODIR_ENCRYPT;
     crypConfig->algoMode = CRYP_ALGOMODE_TDES_ECB;
@@ -94,7 +94,7 @@ void CRYP_ConfigStructInit(CRYP_Config_T* crypConfig)
  *
  * @retval    None
  */
-void CRYP_ConfigKey(CRYP_KeyConfig_T* keyConfig)
+void CRYP_ConfigKey(CRYP_KeyConfig_T *keyConfig)
 {
     /* Key Initialisation */
     CRYP->K0L = keyConfig->key0Left;
@@ -114,7 +114,7 @@ void CRYP_ConfigKey(CRYP_KeyConfig_T* keyConfig)
  *
  * @retval    None
  */
-void CRYP_ConfigKeyStructInit(CRYP_KeyConfig_T* keyConfig)
+void CRYP_ConfigKeyStructInit(CRYP_KeyConfig_T *keyConfig)
 {
     keyConfig->key0Left  = 0;
     keyConfig->key0Right = 0;
@@ -133,7 +133,7 @@ void CRYP_ConfigKeyStructInit(CRYP_KeyConfig_T* keyConfig)
  *
  * @retval    None
  */
-void CRYP_ConfigIV(CRYP_IVConfig_T* IVConfig)
+void CRYP_ConfigIV(CRYP_IVConfig_T *IVConfig)
 {
     CRYP->IV0L = IVConfig->IV0Left;
     CRYP->IV0R = IVConfig->IV0Right;
@@ -148,7 +148,7 @@ void CRYP_ConfigIV(CRYP_IVConfig_T* IVConfig)
  *
  * @retval    None
  */
-void CRYP_ConfigIVStructInit(CRYP_IVConfig_T* IVConfig)
+void CRYP_ConfigIVStructInit(CRYP_IVConfig_T *IVConfig)
 {
     IVConfig->IV0Left  = 0;
     IVConfig->IV0Right = 0;
@@ -233,12 +233,12 @@ uint32_t CRYP_OutData(void)
  *            restoring the context, you have to enable the DMA again (if the DMA
  *            was previously used).
  */
-uint32_t CRYP_SaveContext(CRYP_Context_T* context, CRYP_KeyConfig_T* keyConfig)
+uint32_t CRYP_SaveContext(CRYP_Context_T *context, CRYP_KeyConfig_T *keyConfig)
 {
     uint32_t flag = 0;
-    uint32_t bitstatus=0;
+    uint32_t bitstatus = 0;
     uint32_t timeout = 0;
-    uint32_t status=0;
+    uint32_t status = 0;
 
     /* Stop DMA transfers on the IN FIFO */
     CRYP->DMACTRL_B.INEN = RESET;
@@ -305,7 +305,7 @@ uint32_t CRYP_SaveContext(CRYP_Context_T* context, CRYP_KeyConfig_T* keyConfig)
  *            after restoring the context, you have to enable the DMA again (if the
  *            DMA was previously used).
  */
-void CRYP_RestoreContext(CRYP_Context_T* context)
+void CRYP_RestoreContext(CRYP_Context_T *context)
 {
     /* Restore The CTRL value */
     CRYP->CTRL = context->curCTRL;
@@ -341,11 +341,11 @@ void CRYP_RestoreContext(CRYP_Context_T* context)
  */
 void CRYP_EnableDMA(CRYP_DMAREQ_T dmaReq)
 {
-    if(dmaReq == CRYP_DMAREQ_DATAIN)
+    if (dmaReq == CRYP_DMAREQ_DATAIN)
     {
         CRYP->DMACTRL_B.INEN = SET;
     }
-    else if(dmaReq == CRYP_DMAREQ_DATAOUT)
+    else if (dmaReq == CRYP_DMAREQ_DATAOUT)
     {
         CRYP->DMACTRL_B.OUTEN = SET;
     }
@@ -363,11 +363,11 @@ void CRYP_EnableDMA(CRYP_DMAREQ_T dmaReq)
  */
 void CRYP_DisableDMA(CRYP_DMAREQ_T dmaReq)
 {
-    if(dmaReq == CRYP_DMAREQ_DATAIN)
+    if (dmaReq == CRYP_DMAREQ_DATAIN)
     {
         CRYP->DMACTRL_B.INEN = RESET;
     }
-    else if(dmaReq == CRYP_DMAREQ_DATAOUT)
+    else if (dmaReq == CRYP_DMAREQ_DATAOUT)
     {
         CRYP->DMACTRL_B.OUTEN = RESET;
     }
@@ -436,13 +436,13 @@ uint8_t CRYP_ReadIntFlag(CRYP_INT_T flag)
  */
 uint8_t CRYP_ReadStatusFlag(CRYP_FLAG_T flag)
 {
-    if(flag & 0x20)
+    if (flag & 0x20)
     {
         return (CRYP->INTSTS & flag) ? SET : RESET;
     }
     else
     {
-       return (CRYP->STS & flag) ? SET : RESET;
+        return (CRYP->STS & flag) ? SET : RESET;
     }
 }
 

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_cryp_aes.c

@@ -56,7 +56,7 @@
  * @retval    SUCCESS or ERROR
  */
 uint8_t CRYP_AES_ECB(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
-                       uint8_t *input, uint32_t length, uint8_t  *output)
+                     uint8_t *input, uint32_t length, uint8_t  *output)
 {
     CRYP_Config_T    AES_crypConfig;
     CRYP_KeyConfig_T AES_keyConfig;
@@ -72,58 +72,58 @@ uint8_t CRYP_AES_ECB(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
 
     CRYP_ConfigKeyStructInit(&AES_keyConfig);
 
-    switch(keysize)
+    switch (keysize)
     {
-        case 128:
+    case 128:
         AES_crypConfig.keySize = CRYP_KEYSIZE_128B;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        case 192:
+    case 192:
         AES_crypConfig.keySize = CRYP_KEYSIZE_192B;
-        AES_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        case 256:
+    case 256:
         AES_crypConfig.keySize = CRYP_KEYSIZE_256B;
-        AES_keyConfig.key0Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key0Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key0Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key0Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        default:
+    default:
         break;
     }
 
-    if(mode == CRYP_MODE_DECRYPT)
+    if (mode == CRYP_MODE_DECRYPT)
     {
         CRYP_FlushFIFO();
 
@@ -140,9 +140,9 @@ uint8_t CRYP_AES_ECB(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
             flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
             counter++;
         }
-        while((counter != 0x00010000) && (flag != RESET));
+        while ((counter != 0x00010000) && (flag != RESET));
 
-        if(flag == SET)
+        if (flag == SET)
         {
             status = ERROR;
         }
@@ -164,20 +164,20 @@ uint8_t CRYP_AES_ECB(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
 
-    for(i=0; i<length; i+=16)
+    for (i = 0; i < length; i += 16)
     {
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
 
         counter = 0;
@@ -186,21 +186,21 @@ uint8_t CRYP_AES_ECB(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
             flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
             counter++;
         }
-        while((counter != 0x00010000) && (flag != RESET));
+        while ((counter != 0x00010000) && (flag != RESET));
 
-        if(flag == SET)
+        if (flag == SET)
         {
             status = ERROR;
         }
         else
         {
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
         }
     }
@@ -226,8 +226,8 @@ uint8_t CRYP_AES_ECB(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
  * @retval    SUCCESS or ERROR
  */
 uint8_t CRYP_AES_CBC(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
-                                       uint8_t IV[16],  uint8_t  *input,
-                                       uint32_t length, uint8_t  *output)
+                     uint8_t IV[16],  uint8_t  *input,
+                     uint32_t length, uint8_t  *output)
 {
     CRYP_Config_T    AES_crypConfig;
     CRYP_KeyConfig_T AES_keyConfig;
@@ -245,66 +245,66 @@ uint8_t CRYP_AES_CBC(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
 
     CRYP_ConfigKeyStructInit(&AES_keyConfig);
 
-    switch(keysize)
+    switch (keysize)
     {
-        case 128:
+    case 128:
         AES_crypConfig.keySize = CRYP_KEYSIZE_128B;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        case 192:
+    case 192:
         AES_crypConfig.keySize = CRYP_KEYSIZE_192B;
-        AES_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        case 256:
+    case 256:
         AES_crypConfig.keySize = CRYP_KEYSIZE_256B;
-        AES_keyConfig.key0Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key0Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key0Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key0Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        default:
+    default:
         break;
     }
 
-    AES_IVConfig.IV0Left  = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV0Left  = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    AES_IVConfig.IV0Right = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV0Right = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    AES_IVConfig.IV1Left  = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV1Left  = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    AES_IVConfig.IV1Right = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV1Right = __REV(*(uint32_t *)(IVAddr));
 
-    if(mode == CRYP_MODE_DECRYPT)
+    if (mode == CRYP_MODE_DECRYPT)
     {
         CRYP_FlushFIFO();
 
@@ -321,9 +321,9 @@ uint8_t CRYP_AES_CBC(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
             flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
             counter++;
         }
-        while((counter != 0x00010000) && (flag != RESET));
+        while ((counter != 0x00010000) && (flag != RESET));
 
-        if(flag == SET)
+        if (flag == SET)
         {
             status = ERROR;
         }
@@ -345,20 +345,20 @@ uint8_t CRYP_AES_CBC(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
 
-    for(i=0; i<length; i+=16)
+    for (i = 0; i < length; i += 16)
     {
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
 
         counter = 0;
@@ -367,21 +367,21 @@ uint8_t CRYP_AES_CBC(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
             flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
             counter++;
         }
-        while((counter != 0x00010000) && (flag != RESET));
+        while ((counter != 0x00010000) && (flag != RESET));
 
-        if(flag == SET)
+        if (flag == SET)
         {
             status = ERROR;
         }
         else
         {
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
         }
     }
@@ -407,8 +407,8 @@ uint8_t CRYP_AES_CBC(CRYP_MODE_T mode, uint8_t *key,    uint16_t keysize,
  * @retval    SUCCESS or ERROR
  */
 uint8_t CRYP_AES_CTR(CRYP_MODE_T mode, uint8_t  *key,   uint16_t keysize,
-                                       uint8_t  IV[16], uint8_t  *input,
-                                       uint32_t length, uint8_t  *output)
+                     uint8_t  IV[16], uint8_t  *input,
+                     uint32_t length, uint8_t  *output)
 {
     CRYP_Config_T    AES_crypConfig;
     CRYP_KeyConfig_T AES_keyConfig;
@@ -426,68 +426,68 @@ uint8_t CRYP_AES_CTR(CRYP_MODE_T mode, uint8_t  *key,   uint16_t keysize,
 
     CRYP_ConfigKeyStructInit(&AES_keyConfig);
 
-    switch(keysize)
+    switch (keysize)
     {
-        case 128:
+    case 128:
         AES_crypConfig.keySize = CRYP_KEYSIZE_128B;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        case 192:
+    case 192:
         AES_crypConfig.keySize = CRYP_KEYSIZE_192B;
-        AES_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        case 256:
+    case 256:
         AES_crypConfig.keySize = CRYP_KEYSIZE_256B;
-        AES_keyConfig.key0Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key0Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key0Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key0Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
         keyAddr += 0x04;
-        AES_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+        AES_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
         break;
 
-        default:
+    default:
         break;
     }
 
-    AES_IVConfig.IV0Left  = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV0Left  = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    AES_IVConfig.IV0Right = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV0Right = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    AES_IVConfig.IV1Left  = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV1Left  = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    AES_IVConfig.IV1Right = __REV(*(uint32_t*)(IVAddr));
+    AES_IVConfig.IV1Right = __REV(*(uint32_t *)(IVAddr));
 
     CRYP_ConfigKey(&AES_keyConfig);
 
-    if(mode == CRYP_MODE_DECRYPT)
+    if (mode == CRYP_MODE_DECRYPT)
     {
         AES_crypConfig.algoDir  = CRYP_ALGODIR_DECRYPT;
     }
@@ -504,20 +504,20 @@ uint8_t CRYP_AES_CTR(CRYP_MODE_T mode, uint8_t  *key,   uint16_t keysize,
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
 
-    for(i=0; i<length; i+=16)
+    for (i = 0; i < length; i += 16)
     {
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
-        CRYP_InData(*(uint32_t*)(inputAddr));
+        CRYP_InData(*(uint32_t *)(inputAddr));
         inputAddr += 0x04;
 
         counter = 0;
@@ -526,21 +526,21 @@ uint8_t CRYP_AES_CTR(CRYP_MODE_T mode, uint8_t  *key,   uint16_t keysize,
             flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
             counter++;
         }
-        while((counter != 0x00010000) && (flag != RESET));
+        while ((counter != 0x00010000) && (flag != RESET));
 
-        if(flag == SET)
+        if (flag == SET)
         {
             status = ERROR;
         }
         else
         {
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
-            *(uint32_t*)(outputAddr) = CRYP_OutData();
+            *(uint32_t *)(outputAddr) = CRYP_OutData();
             outputAddr += 0x04;
         }
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_cryp_des.c

@@ -55,7 +55,7 @@
  * @retval    SUCCESS or ERROR
  */
 uint8_t CRYP_DES_ECB(CRYP_MODE_T mode, uint8_t key[8], uint8_t *input,
-                                      uint32_t length, uint8_t *output)
+                     uint32_t length, uint8_t *output)
 {
     CRYP_Config_T    DEC_crypConfig;
     CRYP_KeyConfig_T DEC_keyConfig;
@@ -71,7 +71,7 @@ uint8_t CRYP_DES_ECB(CRYP_MODE_T mode, uint8_t key[8], uint8_t *input,
 
     CRYP_ConfigKeyStructInit(&DEC_keyConfig);
 
-    if(mode == CRYP_MODE_ENCRYPT)
+    if (mode == CRYP_MODE_ENCRYPT)
     {
         DEC_crypConfig.algoDir = CRYP_ALGODIR_ENCRYPT;
     }
@@ -83,25 +83,25 @@ uint8_t CRYP_DES_ECB(CRYP_MODE_T mode, uint8_t key[8], uint8_t *input,
     DEC_crypConfig.dataType = CRYP_DATATYPE_8B;
     CRYP_Config(&DEC_crypConfig);
 
-    DEC_keyConfig.key1Left = __REV(*(uint32_t*)(keyAddr));
+    DEC_keyConfig.key1Left = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    DEC_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+    DEC_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
     CRYP_ConfigKey(&DEC_keyConfig);
 
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
     else
     {
-        for(i=0; i<length; i+=8)
+        for (i = 0; i < length; i += 8)
         {
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
 
             counter = 0;
@@ -110,17 +110,17 @@ uint8_t CRYP_DES_ECB(CRYP_MODE_T mode, uint8_t key[8], uint8_t *input,
                 flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
                 counter++;
             }
-            while((counter != 0x00010000) && (flag != RESET));
+            while ((counter != 0x00010000) && (flag != RESET));
 
-            if(flag == SET)
+            if (flag == SET)
             {
                 status = ERROR;
             }
             else
             {
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
             }
         }
@@ -146,7 +146,7 @@ uint8_t CRYP_DES_ECB(CRYP_MODE_T mode, uint8_t key[8], uint8_t *input,
  * @retval    None
  */
 uint8_t CRYP_DES_CBC(CRYP_MODE_T mode, uint8_t key[8],  uint8_t *input,
-                        uint8_t IV[8], uint32_t length, uint8_t *output)
+                     uint8_t IV[8], uint32_t length, uint8_t *output)
 {
     CRYP_Config_T    DEC_crypConfig;
     CRYP_KeyConfig_T DEC_keyConfig;
@@ -164,7 +164,7 @@ uint8_t CRYP_DES_CBC(CRYP_MODE_T mode, uint8_t key[8],  uint8_t *input,
 
     CRYP_ConfigKeyStructInit(&DEC_keyConfig);
 
-    if(mode == CRYP_MODE_ENCRYPT)
+    if (mode == CRYP_MODE_ENCRYPT)
     {
         DEC_crypConfig.algoDir = CRYP_ALGODIR_ENCRYPT;
     }
@@ -176,30 +176,30 @@ uint8_t CRYP_DES_CBC(CRYP_MODE_T mode, uint8_t key[8],  uint8_t *input,
     DEC_crypConfig.dataType = CRYP_DATATYPE_8B;
     CRYP_Config(&DEC_crypConfig);
 
-    DEC_keyConfig.key1Left = __REV(*(uint32_t*)(keyAddr));
+    DEC_keyConfig.key1Left = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    DEC_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+    DEC_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
     CRYP_ConfigKey(&DEC_keyConfig);
 
-    DEC_IVConfig.IV0Left  = __REV(*(uint32_t*)(IVAddr));
+    DEC_IVConfig.IV0Left  = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    DEC_IVConfig.IV0Right = __REV(*(uint32_t*)(IVAddr));
+    DEC_IVConfig.IV0Right = __REV(*(uint32_t *)(IVAddr));
     CRYP_ConfigIV(&DEC_IVConfig);
 
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
     else
     {
-        for(i=0; i<length; i+=8)
+        for (i = 0; i < length; i += 8)
         {
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
 
             counter = 0;
@@ -208,17 +208,17 @@ uint8_t CRYP_DES_CBC(CRYP_MODE_T mode, uint8_t key[8],  uint8_t *input,
                 flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
                 counter++;
             }
-            while((counter != 0x00010000) && (flag != RESET));
+            while ((counter != 0x00010000) && (flag != RESET));
 
-            if(flag == SET)
+            if (flag == SET)
             {
                 status = ERROR;
             }
             else
             {
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
             }
         }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_cryp_tdes.c

@@ -55,7 +55,7 @@
  * @retval    SUCCESS or ERROR
  */
 uint8_t CRYP_TDES_ECB(CRYP_MODE_T mode, uint8_t key[24], uint8_t *input,
-                                       uint32_t length,  uint8_t *output)
+                      uint32_t length,  uint8_t *output)
 {
     CRYP_Config_T    TDEC_crypConfig;
     CRYP_KeyConfig_T TDEC_keyConfig;
@@ -71,7 +71,7 @@ uint8_t CRYP_TDES_ECB(CRYP_MODE_T mode, uint8_t key[24], uint8_t *input,
 
     CRYP_ConfigKeyStructInit(&TDEC_keyConfig);
 
-    if(mode == CRYP_MODE_ENCRYPT)
+    if (mode == CRYP_MODE_ENCRYPT)
     {
         TDEC_crypConfig.algoDir = CRYP_ALGODIR_ENCRYPT;
     }
@@ -83,33 +83,33 @@ uint8_t CRYP_TDES_ECB(CRYP_MODE_T mode, uint8_t key[24], uint8_t *input,
     TDEC_crypConfig.dataType = CRYP_DATATYPE_8B;
     CRYP_Config(&TDEC_crypConfig);
 
-    TDEC_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
     CRYP_ConfigKey(&TDEC_keyConfig);
 
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
     else
     {
-        for(i=0; i<length; i+=8)
+        for (i = 0; i < length; i += 8)
         {
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
 
             counter = 0;
@@ -118,17 +118,17 @@ uint8_t CRYP_TDES_ECB(CRYP_MODE_T mode, uint8_t key[24], uint8_t *input,
                 flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
                 counter++;
             }
-            while((counter != 0x00010000) && (flag != RESET));
+            while ((counter != 0x00010000) && (flag != RESET));
 
-            if(flag == SET)
+            if (flag == SET)
             {
                 status = ERROR;
             }
             else
             {
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
             }
         }
@@ -153,8 +153,8 @@ uint8_t CRYP_TDES_ECB(CRYP_MODE_T mode, uint8_t key[24], uint8_t *input,
  *
  * @retval    None
  */
-uint8_t CRYP_TDES_CBC(CRYP_MODE_T mode,uint8_t key[24], uint8_t *input,
-                        uint8_t IV[8], uint32_t length, uint8_t *output)
+uint8_t CRYP_TDES_CBC(CRYP_MODE_T mode, uint8_t key[24], uint8_t *input,
+                      uint8_t IV[8], uint32_t length, uint8_t *output)
 {
     CRYP_Config_T    TDEC_crypConfig;
     CRYP_KeyConfig_T TDEC_keyConfig;
@@ -172,7 +172,7 @@ uint8_t CRYP_TDES_CBC(CRYP_MODE_T mode,uint8_t key[24], uint8_t *input,
 
     CRYP_ConfigKeyStructInit(&TDEC_keyConfig);
 
-    if(mode == CRYP_MODE_ENCRYPT)
+    if (mode == CRYP_MODE_ENCRYPT)
     {
         TDEC_crypConfig.algoDir = CRYP_ALGODIR_ENCRYPT;
     }
@@ -184,38 +184,38 @@ uint8_t CRYP_TDES_CBC(CRYP_MODE_T mode,uint8_t key[24], uint8_t *input,
     TDEC_crypConfig.dataType = CRYP_DATATYPE_8B;
     CRYP_Config(&TDEC_crypConfig);
 
-    TDEC_keyConfig.key1Left  = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key1Left  = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key1Right = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key1Right = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key2Left  = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key2Left  = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key2Right = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key2Right = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key3Left  = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key3Left  = __REV(*(uint32_t *)(keyAddr));
     keyAddr += 0x04;
-    TDEC_keyConfig.key3Right = __REV(*(uint32_t*)(keyAddr));
+    TDEC_keyConfig.key3Right = __REV(*(uint32_t *)(keyAddr));
     CRYP_ConfigKey(&TDEC_keyConfig);
 
-    TDEC_IVConfig.IV0Left  = __REV(*(uint32_t*)(IVAddr));
+    TDEC_IVConfig.IV0Left  = __REV(*(uint32_t *)(IVAddr));
     keyAddr += 0x04;
-    TDEC_IVConfig.IV0Right = __REV(*(uint32_t*)(IVAddr));
+    TDEC_IVConfig.IV0Right = __REV(*(uint32_t *)(IVAddr));
     CRYP_ConfigIV(&TDEC_IVConfig);
 
     CRYP_FlushFIFO();
     CRYP_Enable();
 
-    if(CRYP_ReadCmdStatus() == DISABLE)
+    if (CRYP_ReadCmdStatus() == DISABLE)
     {
         status = ERROR;
     }
     else
     {
-        for(i=0; i<length; i+=8)
+        for (i = 0; i < length; i += 8)
         {
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
-            CRYP_InData(*(uint32_t*)(inputAddr));
+            CRYP_InData(*(uint32_t *)(inputAddr));
             inputAddr += 0x04;
 
             counter = 0;
@@ -224,17 +224,17 @@ uint8_t CRYP_TDES_CBC(CRYP_MODE_T mode,uint8_t key[24], uint8_t *input,
                 flag = CRYP_ReadStatusFlag(CRYP_FLAG_BUSY);
                 counter++;
             }
-            while((counter != 0x00010000) && (flag != RESET));
+            while ((counter != 0x00010000) && (flag != RESET));
 
-            if(flag == SET)
+            if (flag == SET)
             {
                 status = ERROR;
             }
             else
             {
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
-                *(uint32_t*)(outputAddr) = CRYP_OutData();
+                *(uint32_t *)(outputAddr) = CRYP_OutData();
                 outputAddr += 0x04;
             }
         }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_dac.c

@@ -64,7 +64,7 @@ void DAC_Reset(void)
  *
  * @retval    None
  */
-void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
+void DAC_Config(uint32_t channel, DAC_Config_T *dacConfig)
 {
     uint32_t temp1 = 0, temp2 = 0;
 
@@ -89,7 +89,7 @@ void DAC_Config(uint32_t channel, DAC_Config_T* dacConfig)
  *
  * @retval    None
  */
-void DAC_ConfigStructInit(DAC_Config_T* dacConfig)
+void DAC_ConfigStructInit(DAC_Config_T *dacConfig)
 {
     dacConfig->trigger = DAC_TRIGGER_NONE;
     dacConfig->waveGeneration = DAC_WAVE_GENERATION_NONE;
@@ -398,7 +398,7 @@ uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel)
     temp += 0x0000002C + ((uint32_t)channel >> 2);
 
     /* Returns the DAC channel data output register value */
-    return (uint16_t) (*(__IO uint32_t*) temp);
+    return (uint16_t)(*(__IO uint32_t *) temp);
 }
 
 /*!

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_dbgmcu.c

@@ -47,7 +47,7 @@
  */
 uint32_t DBGMCU_ReadDEVID(void)
 {
-    return(DBGMCU->IDCODE_B.EQR);
+    return (DBGMCU->IDCODE_B.EQR);
 }
 
 /*!
@@ -59,7 +59,7 @@ uint32_t DBGMCU_ReadDEVID(void)
  */
 uint32_t DBGMCU_ReadREVID(void)
 {
-    return(DBGMCU->IDCODE_B.WVR);
+    return (DBGMCU->IDCODE_B.WVR);
 }
 
 /*!

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_dci.c

@@ -64,7 +64,7 @@ void DCI_Rest(void)
  *
  * @retval    None
  */
-void DCI_Config(DCI_Config_T* dciConfig)
+void DCI_Config(DCI_Config_T *dciConfig)
 {
     DCI->CTRL_B.CMODE    = dciConfig->captureMode;
     DCI->CTRL_B.ESYNCSEL = dciConfig->synchroMode;
@@ -82,7 +82,7 @@ void DCI_Config(DCI_Config_T* dciConfig)
  *
  * @retval    None
  */
-void DCI_ConfigStructInit(DCI_Config_T* dciConfig)
+void DCI_ConfigStructInit(DCI_Config_T *dciConfig)
 {
     dciConfig->captureMode      = DCI_CAPTURE_MODE_CONTINUOUS;
     dciConfig->synchroMode      = DCI_SYNCHRO_MODE_HARDWARE;
@@ -100,7 +100,7 @@ void DCI_ConfigStructInit(DCI_Config_T* dciConfig)
  *
  * @retval      None
  */
-void DCI_ConfigCROP(DCI_CropConfig_T* cropConfig)
+void DCI_ConfigCROP(DCI_CropConfig_T *cropConfig)
 {
     DCI->CROPWSTAT_B.HOFSCNT   = (uint16_t)cropConfig->horizontalOffsetCount;
     DCI->CROPWSTAT_B.VSLINECNT = (uint16_t)cropConfig->verticalStartLine;
@@ -140,7 +140,7 @@ void DCI_DisableCROP(void)
  *
  * @retval    None
  */
-void DCI_ConfigSynchroCode(DCI_CodeConfig_T* codeConfig)
+void DCI_ConfigSynchroCode(DCI_CodeConfig_T *codeConfig)
 {
     DCI->ESYNCC_B.FSDC = (uint8_t)codeConfig->frameStartCode;
     DCI->ESYNCC_B.LSDC = (uint8_t)codeConfig->lineStartCode;
@@ -297,7 +297,7 @@ uint16_t DCI_ReadStatusFlag(DCI_FLAG_T flag)
 
     if (offset == 0x00)
     {
-        temp= DCI->RINTSTS;
+        temp = DCI->RINTSTS;
     }
     else if (offset == 0x01)
     {
@@ -307,7 +307,7 @@ uint16_t DCI_ReadStatusFlag(DCI_FLAG_T flag)
     {
         temp = DCI->STS;
     }
-    return(temp & flag) ? SET : RESET;
+    return (temp & flag) ? SET : RESET;
 }
 
 /*!

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_dma.c

@@ -48,7 +48,7 @@
  *
  * @note      DMA2 channel only for APM32 High density devices.
  */
-void DMA_Reset(DMA_Stream_T* stream)
+void DMA_Reset(DMA_Stream_T *stream)
 {
     stream->SCFG_B.EN  =  BIT_RESET;
     stream->SCFG       =  0;
@@ -56,7 +56,7 @@ void DMA_Reset(DMA_Stream_T* stream)
     stream->PADDR      =  0;
     stream->M0ADDR     =  0;
     stream->M1ADDR     =  0;
-    stream->FCTRL      =  (uint32_t)0x00000021;
+    stream->FCTRL      = (uint32_t)0x00000021;
 
     if (stream == DMA1_Stream0)
     {
@@ -135,7 +135,7 @@ void DMA_Reset(DMA_Stream_T* stream)
  *
  * @note      DMA2 channel only for APM32 High density devices.
  */
-void DMA_Config(DMA_Stream_T* stream, DMA_Config_T* dmaConfig)
+void DMA_Config(DMA_Stream_T *stream, DMA_Config_T *dmaConfig)
 {
     stream->SCFG_B.DIRCFG = dmaConfig->dir;
     stream->SCFG_B.CIRCMEN = dmaConfig->loopMode;
@@ -163,7 +163,7 @@ void DMA_Config(DMA_Stream_T* stream, DMA_Config_T* dmaConfig)
  *
  * @retval    None
  */
-void DMA_ConfigStructInit( DMA_Config_T* dmaConfig)
+void DMA_ConfigStructInit(DMA_Config_T *dmaConfig)
 {
     dmaConfig->channel = DMA_CHANNEL_0;
     dmaConfig->peripheralBaseAddr = 0;
@@ -191,7 +191,7 @@ void DMA_ConfigStructInit( DMA_Config_T* dmaConfig)
  *
  * @note      DMA2 channel only for APM32 High density devices.
  */
-void DMA_Enable(DMA_Stream_T* stream)
+void DMA_Enable(DMA_Stream_T *stream)
 {
     stream->SCFG_B.EN = ENABLE;
 }
@@ -205,7 +205,7 @@ void DMA_Enable(DMA_Stream_T* stream)
  *
  * @note      DMA2 channel only for APM32 High density devices.
  */
-void DMA_Disable(DMA_Stream_T* stream)
+void DMA_Disable(DMA_Stream_T *stream)
 {
     stream->SCFG_B.EN = DISABLE;
 }
@@ -224,7 +224,7 @@ void DMA_Disable(DMA_Stream_T* stream)
  *
  * @note      DMA2 Stream only for APM32 High density devices.
  */
-void DMA_ConfigPeriphIncOffsetSize(DMA_Stream_T* stream, DMA_PERIOSIZE_T perioSize)
+void DMA_ConfigPeriphIncOffsetSize(DMA_Stream_T *stream, DMA_PERIOSIZE_T perioSize)
 {
     stream->SCFG_B.PERIOSIZE = perioSize;
 }
@@ -245,7 +245,7 @@ void DMA_ConfigPeriphIncOffsetSize(DMA_Stream_T* stream, DMA_PERIOSIZE_T perioSi
  *
  * @note      DMA2 Stream only for APM32 High density devices.
  */
-void DMA_ConfigFlowController(DMA_Stream_T* stream, DMA_FLOWCTRL_T flowController)
+void DMA_ConfigFlowController(DMA_Stream_T *stream, DMA_FLOWCTRL_T flowController)
 {
     stream->SCFG_B.PERFC = flowController;
 }
@@ -261,7 +261,7 @@ void DMA_ConfigFlowController(DMA_Stream_T* stream, DMA_FLOWCTRL_T flowControlle
  *
  * @note      DMA2 Stream only for APM32 High density devices.
  */
-void DMA_ConfigDataNumber(DMA_Stream_T* stream, uint16_t dataNumber)
+void DMA_ConfigDataNumber(DMA_Stream_T *stream, uint16_t dataNumber)
 {
     stream->NDATA = dataNumber;
 }
@@ -275,7 +275,7 @@ void DMA_ConfigDataNumber(DMA_Stream_T* stream, uint16_t dataNumber)
  *
  * @note      DMA2 Stream only for APM32 High density devices.
  */
-uint16_t DMA_ReadDataNumber(DMA_Stream_T* stream)
+uint16_t DMA_ReadDataNumber(DMA_Stream_T *stream)
 {
     return (uint16_t)(stream->NDATA);
 }
@@ -295,7 +295,7 @@ uint16_t DMA_ReadDataNumber(DMA_Stream_T* stream)
  *
  * @retval    None
  */
-void DMA_ConfigBufferMode(DMA_Stream_T* stream, uint32_t memory1BaseAddr, DMA_MEMORY_T currentMemory)
+void DMA_ConfigBufferMode(DMA_Stream_T *stream, uint32_t memory1BaseAddr, DMA_MEMORY_T currentMemory)
 {
     stream->SCFG_B.CTARG = currentMemory;
     stream->M1ADDR = memory1BaseAddr;
@@ -308,7 +308,7 @@ void DMA_ConfigBufferMode(DMA_Stream_T* stream, uint32_t memory1BaseAddr, DMA_ME
  *
  * @retval    None
  */
-void DMA_EnableDoubleBufferMode(DMA_Stream_T* stream)
+void DMA_EnableDoubleBufferMode(DMA_Stream_T *stream)
 {
     stream->SCFG_B.DBM = BIT_SET;
 }
@@ -320,7 +320,7 @@ void DMA_EnableDoubleBufferMode(DMA_Stream_T* stream)
  *
  * @retval    None
  */
-void DMA_DisableDoubleBufferMode(DMA_Stream_T* stream)
+void DMA_DisableDoubleBufferMode(DMA_Stream_T *stream)
 {
     stream->SCFG_B.DBM = BIT_RESET;
 }
@@ -340,7 +340,7 @@ void DMA_DisableDoubleBufferMode(DMA_Stream_T* stream)
  *
  * @retval       None
  */
-void DMA_ConfigMemoryTarget(DMA_Stream_T* stream, uint32_t memoryBaseAddr, DMA_MEMORY_T memoryTarget)
+void DMA_ConfigMemoryTarget(DMA_Stream_T *stream, uint32_t memoryBaseAddr, DMA_MEMORY_T memoryTarget)
 {
     if (memoryTarget != DMA_MEMORY_0)
     {
@@ -359,7 +359,7 @@ void DMA_ConfigMemoryTarget(DMA_Stream_T* stream, uint32_t memoryBaseAddr, DMA_M
  *
  * @retval    The memory target number: 0 for Memory0 or 1 for Memory1.
  */
-uint32_t DMA_ReadCurrentMemoryTarget(DMA_Stream_T* stream)
+uint32_t DMA_ReadCurrentMemoryTarget(DMA_Stream_T *stream)
 {
     return (uint32_t)(stream->SCFG_B.CTARG);
 }
@@ -371,7 +371,7 @@ uint32_t DMA_ReadCurrentMemoryTarget(DMA_Stream_T* stream)
  *
  * @retval     Return state of the DMAy channelx (ENABLE or DISABLE).
  */
-uint8_t DMA_ReadCmdStatus(DMA_Stream_T* stream)
+uint8_t DMA_ReadCmdStatus(DMA_Stream_T *stream)
 {
     return (uint8_t)(stream->SCFG_B.EN);
 }
@@ -389,7 +389,7 @@ uint8_t DMA_ReadCmdStatus(DMA_Stream_T* stream)
  *                  - DMA_FIFOSTATUS_EMPTY: when FIFO is empty
  *                  - DMA_FIFOSTATUS_FULL: when FIFO is full
  */
-uint32_t DMA_ReadFIFOFlag(DMA_Stream_T* stream)
+uint32_t DMA_ReadFIFOFlag(DMA_Stream_T *stream)
 {
     return (uint32_t)(stream->FCTRL_B.FSTS);
 }
@@ -410,9 +410,9 @@ uint32_t DMA_ReadFIFOFlag(DMA_Stream_T* stream)
  *
  * @retval    None
  */
-uint8_t DMA_ReadStatusFlag(DMA_Stream_T* stream, DMA_FLAG_T flag)
+uint8_t DMA_ReadStatusFlag(DMA_Stream_T *stream, DMA_FLAG_T flag)
 {
-    DMA_T* dma;
+    DMA_T *dma;
 
     if (stream < DMA2_Stream0)
     {
@@ -463,9 +463,9 @@ uint8_t DMA_ReadStatusFlag(DMA_Stream_T* stream, DMA_FLAG_T flag)
  *
  * @retval    None
  */
-void DMA_ClearStatusFlag(DMA_Stream_T* stream, uint32_t flag)
+void DMA_ClearStatusFlag(DMA_Stream_T *stream, uint32_t flag)
 {
-    DMA_T* dma;
+    DMA_T *dma;
 
     if (stream < DMA2_Stream0)
     {
@@ -500,7 +500,7 @@ void DMA_ClearStatusFlag(DMA_Stream_T* stream, uint32_t flag)
  *
  * @retval    None
  */
-void DMA_EnableInterrupt(DMA_Stream_T* stream, uint32_t interrupt)
+void DMA_EnableInterrupt(DMA_Stream_T *stream, uint32_t interrupt)
 {
     if ((interrupt & DMA_INT_FEIFLG) == DMA_INT_FEIFLG)
     {
@@ -528,7 +528,7 @@ void DMA_EnableInterrupt(DMA_Stream_T* stream, uint32_t interrupt)
  *
  * @retval    None
  */
-void DMA_DisableInterrupt(DMA_Stream_T* stream, uint32_t interrupt)
+void DMA_DisableInterrupt(DMA_Stream_T *stream, uint32_t interrupt)
 {
     if ((interrupt & DMA_INT_FEIFLG) == DMA_INT_FEIFLG)
     {
@@ -557,10 +557,10 @@ void DMA_DisableInterrupt(DMA_Stream_T* stream, uint32_t interrupt)
  *
  * @retval    None.
  */
-uint8_t DMA_ReadIntFlag(DMA_Stream_T* stream, DMA_INT_FLAG_T flag)
+uint8_t DMA_ReadIntFlag(DMA_Stream_T *stream, DMA_INT_FLAG_T flag)
 {
     uint32_t tmpreg = 0, enablestatus = 0;
-    DMA_T* dma;
+    DMA_T *dma;
 
     if (stream < DMA2_Stream0)
     {
@@ -580,7 +580,7 @@ uint8_t DMA_ReadIntFlag(DMA_Stream_T* stream, DMA_INT_FLAG_T flag)
     else
     {
         /** Get the interrupt enable position mask in SCFG register */
-        tmpreg = ((flag & 0xE000)>> 11) ;
+        tmpreg = ((flag & 0xE000) >> 11) ;
 
         /** Check the enable bit in SCFG register */
         enablestatus = (stream->SCFG & tmpreg);
@@ -624,9 +624,9 @@ uint8_t DMA_ReadIntFlag(DMA_Stream_T* stream, DMA_INT_FLAG_T flag)
  *
  * @retval    None
  */
-void DMA_ClearIntFlag(DMA_Stream_T* stream, uint32_t flag)
+void DMA_ClearIntFlag(DMA_Stream_T *stream, uint32_t flag)
 {
-    DMA_T* dma;
+    DMA_T *dma;
 
     if (stream < DMA2_Stream0)
     {

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_dmc.c

@@ -45,10 +45,10 @@
  *
  * @retval    None
  */
-void DMC_Config(DMC_Config_T* dmcConfig)
+void DMC_Config(DMC_Config_T *dmcConfig)
 {
     DMC->SW_B.MCSW = 1;
-    while(!DMC->CTRL1_B.INIT);
+    while (!DMC->CTRL1_B.INIT);
 
     DMC->CFG_B.BAWCFG = dmcConfig->bankWidth;
     DMC->CFG_B.RAWCFG = dmcConfig->rowWidth;
@@ -59,7 +59,7 @@ void DMC_Config(DMC_Config_T* dmcConfig)
     DMC_ConfigTiming(&dmcConfig->timing);
 
     DMC->CTRL1_B.MODESET = 1;
-    while(!DMC->CTRL1_B.MODESET);
+    while (!DMC->CTRL1_B.MODESET);
 
     DMC->CTRL2_B.RDDEN = 1;
     DMC->CTRL2_B.RDDCFG = 7;
@@ -72,7 +72,7 @@ void DMC_Config(DMC_Config_T* dmcConfig)
  *
  * @retval    None
  */
-void DMC_ConfigStructInit(DMC_Config_T* dmcConfig)
+void DMC_ConfigStructInit(DMC_Config_T *dmcConfig)
 {
     dmcConfig->bankWidth   = DMC_BANK_WIDTH_2;
     dmcConfig->clkPhase    = DMC_CLK_PHASE_REVERSE;
@@ -89,7 +89,7 @@ void DMC_ConfigStructInit(DMC_Config_T* dmcConfig)
  *
  * @retval    None
  */
-void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig)
+void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig)
 {
     DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
     DMC->TIM0_B.DTIMSEL    = timingConfig->tRCD;
@@ -114,7 +114,7 @@ void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig)
  *
  * @retval    None
  */
-void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig)
+void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig)
 {
     timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
     timingConfig->tARP = DMC_AUTO_REFRESH_10;

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_eint.c

@@ -61,12 +61,12 @@ void EINT_Reset(void)
  *
  * @retval    None
  */
-void EINT_Config(EINT_Config_T* eintConfig)
+void EINT_Config(EINT_Config_T *eintConfig)
 {
     uint32_t temp = 0;
     temp = (uint32_t)EINT_BASE;
 
-    if(eintConfig->lineCmd != DISABLE)
+    if (eintConfig->lineCmd != DISABLE)
     {
         EINT->IMASK &= ~eintConfig->line;
         EINT->EMASK &= ~eintConfig->line;
@@ -103,7 +103,7 @@ void EINT_Config(EINT_Config_T* eintConfig)
  *
  * @retval    None
  */
-void EINT_ConfigStructInit(EINT_Config_T* eintConfig)
+void EINT_ConfigStructInit(EINT_Config_T *eintConfig)
 {
     eintConfig->line = EINT_LINENONE;
     eintConfig->mode = EINT_MODE_INTERRUPT;
@@ -184,7 +184,7 @@ uint8_t EINT_ReadStatusFlag(EINT_LINE_T line)
 {
     uint8_t status = RESET;
 
-    if((EINT->IPEND & line) != (uint32_t)RESET)
+    if ((EINT->IPEND & line) != (uint32_t)RESET)
     {
         status = SET;
     }
@@ -271,7 +271,7 @@ uint8_t EINT_ReadIntFlag(EINT_LINE_T line)
 
     enablestatus = EINT->IMASK & line;
 
-    if((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    if ((EINT->IPEND & line) != ((uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
     {
         status = SET;
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_fmc.c

@@ -165,7 +165,7 @@ void FMC_ResetDataCache(void)
  */
 void FMC_Unlock(void)
 {
-  if((FMC->CTRL & FMC_CTRL_LOCK) != RESET)
+    if ((FMC->CTRL & FMC_CTRL_LOCK) != RESET)
     {
         FMC->KEY = FMC_KEY1;
         FMC->KEY = FMC_KEY2;
@@ -318,7 +318,7 @@ FMC_STATUS_T FMC_ProgramDoubleWord(uint32_t address, uint64_t data)
         FMC->CTRL &= 0xFFFFFCFF;
         FMC->CTRL |= FMC_PSIZE_DOUBLE_WORD;
         FMC->CTRL |= FMC_CTRL_PG;
-        *(__IO uint64_t*)address = data;
+        *(__IO uint64_t *)address = data;
         status = FMC_WaitForLastOperation();
         FMC->CTRL &= (~FMC_CTRL_PG);
     }
@@ -349,7 +349,7 @@ FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data)
         FMC->CTRL &= 0xFFFFFCFF;
         FMC->CTRL |= FMC_PSIZE_WORD;
         FMC->CTRL |= FMC_CTRL_PG;
-        *(__IO uint32_t*)address = data;
+        *(__IO uint32_t *)address = data;
         status = FMC_WaitForLastOperation();
         FMC->CTRL &= (~FMC_CTRL_PG);
     }
@@ -379,7 +379,7 @@ FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data)
         FMC->CTRL &= 0xFFFFFCFF;
         FMC->CTRL |= FMC_PSIZE_HALF_WORD;
         FMC->CTRL |= FMC_CTRL_PG;
-        *(__IO uint16_t*)address = data;
+        *(__IO uint16_t *)address = data;
         status = FMC_WaitForLastOperation();
         FMC->CTRL &= (~FMC_CTRL_PG);
     }
@@ -409,7 +409,7 @@ FMC_STATUS_T FMC_ProgramByte(uint32_t address, uint8_t data)
         FMC->CTRL &= 0xFFFFFCFF;
         FMC->CTRL |= FMC_PSIZE_BYTE;
         FMC->CTRL |= FMC_CTRL_PG;
-        *(__IO uint8_t*)address = data;
+        *(__IO uint8_t *)address = data;
         status = FMC_WaitForLastOperation();
         FMC->CTRL &= (~FMC_CTRL_PG);
     }
@@ -463,7 +463,7 @@ void FMC_OPT_EnableWriteProtect(FMC_OPT_WRP_T wrp)
 
     if (status == FMC_COMPLETE)
     {
-        *(__IO uint16_t*)(OPTCTRL_BYTE2_ADDRESS) &= (~(uint16_t)wrp);
+        *(__IO uint16_t *)(OPTCTRL_BYTE2_ADDRESS) &= (~(uint16_t)wrp);
     }
 }
 
@@ -485,7 +485,7 @@ void FMC_OPT_DisableWriteProtect(FMC_OPT_WRP_T wrp)
 
     if (status == FMC_COMPLETE)
     {
-        *(__IO uint16_t*)(OPTCTRL_BYTE2_ADDRESS) |= (uint16_t)wrp;
+        *(__IO uint16_t *)(OPTCTRL_BYTE2_ADDRESS) |= (uint16_t)wrp;
     }
 }
 /*!
@@ -505,7 +505,7 @@ void FMC_OPT_ConfigReadProtect(FMC_OPT_RDP_T rdp)
 
     if (status == FMC_COMPLETE)
     {
-        *(__IO uint8_t*)OPTCTRL_BYTE1_ADDRESS = rdp;
+        *(__IO uint8_t *)OPTCTRL_BYTE1_ADDRESS = rdp;
     }
 }
 
@@ -554,8 +554,8 @@ void FMC_OPT_ConfigUser(FMC_OPT_IWDT_T iwdt, FMC_OPT_STOP_T stop, FMC_OPT_STDBY_
  */
 void FMC_OPT_ConfigBrownoutReset(FMC_OPT_BOR_T bor)
 {
-    *(__IO uint8_t*)(OPTCTRL_BYTE0_ADDRESS) &= (~(FMC_OPTCTRL_BORLVL));
-    *(__IO uint8_t*)(OPTCTRL_BYTE0_ADDRESS) |= bor;
+    *(__IO uint8_t *)(OPTCTRL_BYTE0_ADDRESS) &= (~(FMC_OPTCTRL_BORLVL));
+    *(__IO uint8_t *)(OPTCTRL_BYTE0_ADDRESS) |= bor;
 }
 
 /*!
@@ -570,7 +570,7 @@ FMC_STATUS_T FMC_OPT_Launch(void)
 {
     FMC_STATUS_T status = FMC_COMPLETE;
 
-    *(__IO uint8_t*)(OPTCTRL_BYTE0_ADDRESS) |= (uint32_t)FMC_OPTCTRL_OPTSTART;
+    *(__IO uint8_t *)(OPTCTRL_BYTE0_ADDRESS) |= (uint32_t)FMC_OPTCTRL_OPTSTART;
     status = FMC_WaitForLastOperation();
 
     return status;
@@ -614,7 +614,7 @@ uint8_t FMC_OPT_ReadProtectLevel(void)
 {
     uint8_t tmp = RESET;
 
-    if ((*(__IO uint8_t*)((OPTCTRL_BYTE1_ADDRESS)) != (uint8_t)FMC_OPT_RDP_LV0))
+    if ((*(__IO uint8_t *)((OPTCTRL_BYTE1_ADDRESS)) != (uint8_t)FMC_OPT_RDP_LV0))
     {
         tmp = SET;
     }
@@ -635,7 +635,7 @@ uint8_t FMC_OPT_ReadProtectLevel(void)
  */
 uint8_t FMC_OPT_ReadBrownoutReset(void)
 {
-    return (uint8_t)(*(__IO uint8_t*)((OPTCTRL_BYTE0_ADDRESS)) & FMC_OPT_BOR_OFF);
+    return (uint8_t)(*(__IO uint8_t *)((OPTCTRL_BYTE0_ADDRESS)) & FMC_OPT_BOR_OFF);
 }
 
 /*!

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_gpio.c

@@ -49,53 +49,53 @@
  *
  * @note   By reset, The GPIO pins are configured in input floating mode (except the JTAG pins).
  */
-void GPIO_Reset(GPIO_T* port)
+void GPIO_Reset(GPIO_T *port)
 {
     RCM_AHB1_PERIPH_T AHB1Periph;
 
     if (port == GPIOA)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOA;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOA;
     }
     else if (port == GPIOB)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOB;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOB;
     }
     else if (port == GPIOC)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOC;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOC;
     }
     else if (port == GPIOD)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOD;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOD;
     }
     else if (port == GPIOE)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOE;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOE;
     }
     else if (port == GPIOF)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOF;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOF;
     }
     else if (port == GPIOG)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOG;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOG;
     }
     else if (port == GPIOH)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOH;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOH;
     }
     else if (port == GPIOI)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOI;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOI;
     }
     else if (port == GPIOJ)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOJ;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOJ;
     }
     else if (port == GPIOK)
     {
-        AHB1Periph=RCM_AHB1_PERIPH_GPIOK;
+        AHB1Periph = RCM_AHB1_PERIPH_GPIOK;
     }
 
     RCM_EnableAHB1PeriphReset(AHB1Periph);
@@ -113,7 +113,7 @@ void GPIO_Reset(GPIO_T* port)
  *
  * @retval      None
  */
-void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
+void GPIO_Config(GPIO_T *port, GPIO_Config_T *gpioConfig)
 {
     uint32_t i = 0x00;
     uint32_t pos = 0x00;
@@ -151,7 +151,7 @@ void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig)
  *
  * @retval      None
  */
-void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
+void GPIO_ConfigStructInit(GPIO_Config_T *gpioConfig)
 {
     gpioConfig->pin  = GPIO_PIN_ALL;
     gpioConfig->mode = GPIO_MODE_IN;
@@ -177,7 +177,7 @@ void GPIO_ConfigStructInit(GPIO_Config_T* gpioConfig)
  *               configuration of the locked GPIO pins can no longer be config.
  *
  */
-void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
+void GPIO_ConfigPinLock(GPIO_T *port, uint16_t pin)
 {
     __IOM uint32_t temp = 0x00010000;
 
@@ -204,7 +204,7 @@ void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin)
  *
  * @retval The input port pin value.
  */
-uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
+uint8_t GPIO_ReadInputBit(GPIO_T *port, uint16_t pin)
 {
     uint8_t readBit = 0x00;
 
@@ -222,7 +222,7 @@ uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin)
  *
  * @retval      GPIO input data port value.
  */
-uint16_t GPIO_ReadInputPort(GPIO_T* port)
+uint16_t GPIO_ReadInputPort(GPIO_T *port)
 {
     return ((uint16_t)port->IDATA);
 }
@@ -239,7 +239,7 @@ uint16_t GPIO_ReadInputPort(GPIO_T* port)
  *
  * @retval       The output port pin value.
  */
-uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
+uint8_t GPIO_ReadOutputBit(GPIO_T *port, uint16_t pin)
 {
     uint8_t readBit = 0x00;
 
@@ -257,7 +257,7 @@ uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin)
  *
  * @retval       output data port value
  */
-uint16_t GPIO_ReadOutputPort(GPIO_T* port)
+uint16_t GPIO_ReadOutputPort(GPIO_T *port)
 {
     return ((uint16_t)port->ODATA);
 }
@@ -274,7 +274,7 @@ uint16_t GPIO_ReadOutputPort(GPIO_T* port)
  *
  * @retval       None
  */
-void GPIO_SetBit(GPIO_T* port, uint16_t pin)
+void GPIO_SetBit(GPIO_T *port, uint16_t pin)
 {
     port->BSCL = pin;
 }
@@ -291,7 +291,7 @@ void GPIO_SetBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
+void GPIO_ResetBit(GPIO_T *port, uint16_t pin)
 {
     port->BSCH = pin;
 }
@@ -313,7 +313,7 @@ void GPIO_ResetBit(GPIO_T* port, uint16_t pin)
  *
  * @retval       None
  */
-void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
+void GPIO_WriteBitValue(GPIO_T *port, uint16_t pin, uint8_t bitVal)
 {
     if (bitVal != BIT_RESET)
     {
@@ -336,7 +336,7 @@ void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal)
  *
  * @retval       None
  */
-void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
+void GPIO_WriteOutputPort(GPIO_T *port, uint16_t portValue)
 {
     port->ODATA = (uint16_t)portValue;
 }
@@ -351,7 +351,7 @@ void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue)
  *
  * @retval      None
  */
-void GPIO_ToggleBit(GPIO_T* port, uint16_t pin)
+void GPIO_ToggleBit(GPIO_T *port, uint16_t pin)
 {
     port->ODATA ^= pin;
 }
@@ -416,12 +416,12 @@ void GPIO_ToggleBit(GPIO_T* port, uint16_t pin)
  *
  * @retval    None
  */
-void GPIO_ConfigPinAF(GPIO_T* port, GPIO_PIN_SOURCE_T gpioPinSource, GPIO_AF_T gpioAf)
+void GPIO_ConfigPinAF(GPIO_T *port, GPIO_PIN_SOURCE_T gpioPinSource, GPIO_AF_T gpioAf)
 {
     uint32_t val = 0x00;
     uint32_t val_2 = 0x00;
 
-    if (gpioPinSource >> 0x03==0)
+    if (gpioPinSource >> 0x03 == 0)
     {
         val = (uint32_t)(gpioAf) << (((uint32_t)gpioPinSource & (uint32_t)0x07) * 4);
         port->ALFL &= ~((uint32_t)0xF << (((uint32_t)gpioPinSource & (uint32_t)0x07) * 4)) ;

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_hash.c

@@ -59,7 +59,7 @@ void HASH_Reset(void)
  *
  * @retval    None
  */
-void HASH_Config(HASH_Config_T* hashConfig)
+void HASH_Config(HASH_Config_T *hashConfig)
 {
     /* Configure the Algorithm used, algorithm mode and the datatype */
     HASH->CTRL_B.ALGSEL = RESET;
@@ -79,7 +79,7 @@ void HASH_Config(HASH_Config_T* hashConfig)
 
     /* Reset the HASH processor core, so that the HASH will be ready to compute
      the message digest of a new message */
-    HASH->CTRL_B.INITCAL=SET;
+    HASH->CTRL_B.INITCAL = SET;
 }
 
 /*!
@@ -89,7 +89,7 @@ void HASH_Config(HASH_Config_T* hashConfig)
  *
  * @retval    None
  */
-void HASH_ConfigStructInit(HASH_Config_T* hashConfig)
+void HASH_ConfigStructInit(HASH_Config_T *hashConfig)
 {
     hashConfig->algoSelect = HASH_ALGO_SELECTION_SHA1;
     hashConfig->algoMode = HASH_ALGO_MODE_HASH;
@@ -106,7 +106,7 @@ void HASH_ConfigStructInit(HASH_Config_T* hashConfig)
  */
 void HASH_ResetProceCore(void)
 {
-    HASH->CTRL_B.INITCAL=SET;
+    HASH->CTRL_B.INITCAL = SET;
 }
 
 /*!
@@ -153,7 +153,7 @@ uint8_t HASH_ReadInFIFOWordsNbr(void)
  *
  * @retval    None
  */
-void HASH_ReadDigest(HASH_MessageDigest_T* messageDigest)
+void HASH_ReadDigest(HASH_MessageDigest_T *messageDigest)
 {
     /* Read the data field */
     messageDigest->Data[0] = HASH->DIG[0];
@@ -183,7 +183,7 @@ void HASH_StartDigest(void)
  *
  * @retval    None
  */
-void HASH_ReadContext(HASH_Context_T* contextRead)
+void HASH_ReadContext(HASH_Context_T *contextRead)
 {
     uint8_t i = 0;
 
@@ -205,7 +205,7 @@ void HASH_ReadContext(HASH_Context_T* contextRead)
  *
  * @retval    None
  */
-void HASH_WriteContext(HASH_Context_T* contextWrite)
+void HASH_WriteContext(HASH_Context_T *contextWrite)
 {
     uint8_t i = 0;
 

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_hash_md5.c

@@ -63,7 +63,7 @@
  *            ERROR: digest computation failed
  *
  */
-uint8_t HASH_ComputeMD5(uint8_t* inBuffer, uint32_t lenBuffer,
+uint8_t HASH_ComputeMD5(uint8_t *inBuffer, uint32_t lenBuffer,
                         uint8_t outBuffer[16])
 {
     HASH_Config_T hashMD5Config;
@@ -87,10 +87,10 @@ uint8_t HASH_ComputeMD5(uint8_t* inBuffer, uint32_t lenBuffer,
     HASH_ConfigLastWordValidBitsNbr(nuValidBits);
 
     /* Write the input block in the IN FIFO */
-    for (m=0; m<lenBuffer; m+=4)
+    for (m = 0; m < lenBuffer; m += 4)
     {
-        HASH_WritesInputData(*(uint32_t*)inBufferaddr);
-        inBufferaddr+=4;
+        HASH_WritesInputData(*(uint32_t *)inBufferaddr);
+        inBufferaddr += 4;
     }
 
     /* Start the HASH processor */
@@ -106,16 +106,16 @@ uint8_t HASH_ComputeMD5(uint8_t* inBuffer, uint32_t lenBuffer,
         /* Read the message digest */
         HASH_ReadDigest(&hashMD5MessageDigest);
 
-        *(uint32_t*)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[0]);
+        *(uint32_t *)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[0]);
 
-        outBufferaddr+=4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[1]);
+        outBufferaddr += 4;
+        *(uint32_t *)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[1]);
 
-        outBufferaddr+=4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[2]);
+        outBufferaddr += 4;
+        *(uint32_t *)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[2]);
 
-        outBufferaddr+=4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[3]);
+        outBufferaddr += 4;
+        *(uint32_t *)(outBufferaddr)  = __REV(hashMD5MessageDigest.Data[3]);
     }
 
     return SUCCESS;
@@ -139,7 +139,7 @@ uint8_t HASH_ComputeMD5(uint8_t* inBuffer, uint32_t lenBuffer,
  *            ERROR: digest computation failed
  *
  */
-uint8_t HMAC_ComputeMD5(uint8_t* key, uint32_t keylen, uint8_t* inBuffer,
+uint8_t HMAC_ComputeMD5(uint8_t *key, uint32_t keylen, uint8_t *inBuffer,
                         uint32_t lenBuffer, uint8_t outBuffer[16])
 {
     HASH_Config_T hmacMD5Config;
@@ -173,10 +173,10 @@ uint8_t HMAC_ComputeMD5(uint8_t* key, uint32_t keylen, uint8_t* inBuffer,
     HASH_Config(&hmacMD5Config);
     HASH_ConfigLastWordValidBitsNbr(nuValidKey);
 
-    for (m=0; m<keylen; m+=4)
+    for (m = 0; m < keylen; m += 4)
     {
-        HASH_WritesInputData(*(uint32_t*)keyaddr);
-        keyaddr+=4;
+        HASH_WritesInputData(*(uint32_t *)keyaddr);
+        keyaddr += 4;
     }
 
     /* Start the HASH processor */
@@ -193,10 +193,10 @@ uint8_t HMAC_ComputeMD5(uint8_t* key, uint32_t keylen, uint8_t* inBuffer,
         HASH_ConfigLastWordValidBitsNbr(nuValidBits);
 
         /* Write the input block in the IN FIFO */
-        for (m=0; m<lenBuffer; m+=4)
+        for (m = 0; m < lenBuffer; m += 4)
         {
-            HASH_WritesInputData(*(uint32_t*)inBufferaddr);
-            inBufferaddr+=4;
+            HASH_WritesInputData(*(uint32_t *)inBufferaddr);
+            inBufferaddr += 4;
         }
 
         /* Start the HASH processor */
@@ -212,10 +212,10 @@ uint8_t HMAC_ComputeMD5(uint8_t* key, uint32_t keylen, uint8_t* inBuffer,
             HASH_ConfigLastWordValidBitsNbr(nuValidKey);
             keyaddr = (uint32_t)key;
 
-            for (m=0; m<keylen; m+=4)
+            for (m = 0; m < keylen; m += 4)
             {
-                HASH_WritesInputData(*(uint32_t*)keyaddr);
-                keyaddr+=4;
+                HASH_WritesInputData(*(uint32_t *)keyaddr);
+                keyaddr += 4;
             }
 
             /* Start the HASH processor */
@@ -231,16 +231,16 @@ uint8_t HMAC_ComputeMD5(uint8_t* key, uint32_t keylen, uint8_t* inBuffer,
                 /* Read the message digest */
                 HASH_ReadDigest(&hmacMD5MessageDigest);
 
-                *(uint32_t*)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[0]);
+                *(uint32_t *)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[0]);
 
-                outBufferaddr+=4;
-                *(uint32_t*)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[1]);
+                outBufferaddr += 4;
+                *(uint32_t *)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[1]);
 
-                outBufferaddr+=4;
-                *(uint32_t*)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[2]);
+                outBufferaddr += 4;
+                *(uint32_t *)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[2]);
 
-                outBufferaddr+=4;
-                *(uint32_t*)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[3]);
+                outBufferaddr += 4;
+                *(uint32_t *)(outBufferaddr)  = __REV(hmacMD5MessageDigest.Data[3]);
             }
         }
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_hash_sha1.c

@@ -62,7 +62,7 @@
  *            ERROR: digest computation failed
  *
  */
-uint8_t HASH_ComputeSHA1(uint8_t* inBuffer, uint32_t lenBuffer,
+uint8_t HASH_ComputeSHA1(uint8_t *inBuffer, uint32_t lenBuffer,
                          uint8_t outBuffer[20])
 {
     HASH_Config_T hashSHA1Config;
@@ -72,7 +72,7 @@ uint8_t HASH_ComputeSHA1(uint8_t* inBuffer, uint32_t lenBuffer,
     uint32_t inBufferaddr  = (uint32_t)inBuffer;
     uint32_t outBufferaddr = (uint32_t)outBuffer;
 
-    nBufferBits = (lenBuffer % 4)* 8;
+    nBufferBits = (lenBuffer % 4) * 8;
 
     HASH_Reset();
 
@@ -86,7 +86,7 @@ uint8_t HASH_ComputeSHA1(uint8_t* inBuffer, uint32_t lenBuffer,
     /* Write the input block in the IN FIFO */
     for (m = 0; m < lenBuffer; m += 4)
     {
-        HASH_WritesInputData(*(uint32_t*)inBufferaddr);
+        HASH_WritesInputData(*(uint32_t *)inBufferaddr);
         inBufferaddr += 4;
     }
 
@@ -103,19 +103,19 @@ uint8_t HASH_ComputeSHA1(uint8_t* inBuffer, uint32_t lenBuffer,
         /* Read the message digest */
         HASH_ReadDigest(&hashSHA1MessageDigest);
 
-        *(uint32_t*)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[0]);
+        *(uint32_t *)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[0]);
 
         outBufferaddr += 4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[1]);
+        *(uint32_t *)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[1]);
 
         outBufferaddr += 4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[2]);
+        *(uint32_t *)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[2]);
 
         outBufferaddr += 4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[3]);
+        *(uint32_t *)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[3]);
 
         outBufferaddr += 4;
-        *(uint32_t*)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[4]);
+        *(uint32_t *)(outBufferaddr)  = __REV(hashSHA1MessageDigest.Data[4]);
     }
 
     return SUCCESS;
@@ -139,7 +139,7 @@ uint8_t HASH_ComputeSHA1(uint8_t* inBuffer, uint32_t lenBuffer,
  *            ERROR: digest computation failed
  *
  */
-uint8_t HMAC_ComputeSHA1(uint8_t* key, uint32_t lenkey, uint8_t* inBuffer,
+uint8_t HMAC_ComputeSHA1(uint8_t *key, uint32_t lenkey, uint8_t *inBuffer,
                          uint32_t lenBuffer, uint8_t outBuffer[20])
 {
     HASH_Config_T hmacSHA1Config;
@@ -174,10 +174,10 @@ uint8_t HMAC_ComputeSHA1(uint8_t* key, uint32_t lenkey, uint8_t* inBuffer,
     HASH_ConfigLastWordValidBitsNbr(nuValidKey);
 
     /* Write the key */
-    for (m=0; m<lenkey; m+=4)
+    for (m = 0; m < lenkey; m += 4)
     {
-        HASH_WritesInputData(*(uint32_t*)keyaddr);
-        keyaddr+=4;
+        HASH_WritesInputData(*(uint32_t *)keyaddr);
+        keyaddr += 4;
     }
 
     HASH_StartDigest();
@@ -191,10 +191,10 @@ uint8_t HMAC_ComputeSHA1(uint8_t* key, uint32_t lenkey, uint8_t* inBuffer,
     {
         HASH_ConfigLastWordValidBitsNbr(nBufferBits);
 
-        for (m=0; m<lenkey; m+=4)
+        for (m = 0; m < lenkey; m += 4)
         {
-            HASH_WritesInputData(*(uint32_t*)inputaddr);
-            inputaddr+=4;
+            HASH_WritesInputData(*(uint32_t *)inputaddr);
+            inputaddr += 4;
         }
 
         HASH_StartDigest();
@@ -210,10 +210,10 @@ uint8_t HMAC_ComputeSHA1(uint8_t* key, uint32_t lenkey, uint8_t* inBuffer,
             /* Write the key */
             keyaddr = (uint32_t)key;
 
-            for (m=0; m<lenkey; m+=4)
+            for (m = 0; m < lenkey; m += 4)
             {
-                HASH_WritesInputData(*(uint32_t*)keyaddr);
-                keyaddr+=4;
+                HASH_WritesInputData(*(uint32_t *)keyaddr);
+                keyaddr += 4;
             }
 
             /* Start the HASH processor */
@@ -228,19 +228,19 @@ uint8_t HMAC_ComputeSHA1(uint8_t* key, uint32_t lenkey, uint8_t* inBuffer,
             {
                 /* Read the message digest */
                 HASH_ReadDigest(&hashSHA1MessageDigest);
-                *(uint32_t*)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[0]);
+                *(uint32_t *)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[0]);
 
-                outputaddr+=4;
-                *(uint32_t*)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[1]);
+                outputaddr += 4;
+                *(uint32_t *)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[1]);
 
-                outputaddr+=4;
-                *(uint32_t*)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[2]);
+                outputaddr += 4;
+                *(uint32_t *)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[2]);
 
-                outputaddr+=4;
-                *(uint32_t*)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[3]);
+                outputaddr += 4;
+                *(uint32_t *)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[3]);
 
-                outputaddr+=4;
-                *(uint32_t*)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[4]);
+                outputaddr += 4;
+                *(uint32_t *)(outputaddr)  = __REV(hashSHA1MessageDigest.Data[4]);
             }
         }
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_i2c.c

@@ -46,7 +46,7 @@
  *
  * @retval    None
  */
-void I2C_Reset(I2C_T* i2c)
+void I2C_Reset(I2C_T *i2c)
 {
     if (i2c == I2C1)
     {
@@ -74,7 +74,7 @@ void I2C_Reset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
+void I2C_Config(I2C_T *i2c, I2C_Config_T *i2cConfig)
 {
     uint16_t temp = 0, freq = 0;
     uint32_t PCLK1 = 8000000, PCLK2 = 0;
@@ -140,7 +140,7 @@ void I2C_Config(I2C_T* i2c, I2C_Config_T* i2cConfig)
  *
  * @retval    None
  */
-void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
+void I2C_ConfigStructInit(I2C_Config_T *i2cConfig)
 {
     i2cConfig->clockSpeed = 5000;
     i2cConfig->mode = I2C_MODE_I2C;
@@ -157,7 +157,7 @@ void I2C_ConfigStructInit(I2C_Config_T* i2cConfig)
  *
  * @retval    None
  */
-void I2C_Enable(I2C_T* i2c)
+void I2C_Enable(I2C_T *i2c)
 {
     i2c->CTRL1_B.I2CEN = SET;
 }
@@ -169,7 +169,7 @@ void I2C_Enable(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Disable(I2C_T* i2c)
+void I2C_Disable(I2C_T *i2c)
 {
     i2c->CTRL1_B.I2CEN = RESET;
 }
@@ -181,7 +181,7 @@ void I2C_Disable(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStart(I2C_T* i2c)
+void I2C_EnableGenerateStart(I2C_T *i2c)
 {
     i2c->CTRL1_B.START = SET;
 }
@@ -193,7 +193,7 @@ void I2C_EnableGenerateStart(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStart(I2C_T* i2c)
+void I2C_DisableGenerateStart(I2C_T *i2c)
 {
     i2c->CTRL1_B.START = RESET;
 }
@@ -205,7 +205,7 @@ void I2C_DisableGenerateStart(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGenerateStop(I2C_T* i2c)
+void I2C_EnableGenerateStop(I2C_T *i2c)
 {
     i2c->CTRL1_B.STOP = SET;
 }
@@ -217,7 +217,7 @@ void I2C_EnableGenerateStop(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGenerateStop(I2C_T* i2c)
+void I2C_DisableGenerateStop(I2C_T *i2c)
 {
     i2c->CTRL1_B.STOP = RESET;
 }
@@ -236,9 +236,9 @@ void I2C_DisableGenerateStop(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
+void I2C_Tx7BitAddress(I2C_T *i2c, uint8_t address, I2C_DIRECTION_T direction)
 {
-    if(direction != I2C_DIRECTION_TX)
+    if (direction != I2C_DIRECTION_TX)
     {
         i2c->DATA_B.DATA = address | 0x0001;
     }
@@ -254,7 +254,7 @@ void I2C_Tx7BitAddress(I2C_T* i2c, uint8_t address, I2C_DIRECTION_T direction)
  *
  * @retval    None
  */
-void I2C_EnableAcknowledge(I2C_T* i2c)
+void I2C_EnableAcknowledge(I2C_T *i2c)
 {
     i2c->CTRL1_B.ACKEN = SET;
 }
@@ -266,7 +266,7 @@ void I2C_EnableAcknowledge(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableAcknowledge(I2C_T* i2c)
+void I2C_DisableAcknowledge(I2C_T *i2c)
 {
     i2c->CTRL1_B.ACKEN = RESET;
 }
@@ -280,7 +280,7 @@ void I2C_DisableAcknowledge(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
+void I2C_ConfigOwnAddress2(I2C_T *i2c, uint8_t address)
 {
     i2c->SADDR2_B.ADDR2 = address;
 }
@@ -292,7 +292,7 @@ void I2C_ConfigOwnAddress2(I2C_T* i2c, uint8_t address)
  *
  * @retval    None
  */
-void I2C_EnableDualAddress(I2C_T* i2c)
+void I2C_EnableDualAddress(I2C_T *i2c)
 {
     i2c->SADDR2_B.ADDRNUM = SET;
 }
@@ -304,7 +304,7 @@ void I2C_EnableDualAddress(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDualAddress(I2C_T* i2c)
+void I2C_DisableDualAddress(I2C_T *i2c)
 {
     i2c->SADDR2_B.ADDRNUM = RESET;
 }
@@ -316,7 +316,7 @@ void I2C_DisableDualAddress(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableGeneralCall(I2C_T* i2c)
+void I2C_EnableGeneralCall(I2C_T *i2c)
 {
     i2c->CTRL1_B.SRBEN = SET;
 }
@@ -328,7 +328,7 @@ void I2C_EnableGeneralCall(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableGeneralCall(I2C_T* i2c)
+void I2C_DisableGeneralCall(I2C_T *i2c)
 {
     i2c->CTRL1_B.SRBEN = RESET;
 }
@@ -340,7 +340,7 @@ void I2C_DisableGeneralCall(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableSoftwareReset(I2C_T* i2c)
+void I2C_EnableSoftwareReset(I2C_T *i2c)
 {
     i2c->CTRL1_B.SWRST = SET;
 }
@@ -352,7 +352,7 @@ void I2C_EnableSoftwareReset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableSoftwareReset(I2C_T* i2c)
+void I2C_DisableSoftwareReset(I2C_T *i2c)
 {
     i2c->CTRL1_B.SWRST = RESET;
 }
@@ -364,7 +364,7 @@ void I2C_DisableSoftwareReset(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableStretchClock(I2C_T* i2c)
+void I2C_EnableStretchClock(I2C_T *i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = RESET;
 }
@@ -376,7 +376,7 @@ void I2C_EnableStretchClock(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableStretchClock(I2C_T* i2c)
+void I2C_DisableStretchClock(I2C_T *i2c)
 {
     i2c->CTRL1_B.CLKSTRETCHD = SET;
 }
@@ -392,9 +392,9 @@ void I2C_DisableStretchClock(I2C_T* i2c)
  *              @arg I2C_DUTYCYCLE_2: I2C fast mode Tlow/Thigh = 2
  * @retval    None
  */
-void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
+void I2C_ConfigFastModeDutyCycle(I2C_T *i2c, I2C_DUTYCYCLE_T dutyCycle)
 {
-    if(dutyCycle == I2C_DUTYCYCLE_16_9)
+    if (dutyCycle == I2C_DUTYCYCLE_16_9)
     {
         i2c->CLKCTRL_B.FDUTYCFG = BIT_SET;
     }
@@ -413,9 +413,9 @@ void I2C_ConfigFastModeDutyCycle(I2C_T* i2c, I2C_DUTYCYCLE_T dutyCycle)
  *
  * @retval    None
  */
-void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
+void I2C_ConfigNACKPosition(I2C_T *i2c, I2C_NACK_POSITION_T NACKPosition)
 {
-    if(NACKPosition == I2C_NACK_POSITION_NEXT)
+    if (NACKPosition == I2C_NACK_POSITION_NEXT)
     {
         i2c->CTRL1_B.ACKPOS = BIT_SET;
     }
@@ -437,7 +437,7 @@ void I2C_ConfigNACKPosition(I2C_T* i2c, I2C_NACK_POSITION_T NACKPosition)
  *
  * @retval    None
  */
-void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
+void I2C_ConfigSMBusAlert(I2C_T *i2c, I2C_SMBUSALER_T SMBusState)
 {
     if (SMBusState == I2C_SMBUSALER_LOW)
     {
@@ -456,7 +456,7 @@ void I2C_ConfigSMBusAlert(I2C_T* i2c, I2C_SMBUSALER_T SMBusState)
  *
  * @retval    None
  */
-void I2C_EnableARP(I2C_T* i2c)
+void I2C_EnableARP(I2C_T *i2c)
 {
     i2c->CTRL1_B.ARPEN = SET;
 }
@@ -468,7 +468,7 @@ void I2C_EnableARP(I2C_T* i2c)
 *
 * @retval     None
 */
-void I2C_DisableARP(I2C_T* i2c)
+void I2C_DisableARP(I2C_T *i2c)
 {
     i2c->CTRL1_B.ARPEN = RESET;
 }
@@ -482,7 +482,7 @@ void I2C_DisableARP(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_TxData(I2C_T* i2c, uint8_t data)
+void I2C_TxData(I2C_T *i2c, uint8_t data)
 {
     i2c->DATA_B.DATA = data;
 }
@@ -494,7 +494,7 @@ void I2C_TxData(I2C_T* i2c, uint8_t data)
  *
  * @retval    received data
  */
-uint8_t I2C_RxData(I2C_T* i2c)
+uint8_t I2C_RxData(I2C_T *i2c)
 {
     return i2c->DATA_B.DATA;
 }
@@ -506,7 +506,7 @@ uint8_t I2C_RxData(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnablePECTransmit(I2C_T* i2c)
+void I2C_EnablePECTransmit(I2C_T *i2c)
 {
     i2c->CTRL1_B.PEC = SET;
 }
@@ -518,7 +518,7 @@ void I2C_EnablePECTransmit(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisablePECTransmit(I2C_T* i2c)
+void I2C_DisablePECTransmit(I2C_T *i2c)
 {
     i2c->CTRL1_B.PEC = RESET;
 }
@@ -535,9 +535,9 @@ void I2C_DisablePECTransmit(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
+void I2C_ConfigPECPosition(I2C_T *i2c, I2C_PEC_POSITION_T PECPosition)
 {
-    if(PECPosition == I2C_PEC_POSITION_NEXT)
+    if (PECPosition == I2C_PEC_POSITION_NEXT)
     {
         i2c->CTRL1_B.ACKPOS = SET;
     }
@@ -554,7 +554,7 @@ void I2C_ConfigPECPosition(I2C_T* i2c, I2C_PEC_POSITION_T PECPosition)
  *
  * @retval    None
  */
-void I2C_EnablePEC(I2C_T* i2c)
+void I2C_EnablePEC(I2C_T *i2c)
 {
     i2c->CTRL1_B.PECEN = SET;
 }
@@ -566,7 +566,7 @@ void I2C_EnablePEC(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisablePEC(I2C_T* i2c)
+void I2C_DisablePEC(I2C_T *i2c)
 {
     i2c->CTRL1_B.PECEN = RESET;
 }
@@ -578,7 +578,7 @@ void I2C_DisablePEC(I2C_T* i2c)
  *
  * @retval    value of PEC
  */
-uint8_t I2C_ReadPEC(I2C_T* i2c)
+uint8_t I2C_ReadPEC(I2C_T *i2c)
 {
     return i2c->STS2_B.PECVALUE;
 }
@@ -590,7 +590,7 @@ uint8_t I2C_ReadPEC(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableDMA(I2C_T* i2c)
+void I2C_EnableDMA(I2C_T *i2c)
 {
     i2c->CTRL2_B.DMAEN = SET;
 }
@@ -602,7 +602,7 @@ void I2C_EnableDMA(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMA(I2C_T* i2c)
+void I2C_DisableDMA(I2C_T *i2c)
 {
     i2c->CTRL2_B.DMAEN = RESET;
 }
@@ -614,7 +614,7 @@ void I2C_DisableDMA(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_EnableDMALastTransfer(I2C_T* i2c)
+void I2C_EnableDMALastTransfer(I2C_T *i2c)
 {
     i2c->CTRL2_B.LTCFG = SET;
 }
@@ -626,7 +626,7 @@ void I2C_EnableDMALastTransfer(I2C_T* i2c)
  *
  * @retval    None
  */
-void I2C_DisableDMALastTransfer(I2C_T* i2c)
+void I2C_DisableDMALastTransfer(I2C_T *i2c)
 {
     i2c->CTRL2_B.LTCFG = RESET;
 }
@@ -650,39 +650,39 @@ void I2C_DisableDMALastTransfer(I2C_T* i2c)
  *
  * @retval    The value of the read register
  */
-uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
+uint16_t I2C_ReadRegister(I2C_T *i2c, I2C_REGISTER_T i2cRegister)
 {
     switch (i2cRegister)
     {
-        case I2C_REGISTER_CTRL1:
-            return i2c->CTRL1;
+    case I2C_REGISTER_CTRL1:
+        return i2c->CTRL1;
 
-        case I2C_REGISTER_CTRL2:
-            return i2c->CTRL2;
+    case I2C_REGISTER_CTRL2:
+        return i2c->CTRL2;
 
-        case I2C_REGISTER_SADDR1:
-            return i2c->SADDR1;
+    case I2C_REGISTER_SADDR1:
+        return i2c->SADDR1;
 
-        case I2C_REGISTER_SADDR2:
-            return i2c->SADDR2;
+    case I2C_REGISTER_SADDR2:
+        return i2c->SADDR2;
 
-        case I2C_REGISTER_DATA:
-            return i2c->DATA;
+    case I2C_REGISTER_DATA:
+        return i2c->DATA;
 
-        case I2C_REGISTER_STS1:
-            return i2c->STS1;
+    case I2C_REGISTER_STS1:
+        return i2c->STS1;
 
-        case I2C_REGISTER_STS2:
-            return i2c->STS2;
+    case I2C_REGISTER_STS2:
+        return i2c->STS2;
 
-        case I2C_REGISTER_CLKCTRL:
-            return i2c->CLKCTRL;
+    case I2C_REGISTER_CLKCTRL:
+        return i2c->CLKCTRL;
 
-        case I2C_REGISTER_RISETMAX:
-            return i2c->RISETMAX;
+    case I2C_REGISTER_RISETMAX:
+        return i2c->RISETMAX;
 
-        default:
-            return 0;
+    default:
+        return 0;
     }
 }
 
@@ -699,7 +699,7 @@ uint16_t I2C_ReadRegister(I2C_T* i2c, I2C_REGISTER_T i2cRegister)
  *
  * @retval    None
  */
-void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
+void I2C_EnableInterrupt(I2C_T *i2c, uint16_t interrupt)
 {
     i2c->CTRL2 |= interrupt;
 }
@@ -717,7 +717,7 @@ void I2C_EnableInterrupt(I2C_T* i2c, uint16_t interrupt)
  *
  * @retval    None
  */
-void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
+void I2C_DisableInterrupt(I2C_T *i2c, uint16_t interrupt)
 {
     i2c->CTRL2 &= ~interrupt;
 }
@@ -752,7 +752,7 @@ void I2C_DisableInterrupt(I2C_T* i2c, uint16_t interrupt)
  *
  * @retval    Status: SUCCESS or ERROR
  */
-uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
+uint8_t  I2C_ReadEventStatus(I2C_T *i2c, I2C_EVENT_T i2cEvent)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -763,7 +763,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
 
     lastevent = (flag1 | flag2) & 0x00FFFFFF;
 
-    if((lastevent & i2cEvent) == i2cEvent)
+    if ((lastevent & i2cEvent) == i2cEvent)
     {
         return SUCCESS;
     }
@@ -778,7 +778,7 @@ uint8_t  I2C_ReadEventStatus(I2C_T* i2c, I2C_EVENT_T i2cEvent)
  *
  * @retval    The last event
  */
-uint32_t I2C_ReadLastEvent(I2C_T* i2c)
+uint32_t I2C_ReadLastEvent(I2C_T *i2c)
 {
     uint32_t lastevent = 0;
     uint32_t flag1 = 0, flag2 = 0;
@@ -823,98 +823,98 @@ uint32_t I2C_ReadLastEvent(I2C_T* i2c)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
+uint8_t I2C_ReadStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
 {
 
     uint8_t status = 0;
     switch (flag)
     {
-        case I2C_FLAG_DUALADDR:
-            status = i2c->STS2_B.DUALADDRFLG;
-            break;
+    case I2C_FLAG_DUALADDR:
+        status = i2c->STS2_B.DUALADDRFLG;
+        break;
 
-        case I2C_FLAG_SMMHADDR:
-            status = i2c->STS2_B.SMMHADDR;
-            break;
+    case I2C_FLAG_SMMHADDR:
+        status = i2c->STS2_B.SMMHADDR;
+        break;
 
-        case I2C_FLAG_SMBDADDR:
-            status = i2c->STS2_B.SMBDADDRFLG;
-            break;
+    case I2C_FLAG_SMBDADDR:
+        status = i2c->STS2_B.SMBDADDRFLG;
+        break;
 
-        case I2C_FLAG_GENCALL:
-            status = i2c->STS2_B.GENCALLFLG;
-            break;
+    case I2C_FLAG_GENCALL:
+        status = i2c->STS2_B.GENCALLFLG;
+        break;
 
-        case I2C_FLAG_TR:
-            status = i2c->STS2_B.TRFLG;
-            break;
+    case I2C_FLAG_TR:
+        status = i2c->STS2_B.TRFLG;
+        break;
 
-        case I2C_FLAG_BUSBSY:
-            status = i2c->STS2_B.BUSBSYFLG;
-            break;
+    case I2C_FLAG_BUSBSY:
+        status = i2c->STS2_B.BUSBSYFLG;
+        break;
 
-        case I2C_FLAG_MS:
-            status = i2c->STS2_B.MSFLG;
-            break;
+    case I2C_FLAG_MS:
+        status = i2c->STS2_B.MSFLG;
+        break;
 
-        case I2C_FLAG_SMBALT:
-            status = i2c->STS1_B.SMBALTFLG;
-            break;
+    case I2C_FLAG_SMBALT:
+        status = i2c->STS1_B.SMBALTFLG;
+        break;
 
-        case I2C_FLAG_TTE:
-            status = i2c->STS1_B.TTEFLG;
-            break;
+    case I2C_FLAG_TTE:
+        status = i2c->STS1_B.TTEFLG;
+        break;
 
-        case I2C_FLAG_PECE:
-            status = i2c->STS1_B.PECEFLG;
-            break;
+    case I2C_FLAG_PECE:
+        status = i2c->STS1_B.PECEFLG;
+        break;
 
-        case  I2C_FLAG_OVRUR:
-            status = i2c->STS1_B.OVRURFLG;
-            break;
+    case  I2C_FLAG_OVRUR:
+        status = i2c->STS1_B.OVRURFLG;
+        break;
 
-        case I2C_FLAG_AE:
-            status = i2c->STS1_B.AEFLG;
-            break;
+    case I2C_FLAG_AE:
+        status = i2c->STS1_B.AEFLG;
+        break;
 
-        case I2C_FLAG_AL:
-            status = i2c->STS1_B.ALFLG;
-            break;
+    case I2C_FLAG_AL:
+        status = i2c->STS1_B.ALFLG;
+        break;
 
-        case I2C_FLAG_BERR:
-            status = i2c->STS1_B.BERRFLG;
-            break;
+    case I2C_FLAG_BERR:
+        status = i2c->STS1_B.BERRFLG;
+        break;
 
-        case I2C_FLAG_TXBE:
-            status = i2c->STS1_B.TXBEFLG;
-            break;
+    case I2C_FLAG_TXBE:
+        status = i2c->STS1_B.TXBEFLG;
+        break;
 
-        case I2C_FLAG_RXBNE:
-            status = i2c->STS1_B.RXBNEFLG;
-            break;
+    case I2C_FLAG_RXBNE:
+        status = i2c->STS1_B.RXBNEFLG;
+        break;
 
-        case I2C_FLAG_STOP:
-            status = i2c->STS1_B.STOPFLG;
-            break;
+    case I2C_FLAG_STOP:
+        status = i2c->STS1_B.STOPFLG;
+        break;
 
-        case I2C_FLAG_ADDR10:
-            status = i2c->STS1_B.ADDR10FLG;
-            break;
+    case I2C_FLAG_ADDR10:
+        status = i2c->STS1_B.ADDR10FLG;
+        break;
 
-        case I2C_FLAG_BTC:
-            status = i2c->STS1_B.BTCFLG;
-            break;
+    case I2C_FLAG_BTC:
+        status = i2c->STS1_B.BTCFLG;
+        break;
 
-        case I2C_FLAG_ADDR:
-            status = i2c->STS1_B.ADDRFLG;
-            break;
+    case I2C_FLAG_ADDR:
+        status = i2c->STS1_B.ADDRFLG;
+        break;
 
-        case I2C_FLAG_START:
-            status = i2c->STS1_B.STARTFLG;
-            break;
+    case I2C_FLAG_START:
+        status = i2c->STS1_B.STARTFLG;
+        break;
 
-        default:
-            break;
+    default:
+        break;
     }
     return status;
 }
@@ -952,40 +952,40 @@ uint8_t I2C_ReadStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadStatusFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
+void I2C_ClearStatusFlag(I2C_T *i2c, I2C_FLAG_T flag)
 {
     switch (flag)
     {
-        case I2C_FLAG_SMBALT:
-            i2c->STS1_B.SMBALTFLG = BIT_RESET;
-            break;
+    case I2C_FLAG_SMBALT:
+        i2c->STS1_B.SMBALTFLG = BIT_RESET;
+        break;
 
-        case I2C_FLAG_TTE:
-            i2c->STS1_B.TTEFLG = BIT_RESET;
-            break;
+    case I2C_FLAG_TTE:
+        i2c->STS1_B.TTEFLG = BIT_RESET;
+        break;
 
-        case I2C_FLAG_PECE:
-            i2c->STS1_B.PECEFLG = BIT_RESET;
-            break;
+    case I2C_FLAG_PECE:
+        i2c->STS1_B.PECEFLG = BIT_RESET;
+        break;
 
-        case  I2C_FLAG_OVRUR:
-            i2c->STS1_B.OVRURFLG = BIT_RESET;
-            break;
+    case  I2C_FLAG_OVRUR:
+        i2c->STS1_B.OVRURFLG = BIT_RESET;
+        break;
 
-        case I2C_FLAG_AE:
-            i2c->STS1_B.AEFLG = BIT_RESET;
-            break;
+    case I2C_FLAG_AE:
+        i2c->STS1_B.AEFLG = BIT_RESET;
+        break;
 
-        case I2C_FLAG_AL:
-            i2c->STS1_B.ALFLG = BIT_RESET;
-            break;
+    case I2C_FLAG_AL:
+        i2c->STS1_B.ALFLG = BIT_RESET;
+        break;
 
-        case I2C_FLAG_BERR:
-            i2c->STS1_B.BERRFLG = BIT_RESET;
-            break;
+    case I2C_FLAG_BERR:
+        i2c->STS1_B.BERRFLG = BIT_RESET;
+        break;
 
-        default:
-            break;
+    default:
+        break;
     }
 }
 
@@ -1013,13 +1013,13 @@ void I2C_ClearStatusFlag(I2C_T* i2c, I2C_FLAG_T flag)
  *
  * @retval    Status: flag SET or RESET
  */
-uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
+uint8_t I2C_ReadIntFlag(I2C_T *i2c, I2C_INT_FLAG_T flag)
 {
     uint32_t enablestatus = 0;
 
     enablestatus = ((flag & 0x07000000) >> 16) & (i2c->CTRL2);
     flag &= 0x00FFFFFF;
-    if(((i2c->STS1 & flag) != RESET) && enablestatus)
+    if (((i2c->STS1 & flag) != RESET) && enablestatus)
     {
         return SET;
     }
@@ -1060,7 +1060,7 @@ uint8_t I2C_ReadIntFlag(I2C_T* i2c, I2C_INT_FLAG_T flag)
  *              a read operation to I2C_STS1 register (I2C_ReadIntFlag())
  *              followed by a write operation to I2C_DATA register (I2C_TxData()).
  */
-void I2C_ClearIntFlag(I2C_T* i2c, uint32_t flag)
+void I2C_ClearIntFlag(I2C_T *i2c, uint32_t flag)
 {
     i2c->STS1 = (uint16_t)~(flag & 0x00FFFFFF);
 }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_iwdt.c

@@ -134,7 +134,7 @@ uint8_t IWDT_ReadStatusFlag(uint16_t flag)
 {
     uint8_t bitStatus = RESET;
 
-    if((IWDT->STS & flag) != (uint32_t)RESET)
+    if ((IWDT->STS & flag) != (uint32_t)RESET)
     {
         bitStatus = SET;
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_misc.c

@@ -67,7 +67,7 @@
  */
 void NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_T priorityGroup)
 {
-   SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | priorityGroup;
 }
 
 /*!
@@ -91,38 +91,38 @@ void NVIC_EnableIRQRequest(IRQn_Type irq, uint8_t preemptionPriority, uint8_t su
     priorityGrp = (SCB->AIRCR) & (uint32_t)0x700U;
 
     /** get pre-emption priority and subpriority */
-    switch(priorityGrp)
+    switch (priorityGrp)
     {
-        case NVIC_PRIORITY_GROUP_0:
-            tempPrePri = 0;
-            tempSubPri = 4;
-            break;
-
-        case NVIC_PRIORITY_GROUP_1:
-            tempPrePri = 1;
-            tempSubPri = 3;
-            break;
-
-        case NVIC_PRIORITY_GROUP_2:
-            tempPrePri = 2;
-            tempSubPri = 2;
-            break;
-
-        case NVIC_PRIORITY_GROUP_3:
-            tempPrePri = 3;
-            tempSubPri = 1;
-            break;
-
-        case NVIC_PRIORITY_GROUP_4:
-            tempPrePri = 4;
-            tempSubPri = 0;
-            break;
-
-        default:
-            NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
-            tempPrePri = 0;
-            tempSubPri = 4;
-            break;
+    case NVIC_PRIORITY_GROUP_0:
+        tempPrePri = 0;
+        tempSubPri = 4;
+        break;
+
+    case NVIC_PRIORITY_GROUP_1:
+        tempPrePri = 1;
+        tempSubPri = 3;
+        break;
+
+    case NVIC_PRIORITY_GROUP_2:
+        tempPrePri = 2;
+        tempSubPri = 2;
+        break;
+
+    case NVIC_PRIORITY_GROUP_3:
+        tempPrePri = 3;
+        tempSubPri = 1;
+        break;
+
+    case NVIC_PRIORITY_GROUP_4:
+        tempPrePri = 4;
+        tempSubPri = 0;
+        break;
+
+    default:
+        NVIC_ConfigPriorityGroup(NVIC_PRIORITY_GROUP_0);
+        tempPrePri = 0;
+        tempSubPri = 4;
+        break;
     }
 
     tempPrePri = 4 - tempPrePri;

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_pmu.c

@@ -232,9 +232,9 @@ void PMU_EnterSTOPMode(PMU_REGULATOR_T regulator, PMU_STOP_ENTRY_T entry)
     /* Set LPDSCFG bit according to regulator value */
     PMU->CTRL_B.LPDSCFG = regulator;
     /* Set Cortex System Control Register */
-    SCB->SCR |= (uint32_t )0x04;
+    SCB->SCR |= (uint32_t)0x04;
     /* Select STOP mode entry*/
-    if(entry == PMU_STOP_ENTRY_WFI)
+    if (entry == PMU_STOP_ENTRY_WFI)
     {
         /* Request Wait For Interrupt */
         __WFI();
@@ -261,10 +261,10 @@ void PMU_EnterSTANDBYMode(void)
     /* Select STANDBY mode */
     PMU->CTRL_B.PDDSCFG = BIT_SET;
     /* Set SLEEPDEEP bit of Cortex System Control Register */
-    SCB->SCR |= (uint32_t )0x04;
-    #if defined ( __CC_ARM   )
+    SCB->SCR |= (uint32_t)0x04;
+#if defined ( __CC_ARM   )
     __force_stores();
-    #endif
+#endif
     /* Request Wait For Interrupt */
     __WFI();
 

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_rcm.c

@@ -240,7 +240,7 @@ void RCM_DisableLSI(void)
  * @retval    None
  */
 void RCM_ConfigPLL1(uint32_t pllSelect, uint32_t inputDiv, uint32_t vcoMul,
-                   RCM_PLL_SYS_DIV_T sysDiv, uint32_t appDiv)
+                    RCM_PLL_SYS_DIV_T sysDiv, uint32_t appDiv)
 {
     RCM->PLL1CFG_B.PLL1CLKS = pllSelect;
     RCM->PLL1CFG_B.PLLB = inputDiv;
@@ -510,39 +510,39 @@ uint32_t RCM_ReadSYSCLKFreq(void)
 
     switch (sysClock)
     {
-        /* sys clock is HSI */
-        case RCM_SYSCLK_SEL_HSI:
-            sysClock = HSI_VALUE;
-            break;
-
-        /* sys clock is HSE */
-        case RCM_SYSCLK_SEL_HSE:
-            sysClock = HSE_VALUE;
-            break;
-
-        /* sys clock is PLL */
-        case RCM_SYSCLK_SEL_PLL:
-            pllMull = RCM->PLL1CFG_B.PLLB;
-            pllSource = RCM->PLL1CFG_B.PLL1CLKS;
-
-            /* PLL entry clock source is HSE */
-            if (pllSource == BIT_SET)
-            {
-                /* HSE used as PLL clock source */
-                pllvco = (HSE_VALUE / pllMull) * (RCM->PLL1CFG_B.PLL1A);
-            }
-            else
-            {
-                /* HSI used as PLL clock source */
-                pllvco = (HSI_VALUE / pllMull) * (RCM->PLL1CFG_B.PLL1A);
-            }
-
-            sysClock = pllvco/((RCM->PLL1CFG_B.PLL1C + 1) *2);
-            break;
-
-        default:
-            sysClock  = HSI_VALUE;
-            break;
+    /* sys clock is HSI */
+    case RCM_SYSCLK_SEL_HSI:
+        sysClock = HSI_VALUE;
+        break;
+
+    /* sys clock is HSE */
+    case RCM_SYSCLK_SEL_HSE:
+        sysClock = HSE_VALUE;
+        break;
+
+    /* sys clock is PLL */
+    case RCM_SYSCLK_SEL_PLL:
+        pllMull = RCM->PLL1CFG_B.PLLB;
+        pllSource = RCM->PLL1CFG_B.PLL1CLKS;
+
+        /* PLL entry clock source is HSE */
+        if (pllSource == BIT_SET)
+        {
+            /* HSE used as PLL clock source */
+            pllvco = (HSE_VALUE / pllMull) * (RCM->PLL1CFG_B.PLL1A);
+        }
+        else
+        {
+            /* HSI used as PLL clock source */
+            pllvco = (HSI_VALUE / pllMull) * (RCM->PLL1CFG_B.PLL1A);
+        }
+
+        sysClock = pllvco / ((RCM->PLL1CFG_B.PLL1C + 1) * 2);
+        break;
+
+    default:
+        sysClock  = HSI_VALUE;
+        break;
     }
 
     return sysClock;
@@ -577,7 +577,7 @@ uint32_t RCM_ReadHCLKFreq(void)
  *
  * @retval    None
  */
-void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2)
+void RCM_ReadPCLKFreq(uint32_t *PCLK1, uint32_t *PCLK2)
 {
     uint32_t hclk, divider;
     uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
@@ -1487,20 +1487,20 @@ uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag)
 
     switch (reg)
     {
-        case 0:
-            reg = RCM->CTRL;
-            break;
+    case 0:
+        reg = RCM->CTRL;
+        break;
 
-        case 1:
-            reg = RCM->BDCTRL;
-            break;
+    case 1:
+        reg = RCM->BDCTRL;
+        break;
 
-        case 2:
-            reg = RCM->CSTS;
-            break;
+    case 2:
+        reg = RCM->CSTS;
+        break;
 
-        default:
-            break;
+    default:
+        break;
     }
 
     if (reg & bit)
@@ -1544,7 +1544,7 @@ void RCM_ClearStatusFlag(void)
  */
 uint8_t RCM_ReadIntFlag(RCM_INT_T flag)
 {
-    return (RCM->INT& flag) ? SET : RESET;
+    return (RCM->INT &flag) ? SET : RESET;
 }
 
 /*!

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_rtc.c

@@ -136,7 +136,7 @@ uint8_t RTC_Reset(void)
  *
  * @retval    SUCCESS or ERROR
  */
-uint8_t RTC_Config(RTC_Config_T* rtcConfig)
+uint8_t RTC_Config(RTC_Config_T *rtcConfig)
 {
     RTC_DisableWriteProtection();
 
@@ -166,7 +166,7 @@ uint8_t RTC_Config(RTC_Config_T* rtcConfig)
  *
  * @retval    None
  */
-void RTC_ConfigStructInit(RTC_Config_T* rtcConfig)
+void RTC_ConfigStructInit(RTC_Config_T *rtcConfig)
 {
     rtcConfig->format = RTC_HOURFORMAT_24;
     rtcConfig->asynchPrediv = (uint32_t)0x7F;
@@ -376,7 +376,7 @@ void RTC_DisableBypassShadow(void)
  *
  * @retval    SUCCESS or ERROR
  */
-uint8_t RTC_ConfigTime(RTC_FORMAT_T format, RTC_TimeConfig_T* timeConfig)
+uint8_t RTC_ConfigTime(RTC_FORMAT_T format, RTC_TimeConfig_T *timeConfig)
 {
     uint8_t state = ERROR;
     uint32_t temp = 0;
@@ -391,14 +391,14 @@ uint8_t RTC_ConfigTime(RTC_FORMAT_T format, RTC_TimeConfig_T* timeConfig)
     {
         temp = (((uint32_t)(timeConfig->hours) << 16) | \
                 ((uint32_t)(timeConfig->minutes) << 8) | \
-                ((uint32_t)(timeConfig->seconds))| \
+                ((uint32_t)(timeConfig->seconds)) | \
                 ((uint32_t)(timeConfig->h12) << 22));
     }
     else
     {
         temp = (uint32_t)(((uint32_t)RTC_ByteConBcd2(timeConfig->hours) << 16) | \
                           ((uint32_t)RTC_ByteConBcd2(timeConfig->minutes) << 8) | \
-                          ((uint32_t)RTC_ByteConBcd2(timeConfig->seconds))| \
+                          ((uint32_t)RTC_ByteConBcd2(timeConfig->seconds)) | \
                           (((uint32_t)(timeConfig->h12) << 22)));
     }
 
@@ -444,7 +444,7 @@ uint8_t RTC_ConfigTime(RTC_FORMAT_T format, RTC_TimeConfig_T* timeConfig)
  *
  * @retval    None
  */
-void RTC_ConfigTimeStructInit(RTC_TimeConfig_T* timeConfig)
+void RTC_ConfigTimeStructInit(RTC_TimeConfig_T *timeConfig)
 {
     timeConfig->hours = 0;
     timeConfig->minutes = 0;
@@ -465,7 +465,7 @@ void RTC_ConfigTimeStructInit(RTC_TimeConfig_T* timeConfig)
  *
  * @retval    None
  */
-void RTC_ReadTime(RTC_FORMAT_T format, RTC_TimeConfig_T* time)
+void RTC_ReadTime(RTC_FORMAT_T format, RTC_TimeConfig_T *time)
 {
     uint32_t temp = 0;
 
@@ -473,7 +473,7 @@ void RTC_ReadTime(RTC_FORMAT_T format, RTC_TimeConfig_T* time)
 
     time->h12 = (RTC_H12_T)((temp & 0x00400000) >> 22);
     time->hours   = (uint8_t)((temp & 0x003F0000) >> 16);
-    time->minutes = (uint8_t)((temp & 0x00007F00) >>8);
+    time->minutes = (uint8_t)((temp & 0x00007F00) >> 8);
     time->seconds = (uint8_t)(temp & 0x0000007F);
 
     if (format == RTC_FORMAT_BIN)
@@ -496,7 +496,7 @@ uint32_t RTC_ReadSubSecond(void)
     uint32_t temp = 0;
 
     temp = (uint32_t)(RTC->SUBSEC);
-    (void) (RTC->DATE);
+    (void)(RTC->DATE);
 
     return temp;
 }
@@ -514,7 +514,7 @@ uint32_t RTC_ReadSubSecond(void)
  *
  * @retval    None
  */
-uint8_t RTC_ConfigDate(RTC_FORMAT_T format, RTC_DateConfig_T* dateConfig)
+uint8_t RTC_ConfigDate(RTC_FORMAT_T format, RTC_DateConfig_T *dateConfig)
 {
     uint8_t state = ERROR;
     uint32_t temp = 0;
@@ -528,14 +528,14 @@ uint8_t RTC_ConfigDate(RTC_FORMAT_T format, RTC_DateConfig_T* dateConfig)
     {
         temp = (((uint32_t)(dateConfig->year) << 16) | \
                 ((uint32_t)(dateConfig->month) << 8) | \
-                ((uint32_t)(dateConfig->date))| \
+                ((uint32_t)(dateConfig->date)) | \
                 ((uint32_t)(dateConfig->weekday) << 13));
     }
     else
     {
         temp = (((uint32_t)RTC_ByteConBcd2(dateConfig->year) << 16) | \
                 ((uint32_t)RTC_ByteConBcd2(dateConfig->month) << 8) | \
-                ((uint32_t)RTC_ByteConBcd2(dateConfig->date))| \
+                ((uint32_t)RTC_ByteConBcd2(dateConfig->date)) | \
                 ((uint32_t)(dateConfig->weekday) << 13));
     }
 
@@ -579,7 +579,7 @@ uint8_t RTC_ConfigDate(RTC_FORMAT_T format, RTC_DateConfig_T* dateConfig)
  *
  * @retval    None
  */
-void RTC_ConfigDateStructInit(RTC_DateConfig_T* dateConfig)
+void RTC_ConfigDateStructInit(RTC_DateConfig_T *dateConfig)
 {
     dateConfig->weekday = RTC_WEEKDAY_MONDAY;
     dateConfig->month = RTC_MONTH_JANUARY;
@@ -600,15 +600,15 @@ void RTC_ConfigDateStructInit(RTC_DateConfig_T* dateConfig)
  *
  * @retval    None
  */
-void RTC_ReadDate(RTC_FORMAT_T format, RTC_DateConfig_T* date)
+void RTC_ReadDate(RTC_FORMAT_T format, RTC_DateConfig_T *date)
 {
     uint32_t temp = 0;
     temp = (uint32_t)((RTC->DATE) & 0x00FFFF3F);
 
     date->year  = (uint8_t)((temp & 0x00FF0000) >> 16);
-    date->month = (RTC_MONTH_T)((temp & 0x00001F00) >>8);
+    date->month = (RTC_MONTH_T)((temp & 0x00001F00) >> 8);
     date->date  = (uint8_t)(temp &  0x0000003F);
-    date->weekday =(RTC_WEEKDAY_T)((temp & 0x0000E000) >> 13);
+    date->weekday = (RTC_WEEKDAY_T)((temp & 0x0000E000) >> 13);
 
     if (format == RTC_FORMAT_BIN)
     {
@@ -637,7 +637,7 @@ void RTC_ReadDate(RTC_FORMAT_T format, RTC_DateConfig_T* date)
  *
  * @retva    None
  */
-void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T* alarmConfig)
+void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T *alarmConfig)
 {
     uint32_t temp = 0;
 
@@ -650,7 +650,7 @@ void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T*
     {
         temp = (((uint32_t)(alarmConfig->time.hours) << 16) | \
                 ((uint32_t)(alarmConfig->time.minutes) << 8) | \
-                ((uint32_t)alarmConfig->time.seconds)| \
+                ((uint32_t)alarmConfig->time.seconds) | \
                 ((uint32_t)(alarmConfig->time.h12) << 22) | \
                 ((uint32_t)(alarmConfig->alarmDateWeekDay) << 24) | \
                 ((uint32_t)alarmConfig->alarmDateWeekDaySel << 30) | \
@@ -660,7 +660,7 @@ void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T*
     {
         temp = (((uint32_t)RTC_ByteConBcd2(alarmConfig->time.hours) << 16) | \
                 ((uint32_t)RTC_ByteConBcd2(alarmConfig->time.minutes) << 8) | \
-                ((uint32_t)RTC_ByteConBcd2(alarmConfig->time.seconds))| \
+                ((uint32_t)RTC_ByteConBcd2(alarmConfig->time.seconds)) | \
                 ((uint32_t)(alarmConfig->time.h12) << 22) | \
                 ((uint32_t)RTC_ByteConBcd2(alarmConfig->alarmDateWeekDay) << 24) | \
                 ((uint32_t)alarmConfig->alarmDateWeekDaySel << 30) | \
@@ -689,7 +689,7 @@ void RTC_ConfigAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T*
  *
  * @retval    None
  */
-void RTC_ConfigAlarmStructInit(RTC_AlarmConfig_T* alarmConfig)
+void RTC_ConfigAlarmStructInit(RTC_AlarmConfig_T *alarmConfig)
 {
     alarmConfig->time.hours = 0;
     alarmConfig->time.minutes = 0;
@@ -697,7 +697,7 @@ void RTC_ConfigAlarmStructInit(RTC_AlarmConfig_T* alarmConfig)
     alarmConfig->time.h12 = RTC_H12_AM;
     alarmConfig->alarmDateWeekDay = 1;
     alarmConfig->alarmDateWeekDaySel = RTC_WEEKDAY_SEL_DATE;
-    alarmConfig->alarmMask= RTC_MASK_NONE;
+    alarmConfig->alarmMask = RTC_MASK_NONE;
 }
 
 /*!
@@ -718,10 +718,10 @@ void RTC_ConfigAlarmStructInit(RTC_AlarmConfig_T* alarmConfig)
  *
  * @retval    None
  */
-void RTC_ReadAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T* alarmConfig)
+void RTC_ReadAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T *alarmConfig)
 {
-    uint8_t day_d,day_u,hours_d,hours_u,minutes_d,minutes_u,seconds_d,seconds_u;
-    uint32_t day_mask,hours_mask,minutes_mask,seconds_mask;
+    uint8_t day_d, day_u, hours_d, hours_u, minutes_d, minutes_u, seconds_d, seconds_u;
+    uint32_t day_mask, hours_mask, minutes_mask, seconds_mask;
 
     if (alarm == RTC_ALARM_A)
     {
@@ -734,10 +734,10 @@ void RTC_ReadAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T* al
         seconds_d = RTC->ALRMA_B.SECT << 0x04;
         seconds_u = RTC->ALRMA_B.SECU;
 
-        day_mask = RTC->ALRMA_B.DATEMEN<<8;
-        hours_mask = RTC->ALRMA_B.HRMEN<<8;
-        minutes_mask = RTC->ALRMA_B.MINMEN<<8;
-        seconds_mask = RTC->ALRMA_B.SECMEN<<7;
+        day_mask = RTC->ALRMA_B.DATEMEN << 8;
+        hours_mask = RTC->ALRMA_B.HRMEN << 8;
+        minutes_mask = RTC->ALRMA_B.MINMEN << 8;
+        seconds_mask = RTC->ALRMA_B.SECMEN << 7;
 
         alarmConfig->time.hours   = (uint8_t)(hours_d | hours_u);
         alarmConfig->time.minutes = (uint8_t)(minutes_d | minutes_u);
@@ -758,10 +758,10 @@ void RTC_ReadAlarm(RTC_FORMAT_T format, RTC_ALARM_T alarm, RTC_AlarmConfig_T* al
         seconds_d = RTC->ALRMB_B.SECT << 0x04;
         seconds_u = RTC->ALRMB_B.SECU;
 
-        day_mask = RTC->ALRMB_B.DATEMEN<<8;
-        hours_mask = RTC->ALRMB_B.HRMEN<<8;
-        minutes_mask = RTC->ALRMB_B.MINMEN<<8;
-        seconds_mask = RTC->ALRMB_B.SECMEN<<7;
+        day_mask = RTC->ALRMB_B.DATEMEN << 8;
+        hours_mask = RTC->ALRMB_B.HRMEN << 8;
+        minutes_mask = RTC->ALRMB_B.MINMEN << 8;
+        seconds_mask = RTC->ALRMB_B.SECMEN << 7;
 
         alarmConfig->time.hours   = (uint8_t)(hours_d | hours_u);
         alarmConfig->time.minutes = (uint8_t)(minutes_d | minutes_u);
@@ -1373,23 +1373,23 @@ void RTC_DisableTimeStamp(void)
  *
  * @retval    None
  */
-void RTC_ReadTimeDate(RTC_FORMAT_T format, RTC_TimeConfig_T* time, RTC_DateConfig_T* date)
+void RTC_ReadTimeDate(RTC_FORMAT_T format, RTC_TimeConfig_T *time, RTC_DateConfig_T *date)
 {
     uint32_t temptime = 0, tempdate = 0;
     temptime = (uint32_t)((RTC->TSTIME) & 0x007F7F7F);
     tempdate = (uint32_t)((RTC->TSDATE) & 0x00FFFF3F);
 
     /* Read the time in BCD format */
-    time->hours   = (uint8_t)((temptime & 0x003F0000 ) >> 16);
-    time->minutes = (uint8_t)((temptime & 0x00007F00) >>8);
+    time->hours   = (uint8_t)((temptime & 0x003F0000) >> 16);
+    time->minutes = (uint8_t)((temptime & 0x00007F00) >> 8);
     time->seconds = (uint8_t)(temptime &  0x0000007F);
     time->h12 = (RTC_H12_T)((temptime & 0x00400000) >> 22);
 
     /* Read the date in BCD format */
     date->year  =  0;
-    date->month = (RTC_MONTH_T)((tempdate & 0x00001F00) >>8);
+    date->month = (RTC_MONTH_T)((tempdate & 0x00001F00) >> 8);
     date->date  = (uint8_t)(tempdate &  0x0000003F);
-    date->weekday =(RTC_WEEKDAY_T)((tempdate & 0x0000E000) >> 13);
+    date->weekday = (RTC_WEEKDAY_T)((tempdate & 0x0000E000) >> 13);
 
     /* Binary format */
     if (format == RTC_FORMAT_BIN)
@@ -1782,7 +1782,7 @@ void RTC_DisableInterrupt(uint32_t interrupt)
  */
 uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag)
 {
-    return  (RTC->STS & flag) ? SET : RESET;
+    return (RTC->STS & flag) ? SET : RESET;
 }
 
 /*!
@@ -1877,7 +1877,7 @@ static uint8_t RTC_ByteConBcd2(uint8_t val)
         val -= 10;
     }
 
-    return  ((uint8_t)(bcdhigh << 4) | val);
+    return ((uint8_t)(bcdhigh << 4) | val);
 }
 
 /*!

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_sdio.c

@@ -59,7 +59,7 @@ void SDIO_Reset(void)
  *
  * @retval    None
  */
-void SDIO_Config(SDIO_Config_T* sdioConfig)
+void SDIO_Config(SDIO_Config_T *sdioConfig)
 {
     SDIO->CLKCTRL_B.CLKDIV   = sdioConfig->clockDiv;
     SDIO->CLKCTRL_B.PWRSAV   = sdioConfig->clockPowerSave;
@@ -76,7 +76,7 @@ void SDIO_Config(SDIO_Config_T* sdioConfig)
  *
  * @retval    None
  */
-void SDIO_ConfigStructInit(SDIO_Config_T* sdioConfig)
+void SDIO_ConfigStructInit(SDIO_Config_T *sdioConfig)
 {
     sdioConfig->clockDiv = 0x00;
     sdioConfig->clockEdge = SDIO_CLOCK_EDGE_RISING;
@@ -170,7 +170,7 @@ void SDIO_DisableDMA(void)
  *
  * @retval    None
  */
-void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig)
+void SDIO_TxCommand(SDIO_CmdConfig_T *cmdConfig)
 {
     uint32_t tempReg = 0;
 
@@ -179,7 +179,7 @@ void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig)
     /* Clear CMDINDEX, WAITRES, WAITINT, WENDDATA, CPSMEN bits */
     tempReg &= ((uint32_t)0xFFFFF800);
     tempReg |= (uint32_t)(cmdConfig->cmdIndex) | (cmdConfig->response) << 6
-             | (cmdConfig->wait) << 8 | (cmdConfig->CPSM) << 10;
+               | (cmdConfig->wait) << 8 | (cmdConfig->CPSM) << 10;
     SDIO->CMD = tempReg;
 }
 
@@ -190,7 +190,7 @@ void SDIO_TxCommand(SDIO_CmdConfig_T* cmdConfig)
  *
  * @retval    None
  */
-void SDIO_TxCommandStructInit(SDIO_CmdConfig_T* cmdConfig)
+void SDIO_TxCommandStructInit(SDIO_CmdConfig_T *cmdConfig)
 {
     cmdConfig->argument = 0x00;
     cmdConfig->cmdIndex = 0x00;
@@ -229,7 +229,7 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res)
 
     tmp = ((uint32_t)(SDIO_BASE + 0x14)) + res;
 
-    return (*(__IO uint32_t*) tmp);
+    return (*(__IO uint32_t *) tmp);
 }
 
 /*!
@@ -239,7 +239,7 @@ uint32_t SDIO_ReadResponse(SDIO_RES_T res)
  *
  * @retval    None
  */
-void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
+void SDIO_ConfigData(SDIO_DataConfig_T *dataConfig)
 {
     uint32_t tempReg = 0;
 
@@ -251,7 +251,7 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
     /* Clear DTEN, DTSEL, DTDRCFG and DBSIZE bits */
     tempReg &= ((uint32_t)0xFFFFFF08);
     tempReg |= (uint32_t)(dataConfig->dataBlockSize) << 4 | (dataConfig->transferDir) << 1
-       | (dataConfig->transferMode) << 2 | (dataConfig->DPSM);
+               | (dataConfig->transferMode) << 2 | (dataConfig->DPSM);
     SDIO->DCTRL = tempReg;
 }
 
@@ -262,7 +262,7 @@ void SDIO_ConfigData(SDIO_DataConfig_T* dataConfig)
  *
  * @retval    None
  */
-void SDIO_ConfigDataStructInit(SDIO_DataConfig_T* dataConfig)
+void SDIO_ConfigDataStructInit(SDIO_DataConfig_T *dataConfig)
 {
     dataConfig->dataTimeOut = 0xFFFFFFFF;
     dataConfig->dataLength = 0x00;

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_smc.c

@@ -130,7 +130,7 @@ void SMC_ResetPCCard(void)
  *
  * @retval    None
  */
-void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
+void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T *smcNORSRAMConfig)
 {
     if (smcNORSRAMConfig->bank == SMC_BANK1_NORSRAM_1)
     {
@@ -153,32 +153,32 @@ void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
         }
 
         SMC_Bank1->CSTIM1_B.ADDRSETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
         SMC_Bank1->CSTIM1_B.ADDRHLDCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
         SMC_Bank1->CSTIM1_B.DATASETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
         SMC_Bank1->CSTIM1_B.BUSTURNCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
         SMC_Bank1->CSTIM1_B.CLKDIVCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
+                                        smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
         SMC_Bank1->CSTIM1_B.DATALATCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
         SMC_Bank1->CSTIM1_B.ASYNCACCCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->accessMode;
+                                          smcNORSRAMConfig->readWriteTimingStruct->accessMode;
 
         if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
         {
             SMC_Bank1E->WRTTIM1_B.ADDRSETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
             SMC_Bank1E->WRTTIM1_B.ADDRHLDCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
             SMC_Bank1E->WRTTIM1_B.DATASETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
             SMC_Bank1E->WRTTIM1_B.BUSTURNCFG = \
-                smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
+                                               smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
             SMC_Bank1E->WRTTIM1_B.ASYNCACCCFG = \
-                smcNORSRAMConfig->writeTimingStruct->accessMode;
+                                                smcNORSRAMConfig->writeTimingStruct->accessMode;
         }
         else
         {
@@ -206,32 +206,32 @@ void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
         }
 
         SMC_Bank1->CSTIM2_B.ADDRSETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
         SMC_Bank1->CSTIM2_B.ADDRHLDCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
         SMC_Bank1->CSTIM2_B.DATASETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
         SMC_Bank1->CSTIM2_B.BUSTURNCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
         SMC_Bank1->CSTIM2_B.CLKDIVCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
+                                        smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
         SMC_Bank1->CSTIM2_B.DATALATCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
         SMC_Bank1->CSTIM2_B.ASYNCACCCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->accessMode;
+                                          smcNORSRAMConfig->readWriteTimingStruct->accessMode;
 
         if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
         {
             SMC_Bank1E->WRTTIM2_B.ADDRSETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
             SMC_Bank1E->WRTTIM2_B.ADDRHLDCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
             SMC_Bank1E->WRTTIM2_B.DATASETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
             SMC_Bank1E->WRTTIM2_B.BUSTURNCFG = \
-                smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
+                                               smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
             SMC_Bank1E->WRTTIM2_B.ASYNCACCCFG = \
-                smcNORSRAMConfig->writeTimingStruct->accessMode;
+                                                smcNORSRAMConfig->writeTimingStruct->accessMode;
         }
         else
         {
@@ -259,32 +259,32 @@ void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
         }
 
         SMC_Bank1->CSTIM3_B.ADDRSETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
         SMC_Bank1->CSTIM3_B.ADDRHLDCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
         SMC_Bank1->CSTIM3_B.DATASETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
         SMC_Bank1->CSTIM3_B.BUSTURNCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
         SMC_Bank1->CSTIM3_B.CLKDIVCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
+                                        smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
         SMC_Bank1->CSTIM3_B.DATALATCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
         SMC_Bank1->CSTIM3_B.ASYNCACCCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->accessMode;
+                                          smcNORSRAMConfig->readWriteTimingStruct->accessMode;
 
         if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
         {
             SMC_Bank1E->WRTTIM3_B.ADDRSETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
             SMC_Bank1E->WRTTIM3_B.ADDRHLDCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
             SMC_Bank1E->WRTTIM3_B.DATASETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
             SMC_Bank1E->WRTTIM3_B.BUSTURNCFG = \
-                smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
+                                               smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
             SMC_Bank1E->WRTTIM3_B.ASYNCACCCFG = \
-                smcNORSRAMConfig->writeTimingStruct->accessMode;
+                                                smcNORSRAMConfig->writeTimingStruct->accessMode;
         }
         else
         {
@@ -312,32 +312,32 @@ void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
         }
 
         SMC_Bank1->CSTIM4_B.ADDRSETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressSetupTime;
         SMC_Bank1->CSTIM4_B.ADDRHLDCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->addressHodeTime;
         SMC_Bank1->CSTIM4_B.DATASETCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataSetupTime;
         SMC_Bank1->CSTIM4_B.BUSTURNCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
+                                         smcNORSRAMConfig->readWriteTimingStruct->busTurnaroundTime;
         SMC_Bank1->CSTIM4_B.CLKDIVCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
+                                        smcNORSRAMConfig->readWriteTimingStruct->clockDivision;
         SMC_Bank1->CSTIM4_B.DATALATCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
+                                         smcNORSRAMConfig->readWriteTimingStruct->dataLatency;
         SMC_Bank1->CSTIM4_B.ASYNCACCCFG = \
-            smcNORSRAMConfig->readWriteTimingStruct->accessMode;
+                                          smcNORSRAMConfig->readWriteTimingStruct->accessMode;
 
         if (smcNORSRAMConfig->extendedMode == SMC_EXTENDEN_MODE_ENABLE)
         {
             SMC_Bank1E->WRTTIM4_B.ADDRSETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressSetupTime;
             SMC_Bank1E->WRTTIM4_B.ADDRHLDCFG = \
-                smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
+                                               smcNORSRAMConfig->writeTimingStruct->addressHodeTime;
             SMC_Bank1E->WRTTIM4_B.DATASETCFG = \
-                smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
+                                               smcNORSRAMConfig->writeTimingStruct->dataSetupTime;
             SMC_Bank1E->WRTTIM4_B.BUSTURNCFG = \
-                smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
+                                               smcNORSRAMConfig->writeTimingStruct->busTurnaroundTime;
             SMC_Bank1E->WRTTIM4_B.ASYNCACCCFG = \
-                smcNORSRAMConfig->writeTimingStruct->accessMode;
+                                                smcNORSRAMConfig->writeTimingStruct->accessMode;
         }
         else
         {
@@ -353,7 +353,7 @@ void SMC_ConfigNORSRAM(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
  *
  * @retval    None
  */
-void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
+void SMC_ConfigNAND(SMC_NANDConfig_T *smcNANDConfig)
 {
     if (smcNANDConfig->bank == SMC_BANK2_NAND)
     {
@@ -366,22 +366,22 @@ void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
         SMC_Bank2->CTRL2_B.MTYPECFG = BIT_SET;
 
         SMC_Bank2->CMSTIM2_B.SET2 = \
-            smcNANDConfig->commonSpaceTimingStruct->setupTime;
+                                    smcNANDConfig->commonSpaceTimingStruct->setupTime;
         SMC_Bank2->CMSTIM2_B.WAIT2 = \
-            smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
+                                     smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
         SMC_Bank2->CMSTIM2_B.HLD2 = \
-            smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
+                                    smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
         SMC_Bank2->CMSTIM2_B.HIZ2 = \
-            smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
+                                    smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
 
         SMC_Bank2->AMSTIM2_B.SET2 = \
-            smcNANDConfig->attributeSpaceTimingStruct->setupTime;
+                                    smcNANDConfig->attributeSpaceTimingStruct->setupTime;
         SMC_Bank2->AMSTIM2_B.WAIT2 = \
-            smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
+                                     smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
         SMC_Bank2->AMSTIM2_B.HLD2 = \
-            smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
+                                    smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
         SMC_Bank2->AMSTIM2_B.HIZ2 = \
-            smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
+                                    smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
     }
     else if (smcNANDConfig->bank == SMC_BANK3_NAND)
     {
@@ -394,22 +394,22 @@ void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
         SMC_Bank3->CTRL3_B.MTYPECFG = BIT_SET;
 
         SMC_Bank3->CMSTIM3_B.SET3 = \
-            smcNANDConfig->commonSpaceTimingStruct->setupTime;
+                                    smcNANDConfig->commonSpaceTimingStruct->setupTime;
         SMC_Bank3->CMSTIM3_B.WAIT3 = \
-            smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
+                                     smcNANDConfig->commonSpaceTimingStruct->waitSetupTime;
         SMC_Bank3->CMSTIM3_B.HLD3 = \
-            smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
+                                    smcNANDConfig->commonSpaceTimingStruct->holdSetupTime;
         SMC_Bank3->CMSTIM3_B.HIZ3 = \
-            smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
+                                    smcNANDConfig->commonSpaceTimingStruct->HiZSetupTime;
 
         SMC_Bank3->AMSTIM3_B.SET3 = \
-            smcNANDConfig->attributeSpaceTimingStruct->setupTime;
+                                    smcNANDConfig->attributeSpaceTimingStruct->setupTime;
         SMC_Bank3->AMSTIM3_B.WAIT3 = \
-            smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
+                                     smcNANDConfig->attributeSpaceTimingStruct->waitSetupTime;
         SMC_Bank3->AMSTIM3_B.HLD3 = \
-            smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
+                                    smcNANDConfig->attributeSpaceTimingStruct->holdSetupTime;
         SMC_Bank3->AMSTIM3_B.HIZ3 = \
-            smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
+                                    smcNANDConfig->attributeSpaceTimingStruct->HiZSetupTime;
     }
 }
 
@@ -420,7 +420,7 @@ void SMC_ConfigNAND(SMC_NANDConfig_T* smcNANDConfig)
  *
  * @retval    None
  */
-void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig)
+void SMC_ConfigPCCard(SMC_PCCARDConfig_T *smcPCCardConfig)
 {
     SMC_Bank4->CTRL4_B.WAITFEN = smcPCCardConfig->waitFeature;
     SMC_Bank4->CTRL4_B.C2RDCFG = smcPCCardConfig->TCLRSetupTime;
@@ -428,31 +428,31 @@ void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig)
     SMC_Bank4->CTRL4_B.DBWIDCFG = BIT_SET;
 
     SMC_Bank4->CMSTIM4_B.SET4 = \
-        smcPCCardConfig->commonSpaceTimingStruct->setupTime;
+                                smcPCCardConfig->commonSpaceTimingStruct->setupTime;
     SMC_Bank4->CMSTIM4_B.WAIT4 = \
-        smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime;
+                                 smcPCCardConfig->commonSpaceTimingStruct->waitSetupTime;
     SMC_Bank4->CMSTIM4_B.HLD4 = \
-        smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime;
+                                smcPCCardConfig->commonSpaceTimingStruct->holdSetupTime;
     SMC_Bank4->CMSTIM4_B.HIZ4 = \
-        smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime;
+                                smcPCCardConfig->commonSpaceTimingStruct->HiZSetupTime;
 
     SMC_Bank4->AMSTIM4_B.SET4 = \
-        smcPCCardConfig->attributeSpaceTimingStruct->setupTime;
+                                smcPCCardConfig->attributeSpaceTimingStruct->setupTime;
     SMC_Bank4->AMSTIM4_B.WAIT4 = \
-        smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime;
+                                 smcPCCardConfig->attributeSpaceTimingStruct->waitSetupTime;
     SMC_Bank4->AMSTIM4_B.HLD4 = \
-        smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime;
+                                smcPCCardConfig->attributeSpaceTimingStruct->holdSetupTime;
     SMC_Bank4->AMSTIM4_B.HIZ4 = \
-        smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime;
+                                smcPCCardConfig->attributeSpaceTimingStruct->HiZSetupTime;
 
     SMC_Bank4->IOSTIM4_B.SET = \
-        smcPCCardConfig->IOSpaceTimingStruct->setupTime;
+                               smcPCCardConfig->IOSpaceTimingStruct->setupTime;
     SMC_Bank4->IOSTIM4_B.WAIT = \
-        smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime;
+                                smcPCCardConfig->IOSpaceTimingStruct->waitSetupTime;
     SMC_Bank4->IOSTIM4_B.HLD = \
-        smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime;
+                               smcPCCardConfig->IOSpaceTimingStruct->holdSetupTime;
     SMC_Bank4->IOSTIM4_B.HIZ = \
-        smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime;
+                               smcPCCardConfig->IOSpaceTimingStruct->HiZSetupTime;
 }
 
 /*!
@@ -462,7 +462,7 @@ void SMC_ConfigPCCard(SMC_PCCARDConfig_T* smcPCCardConfig)
  *
  * @retval    None
  */
-void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
+void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T *smcNORSRAMConfig)
 {
     smcNORSRAMConfig->bank = SMC_BANK1_NORSRAM_1;
     smcNORSRAMConfig->dataAddressMux = SMC_DATA_ADDRESS_MUX_ENABLE;
@@ -500,7 +500,7 @@ void SMC_ConfigNORSRAMStructInit(SMC_NORSRAMConfig_T* smcNORSRAMConfig)
  *
  * @retval    None
  */
-void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig)
+void SMC_ConfigNANDStructInit(SMC_NANDConfig_T *smcNANDConfig)
 {
     smcNANDConfig->bank = SMC_BANK2_NAND;
     smcNANDConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
@@ -526,7 +526,7 @@ void SMC_ConfigNANDStructInit(SMC_NANDConfig_T* smcNANDConfig)
  *
  * @retval    None
  */
-void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T* smcPCCardConfig)
+void SMC_ConfigPCCardStructInit(SMC_PCCARDConfig_T *smcPCCardConfig)
 {
     smcPCCardConfig->waitFeature = SMC_WAIT_FEATURE_DISABLE;
     smcPCCardConfig->TCLRSetupTime = 0x0;

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_spi.c

@@ -46,7 +46,7 @@
  *
  * @retval    None
  */
-void SPI_I2S_Reset(SPI_T* spi)
+void SPI_I2S_Reset(SPI_T *spi)
 {
     if (spi == SPI1)
     {
@@ -89,7 +89,7 @@ void SPI_I2S_Reset(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
+void SPI_Config(SPI_T *spi, SPI_Config_T *spiConfig)
 {
     spi->CTRL1_B.MSMCFG = spiConfig->mode;
     spi->CTRL1_B.ISSEL = spiConfig->mode;
@@ -118,7 +118,7 @@ void SPI_Config(SPI_T* spi, SPI_Config_T* spiConfig)
  *
  * @retval    None
  */
-void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
+void I2S_Config(SPI_T *spi, I2S_Config_T *i2sConfig)
 {
     uint16_t i2sDiv = 2, i2sOdd = 0, packetSize = 1;
     uint32_t tmp = 0;
@@ -189,7 +189,7 @@ void I2S_Config(SPI_T* spi, I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
+void SPI_ConfigStructInit(SPI_Config_T *spiConfig)
 {
     spiConfig->direction     = SPI_DIRECTION_2LINES_FULLDUPLEX;
     spiConfig->mode          = SPI_MODE_SLAVE;
@@ -209,7 +209,7 @@ void SPI_ConfigStructInit(SPI_Config_T* spiConfig)
  *
  * @retval    None
  */
-void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
+void I2S_ConfigStructInit(I2S_Config_T *i2sConfig)
 {
     i2sConfig->mode       = I2S_MODE_SLAVE_TX;
     i2sConfig->standard   = I2S_STANDARD_PHILLIPS;
@@ -226,7 +226,7 @@ void I2S_ConfigStructInit(I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_Enable(SPI_T* spi)
+void SPI_Enable(SPI_T *spi)
 {
     spi->CTRL1_B.SPIEN = BIT_SET;
 }
@@ -238,7 +238,7 @@ void SPI_Enable(SPI_T* spi)
 *
 * @retval    None
 */
-void SPI_Disable(SPI_T* spi)
+void SPI_Disable(SPI_T *spi)
 {
     spi->CTRL1_B.SPIEN = BIT_RESET;
 }
@@ -250,7 +250,7 @@ void SPI_Disable(SPI_T* spi)
  *
  * @retval    None
  */
-void I2S_Enable(SPI_T* spi)
+void I2S_Enable(SPI_T *spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_SET;
 }
@@ -262,7 +262,7 @@ void I2S_Enable(SPI_T* spi)
  *
  * @retval    None
  */
-void I2S_Disable(SPI_T* spi)
+void I2S_Disable(SPI_T *spi)
 {
     spi->I2SCFG_B.I2SEN = BIT_RESET;
 }
@@ -279,7 +279,7 @@ void I2S_Disable(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
+void SPI_ConfigDataSize(SPI_T *spi, SPI_DATA_LENGTH_T length)
 {
     spi->CTRL1_B.DFLSEL = length;
 }
@@ -295,7 +295,7 @@ void SPI_ConfigDataSize(SPI_T* spi, SPI_DATA_LENGTH_T length)
  *                      @arg SPI_DIRECTION_TX : Selects Tx transmission direction
  * @retval    None
  */
-void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
+void SPI_ConfigBiDirectionalLine(SPI_T *spi, SPI_DIRECTION_SELECT_T direction)
 {
     spi->CTRL1_B.BMOEN = direction;
 }
@@ -306,7 +306,7 @@ void SPI_ConfigBiDirectionalLine(SPI_T* spi, SPI_DIRECTION_SELECT_T direction)
  *
  * @retval    None
  */
-void SPI_SetSoftwareNSS(SPI_T* spi)
+void SPI_SetSoftwareNSS(SPI_T *spi)
 {
     spi->CTRL1_B.ISSEL = BIT_SET;
 }
@@ -318,7 +318,7 @@ void SPI_SetSoftwareNSS(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_ResetSoftwareNSS(SPI_T* spi)
+void SPI_ResetSoftwareNSS(SPI_T *spi)
 {
     spi->CTRL1_B.ISSEL = BIT_RESET;
 }
@@ -330,7 +330,7 @@ void SPI_ResetSoftwareNSS(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableSSOutput(SPI_T* spi)
+void SPI_EnableSSOutput(SPI_T *spi)
 {
     spi->CTRL2_B.SSOEN = BIT_SET;
 }
@@ -342,7 +342,7 @@ void SPI_EnableSSOutput(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_DisableSSOutput(SPI_T* spi)
+void SPI_DisableSSOutput(SPI_T *spi)
 {
     spi->CTRL2_B.SSOEN = BIT_RESET;
 }
@@ -354,7 +354,7 @@ void SPI_DisableSSOutput(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableTIMode(SPI_T* spi)
+void SPI_EnableTIMode(SPI_T *spi)
 {
     spi->CTRL2_B.FRFCFG = BIT_SET;
 }
@@ -366,7 +366,7 @@ void SPI_EnableTIMode(SPI_T* spi)
 *
 * @retval    None
 */
-void SPI_DisableTIMode(SPI_T* spi)
+void SPI_DisableTIMode(SPI_T *spi)
 {
     spi->CTRL2_B.FRFCFG = BIT_RESET;
 }
@@ -389,7 +389,7 @@ void SPI_DisableTIMode(SPI_T* spi)
  *
  * @note   The I2S full-duplex extension only can be configured in slave mode.
  */
-void I2S_ConfigFullDuplex(SPI_T* i2sExt, I2S_Config_T* i2sConfig)
+void I2S_ConfigFullDuplex(SPI_T *i2sExt, I2S_Config_T *i2sConfig)
 {
     /** Reset I2SCFG and I2SPSC register */
     i2sExt->I2SCFG = 0;
@@ -427,7 +427,7 @@ void I2S_ConfigFullDuplex(SPI_T* i2sExt, I2S_Config_T* i2sConfig)
  *
  * @retval    None
  */
-void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
+void SPI_I2S_TxData(SPI_T *spi, uint16_t data)
 {
     spi->DATA = data;
 }
@@ -441,7 +441,7 @@ void SPI_I2S_TxData(SPI_T* spi, uint16_t data)
 *
 * @retval    None
 */
-uint16_t SPI_I2S_RxData(SPI_T* spi)
+uint16_t SPI_I2S_RxData(SPI_T *spi)
 {
     return spi->DATA;
 }
@@ -453,7 +453,7 @@ uint16_t SPI_I2S_RxData(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_EnableCRC(SPI_T* spi)
+void SPI_EnableCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCEN = BIT_SET;
 }
@@ -464,7 +464,7 @@ void SPI_EnableCRC(SPI_T* spi)
  * @param     spi: The SPIx can be 1,2,3,4,5,6.
  *
  */
-void SPI_DisableCRC(SPI_T* spi)
+void SPI_DisableCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCEN = BIT_RESET;
 }
@@ -476,7 +476,7 @@ void SPI_DisableCRC(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_TxCRC(SPI_T* spi)
+void SPI_TxCRC(SPI_T *spi)
 {
     spi->CTRL1_B.CRCNXT = BIT_SET;
 }
@@ -488,7 +488,7 @@ void SPI_TxCRC(SPI_T* spi)
  *
  * @retval    The SPI transmit CRC register value
  */
-uint16_t SPI_ReadTxCRC(SPI_T* spi)
+uint16_t SPI_ReadTxCRC(SPI_T *spi)
 {
     return spi->TXCRC_B.TXCRC;
 }
@@ -500,7 +500,7 @@ uint16_t SPI_ReadTxCRC(SPI_T* spi)
  *
  * @retval    The SPI receive CRC register value
  */
-uint16_t SPI_ReadRxCRC(SPI_T* spi)
+uint16_t SPI_ReadRxCRC(SPI_T *spi)
 {
     return spi->RXCRC_B.RXCRC;
 }
@@ -512,7 +512,7 @@ uint16_t SPI_ReadRxCRC(SPI_T* spi)
  *
  * @retval    The SPI CRC Polynomial register value
  */
-uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
+uint16_t SPI_ReadCRCPolynomial(SPI_T *spi)
 {
     return spi->CRCPOLY_B.CRCPOLY;
 }
@@ -529,7 +529,7 @@ uint16_t SPI_ReadCRCPolynomial(SPI_T* spi)
  *
  * @retval    None
  */
-void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_EnableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
     if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
@@ -553,7 +553,7 @@ void SPI_I2S_EnableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
  *
  * @retval    None
  */
-void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
+void SPI_I2S_DisableDMA(SPI_T *spi, SPI_I2S_DMA_REQ_T dmaReq)
 {
     if (dmaReq == SPI_I2S_DMA_REQ_TX)
     {
@@ -578,7 +578,7 @@ void SPI_I2S_DisableDMA(SPI_T* spi, SPI_I2S_DMA_REQ_T dmaReq)
  *
  * @retval       None
  */
-void SPI_I2S_EnableInterrupt(SPI_T* spi, uint32_t interrupt)
+void SPI_I2S_EnableInterrupt(SPI_T *spi, uint32_t interrupt)
 {
     spi->CTRL2 |= (uint32_t)(interrupt >> 8);
 }
@@ -596,7 +596,7 @@ void SPI_I2S_EnableInterrupt(SPI_T* spi, uint32_t interrupt)
  *
  * @retval    None
  */
-void SPI_I2S_DisableInterrupt(SPI_T* spi, uint32_t interrupt)
+void SPI_I2S_DisableInterrupt(SPI_T *spi, uint32_t interrupt)
 {
     spi->CTRL2 &= ~((uint32_t)(interrupt >> 8));
 }
@@ -619,7 +619,7 @@ void SPI_I2S_DisableInterrupt(SPI_T* spi, uint32_t interrupt)
  *
  * @retval     SET or RESET
  */
-uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
+uint8_t SPI_I2S_ReadStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 {
     return (spi->STS & flag) ? SET : RESET;
 }
@@ -642,7 +642,7 @@ uint8_t SPI_I2S_ReadStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadStatusFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
+void SPI_I2S_ClearStatusFlag(SPI_T *spi, SPI_FLAG_T flag)
 {
     if (flag == SPI_FLAG_CRCE)
     {
@@ -666,7 +666,7 @@ void SPI_I2S_ClearStatusFlag(SPI_T* spi, SPI_FLAG_T flag)
  *
  * @retval       SET or RESET
  */
-uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
+uint8_t SPI_I2S_ReadIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 {
     uint32_t intEnable;
     uint32_t intStatus;
@@ -700,7 +700,7 @@ uint8_t SPI_I2S_ReadIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
  *              a read/write operation to SPI_STS register (SPI_I2S_ReadIntFlag())
  *              followed by a write operation to SPI_CTRL1 register (SPI_Enable()).
  */
-void SPI_I2S_ClearIntFlag(SPI_T* spi, SPI_I2S_INT_T flag)
+void SPI_I2S_ClearIntFlag(SPI_T *spi, SPI_I2S_INT_T flag)
 {
     if (flag == SPI_INT_CRCE)
     {

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_syscfg.c

@@ -118,15 +118,15 @@ void SYSCFG_ConfigEINTLine(SYSCFG_PORT_T port, SYSCFG_PIN_T pin)
     {
         SYSCFG->EINTCFG1 |= status;
     }
-    else if  ((pin >> 2) == 1)
+    else if ((pin >> 2) == 1)
     {
         SYSCFG->EINTCFG2 |= status;
     }
-    else if  ((pin >> 2) == 2)
+    else if ((pin >> 2) == 2)
     {
         SYSCFG->EINTCFG3 |= status;
     }
-    else if  ((pin >> 2) == 3)
+    else if ((pin >> 2) == 3)
     {
         SYSCFG->EINTCFG4 |= status;
     }

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_tmr.c

@@ -39,10 +39,10 @@
   @{
 */
 
-static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
-static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
-static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
-static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
+static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter);
 
 /*!
  * @brief     Deinitializes the TMRx peripheral registers to their default reset values.
@@ -53,7 +53,7 @@ static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @note
  */
-void TMR_Reset(TMR_T* tmr)
+void TMR_Reset(TMR_T *tmr)
 {
     if (tmr == TMR1)
     {
@@ -136,11 +136,11 @@ void TMR_Reset(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig)
+void TMR_ConfigTimeBase(TMR_T *tmr, TMR_BaseConfig_T *baseConfig)
 {
     if ((tmr == TMR1) || (tmr == TMR2) || \
-        (tmr == TMR3) || (tmr == TMR4) || \
-        (tmr == TMR5) || (tmr == TMR8))
+            (tmr == TMR3) || (tmr == TMR4) || \
+            (tmr == TMR5) || (tmr == TMR8))
     {
         /** Count Direction */
         tmr->CTRL1_B.CNTDIR = baseConfig->countMode & 0x01;
@@ -172,7 +172,7 @@ void TMR_ConfigTimeBase(TMR_T* tmr, TMR_BaseConfig_T* baseConfig)
  *
  * @retval    None
  */
-void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig)
+void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T *baseConfig)
 {
     baseConfig->countMode = TMR_COUNTER_MODE_UP;
     baseConfig->clockDivision = TMR_CLOCK_DIV_1;
@@ -195,7 +195,7 @@ void TMR_ConfigTimeBaseStructInit(TMR_BaseConfig_T* baseConfig)
  *
  * @retval    None
  */
-void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t psc, TMR_PSC_RELOAD_T reload)
+void TMR_ConfigPrescaler(TMR_T *tmr, uint16_t psc, TMR_PSC_RELOAD_T reload)
 {
     tmr->PSC_B.PSC = psc;
     tmr->CEG_B.UEG = reload;
@@ -216,7 +216,7 @@ void TMR_ConfigPrescaler(TMR_T* tmr, uint16_t psc, TMR_PSC_RELOAD_T reload)
  *
  * @retval    None
  */
-void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode)
+void TMR_ConfigCounterMode(TMR_T *tmr, TMR_COUNTER_MODE_T countMode)
 {
     tmr->CTRL1_B.CNTDIR = countMode & 0x01;
     tmr->CTRL1_B.CAMSEL = countMode >> 4;
@@ -231,7 +231,7 @@ void TMR_ConfigCounterMode(TMR_T* tmr, TMR_COUNTER_MODE_T countMode)
  *
  * @retval    None
  */
-void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter)
+void TMR_ConfigCounter(TMR_T *tmr, uint16_t counter)
 {
     tmr->CNT = counter;
 }
@@ -245,7 +245,7 @@ void TMR_ConfigCounter(TMR_T* tmr, uint16_t counter)
  *
  * @retval    None
  */
-void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload)
+void TMR_ConfigAutoreload(TMR_T *tmr, uint16_t autoReload)
 {
     tmr->AUTORLD_B.AUTORLD = autoReload;
 }
@@ -257,7 +257,7 @@ void TMR_ConfigAutoreload(TMR_T* tmr, uint16_t autoReload)
  *
  * @retval    Counter Register value.
  */
-uint16_t TMR_ReadCounter(TMR_T* tmr)
+uint16_t TMR_ReadCounter(TMR_T *tmr)
 {
     return tmr->CNT;
 }
@@ -269,7 +269,7 @@ uint16_t TMR_ReadCounter(TMR_T* tmr)
  *
  * @retval    Prescaler Register value.
  */
-uint16_t TMR_ReadPrescaler(TMR_T* tmr)
+uint16_t TMR_ReadPrescaler(TMR_T *tmr)
 {
     return tmr->PSC;
 }
@@ -281,7 +281,7 @@ uint16_t TMR_ReadPrescaler(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_EnableUpdate(TMR_T* tmr)
+void TMR_EnableUpdate(TMR_T *tmr)
 {
     /** Clear Update Disable bit */
     tmr->CTRL1_B.UD = DISABLE;
@@ -294,7 +294,7 @@ void TMR_EnableUpdate(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableUpdate(TMR_T* tmr)
+void TMR_DisableUpdate(TMR_T *tmr)
 {
     /** Set Update Disable bit */
     tmr->CTRL1_B.UD = ENABLE;
@@ -316,7 +316,7 @@ void TMR_DisableUpdate(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource)
+void TMR_ConfigUpdateRequest(TMR_T *tmr, TMR_UPDATE_SOURCE_T updateSource)
 {
     tmr->CTRL1_B.URSSEL = updateSource;
 }
@@ -328,7 +328,7 @@ void TMR_ConfigUpdateRequest(TMR_T* tmr, TMR_UPDATE_SOURCE_T updateSource)
  *
  * @retval    None
  */
-void TMR_EnableAutoReload(TMR_T* tmr)
+void TMR_EnableAutoReload(TMR_T *tmr)
 {
     tmr->CTRL1_B.ARPEN = ENABLE;
 }
@@ -340,7 +340,7 @@ void TMR_EnableAutoReload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableAutoReload(TMR_T* tmr)
+void TMR_DisableAutoReload(TMR_T *tmr)
 {
     tmr->CTRL1_B.ARPEN = DISABLE;
 }
@@ -357,7 +357,7 @@ void TMR_DisableAutoReload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode)
+void TMR_ConfigSinglePulseMode(TMR_T *tmr, TMR_SPM_T singlePulseMode)
 {
     tmr->CTRL1_B.SPMEN = singlePulseMode;
 }
@@ -375,7 +375,7 @@ void TMR_ConfigSinglePulseMode(TMR_T* tmr, TMR_SPM_T singlePulseMode)
  *
  * @retval    None
  */
-void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision)
+void TMR_ConfigClockDivision(TMR_T *tmr, TMR_CLOCK_DIV_T clockDivision)
 {
     tmr->CTRL1_B.CLKDIV = clockDivision;
 }
@@ -387,7 +387,7 @@ void TMR_ConfigClockDivision(TMR_T* tmr, TMR_CLOCK_DIV_T clockDivision)
  *
  * @retval    None
  */
-void TMR_Enable(TMR_T* tmr)
+void TMR_Enable(TMR_T *tmr)
 {
     tmr->CTRL1_B.CNTEN = ENABLE;
 }
@@ -399,7 +399,7 @@ void TMR_Enable(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_Disable(TMR_T* tmr)
+void TMR_Disable(TMR_T *tmr)
 {
     tmr->CTRL1_B.CNTEN = DISABLE;
 }
@@ -413,7 +413,7 @@ void TMR_Disable(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC1(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC1EN = BIT_RESET;
 
@@ -444,7 +444,7 @@ void TMR_ConfigOC1(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC2(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC2EN = BIT_RESET;
 
@@ -477,7 +477,7 @@ void TMR_ConfigOC2(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC3(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC3EN = BIT_RESET;
 
@@ -510,7 +510,7 @@ void TMR_ConfigOC3(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOC4(TMR_T *tmr, TMR_OCConfig_T *OCConfig)
 {
     tmr->CCEN_B.CC4EN = BIT_RESET;
 
@@ -536,7 +536,7 @@ void TMR_ConfigOC4(TMR_T* tmr, TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig)
+void TMR_ConfigOCStructInit(TMR_OCConfig_T *OCConfig)
 {
     OCConfig->mode = TMR_OC_MODE_TMRING;
     OCConfig->outputState = TMR_OC_STATE_DISABLE;
@@ -573,7 +573,7 @@ void TMR_ConfigOCStructInit(TMR_OCConfig_T* OCConfig)
  *
  * @retval    None
  */
-void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
+void TMR_SelectOCxMode(TMR_T *tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
 {
     if (channel == TMR_CHANNEL_1)
     {
@@ -602,7 +602,7 @@ void TMR_SelectOCxMode(TMR_T* tmr, TMR_CHANNEL_T channel, TMR_OC_MODE_T mode)
  *
  * @retval    None
  */
-void TMR_ConfigCompare1(TMR_T* tmr, uint32_t compare1)
+void TMR_ConfigCompare1(TMR_T *tmr, uint32_t compare1)
 {
     tmr->CC1 = compare1;
 }
@@ -616,7 +616,7 @@ void TMR_ConfigCompare1(TMR_T* tmr, uint32_t compare1)
  *
  * @retval    None
  */
-void TMR_ConfigCompare2(TMR_T* tmr, uint32_t compare2)
+void TMR_ConfigCompare2(TMR_T *tmr, uint32_t compare2)
 {
     tmr->CC2 = compare2;
 }
@@ -630,7 +630,7 @@ void TMR_ConfigCompare2(TMR_T* tmr, uint32_t compare2)
  *
  * @retval    None
  */
-void TMR_ConfigCompare3(TMR_T* tmr, uint32_t compare3)
+void TMR_ConfigCompare3(TMR_T *tmr, uint32_t compare3)
 {
     tmr->CC3 = compare3;
 }
@@ -644,7 +644,7 @@ void TMR_ConfigCompare3(TMR_T* tmr, uint32_t compare3)
  *
  * @retval    None
  */
-void TMR_ConfigCompare4(TMR_T* tmr, uint32_t compare4)
+void TMR_ConfigCompare4(TMR_T *tmr, uint32_t compare4)
 {
     tmr->CC4 = compare4;
 }
@@ -661,7 +661,7 @@ void TMR_ConfigCompare4(TMR_T* tmr, uint32_t compare4)
  *
  * @retval    None
  */
-void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC1(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM1_COMPARE_B.OC1MOD = forcesAction;
 }
@@ -678,7 +678,7 @@ void TMR_ConfigForcedOC1(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC2(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM1_COMPARE_B.OC2MOD = forcesAction;
 }
@@ -695,7 +695,7 @@ void TMR_ConfigForcedOC2(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC3(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM2_COMPARE_B.OC3MOD = forcesAction;
 }
@@ -712,7 +712,7 @@ void TMR_ConfigForcedOC3(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
+void TMR_ConfigForcedOC4(TMR_T *tmr, TMR_FORCED_ACTION_T forcesAction)
 {
     tmr->CCM2_COMPARE_B.OC4MOD = forcesAction;
 }
@@ -729,7 +729,7 @@ void TMR_ConfigForcedOC4(TMR_T* tmr, TMR_FORCED_ACTION_T forcesAction)
  *
  * @retval    None
  */
-void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC1Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM1_COMPARE_B.OC1PEN = OCPreload;
 }
@@ -746,7 +746,7 @@ void TMR_ConfigOC1Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *
  * @retval    None
  */
-void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC2Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM1_COMPARE_B.OC2PEN = OCPreload;
 }
@@ -763,7 +763,7 @@ void TMR_ConfigOC2Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *
  * @retval    None
  */
-void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC3Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM2_COMPARE_B.OC3PEN = OCPreload;
 }
@@ -780,7 +780,7 @@ void TMR_ConfigOC3Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *
  * @retval    Nonee
  */
-void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
+void TMR_ConfigOC4Preload(TMR_T *tmr, TMR_OC_PRELOAD_T OCPreload)
 {
     tmr->CCM2_COMPARE_B.OC4PEN = OCPreload;
 }
@@ -797,7 +797,7 @@ void TMR_ConfigOC4Preload(TMR_T* tmr, TMR_OC_PRELOAD_T OCPreload)
  *
  * @retval    None
  */
-void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC1Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM1_COMPARE_B.OC1FEN = OCFast;
 }
@@ -814,7 +814,7 @@ void TMR_ConfigOC1Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *
  * @retval    None
  */
-void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC2Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM1_COMPARE_B.OC2FEN = OCFast;
 }
@@ -831,7 +831,7 @@ void TMR_ConfigOC2Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *
  * @retval    None
  */
-void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC3Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM2_COMPARE_B.OC3FEN = OCFast;
 }
@@ -848,7 +848,7 @@ void TMR_ConfigOC3Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *
  * @retval    None
  */
-void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
+void TMR_ConfigOC4Fast(TMR_T *tmr, TMR_OC_FAST_T OCFast)
 {
     tmr->CCM2_COMPARE_B.OC4FEN = OCFast;
 }
@@ -865,7 +865,7 @@ void TMR_ConfigOC4Fast(TMR_T* tmr, TMR_OC_FAST_T OCFast)
  *
  * @retval    None
  */
-void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC1Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM1_COMPARE_B.OC1CEN = OCClear;
 }
@@ -882,7 +882,7 @@ void TMR_ClearOC1Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *
  * @retval    None
  */
-void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC2Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM1_COMPARE_B.OC2CEN = OCClear;
 }
@@ -899,7 +899,7 @@ void TMR_ClearOC2Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *
  * @retval    None
  */
-void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC3Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM2_COMPARE_B.OC3CEN = OCClear;
 }
@@ -916,7 +916,7 @@ void TMR_ClearOC3Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *
  * @retval    None
  */
-void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
+void TMR_ClearOC4Ref(TMR_T *tmr, TMR_OC_CLEAR_T OCClear)
 {
     tmr->CCM2_COMPARE_B.OC4CEN = OCClear;
 }
@@ -933,7 +933,7 @@ void TMR_ClearOC4Ref(TMR_T* tmr, TMR_OC_CLEAR_T OCClear)
  *
  * @retval    None
  */
-void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC1Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC1POL = polarity;
 }
@@ -950,7 +950,7 @@ void TMR_ConfigOC1Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *
  * @retval    None
  */
-void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
+void TMR_ConfigOC1NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
 {
     tmr->CCEN_B.CC1NPOL = nPolarity;
 }
@@ -967,7 +967,7 @@ void TMR_ConfigOC1NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
  *
  * @retval    None
  */
-void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC2Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC2POL = polarity;
 }
@@ -984,7 +984,7 @@ void TMR_ConfigOC2Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *
  * @retval    None
  */
-void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
+void TMR_ConfigOC2NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
 {
     tmr->CCEN_B.CC2NPOL = nPolarity;
 }
@@ -1001,7 +1001,7 @@ void TMR_ConfigOC2NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
  *
  * @retval    None
  */
-void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC3Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC3POL = polarity;
 }
@@ -1018,7 +1018,7 @@ void TMR_ConfigOC3Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *
  * @retval    None
  */
-void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
+void TMR_ConfigOC3NPolarity(TMR_T *tmr, TMR_OC_NPOLARITY_T nPolarity)
 {
     tmr->CCEN_B.CC3NPOL = nPolarity;
 }
@@ -1035,7 +1035,7 @@ void TMR_ConfigOC3NPolarity(TMR_T* tmr, TMR_OC_NPOLARITY_T nPolarity)
  *
  * @retval    None
  */
-void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
+void TMR_ConfigOC4Polarity(TMR_T *tmr, TMR_OC_POLARITY_T polarity)
 {
     tmr->CCEN_B.CC4POL = polarity;
 }
@@ -1054,7 +1054,7 @@ void TMR_ConfigOC4Polarity(TMR_T* tmr, TMR_OC_POLARITY_T polarity)
  *
  * @retval    None
  */
-void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_EnableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     if (channel == TMR_CHANNEL_1)
     {
@@ -1088,7 +1088,7 @@ void TMR_EnableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *
  * @retval    None
  */
-void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_DisableCCxChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     if (channel == TMR_CHANNEL_1)
     {
@@ -1121,7 +1121,7 @@ void TMR_DisableCCxChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *
  * @retval    None
  */
-void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_EnableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     if (channel == TMR_CHANNEL_1)
     {
@@ -1150,7 +1150,7 @@ void TMR_EnableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *
  * @retval    None
  */
-void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
+void TMR_DisableCCxNChannel(TMR_T *tmr, TMR_CHANNEL_T channel)
 {
     if (channel == TMR_CHANNEL_1)
     {
@@ -1175,7 +1175,7 @@ void TMR_DisableCCxNChannel(TMR_T* tmr, TMR_CHANNEL_T channel)
  *
  * @retval    None
  */
-void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig)
+void TMR_ConfigIC(TMR_T *tmr, TMR_ICConfig_T *ICConfig)
 {
     if (ICConfig->channel == TMR_CHANNEL_1)
     {
@@ -1206,7 +1206,7 @@ void TMR_ConfigIC(TMR_T* tmr, TMR_ICConfig_T* ICConfig)
  *
  * @retval    None
  */
-void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig)
+void TMR_ConfigICStructInit(TMR_ICConfig_T *ICConfig)
 {
     ICConfig->channel = TMR_CHANNEL_1;
     ICConfig->polarity = TMR_IC_POLARITY_RISING;
@@ -1224,7 +1224,7 @@ void TMR_ConfigICStructInit(TMR_ICConfig_T* ICConfig)
  *
  * @retval    None
  */
-void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig)
+void TMR_ConfigPWM(TMR_T *tmr, TMR_ICConfig_T *PWMConfig)
 {
     uint16_t icpolarity = TMR_IC_POLARITY_RISING;
     uint16_t icselection = TMR_IC_SELECTION_DIRECT_TI;
@@ -1270,7 +1270,7 @@ void TMR_ConfigPWM(TMR_T* tmr, TMR_ICConfig_T* PWMConfig)
  *
  * @retval    Capture Compare 1 Register value.
  */
-uint32_t TMR_ReadCaputer1(TMR_T* tmr)
+uint32_t TMR_ReadCaputer1(TMR_T *tmr)
 {
     return tmr->CC1;
 }
@@ -1282,7 +1282,7 @@ uint32_t TMR_ReadCaputer1(TMR_T* tmr)
  *
  * @retval    Capture Compare 2 Register value.
  */
-uint32_t TMR_ReadCaputer2(TMR_T* tmr)
+uint32_t TMR_ReadCaputer2(TMR_T *tmr)
 {
     return tmr->CC2;
 }
@@ -1294,7 +1294,7 @@ uint32_t TMR_ReadCaputer2(TMR_T* tmr)
  *
  * @retval    Capture Compare 3 Register value.
  */
-uint32_t TMR_ReadCaputer3(TMR_T* tmr)
+uint32_t TMR_ReadCaputer3(TMR_T *tmr)
 {
     return tmr->CC3;
 }
@@ -1306,7 +1306,7 @@ uint32_t TMR_ReadCaputer3(TMR_T* tmr)
  *
  * @retval    Capture Compare 4 Register value.
  */
-uint32_t TMR_ReadCaputer4(TMR_T* tmr)
+uint32_t TMR_ReadCaputer4(TMR_T *tmr)
 {
     return tmr->CC4;
 }
@@ -1325,7 +1325,7 @@ uint32_t TMR_ReadCaputer4(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigIC1Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC1Prescaler(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM1_CAPTURE_B.IC1PSC = prescaler;
 }
@@ -1343,7 +1343,7 @@ void TMR_ConfigIC1Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *
  * @retval    None
  */
-void TMR_ConfigIC2Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC2Prescaler(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM1_CAPTURE_B.IC2PSC = prescaler;
 }
@@ -1362,7 +1362,7 @@ void TMR_ConfigIC2Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *
  * @retval    None
  */
-void TMR_ConfigIC3Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC3Prescaler(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM2_CAPTURE_B.IC3PSC = prescaler;
 }
@@ -1381,7 +1381,7 @@ void TMR_ConfigIC3Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *
  * @retval    None
  */
-void TMR_ConfigIC4Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
+void TMR_ConfigIC4Prescaler(TMR_T *tmr, TMR_IC_PSC_T prescaler)
 {
     tmr->CCM2_CAPTURE_B.IC4PSC = prescaler;
 }
@@ -1395,7 +1395,7 @@ void TMR_ConfigIC4Prescaler(TMR_T* tmr, TMR_IC_PSC_T prescaler)
  *
  * @retval    None
  */
-void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig)
+void TMR_ConfigBDT(TMR_T *tmr, TMR_BDTConfig_T *BDTConfig)
 {
     tmr->BDT = (BDTConfig->IMOS) << 10 | \
                (BDTConfig->RMOS) << 11 | \
@@ -1413,7 +1413,7 @@ void TMR_ConfigBDT(TMR_T* tmr, TMR_BDTConfig_T* BDTConfig)
  *
  * @retval    None
  */
-void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig)
+void TMR_ConfigBDTStructInit(TMR_BDTConfig_T *BDTConfig)
 {
     BDTConfig->RMOS = TMR_RMOS_STATE_DISABLE;
     BDTConfig->IMOS = TMR_IMOS_STATE_DISABLE;
@@ -1431,7 +1431,7 @@ void TMR_ConfigBDTStructInit( TMR_BDTConfig_T* BDTConfig)
  *
  * @retval    None
  */
-void TMR_EnablePWMOutputs(TMR_T* tmr)
+void TMR_EnablePWMOutputs(TMR_T *tmr)
 {
     tmr->BDT_B.MOEN = ENABLE;
 }
@@ -1443,7 +1443,7 @@ void TMR_EnablePWMOutputs(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisablePWMOutputs(TMR_T* tmr)
+void TMR_DisablePWMOutputs(TMR_T *tmr)
 {
     tmr->BDT_B.MOEN = DISABLE;
 }
@@ -1455,7 +1455,7 @@ void TMR_DisablePWMOutputs(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_EnableSelectCOM(TMR_T* tmr)
+void TMR_EnableSelectCOM(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCUSEL = ENABLE;
 }
@@ -1466,7 +1466,7 @@ void TMR_EnableSelectCOM(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableSelectCOM(TMR_T* tmr)
+void TMR_DisableSelectCOM(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCUSEL = DISABLE;
 }
@@ -1478,7 +1478,7 @@ void TMR_DisableSelectCOM(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_EnableCCPreload(TMR_T* tmr)
+void TMR_EnableCCPreload(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCPEN = ENABLE;
 }
@@ -1490,7 +1490,7 @@ void TMR_EnableCCPreload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableCCPreload(TMR_T* tmr)
+void TMR_DisableCCPreload(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCPEN = DISABLE;
 }
@@ -1527,7 +1527,7 @@ void TMR_DisableCCPreload(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
+void TMR_ConfigDMA(TMR_T *tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T burstLength)
 {
     tmr->DCTRL = (uint32_t)baseAddress | (uint32_t)burstLength;
 }
@@ -1551,7 +1551,7 @@ void TMR_ConfigDMA(TMR_T* tmr, TMR_DMA_BASE_T baseAddress, TMR_DMA_BURSTLENGTH_T
  *
  * @note
  */
-void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource)
+void TMR_EnableDMASoure(TMR_T *tmr, uint16_t dmaSource)
 {
     tmr->DIEN |= dmaSource;
 }
@@ -1575,7 +1575,7 @@ void TMR_EnableDMASoure(TMR_T* tmr, uint16_t dmaSource)
  *
  * @note
  */
-void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource)
+void TMR_DisableDMASoure(TMR_T *tmr, uint16_t dmaSource)
 {
     tmr->DIEN &= ~dmaSource;
 }
@@ -1587,7 +1587,7 @@ void TMR_DisableDMASoure(TMR_T* tmr, uint16_t dmaSource)
  *
  * @retval    None
  */
-void TMR_EnableCCDMA(TMR_T* tmr)
+void TMR_EnableCCDMA(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCDSEL = ENABLE;
 }
@@ -1599,7 +1599,7 @@ void TMR_EnableCCDMA(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableCCDMA(TMR_T* tmr)
+void TMR_DisableCCDMA(TMR_T *tmr)
 {
     tmr->CTRL2_B.CCDSEL = DISABLE;
 }
@@ -1611,7 +1611,7 @@ void TMR_DisableCCDMA(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigInternalClock(TMR_T* tmr)
+void TMR_ConfigInternalClock(TMR_T *tmr)
 {
     tmr->SMCTRL_B.SMFSEL = BIT_RESET;
 }
@@ -1630,7 +1630,7 @@ void TMR_ConfigInternalClock(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
+void TMR_ConfigIntTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
 {
     TMR_SelectInputTrigger(tmr, triggerSource);
     tmr->SMCTRL_B.SMFSEL = TMR_SLAVE_MODE_EXTERNAL1;
@@ -1656,7 +1656,7 @@ void TMR_ConfigIntTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSour
  *
  * @retval    None
  */
-void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
+void TMR_ConfigTrigExternalClock(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource,
                                  TMR_IC_POLARITY_T ICpolarity, uint16_t ICfilter)
 {
     if (triggerSource == TMR_TRIGGER_SOURCE_TI2FP2)
@@ -1693,7 +1693,7 @@ void TMR_ConfigTrigExternalClock(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource,
  *
  * @retval    None
  */
-void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode1(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter)
 {
     TMR_ConfigETR(tmr, prescaler, polarity, filter);
@@ -1723,7 +1723,7 @@ void TMR_ConfigETRClockMode1(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
  *
  * @retval    None
  */
-void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETRClockMode2(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                              TMR_EXTTRG_POL_T polarity, uint16_t filter)
 {
     TMR_ConfigETR(tmr, prescaler, polarity, filter);
@@ -1749,7 +1749,7 @@ void TMR_ConfigETRClockMode2(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
  *
  * @retval    None
  */
-void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
+void TMR_SelectInputTrigger(TMR_T *tmr, TMR_TRIGGER_SOURCE_T triggerSource)
 {
     tmr->SMCTRL_B.TRGSEL = triggerSource;
 }
@@ -1773,7 +1773,7 @@ void TMR_SelectInputTrigger(TMR_T* tmr, TMR_TRIGGER_SOURCE_T triggerSource)
  *
  * @retval    None
  */
-void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource)
+void TMR_SelectOutputTrigger(TMR_T *tmr, TMR_TRGO_SOURCE_T TRGOSource)
 {
     tmr->CTRL2_B.MMSEL = TRGOSource;
 }
@@ -1792,7 +1792,7 @@ void TMR_SelectOutputTrigger(TMR_T* tmr, TMR_TRGO_SOURCE_T TRGOSource)
  *
  * @retval    None
  */
-void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode)
+void TMR_SelectSlaveMode(TMR_T *tmr, TMR_SLAVE_MODE_T slaveMode)
 {
     tmr->SMCTRL_B.SMFSEL = slaveMode;
 }
@@ -1804,7 +1804,7 @@ void TMR_SelectSlaveMode(TMR_T* tmr, TMR_SLAVE_MODE_T slaveMode)
  *
  * @retval    None
  */
-void TMR_EnableMasterSlaveMode(TMR_T* tmr)
+void TMR_EnableMasterSlaveMode(TMR_T *tmr)
 {
     tmr->SMCTRL_B.MSMEN = ENABLE;
 }
@@ -1816,7 +1816,7 @@ void TMR_EnableMasterSlaveMode(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableMasterSlaveMode(TMR_T* tmr)
+void TMR_DisableMasterSlaveMode(TMR_T *tmr)
 {
     tmr->SMCTRL_B.MSMEN = DISABLE;
 }
@@ -1842,7 +1842,7 @@ void TMR_DisableMasterSlaveMode(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
+void TMR_ConfigETR(TMR_T *tmr, TMR_EXTTRG_PSC_T prescaler,
                    TMR_EXTTRG_POL_T polarity, uint16_t filter)
 {
     tmr->SMCTRL &= 0x00FF;
@@ -1874,7 +1874,7 @@ void TMR_ConfigETR(TMR_T* tmr, TMR_EXTTRG_PSC_T prescaler,
  *
  * @retval    None
  */
-void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
+void TMR_ConfigEncodeInterface(TMR_T *tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC_POLARITY_T IC1Polarity,
                                TMR_IC_POLARITY_T IC2Polarity)
 {
     tmr->SMCTRL_B.SMFSEL = BIT_RESET;
@@ -1898,7 +1898,7 @@ void TMR_ConfigEncodeInterface(TMR_T* tmr, TMR_ENCODER_MODE_T encodeMode, TMR_IC
  *
  * @retval    None
  */
-void TMR_EnableHallSensor(TMR_T* tmr)
+void TMR_EnableHallSensor(TMR_T *tmr)
 {
     tmr->CTRL2_B.TI1SEL = ENABLE;
 }
@@ -1910,7 +1910,7 @@ void TMR_EnableHallSensor(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_DisableHallSensor(TMR_T* tmr)
+void TMR_DisableHallSensor(TMR_T *tmr)
 {
     tmr->CTRL2_B.TI1SEL = DISABLE;
 }
@@ -1937,7 +1937,7 @@ void TMR_DisableHallSensor(TMR_T* tmr)
  *
  * @retval    None
  */
-void TMR_ConfigRemap(TMR_T* tmr, uint32_t remap)
+void TMR_ConfigRemap(TMR_T *tmr, uint32_t remap)
 {
     tmr->OPT = remap;
 }
@@ -1962,7 +1962,7 @@ void TMR_ConfigRemap(TMR_T* tmr, uint32_t remap)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt)
+void TMR_EnableInterrupt(TMR_T *tmr, uint16_t interrupt)
 {
     tmr->DIEN |= interrupt;
 }
@@ -1987,7 +1987,7 @@ void TMR_EnableInterrupt(TMR_T* tmr, uint16_t interrupt)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt)
+void TMR_DisableInterrupt(TMR_T *tmr, uint16_t interrupt)
 {
     tmr->DIEN &= ~interrupt;
 }
@@ -2012,7 +2012,7 @@ void TMR_DisableInterrupt(TMR_T* tmr, uint16_t interrupt)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_EVENT_UPDATE.
  */
-void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources)
+void TMR_GenerateEvent(TMR_T *tmr, uint16_t eventSources)
 {
     tmr->CEG = eventSources;
 }
@@ -2041,7 +2041,7 @@ void TMR_GenerateEvent(TMR_T* tmr, uint16_t eventSources)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
  */
-uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag)
+uint16_t TMR_ReadStatusFlag(TMR_T *tmr, TMR_FLAG_T flag)
 {
     return (tmr->STS & flag) ? SET : RESET;
 }
@@ -2070,7 +2070,7 @@ uint16_t TMR_ReadStatusFlag(TMR_T* tmr, TMR_FLAG_T flag)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_FLAG_UPDATE.
  */
-void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag)
+void TMR_ClearStatusFlag(TMR_T *tmr, uint16_t flag)
 {
     tmr->STS = ~flag;
 }
@@ -2095,9 +2095,9 @@ void TMR_ClearStatusFlag(TMR_T* tmr, uint16_t flag)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag)
+uint16_t TMR_ReadIntFlag(TMR_T *tmr, TMR_INT_T flag)
 {
-    if (((tmr->STS & flag) != RESET ) && ((tmr->DIEN & flag) != RESET))
+    if (((tmr->STS & flag) != RESET) && ((tmr->DIEN & flag) != RESET))
     {
         return SET;
     }
@@ -2127,7 +2127,7 @@ uint16_t TMR_ReadIntFlag(TMR_T* tmr, TMR_INT_T flag)
  *
  * @note      TMR6 and TMR7 can only generate an TMR_INT_UPDATE.
  */
-void TMR_ClearIntFlag(TMR_T* tmr,  uint16_t flag)
+void TMR_ClearIntFlag(TMR_T *tmr,  uint16_t flag)
 {
     tmr->STS = ~flag;
 }
@@ -2145,7 +2145,7 @@ void TMR_ClearIntFlag(TMR_T* tmr,  uint16_t flag)
  *
  * @retval    None
  */
-static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI1Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 
@@ -2157,7 +2157,7 @@ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
     tmr->CCM1_CAPTURE_B.IC1F = ICfilter;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         tmr->CCEN_B.CC1POL = BIT_RESET;
         tmr->CCEN_B.CC1EN = BIT_SET;
@@ -2189,7 +2189,7 @@ static void TI1Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @retval    None
  */
-static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI2Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 
@@ -2201,7 +2201,7 @@ static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
     tmr->CCM1_CAPTURE_B.IC2F = ICfilter;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         tmr->CCEN_B.CC2POL = BIT_RESET;
         tmr->CCEN_B.CC2EN = BIT_SET;
@@ -2233,7 +2233,7 @@ static void TI2Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @retval    None
  */
-static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI3Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 
@@ -2245,7 +2245,7 @@ static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
     tmr->CCM2_CAPTURE_B.IC3F = ICfilter;
 
     if ((tmr == TMR1) || (tmr == TMR8) || (tmr == TMR2) || (tmr == TMR3) ||
-        (tmr == TMR4) || (tmr == TMR5))
+            (tmr == TMR4) || (tmr == TMR5))
     {
         tmr->CCEN_B.CC3POL = BIT_RESET;
         tmr->CCEN_B.CC3EN = BIT_SET;
@@ -2277,7 +2277,7 @@ static void TI3Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uin
  *
  * @retval    None
  */
-static void TI4Config(TMR_T* tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
+static void TI4Config(TMR_T *tmr, uint16_t ICpolarity, uint16_t ICselection, uint16_t ICfilter)
 {
     uint16_t tmpchctrl = 0;
 

bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/apm32f4xx_usart.c

@@ -47,7 +47,7 @@
  *
  * @retval    None
  */
-void USART_Reset(USART_T* usart)
+void USART_Reset(USART_T *usart)
 {
     if (USART1 == usart)
     {
@@ -102,7 +102,7 @@ void USART_Reset(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_Config(USART_T* usart, USART_Config_T* usartConfig)
+void USART_Config(USART_T *usart, USART_Config_T *usartConfig)
 {
     uint32_t temp, fCLK, intDiv, fractionalDiv;
 
@@ -159,7 +159,7 @@ void USART_Config(USART_T* usart, USART_Config_T* usartConfig)
  *
  * @retval    None
  */
-void USART_ConfigStructInit(USART_Config_T* usartConfig)
+void USART_ConfigStructInit(USART_Config_T *usartConfig)
 {
     usartConfig->baudRate = 9600;
     usartConfig->wordLength = USART_WORD_LEN_8B;
@@ -180,7 +180,7 @@ void USART_ConfigStructInit(USART_Config_T* usartConfig)
  *
  * @note      The usart can be USART1, USART2, USART3 and USART6
  */
-void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
+void USART_ConfigClock(USART_T *usart, USART_ClockConfig_T *clockConfig)
 {
     usart->CTRL2_B.CLKEN   = clockConfig->clock;
     usart->CTRL2_B.CPHA    = clockConfig->phase;
@@ -197,7 +197,7 @@ void USART_ConfigClock(USART_T* usart, USART_ClockConfig_T* clockConfig)
  *
  * @note
  */
-void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
+void USART_ConfigClockStructInit(USART_ClockConfig_T *clockConfig)
 {
     clockConfig->clock     = USART_CLKEN_DISABLE;
     clockConfig->phase     = USART_CLKPHA_1EDGE;
@@ -214,7 +214,7 @@ void USART_ConfigClockStructInit(USART_ClockConfig_T* clockConfig)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_Enable(USART_T* usart)
+void USART_Enable(USART_T *usart)
 {
     usart->CTRL1_B.UEN = BIT_SET;
 }
@@ -228,7 +228,7 @@ void USART_Enable(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_Disable(USART_T* usart)
+void USART_Disable(USART_T *usart)
 {
     usart->CTRL1_B.UEN = BIT_RESET;
 }
@@ -244,7 +244,7 @@ void USART_Disable(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
+void USART_ConfigPrescaler(USART_T *usart, uint8_t div)
 {
     usart->GTPSC_B.PSC = div;
 }
@@ -258,7 +258,7 @@ void USART_ConfigPrescaler(USART_T* usart, uint8_t div)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableOverSampling8(USART_T* usart)
+void USART_EnableOverSampling8(USART_T *usart)
 {
     usart->CTRL1_B.OSMCFG = BIT_SET;
 }
@@ -272,7 +272,7 @@ void USART_EnableOverSampling8(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableOverSampling8(USART_T* usart)
+void USART_DisableOverSampling8(USART_T *usart)
 {
     usart->CTRL1_B.OSMCFG = BIT_RESET;
 }
@@ -286,7 +286,7 @@ void USART_DisableOverSampling8(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableOverSampling(USART_T* usart)
+void USART_EnableOverSampling(USART_T *usart)
 {
     usart->CTRL3_B.SAMCFG = BIT_SET;
 }
@@ -300,7 +300,7 @@ void USART_EnableOverSampling(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableOverSampling(USART_T* usart)
+void USART_DisableOverSampling(USART_T *usart)
 {
     usart->CTRL3_B.SAMCFG = BIT_RESET;
 }
@@ -316,7 +316,7 @@ void USART_DisableOverSampling(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_TxData(USART_T* usart, uint16_t data)
+void USART_TxData(USART_T *usart, uint16_t data)
 {
     usart->DATA_B.DATA = data;
 }
@@ -330,7 +330,7 @@ void USART_TxData(USART_T* usart, uint16_t data)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-uint16_t USART_RxData(USART_T* usart)
+uint16_t USART_RxData(USART_T *usart)
 {
     return (uint16_t)(usart->DATA_B.DATA);
 }
@@ -346,7 +346,7 @@ uint16_t USART_RxData(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_Address(USART_T* usart, uint8_t address)
+void USART_Address(USART_T *usart, uint8_t address)
 {
     usart->CTRL2_B.ADDR = address;
 }
@@ -360,7 +360,7 @@ void USART_Address(USART_T* usart, uint8_t address)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableMuteMode(USART_T* usart)
+void USART_EnableMuteMode(USART_T *usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_SET;
 }
@@ -374,7 +374,7 @@ void USART_EnableMuteMode(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableMuteMode(USART_T* usart)
+void USART_DisableMuteMode(USART_T *usart)
 {
     usart->CTRL1_B.RXMUTEEN = BIT_RESET;
 }
@@ -393,7 +393,7 @@ void USART_DisableMuteMode(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
+void USART_ConfigWakeUp(USART_T *usart, USART_WAKEUP_T wakeup)
 {
     usart->CTRL1_B.WUPMCFG = wakeup;
 }
@@ -412,7 +412,7 @@ void USART_ConfigWakeUp(USART_T* usart, USART_WAKEUP_T wakeup)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
+void USART_ConfigLINBreakDetectLength(USART_T *usart, USART_LBDL_T length)
 {
     usart->CTRL2_B.LBDLCFG = length;
 }
@@ -426,7 +426,7 @@ void USART_ConfigLINBreakDetectLength(USART_T* usart, USART_LBDL_T length)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableLIN(USART_T* usart)
+void USART_EnableLIN(USART_T *usart)
 {
     usart->CTRL2_B.LINMEN = BIT_SET;
 }
@@ -440,7 +440,7 @@ void USART_EnableLIN(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableLIN(USART_T* usart)
+void USART_DisableLIN(USART_T *usart)
 {
     usart->CTRL2_B.LINMEN = BIT_RESET;
 }
@@ -454,7 +454,7 @@ void USART_DisableLIN(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_TxBreak(USART_T* usart)
+void USART_TxBreak(USART_T *usart)
 {
     usart->CTRL1_B.TXBF = BIT_SET;
 }
@@ -468,7 +468,7 @@ void USART_TxBreak(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableHalfDuplex(USART_T* usart)
+void USART_EnableHalfDuplex(USART_T *usart)
 {
     usart->CTRL3_B.HDEN = BIT_SET;
 }
@@ -482,7 +482,7 @@ void USART_EnableHalfDuplex(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableHalfDuplex(USART_T* usart)
+void USART_DisableHalfDuplex(USART_T *usart)
 {
     usart->CTRL3_B.HDEN = BIT_RESET;
 }
@@ -498,7 +498,7 @@ void USART_DisableHalfDuplex(USART_T* usart)
  *
  * @note      The specified USART guard time is not available for UART4 and UART5
  */
-void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
+void USART_ConfigGuardTime(USART_T *usart, uint8_t guardTime)
 {
     usart->GTPSC_B.GRDT = guardTime;
 }
@@ -512,7 +512,7 @@ void USART_ConfigGuardTime(USART_T* usart, uint8_t guardTime)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCard(USART_T* usart)
+void USART_EnableSmartCard(USART_T *usart)
 {
     usart->CTRL3_B.SCEN = BIT_SET;
 }
@@ -526,7 +526,7 @@ void USART_EnableSmartCard(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCard(USART_T* usart)
+void USART_DisableSmartCard(USART_T *usart)
 {
     usart->CTRL3_B.SCEN = BIT_RESET;
 }
@@ -540,7 +540,7 @@ void USART_DisableSmartCard(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_EnableSmartCardNACK(USART_T* usart)
+void USART_EnableSmartCardNACK(USART_T *usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_SET;
 }
@@ -554,7 +554,7 @@ void USART_EnableSmartCardNACK(USART_T* usart)
  *
  * @note      The Smart Card mode is not available for UART4 and UART5
  */
-void USART_DisableSmartCardNACK(USART_T* usart)
+void USART_DisableSmartCardNACK(USART_T *usart)
 {
     usart->CTRL3_B.SCNACKEN = BIT_RESET;
 }
@@ -572,7 +572,7 @@ void USART_DisableSmartCardNACK(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
+void USART_ConfigIrDA(USART_T *usart, USART_IRDALP_T IrDAMode)
 {
     usart->CTRL3_B.IRLPEN = IrDAMode;
 }
@@ -586,7 +586,7 @@ void USART_ConfigIrDA(USART_T* usart, USART_IRDALP_T IrDAMode)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableIrDA(USART_T* usart)
+void USART_EnableIrDA(USART_T *usart)
 {
     usart->CTRL3_B.IREN = BIT_SET;
 }
@@ -600,7 +600,7 @@ void USART_EnableIrDA(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableIrDA(USART_T* usart)
+void USART_DisableIrDA(USART_T *usart)
 {
     usart->CTRL3_B.IREN = BIT_RESET;
 }
@@ -620,7 +620,7 @@ void USART_DisableIrDA(USART_T* usart)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
+void USART_EnableDMA(USART_T *usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3_B.DMARXEN = dmaReq & 0x01;
     usart->CTRL3_B.DMATXEN = dmaReq >> 1;
@@ -641,7 +641,7 @@ void USART_EnableDMA(USART_T* usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
+void USART_DisableDMA(USART_T *usart, USART_DMA_T dmaReq)
 {
     usart->CTRL3_B.DMARXEN = !(dmaReq & 0x01);
     usart->CTRL3_B.DMATXEN = !(dmaReq >> 1);
@@ -667,7 +667,7 @@ void USART_DisableDMA(USART_T* usart, USART_DMA_T dmaReq)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
+void USART_EnableInterrupt(USART_T *usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
@@ -709,7 +709,7 @@ void USART_EnableInterrupt(USART_T* usart, USART_INT_T interrupt)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
+void USART_DisableInterrupt(USART_T *usart, USART_INT_T interrupt)
 {
     uint32_t temp;
 
@@ -753,7 +753,7 @@ void USART_DisableInterrupt(USART_T* usart, USART_INT_T interrupt)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
+uint8_t USART_ReadStatusFlag(USART_T *usart, USART_FLAG_T flag)
 {
     return (usart->STS & flag) ? SET : RESET;
 }
@@ -774,7 +774,7 @@ uint8_t USART_ReadStatusFlag(USART_T* usart, USART_FLAG_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
+void USART_ClearStatusFlag(USART_T *usart, USART_FLAG_T flag)
 {
     usart->STS &= (uint32_t)~flag;
 }
@@ -802,7 +802,7 @@ void USART_ClearStatusFlag(USART_T* usart, USART_FLAG_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
+uint8_t USART_ReadIntFlag(USART_T *usart, USART_INT_T flag)
 {
     uint32_t itFlag, srFlag;
 
@@ -847,7 +847,7 @@ uint8_t USART_ReadIntFlag(USART_T* usart, USART_INT_T flag)
  *
  * @note      The usart can be USART1, USART2, USART3, UART4, UART5, USART6, UART7 and UART8
  */
-void USART_ClearIntFlag(USART_T* usart, USART_INT_T flag)
+void USART_ClearIntFlag(USART_T *usart, USART_INT_T flag)
 {
     uint32_t srFlag;
 

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/ComputeLibrary/Include/NEMath.h

@@ -1,414 +0,0 @@
-/*
- * Copyright (c) 2016, 2019 ARM Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef __ARM_COMPUTE_NEMATH_H__
-#define __ARM_COMPUTE_NEMATH_H__
-
-
-#if defined(ARM_MATH_NEON)
-/** Calculate floor of a vector.
- *
- * @param[in] val Input vector value in F32 format.
- *
- * @return The calculated floor vector.
- */
-static inline float32x4_t vfloorq_f32(float32x4_t val);
-
-/** Calculate inverse square root.
- *
- * @param[in] x Input value.
- *
- * @return The calculated inverse square root.
- */
-static inline float32x2_t vinvsqrt_f32(float32x2_t x);
-
-/** Calculate inverse square root.
- *
- * @param[in] x Input value.
- *
- * @return The calculated inverse square root.
- */
-static inline float32x4_t vinvsqrtq_f32(float32x4_t x);
-
-/** Calculate reciprocal.
- *
- * @param[in] x Input value.
- *
- * @return The calculated reciprocal.
- */
-static inline float32x2_t vinv_f32(float32x2_t x);
-
-/** Calculate reciprocal.
- *
- * @param[in] x Input value.
- *
- * @return The calculated reciprocal.
- */
-static inline float32x4_t vinvq_f32(float32x4_t x);
-
-/** Perform a 7th degree polynomial approximation using Estrin's method.
- *
- * @param[in] x      Input vector value in F32 format.
- * @param[in] coeffs Polynomial coefficients table. (array of flattened float32x4_t vectors)
- *
- * @return The calculated approximation.
- */
-static inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs);
-
-/** Calculate exponential
- *
- * @param[in] x Input vector value in F32 format.
- *
- * @return The calculated exponent.
- */
-static inline float32x4_t vexpq_f32(float32x4_t x);
-
-/** Calculate logarithm
- *
- * @param[in] x Input vector value in F32 format.
- *
- * @return The calculated logarithm.
- */
-static inline float32x4_t vlogq_f32(float32x4_t x);
-
-/** Calculate hyperbolic tangent.
- *
- * tanh(x) = (e^2x - 1)/(e^2x + 1)
- *
- * @note We clamp x to [-5,5] to avoid overflowing issues.
- *
- * @param[in] val Input vector value in F32 format.
- *
- * @return The calculated Hyperbolic Tangent.
- */
-static inline float32x4_t vtanhq_f32(float32x4_t val);
-
-/** Calculate n power of a number.
- *
- * pow(x,n) = e^(n*log(x))
- *
- * @param[in] val Input vector value in F32 format.
- * @param[in] n   Powers to raise the input to.
- *
- * @return The calculated power.
- */
-static inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n);
-
-#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
-/** Calculate hyperbolic tangent.
- *
- * tanh(x) = (e^2x - 1)/(e^2x + 1)
- *
- * @note We clamp x to [-5,5] to avoid overflowing issues.
- *
- * @param[in] val Input vector value in F32 format.
- *
- * @return The calculated Hyperbolic Tangent.
- */
-static inline float16x8_t vtanhq_f16(float16x8_t val);
-
-/** Calculate reciprocal.
- *
- * @param[in] x Input value.
- *
- * @return The calculated reciprocal.
- */
-static inline float16x4_t vinv_f16(float16x4_t x);
-
-/** Calculate reciprocal.
- *
- * @param[in] x Input value.
- *
- * @return The calculated reciprocal.
- */
-static inline float16x8_t vinvq_f16(float16x8_t x);
-
-/** Calculate inverse square root.
- *
- * @param[in] x Input value.
- *
- * @return The calculated inverse square root.
- */
-static inline float16x4_t vinvsqrt_f16(float16x4_t x);
-
-/** Calculate inverse square root.
- *
- * @param[in] x Input value.
- *
- * @return The calculated inverse square root.
- */
-static inline float16x8_t vinvsqrtq_f16(float16x8_t x);
-
-/** Calculate exponential
- *
- * @param[in] x Input vector value in F16 format.
- *
- * @return The calculated exponent.
- */
-static inline float16x8_t vexpq_f16(float16x8_t x);
-
-/** Calculate n power of a number.
- *
- * pow(x,n) = e^(n*log(x))
- *
- * @param[in] val Input vector value in F16 format.
- * @param[in] n   Powers to raise the input to.
- *
- * @return The calculated power.
- */
-static inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n);
-#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
-
-/** Exponent polynomial coefficients */
-extern const float32_t exp_tab[4*8];
-
-
-/** Logarithm polynomial coefficients */
-extern const float32_t log_tab[4*8];
-
-#ifndef DOXYGEN_SKIP_THIS
-inline float32x4_t vfloorq_f32(float32x4_t val)
-{
-    static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f};
-
-    const int32x4_t   z = vcvtq_s32_f32(val);
-    const float32x4_t r = vcvtq_f32_s32(z);
-
-    return vbslq_f32(vcgtq_f32(r, val), vsubq_f32(r, vld1q_f32(CONST_1)), r);
-}
-
-inline float32x2_t vinvsqrt_f32(float32x2_t x)
-{
-    float32x2_t sqrt_reciprocal = vrsqrte_f32(x);
-    sqrt_reciprocal             = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-    sqrt_reciprocal             = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-
-    return sqrt_reciprocal;
-}
-
-inline float32x4_t vinvsqrtq_f32(float32x4_t x)
-{
-    float32x4_t sqrt_reciprocal = vrsqrteq_f32(x);
-    sqrt_reciprocal             = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-    sqrt_reciprocal             = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-
-    return sqrt_reciprocal;
-}
-
-inline float32x2_t vinv_f32(float32x2_t x)
-{
-    float32x2_t recip = vrecpe_f32(x);
-    recip             = vmul_f32(vrecps_f32(x, recip), recip);
-    recip             = vmul_f32(vrecps_f32(x, recip), recip);
-    return recip;
-}
-
-inline float32x4_t vinvq_f32(float32x4_t x)
-{
-    float32x4_t recip = vrecpeq_f32(x);
-    recip             = vmulq_f32(vrecpsq_f32(x, recip), recip);
-    recip             = vmulq_f32(vrecpsq_f32(x, recip), recip);
-    return recip;
-}
-
-inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs)
-{
-    float32x4_t A   = vmlaq_f32(vld1q_f32(&coeffs[4*0]), vld1q_f32(&coeffs[4*4]), x);
-    float32x4_t B   = vmlaq_f32(vld1q_f32(&coeffs[4*2]), vld1q_f32(&coeffs[4*6]), x);
-    float32x4_t C   = vmlaq_f32(vld1q_f32(&coeffs[4*1]), vld1q_f32(&coeffs[4*5]), x);
-    float32x4_t D   = vmlaq_f32(vld1q_f32(&coeffs[4*3]), vld1q_f32(&coeffs[4*7]), x);
-    float32x4_t x2  = vmulq_f32(x, x);
-    float32x4_t x4  = vmulq_f32(x2, x2);
-    float32x4_t res = vmlaq_f32(vmlaq_f32(A, B, x2), vmlaq_f32(C, D, x2), x4);
-    return res;
-}
-
-inline float32x4_t vexpq_f32(float32x4_t x)
-{
-    static const float32_t CONST_LN2[4]          = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2)
-    static const float32_t CONST_INV_LN2[4]      = {1.4426950408f,1.4426950408f,1.4426950408f,1.4426950408f}; // 1/ln(2)
-    static const float32_t CONST_0[4]            = {0.f,0.f,0.f,0.f};
-    static const int32_t   CONST_NEGATIVE_126[4] = {-126,-126,-126,-126};
-
-    // Perform range reduction [-log(2),log(2)]
-    int32x4_t   m   = vcvtq_s32_f32(vmulq_f32(x, vld1q_f32(CONST_INV_LN2)));
-    float32x4_t val = vmlsq_f32(x, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2));
-
-    // Polynomial Approximation
-    float32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
-
-    // Reconstruct
-    poly = vreinterpretq_f32_s32(vqaddq_s32(vreinterpretq_s32_f32(poly), vqshlq_n_s32(m, 23)));
-    poly = vbslq_f32(vcltq_s32(m, vld1q_s32(CONST_NEGATIVE_126)), vld1q_f32(CONST_0), poly);
-
-    return poly;
-}
-
-inline float32x4_t vlogq_f32(float32x4_t x)
-{
-    static const int32_t   CONST_127[4] = {127,127,127,127};           // 127
-    static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2)
-
-    // Extract exponent
-    int32x4_t   m   = vsubq_s32(vreinterpretq_s32_u32(vshrq_n_u32(vreinterpretq_u32_f32(x), 23)), vld1q_s32(CONST_127));
-    float32x4_t val = vreinterpretq_f32_s32(vsubq_s32(vreinterpretq_s32_f32(x), vshlq_n_s32(m, 23)));
-
-    // Polynomial Approximation
-    float32x4_t poly = vtaylor_polyq_f32(val, log_tab);
-
-    // Reconstruct
-    poly = vmlaq_f32(poly, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2));
-
-    return poly;
-}
-
-inline float32x4_t vtanhq_f32(float32x4_t val)
-{
-    static const float32_t CONST_1[4]        = {1.f,1.f,1.f,1.f};
-    static const float32_t CONST_2[4]        = {2.f,2.f,2.f,2.f};
-    static const float32_t CONST_MIN_TANH[4] = {-10.f,-10.f,-10.f,-10.f};
-    static const float32_t CONST_MAX_TANH[4] = {10.f,10.f,10.f,10.f};
-
-    float32x4_t x     = vminq_f32(vmaxq_f32(val, vld1q_f32(CONST_MIN_TANH)), vld1q_f32(CONST_MAX_TANH));
-    float32x4_t exp2x = vexpq_f32(vmulq_f32(vld1q_f32(CONST_2), x));
-    float32x4_t num   = vsubq_f32(exp2x, vld1q_f32(CONST_1));
-    float32x4_t den   = vaddq_f32(exp2x, vld1q_f32(CONST_1));
-    float32x4_t tanh  = vmulq_f32(num, vinvq_f32(den));
-    return tanh;
-}
-
-inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n)
-{
-    return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
-}
-#endif /* DOXYGEN_SKIP_THIS */
-
-#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
-/** Exponent polynomial coefficients */
-/** Logarithm polynomial coefficients */
-#ifndef DOXYGEN_SKIP_THIS
-inline float16x8_t vfloorq_f16(float16x8_t val)
-{
-    static const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f};
-
-    const int16x8_t   z = vcvtq_s16_f16(val);
-    const float16x8_t r = vcvtq_f16_s16(z);
-
-    return vbslq_f16(vcgtq_f16(r, val), vsubq_f16(r, vld1q_f16(CONST_1)), r);
-}
-inline float16x4_t vinvsqrt_f16(float16x4_t x)
-{
-    float16x4_t sqrt_reciprocal = vrsqrte_f16(x);
-    sqrt_reciprocal             = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-    sqrt_reciprocal             = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-    return sqrt_reciprocal;
-}
-
-inline float16x8_t vinvsqrtq_f16(float16x8_t x)
-{
-    float16x8_t sqrt_reciprocal = vrsqrteq_f16(x);
-    sqrt_reciprocal             = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-    sqrt_reciprocal             = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal);
-    return sqrt_reciprocal;
-}
-
-inline float16x4_t vinv_f16(float16x4_t x)
-{
-    float16x4_t recip = vrecpe_f16(x);
-    recip             = vmul_f16(vrecps_f16(x, recip), recip);
-    recip             = vmul_f16(vrecps_f16(x, recip), recip);
-    return recip;
-}
-
-inline float16x8_t vinvq_f16(float16x8_t x)
-{
-    float16x8_t recip = vrecpeq_f16(x);
-    recip             = vmulq_f16(vrecpsq_f16(x, recip), recip);
-    recip             = vmulq_f16(vrecpsq_f16(x, recip), recip);
-    return recip;
-}
-
-inline float16x8_t vtanhq_f16(float16x8_t val)
-{
-    const float16_t CONST_1[8]        = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f};
-    const float16_t CONST_2[8]        = {2.f,2.f,2.f,2.f,2.f,2.f,2.f,2.f};
-    const float16_t CONST_MIN_TANH[8] = {-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f};
-    const float16_t CONST_MAX_TANH[8] = {10.f,10.f,10.f,10.f,10.f,10.f,10.f,10.f};
-
-    const float16x8_t x     = vminq_f16(vmaxq_f16(val, vld1q_f16(CONST_MIN_TANH)), vld1q_f16(CONST_MAX_TANH));
-    const float16x8_t exp2x = vexpq_f16(vmulq_f16(vld1q_f16(CONST_2), x));
-    const float16x8_t num   = vsubq_f16(exp2x, vld1q_f16(CONST_1));
-    const float16x8_t den   = vaddq_f16(exp2x, vld1q_f16(CONST_1));
-    const float16x8_t tanh  = vmulq_f16(num, vinvq_f16(den));
-    return tanh;
-}
-
-inline float16x8_t vtaylor_polyq_f16(float16x8_t x, const float16_t *coeffs)
-{
-    const float16x8_t A   = vaddq_f16(vld1q_f16(&coeffs[8*0]), vmulq_f16(vld1q_f16(&coeffs[8*4]), x));
-    const float16x8_t B   = vaddq_f16(vld1q_f16(&coeffs[8*2]), vmulq_f16(vld1q_f16(&coeffs[8*6]), x));
-    const float16x8_t C   = vaddq_f16(vld1q_f16(&coeffs[8*1]), vmulq_f16(vld1q_f16(&coeffs[8*5]), x));
-    const float16x8_t D   = vaddq_f16(vld1q_f16(&coeffs[8*3]), vmulq_f16(vld1q_f16(&coeffs[8*7]), x));
-    const float16x8_t x2  = vmulq_f16(x, x);
-    const float16x8_t x4  = vmulq_f16(x2, x2);
-    const float16x8_t res = vaddq_f16(vaddq_f16(A, vmulq_f16(B, x2)), vmulq_f16(vaddq_f16(C, vmulq_f16(D, x2)), x4));
-    return res;
-}
-
-inline float16x8_t vexpq_f16(float16x8_t x)
-{
-    // TODO (COMPMID-1535) : Revisit FP16 approximations
-    const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x));
-    const float32x4_t x_low  = vcvt_f32_f16(vget_low_f16(x));
-
-    const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vexpq_f32(x_low)), vexpq_f32(x_high));
-    return res;
-}
-
-inline float16x8_t vlogq_f16(float16x8_t x)
-{
-    // TODO (COMPMID-1535) : Revisit FP16 approximations
-    const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x));
-    const float32x4_t x_low  = vcvt_f32_f16(vget_low_f16(x));
-
-    const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vlogq_f32(x_low)), vlogq_f32(x_high));
-    return res;
-}
-
-inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n)
-{
-    // TODO (giaiod01) - COMPMID-1535
-    float32x4_t n0_f32   = vcvt_f32_f16(vget_low_f16(n));
-    float32x4_t n1_f32   = vcvt_f32_f16(vget_high_f16(n));
-    float32x4_t val0_f32 = vcvt_f32_f16(vget_low_f16(val));
-    float32x4_t val1_f32 = vcvt_f32_f16(vget_high_f16(val));
-
-    float32x4_t res0_f32 = vexpq_f32(vmulq_f32(n0_f32, vlogq_f32(val0_f32)));
-    float32x4_t res1_f32 = vexpq_f32(vmulq_f32(n1_f32, vlogq_f32(val1_f32)));
-
-    return vcombine_f16(vcvt_f16_f32(res0_f32), vcvt_f16_f32(res1_f32));
-}
-#endif /* DOXYGEN_SKIP_THIS */
-#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */
-#endif
-#endif /* __ARM_COMPUTE_NEMATH_H__ */

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/ComputeLibrary/LICENSE.txt

@@ -1,21 +0,0 @@
-MIT License
-
-Copyright (c) 2017-2019 ARM Software
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/ComputeLibrary/README.md

@@ -1,19 +0,0 @@
-README
-======
-
-This folder is containing two files imported, and slightly modified, from the ComputeLibrary:
-
-    NEMath.h and arm_cl_tables.c 
-
-In the original compute library, there are instead two other files:
-
-    NEMath.h and NEMath.inl
-
-NEMath.inl is included from NEMath.h whereas in this CMSIS DSP implementation, there is no NEMath.inl and its content is copied into NEMath.h
-
-The tables contained in NEMath.inl have been moved to arm_cl_tables.c and finally the files are in C for the CMSIS DSP library and in C++ in the original Compute Library.
-
-Otherwise, the features and implementations are the same : a few optimized Neon functions.
-
-The license covering those files is different : It is a MIT license.
-Other parts of the CMSIS-DSP are covered with an Apache-2.0 license.

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c

@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016, 2019 ARM Limited.
- *
- * SPDX-License-Identifier: MIT
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#include "arm_math.h"
-#include "NEMath.h"
-
-#if defined(ARM_MATH_NEON)
-
-/** Exponent polynomial coefficients */
-const float32_t exp_tab[4*8] =
-{
-        1.f,1.f,1.f,1.f,
-        0.0416598916054f,0.0416598916054f,0.0416598916054f,0.0416598916054f,
-        0.500000596046f,0.500000596046f,0.500000596046f,0.500000596046f,
-        0.0014122662833f,0.0014122662833f,0.0014122662833f,0.0014122662833f,
-        1.00000011921f,1.00000011921f,1.00000011921f,1.00000011921f,
-        0.00833693705499f,0.00833693705499f,0.00833693705499f,0.00833693705499f,
-        0.166665703058f,0.166665703058f,0.166665703058f,0.166665703058f,
-        0.000195780929062f,0.000195780929062f,0.000195780929062f,0.000195780929062f
-};
-
-/** Logarithm polynomial coefficients */
-const float32_t log_tab[4*8] =
-{
-        -2.29561495781f,-2.29561495781f,-2.29561495781f,-2.29561495781f,
-        -2.47071170807f,-2.47071170807f,-2.47071170807f,-2.47071170807f,
-        -5.68692588806f,-5.68692588806f,-5.68692588806f,-5.68692588806f,
-        -0.165253549814f,-0.165253549814f,-0.165253549814f,-0.165253549814f,
-        5.17591238022f,5.17591238022f,5.17591238022f,5.17591238022f,
-        0.844007015228f,0.844007015228f,0.844007015228f,0.844007015228f,
-        4.58445882797f,4.58445882797f,4.58445882797f,4.58445882797f,
-        0.0141278216615f,0.0141278216615f,0.0141278216615f,0.0141278216615f
-};
-
-#endif

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_common_tables.h

@@ -1,529 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math_types.h"
-#include "dsp/fast_math_functions.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-  /* Double Precision Float CFFT twiddles */
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
-    extern const uint16_t armBitRevTable[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
-    extern const uint64_t twiddleCoefF64_16[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
-    extern const uint64_t twiddleCoefF64_32[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
-    extern const uint64_t twiddleCoefF64_64[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
-    extern const uint64_t twiddleCoefF64_128[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
-    extern const uint64_t twiddleCoefF64_256[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
-    extern const uint64_t twiddleCoefF64_512[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
-    extern const uint64_t twiddleCoefF64_1024[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
-    extern const uint64_t twiddleCoefF64_2048[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
-    extern const uint64_t twiddleCoefF64_4096[8192];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
-    extern const float32_t twiddleCoef_16[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
-    extern const float32_t twiddleCoef_32[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
-    extern const float32_t twiddleCoef_64[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
-    extern const float32_t twiddleCoef_128[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
-    extern const float32_t twiddleCoef_256[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
-    extern const float32_t twiddleCoef_512[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
-    extern const float32_t twiddleCoef_1024[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
-    extern const float32_t twiddleCoef_2048[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
-    extern const float32_t twiddleCoef_4096[8192];
-    #define twiddleCoef twiddleCoef_4096
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  /* Q31 */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
-    extern const q31_t twiddleCoef_16_q31[24];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
-    extern const q31_t twiddleCoef_32_q31[48];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
-    extern const q31_t twiddleCoef_64_q31[96];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
-    extern const q31_t twiddleCoef_128_q31[192];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
-    extern const q31_t twiddleCoef_256_q31[384];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
-    extern const q31_t twiddleCoef_512_q31[768];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
-    extern const q31_t twiddleCoef_1024_q31[1536];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
-    extern const q31_t twiddleCoef_2048_q31[3072];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
-    extern const q31_t twiddleCoef_4096_q31[6144];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
-    extern const q15_t twiddleCoef_16_q15[24];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
-    extern const q15_t twiddleCoef_32_q15[48];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
-    extern const q15_t twiddleCoef_64_q15[96];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
-    extern const q15_t twiddleCoef_128_q15[192];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
-    extern const q15_t twiddleCoef_256_q15[384];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
-    extern const q15_t twiddleCoef_512_q15[768];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
-    extern const q15_t twiddleCoef_1024_q15[1536];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
-    extern const q15_t twiddleCoef_2048_q15[3072];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
-    extern const q15_t twiddleCoef_4096_q15[6144];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  /* Double Precision Float RFFT twiddles */
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
-    extern const uint64_t twiddleCoefF64_rfft_32[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
-    extern const uint64_t twiddleCoefF64_rfft_64[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
-    extern const uint64_t twiddleCoefF64_rfft_128[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
-    extern const uint64_t twiddleCoefF64_rfft_256[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
-    extern const uint64_t twiddleCoefF64_rfft_512[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
-    extern const uint64_t twiddleCoefF64_rfft_1024[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
-    extern const uint64_t twiddleCoefF64_rfft_2048[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
-    extern const uint64_t twiddleCoefF64_rfft_4096[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
-    extern const float32_t twiddleCoef_rfft_32[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
-    extern const float32_t twiddleCoef_rfft_64[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
-    extern const float32_t twiddleCoef_rfft_128[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
-    extern const float32_t twiddleCoef_rfft_256[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
-    extern const float32_t twiddleCoef_rfft_512[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
-    extern const float32_t twiddleCoef_rfft_1024[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
-    extern const float32_t twiddleCoef_rfft_2048[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
-    extern const float32_t twiddleCoef_rfft_4096[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  /* Double precision floating-point bit reversal tables */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
-    #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
-    extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
-    #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
-    extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
-    #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
-    #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
-    extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
-    #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
-    extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
-    #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
-    extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
-    #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
-    extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
-    #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
-    extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
-    #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-  /* floating-point bit reversal tables */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
-    #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-    extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
-    #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-    extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
-    #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
-    #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-    extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
-    #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-    extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
-    #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-    extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
-    #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-    extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
-    #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-    extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
-    #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  /* fixed-point bit reversal tables */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
-    #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-    extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
-    #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-    extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
-    #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-    extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
-    #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-    extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
-    #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-    extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
-    #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-    extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
-    #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-    extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
-    #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-    extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
-    #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-    extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
-    extern const float32_t realCoefA[8192];
-    extern const float32_t realCoefB[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
-    extern const q31_t realCoefAQ31[8192];
-    extern const q31_t realCoefBQ31[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
-    extern const q15_t realCoefAQ15[8192];
-    extern const q15_t realCoefBQ15[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
-    extern const float32_t Weights_128[256];
-    extern const float32_t cos_factors_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
-    extern const float32_t Weights_512[1024];
-    extern const float32_t cos_factors_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
-    extern const float32_t Weights_2048[4096];
-    extern const float32_t cos_factors_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
-    extern const float32_t Weights_8192[16384];
-    extern const float32_t cos_factors_8192[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
-    extern const q15_t WeightsQ15_128[256];
-    extern const q15_t cos_factorsQ15_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
-    extern const q15_t WeightsQ15_512[1024];
-    extern const q15_t cos_factorsQ15_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
-    extern const q15_t WeightsQ15_2048[4096];
-    extern const q15_t cos_factorsQ15_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
-    extern const q15_t WeightsQ15_8192[16384];
-    extern const q15_t cos_factorsQ15_8192[8192];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
-    extern const q31_t WeightsQ31_128[256];
-    extern const q31_t cos_factorsQ31_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
-    extern const q31_t WeightsQ31_512[1024];
-    extern const q31_t cos_factorsQ31_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
-    extern const q31_t WeightsQ31_2048[4096];
-    extern const q31_t cos_factorsQ31_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
-    extern const q31_t WeightsQ31_8192[16384];
-    extern const q31_t cos_factorsQ31_8192[8192];
-  #endif
-
-#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
-    extern const q15_t armRecipTableQ15[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
-    extern const q31_t armRecipTableQ31[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  /* Tables for Fast Math Sine and Cosine */
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
-    extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
-    extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
-    extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-
-  #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
-     #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
-       extern const q31_t sqrtTable_Q31[256];
-     #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-  #endif
-
-  #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
-     #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
-       extern const q15_t sqrtTable_Q15[256];
-     #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
-  #endif
-
-#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
-
-#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
-       extern const float32_t exp_tab[8];
-       extern const float32_t __logf_lut_f32[8];
-#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
-
-#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
-extern const unsigned char hwLUT[256];
-#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /*  ARM_COMMON_TABLES_H */
-

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_common_tables_f16.h

@@ -1,132 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables_f16.h
- * Description:  Extern declaration for common tables
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_F16_H
-#define _ARM_COMMON_TABLES_F16_H
-
-#include "arm_math_types_f16.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-  /* F16 */
-  #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16)
-    extern const float16_t twiddleCoefF16_16[32];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
-    extern const float16_t twiddleCoefF16_32[64];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64)
-    extern const float16_t twiddleCoefF16_64[128];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
-    extern const float16_t twiddleCoefF16_128[256];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256)
-    extern const float16_t twiddleCoefF16_256[512];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
-    extern const float16_t twiddleCoefF16_512[1024];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024)
-    extern const float16_t twiddleCoefF16_1024[2048];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
-    extern const float16_t twiddleCoefF16_2048[4096];
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096)
-    extern const float16_t twiddleCoefF16_4096[8192];
-    #define twiddleCoefF16 twiddleCoefF16_4096
-  #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
-
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)
-  extern const float16_t twiddleCoefF16_rfft_32[32];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)
-  extern const float16_t twiddleCoefF16_rfft_64[64];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)
-  extern const float16_t twiddleCoefF16_rfft_128[128];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)
-  extern const float16_t twiddleCoefF16_rfft_256[256];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)
-  extern const float16_t twiddleCoefF16_rfft_512[512];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)
-  extern const float16_t twiddleCoefF16_rfft_1024[1024];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)
-  extern const float16_t twiddleCoefF16_rfft_2048[2048];
-  #endif
-
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)
-  extern const float16_t twiddleCoefF16_rfft_4096[4096];
-  #endif
-
-  #endif /* ARMAC5 */
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
-
-#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
-       extern const float16_t exp_tab_f16[8];
-       extern const float16_t __logf_lut_f16[8];
-#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /*  _ARM_COMMON_TABLES_F16_H */
-
-

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_const_structs.h

@@ -1,86 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math_types.h"
-#include "arm_common_tables.h"
-#include "dsp/transform_functions.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
-   extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif
-

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_const_structs_f16.h

@@ -1,77 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs_f16.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f16() function.
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_F16_H
-#define _ARM_CONST_STRUCTS_F16_H
-
-#include "arm_math_types_f16.h"
-#include "arm_common_tables.h"
-#include "arm_common_tables_f16.h"
-#include "dsp/transform_functions_f16.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16;
-   #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048;
-    #endif
-  #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096))
-   extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096;
-  #endif
-#endif
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_helium_utils.h

@@ -1,753 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_helium_utils.h
- * Description:  Utility functions for Helium development
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_UTILS_HELIUM_H_
-#define _ARM_UTILS_HELIUM_H_
-
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-/***************************************
-
-Definitions available for MVEF and MVEI
-
-***************************************/
-#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI))  && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#define INACTIVELANE            0 /* inactive lane content */
-
-
-#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
-
-/***************************************
-
-Definitions available for MVEF only
-
-***************************************/
-#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF))  && !defined(ARM_MATH_AUTOVECTORIZE)
-
-__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
-{
-    float32_t acc;
-
-    acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
-          vgetq_lane(in, 2) + vgetq_lane(in, 3);
-
-    return acc;
-}
-
-
-
-
-/* newton initial guess */
-#define INVSQRT_MAGIC_F32           0x5f3759df
-#define INV_NEWTON_INIT_F32         0x7EF127EA
-
-
-#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
-{                                                     \
-    float32x4_t tmp;                                  \
-                                                      \
-    /* tmp = xhalf * x * x */                         \
-    tmp = vmulq(xStart, xStart);                      \
-    tmp = vmulq(tmp, xHalf);                          \
-    /* (1.5f - xhalf * x * x) */                      \
-    tmp = vsubq(vdupq_n_f32(1.5f), tmp);              \
-    /* x = x*(1.5f-xhalf*x*x); */                     \
-    invSqrt = vmulq(tmp, xStart);                     \
-}
-#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
-
-
-/***************************************
-
-Definitions available for f16 datatype with HW acceleration only
-
-***************************************/
-#if defined(ARM_FLOAT16_SUPPORTED)
-#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
-
-__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
-{
-    float16x8_t tmpVec;
-    _Float16 acc;
-
-    tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in);
-    in = vaddq_f16(tmpVec, in);
-    tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in);
-    in = vaddq_f16(tmpVec, in);
-    acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4);
-
-    return acc;
-}
-
-__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
-    float16x8_t   vecIn)
-{
-    float16x8_t   vecTmp, vecOut;
-    uint32_t    tmp;
-
-    vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn);
-    // TO TRACK : using canonical addition leads to unefficient code generation for f16
-    // vecTmp = vecTmp + vecAccCpx0;
-    /*
-     * Compute
-     *  re0+re1 | im0+im1 | re0+re1 | im0+im1
-     *  re2+re3 | im2+im3 | re2+re3 | im2+im3
-     */
-    vecTmp = vaddq_f16(vecTmp, vecIn);
-    vecOut = vecTmp;
-    /*
-     * shift left, random tmp insertion in bottom
-     */
-    vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut)   , &tmp, 32));
-    /*
-     * Compute:
-     *    DONTCARE     |    DONTCARE     | re0+re1+re0+re1 |im0+im1+im0+im1
-     * re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3
-     */
-    vecOut = vaddq_f16(vecOut, vecTmp);
-    /*
-     * Cmplx sum is in 4rd & 5th f16 elt
-     * return full vector
-     */
-    return vecOut;
-}
-
-
-#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im)                \
-{                                                               \
-    float16x8_t   vecOut = __mve_cmplx_sum_intra_vec_f16(vec);    \
-    Re = vgetq_lane(vecOut, 4);                                 \
-    Im = vgetq_lane(vecOut, 5);                                 \
-}
-
-__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(
-    float16x8_t   vecIn,
-    float16_t  *pOut)
-{
-    float16x8_t   vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn);
-    /*
-     * Cmplx sum is in 4rd & 5th f16 elt
-     * use 32-bit extraction
-     */
-    *(float32_t *) pOut = ((float32x4_t) vecOut)[2];
-}
-
-
-#define INVSQRT_MAGIC_F16           0x59ba      /*  ( 0x1ba = 0x3759df >> 13) */
-
-/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */
-#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart)                  \
-{                                                                       \
-    float16x8_t tmp;                                                      \
-                                                                        \
-    /* tmp = xhalf * x * x */                                           \
-    tmp = vmulq(xStart, xStart);                                        \
-    tmp = vmulq(tmp, xHalf);                                            \
-    /* (1.5f - xhalf * x * x) */                                        \
-    tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp);                      \
-    /* x = x*(1.5f-xhalf*x*x); */                                       \
-    invSqrt = vmulq(tmp, xStart);                                       \
-}
-
-#endif
-#endif
-
-/***************************************
-
-Definitions available for MVEI and MVEF only
-
-***************************************/
-#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI))  && !defined(ARM_MATH_AUTOVECTORIZE)
-/* Following functions are used to transpose matrix in f32 and q31 cases */
-__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
-    uint32_t * pDataSrc,
-    uint32_t * pDataDest)
-{
-    static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
-    /*
-     *
-     * | 0   1 |   =>  |  0   2 |
-     * | 2   3 |       |  1   3 |
-     *
-     */
-    uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
-    vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
-    uint32_t * pDataSrc,
-    uint32_t * pDataDest)
-{
-    const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
-    const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
-    /*
-     *
-     *  | 0   1   2 |       | 0   3   6 |  4 x 32 flattened version | 0   3   6   1 |
-     *  | 3   4   5 |   =>  | 1   4   7 |            =>             | 4   7   2   5 |
-     *  | 6   7   8 |       | 2   5   8 |       (row major)         | 8   .   .   . |
-     *
-     */
-    uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
-    uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
-
-    vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
-    vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
-
-    pDataDest[8] = pDataSrc[8];
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
-{
-    /*
-     * 4x4 Matrix transposition
-     * is 4 x de-interleave operation
-     *
-     * 0   1   2   3       0   4   8   12
-     * 4   5   6   7       1   5   9   13
-     * 8   9   10  11      2   6   10  14
-     * 12  13  14  15      3   7   11  15
-     */
-
-    uint32x4x4_t vecIn;
-
-    vecIn = vld4q((uint32_t const *) pDataSrc);
-    vstrwq(pDataDest, vecIn.val[0]);
-    pDataDest += 4;
-    vstrwq(pDataDest, vecIn.val[1]);
-    pDataDest += 4;
-    vstrwq(pDataDest, vecIn.val[2]);
-    pDataDest += 4;
-    vstrwq(pDataDest, vecIn.val[3]);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-
-__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
-    uint16_t    srcRows,
-    uint16_t    srcCols,
-    uint32_t  * pDataSrc,
-    uint32_t  * pDataDest)
-{
-    uint32x4_t vecOffs;
-    uint32_t  i;
-    uint32_t  blkCnt;
-    uint32_t const *pDataC;
-    uint32_t *pDataDestR;
-    uint32x4_t vecIn;
-
-    vecOffs = vidupq_u32((uint32_t)0, 1);
-    vecOffs = vecOffs * srcCols;
-
-    i = srcCols;
-    do
-    {
-        pDataC = (uint32_t const *) pDataSrc;
-        pDataDestR = pDataDest;
-
-        blkCnt = srcRows >> 2;
-        while (blkCnt > 0U)
-        {
-            vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
-            vstrwq(pDataDestR, vecIn);
-            pDataDestR += 4;
-            pDataC = pDataC + srcCols * 4;
-            /*
-             * Decrement the blockSize loop counter
-             */
-            blkCnt--;
-        }
-
-        /*
-         * tail
-         */
-        blkCnt = srcRows & 3;
-        if (blkCnt > 0U)
-        {
-            mve_pred16_t p0 = vctp32q(blkCnt);
-            vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
-            vstrwq_p(pDataDestR, vecIn, p0);
-        }
-
-        pDataSrc += 1;
-        pDataDest += srcRows;
-    }
-    while (--i);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
-    uint16_t    srcRows,
-    uint16_t    srcCols,
-    uint32_t   *pDataSrc,
-    uint16_t    dstRows,
-    uint16_t    dstCols,
-    uint32_t   *pDataDest)
-{
-    uint32_t        i;
-    uint32_t const *pDataC;
-    uint32_t       *pDataRow;
-    uint32_t       *pDataDestR, *pDataDestRow;
-    uint32x4_t      vecOffsRef, vecOffsCur;
-    uint32_t        blkCnt;
-    uint32x4_t      vecIn;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-    /*
-     * Check for matrix mismatch condition
-     */
-    if ((srcRows != dstCols) || (srcCols != dstRows))
-    {
-        /*
-         * Set status as ARM_MATH_SIZE_MISMATCH
-         */
-        return ARM_MATH_SIZE_MISMATCH;
-    }
-#else
-    (void)dstRows;
-    (void)dstCols;
-#endif
-
-    /* 2x2, 3x3 and 4x4 specialization to be added */
-
-    vecOffsRef[0] = 0;
-    vecOffsRef[1] = 1;
-    vecOffsRef[2] = srcCols << 1;
-    vecOffsRef[3] = (srcCols << 1) + 1;
-
-    pDataRow = pDataSrc;
-    pDataDestRow = pDataDest;
-    i = srcCols;
-    do
-    {
-        pDataC = (uint32_t const *) pDataRow;
-        pDataDestR = pDataDestRow;
-        vecOffsCur = vecOffsRef;
-
-        blkCnt = (srcRows * CMPLX_DIM) >> 2;
-        while (blkCnt > 0U)
-        {
-            vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
-            vstrwq(pDataDestR, vecIn);
-            pDataDestR += 4;
-            vecOffsCur = vaddq(vecOffsCur, (srcCols << 2));
-            /*
-             * Decrement the blockSize loop counter
-             */
-             blkCnt--;
-        }
-        /*
-         * tail
-         * (will be merged thru tail predication)
-         */
-        blkCnt = (srcRows * CMPLX_DIM) & 3;
-        if (blkCnt > 0U)
-        {
-            mve_pred16_t p0 = vctp32q(blkCnt);
-            vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
-            vstrwq_p(pDataDestR, vecIn, p0);
-        }
-
-        pDataRow += CMPLX_DIM;
-        pDataDestRow += (srcRows * CMPLX_DIM);
-    }
-    while (--i);
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    pDataDest[0] = pDataSrc[0];
-    pDataDest[3] = pDataSrc[3];
-    pDataDest[2] = pDataSrc[1];
-    pDataDest[1] = pDataSrc[2];
-
-    return (ARM_MATH_SUCCESS);
-}
-
-__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 };
-    uint16x8_t    vecOffs1;
-    uint16x8_t    vecIn1;
-    /*
-     *
-     *  | 0   1   2 |       | 0   3   6 |  8 x 16 flattened version | 0   3   6   1   4   7   2   5 |
-     *  | 3   4   5 | =>    | 1   4   7 |            =>             | 8   .   .   .   .   .   .   . |
-     *  | 6   7   8 |       | 2   5   8 |       (row major)
-     *
-     */
-    vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33);
-    vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc);
-
-    vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
-
-    pDataDest[8] = pDataSrc[8];
-
-    return (ARM_MATH_SUCCESS);
-}
-
-
-__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
-{
-    static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 };
-    static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 };
-    uint16x8_t    vecOffs1, vecOffs2;
-    uint16x8_t    vecIn1, vecIn2;
-    uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc;
-
-    /*
-     * 4x4 Matrix transposition
-     *
-     * | 0   1   2   3  |       | 0   4   8   12 |   8 x 16 flattened version
-     * | 4   5   6   7  |  =>   | 1   5   9   13 |   =>      [0   4   8   12  1   5   9   13]
-     * | 8   9   10  11 |       | 2   6   10  14 |           [2   6   10  14  3   7   11  15]
-     * | 12  13  14  15 |       | 3   7   11  15 |
-     */
-
-    vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1);
-    vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2);
-    vecIn1 = vldrhq_u16(pDataSrcVec);
-    pDataSrcVec += 8;
-    vecIn2 = vldrhq_u16(pDataSrcVec);
-
-    vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
-    vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2);
-
-
-    return (ARM_MATH_SUCCESS);
-}
-
-
-
-__STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
-    uint16_t    srcRows,
-    uint16_t    srcCols,
-    uint16_t  * pDataSrc,
-    uint16_t  * pDataDest)
-{
-    uint16x8_t    vecOffs;
-    uint32_t        i;
-    uint32_t        blkCnt;
-    uint16_t const *pDataC;
-    uint16_t       *pDataDestR;
-    uint16x8_t    vecIn;
-
-    vecOffs = vidupq_u16((uint32_t)0, 1);
-    vecOffs = vecOffs * srcCols;
-
-    i = srcCols;
-    while(i > 0U)
-    {
-        pDataC = (uint16_t const *) pDataSrc;
-        pDataDestR = pDataDest;
-
-        blkCnt = srcRows >> 3;
-        while (blkCnt > 0U)
-        {
-            vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
-            vstrhq_u16(pDataDestR, vecIn);
-            pDataDestR += 8;
-            pDataC = pDataC + srcCols * 8;
-            /*
-             * Decrement the blockSize loop counter
-             */
-            blkCnt--;
-        }
-
-        /*
-         * tail
-         */
-        blkCnt = srcRows & 7;
-        if (blkCnt > 0U)
-        {
-            mve_pred16_t p0 = vctp16q(blkCnt);
-            vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
-            vstrhq_p_u16(pDataDestR, vecIn, p0);
-        }
-        pDataSrc += 1;
-        pDataDest += srcRows;
-        i--;
-    }
-
-    return (ARM_MATH_SUCCESS);
-}
-
-
-__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
-    uint16_t    srcRows,
-    uint16_t    srcCols,
-    uint16_t   *pDataSrc,
-    uint16_t    dstRows,
-    uint16_t    dstCols,
-    uint16_t   *pDataDest)
-{
-    static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
-    int             i;
-    uint16x8_t    vecOffsRef, vecOffsCur;
-    uint16_t const *pDataC;
-    uint16_t       *pDataRow;
-    uint16_t       *pDataDestR, *pDataDestRow;
-    uint32_t        blkCnt;
-    uint16x8_t    vecIn;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-    /*
-     * Check for matrix mismatch condition
-     */
-    if ((srcRows != dstCols) || (srcCols != dstRows))
-    {
-        /*
-         * Set status as ARM_MATH_SIZE_MISMATCH
-         */
-        return ARM_MATH_SIZE_MISMATCH;
-    }
-#else
-    (void)dstRows;
-    (void)dstCols;
-#endif
-
-    /*
-     * 2x2, 3x3 and 4x4 specialization to be added
-     */
-
-
-    /*
-     * build  [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1]
-     */
-    vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol);
-    vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM))
-                    + viwdupq_u16((uint32_t)0, (uint16_t) 2, 1);
-
-    pDataRow = pDataSrc;
-    pDataDestRow = pDataDest;
-    i = srcCols;
-    do
-    {
-        pDataC = (uint16_t const *) pDataRow;
-        pDataDestR = pDataDestRow;
-        vecOffsCur = vecOffsRef;
-
-        blkCnt = (srcRows * CMPLX_DIM) >> 3;
-        while (blkCnt > 0U)
-        {
-            vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
-            vstrhq(pDataDestR, vecIn);
-            pDataDestR+= 8; // VEC_LANES_U16
-            vecOffsCur = vaddq(vecOffsCur, (srcCols << 3));
-            /*
-             * Decrement the blockSize loop counter
-             */
-            blkCnt--;
-        }
-        /*
-         * tail
-         * (will be merged thru tail predication)
-         */
-        blkCnt = (srcRows * CMPLX_DIM) & 0x7;
-        if (blkCnt > 0U)
-        {
-            mve_pred16_t p0 = vctp16q(blkCnt);
-            vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
-            vstrhq_p(pDataDestR, vecIn, p0);
-        }
-
-        pDataRow += CMPLX_DIM;
-        pDataDestRow += (srcRows * CMPLX_DIM);
-    }
-    while (--i);
-
-    return (ARM_MATH_SUCCESS);
-}
-#endif /* MVEF and MVEI */
-
-/***************************************
-
-Definitions available for MVEI only
-
-***************************************/
-#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI))  && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#include "arm_common_tables.h"
-
-#define MVE_ASRL_SAT16(acc, shift)          ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff)
-#define MVE_ASRL_SAT32(acc, shift)          ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff)
-
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
-__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
-{
-    q63x2_t         vecTmpLL;
-    q31x4_t         vecTmp0, vecTmp1;
-    q31_t           scale;
-    q63_t           tmp64;
-    q31x4_t         vecNrm, vecDst, vecIdx, vecSignBits;
-
-
-    vecSignBits = vclsq(vecIn);
-    vecSignBits = vbicq_n_s32(vecSignBits, 1);
-    /*
-     * in = in << no_of_sign_bits;
-     */
-    vecNrm = vshlq(vecIn, vecSignBits);
-    /*
-     * index = in >> 24;
-     */
-    vecIdx = vecNrm >> 24;
-    vecIdx = vecIdx << 1;
-
-    vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
-
-    vecIdx = vecIdx + 1;
-
-    vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
-
-    vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
-    vecTmp0 = vecTmp0 - vecTmp1;
-    vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
-    vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
-    vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
-    vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
-    vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
-
-    /*
-     * scale elements 0, 2
-     */
-    scale = 26 + (vecSignBits[0] >> 1);
-    tmp64 = asrl(vecTmpLL[0], scale);
-    vecDst[0] = (q31_t) tmp64;
-
-    scale = 26 + (vecSignBits[2] >> 1);
-    tmp64 = asrl(vecTmpLL[1], scale);
-    vecDst[2] = (q31_t) tmp64;
-
-    vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
-
-    /*
-     * scale elements 1, 3
-     */
-    scale = 26 + (vecSignBits[1] >> 1);
-    tmp64 = asrl(vecTmpLL[0], scale);
-    vecDst[1] = (q31_t) tmp64;
-
-    scale = 26 + (vecSignBits[3] >> 1);
-    tmp64 = asrl(vecTmpLL[1], scale);
-    vecDst[3] = (q31_t) tmp64;
-    /*
-     * set negative values to 0
-     */
-    vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
-
-    return vecDst;
-}
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
-__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
-{
-    q31x4_t         vecTmpLev, vecTmpLodd, vecSignL;
-    q15x8_t         vecTmp0, vecTmp1;
-    q15x8_t         vecNrm, vecDst, vecIdx, vecSignBits;
-
-    vecDst = vuninitializedq_s16();
-
-    vecSignBits = vclsq(vecIn);
-    vecSignBits = vbicq_n_s16(vecSignBits, 1);
-    /*
-     * in = in << no_of_sign_bits;
-     */
-    vecNrm = vshlq(vecIn, vecSignBits);
-
-    vecIdx = vecNrm >> 8;
-    vecIdx = vecIdx << 1;
-
-    vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
-
-    vecIdx = vecIdx + 1;
-
-    vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
-
-    vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
-    vecTmp0 = vecTmp0 - vecTmp1;
-    vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
-    vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
-    vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
-    vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
-
-    vecSignBits = vecSignBits >> 1;
-
-    vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
-    vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
-
-    vecTmp0 = vecSignBits + 10;
-    /*
-     * negate sign to apply register based vshl
-     */
-    vecTmp0 = -vecTmp0;
-
-    /*
-     * shift even elements
-     */
-    vecSignL = vmovlbq(vecTmp0);
-    vecTmpLev = vshlq(vecTmpLev, vecSignL);
-    /*
-     * shift odd elements
-     */
-    vecSignL = vmovltq(vecTmp0);
-    vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
-    /*
-     * merge and narrow odd and even parts
-     */
-    vecDst = vmovnbq_s32(vecDst, vecTmpLev);
-    vecDst = vmovntq_s32(vecDst, vecTmpLodd);
-    /*
-     * set negative values to 0
-     */
-    vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
-
-    return vecDst;
-}
-#endif
-
-#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_math.h

@@ -1,236 +0,0 @@
-/******************************************************************************
- * @file     arm_math.h
- * @brief    Public header file for CMSIS DSP Library
- * @version  V1.9.0
- * @date     23 April 2021
- * Target Processor: Cortex-M and Cortex-A cores
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * \section intro Introduction
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor
-   * based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filtering functions
-   * - Matrix functions
-   * - Transform functions
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   * - Support Vector Machine functions (SVM)
-   * - Bayes classifier functions
-   * - Distance functions
-   * - Quaternion functions
-   *
-   * The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * The library is providing vectorized versions of most algorthms for Helium
-   * and of most f32 algorithms for Neon.
-   *
-   * When using a vectorized version, provide a little bit of padding after the end of
-   * a buffer (3 words) because the vectorized code may read a little bit after the end
-   * of a buffer. You don't have to modify your buffers but just ensure that the
-   * end of buffer + padding is not outside of a memory region.
-   *
-   * \section using Using the Library
-   *
-   * The library is released in source form. It is strongly advised to compile the library using -Ofast to
-   * have the best performances.
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file. If you don't want to include everything, you can also rely
-   * on headers in Include/dsp folder and use only what you need.
-   *
-   * \section example Examples
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * \section toolchain Toolchain Support
-   *
-   * The library is now tested on Fast Models building with cmake.
-   * Core M0, M4, M7, M33, M55, A32 are tested.
-   *
-   *
-   * \section preprocessor Preprocessor Macros
-   *
-   * Each library project have different preprocessor macros.
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_LOOPUNROLL:
-   *
-   * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
-   *
-   * - ARM_MATH_NEON:
-   *
-   * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
-   * It is not enabled by default when Neon is available because performances are
-   * dependent on the compiler and target architecture.
-   *
-   * - ARM_MATH_NEON_EXPERIMENTAL:
-   *
-   * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
-   * of some DSP functions. Experimental Neon versions currently do not have better
-   * performances than the scalar versions.
-   *
-   * - ARM_MATH_HELIUM:
-   *
-   * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.
-   *
-   * - ARM_MATH_HELIUM_EXPERIMENTAL:
-   *
-   * Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined.
-   * Enable some vector versions which may have worse performance than scalar
-   * depending on the core / compiler configuration.
-   *
-   * - ARM_MATH_MVEF:
-   *
-   * Select Helium versions of the f32 algorithms.
-   * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
-   *
-   * - ARM_MATH_MVEI:
-   *
-   * Select Helium versions of the int and fixed point algorithms.
-   *
-   * - ARM_MATH_MVE_FLOAT16:
-   *
-   * MVE Float16 implementations of some algorithms (Requires MVE extension).
-   *
-   * - DISABLEFLOAT16:
-   *
-   * Disable float16 algorithms when __fp16 is not supported for a
-   * specific compiler / core configuration.
-   * This is only valid for scalar. When vector architecture is
-   * supporting f16 then it can't be disabled.
-   *
-   * - ARM_MATH_AUTOVECTORIZE:
-   *
-   * With Helium or Neon, disable the use of vectorized code with C intrinsics
-   * and use pure C instead. The vectorization is then done by the compiler.
-   *
-   * <hr>
-   * \section pack CMSIS-DSP in ARM::CMSIS Pack
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                      |Content                                                                 |
-   * |---------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP     | This documentation                                                     |
-   * |\b CMSIS\\DSP\\Examples          | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP\\Include           | DSP_Lib include files for using and building the lib
-   * |\b CMSIS\\DSP\\PrivateInclude    | DSP_Lib private include files for building the lib                                               |
-   * |\b CMSIS\\DSP\\Lib               | DSP_Lib binaries                                                       |
-   * |\b CMSIS\\DSP\\Source            | DSP_Lib source files                                                   |
-   *
-   * <hr>
-   * \section rev Revision History of CMSIS-DSP
-   * Please refer to \ref ChangeLog_pg.
-   */
-
-
-
-
-
-
-
-
-
-
-
-/**
- * @defgroup groupExamples Examples
- */
-
-
-
-
-
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-
-#include "arm_math_types.h"
-#include "arm_math_memory.h"
-
-#include "dsp/none.h"
-#include "dsp/utils.h"
-
-#include "dsp/basic_math_functions.h"
-#include "dsp/interpolation_functions.h"
-#include "dsp/bayes_functions.h"
-#include "dsp/matrix_functions.h"
-#include "dsp/complex_math_functions.h"
-#include "dsp/statistics_functions.h"
-#include "dsp/controller_functions.h"
-#include "dsp/support_functions.h"
-#include "dsp/distance_functions.h"
-#include "dsp/svm_functions.h"
-#include "dsp/fast_math_functions.h"
-#include "dsp/transform_functions.h"
-#include "dsp/filtering_functions.h"
-#include "dsp/quaternion_math_functions.h"
-
-
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-
-
-//#define TABLE_SPACING_Q31     0x400000
-//#define TABLE_SPACING_Q15     0x80
-
-
-
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_math_f16.h

@@ -1,59 +0,0 @@
-/******************************************************************************
- * @file     arm_math_f16.h
- * @brief    Public header file for f16 function of the CMSIS DSP Library
- * @version  V1.9.0
- * @date     23 April 2021
- * Target Processor: Cortex-M and Cortex-A cores
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_MATH_F16_H
-#define _ARM_MATH_F16_H
-
-#include "arm_math.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-#include "arm_math_types_f16.h"
-#include "dsp/none.h"
-#include "dsp/utils.h"
-#include "dsp/basic_math_functions_f16.h"
-#include "dsp/interpolation_functions_f16.h"
-#include "dsp/bayes_functions_f16.h"
-#include "dsp/matrix_functions_f16.h"
-#include "dsp/complex_math_functions_f16.h"
-#include "dsp/statistics_functions_f16.h"
-#include "dsp/controller_functions_f16.h"
-#include "dsp/support_functions_f16.h"
-#include "dsp/distance_functions_f16.h"
-#include "dsp/svm_functions_f16.h"
-#include "dsp/fast_math_functions_f16.h"
-#include "dsp/transform_functions_f16.h"
-#include "dsp/filtering_functions_f16.h"
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /* _ARM_MATH_F16_H */
-
-

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_math_memory.h

@@ -1,241 +0,0 @@
-/******************************************************************************
- * @file     arm_math_memory.h
- * @brief    Public header file for CMSIS DSP Library
- * @version  V1.9.0
- * @date     23 April 2021
- * Target Processor: Cortex-M and Cortex-A cores
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_MATH_MEMORY_H_
-
-#define _ARM_MATH_MEMORY_H_
-
-#include "arm_math_types.h"
-
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-/**
-  @brief definition to read/write two 16 bit values.
-  @deprecated
- */
-#if   defined ( __CC_ARM )
-  #define __SIMD32_TYPE int32_t __packed
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __GNUC__ )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __ICCARM__ )
-  #define __SIMD32_TYPE int32_t __packed
-#elif defined ( __TI_ARM__ )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __CSMC__ )
-  #define __SIMD32_TYPE int32_t
-#elif defined ( __TASKING__ )
-  #define __SIMD32_TYPE __un(aligned) int32_t
-#elif defined(_MSC_VER )
-  #define __SIMD32_TYPE int32_t
-#else
-  #error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ( (__SIMD32_TYPE * )   (addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE * )   (addr))
-#define __SIMD64(addr)        (*(      int64_t **) & (addr))
-
-
-/* SIMD replacement */
-
-
-/**
-  @brief         Read 2 Q15 from Q15 pointer.
-  @param[in]     pQ15      points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2 (
-  q15_t * pQ15)
-{
-  q31_t val;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, pQ15, 4);
-#else
-  val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
-#endif
-
-  return (val);
-}
-
-/**
-  @brief         Read 2 Q15 from Q15 pointer and increment pointer afterwards.
-  @param[in]     pQ15      points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2_ia (
-  q15_t ** pQ15)
-{
-  q31_t val;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ15, 4);
-#else
-  val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
-#endif
-
- *pQ15 += 2;
- return (val);
-}
-
-/**
-  @brief         Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
-  @param[in]     pQ15      points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q15x2_da (
-  q15_t ** pQ15)
-{
-  q31_t val;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ15, 4);
-#else
-  val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
-#endif
-
-  *pQ15 -= 2;
-  return (val);
-}
-
-/**
-  @brief         Write 2 Q15 to Q15 pointer and increment pointer afterwards.
-  @param[in]     pQ15      points to input value
-  @param[in]     value     Q31 value
-  @return        none
- */
-__STATIC_FORCEINLINE void write_q15x2_ia (
-  q15_t ** pQ15,
-  q31_t    value)
-{
-  q31_t val = value;
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (*pQ15, &val, 4);
-#else
-  (*pQ15)[0] = (val & 0x0FFFF);
-  (*pQ15)[1] = (val >> 16) & 0x0FFFF;
-#endif
-
- *pQ15 += 2;
-}
-
-/**
-  @brief         Write 2 Q15 to Q15 pointer.
-  @param[in]     pQ15      points to input value
-  @param[in]     value     Q31 value
-  @return        none
- */
-__STATIC_FORCEINLINE void write_q15x2 (
-  q15_t * pQ15,
-  q31_t   value)
-{
-  q31_t val = value;
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (pQ15, &val, 4);
-#else
-  pQ15[0] = val & 0x0FFFF;
-  pQ15[1] = val >> 16;
-#endif
-}
-
-
-/**
-  @brief         Read 4 Q7 from Q7 pointer and increment pointer afterwards.
-  @param[in]     pQ7       points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q7x4_ia (
-  q7_t ** pQ7)
-{
-  q31_t val;
-
-
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ7, 4);
-#else
-  val =(((*pQ7)[3] & 0x0FF) << 24)  | (((*pQ7)[2] & 0x0FF) << 16)  | (((*pQ7)[1] & 0x0FF) << 8)  | ((*pQ7)[0] & 0x0FF);
-#endif
-
-  *pQ7 += 4;
-
-  return (val);
-}
-
-/**
-  @brief         Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
-  @param[in]     pQ7       points to input value
-  @return        Q31 value
- */
-__STATIC_FORCEINLINE q31_t read_q7x4_da (
-  q7_t ** pQ7)
-{
-  q31_t val;
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (&val, *pQ7, 4);
-#else
-  val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16)   | ((((*pQ7)[1]) & 0x0FF) << 8)  | ((*pQ7)[0] & 0x0FF);
-#endif
-  *pQ7 -= 4;
-
-  return (val);
-}
-
-/**
-  @brief         Write 4 Q7 to Q7 pointer and increment pointer afterwards.
-  @param[in]     pQ7       points to input value
-  @param[in]     value     Q31 value
-  @return        none
- */
-__STATIC_FORCEINLINE void write_q7x4_ia (
-  q7_t ** pQ7,
-  q31_t   value)
-{
-  q31_t val = value;
-#ifdef __ARM_FEATURE_UNALIGNED
-  memcpy (*pQ7, &val, 4);
-#else
-  (*pQ7)[0] = val & 0x0FF;
-  (*pQ7)[1] = (val >> 8) & 0x0FF;
-  (*pQ7)[2] = (val >> 16) & 0x0FF;
-  (*pQ7)[3] = (val >> 24) & 0x0FF;
-
-#endif
-  *pQ7 += 4;
-}
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /*ifndef _ARM_MATH_MEMORY_H_ */

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_math_types.h

@@ -1,592 +0,0 @@
-/******************************************************************************
- * @file     arm_math_types.h
- * @brief    Public header file for CMSIS DSP Library
- * @version  V1.9.0
- * @date     23 April 2021
- * Target Processor: Cortex-M and Cortex-A cores
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_MATH_TYPES_H_
-
-#define _ARM_MATH_TYPES_H_
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wsign-conversion"
-  #pragma GCC diagnostic ignored "-Wconversion"
-  #pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#elif defined ( _MSC_VER )
-
-#else
-  #error Unknown compiler
-#endif
-
-
-/* Included for instrinsics definitions */
-#if defined (_MSC_VER )
-#include <stdint.h>
-#define __STATIC_FORCEINLINE static __forceinline
-#define __STATIC_INLINE static __inline
-#define __ALIGNED(x) __declspec(align(x))
-
-#elif defined (__GNUC_PYTHON__)
-#include <stdint.h>
-#define  __ALIGNED(x) __attribute__((aligned(x)))
-#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
-#define __STATIC_INLINE static inline
-
-#else
-#include "cmsis_compiler.h"
-#endif
-
-
-
-#include <string.h>
-#include <math.h>
-#include <float.h>
-#include <limits.h>
-
-/* evaluate ARM DSP feature */
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-  #define ARM_MATH_DSP                   1
-#endif
-
-#if defined(ARM_MATH_NEON)
-#include <arm_neon.h>
-#if __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
-  #if !defined(ARM_MATH_NEON_FLOAT16)
-  #define ARM_MATH_NEON_FLOAT16
-  #endif
-#endif
-#endif
-
-#if !defined(ARM_MATH_AUTOVECTORIZE)
-
-#if __ARM_FEATURE_MVE
-  #if !defined(ARM_MATH_MVEI)
-    #define ARM_MATH_MVEI
-  #endif
-#endif
-
-#if (__ARM_FEATURE_MVE & 2)
-  #if !defined(ARM_MATH_MVEF)
-    #define ARM_MATH_MVEF
-  #endif
-  #if !defined(ARM_MATH_MVE_FLOAT16)
-       #define ARM_MATH_MVE_FLOAT16
-  #endif
-#endif
-
-#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/
-
-
-#if defined (ARM_MATH_HELIUM)
-  #if !defined(ARM_MATH_MVEF)
-    #define ARM_MATH_MVEF
-  #endif
-
-  #if !defined(ARM_MATH_MVEI)
-    #define ARM_MATH_MVEI
-  #endif
-
-  #if !defined(ARM_MATH_MVE_FLOAT16)
-       #define ARM_MATH_MVE_FLOAT16
-  #endif
-#endif
-
-
-
-#if   defined ( __CC_ARM )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined( __ARM_ARCH_7EM__ )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("push")         \
-       _Pragma ("O1")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #if defined ( __ARM_ARCH_7EM__ )
-    #define LOW_OPTIMIZATION_EXIT \
-       _Pragma ("pop")
-  #else
-    #define LOW_OPTIMIZATION_EXIT
-  #endif
-
-  /* Enter low optimization region - place directly above function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-  #define LOW_OPTIMIZATION_ENTER \
-       __attribute__(( optimize("-O1") ))
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( __ARM_ARCH_7EM__ )
-    #define LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define LOW_OPTIMIZATION_EXIT
-
-  /* Enter low optimization region - place directly above function definition */
-  #if defined ( __ARM_ARCH_7EM__ )
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-       _Pragma ("optimize=low")
-  #else
-    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #endif
-
-  /* Exit low optimization region - place directly after end of function definition */
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-  #define LOW_OPTIMIZATION_ENTER
-  #define LOW_OPTIMIZATION_EXIT
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
-      #define LOW_OPTIMIZATION_ENTER
-      #define LOW_OPTIMIZATION_EXIT
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-      #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-#endif
-
-
-
-/* Compiler specific diagnostic adjustment */
-#if   defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#elif defined ( _MSC_VER )
-
-#else
-  #error Unknown compiler
-#endif
-
-#ifdef   __cplusplus
-}
-#endif
-
-#if __ARM_FEATURE_MVE
-#include <arm_mve.h>
-#endif
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
- /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief vector types
-   */
-#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI)  && !defined(ARM_MATH_AUTOVECTORIZE))
-  /**
-   * @brief 64-bit fractional 128-bit vector data type in 1.63 format
-   */
-  typedef int64x2_t q63x2_t;
-
-  /**
-   * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
-   */
-  typedef int32x4_t q31x4_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format.
-   */
-  typedef __ALIGNED(2) int16x8_t q15x8_t;
-
- /**
-   * @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format.
-   */
-  typedef __ALIGNED(1) int8x16_t q7x16_t;
-
-    /**
-   * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
-   */
-  typedef int32x4x2_t q31x4x2_t;
-
-  /**
-   * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
-   */
-  typedef int32x4x4_t q31x4x4_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
-   */
-  typedef int16x8x2_t q15x8x2_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
-   */
-  typedef int16x8x4_t q15x8x4_t;
-
-  /**
-   * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
-   */
-  typedef int8x16x2_t q7x16x2_t;
-
-  /**
-   * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
-   */
-   typedef int8x16x4_t q7x16x4_t;
-
-  /**
-   * @brief 32-bit fractional data type in 9.23 format.
-   */
-  typedef int32_t q23_t;
-
-  /**
-   * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
-   */
-  typedef int32x4_t q23x4_t;
-
-  /**
-   * @brief 64-bit status 128-bit vector data type.
-   */
-  typedef int64x2_t status64x2_t;
-
-  /**
-   * @brief 32-bit status 128-bit vector data type.
-   */
-  typedef int32x4_t status32x4_t;
-
-  /**
-   * @brief 16-bit status 128-bit vector data type.
-   */
-  typedef int16x8_t status16x8_t;
-
-  /**
-   * @brief 8-bit status 128-bit vector data type.
-   */
-  typedef int8x16_t status8x16_t;
-
-
-#endif
-
-#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF)  && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
-  /**
-   * @brief 32-bit floating-point 128-bit vector type
-   */
-  typedef float32x4_t f32x4_t;
-
-  /**
-   * @brief 32-bit floating-point 128-bit vector pair data type
-   */
-  typedef float32x4x2_t f32x4x2_t;
-
-  /**
-   * @brief 32-bit floating-point 128-bit vector quadruplet data type
-   */
-  typedef float32x4x4_t f32x4x4_t;
-
-  /**
-   * @brief 32-bit ubiquitous 128-bit vector data type
-   */
-  typedef union _any32x4_t
-  {
-      float32x4_t     f;
-      int32x4_t       i;
-  } any32x4_t;
-
-#endif
-
-#if defined(ARM_MATH_NEON)
-  /**
-   * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
-   */
-  typedef int32x2_t  q31x2_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
-   */
-  typedef  __ALIGNED(2) int16x4_t q15x4_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
-   */
-  typedef  __ALIGNED(1) int8x8_t q7x8_t;
-
-  /**
-   * @brief 32-bit float 64-bit vector data type.
-   */
-  typedef float32x2_t  f32x2_t;
-
-  /**
-   * @brief 32-bit floating-point 128-bit vector triplet data type
-   */
-  typedef float32x4x3_t f32x4x3_t;
-
-
-  /**
-   * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
-   */
-  typedef int32x4x3_t q31x4x3_t;
-
-  /**
-   * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
-   */
-  typedef int16x8x3_t q15x8x3_t;
-
-  /**
-   * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
-   */
-  typedef int8x16x3_t q7x16x3_t;
-
-  /**
-   * @brief 32-bit floating-point 64-bit vector pair data type
-   */
-  typedef float32x2x2_t f32x2x2_t;
-
-  /**
-   * @brief 32-bit floating-point 64-bit vector triplet data type
-   */
-  typedef float32x2x3_t f32x2x3_t;
-
-  /**
-   * @brief 32-bit floating-point 64-bit vector quadruplet data type
-   */
-  typedef float32x2x4_t f32x2x4_t;
-
-
-  /**
-   * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
-   */
-  typedef int32x2x2_t q31x2x2_t;
-
-  /**
-   * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
-   */
-  typedef int32x2x3_t q31x2x3_t;
-
-  /**
-   * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
-   */
-  typedef int32x4x3_t q31x2x4_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
-   */
-  typedef int16x4x2_t q15x4x2_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
-   */
-  typedef int16x4x2_t q15x4x3_t;
-
-  /**
-   * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
-   */
-  typedef int16x4x3_t q15x4x4_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
-   */
-  typedef int8x8x2_t q7x8x2_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
-   */
-  typedef int8x8x3_t q7x8x3_t;
-
-  /**
-   * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
-   */
-  typedef int8x8x4_t q7x8x4_t;
-
-  /**
-   * @brief 32-bit ubiquitous 64-bit vector data type
-   */
-  typedef union _any32x2_t
-  {
-      float32x2_t     f;
-      int32x2_t       i;
-  } any32x2_t;
-
-
-  /**
-   * @brief 32-bit status 64-bit vector data type.
-   */
-  typedef int32x4_t status32x2_t;
-
-  /**
-   * @brief 16-bit status 64-bit vector data type.
-   */
-  typedef int16x8_t status16x4_t;
-
-  /**
-   * @brief 8-bit status 64-bit vector data type.
-   */
-  typedef int8x16_t status8x8_t;
-
-#endif
-
-
-
-
-
-#define F64_MAX   ((float64_t)DBL_MAX)
-#define F32_MAX   ((float32_t)FLT_MAX)
-
-
-
-#define F64_MIN   (-DBL_MAX)
-#define F32_MIN   (-FLT_MAX)
-
-
-
-#define F64_ABSMAX   ((float64_t)DBL_MAX)
-#define F32_ABSMAX   ((float32_t)FLT_MAX)
-
-
-
-#define F64_ABSMIN   ((float64_t)0.0)
-#define F32_ABSMIN   ((float32_t)0.0)
-
-
-#define Q31_MAX   ((q31_t)(0x7FFFFFFFL))
-#define Q15_MAX   ((q15_t)(0x7FFF))
-#define Q7_MAX    ((q7_t)(0x7F))
-#define Q31_MIN   ((q31_t)(0x80000000L))
-#define Q15_MIN   ((q15_t)(0x8000))
-#define Q7_MIN    ((q7_t)(0x80))
-
-#define Q31_ABSMAX   ((q31_t)(0x7FFFFFFFL))
-#define Q15_ABSMAX   ((q15_t)(0x7FFF))
-#define Q7_ABSMAX    ((q7_t)(0x7F))
-#define Q31_ABSMIN   ((q31_t)0)
-#define Q15_ABSMIN   ((q15_t)0)
-#define Q7_ABSMIN    ((q7_t)0)
-
-  /* Dimension C vector space */
-  #define CMPLX_DIM 2
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS                 =  0,        /**< No error */
-    ARM_MATH_ARGUMENT_ERROR          = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR            = -2,        /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH           = -3,        /**< Size of matrices is not compatible with the operation */
-    ARM_MATH_NANINF                  = -4,        /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR                = -5,        /**< Input matrix is singular and cannot be inverted */
-    ARM_MATH_TEST_FAILURE            = -6,        /**< Test Failed */
-    ARM_MATH_DECOMPOSITION_FAILURE   = -7         /**< Decomposition Failed */
-  } arm_status;
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /*ifndef _ARM_MATH_TYPES_H_ */

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_math_types_f16.h

@@ -1,156 +0,0 @@
-/******************************************************************************
- * @file     arm_math_types_f16.h
- * @brief    Public header file for f16 function of the CMSIS DSP Library
- * @version  V1.9.0
- * @date     23 April 2021
- * Target Processor: Cortex-M and Cortex-A cores
- ******************************************************************************/
-/*
- * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_MATH_TYPES_F16_H
-#define _ARM_MATH_TYPES_F16_H
-
-#include "arm_math_types.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-#if !defined( __CC_ARM )
-
-/**
- * @brief 16-bit floating-point type definition.
- * This is already defined in arm_mve.h
- *
- * This is not fully supported on ARM AC5.
- */
-
-/*
-
-Check if the type __fp16 is available.
-If it is not available, f16 version of the kernels
-won't be built.
-
-*/
-#if !(__ARM_FEATURE_MVE & 2)
-  #if !defined(DISABLEFLOAT16)
-    #if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE)
-      typedef __fp16 float16_t;
-      #define ARM_FLOAT16_SUPPORTED
-    #endif
-  #endif
-#else
-  /* When Vector float16, this flag is always defined and can't be disabled */
-  #define ARM_FLOAT16_SUPPORTED
-#endif
-
-#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF)  && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
-
-#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16)
-
-  /**
-   * @brief 16-bit floating-point 128-bit vector data type
-   */
-  typedef __ALIGNED(2) float16x8_t f16x8_t;
-
-  /**
-   * @brief 16-bit floating-point 128-bit vector pair data type
-   */
-  typedef float16x8x2_t f16x8x2_t;
-
-  /**
-   * @brief 16-bit floating-point 128-bit vector quadruplet data type
-   */
-  typedef float16x8x4_t f16x8x4_t;
-
-  /**
-   * @brief 16-bit ubiquitous 128-bit vector data type
-   */
-  typedef union _any16x8_t
-  {
-      float16x8_t     f;
-      int16x8_t       i;
-  } any16x8_t;
-#endif
-
-#endif
-
-#if defined(ARM_MATH_NEON)
-
-
-#if defined(ARM_MATH_NEON_FLOAT16)
-  /**
-   * @brief 16-bit float 64-bit vector data type.
-   */
-  typedef  __ALIGNED(2) float16x4_t f16x4_t;
-
-  /**
-   * @brief 16-bit floating-point 128-bit vector triplet data type
-   */
-  typedef float16x8x3_t f16x8x3_t;
-
-  /**
-   * @brief 16-bit floating-point 64-bit vector pair data type
-   */
-  typedef float16x4x2_t f16x4x2_t;
-
-  /**
-   * @brief 16-bit floating-point 64-bit vector triplet data type
-   */
-  typedef float16x4x3_t f16x4x3_t;
-
-  /**
-   * @brief 16-bit floating-point 64-bit vector quadruplet data type
-   */
-  typedef float16x4x4_t f16x4x4_t;
-
-  /**
-   * @brief 16-bit ubiquitous 64-bit vector data type
-   */
-  typedef union _any16x4_t
-  {
-      float16x4_t     f;
-      int16x4_t       i;
-  } any16x4_t;
-#endif
-
-#endif
-
-
-
-#if defined(ARM_FLOAT16_SUPPORTED)
-#define F16_MAX   ((float16_t)__FLT16_MAX__)
-#define F16_MIN   (-(float16_t)__FLT16_MAX__)
-
-#define F16_ABSMAX   ((float16_t)__FLT16_MAX__)
-#define F16_ABSMIN   ((float16_t)0.0f16)
-
-#define F16INFINITY ((float16_t)__builtin_inf())
-
-#endif /* ARM_FLOAT16_SUPPORTED*/
-#endif /* !defined( __CC_ARM ) */
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /* _ARM_MATH_F16_H */
-
-

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_mve_tables.h

@@ -1,231 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_mve_tables.h
- * Description:  common tables like fft twiddle factors, Bitreverse, reciprocal etc
- *               used for MVE implementation only
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #ifndef _ARM_MVE_TABLES_H
- #define _ARM_MVE_TABLES_H
-
-#include "arm_math_types.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-
-
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
-extern float32_t rearranged_twiddle_stride1_16_f32[8];
-extern float32_t rearranged_twiddle_stride2_16_f32[8];
-extern float32_t rearranged_twiddle_stride3_16_f32[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
-extern float32_t rearranged_twiddle_stride1_64_f32[40];
-extern float32_t rearranged_twiddle_stride2_64_f32[40];
-extern float32_t rearranged_twiddle_stride3_64_f32[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
-extern float32_t rearranged_twiddle_stride1_256_f32[168];
-extern float32_t rearranged_twiddle_stride2_256_f32[168];
-extern float32_t rearranged_twiddle_stride3_256_f32[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
-extern float32_t rearranged_twiddle_stride1_1024_f32[680];
-extern float32_t rearranged_twiddle_stride2_1024_f32[680];
-extern float32_t rearranged_twiddle_stride3_1024_f32[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
-extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
-extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
-extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
-
-
-
-#if defined(ARM_MATH_MVEI)  && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
-extern q31_t rearranged_twiddle_stride1_16_q31[8];
-extern q31_t rearranged_twiddle_stride2_16_q31[8];
-extern q31_t rearranged_twiddle_stride3_16_q31[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
-extern q31_t rearranged_twiddle_stride1_64_q31[40];
-extern q31_t rearranged_twiddle_stride2_64_q31[40];
-extern q31_t rearranged_twiddle_stride3_64_q31[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
-extern q31_t rearranged_twiddle_stride1_256_q31[168];
-extern q31_t rearranged_twiddle_stride2_256_q31[168];
-extern q31_t rearranged_twiddle_stride3_256_q31[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
-extern q31_t rearranged_twiddle_stride1_1024_q31[680];
-extern q31_t rearranged_twiddle_stride2_1024_q31[680];
-extern q31_t rearranged_twiddle_stride3_1024_q31[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
-extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
-extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
-extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEI) */
-
-
-
-#if defined(ARM_MATH_MVEI)  && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
-extern q15_t rearranged_twiddle_stride1_16_q15[8];
-extern q15_t rearranged_twiddle_stride2_16_q15[8];
-extern q15_t rearranged_twiddle_stride3_16_q15[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
-extern q15_t rearranged_twiddle_stride1_64_q15[40];
-extern q15_t rearranged_twiddle_stride2_64_q15[40];
-extern q15_t rearranged_twiddle_stride3_64_q15[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
-extern q15_t rearranged_twiddle_stride1_256_q15[168];
-extern q15_t rearranged_twiddle_stride2_256_q15[168];
-extern q15_t rearranged_twiddle_stride3_256_q15[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
-extern q15_t rearranged_twiddle_stride1_1024_q15[680];
-extern q15_t rearranged_twiddle_stride2_1024_q15[680];
-extern q15_t rearranged_twiddle_stride3_1024_q15[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
-extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
-extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
-extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEI) */
-
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /*_ARM_MVE_TABLES_H*/
-

bsp/apm32/libraries/APM32F4xx_Library/CMSIS/DSP/Include/arm_mve_tables_f16.h

@@ -1,109 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_mve_tables_f16.h
- * Description:  common tables like fft twiddle factors, Bitreverse, reciprocal etc
- *               used for MVE implementation only
- *
- * @version  V1.9.0
- * @date     23 April 2021
- *
- * Target Processor: Cortex-M and Cortex-A cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #ifndef _ARM_MVE_TABLES_F16_H
- #define _ARM_MVE_TABLES_F16_H
-
-#include "arm_math_types_f16.h"
-
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-
-
-#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2];
-extern float16_t rearranged_twiddle_stride1_16_f16[8];
-extern float16_t rearranged_twiddle_stride2_16_f16[8];
-extern float16_t rearranged_twiddle_stride3_16_f16[8];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3];
-extern float16_t rearranged_twiddle_stride1_64_f16[40];
-extern float16_t rearranged_twiddle_stride2_64_f16[40];
-extern float16_t rearranged_twiddle_stride3_64_f16[40];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4];
-extern float16_t rearranged_twiddle_stride1_256_f16[168];
-extern float16_t rearranged_twiddle_stride2_256_f16[168];
-extern float16_t rearranged_twiddle_stride3_256_f16[168];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5];
-extern float16_t rearranged_twiddle_stride1_1024_f16[680];
-extern float16_t rearranged_twiddle_stride2_1024_f16[680];
-extern float16_t rearranged_twiddle_stride3_1024_f16[680];
-#endif
-
-#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192)
-
-extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6];
-extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6];
-extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6];
-extern float16_t rearranged_twiddle_stride1_4096_f16[2728];
-extern float16_t rearranged_twiddle_stride2_4096_f16[2728];
-extern float16_t rearranged_twiddle_stride3_4096_f16[2728];
-#endif
-
-
-#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
-
-#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
-
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-#endif /*_ARM_MVE_TABLES_F16_H*/
-