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@@ -1,10 +1,23 @@
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/*
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-* Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
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-*/
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+ * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
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+ *
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+ * Licensed under the Apache License, Version 2.0 (the "License");
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+ * you may not use this file except in compliance with the License.
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+ * You may obtain a copy of the License at
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+ *
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+ * http://www.apache.org/licenses/LICENSE-2.0
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+ *
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+ * Unless required by applicable law or agreed to in writing, software
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+ * distributed under the License is distributed on an "AS IS" BASIS,
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+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+ * See the License for the specific language governing permissions and
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+ * limitations under the License.
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+ */
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#include <rtthread.h>
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#include "dw_eth_mac.h"
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#include "cache.h"
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+#include "string.h"
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#define roundup(x, y) ( \
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{ \
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@@ -91,7 +104,7 @@ static void tx_descs_init(eth_mac_handle_t handle)
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desc_p->dmamac_next = (unsigned long)&desc_table_p[0];
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/* Flush all Tx buffer descriptors at once */
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- rt_hw_cpu_dcache_clean((unsigned long)priv->tx_mac_descrtable, sizeof(priv->tx_mac_descrtable));
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+ rt_hw_cpu_dcache_clean((void *)priv->tx_mac_descrtable, sizeof(priv->tx_mac_descrtable));
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dma_reg->txdesclistaddr = (unsigned long)&desc_table_p[0];
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@@ -114,7 +127,7 @@ static void rx_descs_init(eth_mac_handle_t handle)
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* Otherwise there's a chance to get some of them flushed in RAM when
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* GMAC is already pushing data to RAM via DMA. This way incoming from
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* GMAC data will be corrupted. */
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- rt_hw_cpu_dcache_clean((unsigned long)rxbuffs, CVI_RX_TOTAL_BUFSIZE);
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+ rt_hw_cpu_dcache_clean((void *)rxbuffs, CVI_RX_TOTAL_BUFSIZE);
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for (idx = 0; idx < CVI_CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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@@ -132,7 +145,7 @@ static void rx_descs_init(eth_mac_handle_t handle)
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desc_p->dmamac_next = (unsigned long)&desc_table_p[0];
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/* Flush all Rx buffer descriptors at once */
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- rt_hw_cpu_dcache_clean((unsigned long)priv->rx_mac_descrtable, sizeof(priv->rx_mac_descrtable));
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+ rt_hw_cpu_dcache_clean((void *)priv->rx_mac_descrtable, sizeof(priv->rx_mac_descrtable));
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dma_reg->rxdesclistaddr = (unsigned long)&desc_table_p[0];
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@@ -238,8 +251,8 @@ static int32_t designware_eth_enable(eth_mac_handle_t handle, int32_t control)
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struct dw_gmac_mac_regs *mac_reg = mac_dev->priv->mac_regs_p;
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eth_link_state_t link_state = mac_dev->phy_dev->link_state;
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- if (link_state == ETH_LINK_DOWN)
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- return -1;
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+ // if (link_state == ETH_LINK_DOWN)
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+ // return -1;
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switch (control) {
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case CSI_ETH_MAC_CONTROL_TX:
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@@ -320,7 +333,7 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame
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/* Check if the descriptor is owned by CPU */
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while (1) {
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- rt_hw_cpu_dcache_invalidate(desc_start, desc_end - desc_start);
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+ rt_hw_cpu_dcache_invalidate((void *)desc_start, desc_end - desc_start);
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if (!(desc_p->txrx_status & CVI_DESC_TXSTS_OWNBYDMA)) {
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break;
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}
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@@ -335,7 +348,7 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame
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memcpy((void *)data_start, frame, length);
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/* Flush data to be sent */
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- rt_hw_cpu_dcache_clean(data_start, data_end - data_start);
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+ rt_hw_cpu_dcache_clean((void *)data_start, data_end - data_start);
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status |= CVI_DESC_TXSTS_TXFIRST | CVI_DESC_TXSTS_TXLAST;
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@@ -355,7 +368,7 @@ static int32_t designware_eth_send(eth_mac_handle_t handle, const uint8_t *frame
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#endif
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/* Flush modified buffer descriptor */
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- rt_hw_cpu_dcache_clean(desc_start, desc_end - desc_start);
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+ rt_hw_cpu_dcache_clean((void *)desc_start, desc_end - desc_start);
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/* Test the wrap-around condition. */
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if (++desc_num >= CVI_CONFIG_TX_DESCR_NUM)
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@@ -383,7 +396,7 @@ static int32_t designware_eth_recv(eth_mac_handle_t handle, uint8_t **packetp)
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uint64_t data_end;
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/* Invalidate entire buffer descriptor */
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- rt_hw_cpu_dcache_invalidate(desc_start, desc_end - desc_start);
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+ rt_hw_cpu_dcache_invalidate((void *)desc_start, desc_end - desc_start);
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status = desc_p->txrx_status;
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/* Check if the owner is the CPU */
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if (!(status & CVI_DESC_RXSTS_OWNBYDMA)) {
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@@ -391,7 +404,7 @@ static int32_t designware_eth_recv(eth_mac_handle_t handle, uint8_t **packetp)
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CVI_DESC_RXSTS_FRMLENSHFT;
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/* Invalidate received data */
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data_end = data_start + roundup(length, DW_GMAC_DMA_ALIGN);
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- rt_hw_cpu_dcache_invalidate(data_start, data_end - data_start);
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+ rt_hw_cpu_dcache_invalidate((void *)data_start, data_end - data_start);
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*packetp = (uint8_t *)((uint64_t)desc_p->dmamac_addr);
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}
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@@ -415,7 +428,7 @@ static int32_t designware_free_pkt(eth_mac_handle_t handle)
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desc_p->txrx_status |= CVI_DESC_RXSTS_OWNBYDMA;
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/* Flush only status field - others weren't changed */
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- rt_hw_cpu_dcache_clean(desc_start, desc_end - desc_start);
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+ rt_hw_cpu_dcache_clean((void *)desc_start, desc_end - desc_start);
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/* Test the wrap-around condition. */
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if (++desc_num >= CVI_CONFIG_RX_DESCR_NUM)
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@@ -619,10 +632,9 @@ int32_t cvi_eth_mac_set_macaddr(eth_mac_handle_t handle, const eth_mac_addr_t *m
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\param[in] handle ethernet handle
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\param[in] frame Pointer to frame buffer with data to send
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\param[in] len Frame buffer length in bytes
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- \param[in] flags Frame transmit flags (see CSI_ETH_MAC_TX_FRAME_...)
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\return error code
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*/
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-int32_t cvi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len, uint32_t flags)
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+int32_t cvi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len)
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{
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RT_ASSERT(handle);
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RT_ASSERT(frame);
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