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@@ -0,0 +1,1691 @@
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+/**
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+ ******************************************************************************
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+ * @file stm32f0xx_hal_can.c
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+ * @author MCD Application Team
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+ * @brief This file provides firmware functions to manage the following
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+ * functionalities of the Controller Area Network (CAN) peripheral:
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+ * + Initialization and de-initialization functions
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+ * + IO operation functions
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+ * + Peripheral Control functions
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+ * + Peripheral State and Error functions
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+ *
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+ @verbatim
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+ ==============================================================================
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+ ##### User NOTE #####
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+ ==============================================================================
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+ [..]
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+ (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations.
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+ Another HAL CAN driver version has been designed with new API's, to fix these limitations.
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+
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+ ==============================================================================
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+ ##### How to use this driver #####
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+ ==============================================================================
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+ [..]
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+ (#) Enable the CAN controller interface clock using __HAL_RCC_CAN1_CLK_ENABLE();
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+
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+ (#) CAN pins configuration
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+ (++) Enable the clock for the CAN GPIOs using the following function:
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+ __HAL_RCC_GPIOx_CLK_ENABLE();
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+ (++) Connect and configure the involved CAN pins to AF9 using the
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+ following function HAL_GPIO_Init();
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+
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+ (#) Initialise and configure the CAN using HAL_CAN_Init() function.
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+
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+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
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+
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+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
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+
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+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
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+
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+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
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+
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+ *** Polling mode IO operation ***
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+ =================================
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+ [..]
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+ (+) Start the CAN peripheral transmission and wait the end of this operation
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+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
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+ according to his end application
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+ (+) Start the CAN peripheral reception and wait the end of this operation
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+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
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+ according to his end application
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+
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+ *** Interrupt mode IO operation ***
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+ ===================================
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+ [..]
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+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
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+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
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+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
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+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
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+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
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+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
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+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
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+
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+ *** CAN HAL driver macros list ***
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+ =============================================
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+ [..]
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+ Below the list of most used macros in CAN HAL driver.
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+
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+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
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+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
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+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
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+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
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+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
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+
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+ [..]
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+ (@) You can refer to the CAN Legacy HAL driver header file for more useful macros
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+
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+ @endverbatim
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+
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+ ******************************************************************************
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+ * @attention
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+ *
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+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
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+ * All rights reserved.</center></h2>
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+ *
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+ * This software component is licensed by ST under BSD 3-Clause license,
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+ * the "License"; You may not use this file except in compliance with the
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+ * License. You may obtain a copy of the License at:
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+ * opensource.org/licenses/BSD-3-Clause
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+ *
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+ ******************************************************************************
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+ */
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+
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+/* Includes ------------------------------------------------------------------*/
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+#include "stm32f0xx_hal.h"
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+
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+/** @addtogroup STM32F0xx_HAL_Driver
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+ * @{
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+ */
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+
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+/** @defgroup CAN CAN
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+ * @brief CAN driver modules
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+ * @{
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+ */
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+
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+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
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+#if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx)
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+#ifdef HAL_CAN_MODULE_ENABLED
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+/* Select HAL CAN module in stm32f0xx_hal_conf.h file:
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+ (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations
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+ (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */
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+#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f0xx_hal_conf.h file'
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+#endif /* HAL_CAN_MODULE_ENABLED */
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+
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+#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
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+/* Private typedef -----------------------------------------------------------*/
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+/* Private define ------------------------------------------------------------*/
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+/** @defgroup CAN_Private_Constants CAN Private Constants
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+ * @{
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+ */
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+#define CAN_TIMEOUT_VALUE 10U
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+/**
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+ * @}
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+ */
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+/* Private macro -------------------------------------------------------------*/
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+/* Private variables ---------------------------------------------------------*/
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+/* Private function prototypes -----------------------------------------------*/
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+/** @defgroup CAN_Private_Functions CAN Private Functions
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+ * @{
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+ */
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+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
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+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
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+/**
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+ * @}
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+ */
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+
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+/* Exported functions ---------------------------------------------------------*/
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+
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+/** @defgroup CAN_Exported_Functions CAN Exported Functions
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+ * @{
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+ */
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+
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+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
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+ * @brief Initialization and Configuration functions
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+ *
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+@verbatim
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+ ==============================================================================
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+ ##### Initialization and de-initialization functions #####
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+ ==============================================================================
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+ [..] This section provides functions allowing to:
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+ (+) Initialize and configure the CAN.
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+ (+) De-initialize the CAN.
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+
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+@endverbatim
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+ * @{
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+ */
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+
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+/**
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+ * @brief Initializes the CAN peripheral according to the specified
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+ * parameters in the CAN_InitStruct.
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+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
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+ * the configuration information for the specified CAN.
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+ * @retval HAL status
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+ */
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+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
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+{
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+ uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
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+ uint32_t tickstart = 0U;
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+
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+ /* Check CAN handle */
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+ if(hcan == NULL)
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+ {
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+ return HAL_ERROR;
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+ }
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+
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+ /* Check the parameters */
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+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
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+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
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+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
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+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
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+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
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+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
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+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
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+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
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+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
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+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
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+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
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+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
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+
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+ if(hcan->State == HAL_CAN_STATE_RESET)
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+ {
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+ /* Allocate lock resource and initialize it */
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+ hcan->Lock = HAL_UNLOCKED;
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+ /* Init the low level hardware */
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+ HAL_CAN_MspInit(hcan);
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+ }
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+
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+ /* Initialize the CAN state*/
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+ hcan->State = HAL_CAN_STATE_BUSY;
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+
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+ /* Exit from sleep mode */
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
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+
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+ /* Request initialisation */
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
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+
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+ /* Get tick */
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+ tickstart = HAL_GetTick();
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+
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+ /* Wait the acknowledge */
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+ while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
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+ {
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+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
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+ {
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+ hcan->State= HAL_CAN_STATE_TIMEOUT;
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+ /* Process unlocked */
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+ __HAL_UNLOCK(hcan);
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+ return HAL_TIMEOUT;
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+ }
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+ }
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+
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+ /* Check acknowledge */
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+ if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
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+ {
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+ /* Set the time triggered communication mode */
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+ if (hcan->Init.TTCM == ENABLE)
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+ {
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
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+ }
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+ else
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+ {
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
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+ }
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+
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+ /* Set the automatic bus-off management */
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+ if (hcan->Init.ABOM == ENABLE)
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+ {
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
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+ }
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+ else
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+ {
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
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+ }
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+
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+ /* Set the automatic wake-up mode */
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+ if (hcan->Init.AWUM == ENABLE)
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+ {
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
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+ }
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+ else
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+ {
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
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+ }
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+
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+ /* Set the no automatic retransmission */
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+ if (hcan->Init.NART == ENABLE)
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+ {
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
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+ }
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+ else
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+ {
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
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+ }
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+
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+ /* Set the receive FIFO locked mode */
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+ if (hcan->Init.RFLM == ENABLE)
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+ {
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
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+ }
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+ else
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+ {
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
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+ }
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+
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+ /* Set the transmit FIFO priority */
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+ if (hcan->Init.TXFP == ENABLE)
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+ {
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+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
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+ }
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+ else
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+ {
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
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+ }
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+
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+ /* Set the bit timing register */
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+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
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+ hcan->Init.SJW |
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+ hcan->Init.BS1 |
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+ hcan->Init.BS2 |
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+ (hcan->Init.Prescaler - 1U) ));
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+
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+ /* Request leave initialisation */
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+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
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+
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+ /* Get tick */
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+ tickstart = HAL_GetTick();
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+
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+ /* Wait the acknowledge */
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+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
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+ {
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+ if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
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+ {
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+ hcan->State= HAL_CAN_STATE_TIMEOUT;
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+
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+ /* Process unlocked */
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+ __HAL_UNLOCK(hcan);
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+
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+ return HAL_TIMEOUT;
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+ }
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+ }
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+
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+ /* Check acknowledged */
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+ if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
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+ {
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+ status = CAN_INITSTATUS_SUCCESS;
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+ }
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+ }
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+
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+ if(status == CAN_INITSTATUS_SUCCESS)
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+ {
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+ /* Set CAN error code to none */
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+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
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+
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+ /* Initialize the CAN state */
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+ hcan->State = HAL_CAN_STATE_READY;
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+
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+ /* Return function status */
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+ return HAL_OK;
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+ }
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+ else
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+ {
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+ /* Initialize the CAN state */
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+ hcan->State = HAL_CAN_STATE_ERROR;
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+
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+ /* Return function status */
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+ return HAL_ERROR;
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+ }
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+}
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+
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+/**
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+ * @brief Configures the CAN reception filter according to the specified
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+ * parameters in the CAN_FilterInitStruct.
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+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
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+ * the configuration information for the specified CAN.
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+ * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
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+ * contains the filter configuration information.
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+ * @retval None
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+ */
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+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
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+{
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+ uint32_t filternbrbitpos = 0U;
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+
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+ /* Check the parameters */
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+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
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+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
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+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
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+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
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+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
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+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
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+
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+ filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
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+
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+ /* Initialisation mode for the filter */
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+ /* Select the start slave bank */
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+ MODIFY_REG(hcan->Instance->FMR ,
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+ CAN_FMR_CAN2SB ,
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+ CAN_FMR_FINIT |
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+ (uint32_t)(sFilterConfig->BankNumber << 8U) ); /* Filter Deactivation */
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+ CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
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+
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+ /* Filter Scale */
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+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
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+ {
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+ /* 16-bit scale for the filter */
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+ CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
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+
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+ /* First 16-bit identifier and First 16-bit mask */
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+ /* Or First 16-bit identifier and Second 16-bit identifier */
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+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
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+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
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+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
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+
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+ /* Second 16-bit identifier and Second 16-bit mask */
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+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
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+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
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+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
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+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
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+ }
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+
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+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
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+ {
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+ /* 32-bit scale for the filter */
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+ SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
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+
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+ /* 32-bit identifier or First 32-bit identifier */
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+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
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+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
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+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
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+
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+ /* 32-bit mask or Second 32-bit identifier */
|
|
|
+ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
|
|
|
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
|
|
|
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Filter Mode */
|
|
|
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
|
|
|
+ {
|
|
|
+ /*Id/Mask mode for the filter*/
|
|
|
+ CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
|
|
|
+ }
|
|
|
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
|
|
|
+ {
|
|
|
+ /*Identifier list mode for the filter*/
|
|
|
+ SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Filter FIFO assignment */
|
|
|
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
|
|
|
+ {
|
|
|
+ /* FIFO 0 assignation for the filter */
|
|
|
+ CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* FIFO 1 assignation for the filter */
|
|
|
+ SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Filter activation */
|
|
|
+ if (sFilterConfig->FilterActivation == ENABLE)
|
|
|
+ {
|
|
|
+ SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Leave the initialisation mode for the filter */
|
|
|
+ CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Check CAN handle */
|
|
|
+ if(hcan == NULL)
|
|
|
+ {
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY;
|
|
|
+
|
|
|
+ /* DeInit the low level hardware */
|
|
|
+ HAL_CAN_MspDeInit(hcan);
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_RESET;
|
|
|
+
|
|
|
+ /* Release Lock */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Initializes the CAN MSP.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hcan);
|
|
|
+
|
|
|
+ /* NOTE : This function Should not be modified, when the callback is needed,
|
|
|
+ the HAL_CAN_MspInit could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief DeInitializes the CAN MSP.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hcan);
|
|
|
+
|
|
|
+ /* NOTE : This function Should not be modified, when the callback is needed,
|
|
|
+ the HAL_CAN_MspDeInit could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
|
|
|
+ * @brief IO operation functions
|
|
|
+ *
|
|
|
+@verbatim
|
|
|
+ ==============================================================================
|
|
|
+ ##### IO operation functions #####
|
|
|
+ ==============================================================================
|
|
|
+ [..] This section provides functions allowing to:
|
|
|
+ (+) Transmit a CAN frame message.
|
|
|
+ (+) Receive a CAN frame message.
|
|
|
+ (+) Enter CAN peripheral in sleep mode.
|
|
|
+ (+) Wake up the CAN peripheral from sleep mode.
|
|
|
+
|
|
|
+@endverbatim
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Initiates and transmits a CAN frame message.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @param Timeout Timeout duration.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
|
|
|
+{
|
|
|
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
|
|
|
+ uint32_t tickstart = 0U;
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
|
|
|
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
|
|
|
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
|
|
|
+
|
|
|
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
|
|
|
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
|
|
|
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
|
|
|
+ {
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hcan);
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_READY */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Select one empty transmit mailbox */
|
|
|
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
|
|
|
+ {
|
|
|
+ transmitmailbox = CAN_TXMAILBOX_0;
|
|
|
+ }
|
|
|
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
|
|
|
+ {
|
|
|
+ transmitmailbox = CAN_TXMAILBOX_1;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ transmitmailbox = CAN_TXMAILBOX_2;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set up the Id */
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
|
|
|
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
|
|
|
+ {
|
|
|
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
|
|
|
+ hcan->pTxMsg->RTR);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
|
|
|
+ hcan->pTxMsg->IDE | \
|
|
|
+ hcan->pTxMsg->RTR);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set up the DLC */
|
|
|
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
|
|
|
+
|
|
|
+ /* Set up the data field */
|
|
|
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
|
|
|
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
|
|
|
+
|
|
|
+ /* Request transmission */
|
|
|
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
|
|
|
+
|
|
|
+ /* Get tick */
|
|
|
+ tickstart = HAL_GetTick();
|
|
|
+
|
|
|
+ /* Check End of transmission flag */
|
|
|
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
|
|
|
+ {
|
|
|
+ /* Check for the Timeout */
|
|
|
+ if(Timeout != HAL_MAX_DELAY)
|
|
|
+ {
|
|
|
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
|
|
+ {
|
|
|
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
|
|
|
+
|
|
|
+ /* Cancel transmission */
|
|
|
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+ return HAL_TIMEOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_BUSY_TX */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_ERROR;
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Initiates and transmits a CAN frame message.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
|
|
|
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
|
|
|
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
|
|
|
+
|
|
|
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
|
|
|
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
|
|
|
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
|
|
|
+ {
|
|
|
+ /* Process Locked */
|
|
|
+ __HAL_LOCK(hcan);
|
|
|
+
|
|
|
+ /* Select one empty transmit mailbox */
|
|
|
+ if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
|
|
|
+ {
|
|
|
+ transmitmailbox = CAN_TXMAILBOX_0;
|
|
|
+ }
|
|
|
+ else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
|
|
|
+ {
|
|
|
+ transmitmailbox = CAN_TXMAILBOX_1;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ transmitmailbox = CAN_TXMAILBOX_2;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set up the Id */
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
|
|
|
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
|
|
|
+ {
|
|
|
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
|
|
|
+ hcan->pTxMsg->RTR);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
|
|
|
+ hcan->pTxMsg->IDE | \
|
|
|
+ hcan->pTxMsg->RTR);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set up the DLC */
|
|
|
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
|
|
|
+
|
|
|
+ /* Set up the data field */
|
|
|
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
|
|
|
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
|
|
|
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_READY */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set CAN error code to none */
|
|
|
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
|
|
|
+
|
|
|
+ /* Process Unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Request transmission */
|
|
|
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
|
|
|
+
|
|
|
+ /* Enable interrupts: */
|
|
|
+ /* - Enable Error warning Interrupt */
|
|
|
+ /* - Enable Error passive Interrupt */
|
|
|
+ /* - Enable Bus-off Interrupt */
|
|
|
+ /* - Enable Last error code Interrupt */
|
|
|
+ /* - Enable Error Interrupt */
|
|
|
+ /* - Enable Transmit mailbox empty Interrupt */
|
|
|
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
|
|
|
+ CAN_IT_EPV |
|
|
|
+ CAN_IT_BOF |
|
|
|
+ CAN_IT_LEC |
|
|
|
+ CAN_IT_ERR |
|
|
|
+ CAN_IT_TME );
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_ERROR;
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Receives a correct CAN frame.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @param FIFONumber FIFO number.
|
|
|
+ * @param Timeout Timeout duration.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
|
|
|
+{
|
|
|
+ uint32_t tickstart = 0U;
|
|
|
+ CanRxMsgTypeDef* pRxMsg = NULL;
|
|
|
+
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_CAN_FIFO(FIFONumber));
|
|
|
+
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hcan);
|
|
|
+
|
|
|
+ /* Check if CAN state is not busy for RX FIFO0 */
|
|
|
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
|
+ {
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ return HAL_BUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check if CAN state is not busy for RX FIFO1 */
|
|
|
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
|
+ {
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ return HAL_BUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ if (FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_READY */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_READY */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Get tick */
|
|
|
+ tickstart = HAL_GetTick();
|
|
|
+
|
|
|
+ /* Check pending message */
|
|
|
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
|
|
|
+ {
|
|
|
+ /* Check for the Timeout */
|
|
|
+ if(Timeout != HAL_MAX_DELAY)
|
|
|
+ {
|
|
|
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
|
|
+ {
|
|
|
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ return HAL_TIMEOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set RxMsg pointer */
|
|
|
+ if(FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ pRxMsg = hcan->pRxMsg;
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ pRxMsg = hcan->pRx1Msg;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Get the Id */
|
|
|
+ pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
|
|
|
+ if (pRxMsg->IDE == CAN_ID_STD)
|
|
|
+ {
|
|
|
+ pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
|
|
|
+ }
|
|
|
+ pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
|
|
|
+ /* Get the DLC */
|
|
|
+ pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
|
|
|
+ /* Get the FMI */
|
|
|
+ pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
|
|
|
+ /* Get the FIFONumber */
|
|
|
+ pRxMsg->FIFONumber = FIFONumber;
|
|
|
+ /* Get the data field */
|
|
|
+ pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
|
|
|
+ pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
|
|
|
+ pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
|
|
|
+ pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
|
|
|
+ pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
|
|
|
+ pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
|
|
|
+ pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
|
|
|
+ pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
|
|
|
+
|
|
|
+ /* Release the FIFO */
|
|
|
+ if(FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ /* Release FIFO0 */
|
|
|
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ /* Release FIFO1 */
|
|
|
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ if (FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Receives a correct CAN frame.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @param FIFONumber FIFO number.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
|
|
|
+{
|
|
|
+ /* Check the parameters */
|
|
|
+ assert_param(IS_CAN_FIFO(FIFONumber));
|
|
|
+
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hcan);
|
|
|
+
|
|
|
+ /* Check if CAN state is not busy for RX FIFO0 */
|
|
|
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
|
+ {
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ return HAL_BUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check if CAN state is not busy for RX FIFO1 */
|
|
|
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
|
|
|
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
|
|
|
+ {
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ return HAL_BUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ if (FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_READY */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_READY */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set CAN error code to none */
|
|
|
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
|
|
|
+
|
|
|
+ /* Enable interrupts: */
|
|
|
+ /* - Enable Error warning Interrupt */
|
|
|
+ /* - Enable Error passive Interrupt */
|
|
|
+ /* - Enable Bus-off Interrupt */
|
|
|
+ /* - Enable Last error code Interrupt */
|
|
|
+ /* - Enable Error Interrupt */
|
|
|
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
|
|
|
+ CAN_IT_EPV |
|
|
|
+ CAN_IT_BOF |
|
|
|
+ CAN_IT_LEC |
|
|
|
+ CAN_IT_ERR);
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ if(FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ /* Enable FIFO 0 overrun and message pending Interrupt */
|
|
|
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ /* Enable FIFO 1 overrun and message pending Interrupt */
|
|
|
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Enters the Sleep (low power) mode.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval HAL status.
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ uint32_t tickstart = 0U;
|
|
|
+
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hcan);
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY;
|
|
|
+
|
|
|
+ /* Request Sleep mode */
|
|
|
+ MODIFY_REG(hcan->Instance->MCR,
|
|
|
+ CAN_MCR_INRQ ,
|
|
|
+ CAN_MCR_SLEEP );
|
|
|
+
|
|
|
+ /* Sleep mode status */
|
|
|
+ if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
|
|
|
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
|
|
|
+ {
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Get tick */
|
|
|
+ tickstart = HAL_GetTick();
|
|
|
+
|
|
|
+ /* Wait the acknowledge */
|
|
|
+ while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
|
|
|
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
|
|
|
+ {
|
|
|
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
|
|
|
+ {
|
|
|
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+ return HAL_TIMEOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
|
|
|
+ * is in the normal mode.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval HAL status.
|
|
|
+ */
|
|
|
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ uint32_t tickstart = 0U;
|
|
|
+
|
|
|
+ /* Process locked */
|
|
|
+ __HAL_LOCK(hcan);
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY;
|
|
|
+
|
|
|
+ /* Wake up request */
|
|
|
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
|
|
|
+
|
|
|
+ /* Get tick */
|
|
|
+ tickstart = HAL_GetTick();
|
|
|
+
|
|
|
+ /* Sleep mode status */
|
|
|
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
|
|
|
+ {
|
|
|
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
|
|
|
+ {
|
|
|
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ return HAL_TIMEOUT;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
|
|
|
+ {
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+
|
|
|
+ /* Process unlocked */
|
|
|
+ __HAL_UNLOCK(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Handles CAN interrupt request
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
|
|
|
+
|
|
|
+ /* Check Overrun flag for FIFO0 */
|
|
|
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
|
|
|
+ {
|
|
|
+ /* Set CAN error code to FOV0 error */
|
|
|
+ errorcode |= HAL_CAN_ERROR_FOV0;
|
|
|
+
|
|
|
+ /* Clear FIFO0 Overrun Flag */
|
|
|
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check Overrun flag for FIFO1 */
|
|
|
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
|
|
|
+ {
|
|
|
+ /* Set CAN error code to FOV1 error */
|
|
|
+ errorcode |= HAL_CAN_ERROR_FOV1;
|
|
|
+
|
|
|
+ /* Clear FIFO1 Overrun Flag */
|
|
|
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check End of transmission flag */
|
|
|
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
|
|
|
+ {
|
|
|
+ /* Check Transmit request completion status */
|
|
|
+ if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
|
|
|
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
|
|
|
+ (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
|
|
|
+ {
|
|
|
+ /* Check Transmit success */
|
|
|
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
|
|
|
+ (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
|
|
|
+ (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
|
|
|
+ {
|
|
|
+ /* Call transmit function */
|
|
|
+ CAN_Transmit_IT(hcan);
|
|
|
+ }
|
|
|
+ else /* Transmit failure */
|
|
|
+ {
|
|
|
+ /* Set CAN error code to TXFAIL error */
|
|
|
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Clear transmission status flags (RQCPx and TXOKx) */
|
|
|
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
|
|
|
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check End of reception flag for FIFO0 */
|
|
|
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
|
|
|
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
|
|
|
+ {
|
|
|
+ /* Call receive function */
|
|
|
+ CAN_Receive_IT(hcan, CAN_FIFO0);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check End of reception flag for FIFO1 */
|
|
|
+ if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
|
|
|
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
|
|
|
+ {
|
|
|
+ /* Call receive function */
|
|
|
+ CAN_Receive_IT(hcan, CAN_FIFO1);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Set error code in handle */
|
|
|
+ hcan->ErrorCode |= errorcode;
|
|
|
+
|
|
|
+ /* Check Error Warning Flag */
|
|
|
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
|
|
|
+ {
|
|
|
+ /* Set CAN error code to EWG error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
|
|
|
+ /* No need for clear of Error Warning Flag as read-only */
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check Error Passive Flag */
|
|
|
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
|
|
|
+ {
|
|
|
+ /* Set CAN error code to EPV error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
|
|
|
+ /* No need for clear of Error Passive Flag as read-only */
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check Bus-Off Flag */
|
|
|
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
|
|
|
+ {
|
|
|
+ /* Set CAN error code to BOF error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
|
|
|
+ /* No need for clear of Bus-Off Flag as read-only */
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check Last error code Flag */
|
|
|
+ if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
|
|
|
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
|
|
|
+ {
|
|
|
+ switch(hcan->Instance->ESR & CAN_ESR_LEC)
|
|
|
+ {
|
|
|
+ case(CAN_ESR_LEC_0):
|
|
|
+ /* Set CAN error code to STF error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
|
|
|
+ break;
|
|
|
+ case(CAN_ESR_LEC_1):
|
|
|
+ /* Set CAN error code to FOR error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
|
|
|
+ break;
|
|
|
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
|
|
|
+ /* Set CAN error code to ACK error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
|
|
|
+ break;
|
|
|
+ case(CAN_ESR_LEC_2):
|
|
|
+ /* Set CAN error code to BR error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
|
|
|
+ break;
|
|
|
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
|
|
|
+ /* Set CAN error code to BD error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
|
|
|
+ break;
|
|
|
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
|
|
|
+ /* Set CAN error code to CRC error */
|
|
|
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Clear Last error code Flag */
|
|
|
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Call the Error call Back in case of Errors */
|
|
|
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
|
|
|
+ {
|
|
|
+ /* Clear ERRI Flag */
|
|
|
+ SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
|
|
|
+
|
|
|
+ /* Set the CAN state ready to be able to start again the process */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+
|
|
|
+ /* Disable interrupts: */
|
|
|
+ /* - Disable Error warning Interrupt */
|
|
|
+ /* - Disable Error passive Interrupt */
|
|
|
+ /* - Disable Bus-off Interrupt */
|
|
|
+ /* - Disable Last error code Interrupt */
|
|
|
+ /* - Disable Error Interrupt */
|
|
|
+ /* - Disable FIFO 0 message pending Interrupt */
|
|
|
+ /* - Disable FIFO 0 Overrun Interrupt */
|
|
|
+ /* - Disable FIFO 1 message pending Interrupt */
|
|
|
+ /* - Disable FIFO 1 Overrun Interrupt */
|
|
|
+ /* - Disable Transmit mailbox empty Interrupt */
|
|
|
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
|
|
|
+ CAN_IT_EPV |
|
|
|
+ CAN_IT_BOF |
|
|
|
+ CAN_IT_LEC |
|
|
|
+ CAN_IT_ERR |
|
|
|
+ CAN_IT_FMP0|
|
|
|
+ CAN_IT_FOV0|
|
|
|
+ CAN_IT_FMP1|
|
|
|
+ CAN_IT_FOV1|
|
|
|
+ CAN_IT_TME );
|
|
|
+
|
|
|
+ /* Call Error callback function */
|
|
|
+ HAL_CAN_ErrorCallback(hcan);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Transmission complete callback in non blocking mode
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hcan);
|
|
|
+
|
|
|
+ /* NOTE : This function Should not be modified, when the callback is needed,
|
|
|
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Transmission complete callback in non blocking mode
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hcan);
|
|
|
+
|
|
|
+ /* NOTE : This function Should not be modified, when the callback is needed,
|
|
|
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Error CAN callback.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
|
|
|
+{
|
|
|
+ /* Prevent unused argument(s) compilation warning */
|
|
|
+ UNUSED(hcan);
|
|
|
+
|
|
|
+ /* NOTE : This function Should not be modified, when the callback is needed,
|
|
|
+ the HAL_CAN_ErrorCallback could be implemented in the user file
|
|
|
+ */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
|
|
|
+ * @brief CAN Peripheral State functions
|
|
|
+ *
|
|
|
+@verbatim
|
|
|
+ ==============================================================================
|
|
|
+ ##### Peripheral State and Error functions #####
|
|
|
+ ==============================================================================
|
|
|
+ [..]
|
|
|
+ This subsection provides functions allowing to :
|
|
|
+ (+) Check the CAN state.
|
|
|
+ (+) Check CAN Errors detected during interrupt process
|
|
|
+
|
|
|
+@endverbatim
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief return the CAN state
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval HAL state
|
|
|
+ */
|
|
|
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Return CAN state */
|
|
|
+ return hcan->State;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Return the CAN error code
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval CAN Error Code
|
|
|
+ */
|
|
|
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
|
|
|
+{
|
|
|
+ return hcan->ErrorCode;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup CAN_Private_Functions CAN Private Functions
|
|
|
+ * @brief CAN Frame message Rx/Tx functions
|
|
|
+ *
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Initiates and transmits a CAN frame message.
|
|
|
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @retval HAL status
|
|
|
+ */
|
|
|
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
|
|
|
+{
|
|
|
+ /* Disable Transmit mailbox empty Interrupt */
|
|
|
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
|
|
|
+
|
|
|
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
|
|
|
+ {
|
|
|
+ /* Disable interrupts: */
|
|
|
+ /* - Disable Error warning Interrupt */
|
|
|
+ /* - Disable Error passive Interrupt */
|
|
|
+ /* - Disable Bus-off Interrupt */
|
|
|
+ /* - Disable Last error code Interrupt */
|
|
|
+ /* - Disable Error Interrupt */
|
|
|
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
|
|
|
+ CAN_IT_EPV |
|
|
|
+ CAN_IT_BOF |
|
|
|
+ CAN_IT_LEC |
|
|
|
+ CAN_IT_ERR );
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_BUSY_TX */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Transmission complete callback */
|
|
|
+ HAL_CAN_TxCpltCallback(hcan);
|
|
|
+
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Receives a correct CAN frame.
|
|
|
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
|
|
|
+ * the configuration information for the specified CAN.
|
|
|
+ * @param FIFONumber Specify the FIFO number
|
|
|
+ * @retval HAL status
|
|
|
+ * @retval None
|
|
|
+ */
|
|
|
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
|
|
|
+{
|
|
|
+ CanRxMsgTypeDef* pRxMsg = NULL;
|
|
|
+
|
|
|
+ /* Set RxMsg pointer */
|
|
|
+ if(FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ pRxMsg = hcan->pRxMsg;
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ pRxMsg = hcan->pRx1Msg;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Get the Id */
|
|
|
+ pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
|
|
|
+ if (pRxMsg->IDE == CAN_ID_STD)
|
|
|
+ {
|
|
|
+ pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
|
|
|
+ }
|
|
|
+ pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
|
|
|
+ /* Get the DLC */
|
|
|
+ pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
|
|
|
+ /* Get the FMI */
|
|
|
+ pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
|
|
|
+ /* Get the FIFONumber */
|
|
|
+ pRxMsg->FIFONumber = FIFONumber;
|
|
|
+ /* Get the data field */
|
|
|
+ pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
|
|
|
+ pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
|
|
|
+ pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
|
|
|
+ pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
|
|
|
+ pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
|
|
|
+ pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
|
|
|
+ pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
|
|
|
+ pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
|
|
|
+
|
|
|
+ /* Release the FIFO */
|
|
|
+ /* Release FIFO0 */
|
|
|
+ if (FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
|
|
|
+
|
|
|
+ /* Disable FIFO 0 overrun and message pending Interrupt */
|
|
|
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
|
|
|
+ }
|
|
|
+ /* Release FIFO1 */
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
|
|
|
+
|
|
|
+ /* Disable FIFO 1 overrun and message pending Interrupt */
|
|
|
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
|
|
|
+ }
|
|
|
+
|
|
|
+ if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
|
|
|
+ {
|
|
|
+ /* Disable interrupts: */
|
|
|
+ /* - Disable Error warning Interrupt */
|
|
|
+ /* - Disable Error passive Interrupt */
|
|
|
+ /* - Disable Bus-off Interrupt */
|
|
|
+ /* - Disable Last error code Interrupt */
|
|
|
+ /* - Disable Error Interrupt */
|
|
|
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
|
|
|
+ CAN_IT_EPV |
|
|
|
+ CAN_IT_BOF |
|
|
|
+ CAN_IT_LEC |
|
|
|
+ CAN_IT_ERR );
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Change CAN state */
|
|
|
+ if (FIFONumber == CAN_FIFO0)
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else /* FIFONumber == CAN_FIFO1 */
|
|
|
+ {
|
|
|
+ switch(hcan->State)
|
|
|
+ {
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
|
|
|
+ break;
|
|
|
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
|
|
|
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
|
|
|
+ break;
|
|
|
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
|
|
|
+ hcan->State = HAL_CAN_STATE_READY;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Receive complete callback */
|
|
|
+ HAL_CAN_RxCpltCallback(hcan);
|
|
|
+
|
|
|
+ /* Return function status */
|
|
|
+ return HAL_OK;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+#endif /* defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F091xC) || defined(STM32F098xx) */
|
|
|
+
|
|
|
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
yangjie