[BSP][stm32f103-100ask-pro]add ext_sram driver to stm32f103-100ask-pro

bsp/stm32/stm32f103-100ask-pro/README.md

@@ -45,6 +45,7 @@ STM32F103 Pro开发板是百问网推出的一块基于ARM Cortex-M3内核的开
 | 电位器       |     支持     | ADC1/2/3 CH10                                                |
 | SPI FLASH    |     支持     | W25Q64                                                       |
 | EEPROM       |     支持     | 软件i2c1                                                     |
+| SRAM         |     支持     | IS62WV51216BLL                                               |
 | **片上外设** | **支持情况** | **备注**                                                     |
 | GPIO         |     支持     | PA0, PA1... PK15 ---> PIN: 0, 1...176                        |
 | UART         |     支持     | UART1/2/3                                                    |

bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/CubeMX_Config.ioc

@@ -19,6 +19,12 @@ CAN.CalculateBaudRate=749999
 CAN.CalculateTimeBit=1333
 CAN.CalculateTimeQuantum=444.44444444444446
 CAN.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate
+FSMC.AddressSetupTime1=0
+FSMC.BusTurnAroundDuration1=0
+FSMC.DataSetupTime1=3
+FSMC.ExtendedMode1=FSMC_EXTENDED_MODE_DISABLE
+FSMC.IPParameters=WriteOperation1,ExtendedMode1,AddressSetupTime1,BusTurnAroundDuration1,DataSetupTime1
+FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
 File.Version=6
 GPIO.groupedBy=Group By Peripherals
 KeepUserPlacement=false
@@ -26,79 +32,120 @@ Mcu.CPN=STM32F103ZET6
 Mcu.Family=STM32F1
 Mcu.IP0=ADC1
 Mcu.IP1=ADC2
-Mcu.IP10=SPI2
-Mcu.IP11=SYS
-Mcu.IP12=TIM2
-Mcu.IP13=TIM3
-Mcu.IP14=TIM4
-Mcu.IP15=USART1
-Mcu.IP16=USART2
-Mcu.IP17=USART3
+Mcu.IP10=SPI1
+Mcu.IP11=SPI2
+Mcu.IP12=SYS
+Mcu.IP13=TIM2
+Mcu.IP14=TIM3
+Mcu.IP15=TIM4
+Mcu.IP16=USART1
+Mcu.IP17=USART2
+Mcu.IP18=USART3
 Mcu.IP2=ADC3
 Mcu.IP3=CAN
-Mcu.IP4=I2C1
-Mcu.IP5=NVIC
-Mcu.IP6=RCC
-Mcu.IP7=RTC
-Mcu.IP8=SDIO
-Mcu.IP9=SPI1
-Mcu.IPNb=18
+Mcu.IP4=FSMC
+Mcu.IP5=I2C1
+Mcu.IP6=NVIC
+Mcu.IP7=RCC
+Mcu.IP8=RTC
+Mcu.IP9=SDIO
+Mcu.IPNb=19
 Mcu.Name=STM32F103Z(C-D-E)Tx
 Mcu.Package=LQFP144
 Mcu.Pin0=PC14-OSC32_IN
 Mcu.Pin1=PC15-OSC32_OUT
-Mcu.Pin10=PB0
-Mcu.Pin11=PB1
-Mcu.Pin12=PB10
-Mcu.Pin13=PB11
-Mcu.Pin14=PB13
-Mcu.Pin15=PB14
-Mcu.Pin16=PB15
-Mcu.Pin17=PC8
-Mcu.Pin18=PC9
-Mcu.Pin19=PA9
-Mcu.Pin2=OSC_IN
-Mcu.Pin20=PA10
-Mcu.Pin21=PA13
-Mcu.Pin22=PA14
-Mcu.Pin23=PC10
-Mcu.Pin24=PC11
-Mcu.Pin25=PC12
-Mcu.Pin26=PD2
-Mcu.Pin27=PB5
-Mcu.Pin28=PB6
-Mcu.Pin29=PB7
-Mcu.Pin3=OSC_OUT
-Mcu.Pin30=PB8
-Mcu.Pin31=PB9
-Mcu.Pin32=VP_RTC_VS_RTC_Activate
-Mcu.Pin33=VP_SYS_VS_Systick
-Mcu.Pin34=VP_TIM2_VS_ClockSourceINT
-Mcu.Pin35=VP_TIM3_VS_ClockSourceINT
-Mcu.Pin36=VP_TIM4_VS_ClockSourceINT
-Mcu.Pin4=PC0
-Mcu.Pin5=PA2
-Mcu.Pin6=PA3
-Mcu.Pin7=PA5
-Mcu.Pin8=PA6
-Mcu.Pin9=PA7
-Mcu.PinsNb=37
+Mcu.Pin10=PC0
+Mcu.Pin11=PA2
+Mcu.Pin12=PA3
+Mcu.Pin13=PA5
+Mcu.Pin14=PA6
+Mcu.Pin15=PA7
+Mcu.Pin16=PB0
+Mcu.Pin17=PB1
+Mcu.Pin18=PF12
+Mcu.Pin19=PF13
+Mcu.Pin2=PF0
+Mcu.Pin20=PF14
+Mcu.Pin21=PF15
+Mcu.Pin22=PG0
+Mcu.Pin23=PG1
+Mcu.Pin24=PE7
+Mcu.Pin25=PE8
+Mcu.Pin26=PE9
+Mcu.Pin27=PE10
+Mcu.Pin28=PE11
+Mcu.Pin29=PE12
+Mcu.Pin3=PF1
+Mcu.Pin30=PE13
+Mcu.Pin31=PE14
+Mcu.Pin32=PE15
+Mcu.Pin33=PB10
+Mcu.Pin34=PB11
+Mcu.Pin35=PB13
+Mcu.Pin36=PB14
+Mcu.Pin37=PB15
+Mcu.Pin38=PD8
+Mcu.Pin39=PD9
+Mcu.Pin4=PF2
+Mcu.Pin40=PD10
+Mcu.Pin41=PD11
+Mcu.Pin42=PD12
+Mcu.Pin43=PD13
+Mcu.Pin44=PD14
+Mcu.Pin45=PD15
+Mcu.Pin46=PG2
+Mcu.Pin47=PG3
+Mcu.Pin48=PG4
+Mcu.Pin49=PG5
+Mcu.Pin5=PF3
+Mcu.Pin50=PC8
+Mcu.Pin51=PC9
+Mcu.Pin52=PA9
+Mcu.Pin53=PA10
+Mcu.Pin54=PA13
+Mcu.Pin55=PA14
+Mcu.Pin56=PC10
+Mcu.Pin57=PC11
+Mcu.Pin58=PC12
+Mcu.Pin59=PD0
+Mcu.Pin6=PF4
+Mcu.Pin60=PD1
+Mcu.Pin61=PD2
+Mcu.Pin62=PD4
+Mcu.Pin63=PD5
+Mcu.Pin64=PG10
+Mcu.Pin65=PB5
+Mcu.Pin66=PB6
+Mcu.Pin67=PB7
+Mcu.Pin68=PB8
+Mcu.Pin69=PB9
+Mcu.Pin7=PF5
+Mcu.Pin70=PE0
+Mcu.Pin71=PE1
+Mcu.Pin72=VP_RTC_VS_RTC_Activate
+Mcu.Pin73=VP_SYS_VS_Systick
+Mcu.Pin74=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin75=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin76=VP_TIM4_VS_ClockSourceINT
+Mcu.Pin8=OSC_IN
+Mcu.Pin9=OSC_OUT
+Mcu.PinsNb=77
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F103ZETx
 MxCube.Version=6.5.0
 MxDb.Version=DB.6.0.50
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.ForceEnableDMAVector=true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
-NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 OSC_IN.Mode=HSE-External-Oscillator
 OSC_IN.Signal=RCC_OSC_IN
 OSC_OUT.Mode=HSE-External-Oscillator
@@ -163,8 +210,49 @@ PC8.Mode=SD_4_bits_Wide_bus
 PC8.Signal=SDIO_D0
 PC9.Mode=SD_4_bits_Wide_bus
 PC9.Signal=SDIO_D1
+PD0.Signal=FSMC_D2_DA2
+PD1.Signal=FSMC_D3_DA3
+PD10.Signal=FSMC_D15_DA15
+PD11.Signal=FSMC_A16_CLE
+PD12.Signal=FSMC_A17_ALE
+PD13.Signal=FSMC_A18
+PD14.Signal=FSMC_D0_DA0
+PD15.Signal=FSMC_D1_DA1
 PD2.Mode=SD_4_bits_Wide_bus
 PD2.Signal=SDIO_CMD
+PD4.Signal=FSMC_NOE
+PD5.Signal=FSMC_NWE
+PD8.Signal=FSMC_D13_DA13
+PD9.Signal=FSMC_D14_DA14
+PE0.Signal=FSMC_NBL0
+PE1.Signal=FSMC_NBL1
+PE10.Signal=FSMC_D7_DA7
+PE11.Signal=FSMC_D8_DA8
+PE12.Signal=FSMC_D9_DA9
+PE13.Signal=FSMC_D10_DA10
+PE14.Signal=FSMC_D11_DA11
+PE15.Signal=FSMC_D12_DA12
+PE7.Signal=FSMC_D4_DA4
+PE8.Signal=FSMC_D5_DA5
+PE9.Signal=FSMC_D6_DA6
+PF0.Signal=FSMC_A0
+PF1.Signal=FSMC_A1
+PF12.Signal=FSMC_A6
+PF13.Signal=FSMC_A7
+PF14.Signal=FSMC_A8
+PF15.Signal=FSMC_A9
+PF2.Signal=FSMC_A2
+PF3.Signal=FSMC_A3
+PF4.Signal=FSMC_A4
+PF5.Signal=FSMC_A5
+PG0.Signal=FSMC_A10
+PG1.Signal=FSMC_A11
+PG10.Mode=NorPsramChipSelect3_1
+PG10.Signal=FSMC_NE3
+PG2.Signal=FSMC_A12
+PG3.Signal=FSMC_A13
+PG4.Signal=FSMC_A14
+PG5.Signal=FSMC_A15
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -193,7 +281,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN_Init-CAN-false-HAL-true,5-MX_I2C1_Init-I2C1-false-HAL-true,6-MX_SDIO_SD_Init-SDIO-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_SPI2_Init-SPI2-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USART2_UART_Init-USART2-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN_Init-CAN-false-HAL-true,5-MX_I2C1_Init-I2C1-false-HAL-true,6-MX_SDIO_SD_Init-SDIO-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_SPI2_Init-SPI2-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USART2_UART_Init-USART2-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true,12-MX_ADC2_Init-ADC2-false-HAL-true,13-MX_ADC3_Init-ADC3-false-HAL-true,14-MX_RTC_Init-RTC-false-HAL-true,15-MX_TIM2_Init-TIM2-false-HAL-true,16-MX_TIM3_Init-TIM3-false-HAL-true,17-MX_TIM4_Init-TIM4-false-HAL-true
 RCC.ADCFreqValue=12000000
 RCC.ADCPresc=RCC_ADCPCLK2_DIV6
 RCC.AHBFreq_Value=72000000
@@ -227,6 +315,84 @@ SH.ADCx_IN10.0=ADC1_IN10,IN10
 SH.ADCx_IN10.1=ADC2_IN10,IN10
 SH.ADCx_IN10.2=ADC3_IN10,IN10
 SH.ADCx_IN10.ConfNb=3
+SH.FSMC_A0.0=FSMC_A0,19b-a1
+SH.FSMC_A0.ConfNb=1
+SH.FSMC_A1.0=FSMC_A1,19b-a1
+SH.FSMC_A1.ConfNb=1
+SH.FSMC_A10.0=FSMC_A10,19b-a1
+SH.FSMC_A10.ConfNb=1
+SH.FSMC_A11.0=FSMC_A11,19b-a1
+SH.FSMC_A11.ConfNb=1
+SH.FSMC_A12.0=FSMC_A12,19b-a1
+SH.FSMC_A12.ConfNb=1
+SH.FSMC_A13.0=FSMC_A13,19b-a1
+SH.FSMC_A13.ConfNb=1
+SH.FSMC_A14.0=FSMC_A14,19b-a1
+SH.FSMC_A14.ConfNb=1
+SH.FSMC_A15.0=FSMC_A15,19b-a1
+SH.FSMC_A15.ConfNb=1
+SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1
+SH.FSMC_A16_CLE.ConfNb=1
+SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1
+SH.FSMC_A17_ALE.ConfNb=1
+SH.FSMC_A18.0=FSMC_A18,19b-a1
+SH.FSMC_A18.ConfNb=1
+SH.FSMC_A2.0=FSMC_A2,19b-a1
+SH.FSMC_A2.ConfNb=1
+SH.FSMC_A3.0=FSMC_A3,19b-a1
+SH.FSMC_A3.ConfNb=1
+SH.FSMC_A4.0=FSMC_A4,19b-a1
+SH.FSMC_A4.ConfNb=1
+SH.FSMC_A5.0=FSMC_A5,19b-a1
+SH.FSMC_A5.ConfNb=1
+SH.FSMC_A6.0=FSMC_A6,19b-a1
+SH.FSMC_A6.ConfNb=1
+SH.FSMC_A7.0=FSMC_A7,19b-a1
+SH.FSMC_A7.ConfNb=1
+SH.FSMC_A8.0=FSMC_A8,19b-a1
+SH.FSMC_A8.ConfNb=1
+SH.FSMC_A9.0=FSMC_A9,19b-a1
+SH.FSMC_A9.ConfNb=1
+SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1
+SH.FSMC_D0_DA0.ConfNb=1
+SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1
+SH.FSMC_D10_DA10.ConfNb=1
+SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1
+SH.FSMC_D11_DA11.ConfNb=1
+SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1
+SH.FSMC_D12_DA12.ConfNb=1
+SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1
+SH.FSMC_D13_DA13.ConfNb=1
+SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1
+SH.FSMC_D14_DA14.ConfNb=1
+SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1
+SH.FSMC_D15_DA15.ConfNb=1
+SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1
+SH.FSMC_D1_DA1.ConfNb=1
+SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1
+SH.FSMC_D2_DA2.ConfNb=1
+SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1
+SH.FSMC_D3_DA3.ConfNb=1
+SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1
+SH.FSMC_D4_DA4.ConfNb=1
+SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1
+SH.FSMC_D5_DA5.ConfNb=1
+SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1
+SH.FSMC_D6_DA6.ConfNb=1
+SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1
+SH.FSMC_D7_DA7.ConfNb=1
+SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1
+SH.FSMC_D8_DA8.ConfNb=1
+SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1
+SH.FSMC_D9_DA9.ConfNb=1
+SH.FSMC_NBL0.0=FSMC_NBL0,2ByteEnable1
+SH.FSMC_NBL0.ConfNb=1
+SH.FSMC_NBL1.0=FSMC_NBL1,2ByteEnable1
+SH.FSMC_NBL1.ConfNb=1
+SH.FSMC_NOE.0=FSMC_NOE,Sram1
+SH.FSMC_NOE.ConfNb=1
+SH.FSMC_NWE.0=FSMC_NWE,Sram1
+SH.FSMC_NWE.ConfNb=1
 SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2
 SH.S_TIM3_CH2.ConfNb=1
 SH.S_TIM3_CH3.0=TIM3_CH3,PWM Generation3 CH3

bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h

@@ -63,7 +63,7 @@
 /*#define HAL_SDRAM_MODULE_ENABLED   */
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
-/*#define HAL_SRAM_MODULE_ENABLED   */
+#define HAL_SRAM_MODULE_ENABLED
 #define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */

bsp/stm32/stm32f103-100ask-pro/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c

@@ -870,6 +870,190 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
 
 }
 
+static uint32_t FSMC_Initialized = 0;
+
+static void HAL_FSMC_MspInit(void){
+  /* USER CODE BEGIN FSMC_MspInit 0 */
+
+  /* USER CODE END FSMC_MspInit 0 */
+  GPIO_InitTypeDef GPIO_InitStruct ={0};
+  if (FSMC_Initialized) {
+    return;
+  }
+  FSMC_Initialized = 1;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_FSMC_CLK_ENABLE();
+
+  /** FSMC GPIO Configuration
+  PF0   ------> FSMC_A0
+  PF1   ------> FSMC_A1
+  PF2   ------> FSMC_A2
+  PF3   ------> FSMC_A3
+  PF4   ------> FSMC_A4
+  PF5   ------> FSMC_A5
+  PF12   ------> FSMC_A6
+  PF13   ------> FSMC_A7
+  PF14   ------> FSMC_A8
+  PF15   ------> FSMC_A9
+  PG0   ------> FSMC_A10
+  PG1   ------> FSMC_A11
+  PE7   ------> FSMC_D4
+  PE8   ------> FSMC_D5
+  PE9   ------> FSMC_D6
+  PE10   ------> FSMC_D7
+  PE11   ------> FSMC_D8
+  PE12   ------> FSMC_D9
+  PE13   ------> FSMC_D10
+  PE14   ------> FSMC_D11
+  PE15   ------> FSMC_D12
+  PD8   ------> FSMC_D13
+  PD9   ------> FSMC_D14
+  PD10   ------> FSMC_D15
+  PD11   ------> FSMC_A16
+  PD12   ------> FSMC_A17
+  PD13   ------> FSMC_A18
+  PD14   ------> FSMC_D0
+  PD15   ------> FSMC_D1
+  PG2   ------> FSMC_A12
+  PG3   ------> FSMC_A13
+  PG4   ------> FSMC_A14
+  PG5   ------> FSMC_A15
+  PD0   ------> FSMC_D2
+  PD1   ------> FSMC_D3
+  PD4   ------> FSMC_NOE
+  PD5   ------> FSMC_NWE
+  PG10   ------> FSMC_NE3
+  PE0   ------> FSMC_NBL0
+  PE1   ------> FSMC_NBL1
+  */
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
+                          |GPIO_PIN_14|GPIO_PIN_15;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+                          |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+                          |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
+                          |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN FSMC_MspInit 1 */
+
+  /* USER CODE END FSMC_MspInit 1 */
+}
+
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
+  /* USER CODE BEGIN SRAM_MspInit 0 */
+
+  /* USER CODE END SRAM_MspInit 0 */
+  HAL_FSMC_MspInit();
+  /* USER CODE BEGIN SRAM_MspInit 1 */
+
+  /* USER CODE END SRAM_MspInit 1 */
+}
+
+static uint32_t FSMC_DeInitialized = 0;
+
+static void HAL_FSMC_MspDeInit(void){
+  /* USER CODE BEGIN FSMC_MspDeInit 0 */
+
+  /* USER CODE END FSMC_MspDeInit 0 */
+  if (FSMC_DeInitialized) {
+    return;
+  }
+  FSMC_DeInitialized = 1;
+  /* Peripheral clock enable */
+  __HAL_RCC_FSMC_CLK_DISABLE();
+
+  /** FSMC GPIO Configuration
+  PF0   ------> FSMC_A0
+  PF1   ------> FSMC_A1
+  PF2   ------> FSMC_A2
+  PF3   ------> FSMC_A3
+  PF4   ------> FSMC_A4
+  PF5   ------> FSMC_A5
+  PF12   ------> FSMC_A6
+  PF13   ------> FSMC_A7
+  PF14   ------> FSMC_A8
+  PF15   ------> FSMC_A9
+  PG0   ------> FSMC_A10
+  PG1   ------> FSMC_A11
+  PE7   ------> FSMC_D4
+  PE8   ------> FSMC_D5
+  PE9   ------> FSMC_D6
+  PE10   ------> FSMC_D7
+  PE11   ------> FSMC_D8
+  PE12   ------> FSMC_D9
+  PE13   ------> FSMC_D10
+  PE14   ------> FSMC_D11
+  PE15   ------> FSMC_D12
+  PD8   ------> FSMC_D13
+  PD9   ------> FSMC_D14
+  PD10   ------> FSMC_D15
+  PD11   ------> FSMC_A16
+  PD12   ------> FSMC_A17
+  PD13   ------> FSMC_A18
+  PD14   ------> FSMC_D0
+  PD15   ------> FSMC_D1
+  PG2   ------> FSMC_A12
+  PG3   ------> FSMC_A13
+  PG4   ------> FSMC_A14
+  PG5   ------> FSMC_A15
+  PD0   ------> FSMC_D2
+  PD1   ------> FSMC_D3
+  PD4   ------> FSMC_NOE
+  PD5   ------> FSMC_NWE
+  PG10   ------> FSMC_NE3
+  PE0   ------> FSMC_NBL0
+  PE1   ------> FSMC_NBL1
+  */
+  HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
+                          |GPIO_PIN_14|GPIO_PIN_15);
+
+  HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10);
+
+  HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+                          |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
+
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
+                          |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
+                          |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
+
+  /* USER CODE BEGIN FSMC_MspDeInit 1 */
+
+  /* USER CODE END FSMC_MspDeInit 1 */
+}
+
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){
+  /* USER CODE BEGIN SRAM_MspDeInit 0 */
+
+  /* USER CODE END SRAM_MspDeInit 0 */
+  HAL_FSMC_MspDeInit();
+  /* USER CODE BEGIN SRAM_MspDeInit 1 */
+
+  /* USER CODE END SRAM_MspDeInit 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */

bsp/stm32/stm32f103-100ask-pro/board/Kconfig

@@ -37,6 +37,12 @@ menu "Onboard Peripheral Drivers"
         select BSP_USING_I2C1
         default n
 
+    config BSP_USING_EXT_SRAM
+        bool "Enable external sram"
+        default n
+        help
+            Chip name is IS62WV51216BLL, 1Mbytes static RAMs organized as 512K words by 16bits.
+
 endmenu
 
 menu "On-chip Peripheral Drivers"

bsp/stm32/stm32f103-100ask-pro/board/SConscript

@@ -12,6 +12,9 @@ board.c
 CubeMX_Config/Src/stm32f1xx_hal_msp.c
 ''')
 
+if GetDepend(['BSP_USING_EXT_SRAM']):
+    src += Glob('ports/drv_sram.c')
+
 if GetDepend(['BSP_USING_SPI_FLASH']):
     src += Glob('ports/spi_flash_init.c')
 

bsp/stm32/stm32f103-100ask-pro/board/ports/drv_sram.c

@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-01-05     linyiyang    first version
+ * 2024-05-28     WKjay        add this file to stm32f103-100ask-pro
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef BSP_USING_EXT_SRAM
+#include <sram_port.h>
+
+#define DRV_DEBUG
+#define LOG_TAG             "drv.ext_sram"
+#include <drv_log.h>
+
+static SRAM_HandleTypeDef hsram1;
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+static struct rt_memheap system_heap;
+#endif
+
+static int external_sram_init(void)
+{
+    int result = RT_EOK;
+
+    FSMC_NORSRAM_TimingTypeDef Timing = {0};
+
+    /** Perform the SRAM1 memory initialization sequence
+    */
+    hsram1.Instance                 = FSMC_NORSRAM_DEVICE;
+    hsram1.Extended                 = FSMC_NORSRAM_EXTENDED_DEVICE;
+
+    /* hsram1.Init */
+    hsram1.Init.NSBank              = FSMC_NORSRAM_BANK3;
+    hsram1.Init.DataAddressMux      = FSMC_DATA_ADDRESS_MUX_DISABLE;
+    hsram1.Init.MemoryType          = FSMC_MEMORY_TYPE_SRAM;
+#if EXTERNAL_SRAM_DATA_WIDTH == 8
+    hsram1.Init.MemoryDataWidth     = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
+#elif EXTERNAL_SRAM_DATA_WIDTH == 16
+    hsram1.Init.MemoryDataWidth     = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
+#else
+    hsram1.Init.MemoryDataWidth     = FSMC_NORSRAM_MEM_BUS_WIDTH_32;
+#endif
+    hsram1.Init.BurstAccessMode     = FSMC_BURST_ACCESS_MODE_DISABLE;
+    hsram1.Init.WaitSignalPolarity  = FSMC_WAIT_SIGNAL_POLARITY_LOW;
+    hsram1.Init.WrapMode            = FSMC_WRAP_MODE_DISABLE;
+    hsram1.Init.WaitSignalActive    = FSMC_WAIT_TIMING_BEFORE_WS;
+    hsram1.Init.WriteOperation      = FSMC_WRITE_OPERATION_ENABLE;
+    hsram1.Init.WaitSignal          = FSMC_WAIT_SIGNAL_DISABLE;
+    hsram1.Init.ExtendedMode        = FSMC_EXTENDED_MODE_DISABLE;
+    hsram1.Init.AsynchronousWait    = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
+    hsram1.Init.WriteBurst          = FSMC_WRITE_BURST_DISABLE;
+
+    /* Timing */
+    Timing.AddressSetupTime         = 0;
+    Timing.AddressHoldTime          = 15;
+    Timing.DataSetupTime            = 3;
+    Timing.BusTurnAroundDuration    = 0;
+    Timing.CLKDivision              = 16;
+    Timing.DataLatency              = 17;
+    Timing.AccessMode               = FSMC_ACCESS_MODE_A;
+    /* ExtTiming */
+
+    /* Initialize the SRAM controller */
+    if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
+    {
+        LOG_E("External SRAM init failed!");
+        result = -RT_ERROR;
+    }
+    else
+    {
+        LOG_D("External sram init success, mapped at 0x%X, size is %d bytes, data width is %d", EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE, EXTERNAL_SRAM_DATA_WIDTH);
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+        /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
+        rt_memheap_init(&system_heap, "ext_sram", (void *)EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE);
+#endif
+    }
+
+    /** Disconnect NADV
+    */
+
+    __HAL_AFIO_FSMCNADV_DISCONNECTED();
+
+    return result;
+}
+INIT_BOARD_EXPORT(external_sram_init);
+
+#ifdef DRV_DEBUG
+#ifdef FINSH_USING_MSH
+int external_sram_test(void)
+{
+    int i = 0;
+    uint32_t start_time = 0, time_cast = 0;
+#if EXTERNAL_SRAM_DATA_WIDTH == 8
+    char data_width = 1;
+    uint8_t data = 0;
+    uint8_t *ptr = (uint8_t *)EXTERNAL_SRAM_BANK_ADDR;
+#elif EXTERNAL_SRAM_DATA_WIDTH == 16
+    char data_width = 2;
+    uint16_t data = 0;
+    uint16_t *ptr = (uint16_t *)EXTERNAL_SRAM_BANK_ADDR;
+#else
+    char data_width = 4;
+    uint32_t data = 0;
+    uint32_t *ptr = (uint32_t *)EXTERNAL_SRAM_BANK_ADDR;
+#endif
+
+    /* write data */
+    LOG_D("Writing the %ld bytes data, waiting....", EXTERNAL_SRAM_SIZE);
+    start_time = rt_tick_get();
+    for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
+    {
+#if EXTERNAL_SRAM_DATA_WIDTH == 8
+        ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
+#elif EXTERNAL_SRAM_DATA_WIDTH == 16
+        ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
+#else
+        ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
+#endif
+    }
+    time_cast = rt_tick_get() - start_time;
+    LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
+          time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
+
+    /* read data */
+    LOG_D("start Reading and verifying data, waiting....");
+    for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
+    {
+#if EXTERNAL_SRAM_DATA_WIDTH == 8
+        data = ((__IO uint8_t *)ptr)[i];
+        if (data != 0x55)
+        {
+            LOG_E("External SRAM test failed!");
+            break;
+        }
+#elif EXTERNAL_SRAM_DATA_WIDTH == 16
+        data = ((__IO uint16_t *)ptr)[i];
+        if (data != 0x5555)
+        {
+            LOG_E("External SRAM test failed!");
+            break;
+        }
+#else
+        data = ((__IO uint32_t *)ptr)[i];
+        if (data != 0x55555555)
+        {
+            LOG_E("External SRAM test failed!");
+            break;
+        }
+#endif
+    }
+
+    if (i >= EXTERNAL_SRAM_SIZE / data_width)
+    {
+        LOG_D("External SRAM test success!");
+    }
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(external_sram_test, sram test);
+#endif /* FINSH_USING_MSH */
+#endif /* DRV_DEBUG */
+#endif /* BSP_USING_EXT_SRAM */

bsp/stm32/stm32f103-100ask-pro/board/ports/sram_port.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-01-05     linyiyang    first version
+ * 2024-05-28     WKjay        add this file to stm32f103-100ask-pro
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+/* stm32f1 Bank1:0x68000000 */
+#define EXTERNAL_SRAM_BANK_ADDR         ((uint32_t)0x68000000)
+/* data width: 8, 16, 32 */
+#define EXTERNAL_SRAM_DATA_WIDTH        16
+/* sram size */
+#define EXTERNAL_SRAM_SIZE              ((uint32_t)0x100000)
+
+#endif