[bsp/gd32]Complete the pins device define.

bsp/gd32/libraries/gd32_drivers/drv_gpio.c

@@ -18,6 +18,7 @@
 
 static const struct pin_index pins[] =
 {
+    /* GPIOA 0-15 */
     GD32_PIN(0,  A, 0),
     GD32_PIN(1,  A, 1),
     GD32_PIN(2,  A, 2),
@@ -34,6 +35,7 @@ static const struct pin_index pins[] =
     GD32_PIN(13, A, 13),
     GD32_PIN(14, A, 14),
     GD32_PIN(15, A, 15),
+    /* GPIOB 0-15 */
     GD32_PIN(16, B, 0),
     GD32_PIN(17, B, 1),
     GD32_PIN(18, B, 2),
@@ -50,6 +52,7 @@ static const struct pin_index pins[] =
     GD32_PIN(39, B, 13),
     GD32_PIN(30, B, 14),
     GD32_PIN(31, B, 15),
+    /* GPIOC 0-15 */
     GD32_PIN(32, C, 0),
     GD32_PIN(33, C, 1),
     GD32_PIN(34, C, 2),
@@ -66,6 +69,9 @@ static const struct pin_index pins[] =
     GD32_PIN(45, C, 13),
     GD32_PIN(46, C, 14),
     GD32_PIN(47, C, 15),
+    /* GPIOD 0-15 */
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
     GD32_PIN(50, D, 2),
     GD32_PIN_DEFAULT,
     GD32_PIN_DEFAULT,
@@ -80,6 +86,24 @@ static const struct pin_index pins[] =
     GD32_PIN_DEFAULT,
     GD32_PIN_DEFAULT,
     GD32_PIN_DEFAULT,
+    /* GPIOE 0-15 */
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN(66, E, 2),
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    /* GPIOF 0-15 */
     GD32_PIN(64, F, 0),
     GD32_PIN(65, F, 1),
     GD32_PIN_DEFAULT,
@@ -96,6 +120,53 @@ static const struct pin_index pins[] =
     GD32_PIN_DEFAULT,
     GD32_PIN_DEFAULT,
     GD32_PIN_DEFAULT,
+    /* GPIOG 0-15 */
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    /* GPIOH 0-15 */
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    /* GPIOI 0-11 */
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
+    GD32_PIN_DEFAULT,
 };
 
 static const struct pin_irq_map pin_irq_map[] =