Merge branch 'master' into libc_stdio

.github/workflows/action.yml

@@ -59,6 +59,7 @@ jobs:
          - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
          - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
+         - {RTT_BSP: "ls2kdev", RTT_TOOL_CHAIN: "sourcery-mips"}
          - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}

.ignore_format.yml

@@ -1,25 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-file_path:
-- bsp/allwinner_tina/libcpu/cpu.c
-
-dir_path:
-- tools
-- components/net/lwip-1.4.1
-- components/net/lwip-2.0.2
-- components/net/lwip-2.0.3
-- components/net/lwip-2.1.2
-- bsp/mm32f327x/Libraries
-- bsp/fm33lc026/libraries
-- bsp/stm32/libraries/STM32F0xx_HAL
-- bsp/stm32/libraries/STM32F2xx_HAL
-- bsp/stm32/libraries/STM32F4xx_HAL
-- bsp/stm32/libraries/STM32F7xx_HAL
-- bsp/stm32/libraries/STM32G0xx_HAL
-- bsp/stm32/libraries/STM32G4xx_HAL
-- bsp/stm32/libraries/STM32L4xx_HAL
-- bsp/stm32/libraries/STM32MPxx_HAL
-- bsp/stm32/libraries/STM32WBxx_HAL
-- bsp/stm32/libraries/STM32H7xx_HAL

bsp/fm33lc026/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/hc32f4a0/SConstruct

@@ -2,13 +2,13 @@ import os
 import sys
 import rtconfig
 
-print "############sconstruct##############"
+print("############sconstruct##############")
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
     RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
 
-print "RTT_ROOT: " + RTT_ROOT
+print("RTT_ROOT: " + RTT_ROOT)
 
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 try:
@@ -37,8 +37,8 @@ Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-print "######################env:"
-print env 
+print("######################env:")
+print(env)
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
 # make a building

bsp/hc32f4a0/rtconfig.py

@@ -5,12 +5,12 @@ ARCH='arm'
 CPU='cortex-m4'
 CROSS_TOOL='iar'
 
-print "############rtconfig##############"
+print("############rtconfig##############")
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
-print "CROSS_TOOL: " + CROSS_TOOL
+print("CROSS_TOOL: " + CROSS_TOOL)
 
 # cross_tool provides the cross compiler
 # EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR

bsp/lpc55sxx/lpc55s69_nxp_evk/.config

@@ -24,6 +24,13 @@ CONFIG_IDLE_THREAD_STACK_SIZE=256
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
 CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_COLOR is not set
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -55,6 +62,7 @@ CONFIG_RT_USING_MEMPOOL=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -67,7 +75,8 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
-CONFIG_RT_VER_NUM=0x40002
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_ARM_CORTEX_FPU=y
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -89,36 +98,25 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
 CONFIG_FINSH_ARG_MAX=10
 
 #
 # Device virtual file system
 #
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS is not set
 
 #
 # Device Drivers
@@ -127,37 +125,25 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
-CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
-CONFIG_RT_USING_I2C=y
-# CONFIG_RT_I2C_DEBUG is not set
-CONFIG_RT_USING_I2C_BITOPS=y
-# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
-CONFIG_RT_USING_ADC=y
-CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-CONFIG_RT_USING_RTC=y
-# CONFIG_RT_USING_ALARM is not set
-# CONFIG_RT_USING_SOFT_RTC is not set
-CONFIG_RT_USING_SDIO=y
-CONFIG_RT_SDIO_STACK_SIZE=512
-CONFIG_RT_SDIO_THREAD_PRIORITY=15
-CONFIG_RT_MMCSD_STACK_SIZE=1024
-CONFIG_RT_MMCSD_THREAD_PREORITY=22
-CONFIG_RT_MMCSD_MAX_PARTITION=16
-# CONFIG_RT_SDIO_DEBUG is not set
-CONFIG_RT_USING_SPI=y
-# CONFIG_RT_USING_QSPI is not set
-# CONFIG_RT_USING_SPI_MSD is not set
-# CONFIG_RT_USING_SFUD is not set
-# CONFIG_RT_USING_ENC28J60 is not set
-# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@@ -176,13 +162,9 @@ CONFIG_RT_USING_SPI=y
 #
 # POSIX layer and C standard library
 #
-CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
-# CONFIG_RT_USING_MODULE is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
 
 #
 # Network
@@ -219,6 +201,12 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
 
 #
 # RT-Thread online packages
@@ -227,11 +215,15 @@ CONFIG_RT_USING_POSIX=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -258,10 +250,12 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
 
 #
 # IoT Cloud
@@ -270,8 +264,10 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -280,13 +276,28 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LIBRWS is not set
 # CONFIG_PKG_USING_TCPSERVER is not set
 # CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
 # CONFIG_PKG_USING_ABUP_FOTA is not set
 # CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -294,6 +305,8 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -301,6 +314,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
 
 #
 # multimedia packages
@@ -310,6 +324,13 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
 
 #
 # tools packages
@@ -318,35 +339,95 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
 
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
 # CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
 
 #
 # peripheral libraries and drivers
@@ -355,6 +436,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -363,10 +445,13 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_SX12XX is not set
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@@ -379,42 +464,110 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
 
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
 CONFIG_SOC_LPC55S6X_SERIES=y
 
 #
@@ -432,37 +585,21 @@ CONFIG_BSP_USING_UART0=y
 # CONFIG_HW_UART0_BAUDRATE_9600 is not set
 CONFIG_HW_UART0_BAUDRATE_115200=y
 # CONFIG_BSP_USING_UART2 is not set
-CONFIG_BSP_USING_I2C=y
-# CONFIG_BSP_USING_I2C1 is not set
-CONFIG_BSP_USING_I2C4=y
-CONFIG_HW_I2C4_BAUDRATE_100kHZ=y
-# CONFIG_HW_I2C4_BAUDRATE_400kHZ is not set
-CONFIG_BSP_USING_SPI=y
-# CONFIG_BSP_USING_SPI3 is not set
-CONFIG_BSP_USING_SPI8=y
-CONFIG_BSP_USING_ADC=y
-CONFIG_BSP_USING_ADC0_CH0=y
-# CONFIG_BSP_USING_ADC0_CH1 is not set
-CONFIG_BSP_USING_SDIO=y
-CONFIG_BSP_USING_RTC=y
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_WDT is not set
-CONFIG_BSP_USING_HWTIMER=y
-CONFIG_BSP_USING_CTIMER0=y
-# CONFIG_BSP_USING_CTIMER1 is not set
-# CONFIG_BSP_USING_CTIMER3 is not set
-# CONFIG_BSP_USING_CTIMER4 is not set
-CONFIG_BSP_USING_PWM=y
-CONFIG_BSP_USING_CTIMER2_MAT0=y
-# CONFIG_BSP_USING_CTIMER2_MAT1 is not set
-# CONFIG_BSP_USING_CTIMER2_MAT2 is not set
+# CONFIG_BSP_USING_HWTIMER is not set
+# CONFIG_BSP_USING_PWM is not set
 
 #
 # Onboard Peripheral Drivers
 #
 CONFIG_BSP_USING_LED=y
 CONFIG_BSP_USING_KEY=y
-CONFIG_BSP_USING_MMA8562=y
-CONFIG_BSP_USING_MMA8562I2C="i2c4"
+# CONFIG_BSP_USING_MMA8562 is not set
 
 #
 # Board extended module Drivers

bsp/lpc55sxx/lpc55s69_nxp_evk/applications/SConscript

@@ -2,7 +2,7 @@ import rtconfig
 from building import *
 
 cwd = GetCurrentDir()
-src = Glob('*.c')
+src = Glob('main.c')
 CPPPATH = [cwd]
 
 # add for startup script 

bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c

@@ -8,6 +8,7 @@
  * Date           Author       Notes
  * 2019-10-24     Magicoe      first version
  * 2020-01-10     Kevin/Karl   Add PS demo
+ * 2020-09-21     supperthomas fix the main.c
  *
  */
 
@@ -18,12 +19,9 @@
 /* GPIO1_4 is Blue LED */
 #define LEDB_PIN      GET_PINS(1, 4)
 
-extern void protected_storage_demo_thread(void * parameters);
 
 int main(void)
 {
-    rt_thread_t t_psa_ps_demo;
-
 #if defined(__CC_ARM)
     rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION);
 #elif defined(__CLANG_ARM)
@@ -34,14 +32,6 @@ int main(void)
     rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__);
 #endif
 
-    t_psa_ps_demo = rt_thread_create("psa_ps_demo",
-                                     protected_storage_demo_thread,
-                                     RT_NULL,
-                                     512,
-                                     ( RT_MAIN_THREAD_PRIORITY - 1),
-                                     50);
-    if (t_psa_ps_demo != RT_NULL) rt_thread_startup(t_psa_ps_demo);
-
     rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT);  /* Set GPIO as Output */
     while (1)
     {

bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h

@@ -31,6 +31,7 @@
 // </RDTConfigurator>
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$ARM_LIB_HEAP$$ZI$$Base;
+extern int Image$$ARM_LIB_STACK$$ZI$$Base;
 #define HEAP_BEGIN  ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base)
 #elif defined(__ICCARM__)
 #pragma section="HEAP"
@@ -40,7 +41,7 @@ extern int __HeapBase;
 extern int __HeapLimit;
 #define HEAP_BEGIN  ((void *)&__HeapBase)
 #endif
-#define HEAP_END    ((void*)&__HeapLimit)
+#define HEAP_END    ((void*)&Image$$ARM_LIB_STACK$$ZI$$Base)
 
 void rt_hw_board_init(void);
 

bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvoptx

@@ -10,7 +10,7 @@
     <aExt>*.s*; *.src; *.a*</aExt>
     <oExt>*.obj; *.o</oExt>
     <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
     <pExt>*.plm</pExt>
     <CppX>*.cpp</CppX>
     <nMigrate>0</nMigrate>
@@ -196,4 +196,1068 @@
     </TargetOption>
   </Target>
 
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>CPU</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
+      <FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName>
+      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName>
+      <FilenameWithoutPath>div0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</PathWithFileName>
+      <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m4\cpuport.c</PathWithFileName>
+      <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>DeviceDrivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\misc\pin.c</PathWithFileName>
+      <FilenameWithoutPath>pin.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName>
+      <FilenameWithoutPath>serial.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
+      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
+      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\waitqueue.c</PathWithFileName>
+      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\pipe.c</PathWithFileName>
+      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\workqueue.c</PathWithFileName>
+      <FilenameWithoutPath>workqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\completion.c</PathWithFileName>
+      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\dataqueue.c</PathWithFileName>
+      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Drivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>board\MCUX_Config\board\pin_mux.c</PathWithFileName>
+      <FilenameWithoutPath>pin_mux.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>board\MCUX_Config\board\clock_config.c</PathWithFileName>
+      <FilenameWithoutPath>clock_config.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>board\board.c</PathWithFileName>
+      <FilenameWithoutPath>board.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\drivers\drv_pin.c</PathWithFileName>
+      <FilenameWithoutPath>drv_pin.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\drivers\drv_key.c</PathWithFileName>
+      <FilenameWithoutPath>drv_key.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\drivers\drv_led.c</PathWithFileName>
+      <FilenameWithoutPath>drv_led.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\drivers\drv_uart.c</PathWithFileName>
+      <FilenameWithoutPath>drv_uart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Finsh</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\shell.c</PathWithFileName>
+      <FilenameWithoutPath>shell.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\msh.c</PathWithFileName>
+      <FilenameWithoutPath>msh.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\cmd.c</PathWithFileName>
+      <FilenameWithoutPath>cmd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Kernel</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\object.c</PathWithFileName>
+      <FilenameWithoutPath>object.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>27</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
+      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>28</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\thread.c</PathWithFileName>
+      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
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+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_puf.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_puf.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>73</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_rng.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_lpadc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>75</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_inputmux.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>76</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_i2c_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>77</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_prince.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>78</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_i2c.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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+    <File>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
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+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\arm\startup_LPC55S69_cm33_core0.s</PathWithFileName>
+      <FilenameWithoutPath>startup_LPC55S69_cm33_core0.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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+      <GroupNumber>7</GroupNumber>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\system_LPC55S69_cm33_core0.c</PathWithFileName>
+      <FilenameWithoutPath>system_LPC55S69_cm33_core0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
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+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>81</FileNumber>
+      <FileType>4</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib</PathWithFileName>
+      <FilenameWithoutPath>arm_keil_lib_power_cm33_core0.lib</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>82</FileNumber>
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+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_anactrl.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_anactrl.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>83</FileNumber>
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+      <tvExp>0</tvExp>
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+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_iap.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>84</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c</PathWithFileName>
+      <FilenameWithoutPath>fsl_ostimer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
 </ProjectOpt>

bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx

@@ -1,44 +1,46 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
 <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
   <SchemaVersion>2.1</SchemaVersion>
+
   <Header>### uVision Project, (C) Keil Software</Header>
+
   <Targets>
     <Target>
       <TargetName>rtthread-lpc55s6x</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pArmCC>6120000::V6.12::.\ARMCLANG</pArmCC>
-      <pCCUsed>6120000::V6.12::.\ARMCLANG</pCCUsed>
+      <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
       <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>LPC55S69JBD100:cm33_core0</Device>
           <Vendor>NXP</Vendor>
-          <PackID>NXP.LPC55S69_DFP.1.0.0</PackID>
-          <PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
+          <PackID>NXP.LPC55S69_DFP.13.0.0</PackID>
+          <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
           <Cpu>IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec />
-          <StartupFile />
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
           <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
           <RegisterFile>$$Device:LPC55S69JBD100$fsl_device_registers.h</RegisterFile>
-          <MemoryEnv />
-          <Cmp />
-          <Asm />
-          <Linker />
-          <OHString />
-          <InfinionOptionDll />
-          <SLE66CMisc />
-          <SLE66AMisc />
-          <SLE66LinkerMisc />
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
           <SFDFile>$$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
-          <BinPath />
-          <IncludePath />
-          <LibPath />
-          <RegisterFilePath />
-          <DBRegisterFilePath />
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -60,8 +62,8 @@
           <BeforeCompile>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopU1X>0</nStopU1X>
@@ -70,8 +72,8 @@
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopB1X>0</nStopB1X>
@@ -80,15 +82,15 @@
           <AfterMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString />
+          <SVCSIdString></SVCSIdString>
         </TargetCommonOption>
         <CommonProperty>
           <UseCPPCompiler>0</UseCPPCompiler>
@@ -102,15 +104,15 @@
           <AssembleAssemblyFile>0</AssembleAssemblyFile>
           <PublicsOnly>0</PublicsOnly>
           <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument />
-          <IncludeLibraryModules />
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
           <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
-          <SimDllName />
-          <SimDllArguments />
-          <SimDlgDll />
-          <SimDlgDllArguments />
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
           <TargetDllName>SARMV8M.DLL</TargetDllName>
           <TargetDllArguments> -MPU</TargetDllArguments>
           <TargetDlgDll>TCM.DLL</TargetDlgDll>
@@ -137,10 +139,10 @@
           <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2V8M.DLL</Flash2>
           <Flash3>"" ()</Flash3>
-          <Flash4 />
-          <pFcarmOut />
-          <pFcarmGrp />
-          <pFcArmRoot />
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
           <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
@@ -173,7 +175,7 @@
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M33"</AdsCpuType>
-            <RvctDeviceName />
+            <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
             <uocRam>0</uocRam>
@@ -183,6 +185,7 @@
             <uocXRam>0</uocXRam>
             <RvdsVP>2</RvdsVP>
             <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
             <hadIRAM2>1</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -306,7 +309,7 @@
                 <Size>0x8000</Size>
               </OCR_RVCT10>
             </OnChipMemories>
-            <RvctStartVector />
+            <RvctStartVector></RvctStartVector>
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
@@ -334,9 +337,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>--target=arm-arm-none-eabi</MiscControls>
-              <Define>CPU_LPC55S69JBD100_cm33_core0, RT_USING_ARM_LIBC, __RTTHREAD__</Define>
-              <Undefine />
-              <IncludePath>applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port</IncludePath>
+              <Define>CPU_LPC55S69JBD100_cm33_core0, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\..\..\components\libc\compilers\common\nogcc;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port;..\..\..\examples\utest\testcases\kernel</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -349,12 +352,12 @@
             <NoWarn>0</NoWarn>
             <uSurpInc>0</uSurpInc>
             <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
+            <ClangAsOpt>4</ClangAsOpt>
             <VariousControls>
-              <MiscControls />
-              <Define />
-              <Undefine />
-              <IncludePath />
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -366,13 +369,13 @@
             <useFile>0</useFile>
             <TextAddressRange>0x00000000</TextAddressRange>
             <DataAddressRange>0x02000000</DataAddressRange>
-            <pXoBase />
+            <pXoBase></pXoBase>
             <ScatterFile>.\board\linker_scripts\LPC55S69_cm33_core0_flash_mdk.scf</ScatterFile>
-            <IncludeLibs />
-            <IncludeLibsPath />
-            <Misc />
-            <LinkerInputFile />
-            <DisabledWarnings />
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
           </LDads>
         </TargetArmAds>
       </TargetOption>
@@ -386,13 +389,6 @@
               <FilePath>applications\main.c</FilePath>
             </File>
           </Files>
-          <Files>
-            <File>
-              <FileName>tfm_ps.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>applications\tfm_ps.c</FilePath>
-            </File>
-          </Files>
         </Group>
         <Group>
           <GroupName>CPU</GroupName>
@@ -402,950 +398,451 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
             </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>div0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
-            </File>
-          </Files>
-          <Files>
             <File>
               <FileName>showmem.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>cpuport.c</FileName>
+              <FileName>div0.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>context_rvds.S</FileName>
               <FileType>2</FileType>
               <FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
             </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
           <GroupName>DeviceDrivers</GroupName>
           <Files>
             <File>
-              <FileName>hwtimer.c</FileName>
+              <FileName>pin.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\hwtimer\hwtimer.c</FilePath>
+              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>i2c_core.c</FileName>
+              <FileName>serial.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\i2c\i2c_core.c</FilePath>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>i2c_dev.c</FileName>
+              <FileName>ringbuffer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\i2c\i2c_dev.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>i2c-bit-ops.c</FileName>
+              <FileName>ringblk_buf.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\i2c\i2c-bit-ops.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>pin.c</FileName>
+              <FileName>waitqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>adc.c</FileName>
+              <FileName>pipe.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\misc\adc.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>rt_drv_pwm.c</FileName>
+              <FileName>workqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\misc\rt_drv_pwm.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>rtc.c</FileName>
+              <FileName>completion.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\rtc\rtc.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>block_dev.c</FileName>
+              <FileName>dataqueue.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\sdio\block_dev.c</FilePath>
+              <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
             </File>
           </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
           <Files>
             <File>
-              <FileName>mmcsd_core.c</FileName>
+              <FileName>pin_mux.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\sdio\mmcsd_core.c</FilePath>
+              <FilePath>board\MCUX_Config\board\pin_mux.c</FilePath>
             </File>
-          </Files>
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-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_gint.c</FileName>
+              <FileName>fsl_rtc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gint.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_gpio.c</FileName>
+              <FileName>fsl_crc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gpio.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_crc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_hashcrypt.c</FileName>
+              <FileName>fsl_sdif.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_hashcrypt.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_i2c.c</FileName>
+              <FileName>fsl_plu.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_plu.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_i2c_dma.c</FileName>
+              <FileName>fsl_mrt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_mrt.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>fsl_i2s.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_i2s_dma.c</FileName>
+              <FileName>fsl_spi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s_dma.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_iap.c</FileName>
+              <FileName>fsl_ctimer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ctimer.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_inputmux.c</FileName>
+              <FileName>fsl_gint.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gint.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_lpadc.c</FileName>
+              <FileName>fsl_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_dma.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_mrt.c</FileName>
+              <FileName>fsl_sysctl.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_mrt.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_ostimer.c</FileName>
+              <FileName>fsl_flexcomm.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_flexcomm.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>fsl_pint.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_pint.c</FilePath>
             </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_plu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_plu.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_power.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c</FilePath>
-            </File>
-          </Files>
-          <Files>
             <File>
               <FileName>fsl_powerquad_basic.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_powerquad_basic.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_prince.c</FileName>
+              <FileName>fsl_usart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>fsl_puf.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_puf.c</FilePath>
             </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_reset.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c</FilePath>
-            </File>
-          </Files>
-          <Files>
             <File>
               <FileName>fsl_rng.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_rtc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_sctimer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_sdif.c</FileName>
+              <FileName>fsl_lpadc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_spi.c</FileName>
+              <FileName>fsl_inputmux.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_spi_dma.c</FileName>
+              <FileName>fsl_i2c_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_sysctl.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>fsl_usart.c</FileName>
+              <FileName>fsl_prince.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_usart_dma.c</FileName>
+              <FileName>fsl_i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_utick.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c</FilePath>
+              <FileName>startup_LPC55S69_cm33_core0.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\arm\startup_LPC55S69_cm33_core0.s</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_wwdt.c</FileName>
+              <FileName>system_LPC55S69_cm33_core0.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\system_LPC55S69_cm33_core0.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_sd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c</FilePath>
+              <FileName>arm_keil_lib_power_cm33_core0.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_sdmmc_common.c</FileName>
+              <FileName>fsl_anactrl.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_anactrl.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_sdmmc_event.c</FileName>
+              <FileName>fsl_iap.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
-              <FileName>fsl_sdmmc_host.c</FileName>
+              <FileName>fsl_ostimer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>arm_keil_lib_power_cm33_core0.lib</FileName>
-              <FileType>4</FileType>
-              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib</FilePath>
+              <FilePath>..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c</FilePath>
             </File>
           </Files>
         </Group>
       </Groups>
     </Target>
   </Targets>
+
   <RTE>
-    <apis />
-    <components />
-    <files />
+    <apis/>
+    <components/>
+    <files/>
   </RTE>
+
 </Project>

bsp/lpc55sxx/lpc55s69_nxp_evk/rtconfig.h

@@ -21,6 +21,9 @@
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
 #define RT_DEBUG
 
 /* Inter-Thread communication */
@@ -43,7 +46,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart"
-#define RT_VER_NUM 0x40002
+#define RT_VER_NUM 0x40004
 #define ARCH_ARM_CORTEX_FPU
 
 /* RT-Thread Components */
@@ -59,56 +62,37 @@
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
 
-#define RT_USING_DFS
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_HWTIMER
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
-#define RT_USING_ADC
-#define RT_USING_PWM
-#define RT_USING_RTC
-#define RT_USING_SDIO
-#define RT_SDIO_STACK_SIZE 512
-#define RT_SDIO_THREAD_PRIORITY 15
-#define RT_MMCSD_STACK_SIZE 1024
-#define RT_MMCSD_THREAD_PREORITY 22
-#define RT_MMCSD_MAX_PARTITION 16
-#define RT_USING_SPI
 
 /* Using USB */
 
 
 /* POSIX layer and C standard library */
 
-#define RT_USING_LIBC
-#define RT_USING_POSIX
 
 /* Network */
 
@@ -130,6 +114,9 @@
 /* Utilities */
 
 
+/* RT-Thread Utestcases */
+
+
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
@@ -160,15 +147,25 @@
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
 
 /* peripheral libraries and drivers */
 
 
-/* miscellaneous packages */
+/* AI packages */
+
 
+/* miscellaneous packages */
 
 /* samples: kernel and components samples */
 
+
+/* entertainment: terminal games and other interesting software packages */
+
 #define SOC_LPC55S6X_SERIES
 
 /* Hardware Drivers Config */
@@ -181,26 +178,11 @@
 #define BSP_USING_UART
 #define BSP_USING_UART0
 #define HW_UART0_BAUDRATE_115200
-#define BSP_USING_I2C
-#define BSP_USING_I2C4
-#define HW_I2C4_BAUDRATE_100kHZ
-#define BSP_USING_SPI
-#define BSP_USING_SPI8
-#define BSP_USING_ADC
-#define BSP_USING_ADC0_CH0
-#define BSP_USING_SDIO
-#define BSP_USING_RTC
-#define BSP_USING_HWTIMER
-#define BSP_USING_CTIMER0
-#define BSP_USING_PWM
-#define BSP_USING_CTIMER2_MAT0
 
 /* Onboard Peripheral Drivers */
 
 #define BSP_USING_LED
 #define BSP_USING_KEY
-#define BSP_USING_MMA8562
-#define BSP_USING_MMA8562I2C "i2c4"
 
 /* Board extended module Drivers */
 

bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvoptx

@@ -10,7 +10,7 @@
     <aExt>*.s*; *.src; *.a*</aExt>
     <oExt>*.obj; *.o</oExt>
     <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
     <pExt>*.plm</pExt>
     <CppX>*.cpp</CppX>
     <nMigrate>0</nMigrate>

bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvprojx

@@ -10,15 +10,14 @@
       <TargetName>rtthread-lpc55s6x</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
-      <pArmCC>6120000::V6.12::.\ARMCLANG</pArmCC>
       <pCCUsed>6120000::V6.12::.\ARMCLANG</pCCUsed>
       <uAC6>1</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>LPC55S69JBD100:cm33_core0</Device>
           <Vendor>NXP</Vendor>
-          <PackID>NXP.LPC55S69_DFP.1.0.0</PackID>
-          <PackURL>http://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
+          <PackID>NXP.LPC55S69_DFP.13.0.0</PackID>
+          <PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
           <Cpu>IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
           <StartupFile></StartupFile>
@@ -186,6 +185,7 @@
             <uocXRam>0</uocXRam>
             <RvdsVP>2</RvdsVP>
             <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
             <hadIRAM2>1</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -352,7 +352,7 @@
             <NoWarn>0</NoWarn>
             <uSurpInc>0</uSurpInc>
             <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
+            <ClangAsOpt>4</ClangAsOpt>
             <VariousControls>
               <MiscControls></MiscControls>
               <Define></Define>

bsp/ls2kdev/.config

@@ -415,6 +415,7 @@ CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -688,4 +689,4 @@ CONFIG_RT_LWIP_USING_PING=y
 CONFIG_SOC_LS=y
 CONFIG_SOC_LS2K1000=y
 CONFIG_RT_USING_UART0=y
-CONFIG_RT_USING_UART4=y
+# CONFIG_RT_USING_UART4 is not set

bsp/ls2kdev/drivers/drv_spi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,13 +8,15 @@
  * 2020-10-28     0xcccccccccccc           Initial Version
  * 2021-01-17     0xcccccccccccc           Bug Fixed : clock division cannot been adjusted as expected due to wrong register configuration.
  */
+
 /**
  * @addtogroup ls2k
  */
 /*@{*/
-#include <stdio.h>
+
 #include <stdlib.h>
 #include <ctype.h>
+#include <stdint.h>
 #include <rtthread.h>
 #include <drivers/spi.h>
 #include "drv_spi.h"
@@ -22,15 +24,15 @@
 #ifdef RT_USING_SPI
 static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha)
 {
-    SET_SPI(SPSR, 0xc0); 
+    SET_SPI(SPSR, 0xc0);
     SET_SPI(PARAM, 0x40);
     SET_SPI(PARAM2, 0x01);
     SET_SPI(SPER, (spre_spr & 0b00001100) >> 2);
-    SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2 | (spre_spr & 0b00000011)); 
+    SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2 | (spre_spr & 0b00000011));
     SET_SPI(SOFTCS, 0xff);
 }
 
-static void spi_set_csn(uint8_t val) 
+static void spi_set_csn(uint8_t val)
 {
     SET_SPI(SOFTCS, val);
 }
@@ -38,7 +40,7 @@ static void spi_set_csn(uint8_t val)
 #ifdef RT_USING_SPI_GPIOCS
     #include <drivers/pin.h>
 #endif
-static void spi_set_cs(unsigned char cs, int new_status) 
+static void spi_set_cs(unsigned char cs, int new_status)
 {
     if (cs < 4)
     {

bsp/ls2kdev/drivers/drv_spi.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,12 +14,9 @@
 #ifndef LS2K_DRV_SPI_H
 #define LS2K_DRV_SPI_H
 
-#include <rtthread.h>
-#include <rthw.h>
-
 // kseg1 byte operation
-#define KSEG1_STORE8(addr,val)	 *(volatile char *)(0xffffffffa0000000 | addr) = val
-#define KSEG1_LOAD8(addr)	 *(volatile char *)(0xffffffffa0000000 | addr) 
+#define KSEG1_STORE8(addr,val)   *(volatile char *)(0xffffffffa0000000 | addr) = val
+#define KSEG1_LOAD8(addr)    *(volatile char *)(0xffffffffa0000000 | addr)
 // clock configurations
 #define APB_MAX_SPEED 125000000U
 #define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1)
@@ -30,7 +27,7 @@
 // bit bias
 #define SPCR      0x0
 #define SPSR      0x1
-#define FIFO	  0x2
+#define FIFO      0x2
 #define TXFIFO    0x2
 #define RXFIFO    0x2
 #define SPER      0x3

bsp/ls2kdev/rtconfig.h

@@ -253,6 +253,5 @@
 #define SOC_LS
 #define SOC_LS2K1000
 #define RT_USING_UART0
-#define RT_USING_UART4
 
 #endif

bsp/mm32f327x/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- Libraries

bsp/qemu-virt64-aarch64/.config

@@ -14,7 +14,7 @@ CONFIG_RT_ALIGN_SIZE=4
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
 CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_TICK_PER_SECOND=100
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
@@ -29,6 +29,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
 #
 # CONFIG_RT_KSERVICE_USING_STDLIB is not set
 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
 CONFIG_RT_DEBUG=y
 CONFIG_RT_DEBUG_COLOR=y
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -97,19 +98,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-CONFIG_FINSH_USING_MSH_ONLY=y
 CONFIG_FINSH_ARG_MAX=10
 
 #
@@ -121,7 +122,28 @@ CONFIG_DFS_FILESYSTEMS_MAX=2
 CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
 CONFIG_DFS_FD_MAX=16
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
@@ -180,7 +202,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_RT_USING_POSIX_GETLINE is not set
 # CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
-CONFIG_RT_LIBC_FIXED_TIMEZONE=8
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 
 #
 # Network
@@ -312,6 +334,8 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_AGILE_MODBUS is not set
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -328,6 +352,7 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
 
 #
 # multimedia packages
@@ -438,6 +463,9 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_LPM is not set
 # CONFIG_PKG_USING_TLSF is not set
 # CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
 
 #
 # peripheral libraries and drivers
@@ -508,6 +536,9 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_KOBUKI is not set
 # CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 
 #
 # AI packages
@@ -525,6 +556,27 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -542,14 +594,6 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
@@ -557,20 +601,11 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
-
-#
-# entertainment: terminal games and other interesting software packages
-#
-# CONFIG_PKG_USING_THREES is not set
-# CONFIG_PKG_USING_2048 is not set
-# CONFIG_PKG_USING_SNAKE is not set
-# CONFIG_PKG_USING_TETRIS is not set
-# CONFIG_PKG_USING_DONUT is not set
-# CONFIG_PKG_USING_ACLOCK is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
 # CONFIG_PKG_USING_MCURSES is not set
 # CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
 CONFIG_SOC_VIRT64_AARCH64=y
 
 #
@@ -579,5 +614,6 @@ CONFIG_SOC_VIRT64_AARCH64=y
 CONFIG_BSP_SUPPORT_FPU=y
 CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART0=y
+CONFIG_BSP_USING_VIRTIO_BLK=y
+CONFIG_RT_USING_VIRTIO_BLK0=y
 CONFIG_BSP_USING_GIC=y
-CONFIG_BSP_USING_GIC390=y

bsp/qemu-virt64-aarch64/README.md

@@ -49,4 +49,5 @@ msh />
 
 | Driver | Condition | Remark |
 | ------ | --------- | ------ |
-| UART   | Support   | UART0  |
+| UART   | Support   | UART0  |
+| VIRTIO BLK | Support | VIRTIO BLK0 |

bsp/qemu-virt64-aarch64/README_zh.md

@@ -50,4 +50,5 @@ msh />
 
 | 驱动 | 支持情况  |  备注  |
 | ------ | ----  | :------:  |
-| UART | 支持 | UART0 |
+| UART | 支持 | UART0 |
+| VIRTIO BLK | 支持 | VIRTIO BLK0 |

bsp/qemu-virt64-aarch64/SConstruct

@@ -17,6 +17,8 @@ env = Environment(tools = ['mingw'],
     AR   = rtconfig.AR, ARFLAGS = '-rc',
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
 
 Export('RTT_ROOT')
 Export('rtconfig')

bsp/qemu-virt64-aarch64/applications/mnt.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30      bernard      the first version
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+
+int mnt_init(void)
+{
+    if(rt_device_find("virtio-blk0"))
+    {
+        /* mount virtio-blk as root directory */
+        if (dfs_mount("virtio-blk0", "/", "elm", 0, RT_NULL) == 0)
+        {
+            rt_kprintf("file system initialization done!\n");
+        }
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif

bsp/qemu-virt64-aarch64/driver/Kconfig

@@ -15,11 +15,17 @@ menu "AARCH64 qemu virt64 configs"
             default y
         endif
 
-    config BSP_USING_GIC
-    bool
-    default y
+    menuconfig BSP_USING_VIRTIO_BLK
+        bool "Using VirtIO BLK"
+        default y
 
-    config BSP_USING_GIC390
+        if BSP_USING_VIRTIO_BLK
+            config RT_USING_VIRTIO_BLK0
+            bool "Enabel VirtIO BLK 0"
+            default y
+        endif
+
+    config BSP_USING_GIC
     bool
     default y
 endmenu

bsp/qemu-virt64-aarch64/driver/SConscript

@@ -3,12 +3,17 @@
 from building import *
 
 cwd     = GetCurrentDir()
-src     = Split('''
-board.c
-drv_uart.c
-''')
+src  	= Glob('*.c')
+list 	= os.listdir(cwd)
 CPPPATH = [cwd]
+objs 	= []
 
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
-Return('group')
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+objs = objs + group
+
+Return('objs')

bsp/qemu-virt64-aarch64/driver/board.c

@@ -7,6 +7,7 @@
  * Date           Author         Notes
  * 2019-07-29     zdzn           first version
  * 2021-07-31     GuEe-GUI       config the memory/io address map
+ * 2021-09-11     GuEe-GUI       remove do-while in rt_hw_timer_isr
  */
 
 #include <rthw.h>
@@ -18,38 +19,34 @@
 
 void rt_hw_vector_init(void);
 
-static uint64_t tickval = 0;
+static uint64_t timer_val;
+static uint64_t timer_step;
 
 void rt_hw_timer_isr(int vector, void *parameter)
 {
-    uint64_t cntvct_el0;
-
-    do
-    {
-        tickval += 0xF424;
-        __asm__ volatile ("msr CNTV_CVAL_EL0, %0"::"r"(tickval));
-        __asm__ volatile ("mrs %0, CNTVCT_EL0":"=r"(cntvct_el0));
-    }
-    while (cntvct_el0 >= tickval);
+    timer_val += timer_step;
+    __asm__ volatile ("msr CNTV_CVAL_EL0, %0"::"r"(timer_val));
+    __asm__ volatile ("isb":::"memory");
 
     rt_tick_increase();
 }
 
-int rt_hw_timer_init()
+int rt_hw_timer_init(void)
 {
-    uint64_t val;
-
     rt_hw_interrupt_install(27, rt_hw_timer_isr, RT_NULL, "tick");
     rt_hw_interrupt_umask(27);
 
-    val = 0;
-    __asm__ volatile ("msr CNTV_CTL_EL0, %0"::"r"(val));
-    val = 0x03B9ACA0;
-    __asm__ volatile ("msr CNTFRQ_EL0, %0"::"r"(val));
-    tickval += 0xF424;
-    __asm__ volatile ("msr CNTV_CVAL_EL0, %0"::"r"(tickval));
-    val = 1;
-    __asm__ volatile ("msr CNTV_CTL_EL0, %0"::"r"(val));
+    __asm__ volatile ("msr CNTV_CTL_EL0, %0"::"r"(0));
+
+    __asm__ volatile ("isb 0xf":::"memory");
+    __asm__ volatile ("mrs %0, CNTFRQ_EL0" : "=r" (timer_step));
+    timer_step /= RT_TICK_PER_SECOND;
+    timer_val = timer_step;
+    __asm__ volatile ("dsb 0xf":::"memory");
+
+    __asm__ volatile ("msr CNTV_CVAL_EL0, %0"::"r"(timer_val));
+    __asm__ volatile ("msr CNTV_CTL_EL0, %0"::"r"(1));
+
     return 0;
 }
 
@@ -73,6 +70,8 @@ void rt_hw_board_init(void)
     cont >>= 21;
     /* memory location */
     armv8_map_2M(0x40000000, 0x40000000, cont, MEM_ATTR_MEMORY);
+    /* virtio blk0 */
+    armv8_map_2M(VIRTIO_MMIO_BLK0_BASE, VIRTIO_MMIO_BLK0_BASE, 0x1, MEM_ATTR_IO);
     /* uart location*/
     armv8_map_2M(PL011_UART0_BASE, PL011_UART0_BASE, 0x1, MEM_ATTR_IO);
     /* gic location*/

bsp/qemu-virt64-aarch64/driver/board.h

@@ -7,12 +7,15 @@
  * Date           Author       Notes
  * 2017-5-30      Bernard      the first version
  * 2021-07-31     GuEe-GUI     add ARM GIC definitions
+ * 2021-09-11     GuEe-GUI     rename right macros for gic
  */
 
 #ifndef BOARD_H__
 #define BOARD_H__
 
 #include <rthw.h>
+#include <rtdef.h>
+#include <stdint.h>
 
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
@@ -20,17 +23,36 @@ extern unsigned char __bss_end;
 #define RT_HW_HEAP_BEGIN    (void*)&__bss_end
 #define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 1 * 1024 * 1024)
 
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+
+#define VIRTIO_SPI_IRQ_BASE         32
+
+/* Virtio BLK */
+#define VIRTIO_MMIO_BLK0_BASE       0x0a000000
+#define VIRTIO_MMIO_BLK0_SIZE       0x00000200
+#define VIRTIO_MMIO_BLK0_IRQ        (VIRTIO_SPI_IRQ_BASE + 0x10)
+
 /* UART */
 #define PL011_UARTDR                0x000
 #define PL011_UARTFR                0x018
 #define PL011_UARTFR_TXFF_BIT       5
 #define PL011_UART0_BASE            0x09000000
 #define PL011_UART0_SIZE            0x00001000
+#define PL011_UART0_IRQNUM          (VIRTIO_SPI_IRQ_BASE + 1)
 
 /* DIST and CPU */
 #define GIC_PL390_DISTRIBUTOR_PPTR  0x08000000
 #define GIC_PL390_CONTROLLER_PPTR   0x08010000
 
+#define MAX_HANDLERS                96
+#define GIC_IRQ_START               0
+/* number of interrupts on board */
+#define ARM_GIC_NR_IRQS             96
+/* only one GIC available */
+#define ARM_GIC_MAX_NR              1
+
+#define IRQ_ARM_VTIMER              27
+
 /* the basic constants and interfaces needed by gic */
 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
 {

bsp/qemu-virt64-aarch64/driver/drv_uart.c

@@ -116,7 +116,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
 static struct hw_uart_device _uart0_device =
 {
     PL011_UART0_BASE,
-    33,
+    PL011_UART0_IRQNUM,
 };
 static struct rt_serial_device _serial0;
 #endif

bsp/qemu-virt64-aarch64/driver/virtio/SConscript

@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src  	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/qemu-virt64-aarch64/driver/virtio/drv_virtio_blk.c

@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-9-16      GuEe-GUI     the first version
+ */
+
+#include <rtconfig.h>
+#include <rtthread.h>
+#include <rthw.h>
+#include <cpuport.h>
+#include <board.h>
+
+#include "virtio.h"
+#include "virtio_mmio.h"
+#include "drv_virtio_blk.h"
+
+#ifdef BSP_USING_VIRTIO_BLK
+
+#ifdef RT_USING_VIRTIO_BLK0
+static struct virtio_blk blk0;
+static struct virtio_blk_device virtio_blk_dev0;
+#endif /* RT_USING_VIRTIO_BLK0 */
+
+static int alloc_desc(struct virtio_blk *blk)
+{
+    int i;
+    for(i = 0; i < QUEUE_SIZE; i++)
+    {
+        if (blk->free[i])
+        {
+            blk->free[i] = 0;
+            return i;
+        }
+    }
+    return -RT_ERROR;
+}
+
+static void free_desc(struct virtio_blk *blk, int i)
+{
+    if (i >= QUEUE_SIZE)
+    {
+        rt_kprintf("Out of queue number");
+        RT_ASSERT(0);
+    }
+    if (blk0.free[i])
+    {
+        rt_kprintf("Already freed");
+        RT_ASSERT(0);
+    }
+    blk->desc[i].addr = 0;
+    blk->desc[i].len = 0;
+    blk->desc[i].flags = 0;
+    blk->desc[i].next = 0;
+    blk->free[i] = 1;
+}
+
+static void free_chain(struct virtio_blk *blk, int i)
+{
+    int flag, nxt;
+    for (;;)
+    {
+        flag = blk->desc[i].flags;
+        nxt = blk->desc[i].next;
+
+        free_desc(blk, i);
+
+        if (flag & VRING_DESC_F_NEXT)
+        {
+            i = nxt;
+        }
+        else
+        {
+            break;
+        }
+    }
+}
+
+static int alloc3_desc(struct virtio_blk *blk, int *idx)
+{
+    for (int i = 0; i < 3; ++i)
+    {
+        idx[i] = alloc_desc(blk);
+        if (idx[i] < 0)
+        {
+            for (int j = 0; j < i; ++j)
+            {
+                free_desc(blk, idx[j]);
+            }
+            return -RT_ERROR;
+        }
+    }
+    return 0;
+}
+
+static int virtio_blk_device_init(struct virtio_blk_device *virtio_blk_dev)
+{
+    uint32_t status = 0;
+    uint32_t max;
+    uint64_t features;
+    int i;
+
+#ifdef RT_USING_SMP
+    rt_spin_lock_init(&virtio_blk_dev->spinlock);
+#endif
+
+    if (virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_MAGIC_VALUE) != VIRTIO_MMIO_MAGIC ||
+        virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_VERSION) != 1 ||
+        virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_DEVICE_ID) != 2 ||
+        virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_VENDOR_ID) != VIRTIO_MMIO_VENDOR)
+    {
+        rt_kprintf("Could not find virtio disk");
+
+        return -RT_ERROR;
+    }
+
+    status |= VIRTIO_STAT_ACKNOWLEDGE;
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_STATUS, status);
+
+    status |= VIRTIO_STAT_DRIVER;
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_STATUS, status);
+
+    /* negotiate features */
+    features = virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_DEVICE_FEATURES);
+    features &= ~(1 << VIRTIO_BLK_F_RO);
+    features &= ~(1 << VIRTIO_BLK_F_SCSI);
+    features &= ~(1 << VIRTIO_BLK_F_CONFIG_WCE);
+    features &= ~(1 << VIRTIO_BLK_F_MQ);
+    features &= ~(1 << VIRTIO_F_ANY_LAYOUT);
+    features &= ~(1 << VIRTIO_RING_F_EVENT_IDX);
+    features &= ~(1 << VIRTIO_RING_F_INDIRECT_DESC);
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_DRIVER_FEATURES, features);
+
+    /* tell device that feature negotiation is complete */
+    status |= VIRTIO_STAT_FEATURES_OK;
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_STATUS, status);
+
+    /* tell device we're completely ready */
+    status |= VIRTIO_STAT_DRIVER_OK;
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_STATUS, status);
+
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_GUEST_PAGE_SIZE, PAGE_SIZE);
+
+    /* initialize queue 0 */
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_QUEUE_SEL, 0);
+
+    max = virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_QUEUE_NUM_MAX);
+    if (max == 0)
+    {
+        rt_kprintf("Virtio disk has no queue 0");
+        RT_ASSERT(0);
+    }
+    if (max < QUEUE_SIZE)
+    {
+        rt_kprintf("Virtio disk max queue too short");
+        RT_ASSERT(0);
+    }
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_QUEUE_NUM, QUEUE_SIZE);
+
+    rt_memset(virtio_blk_dev->blk->pages, 0, sizeof(virtio_blk_dev->blk->pages));
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_QUEUE_PFN, ((uint64_t)blk0.pages) >> PAGE_SHIFT);
+
+    virtio_blk_dev->blk->desc = (struct virtq_desc *)virtio_blk_dev->blk->pages;
+    virtio_blk_dev->blk->avail = (struct virtq_avail *)(virtio_blk_dev->blk->pages + QUEUE_SIZE * sizeof(struct virtq_desc));
+    virtio_blk_dev->blk->used = (struct virtq_used *)(virtio_blk_dev->blk->pages + PAGE_SIZE);
+
+    /* all QUEUE_SIZE descriptors start out unused */
+    for (i = 0; i < QUEUE_SIZE; ++i)
+    {
+        virtio_blk_dev->blk->free[i] = 1;
+    }
+
+    return RT_EOK;
+}
+
+static void virtio_blk_rw(struct virtio_blk_device *virtio_blk_dev, struct virtio_blk_buf *buf, int flag)
+{
+    struct virtio_blk *blk = virtio_blk_dev->blk;
+    uint64_t sector = buf->block_no * (VIRTIO_BLK_BUF_DATA_SIZE / 512);
+    int idx[3];
+    struct virtio_blk_req *req;
+
+#ifdef RT_USING_SMP
+    rt_base_t level;
+
+    level = rt_spin_lock_irqsave(&virtio_blk_dev->spinlock);
+#endif
+
+    /* allocate the three descriptors */
+    for (;;)
+    {
+        if (alloc3_desc(blk, idx) == 0)
+        {
+            break;
+        }
+    }
+
+    req = &(blk->ops[idx[0]]);
+    req->type = flag;
+    req->reserved = 0;
+    req->sector = sector;
+
+    blk->desc[idx[0]].addr = (uint64_t)req;
+    blk->desc[idx[0]].len = sizeof(struct virtio_blk_req);
+    blk->desc[idx[0]].flags = VRING_DESC_F_NEXT;
+    blk->desc[idx[0]].next = idx[1];
+
+    blk->desc[idx[1]].addr = (uint64_t)buf->data;
+    blk->desc[idx[1]].len = VIRTIO_BLK_BUF_DATA_SIZE;
+
+    blk->desc[idx[1]].flags = flag ? 0 : VRING_DESC_F_WRITE;
+
+    blk->desc[idx[1]].flags |= VRING_DESC_F_NEXT;
+    blk->desc[idx[1]].next = idx[2];
+
+    /* device writes 0 on success */
+    blk->info[idx[0]].status = 0xff;
+    blk->desc[idx[2]].addr = (uint64_t)&(blk->info[idx[0]].status);
+    blk->desc[idx[2]].len = 1;
+    /* device writes the status */
+    blk->desc[idx[2]].flags = VRING_DESC_F_WRITE;
+    blk->desc[idx[2]].next = 0;
+
+    /* record struct buf for virtio_blk_isr() */
+    buf->valid = 1;
+    blk->info[idx[0]].buf = buf;
+
+    /* tell the device the first index in our chain of descriptors */
+    blk->avail->ring[blk->avail->idx % QUEUE_SIZE] = idx[0];
+
+    rt_hw_dsb();
+
+    /* tell the device another avail ring entry is available */
+    blk->avail->idx += 1;
+
+    rt_hw_dsb();
+
+    /* value is queue number */
+    virtio_mmio_write32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_QUEUE_NOTIFY, 0);
+
+    /* wait for virtio_blk_isr() to done */
+    while (buf->valid == 1)
+    {
+#ifdef RT_USING_SMP
+        rt_spin_unlock_irqrestore(&virtio_blk_dev->spinlock, level);
+#endif
+        rt_thread_yield();
+#ifdef RT_USING_SMP
+        level = rt_spin_lock_irqsave(&virtio_blk_dev->spinlock);
+#endif
+    }
+
+    blk->info[idx[0]].buf = 0;
+    free_chain(blk, idx[0]);
+
+#ifdef RT_USING_SMP
+    rt_spin_unlock_irqrestore(&virtio_blk_dev->spinlock, level);
+#endif
+}
+
+static void virtio_blk_isr(int irqno, void *param)
+{
+    int id;
+    struct virtio_blk_device *virtio_blk_dev = (struct virtio_blk_device *)param;
+    struct virtio_blk *blk = virtio_blk_dev->blk;
+    struct virtio_blk_buf *buf_tmp;
+
+#ifdef RT_USING_SMP
+    rt_base_t level;
+
+    level = rt_spin_lock_irqsave(&virtio_blk_dev->spinlock);
+#endif
+
+    virtio_mmio_write32(
+        virtio_blk_dev->mmio_base,
+        VIRTIO_MMIO_INTERRUPT_ACK,
+        virtio_mmio_read32(virtio_blk_dev->mmio_base, VIRTIO_MMIO_INTERRUPT_STATUS) & 0x3);
+
+    rt_hw_dsb();
+
+    /*
+     * the device increments disk.used->idx
+     * when it adds an entry to the used ring
+     */
+    while (blk->used_idx != blk->used->idx)
+    {
+        rt_hw_dsb();
+        id = blk->used->ring[blk->used_idx % QUEUE_SIZE].id;
+
+        if (blk->info[id].status != 0)
+        {
+            rt_kprintf("Virtio BLK Status");
+            RT_ASSERT(0);
+        }
+
+        buf_tmp = blk->info[id].buf;
+
+        /* done with buf */
+        buf_tmp->valid = 0;
+        rt_thread_yield();
+
+        blk->used_idx += 1;
+    }
+
+#ifdef RT_USING_SMP
+    rt_spin_unlock_irqrestore(&virtio_blk_dev->spinlock, level);
+#endif
+}
+
+static rt_err_t virtio_blk_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t virtio_blk_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t virtio_blk_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t virtio_blk_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    struct virtio_blk_device *virtio_blk_dev = (struct virtio_blk_device *)dev;
+    struct virtio_blk_buf buf =
+    {
+        .block_no = (uint32_t)pos,
+        .data = (uint8_t *)buffer
+    };
+
+    virtio_blk_rw(virtio_blk_dev, &buf, VIRTIO_BLK_T_IN);
+
+    return size;
+}
+
+static rt_size_t virtio_blk_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    struct virtio_blk_device *virtio_blk_dev = (struct virtio_blk_device *)dev;
+    struct virtio_blk_buf buf =
+    {
+        .block_no = (uint32_t)pos,
+        .data = (uint8_t *)buffer
+    };
+
+    virtio_blk_rw(virtio_blk_dev, &buf, VIRTIO_BLK_T_OUT);
+
+    return size;
+}
+
+static rt_err_t virtio_blk_control(rt_device_t dev, int cmd, void *args)
+{
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    {
+        struct rt_device_blk_geometry *geometry;
+
+        geometry = (struct rt_device_blk_geometry *)args;
+        if (geometry == RT_NULL)
+        {
+            return -RT_ERROR;
+        }
+
+        geometry->bytes_per_sector = VIRTIO_BLK_BYTES_PER_SECTOR;
+        geometry->block_size = VIRTIO_BLK_BLOCK_SIZE;
+        geometry->sector_count = VIRTIO_BLK_SECTOR_COUNT;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_device_ops virtio_blk_ops =
+{
+    virtio_blk_init,
+    virtio_blk_open,
+    virtio_blk_close,
+    virtio_blk_read,
+    virtio_blk_write,
+    virtio_blk_control
+};
+
+int rt_virtio_blk_init(void)
+{
+    rt_err_t status = RT_EOK;
+
+#ifdef RT_USING_VIRTIO_BLK0
+    virtio_blk_dev0.parent.type = RT_Device_Class_Block;
+    virtio_blk_dev0.parent.ops  = &virtio_blk_ops;
+    virtio_blk_dev0.blk = &blk0;
+    virtio_blk_dev0.mmio_base = (uint32_t *)VIRTIO_MMIO_BLK0_BASE;
+
+    status = virtio_blk_device_init(&virtio_blk_dev0);
+    rt_device_register((rt_device_t)&virtio_blk_dev0, "virtio-blk0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE);
+    rt_hw_interrupt_install(VIRTIO_MMIO_BLK0_IRQ, virtio_blk_isr, &virtio_blk_dev0, "virtio-blk0");
+    rt_hw_interrupt_umask(VIRTIO_MMIO_BLK0_IRQ);
+#endif /* RT_USING_VIRTIO_BLK0 */
+
+    return status;
+}
+INIT_DEVICE_EXPORT(rt_virtio_blk_init);
+#endif /* BSP_USING_VIRTIO_BLK */

bsp/qemu-virt64-aarch64/driver/virtio/drv_virtio_blk.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-9-16      GuEe-GUI     the first version
+ */
+
+#ifndef DRV_VIRTIO_BLK_H__
+#define DRV_VIRTIO_BLK_H__
+
+#include <rthw.h>
+#include <stdint.h>
+#include "virtio.h"
+
+#define VIRTIO_BLK_BUF_DATA_SIZE        512
+#define VIRTIO_BLK_BYTES_PER_SECTOR     512
+#define VIRTIO_BLK_BLOCK_SIZE           512
+#define VIRTIO_BLK_SECTOR_COUNT         0x40000 /* 128MB */
+
+#define VIRTIO_BLK_F_RO                 5   /* Disk is read-only */
+#define VIRTIO_BLK_F_SCSI               7   /* Supports scsi command passthru */
+#define VIRTIO_BLK_F_CONFIG_WCE         11  /* Writeback mode available in config */
+#define VIRTIO_BLK_F_MQ                 12  /* Support more than one vq */
+
+#define VIRTIO_BLK_T_IN                 0   /* Read the blk */
+#define VIRTIO_BLK_T_OUT                1   /* Write the blk */
+
+#define VIRTIO_F_ANY_LAYOUT             27
+#define VIRTIO_RING_F_INDIRECT_DESC     28
+#define VIRTIO_RING_F_EVENT_IDX         29
+
+struct virtio_blk_buf
+{
+    int valid;
+    uint32_t block_no;
+    uint8_t *data;
+};
+
+struct virtio_blk_req
+{
+    uint32_t type;
+    uint32_t reserved;
+    uint64_t sector;
+};
+
+/*
+ * virtio_blk must be a static variable because
+ * pages must consist of two contiguous pages of
+ * page-aligned physical memory
+ */
+struct virtio_blk
+{
+    char pages[2 * PAGE_SIZE];
+    struct virtq_desc *desc;
+    struct virtq_avail *avail;
+    struct virtq_used *used;
+
+    char free[QUEUE_SIZE];
+    uint16_t used_idx;
+    struct
+    {
+        struct virtio_blk_buf *buf;
+        char status;
+    } info[QUEUE_SIZE];
+
+    struct virtio_blk_req ops[QUEUE_SIZE];
+} __attribute__ ((aligned (PAGE_SIZE)));
+
+struct virtio_blk_device
+{
+    struct rt_device parent;
+    struct virtio_blk *blk;
+
+    uint32_t *mmio_base;
+#ifdef RT_USING_SMP
+    struct rt_spinlock spinlock;
+#endif
+};
+
+int rt_hw_virtio_blk_init(void);
+
+#endif /* DRV_VIRTIO_BLK_H__ */

bsp/qemu-virt64-aarch64/driver/virtio/virtio.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-9-16      GuEe-GUI     the first version
+ */
+
+#ifndef VIRTIO_H__
+#define VIRTIO_H__
+
+#include <stdint.h>
+
+#define PAGE_SIZE   4096
+#define PAGE_SHIFT  12
+
+#define VIRTIO_STAT_ACKNOWLEDGE     1
+#define VIRTIO_STAT_DRIVER          2
+#define VIRTIO_STAT_DRIVER_OK       4
+#define VIRTIO_STAT_FEATURES_OK     8
+#define VIRTIO_STAT_NEEDS_RESET     64
+#define VIRTIO_STAT_FAILED          128
+
+#define QUEUE_SIZE  8
+
+struct virtq_desc
+{
+    uint64_t addr;
+    uint32_t len;
+    uint16_t flags;
+    uint16_t next;
+};
+
+#define VRING_DESC_F_NEXT  1    // chained with another descriptor
+#define VRING_DESC_F_WRITE 2    // device writes (vs read)
+
+struct virtq_avail
+{
+    uint16_t flags;             // always zero
+    uint16_t idx;               // driver will write ring[idx] next
+    uint16_t ring[QUEUE_SIZE];  // descriptor numbers of chain heads
+    uint16_t unused;
+};
+
+struct virtq_used_elem
+{
+    uint32_t id;   // index of start of completed descriptor chain
+    uint32_t len;
+};
+
+struct virtq_used
+{
+    uint16_t flags;                         // always zero
+    uint16_t idx;                           // device increments when it adds a ring[] entry
+    struct virtq_used_elem ring[QUEUE_SIZE];
+};
+
+#endif /* VIRTIO_H__ */

bsp/qemu-virt64-aarch64/driver/virtio/virtio_mmio.c

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-9-16      GuEe-GUI     the first version
+ */
+
+#include <rtthread.h>
+#include <cpuport.h>
+
+#include "virtio_mmio.h"
+
+void virtio_mmio_print_configs(uint32_t *device_base)
+{
+    rt_kprintf("MagicValue:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_MAGIC_VALUE));
+    rt_kprintf("Version:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_VERSION));
+    rt_kprintf("DeviceID:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_DEVICE_ID));
+    rt_kprintf("VendorID:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_VENDOR_ID));
+    rt_kprintf("DeviceFeatures0:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_HOST_FEATURES));
+    rt_kprintf("DeviceFeaturesSel0:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_HOST_FEATURES_SEL));
+
+    virtio_mmio_write32(device_base, VIRTIO_MMIO_HOST_FEATURES_SEL, 1);
+    rt_hw_dsb();
+
+    rt_kprintf("DeviceFeatures1:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_HOST_FEATURES));
+    rt_kprintf("DriverFeatures:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_GUEST_FEATURES));
+    rt_kprintf("DriverFeaturesSel:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_GUEST_FEATURES_SEL));
+    rt_kprintf("PageSize:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_GUEST_PAGE_SIZE));
+
+    virtio_mmio_write32(device_base, VIRTIO_MMIO_QUEUE_SEL, 0);
+    rt_hw_dsb();
+
+    rt_kprintf("QueueSel:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_SEL));
+    rt_kprintf("QueueNumMax:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_NUM_MAX));
+    rt_kprintf("QueueNum:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_NUM));
+
+    virtio_mmio_write32(device_base, VIRTIO_MMIO_QUEUE_SEL, 1);
+    rt_hw_dsb();
+
+    rt_kprintf("QueueSel:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_SEL));
+    rt_kprintf("QueueNumMax1:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_NUM_MAX));
+    rt_kprintf("QueueNum1:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_NUM));
+    rt_kprintf("QueueAlign:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_ALIGN));
+    rt_kprintf("QueuePFN:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_PFN));
+    rt_kprintf("QueueReady:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_READY));
+    rt_kprintf("QueueNotify:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_NOTIFY));
+    rt_kprintf("InterruptStatus:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_INTERRUPT_STATUS));
+    rt_kprintf("InterruptACK:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_INTERRUPT_ACK));
+    rt_kprintf("Status:\t\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_STATUS));
+    rt_kprintf("QueueDescLow:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_DESC_LOW));
+    rt_kprintf("QueueDescHigh:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_DESC_HIGH));
+    rt_kprintf("QueueDriverLow:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_AVAIL_LOW));
+    rt_kprintf("QueueDriverHigh:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_AVAIL_HIGH));
+    rt_kprintf("QueueDeviceLow:\t\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_USED_LOW));
+    rt_kprintf("QueueDeviceHigh:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_QUEUE_USED_HIGH));
+    rt_kprintf("ConfigGeneration:\t 0x%x\n", virtio_mmio_read32(device_base, VIRTIO_MMIO_CONFIG_GENERATION));
+    rt_kprintf("Config:\t\t\t 0x%x\n", virtio_mmio_read32(device_base,VIRTIO_MMIO_CONFIG));
+}

bsp/qemu-virt64-aarch64/driver/virtio/virtio_mmio.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-9-16      GuEe-GUI     the first version
+ */
+
+#ifndef VIRTIO_MMIO_H
+#define VIRTIO_MMIO_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define VIRTIO_MMIO_MAGIC               0x74726976
+#define VIRTIO_MMIO_VENDOR              0x554d4551
+
+#define VIRTIO_MMIO_MAGIC_VALUE         0x000   /* VIRTIO_MMIO_MAGIC */
+#define VIRTIO_MMIO_VERSION             0x004   /* version: 1 is legacy */
+#define VIRTIO_MMIO_DEVICE_ID           0x008   /* device type: 1 is net, 2 is disk */
+#define VIRTIO_MMIO_VENDOR_ID           0x00c   /* VIRTIO_MMIO_VENDOR */
+#define VIRTIO_MMIO_DEVICE_FEATURES     0x010
+#define VIRTIO_MMIO_DRIVER_FEATURES     0x020
+#define VIRTIO_MMIO_HOST_FEATURES       0x010
+#define VIRTIO_MMIO_HOST_FEATURES_SEL   0x014
+#define VIRTIO_MMIO_GUEST_FEATURES      0x020
+#define VIRTIO_MMIO_GUEST_FEATURES_SEL  0x024
+#define VIRTIO_MMIO_GUEST_PAGE_SIZE     0x028   /* version 1 only */
+#define VIRTIO_MMIO_QUEUE_SEL           0x030
+#define VIRTIO_MMIO_QUEUE_NUM_MAX       0x034
+#define VIRTIO_MMIO_QUEUE_NUM           0x038
+#define VIRTIO_MMIO_QUEUE_ALIGN         0x03c   /* version 1 only */
+#define VIRTIO_MMIO_QUEUE_PFN           0x040   /* version 1 only */
+#define VIRTIO_MMIO_QUEUE_READY         0x044   /* requires version 2 */
+#define VIRTIO_MMIO_QUEUE_NOTIFY        0x050
+#define VIRTIO_MMIO_INTERRUPT_STATUS    0x060
+#define VIRTIO_MMIO_INTERRUPT_ACK       0x064
+#define VIRTIO_MMIO_STATUS              0x070
+#define VIRTIO_MMIO_QUEUE_DESC_LOW      0x080   /* requires version 2 */
+#define VIRTIO_MMIO_QUEUE_DESC_HIGH     0x084   /* requires version 2 */
+#define VIRTIO_MMIO_QUEUE_AVAIL_LOW     0x090   /* requires version 2 */
+#define VIRTIO_MMIO_QUEUE_AVAIL_HIGH    0x094   /* requires version 2 */
+#define VIRTIO_MMIO_QUEUE_USED_LOW      0x0a0   /* requires version 2 */
+#define VIRTIO_MMIO_QUEUE_USED_HIGH     0x0a4   /* requires version 2 */
+#define VIRTIO_MMIO_CONFIG_GENERATION   0x100   /* requires version 2 */
+#define VIRTIO_MMIO_CONFIG              0x100
+#define VIRTIO_MMIO_INT_VRING           (1 << 0)
+#define VIRTIO_MMIO_INT_CONFIG          (1 << 1)
+#define VIRTIO_MMIO_VRING_ALIGN         4096
+
+static inline uint32_t virtio_mmio_read32(uint32_t *base, size_t offset)
+{
+    return *((volatile uint32_t*) (((uintptr_t) base) + offset));
+}
+
+static inline uint16_t virtio_mmio_read16(uint32_t *base, size_t offset)
+{
+    return *((volatile uint16_t*) (((uintptr_t) base) + offset));
+}
+
+static inline uint8_t virtio_mmio_read8(uint32_t *base, size_t offset)
+{
+    return *((volatile uint8_t*) (((uintptr_t) base) + offset));
+}
+
+static inline void virtio_mmio_write32(uint32_t *base, size_t offset, uint32_t val)
+{
+    *((volatile uint32_t*) (((uintptr_t) base) + offset)) = val;
+}
+
+void virtio_mmio_print_configs(uint32_t *device_base);
+
+#endif /* VIRTIO_MMIO_H */

bsp/qemu-virt64-aarch64/link.lds

@@ -24,7 +24,7 @@
 
 SECTIONS
 {
-    . = 0x40000000;
+    . = 0x40008000;
     . = ALIGN(4096);
     .text :
     {

bsp/qemu-virt64-aarch64/qemu.bat

@@ -1 +1,6 @@
-qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 1 -kernel rtthread.elf -nographic
+@echo off
+if exist sd.bin goto run
+qemu-img create -f raw sd.bin 64M
+
+:run
+qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 4 -kernel rtthread.elf -drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 -nographic

bsp/qemu-virt64-aarch64/qemu.sh

@@ -1 +1,4 @@
-qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 1 -kernel rtthread.elf -nographic -monitor pty
+if [ ! -f "sd.bin" ]; then
+dd if=/dev/zero of=sd.bin bs=1024 count=65536
+fi
+qemu-system-aarch64 -M virt -cpu cortex-a53 -smp 4 -kernel rtthread.elf -nographic -drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 -monitor pty

bsp/qemu-virt64-aarch64/rtconfig.h

@@ -10,7 +10,7 @@
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 1000
+#define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_USING_IDLE_HOOK
@@ -64,17 +64,17 @@
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
-#define FINSH_USING_MSH_ONLY
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -84,6 +84,20 @@
 #define DFS_FILESYSTEMS_MAX 2
 #define DFS_FILESYSTEM_TYPES_MAX 2
 #define DFS_FD_MAX 16
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
@@ -103,7 +117,7 @@
 
 #define RT_USING_LIBC
 #define RT_USING_POSIX
-#define RT_LIBC_FIXED_TIMEZONE 8
+#define RT_LIBC_DEFAULT_TIMEZONE 8
 
 /* Network */
 
@@ -172,7 +186,6 @@
 
 /* miscellaneous packages */
 
-
 /* samples: kernel and components samples */
 
 
@@ -185,7 +198,8 @@
 #define BSP_SUPPORT_FPU
 #define BSP_USING_UART
 #define RT_USING_UART0
+#define BSP_USING_VIRTIO_BLK
+#define RT_USING_VIRTIO_BLK0
 #define BSP_USING_GIC
-#define BSP_USING_GIC390
 
 #endif

bsp/qemu-virt64-aarch64/rtconfig.py

@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH        ='aarch64'
-CPU         ='cortex-a53'
+CPU         ='cortex-a'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):

bsp/raspberry-pi/raspi3-64/.config

@@ -23,6 +23,13 @@ CONFIG_IDLE_THREAD_STACK_SIZE=2048
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
 CONFIG_RT_DEBUG=y
 CONFIG_RT_DEBUG_COLOR=y
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -55,6 +62,7 @@ CONFIG_RT_USING_MEMHEAP=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
 # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
 CONFIG_RT_USING_MEMTRACE=y
 CONFIG_RT_USING_HEAP=y
 
@@ -67,7 +75,8 @@ CONFIG_RT_USING_DEVICE_OPS=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=512
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
 CONFIG_ARCH_CPU_64BIT=y
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_ARMV8=y
@@ -90,19 +99,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-CONFIG_FINSH_USING_MSH_ONLY=y
 CONFIG_FINSH_ARG_MAX=10
 
 #
@@ -126,6 +135,11 @@ CONFIG_RT_DFS_ELM_WORD_ACCESS=y
 # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
 CONFIG_RT_DFS_ELM_USE_LFN_3=y
 CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
 CONFIG_RT_DFS_ELM_MAX_LFN=255
 CONFIG_RT_DFS_ELM_DRIVES=2
 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
@@ -134,8 +148,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
 
 #
 # Device Drivers
@@ -144,6 +156,8 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
@@ -153,8 +167,10 @@ CONFIG_RT_USING_I2C=y
 CONFIG_RT_I2C_DEBUG=y
 CONFIG_RT_USING_I2C_BITOPS=y
 # CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
@@ -196,8 +212,10 @@ CONFIG_RT_USING_LIBC=y
 CONFIG_RT_USING_POSIX=y
 # CONFIG_RT_USING_POSIX_MMAP is not set
 # CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
 # CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 
 #
 # Network
@@ -234,6 +252,12 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
 
 #
 # RT-Thread online packages
@@ -242,7 +266,9 @@ CONFIG_RT_USING_POSIX=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
@@ -280,6 +306,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
 
 #
 # IoT Cloud
@@ -288,7 +315,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
@@ -300,8 +327,6 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LIBRWS is not set
 # CONFIG_PKG_USING_TCPSERVER is not set
 # CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
@@ -310,6 +335,20 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -318,6 +357,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -325,6 +365,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
 
 #
 # multimedia packages
@@ -334,6 +375,13 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
 
 #
 # tools packages
@@ -342,25 +390,65 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
 # CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
 
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
 # CONFIG_PKG_USING_FLASHDB is not set
@@ -370,12 +458,27 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
 # CONFIG_PKG_USING_EV is not set
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
 
 #
 # peripheral libraries and drivers
@@ -384,6 +487,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -399,7 +503,6 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@@ -413,6 +516,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
@@ -421,44 +525,102 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
 # CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
 
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
 CONFIG_BCM2836_SOC=y
-# CONFIG_BSP_SUPPORT_FPU is not set
+CONFIG_BSP_SUPPORT_FPU=y
 
 #
 # Hardware Drivers Config

bsp/raspberry-pi/raspi3-64/driver/mbox.h

@@ -13,6 +13,7 @@
 #define __MBOX_H__
 
 #include <rtthread.h>
+#include <stdint.h>
 /* a properly aligned buffer */
 extern volatile unsigned int* mbox;
 

bsp/raspberry-pi/raspi3-64/driver/raspi.h

@@ -118,6 +118,7 @@ typedef enum
 #define BSC2_BASE_OFFSET (0x805000)
 
 /* IRQ */
+#define MAX_HANDLERS       72
 #define IRQ_SYSTEM_TIMER_0 0
 #define IRQ_SYSTEM_TIMER_1  1
 #define IRQ_SYSTEM_TIMER_2 2

bsp/raspberry-pi/raspi3-64/qemu-64.bat

@@ -1,4 +1,6 @@
-if [ ! -f "sd.bin" ]; then
-dd if=/dev/zero of=sd.bin bs=1024 count=65536
-fi
-qemu-system-aarch64 -M raspi3 -kernel kernel8.img -serial null -serial stdio -sd sd.bin -nographic -monitor pty
+@echo off
+if exist sd.bin goto run
+qemu-img create -f raw sd.bin 64M
+
+:run
+qemu-system-aarch64 -M raspi3 -kernel kernel8.img -serial null -serial stdio -sd sd.bin

bsp/raspberry-pi/raspi3-64/qemu-64.sh

@@ -0,0 +1,4 @@
+if [ ! -f "sd.bin" ]; then
+dd if=/dev/zero of=sd.bin bs=1024 count=65536
+fi
+qemu-system-aarch64 -M raspi3 -kernel kernel8.img -serial null -serial stdio -sd sd.bin -nographic -monitor pty

bsp/raspberry-pi/raspi3-64/rtconfig.h

@@ -19,6 +19,9 @@
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 2048
+
+/* kservice optimization */
+
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
 
@@ -45,7 +48,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 512
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40003
+#define RT_VER_NUM 0x40004
 #define ARCH_CPU_64BIT
 #define ARCH_ARMV8
 
@@ -62,17 +65,17 @@
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
-#define FINSH_USING_MSH_ONLY
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -90,6 +93,8 @@
 #define RT_DFS_ELM_WORD_ACCESS
 #define RT_DFS_ELM_USE_LFN_3
 #define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
 #define RT_DFS_ELM_MAX_LFN 255
 #define RT_DFS_ELM_DRIVES 2
 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512
@@ -101,6 +106,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_HWTIMER
 #define RT_USING_I2C
@@ -124,6 +130,7 @@
 
 #define RT_USING_LIBC
 #define RT_USING_POSIX
+#define RT_LIBC_DEFAULT_TIMEZONE 8
 
 /* Network */
 
@@ -145,6 +152,9 @@
 /* Utilities */
 
 
+/* RT-Thread Utestcases */
+
+
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
@@ -175,16 +185,27 @@
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
 
 /* peripheral libraries and drivers */
 
 
-/* miscellaneous packages */
+/* AI packages */
+
 
+/* miscellaneous packages */
 
 /* samples: kernel and components samples */
 
+
+/* entertainment: terminal games and other interesting software packages */
+
 #define BCM2836_SOC
+#define BSP_SUPPORT_FPU
 
 /* Hardware Drivers Config */
 

bsp/raspberry-pi/raspi3-64/rtconfig.py

@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH        ='aarch64'
-CPU         ='cortex-a53'
+CPU         ='cortex-a'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):

bsp/raspberry-pi/raspi4-64/.config

@@ -23,6 +23,13 @@ CONFIG_IDLE_THREAD_STACK_SIZE=2048
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
 CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_COLOR is not set
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -54,6 +61,7 @@ CONFIG_RT_USING_MEMPOOL=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -65,8 +73,9 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
-CONFIG_RT_VER_NUM=0x40003
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
 CONFIG_ARCH_CPU_64BIT=y
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_ARMV8=y
@@ -89,19 +98,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
 CONFIG_FINSH_ARG_MAX=10
 
 #
@@ -113,34 +122,68 @@ CONFIG_DFS_FILESYSTEMS_MAX=2
 CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
 CONFIG_DFS_FD_MAX=16
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_RTC=y
+CONFIG_RT_USING_ALARM=y
+# CONFIG_RT_USING_SOFT_RTC is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_SDIO_STACK_SIZE=512
+CONFIG_RT_SDIO_THREAD_PRIORITY=15
+CONFIG_RT_MMCSD_STACK_SIZE=2048
+CONFIG_RT_MMCSD_THREAD_PREORITY=22
+CONFIG_RT_MMCSD_MAX_PARTITION=16
+# CONFIG_RT_SDIO_DEBUG is not set
 # CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
@@ -165,8 +208,10 @@ CONFIG_RT_USING_LIBC=y
 CONFIG_RT_USING_POSIX=y
 # CONFIG_RT_USING_POSIX_MMAP is not set
 # CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
 # CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 
 #
 # Network
@@ -175,22 +220,93 @@ CONFIG_RT_USING_POSIX=y
 #
 # Socket abstraction layer
 #
-# CONFIG_RT_USING_SAL is not set
+CONFIG_RT_USING_SAL=y
+CONFIG_SAL_INTERNET_CHECK=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+# CONFIG_SAL_USING_POSIX is not set
+CONFIG_SAL_SOCKETS_NUM=16
 
 #
 # Network interface device
 #
-# CONFIG_RT_USING_NETDEV is not set
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
 
 #
 # light weight TCP/IP stack
 #
-# CONFIG_RT_USING_LWIP is not set
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+CONFIG_RT_USING_LWIP203=y
+# CONFIG_RT_USING_LWIP212 is not set
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=2048
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+# CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_RT_LWIP_DEBUG is not set
 
 #
 # AT commands
 #
 # CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set
 
 #
 # VBUS(Virtual Software BUS)
@@ -200,9 +316,17 @@ CONFIG_RT_USING_POSIX=y
 #
 # Utilities
 #
-# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
 
 #
 # RT-Thread online packages
@@ -211,7 +335,9 @@ CONFIG_RT_USING_POSIX=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
@@ -249,6 +375,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
 
 #
 # IoT Cloud
@@ -257,7 +384,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
@@ -269,8 +396,6 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LIBRWS is not set
 # CONFIG_PKG_USING_TCPSERVER is not set
 # CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
@@ -279,6 +404,20 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -287,6 +426,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -294,6 +434,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
 
 #
 # multimedia packages
@@ -303,6 +444,13 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
 
 #
 # tools packages
@@ -311,25 +459,65 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
 # CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
 
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
 # CONFIG_PKG_USING_FLASHDB is not set
@@ -339,12 +527,27 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
 # CONFIG_PKG_USING_EV is not set
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
 
 #
 # peripheral libraries and drivers
@@ -353,6 +556,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -368,7 +572,6 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@@ -382,6 +585,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
 # CONFIG_PKG_USING_MULTI_RTIMER is not set
@@ -390,44 +594,102 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
 # CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
 
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
 CONFIG_BCM2711_SOC=y
-# CONFIG_BSP_SUPPORT_FPU is not set
+CONFIG_BSP_SUPPORT_FPU=y
 
 #
 # Hardware Drivers Config
@@ -438,15 +700,22 @@ CONFIG_BCM2711_SOC=y
 #
 CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART0=y
+# CONFIG_RT_USING_UART1 is not set
+# CONFIG_RT_USING_UART3 is not set
+# CONFIG_RT_USING_UART4 is not set
+# CONFIG_RT_USING_UART5 is not set
 CONFIG_BSP_USING_GIC=y
 CONFIG_BSP_USING_GIC400=y
 # CONFIG_BSP_USING_GIC500 is not set
 CONFIG_BSP_USING_PIN=y
 CONFIG_BSP_USING_CORETIMER=y
 # CONFIG_BSP_USING_SYSTIMER is not set
+CONFIG_BSP_USING_ETH=y
 # CONFIG_BSP_USING_WDT is not set
-# CONFIG_BSP_USING_RTC is not set
-# CONFIG_BSP_USING_SDIO is not set
+CONFIG_BSP_USING_RTC=y
+CONFIG_BSP_USING_ALARM=y
+CONFIG_BSP_USING_SDIO=y
+CONFIG_BSP_USING_SDIO0=y
 
 #
 # Board Peripheral Drivers

bsp/raspberry-pi/raspi4-64/README.md

@@ -101,7 +101,11 @@ msh />
 
 | 驱动 | 支持情况  |  备注  |
 | ------ | ----  | :------:  |
-| UART | 支持 | UART0|
+| UART | 支持 | UART0,UART2,UART3,UART4,UART5 |
+| GPIO | 支持 | - |
+| MAILBOX | 支持 | - |
+| SDIO | 支持 | - |
+| ETH | 支持 | - |
 
 ## 5. 联系人信息
 

bsp/raspberry-pi/raspi4-64/applications/mnt.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-5-30     bernard       the first version
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_SDIO0
+#include <dfs_fs.h>
+
+int mnt_init(void)
+{
+    rt_thread_delay(RT_TICK_PER_SECOND);
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("file system initialization done!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif

bsp/raspberry-pi/raspi4-64/driver/Kconfig

@@ -14,8 +14,24 @@ menu "Hardware Drivers Config"
                 config RT_USING_UART0
                 bool "Enabel UART 0"
                 default y
+
+                config RT_USING_UART1
+                bool "Enabel UART 1"
+                default n
+
+                config RT_USING_UART3
+                bool "Enabel UART 3"
+                default n
+
+                config RT_USING_UART4
+                bool "Enabel UART 4"
+                default n
+
+                config RT_USING_UART5
+                bool "Enabel UART 5"
+                default n
             endif
-            
+
         menuconfig BSP_USING_GIC
             bool "Enable GIC"
             select RT_USING_GIC
@@ -53,6 +69,10 @@ menu "Hardware Drivers Config"
                 default n
         endif
 
+        config BSP_USING_ETH
+            bool "Enable ETH"
+            default n
+
         config BSP_USING_WDT
             bool "Enable WDT"
             select RT_USING_WDT

bsp/raspberry-pi/raspi4-64/driver/board.c

@@ -16,7 +16,9 @@
 
 #include "cp15.h"
 #include "mmu.h"
+#include "mbox.h"
 
+#ifdef BSP_USING_CORETIMER
 static rt_uint64_t timerStep;
 
 int rt_hw_get_gtimer_frq(void);
@@ -29,15 +31,21 @@ void core0_timer_enable_interrupt_controller(void)
 {
     CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
 }
+#endif
 
 void rt_hw_timer_isr(int vector, void *parameter)
 {
+#ifdef BSP_USING_CORETIMER
     rt_hw_set_gtimer_val(timerStep);
+#else
+    ARM_TIMER_IRQCLR = 0;
+#endif
     rt_tick_increase();
 }
 
 void rt_hw_timer_init(void)
 {
+#ifdef BSP_USING_CORETIMER
     rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
     rt_hw_interrupt_umask(TIMER_IRQ);
     __ISB();
@@ -48,6 +56,27 @@ void rt_hw_timer_init(void)
     rt_hw_gtimer_enable();
     rt_hw_set_gtimer_val(timerStep);
     core0_timer_enable_interrupt_controller();
+#else
+    rt_uint32_t apb_clock = 0;
+    rt_uint32_t timer_clock = 1000000;
+
+    apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
+    ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);
+
+    ARM_TIMER_RELOAD = 0;
+    ARM_TIMER_LOAD   = 0;
+    ARM_TIMER_IRQCLR = 0;
+    ARM_TIMER_CTRL   = 0;
+
+    ARM_TIMER_RELOAD = 1000000 / RT_TICK_PER_SECOND;
+    ARM_TIMER_LOAD   = 1000000 / RT_TICK_PER_SECOND;
+
+    /* 23-bit counter, enable interrupt, enable timer */
+    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
+
+    rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(ARM_TIMER_IRQ);
+#endif
 }
 
 void idle_wfi(void)
@@ -65,6 +94,13 @@ void rt_hw_board_init(void)
     armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
     armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
     armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
+    armv8_map(ARM_TIMER_BASE, ARM_TIMER_BASE, 0x200000, MEM_ATTR_IO);//arm timer
+    armv8_map(STIMER_BASE, STIMER_BASE, 0x200000, MEM_ATTR_IO);//stimer
+    armv8_map(MMC2_BASE_ADDR, MMC2_BASE_ADDR, 0x200000, MEM_ATTR_IO);//mmc
+    armv8_map(MBOX_ADDR, MBOX_ADDR, 0x200000, MEM_ATTR_IO);//mbox msg
+    armv8_map((unsigned long)MAC_REG_BASE_ADDR, (unsigned long)MAC_REG_BASE_ADDR, 0x80000, MEM_ATTR_IO);//mac
+    armv8_map(SEND_DATA_NO_CACHE, SEND_DATA_NO_CACHE, 0x200000, MEM_ATTR_MEMORY);//eth send
+    armv8_map(RECV_DATA_NO_CACHE, RECV_DATA_NO_CACHE, 0x200000, MEM_ATTR_MEMORY);//eth recv
     mmu_enable();
 
     /* initialize hardware interrupt */

bsp/raspberry-pi/raspi4-64/driver/drv_eth.c

@@ -0,0 +1,723 @@
+
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-10-30     bigmagic       first version
+ */
+
+#include <rtdef.h>
+#include <rthw.h>
+#include <stdint.h>
+#include <rtthread.h>
+#include <lwip/sys.h>
+#include <netif/ethernetif.h>
+#include <mmu.h>
+
+#include "mbox.h"
+#include "raspi4.h"
+#include "drv_eth.h"
+
+#define DBG_LEVEL               DBG_LOG
+#include <rtdbg.h>
+#define LOG_TAG                 "drv.eth"
+
+#define RECV_CACHE_BUF          (2048)
+#define SEND_CACHE_BUF          (2048)
+#define DMA_DISC_ADDR_SIZE      (2 * 1024 *1024)
+
+#define RX_DESC_BASE            (MAC_REG_BASE_ADDR + GENET_RX_OFF)
+#define TX_DESC_BASE            (MAC_REG_BASE_ADDR + GENET_TX_OFF)
+
+#define MAX_ADDR_LEN            (6)
+
+#define upper_32_bits(n)        ((rt_uint32_t)(((n) >> 16) >> 16))
+#define lower_32_bits(n)        ((rt_uint32_t)(n))
+
+#define BIT(nr)                 (1UL << (nr))
+
+#define LINK_THREAD_STACK_SIZE  (1024)
+#define LINK_THREAD_PRIORITY    (20)
+#define LINK_THREAD_TIMESLICE   (10)
+
+static int link_speed = 0;
+static int link_flag = 0;
+
+static rt_thread_t link_thread_tid = RT_NULL;
+
+static rt_uint32_t tx_index = 0;
+static rt_uint32_t rx_index = 0;
+static rt_uint32_t index_flag = 0;
+
+
+struct rt_eth_dev
+{
+    struct eth_device parent;
+    rt_uint8_t dev_addr[MAX_ADDR_LEN];
+    char *name;
+    void *iobase;
+    int state;
+    int index;
+    struct rt_timer link_timer;
+    void *priv;
+};
+static struct rt_eth_dev eth_dev;
+
+static struct rt_semaphore send_finsh_sem_lock;
+
+static struct rt_semaphore link_ack;
+
+rt_inline rt_uint32_t read32(void *addr)
+{
+    return (*((volatile unsigned int *)(addr)));
+}
+
+rt_inline void write32(void *addr, rt_uint32_t value)
+{
+    (*((volatile unsigned int *)(addr))) = value;
+}
+
+static void eth_rx_irq(int irq, void *param)
+{
+    rt_uint32_t val = 0;
+
+    val = read32(MAC_REG_BASE_ADDR + GENET_INTRL2_CPU_STAT);
+    val &= ~read32(MAC_REG_BASE_ADDR + GENET_INTRL2_CPU_STAT_MASK);
+
+    write32(MAC_REG_BASE_ADDR + GENET_INTRL2_CPU_CLEAR, val);
+
+    if (val & GENET_IRQ_RXDMA_DONE)
+    {
+        eth_device_ready(&eth_dev.parent);
+    }
+
+    if (val & GENET_IRQ_TXDMA_DONE)
+    {
+        rt_sem_release(&send_finsh_sem_lock);
+    }
+}
+
+/* we only support RGMII (as used on the RPi4) */
+static int bcmgenet_interface_set(void)
+{
+    int phy_mode = PHY_INTERFACE_MODE_RGMII;
+
+    switch (phy_mode)
+    {
+    case PHY_INTERFACE_MODE_RGMII:
+    case PHY_INTERFACE_MODE_RGMII_RXID:
+        write32(MAC_REG_BASE_ADDR + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
+        break;
+    default:
+        rt_kprintf("unknown phy mode: %d\n", MAC_REG_BASE_ADDR);
+        return -1;
+    }
+
+    return 0;
+}
+
+static void bcmgenet_umac_reset(void)
+{
+    rt_uint32_t reg;
+
+    reg = read32(MAC_REG_BASE_ADDR + SYS_RBUF_FLUSH_CTRL);
+    reg |= BIT(1);
+    write32((MAC_REG_BASE_ADDR + SYS_RBUF_FLUSH_CTRL), reg);
+
+    reg &= ~BIT(1);
+    write32((MAC_REG_BASE_ADDR + SYS_RBUF_FLUSH_CTRL), reg);
+
+    DELAY_MICROS(10);
+
+    write32((MAC_REG_BASE_ADDR + SYS_RBUF_FLUSH_CTRL), 0);
+    DELAY_MICROS(10);
+
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, 0);
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
+    DELAY_MICROS(2);
+
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, 0);
+    /* clear tx/rx counter */
+    write32(MAC_REG_BASE_ADDR + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
+    write32(MAC_REG_BASE_ADDR + UMAC_MIB_CTRL, 0);
+    write32(MAC_REG_BASE_ADDR + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
+
+    /* init rx registers, enable ip header optimization */
+    reg = read32(MAC_REG_BASE_ADDR + RBUF_CTRL);
+    reg |= RBUF_ALIGN_2B;
+    write32(MAC_REG_BASE_ADDR + RBUF_CTRL, reg);
+    write32(MAC_REG_BASE_ADDR + RBUF_TBUF_SIZE_CTRL, 1);
+}
+
+static void bcmgenet_disable_dma(void)
+{
+    rt_uint32_t tdma_reg = 0, rdma_reg = 0;
+
+    tdma_reg = read32(MAC_REG_BASE_ADDR + TDMA_REG_BASE + DMA_CTRL);
+    tdma_reg &= ~(1UL << DMA_EN);
+    write32(MAC_REG_BASE_ADDR + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
+    rdma_reg = read32(MAC_REG_BASE_ADDR + RDMA_REG_BASE + DMA_CTRL);
+    rdma_reg &= ~(1UL << DMA_EN);
+    write32(MAC_REG_BASE_ADDR + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
+    write32(MAC_REG_BASE_ADDR + UMAC_TX_FLUSH, 1);
+    DELAY_MICROS(100);
+    write32(MAC_REG_BASE_ADDR + UMAC_TX_FLUSH, 0);
+}
+
+static void bcmgenet_enable_dma(void)
+{
+    rt_uint32_t reg = 0;
+    rt_uint32_t dma_ctrl = 0;
+
+    dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
+    write32(MAC_REG_BASE_ADDR + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
+
+    reg = read32(MAC_REG_BASE_ADDR + RDMA_REG_BASE + DMA_CTRL);
+    write32(MAC_REG_BASE_ADDR + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
+}
+
+static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value)
+{
+    int count = 10000;
+    rt_uint32_t val;
+    rt_uint32_t reg_val;
+
+    val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value);
+    write32(MAC_REG_BASE_ADDR + MDIO_CMD, val);
+
+    reg_val = read32(MAC_REG_BASE_ADDR + MDIO_CMD);
+    reg_val = reg_val | MDIO_START_BUSY;
+    write32(MAC_REG_BASE_ADDR + MDIO_CMD, reg_val);
+
+    while ((read32(MAC_REG_BASE_ADDR + MDIO_CMD) & MDIO_START_BUSY) && (--count))
+    {
+        DELAY_MICROS(1);
+    }
+
+    reg_val = read32(MAC_REG_BASE_ADDR + MDIO_CMD);
+
+    return reg_val & 0xffff;
+}
+
+static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
+{
+    int count = 10000;
+    rt_uint32_t val = 0;
+    rt_uint32_t reg_val = 0;
+
+    val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
+    write32(MAC_REG_BASE_ADDR + MDIO_CMD, val);
+
+    reg_val = read32(MAC_REG_BASE_ADDR + MDIO_CMD);
+    reg_val = reg_val | MDIO_START_BUSY;
+    write32(MAC_REG_BASE_ADDR + MDIO_CMD, reg_val);
+
+    while ((read32(MAC_REG_BASE_ADDR + MDIO_CMD) & MDIO_START_BUSY) && (--count))
+    {
+        DELAY_MICROS(1);
+    }
+
+    reg_val = read32(MAC_REG_BASE_ADDR + MDIO_CMD);
+
+    return reg_val & 0xffff;
+}
+
+static int bcmgenet_gmac_write_hwaddr(void)
+{
+    rt_uint8_t addr[6];
+    rt_uint32_t reg;
+
+    bcm271x_mbox_hardware_get_mac_address(&addr[0]);
+
+    reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
+    write32(MAC_REG_BASE_ADDR + UMAC_MAC0, reg);
+
+    reg = addr[4] << 8 | addr[5];
+    write32(MAC_REG_BASE_ADDR + UMAC_MAC1, reg);
+
+    return 0;
+}
+
+static int get_ethernet_uid(void)
+{
+    rt_uint32_t uid_high = 0;
+    rt_uint32_t uid_low = 0;
+    rt_uint32_t uid = 0;
+
+    uid_high = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_HIGH);
+    uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW);
+    uid = (uid_high << 16 | uid_low);
+
+    if (BCM54213PE_VERSION_B1 == uid)
+    {
+        LOG_I("version is B1\n");
+    }
+
+    return uid;
+}
+
+static void bcmgenet_mdio_init(void)
+{
+    /* get ethernet uid */
+    if (get_ethernet_uid() == 0)
+    {
+        return;
+    }
+
+    /* reset phy */
+    bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET);
+    /* read control reg */
+    bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
+    /* reset phy again */
+    bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET);
+    /* read control reg */
+    bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
+    /* read status reg */
+    bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
+    /* read status reg */
+    bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS);
+    bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV);
+
+    bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
+    bcmgenet_mdio_read(1, BCM54213PE_CONTROL);
+    /* half full duplex capability */
+    bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY));
+    bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
+
+    /* set mii control */
+    bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, (MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART | MII_CONTROL_PHY_FULL_DUPLEX | MII_CONTROL_SPEED_SELECTION));
+}
+
+static void rx_ring_init(void)
+{
+    write32(MAC_REG_BASE_ADDR + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
+    write32(MAC_REG_BASE_ADDR + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
+    write32(MAC_REG_BASE_ADDR + RDMA_READ_PTR, 0x0);
+    write32(MAC_REG_BASE_ADDR + RDMA_WRITE_PTR, 0x0);
+    write32(MAC_REG_BASE_ADDR + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
+
+    write32(MAC_REG_BASE_ADDR + RDMA_PROD_INDEX, 0x0);
+    write32(MAC_REG_BASE_ADDR + RDMA_CONS_INDEX, 0x0);
+    write32(MAC_REG_BASE_ADDR + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
+    write32(MAC_REG_BASE_ADDR + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
+    write32(MAC_REG_BASE_ADDR + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
+}
+
+static void tx_ring_init(void)
+{
+    write32(MAC_REG_BASE_ADDR + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
+    write32(MAC_REG_BASE_ADDR + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_READ_PTR, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_READ_PTR, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_READ_PTR, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_WRITE_PTR, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1);
+    write32(MAC_REG_BASE_ADDR + TDMA_PROD_INDEX, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_CONS_INDEX, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1);
+    write32(MAC_REG_BASE_ADDR + TDMA_FLOW_PERIOD, 0x0);
+    write32(MAC_REG_BASE_ADDR + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
+    write32(MAC_REG_BASE_ADDR + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
+}
+
+static void rx_descs_init(void)
+{
+    char *rxbuffs = (char *)RECV_DATA_NO_CACHE;
+    rt_uint32_t len_stat, i;
+    void *desc_base = (void *)RX_DESC_BASE;
+
+    len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
+    for (i = 0; i < RX_DESCS; i++)
+    {
+        write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
+        write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI), upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
+        write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS), len_stat);
+    }
+}
+
+static int bcmgenet_adjust_link(void)
+{
+    rt_uint32_t speed;
+    rt_uint32_t phy_dev_speed = link_speed;
+    rt_uint32_t reg1;
+
+    switch (phy_dev_speed)
+    {
+    case SPEED_1000:
+        speed = UMAC_SPEED_1000;
+        break;
+    case SPEED_100:
+        speed = UMAC_SPEED_100;
+        break;
+    case SPEED_10:
+        speed = UMAC_SPEED_10;
+        break;
+    default:
+        rt_kprintf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev_speed);
+        return -1;
+    }
+
+    reg1 = read32(MAC_REG_BASE_ADDR + EXT_RGMII_OOB_CTRL);
+    reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
+    write32(MAC_REG_BASE_ADDR + EXT_RGMII_OOB_CTRL, reg1);
+    DELAY_MICROS(1000);
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, speed << CMD_SPEED_SHIFT);
+
+    return 0;
+}
+
+void link_irq(void *param)
+{
+    if ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0)
+    {
+        rt_sem_release(&link_ack);
+    }
+}
+
+static int bcmgenet_gmac_eth_start(void)
+{
+    rt_uint32_t ret;
+    rt_uint32_t count = 10000;
+
+    bcmgenet_umac_reset();
+
+    bcmgenet_gmac_write_hwaddr();
+    /* disable RX/TX DMA and flush TX queues */
+    bcmgenet_disable_dma();
+    rx_ring_init();
+    rx_descs_init();
+    tx_ring_init();
+
+    /* enable RX/TX DMA */
+    bcmgenet_enable_dma();
+
+    /* ppdate MAC registers based on PHY property */
+    ret = bcmgenet_adjust_link();
+    if (ret)
+    {
+        rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret);
+        return ret;
+    }
+
+    /* wait tx index clear */
+    while ((read32(MAC_REG_BASE_ADDR + TDMA_CONS_INDEX) != 0) && (--count))
+    {
+        DELAY_MICROS(1);
+    }
+
+    tx_index = read32(MAC_REG_BASE_ADDR + TDMA_CONS_INDEX);
+    write32(MAC_REG_BASE_ADDR + TDMA_PROD_INDEX, tx_index);
+
+    index_flag = read32(MAC_REG_BASE_ADDR + RDMA_PROD_INDEX);
+
+    rx_index = index_flag % RX_DESCS;
+
+    write32(MAC_REG_BASE_ADDR + RDMA_CONS_INDEX, index_flag);
+    write32(MAC_REG_BASE_ADDR + RDMA_PROD_INDEX, index_flag);
+
+    /* enable Rx/Tx */
+    rt_uint32_t rx_tx_en;
+    rx_tx_en = read32(MAC_REG_BASE_ADDR + UMAC_CMD);
+    rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
+
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, rx_tx_en);
+
+    /* eanble IRQ for TxDMA done and RxDMA done */
+    write32(MAC_REG_BASE_ADDR + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
+
+    return 0;
+}
+
+static rt_uint32_t prev_recv_cnt = 0;
+static rt_uint32_t cur_recv_cnt = 0;
+static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
+{
+    void *desc_base;
+    rt_uint32_t length = 0, addr = 0;
+    rt_uint32_t prod_index = read32(MAC_REG_BASE_ADDR + RDMA_PROD_INDEX);
+
+    /* no buff */
+    if (prod_index == index_flag)
+    {
+        cur_recv_cnt = index_flag;
+        index_flag = 0x7fffffff;
+
+        return 0;
+    }
+    else
+    {
+        /* no new buff */
+        if (prev_recv_cnt == (prod_index & 0xffff))
+        {
+            return 0;
+        }
+
+        desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE;
+        length = read32(desc_base + DMA_DESC_LENGTH_STATUS);
+        length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
+        addr = read32(desc_base + DMA_DESC_ADDRESS_LO);
+        /*
+         * to cater for the IP headepr alignment the hardware does.
+         * This would actually not be needed if we don't program
+         * RBUF_ALIGN_2B
+         */
+
+        /* convert to memory address */
+        addr = addr + RECV_DATA_NO_CACHE - RECV_DATA_NO_CACHE;
+        rt_hw_dcache_invalidate_range(addr, length);
+
+        *packetp = (rt_uint8_t *)(unsigned long)(addr + RX_BUF_OFFSET);
+
+        rx_index = rx_index + 1;
+        if (rx_index >= RX_DESCS)
+        {
+            rx_index = 0;
+        }
+
+        write32(MAC_REG_BASE_ADDR + RDMA_CONS_INDEX, cur_recv_cnt);
+
+        cur_recv_cnt = cur_recv_cnt + 1;
+
+        if (cur_recv_cnt > 0xffff)
+        {
+            cur_recv_cnt = 0;
+        }
+        prev_recv_cnt = cur_recv_cnt;
+
+        return length - RX_BUF_OFFSET;
+    }
+}
+
+
+static int bcmgenet_gmac_eth_send(rt_uint32_t packet, int length, struct pbuf *p)
+{
+    void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
+    pbuf_copy_partial(p, (void *)(unsigned long)(packet + tx_index * SEND_CACHE_BUF), p->tot_len, 0);
+    rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
+    len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
+    len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
+    rt_hw_dcache_flush_range(packet + tx_index * SEND_CACHE_BUF, length);
+
+    rt_uint32_t prod_index;
+
+    prod_index = read32(MAC_REG_BASE_ADDR + TDMA_PROD_INDEX);
+
+    write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE + tx_index * SEND_CACHE_BUF);
+    write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
+    write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);
+
+    tx_index++;
+    if (tx_index >= TX_DESCS)
+    {
+        tx_index = 0;
+    }
+    prod_index = prod_index + 1;
+
+    if (prod_index > 0xffff)
+    {
+        prod_index = 0;
+    }
+
+    /* start Transmisson */
+    write32(MAC_REG_BASE_ADDR + TDMA_PROD_INDEX, prod_index);
+    return 0;
+}
+
+static void link_task_entry(void *param)
+{
+    struct eth_device *eth_device = (struct eth_device *)param;
+    RT_ASSERT(eth_device != RT_NULL);
+    struct rt_eth_dev *dev = &eth_dev;
+
+    /* start mdio */
+    bcmgenet_mdio_init();
+
+    /* start timer link */
+    rt_timer_init(&dev->link_timer, "link_timer",
+                  link_irq,
+                  NULL,
+                  100,
+                  RT_TIMER_FLAG_PERIODIC);
+    rt_timer_start(&dev->link_timer);
+
+    /* link wait forever */
+    rt_sem_take(&link_ack, RT_WAITING_FOREVER);
+    /* link up */
+    eth_device_linkchange(&eth_dev.parent, RT_TRUE);
+    rt_timer_stop(&dev->link_timer);
+
+    /* set mac */
+    bcmgenet_gmac_write_hwaddr();
+
+    /* check link speed */
+    if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11)))
+    {
+        link_speed = 1000;
+        rt_kprintf("Support link mode Speed 1000M\n");
+    }
+    else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9)))
+    {
+        link_speed = 100;
+        rt_kprintf("Support link mode Speed 100M\n");
+    }
+    else
+    {
+        link_speed = 10;
+        rt_kprintf("Support link mode Speed 10M\n");
+    }
+
+    /* convert to memory address */
+    bcmgenet_gmac_eth_start();
+
+    rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq");
+    rt_hw_interrupt_umask(ETH_IRQ);
+
+    link_flag = 1;
+}
+
+static rt_err_t bcmgenet_eth_init(rt_device_t device)
+{
+    rt_uint32_t ret = 0;
+    rt_uint32_t hw_reg = 0;
+
+    /* read GENET HW version */
+    rt_uint8_t major = 0;
+    hw_reg = read32(MAC_REG_BASE_ADDR + SYS_REV_CTRL);
+    major = (hw_reg >> 24) & 0x0f;
+
+    if (major != 6)
+    {
+        if (major == 5)
+        {
+            major = 4;
+        }
+        else if (major == 0)
+        {
+            major = 1;
+        }
+
+        rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f);
+
+        return RT_ERROR;
+    }
+
+    /* set interface */
+    ret = bcmgenet_interface_set();
+    if (ret)
+    {
+        return ret;
+    }
+
+    /* rbuf clear */
+    write32(MAC_REG_BASE_ADDR + SYS_RBUF_FLUSH_CTRL, 0);
+
+    /* disable MAC while updating its registers */
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, 0);
+    /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
+    write32(MAC_REG_BASE_ADDR + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
+
+    link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device,
+                                       LINK_THREAD_STACK_SIZE,
+                                       LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE);
+    if (link_thread_tid != RT_NULL)
+    {
+        rt_thread_startup(link_thread_tid);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
+{
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        if (args)
+        {
+            rt_memcpy(args, eth_dev.dev_addr, 6);
+        }
+        else
+        {
+            return -RT_ERROR;
+        }
+        break;
+    default:
+        break;
+    }
+    return RT_EOK;
+}
+
+rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
+{
+    if (link_flag == 1)
+    {
+        bcmgenet_gmac_eth_send((rt_uint32_t)SEND_DATA_NO_CACHE, p->tot_len, p);
+        rt_sem_take(&send_finsh_sem_lock, RT_WAITING_FOREVER);
+    }
+
+    return RT_EOK;
+}
+
+struct pbuf *rt_eth_rx(rt_device_t device)
+{
+    int recv_len = 0;
+    rt_uint8_t *addr_point = RT_NULL;
+    struct pbuf *pbuf = RT_NULL;
+
+    if (link_flag == 1)
+    {
+        recv_len = bcmgenet_gmac_eth_recv(&addr_point);
+        if (recv_len > 0)
+        {
+            pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
+            if (pbuf)
+            {
+                rt_memcpy(pbuf->payload, addr_point, recv_len);
+            }
+        }
+    }
+
+    return pbuf;
+}
+
+int rt_hw_eth_init(void)
+{
+    rt_uint8_t mac_addr[6];
+    rt_sem_init(&send_finsh_sem_lock, "send_finsh_sem_lock", TX_DESCS, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
+    memset(&eth_dev, 0, sizeof(eth_dev));
+    memset((void *)SEND_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE);
+    memset((void *)RECV_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE);
+    bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
+
+    eth_dev.iobase = MAC_REG_BASE_ADDR;
+    eth_dev.name = "e0";
+    eth_dev.dev_addr[0] = mac_addr[0];
+    eth_dev.dev_addr[1] = mac_addr[1];
+    eth_dev.dev_addr[2] = mac_addr[2];
+    eth_dev.dev_addr[3] = mac_addr[3];
+    eth_dev.dev_addr[4] = mac_addr[4];
+    eth_dev.dev_addr[5] = mac_addr[5];
+
+    eth_dev.parent.parent.type       = RT_Device_Class_NetIf;
+    eth_dev.parent.parent.init       = bcmgenet_eth_init;
+    eth_dev.parent.parent.open       = RT_NULL;
+    eth_dev.parent.parent.close      = RT_NULL;
+    eth_dev.parent.parent.read       = RT_NULL;
+    eth_dev.parent.parent.write      = RT_NULL;
+    eth_dev.parent.parent.control    = bcmgenet_eth_control;
+    eth_dev.parent.parent.user_data  = RT_NULL;
+
+    eth_dev.parent.eth_tx            = rt_eth_tx;
+    eth_dev.parent.eth_rx            = rt_eth_rx;
+
+    eth_device_init(&(eth_dev.parent), "e0");
+    /* link down */
+    eth_device_linkchange(&eth_dev.parent, RT_FALSE);
+
+    return 0;
+}
+INIT_COMPONENT_EXPORT(rt_hw_eth_init);

bsp/raspberry-pi/raspi4-64/driver/drv_eth.h

@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-10-30     bigmagic       first version
+ */
+
+#ifndef __DRV_ETH_H__
+#define __DRV_ETH_H__
+
+#define MAC_REG             (void *)(0xfd580000)
+
+#define SYS_REV_CTRL        (0x00)
+#define SYS_PORT_CTRL       (0x04)
+#define PORT_MODE_EXT_GPHY  (3)
+
+#define GENET_SYS_OFF       (0x0000)
+#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF  + 0x08)
+#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF  + 0x0c)
+
+#define GENET_EXT_OFF       (0x0080)
+#define EXT_RGMII_OOB_CTRL  (GENET_EXT_OFF + 0x0c)
+#define RGMII_LINK          BIT(4)
+#define OOB_DISABLE         BIT(5)
+#define RGMII_MODE_EN       BIT(6)
+#define ID_MODE_DIS         BIT(16)
+
+#define GENET_RBUF_OFF      (0x0300)
+#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4)
+#define RBUF_CTRL           (GENET_RBUF_OFF + 0x00)
+#define RBUF_ALIGN_2B       BIT(1)
+
+#define GENET_UMAC_OFF      (0x0800)
+#define UMAC_MIB_CTRL       (GENET_UMAC_OFF + 0x580)
+#define UMAC_MAX_FRAME_LEN  (GENET_UMAC_OFF + 0x014)
+#define UMAC_MAC0           (GENET_UMAC_OFF + 0x00c)
+#define UMAC_MAC1           (GENET_UMAC_OFF + 0x010)
+#define UMAC_CMD            (GENET_UMAC_OFF + 0x008)
+#define MDIO_CMD            (GENET_UMAC_OFF + 0x614)
+#define UMAC_TX_FLUSH       (GENET_UMAC_OFF + 0x334)
+#define MDIO_START_BUSY     BIT(29)
+#define MDIO_READ_FAIL      BIT(28)
+#define MDIO_RD             (2 << 26)
+#define MDIO_WR             BIT(26)
+#define MDIO_PMD_SHIFT      (21)
+#define MDIO_PMD_MASK       (0x1f)
+#define MDIO_REG_SHIFT      (16)
+#define MDIO_REG_MASK       (0x1f)
+
+#define  GENET_INTRL2_OFF               (0x0200)
+#define  GENET_INTRL2_CPU_STAT          (GENET_INTRL2_OFF + 0x00)
+#define  GENET_INTRL2_CPU_CLEAR         (GENET_INTRL2_OFF + 0x08)
+#define  GENET_INTRL2_CPU_STAT_MASK     (GENET_INTRL2_OFF + 0x0c)
+#define  GENET_INTRL2_CPU_SET_MASK      (GENET_INTRL2_OFF + 0x10)
+#define  GENET_INTRL2_CPU_CLEAR_MASK    (GENET_INTRL2_OFF + 0x14)
+#define  GENET_IRQ_MDIO_ERROR           BIT(24)
+#define  GENET_IRQ_MDIO_DONE            BIT(23)
+#define  GENET_IRQ_TXDMA_DONE           BIT(16)
+#define  GENET_IRQ_RXDMA_DONE           BIT(13)
+
+#define CMD_TX_EN           BIT(0)
+#define CMD_RX_EN           BIT(1)
+#define UMAC_SPEED_10       (0)
+#define UMAC_SPEED_100      (1)
+#define UMAC_SPEED_1000     (2)
+#define UMAC_SPEED_2500     (3)
+#define CMD_SPEED_SHIFT     (2)
+#define CMD_SPEED_MASK      (3)
+#define CMD_SW_RESET        BIT(13)
+#define CMD_LCL_LOOP_EN     BIT(15)
+#define CMD_TX_EN           BIT(0)
+#define CMD_RX_EN           BIT(1)
+
+#define MIB_RESET_RX        BIT(0)
+#define MIB_RESET_RUNT      BIT(1)
+#define MIB_RESET_TX        BIT(2)
+
+/* total number of Buffer Descriptors, same for Rx/Tx */
+#define TOTAL_DESCS         (256)
+#define RX_DESCS            TOTAL_DESCS
+#define TX_DESCS            TOTAL_DESCS
+
+#define DEFAULT_Q           (0x10)
+
+#define ETH_DATA_LEN        (1500)
+#define ETH_HLEN            (14)
+#define VLAN_HLEN           (4)
+#define ETH_FCS_LEN         (4)
+/*
+ * Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
+ * 1536 is multiple of 256 bytes
+ */
+#define ENET_BRCM_TAG_LEN   (6)
+#define ENET_PAD            (8)
+#define ENET_MAX_MTU_SIZE   (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
+
+/* Tx/Rx Dma Descriptor common bits */
+#define DMA_EN                     BIT(0)
+#define DMA_RING_BUF_EN_SHIFT      (0x01)
+#define DMA_RING_BUF_EN_MASK       (0xffff)
+#define DMA_BUFLENGTH_MASK         (0x0fff)
+#define DMA_BUFLENGTH_SHIFT        (16)
+#define DMA_RING_SIZE_SHIFT        (16)
+#define DMA_OWN                    (0x8000)
+#define DMA_EOP                    (0x4000)
+#define DMA_SOP                    (0x2000)
+#define DMA_WRAP                   (0x1000)
+#define DMA_MAX_BURST_LENGTH       (0x8)
+/* Tx specific DMA descriptor bits */
+#define DMA_TX_UNDERRUN            (0x0200)
+#define DMA_TX_APPEND_CRC          (0x0040)
+#define DMA_TX_OW_CRC              (0x0020)
+#define DMA_TX_DO_CSUM             (0x0010)
+#define DMA_TX_QTAG_SHIFT          (7)
+
+/* DMA rings size */
+#define DMA_RING_SIZE              (0x40)
+#define DMA_RINGS_SIZE             (DMA_RING_SIZE * (DEFAULT_Q + 1))
+
+/* DMA descriptor */
+#define DMA_DESC_LENGTH_STATUS     (0x00)
+#define DMA_DESC_ADDRESS_LO        (0x04)
+#define DMA_DESC_ADDRESS_HI        (0x08)
+#define DMA_DESC_SIZE              (12)
+
+#define GENET_RX_OFF               (0x2000)
+#define GENET_RDMA_REG_OFF         (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
+#define GENET_TX_OFF               (0x4000)
+#define GENET_TDMA_REG_OFF         (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
+
+#define DMA_FC_THRESH_HI           (RX_DESCS >> 4)
+#define DMA_FC_THRESH_LO           (5)
+#define DMA_FC_THRESH_VALUE        ((DMA_FC_THRESH_LO << 16) | DMA_FC_THRESH_HI)
+
+#define DMA_XOFF_THRESHOLD_SHIFT   (16)
+
+#define TDMA_RING_REG_BASE         (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
+#define TDMA_READ_PTR              (TDMA_RING_REG_BASE + 0x00)
+#define TDMA_CONS_INDEX            (TDMA_RING_REG_BASE + 0x08)
+#define TDMA_PROD_INDEX            (TDMA_RING_REG_BASE + 0x0c)
+#define DMA_RING_BUF_SIZE          (0x10)
+#define DMA_START_ADDR             (0x14)
+#define DMA_END_ADDR               (0x1c)
+#define DMA_MBUF_DONE_THRESH       (0x24)
+#define TDMA_FLOW_PERIOD           (TDMA_RING_REG_BASE + 0x28)
+#define TDMA_WRITE_PTR             (TDMA_RING_REG_BASE + 0x2c)
+
+#define RDMA_RING_REG_BASE         (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
+#define RDMA_WRITE_PTR             (RDMA_RING_REG_BASE + 0x00)
+#define RDMA_PROD_INDEX            (RDMA_RING_REG_BASE + 0x08)
+#define RDMA_CONS_INDEX            (RDMA_RING_REG_BASE + 0x0c)
+#define RDMA_XON_XOFF_THRESH       (RDMA_RING_REG_BASE + 0x28)
+#define RDMA_READ_PTR              (RDMA_RING_REG_BASE + 0x2c)
+
+#define TDMA_REG_BASE              (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
+#define RDMA_REG_BASE              (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
+#define DMA_RING_CFG               (0x00)
+#define DMA_CTRL                   (0x04)
+#define DMA_SCB_BURST_SIZE         (0x0c)
+
+#define RX_BUF_LENGTH              (2048)
+#define RX_TOTAL_BUFSIZE           (RX_BUF_LENGTH * RX_DESCS)
+#define RX_BUF_OFFSET              (2)
+
+#define PHY_INTERFACE_MODE_RGMII                (7)
+#define PHY_INTERFACE_MODE_RGMII_RXID           (9)
+
+#define  BCM54213PE_MII_CONTROL                 (0x00)
+#define  BCM54213PE_MII_STATUS                  (0x01)
+#define  BCM54213PE_PHY_IDENTIFIER_HIGH         (0x02)
+#define  BCM54213PE_PHY_IDENTIFIER_LOW          (0x03)
+
+#define  BCM54213PE_AUTO_NEGOTIATION_ADV        (0x04)
+#define  BCM54213PE_AUTO_NEGOTIATION_LINK       (0x05)
+#define  BCM54213PE_AUTO_NEGOTIATION_EXPANSION  (0x06)
+
+#define  BCM54213PE_NEXT_PAGE_TX                (0x07)
+
+#define  BCM54213PE_PARTNER_RX                  (0x08)
+
+#define  BCM54213PE_CONTROL                     (0x09)
+#define  BCM54213PE_STATUS                      (0x0A)
+
+#define  BCM54213PE_IEEE_EXTENDED_STATUS        (0x0F)
+#define  BCM54213PE_PHY_EXTENDED_CONTROL        (0x10)
+#define  BCM54213PE_PHY_EXTENDED_STATUS         (0x11)
+
+#define  BCM54213PE_RECEIVE_ERROR_COUNTER       (0x12)
+#define  BCM54213PE_FALSE_C_S_COUNTER           (0x13)
+#define  BCM54213PE_RECEIVE_NOT_OK_COUNTER      (0x14)
+
+#define BCM54213PE_VERSION_B1                   (0x600d84a2)
+#define BCM54213PE_VERSION_X                    (0x600d84a0)
+
+//BCM54213PE_MII_CONTROL
+#define MII_CONTROL_PHY_RESET                   (1 << 15)
+#define MII_CONTROL_AUTO_NEGOTIATION_ENABLED    (1 << 12)
+#define MII_CONTROL_AUTO_NEGOTIATION_RESTART    (1 << 9)
+#define MII_CONTROL_PHY_FULL_DUPLEX             (1 << 8)
+#define MII_CONTROL_SPEED_SELECTION             (1 << 6)
+
+//BCM54213PE_MII_STATUS
+#define MII_STATUS_LINK_UP                      (1 << 2)
+
+//BCM54213PE_CONTROL
+#define CONTROL_FULL_DUPLEX_CAPABILITY          (1 << 9)
+#define CONTROL_HALF_DUPLEX_CAPABILITY          (1 << 8)
+
+#define SPEED_1000  (1000)
+#define SPEED_100   (100)
+#define SPEED_10    (10)
+
+#endif/* __DRV_ETH_H__ */

bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c

@@ -12,6 +12,63 @@
 
 #ifdef BSP_USING_PIN
 
+uint32_t raspi_get_pin_state(uint32_t fselnum)
+{
+    uint32_t gpfsel = 0;
+
+    switch (fselnum)
+    {
+    case 0:
+        gpfsel = GPIO_REG_GPFSEL0(GPIO_BASE);
+        break;
+    case 1:
+        gpfsel = GPIO_REG_GPFSEL1(GPIO_BASE);
+        break;
+    case 2:
+        gpfsel = GPIO_REG_GPFSEL2(GPIO_BASE);
+        break;
+    case 3:
+        gpfsel = GPIO_REG_GPFSEL3(GPIO_BASE);
+        break;
+    case 4:
+        gpfsel = GPIO_REG_GPFSEL4(GPIO_BASE);
+        break;
+    case 5:
+        gpfsel = GPIO_REG_GPFSEL5(GPIO_BASE);
+        break;
+    default:
+        break;
+    }
+    return gpfsel;
+}
+
+void raspi_set_pin_state(uint32_t fselnum, uint32_t gpfsel)
+{
+    switch (fselnum)
+    {
+    case 0:
+        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        break;
+    case 1:
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        break;
+    case 2:
+        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        break;
+    case 3:
+        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        break;
+    case 4:
+        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        break;
+    case 5:
+        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        break;
+    default:
+        break;
+    }
+}
+
 static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
 {
     uint32_t fselnum = pin / 10;
@@ -46,6 +103,18 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
+void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode)
+{
+    uint32_t fselnum = pin / 10;
+    uint32_t fselrest = pin % 10;
+    uint32_t gpfsel = 0;
+
+    gpfsel = raspi_get_pin_state(fselnum);
+    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
+    gpfsel |= (uint32_t)(mode << (fselrest * 3));
+    raspi_set_pin_state(fselnum, gpfsel);
+}
+
 static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
 {
     uint32_t num = pin / 32;

bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h

@@ -60,6 +60,50 @@
 #define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
 #define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
 
+typedef enum {
+    GPIO_PIN_0,
+    GPIO_PIN_1,
+    GPIO_PIN_2,
+    GPIO_PIN_3,
+    GPIO_PIN_4,
+    GPIO_PIN_5,
+    GPIO_PIN_6,
+    GPIO_PIN_7,
+    GPIO_PIN_8,
+    GPIO_PIN_9,
+    GPIO_PIN_10,
+    GPIO_PIN_11,
+    GPIO_PIN_12,
+    GPIO_PIN_13,
+    GPIO_PIN_14,
+    GPIO_PIN_15,
+    GPIO_PIN_16,
+    GPIO_PIN_17,
+    GPIO_PIN_18,
+    GPIO_PIN_19,
+    GPIO_PIN_20,
+    GPIO_PIN_21,
+    GPIO_PIN_22,
+    GPIO_PIN_23,
+    GPIO_PIN_24,
+    GPIO_PIN_25,
+    GPIO_PIN_26,
+    GPIO_PIN_27,
+    GPIO_PIN_28,
+    GPIO_PIN_29,
+    GPIO_PIN_30,
+    GPIO_PIN_31,
+    GPIO_PIN_32,
+    GPIO_PIN_33,
+    GPIO_PIN_34,
+    GPIO_PIN_35,
+    GPIO_PIN_36,
+    GPIO_PIN_37,
+    GPIO_PIN_38,
+    GPIO_PIN_39,
+    GPIO_PIN_40,
+} GPIO_PIN;
+
 typedef enum {
     INPUT = 0b000,
     OUTPUT = 0b001,
@@ -71,7 +115,8 @@ typedef enum {
     ALT5 = 0b010
 } GPIO_FUNC;
 
-
+void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode);
+void prev_raspi_pin_write(GPIO_PIN pin, int pin_value);
 int rt_hw_gpio_init(void);
 
 #endif /* __DRV_GPIO_H__ */

bsp/raspberry-pi/raspi4-64/driver/drv_sdio.c

@@ -0,0 +1,720 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-10-27     bigmagic       first version
+ */
+
+#include <rtdef.h>
+#include "mbox.h"
+#include "raspi4.h"
+#include "drv_sdio.h"
+
+#include "mmu.h"
+
+static rt_uint32_t mmc_base_clock = 0;
+
+static rt_uint32_t sdCommandTable[] =
+{
+    SD_CMD_INDEX(0),
+    SD_CMD_RESERVED(1),
+    SD_CMD_INDEX(2) | SD_RESP_R2,
+    SD_CMD_INDEX(3) | SD_RESP_R1,
+    SD_CMD_INDEX(4),
+    SD_CMD_RESERVED(5), //SD_CMD_INDEX(5) | SD_RESP_R4,
+    SD_CMD_INDEX(6) | SD_RESP_R1,
+    SD_CMD_INDEX(7) | SD_RESP_R1b,
+    SD_CMD_INDEX(8) | SD_RESP_R1,
+    SD_CMD_INDEX(9) | SD_RESP_R2,
+    SD_CMD_INDEX(10) | SD_RESP_R2,
+    SD_CMD_INDEX(11) | SD_RESP_R1,
+    SD_CMD_INDEX(12) | SD_RESP_R1b | SD_CMD_TYPE_ABORT,
+    SD_CMD_INDEX(13) | SD_RESP_R1,
+    SD_CMD_RESERVED(14),
+    SD_CMD_INDEX(15),
+    SD_CMD_INDEX(16) | SD_RESP_R1,
+    SD_CMD_INDEX(17) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_INDEX(18) | SD_RESP_R1 | SD_DATA_READ | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN,
+    SD_CMD_INDEX(19) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_INDEX(20) | SD_RESP_R1b,
+    SD_CMD_RESERVED(21),
+    SD_CMD_RESERVED(22),
+    SD_CMD_INDEX(23) | SD_RESP_R1,
+    SD_CMD_INDEX(24) | SD_RESP_R1 | SD_DATA_WRITE,
+    SD_CMD_INDEX(25) | SD_RESP_R1 | SD_DATA_WRITE | SD_CMD_MULTI_BLOCK | SD_CMD_BLKCNT_EN,
+    SD_CMD_INDEX(26) | SD_RESP_R1 | SD_DATA_WRITE,  // add
+    SD_CMD_INDEX(27) | SD_RESP_R1 | SD_DATA_WRITE,
+    SD_CMD_INDEX(28) | SD_RESP_R1b,
+    SD_CMD_INDEX(29) | SD_RESP_R1b,
+    SD_CMD_INDEX(30) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_RESERVED(31),
+    SD_CMD_INDEX(32) | SD_RESP_R1,
+    SD_CMD_INDEX(33) | SD_RESP_R1,
+    SD_CMD_RESERVED(34),
+    SD_CMD_INDEX(35) | SD_RESP_R1,  // add
+    SD_CMD_INDEX(36) | SD_RESP_R1,  // add
+    SD_CMD_RESERVED(37),
+    SD_CMD_INDEX(38) | SD_RESP_R1b,
+    SD_CMD_INDEX(39) | SD_RESP_R4,  // add
+    SD_CMD_INDEX(40) | SD_RESP_R5,  // add
+    SD_CMD_INDEX(41) | SD_RESP_R3,  // add, mov from harbote
+    SD_CMD_RESERVED(42) | SD_RESP_R1,
+    SD_CMD_RESERVED(43),
+    SD_CMD_RESERVED(44),
+    SD_CMD_RESERVED(45),
+    SD_CMD_RESERVED(46),
+    SD_CMD_RESERVED(47),
+    SD_CMD_RESERVED(48),
+    SD_CMD_RESERVED(49),
+    SD_CMD_RESERVED(50),
+    SD_CMD_INDEX(51) | SD_RESP_R1 | SD_DATA_READ,
+    SD_CMD_RESERVED(52),
+    SD_CMD_RESERVED(53),
+    SD_CMD_RESERVED(54),
+    SD_CMD_INDEX(55) | SD_RESP_R3,
+    SD_CMD_INDEX(56) | SD_RESP_R1 | SD_CMD_ISDATA,
+    SD_CMD_RESERVED(57),
+    SD_CMD_RESERVED(58),
+    SD_CMD_RESERVED(59),
+    SD_CMD_RESERVED(60),
+    SD_CMD_RESERVED(61),
+    SD_CMD_RESERVED(62),
+    SD_CMD_RESERVED(63)
+};
+
+rt_inline rt_uint32_t read32(rt_ubase_t addr)
+{
+    return (*((volatile unsigned int *)(addr)));
+}
+
+rt_inline void write32(rt_ubase_t addr, rt_uint32_t value)
+{
+    (*((volatile unsigned int *)(addr))) = value;
+}
+
+rt_err_t sd_int(struct sdhci_pdata_t *pdat, rt_uint32_t mask)
+{
+    rt_uint32_t r;
+    rt_uint32_t m = mask | INT_ERROR_MASK;
+    int cnt = 1000000;
+    while (!(read32(pdat->virt + EMMC_INTERRUPT) & (m | INT_ERROR_MASK)) && cnt--)
+    {
+        DELAY_MICROS(1);
+    }
+    r = read32(pdat->virt + EMMC_INTERRUPT);
+    if (cnt <= 0 || (r & INT_CMD_TIMEOUT) || (r & INT_DATA_TIMEOUT))
+    {
+        write32(pdat->virt + EMMC_INTERRUPT, r);
+        /* qemu maybe can not use sdcard */
+        rt_kprintf("send cmd/data timeout wait for %x int: %x, status: %x\n", mask, r, read32(pdat->virt + EMMC_STATUS));
+
+        return -RT_ETIMEOUT;
+    }
+    else if (r & INT_ERROR_MASK)
+    {
+        write32(pdat->virt + EMMC_INTERRUPT, r);
+        rt_kprintf("send cmd/data error %x -> %x\n", r, read32(pdat->virt + EMMC_INTERRUPT));
+
+        return -RT_ERROR;
+    }
+    write32(pdat->virt + EMMC_INTERRUPT, mask);
+    return RT_EOK;
+}
+
+rt_err_t sd_status(struct sdhci_pdata_t *pdat, unsigned int mask)
+{
+    int cnt = 500000;
+    while ((read32(pdat->virt + EMMC_STATUS) & mask) && !(read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK) && cnt--)
+    {
+        DELAY_MICROS(1);
+    }
+    if (cnt <= 0)
+    {
+        return -RT_ETIMEOUT;
+    }
+    else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK)
+    {
+        return  -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t raspi_transfer_command(struct sdhci_pdata_t *pdat, struct sdhci_cmd_t *cmd)
+{
+    rt_uint32_t cmdidx;
+    rt_err_t ret = RT_EOK;
+    ret = sd_status(pdat, SR_CMD_INHIBIT);
+    if (ret)
+    {
+        rt_kprintf("ERROR: EMMC busy %d\n", ret);
+        return ret;
+    }
+
+    cmdidx = sdCommandTable[cmd->cmdidx];
+    if (cmdidx == 0xFFFFFFFF)
+    {
+        return -RT_EINVAL;
+    }
+    if (cmd->datarw == DATA_READ)
+    {
+        cmdidx |= SD_DATA_READ;
+    }
+    if (cmd->datarw == DATA_WRITE)
+    {
+        cmdidx |= SD_DATA_WRITE;
+    }
+
+    mmcsd_dbg("transfer cmd %x(%d) %x %x\n", cmdidx, cmd->cmdidx, cmd->cmdarg, read32(pdat->virt + EMMC_INTERRUPT));
+    write32(pdat->virt + EMMC_INTERRUPT, read32(pdat->virt + EMMC_INTERRUPT));
+    write32(pdat->virt + EMMC_ARG1, cmd->cmdarg);
+    write32(pdat->virt + EMMC_CMDTM, cmdidx);
+    if (cmd->cmdidx == SD_APP_OP_COND)
+    {
+        DELAY_MICROS(1000);
+    }
+    else if ((cmd->cmdidx == SD_SEND_IF_COND) || (cmd->cmdidx == APP_CMD))
+    {
+        DELAY_MICROS(100);
+    }
+
+    ret = sd_int(pdat, INT_CMD_DONE);
+    if (ret)
+    {
+        return ret;
+    }
+    if (cmd->resptype & RESP_MASK)
+    {
+
+        if (cmd->resptype & RESP_R2)
+        {
+            rt_uint32_t resp[4];
+            resp[0] = read32(pdat->virt + EMMC_RESP0);
+            resp[1] = read32(pdat->virt + EMMC_RESP1);
+            resp[2] = read32(pdat->virt + EMMC_RESP2);
+            resp[3] = read32(pdat->virt + EMMC_RESP3);
+            if (cmd->resptype == RESP_R2)
+            {
+                cmd->response[0] = resp[3] << 8 | ((resp[2] >> 24) & 0xff);
+                cmd->response[1] = resp[2] << 8 | ((resp[1] >> 24) & 0xff);
+                cmd->response[2] = resp[1] << 8 | ((resp[0] >> 24) & 0xff);
+                cmd->response[3] = resp[0] << 8 ;
+            }
+            else
+            {
+                cmd->response[0] = resp[0];
+                cmd->response[1] = resp[1];
+                cmd->response[2] = resp[2];
+                cmd->response[3] = resp[3];
+            }
+        }
+        else
+        {
+            cmd->response[0] = read32(pdat->virt + EMMC_RESP0);
+        }
+    }
+
+    mmcsd_dbg("response: %x: %x %x %x %x (%x, %x)\n", cmd->resptype, cmd->response[0], cmd->response[1], cmd->response[2], cmd->response[3], read32(pdat->virt + EMMC_STATUS), read32(pdat->virt + EMMC_INTERRUPT));
+    return ret;
+}
+
+static rt_err_t read_bytes(struct sdhci_pdata_t *pdat, rt_uint32_t *buf, rt_uint32_t blkcount, rt_uint32_t blksize)
+{
+    int c = 0;
+    rt_err_t ret;
+    int d;
+
+    while (c < blkcount)
+    {
+        if ((ret = sd_int(pdat, INT_READ_RDY)))
+        {
+            rt_kprintf("timeout happens when reading block %d\n", c);
+            return ret;
+        }
+        for (d = 0; d < blksize / 4; d++)
+        {
+            if (read32(pdat->virt + EMMC_STATUS) & SR_READ_AVAILABLE)
+            {
+                buf[d] = read32(pdat->virt + EMMC_DATA);
+            }
+        }
+        c++;
+        buf += blksize / 4;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t write_bytes(struct sdhci_pdata_t *pdat, rt_uint32_t *buf, rt_uint32_t blkcount, rt_uint32_t blksize)
+{
+    int c = 0;
+    rt_err_t ret;
+    int d;
+    while (c < blkcount)
+    {
+        if ((ret = sd_int(pdat, INT_WRITE_RDY)))
+        {
+            return ret;
+        }
+        for (d = 0; d < blksize / 4; d++)
+        {
+            write32(pdat->virt + EMMC_DATA, buf[d]);
+        }
+        c++;
+        buf += blksize / 4;
+    }
+
+    if ((ret = sd_int(pdat, INT_DATA_DONE)))
+    {
+        return ret;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t raspi_transfer_data(struct sdhci_pdata_t *pdat, struct sdhci_cmd_t *cmd, struct sdhci_data_t *dat)
+{
+    rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz);
+    rt_err_t ret = sd_status(pdat, SR_DAT_INHIBIT);
+
+    if (ret)
+    {
+        rt_kprintf("ERROR: EMMC busy\n");
+        return ret;
+    }
+    if (dat->blkcnt > 1)
+    {
+        struct sdhci_cmd_t newcmd;
+        newcmd.cmdidx = SET_BLOCK_COUNT;
+        newcmd.cmdarg = dat->blkcnt;
+        newcmd.resptype = RESP_R1;
+        ret = raspi_transfer_command(pdat, &newcmd);
+        if (ret)
+        {
+            return ret;
+        }
+    }
+
+    if (dlen < 512)
+    {
+        write32(pdat->virt + EMMC_BLKSIZECNT, dlen | 1 << 16);
+    }
+    else
+    {
+        write32(pdat->virt + EMMC_BLKSIZECNT, 512 | (dat->blkcnt) << 16);
+    }
+    if (dat->flag & DATA_DIR_READ)
+    {
+        cmd->datarw = DATA_READ;
+        ret = raspi_transfer_command(pdat, cmd);
+        if (ret)
+        {
+            return ret;
+        }
+        mmcsd_dbg("read_block %d, %d\n", dat->blkcnt, dat->blksz);
+        ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
+    }
+    else if (dat->flag & DATA_DIR_WRITE)
+    {
+        cmd->datarw = DATA_WRITE;
+        ret = raspi_transfer_command(pdat, cmd);
+        if (ret)
+        {
+            return ret;
+        }
+        mmcsd_dbg("write_block %d, %d", dat->blkcnt, dat->blksz);
+        ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
+    }
+    return ret;
+}
+
+static rt_err_t sdhci_transfer(struct sdhci_t *sdhci, struct sdhci_cmd_t *cmd, struct sdhci_data_t *dat)
+{
+    struct sdhci_pdata_t *pdat = (struct sdhci_pdata_t *)sdhci->priv;
+    if (!dat)
+    {
+        return raspi_transfer_command(pdat, cmd);
+    }
+
+    return raspi_transfer_data(pdat, cmd, dat);
+}
+
+static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
+    struct sdhci_cmd_t cmd;
+    struct sdhci_cmd_t stop;
+    struct sdhci_data_t dat;
+    rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t));
+    rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t));
+    rt_memset(&dat, 0, sizeof(struct sdhci_data_t));
+
+    cmd.cmdidx = req->cmd->cmd_code;
+    cmd.cmdarg = req->cmd->arg;
+    cmd.resptype = resp_type(req->cmd);
+    if (req->data)
+    {
+        dat.buf = (rt_uint8_t *)req->data->buf;
+        dat.flag = req->data->flags;
+        dat.blksz = req->data->blksize;
+        dat.blkcnt = req->data->blks;
+
+        req->cmd->err = sdhci_transfer(sdhci, &cmd, &dat);
+    }
+    else
+    {
+        req->cmd->err = sdhci_transfer(sdhci, &cmd, RT_NULL);
+    }
+
+    req->cmd->resp[3] = cmd.response[3];
+    req->cmd->resp[2] = cmd.response[2];
+    req->cmd->resp[1] = cmd.response[1];
+    req->cmd->resp[0] = cmd.response[0];
+
+    if (req->stop)
+    {
+        stop.cmdidx = req->stop->cmd_code;
+        stop.cmdarg = req->stop->arg;
+        cmd.resptype = resp_type(req->stop);
+        req->stop->err = sdhci_transfer(sdhci, &stop, RT_NULL);
+    }
+
+    mmcsd_req_complete(host);
+}
+
+rt_int32_t mmc_card_status(struct rt_mmcsd_host *host)
+{
+    return 0;
+}
+
+static rt_err_t sdhci_detect(struct sdhci_t *sdhci)
+{
+    return RT_EOK;
+}
+
+static rt_err_t sdhci_setwidth(struct sdhci_t *sdhci, rt_uint32_t width)
+{
+    rt_uint32_t temp = 0;
+    struct sdhci_pdata_t *pdat = (struct sdhci_pdata_t *)sdhci->priv;
+    if (width == MMCSD_BUS_WIDTH_4)
+    {
+        temp = read32((pdat->virt + EMMC_CONTROL0));
+        temp |= C0_HCTL_HS_EN;
+        temp |= C0_HCTL_DWITDH;   // always use 4 data lines:
+        write32((pdat->virt + EMMC_CONTROL0), temp);
+    }
+    return RT_EOK;
+}
+
+
+static uint32_t sd_get_clock_divider(rt_uint32_t sdHostVer, rt_uint32_t base_clock, rt_uint32_t target_rate)
+{
+    rt_uint32_t targetted_divisor = 0;
+    rt_uint32_t freq_select = 0;
+    rt_uint32_t upper_bits = 0;
+    rt_uint32_t ret = 0;
+    int divisor = -1;
+
+    if (target_rate > base_clock)
+    {
+        targetted_divisor = 1;
+    }
+    else
+    {
+        targetted_divisor = base_clock / target_rate;
+        rt_uint32_t mod = base_clock % target_rate;
+        if (mod)
+        {
+            targetted_divisor--;
+        }
+    }
+
+    // Decide on the clock mode to use
+
+    // Currently only 10-bit divided clock mode is supported
+
+    // HCI version 3 or greater supports 10-bit divided clock mode
+    // This requires a power-of-two divider
+
+    // Find the first bit set
+    for (int first_bit = 31; first_bit >= 0; first_bit--)
+    {
+        rt_uint32_t bit_test = (1 << first_bit);
+        if (targetted_divisor & bit_test)
+        {
+            divisor = first_bit;
+            targetted_divisor &= ~bit_test;
+            if (targetted_divisor)
+            {
+                // The divisor is not a power-of-two, increase it
+                divisor++;
+            }
+            break;
+        }
+    }
+
+    if (divisor == -1)
+    {
+        divisor = 31;
+    }
+    if (divisor >= 32)
+    {
+        divisor = 31;
+    }
+
+    if (divisor != 0)
+    {
+        divisor = (1 << (divisor - 1));
+    }
+
+    if (divisor >= 0x400)
+    {
+        divisor = 0x3ff;
+    }
+
+    freq_select = divisor & 0xff;
+    upper_bits = (divisor >> 8) & 0x3;
+    ret = (freq_select << 8) | (upper_bits << 6) | (0 << 5);
+
+    return ret;
+}
+
+static rt_err_t sdhci_setclock(struct sdhci_t *sdhci, rt_uint32_t clock)
+{
+    rt_uint32_t temp = 0;
+    rt_uint32_t sdHostVer = 0;
+    int count = 100000;
+    struct sdhci_pdata_t *pdat = (struct sdhci_pdata_t *)(sdhci->priv);
+
+    while ((read32(pdat->virt + EMMC_STATUS) & (SR_CMD_INHIBIT | SR_DAT_INHIBIT)) && (--count))
+    {
+        DELAY_MICROS(1);
+    }
+    if (count <= 0)
+    {
+        rt_kprintf("EMMC: Set clock: timeout waiting for inhibit flags. Status %08x.\n", read32(pdat->virt + EMMC_STATUS));
+        return RT_ERROR;
+    }
+
+    // Switch clock off.
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp &= ~C1_CLK_EN;
+    write32((pdat->virt + EMMC_CONTROL1), temp);
+    DELAY_MICROS(10);
+    // Request the new clock setting and enable the clock
+    temp = read32(pdat->virt + EMMC_SLOTISR_VER);
+    sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT;
+    int cdiv = sd_get_clock_divider(sdHostVer, mmc_base_clock, clock);
+    temp = read32((pdat->virt + EMMC_CONTROL1));
+    temp |= 1;
+    temp |= cdiv;
+    temp |= (7 << 16);
+
+    temp = (temp & 0xffff003f) | cdiv;
+    write32((pdat->virt + EMMC_CONTROL1), temp);
+    DELAY_MICROS(10);
+
+    // Enable the clock.
+    temp = read32(pdat->virt + EMMC_CONTROL1);
+    temp |= C1_CLK_EN;
+    write32((pdat->virt + EMMC_CONTROL1), temp);
+    DELAY_MICROS(10);
+
+    // wait for clock to be stable.
+    count = 10000;
+    while (!(read32(pdat->virt + EMMC_CONTROL1) & C1_CLK_STABLE) && count--)
+    {
+        DELAY_MICROS(10);
+    }
+
+    if (count <= 0)
+    {
+        rt_kprintf("EMMC: ERROR: failed to get stable clock %d.\n", clock);
+        return RT_ERROR;
+    }
+
+    mmcsd_dbg("set stable clock %d.\n", clock);
+    return RT_EOK;
+}
+
+static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
+    sdhci_setclock(sdhci, io_cfg->clock);
+    sdhci_setwidth(sdhci, io_cfg->bus_width);
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+    mmc_request_send,
+    mmc_set_iocfg,
+    RT_NULL,
+    RT_NULL,
+};
+
+static rt_err_t reset_emmc(struct sdhci_pdata_t *pdat)
+{
+    rt_uint32_t control1;
+    int cnt = 10000;
+
+    /* reset the controller */
+    control1 = read32((pdat->virt + EMMC_CONTROL1));
+    control1 |= (1 << 24);
+    /* disable clock */
+    control1 &= ~(1 << 2);
+    control1 &= ~(1 << 0);
+    /* temp |= C1_CLK_INTLEN | C1_TOUNIT_MAX; */
+    write32((pdat->virt + EMMC_CONTROL1), control1);
+
+    do
+    {
+        DELAY_MICROS(10);
+        --cnt;
+        if (cnt == 0)
+        {
+            break;
+        }
+    }
+    while ((read32(pdat->virt + EMMC_CONTROL1) & (0x7 << 24)) != 0);
+
+    // Enable SD Bus Power VDD1 at 3.3V
+    rt_uint32_t control0 = read32(pdat->virt + EMMC_CONTROL0);
+    control0 |= 0x0F << 8;
+    write32(pdat->virt + EMMC_CONTROL0, control0);
+
+    rt_thread_delay(100);
+
+    /* check for a valid card */
+    mmcsd_dbg("EMMC: checking for an inserted card\n");
+    cnt = 10000;
+
+    do
+    {
+        DELAY_MICROS(10);
+        --cnt;
+        if (cnt == 0)
+        {
+            break;
+        }
+    }
+    while ((read32(pdat->virt + EMMC_STATUS) & (0x1 << 16)) == 0);
+
+    rt_uint32_t status_reg = read32(pdat->virt + EMMC_STATUS);
+
+    if ((status_reg & (1 << 16)) == 0)
+    {
+        rt_kprintf("EMMC: no card inserted\n");
+        return -1;
+    }
+    else
+    {
+        mmcsd_dbg("EMMC: status: %08x\n", status_reg);
+    }
+
+    /* clear control2 */
+    write32(pdat->virt + EMMC_CONTROL2, 0);
+    /* get the base clock rate */
+    mmc_base_clock = bcm271x_mbox_clock_get_rate(EMMC_CLK_ID);
+    if (mmc_base_clock == 0)
+    {
+        rt_kprintf("EMMC: assuming clock rate to be 100MHz\n");
+        mmc_base_clock = 100000000;
+    }
+    mmcsd_dbg("EMMC: setting clock rate is %d\n", mmc_base_clock);
+
+    return RT_EOK;
+}
+
+#ifdef RT_MMCSD_DBG
+void dump_registers(struct sdhci_pdata_t *pdat)
+{
+    int i = EMMC_ARG2;
+
+    rt_kprintf("EMMC registers:");
+    for (; i <= EMMC_CONTROL2; i += 4)
+    {
+        rt_kprintf("\t%x:%x\n", i, read32(pdat->virt + i));
+    }
+    rt_kprintf("\t%x:%x\n", 0x50, read32(pdat->virt + 0x50));
+    rt_kprintf("\t%x:%x\n", 0x70, read32(pdat->virt + 0x70));
+    rt_kprintf("\t%x:%x\n", 0x74, read32(pdat->virt + 0x74));
+    rt_kprintf("\t%x:%x\n", 0x80, read32(pdat->virt + 0x80));
+    rt_kprintf("\t%x:%x\n", 0x84, read32(pdat->virt + 0x84));
+    rt_kprintf("\t%x:%x\n", 0x88, read32(pdat->virt + 0x88));
+    rt_kprintf("\t%x:%x\n", 0x8c, read32(pdat->virt + 0x8c));
+    rt_kprintf("\t%x:%x\n", 0x90, read32(pdat->virt + 0x90));
+    rt_kprintf("\t%x:%x\n", 0xf0, read32(pdat->virt + 0xf0));
+    rt_kprintf("\t%x:%x\n", 0xfc, read32(pdat->virt + 0xfc));
+}
+#endif
+
+int raspi_sdmmc_init(void)
+{
+    size_t virt;
+    struct rt_mmcsd_host *host = RT_NULL;
+    struct sdhci_pdata_t *pdat = RT_NULL;
+    struct sdhci_t *sdhci = RT_NULL;
+
+#ifdef BSP_USING_SDIO0
+    host = mmcsd_alloc_host();
+    if (!host)
+    {
+        rt_kprintf("alloc host failed");
+        goto err;
+    }
+    sdhci = rt_malloc(sizeof(struct sdhci_t));
+    if (!sdhci)
+    {
+        rt_kprintf("alloc sdhci failed");
+        goto err;
+    }
+    rt_memset(sdhci, 0, sizeof(struct sdhci_t));
+
+    virt = MMC2_BASE_ADDR;
+    pdat = (struct sdhci_pdata_t *)rt_malloc(sizeof(struct sdhci_pdata_t));
+    RT_ASSERT(pdat != RT_NULL);
+
+    pdat->virt = virt;
+    reset_emmc(pdat);
+    sdhci->name = "sd0";
+    sdhci->voltages = VDD_33_34;
+    sdhci->width = MMCSD_BUSWIDTH_4;
+    sdhci->clock = 1000 * 1000 * 1000;
+    sdhci->removeable = RT_TRUE;
+
+    sdhci->detect = sdhci_detect;
+    sdhci->setwidth = sdhci_setwidth;
+    sdhci->setclock = sdhci_setclock;
+    sdhci->transfer = sdhci_transfer;
+    sdhci->priv = pdat;
+    host->ops = &ops;
+    host->freq_min = 400000;
+    host->freq_max = 50000000;
+    host->valid_ocr = VDD_32_33 | VDD_33_34;
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
+    host->max_seg_size = 2048;
+    host->max_dma_segs = 10;
+    host->max_blk_size = 512;
+    host->max_blk_count = 1;
+
+    host->private_data = sdhci;
+    write32((pdat->virt + EMMC_IRPT_EN), 0xffffffff);
+    write32((pdat->virt + EMMC_IRPT_MASK), 0xffffffff);
+
+#ifdef RT_MMCSD_DBG
+    dump_registers(pdat);
+#endif
+    mmcsd_change(host);
+#endif
+    return RT_EOK;
+err:
+    if (host)  rt_free(host);
+    if (sdhci) rt_free(sdhci);
+
+    return -RT_EIO;
+}
+
+INIT_DEVICE_EXPORT(raspi_sdmmc_init);

bsp/raspberry-pi/raspi4-64/driver/drv_sdio.h

@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-10-27     bigmagic       first version
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drivers/mmcsd_core.h>
+
+#include "board.h"
+#include "raspi4.h"
+
+/* Struct for Intrrrupt Information */
+#define SDXC_CmdDone       BIT(0)
+#define SDXC_DataDone      BIT(1)
+#define SDXC_BlockGap      BIT(2)
+#define SDXC_WriteRdy      BIT(4)
+#define SDXC_ReadRdy       BIT(5)
+#define SDXC_Card          BIT(8)
+#define SDXC_Retune        BIT(12)
+#define SDXC_BootAck       BIT(13)
+#define SDXC_EndBoot       BIT(14)
+#define SDXC_Err           BIT(15)
+#define SDXC_CTOErr        BIT(16)
+#define SDXC_CCRCErr       BIT(17)
+#define SDXC_CENDErr       BIT(18)
+#define SDXC_CBADErr       BIT(19)
+#define SDXC_DTOErr        BIT(20)
+#define SDXC_DCRCErr       BIT(21)
+#define SDXC_DENDErr       BIT(22)
+#define SDXC_ACMDErr       BIT(24)
+
+#define SDXC_BLKCNT_EN          BIT(1)
+#define SDXC_AUTO_CMD12_EN      BIT(2)
+#define SDXC_AUTO_CMD23_EN      BIT(3)
+#define SDXC_DAT_DIR            BIT(4)   // from card to host
+#define SDXC_MULTI_BLOCK        BIT(5)
+#define SDXC_CMD_RSPNS_136      BIT(16)
+#define SDXC_CMD_RSPNS_48       BIT(17)
+#define SDXC_CMD_RSPNS_48busy   BIT(16)|BIT(17)
+#define SDXC_CHECK_CRC_CMD      BIT(19)
+#define SDXC_CMD_IXCHK_EN       BIT(20)
+#define SDXC_CMD_ISDATA         BIT(21)
+#define SDXC_CMD_SUSPEND        BIT(22)
+#define SDXC_CMD_RESUME         BIT(23)
+#define SDXC_CMD_ABORT          BIT(23)|BIT(22)
+
+#define SDXC_CMD_INHIBIT        BIT(0)
+#define SDXC_DAT_INHIBIT        BIT(1)
+#define SDXC_DAT_ACTIVE         BIT(2)
+#define SDXC_WRITE_TRANSFER     BIT(8)
+#define SDXC_READ_TRANSFER      BIT(9)
+
+struct sdhci_cmd_t
+{
+    rt_uint32_t cmdidx;
+    rt_uint32_t cmdarg;
+    rt_uint32_t resptype;
+    rt_uint32_t datarw;
+#define DATA_READ 1
+#define DATA_WRITE 2
+    rt_uint32_t response[4];
+};
+
+struct sdhci_data_t
+{
+    rt_uint8_t *buf;
+    rt_uint32_t flag;
+    rt_uint32_t blksz;
+    rt_uint32_t blkcnt;
+};
+
+struct sdhci_t
+{
+    char *name;
+    rt_uint32_t voltages;
+    rt_uint32_t width;
+    rt_uint32_t clock;
+    rt_err_t removeable;
+    void *sdcard;
+
+    rt_err_t (*detect)(struct sdhci_t *sdhci);
+    rt_err_t (*setwidth)(struct sdhci_t *sdhci, rt_uint32_t width);
+    rt_err_t (*setclock)(struct sdhci_t *sdhci, rt_uint32_t clock);
+    rt_err_t (*transfer)(struct sdhci_t *sdhci, struct sdhci_cmd_t *cmd, struct sdhci_data_t *dat);
+    void *priv;
+};
+
+struct sdhci_pdata_t
+{
+    size_t virt;
+};
+
+// EMMC command flags
+#define CMD_TYPE_NORMAL     (0x00000000)
+#define CMD_TYPE_SUSPEND    (0x00400000)
+#define CMD_TYPE_RESUME     (0x00800000)
+#define CMD_TYPE_ABORT      (0x00c00000)
+#define CMD_IS_DATA         (0x00200000)
+#define CMD_IXCHK_EN        (0x00100000)
+#define CMD_CRCCHK_EN       (0x00080000)
+#define CMD_RSPNS_NO        (0x00000000)
+#define CMD_RSPNS_136       (0x00010000)
+#define CMD_RSPNS_48        (0x00020000)
+#define CMD_RSPNS_48B       (0x00030000)
+#define TM_MULTI_BLOCK      (0x00000020)
+#define TM_DAT_DIR_HC       (0x00000000)
+#define TM_DAT_DIR_CH       (0x00000010)
+#define TM_AUTO_CMD23       (0x00000008)
+#define TM_AUTO_CMD12       (0x00000004)
+#define TM_BLKCNT_EN        (0x00000002)
+#define TM_MULTI_DATA       (CMD_IS_DATA|TM_MULTI_BLOCK|TM_BLKCNT_EN)
+
+#define RCA_NO              (1)
+#define RCA_YES             (2)
+
+// INTERRUPT register settings
+#define INT_AUTO_ERROR      (0x01000000)
+#define INT_DATA_END_ERR    (0x00400000)
+#define INT_DATA_CRC_ERR    (0x00200000)
+#define INT_DATA_TIMEOUT    (0x00100000)
+#define INT_INDEX_ERROR     (0x00080000)
+#define INT_END_ERROR       (0x00040000)
+#define INT_CRC_ERROR       (0x00020000)
+#define INT_CMD_TIMEOUT     (0x00010000)
+#define INT_ERR             (0x00008000)
+#define INT_ENDBOOT         (0x00004000)
+#define INT_BOOTACK         (0x00002000)
+#define INT_RETUNE          (0x00001000)
+#define INT_CARD            (0x00000100)
+#define INT_READ_RDY        (0x00000020)
+#define INT_WRITE_RDY       (0x00000010)
+#define INT_BLOCK_GAP       (0x00000004)
+#define INT_DATA_DONE       (0x00000002)
+#define INT_CMD_DONE        (0x00000001)
+#define INT_ERROR_MASK \
+( \
+    INT_CRC_ERROR | \
+    INT_END_ERROR | \
+    INT_INDEX_ERROR | \
+    INT_DATA_TIMEOUT | \
+    INT_DATA_CRC_ERR | \
+    INT_DATA_END_ERR | \
+    INT_ERR|INT_AUTO_ERROR \
+)
+
+#define INT_ALL_MASK \
+(\
+    INT_CMD_DONE | \
+    INT_DATA_DONE | \
+    INT_READ_RDY | \
+    INT_WRITE_RDY | \
+    INT_ERROR_MASK \
+)
+
+#define EMMC_ARG2           (0x00)
+#define EMMC_BLKSIZECNT     (0x04)
+#define EMMC_ARG1           (0x08)
+#define EMMC_CMDTM          (0x0c)
+#define EMMC_RESP0          (0x10)
+#define EMMC_RESP1          (0x14)
+#define EMMC_RESP2          (0x18)
+#define EMMC_RESP3          (0x1c)
+#define EMMC_DATA           (0x20)
+#define EMMC_STATUS         (0x24)
+#define EMMC_CONTROL0       (0x28)
+#define EMMC_CONTROL1       (0x2c)
+#define EMMC_INTERRUPT      (0x30)
+#define EMMC_IRPT_MASK      (0x34)
+#define EMMC_IRPT_EN        (0x38)
+#define EMMC_CONTROL2       (0x3c)
+#define EMMC_CAPABILITIES_0 (0x40)
+#define EMMC_CAPABILITIES_1 (0x44)
+#define EMMC_BOOT_TIMEOUT   (0x70)
+#define EMMC_EXRDFIFO_EN    (0x84)
+#define EMMC_SPI_INT_SPT    (0xf0)
+#define EMMC_SLOTISR_VER    (0xfc)
+
+// CONTROL register settings
+#define C0_SPI_MODE_EN      (0x00100000)
+#define C0_HCTL_HS_EN       (0x00000004)
+#define C0_HCTL_DWITDH      (0x00000002)
+
+#define C1_SRST_DATA        (0x04000000)
+#define C1_SRST_CMD         (0x02000000)
+#define C1_SRST_HC          (0x01000000)
+#define C1_TOUNIT_DIS       (0x000f0000)
+#define C1_TOUNIT_MAX       (0x000e0000)
+#define C1_CLK_GENSEL       (0x00000020)
+#define C1_CLK_EN           (0x00000004)
+#define C1_CLK_STABLE       (0x00000002)
+#define C1_CLK_INTLEN       (0x00000001)
+
+#define FREQ_SETUP          (400000)    // 400 Khz
+#define FREQ_NORMAL         (25000000)  // 25 Mhz
+
+// SLOTISR_VER values
+#define HOST_SPEC_NUM       0x00ff0000
+#define HOST_SPEC_NUM_SHIFT 16
+#define HOST_SPEC_V3        2
+#define HOST_SPEC_V2        1
+#define HOST_SPEC_V1        0
+
+// STATUS register settings
+#define SR_DAT_LEVEL1       (0x1e000000)
+#define SR_CMD_LEVEL        (0x01000000)
+#define SR_DAT_LEVEL0       (0x00f00000)
+#define SR_DAT3             (0x00800000)
+#define SR_DAT2             (0x00400000)
+#define SR_DAT1             (0x00200000)
+#define SR_DAT0             (0x00100000)
+#define SR_WRITE_PROT       (0x00080000)  // From SDHC spec v2, BCM says reserved
+#define SR_READ_AVAILABLE   (0x00000800)  // ???? undocumented
+#define SR_WRITE_AVAILABLE  (0x00000400)  // ???? undocumented
+#define SR_READ_TRANSFER    (0x00000200)
+#define SR_WRITE_TRANSFER   (0x00000100)
+#define SR_DAT_ACTIVE       (0x00000004)
+#define SR_DAT_INHIBIT      (0x00000002)
+#define SR_CMD_INHIBIT      (0x00000001)
+
+#define CONFIG_MMC_USE_DMA
+#define DMA_ALIGN                   (32U)
+
+#define SD_CMD_INDEX(a)             ((a) << 24)
+#define SD_CMD_RESERVED(a)          (0xffffffff)
+#define SD_CMD_INDEX(a)             ((a) << 24)
+#define SD_CMD_TYPE_NORMAL          (0x0)
+#define SD_CMD_TYPE_SUSPEND         (1 << 22)
+#define SD_CMD_TYPE_RESUME          (2 << 22)
+#define SD_CMD_TYPE_ABORT           (3 << 22)
+#define SD_CMD_TYPE_MASK            (3 << 22)
+#define SD_CMD_ISDATA               (1 << 21)
+#define SD_CMD_IXCHK_EN             (1 << 20)
+#define SD_CMD_CRCCHK_EN            (1 << 19)
+#define SD_CMD_RSPNS_TYPE_NONE      (0)         // For no response
+#define SD_CMD_RSPNS_TYPE_136       (1 << 16)   // For response R2 (with CRC), R3,4 (no CRC)
+#define SD_CMD_RSPNS_TYPE_48        (2 << 16)   // For responses R1, R5, R6, R7 (with CRC)
+#define SD_CMD_RSPNS_TYPE_48B       (3 << 16)   // For responses R1b, R5b (with CRC)
+#define SD_CMD_RSPNS_TYPE_MASK      (3 << 16)
+#define SD_CMD_MULTI_BLOCK          (1 << 5)
+#define SD_CMD_DAT_DIR_HC           (0)
+#define SD_CMD_DAT_DIR_CH           (1 << 4)
+#define SD_CMD_AUTO_CMD_EN_NONE     (0)
+#define SD_CMD_AUTO_CMD_EN_CMD12    (1 << 2)
+#define SD_CMD_AUTO_CMD_EN_CMD23    (2 << 2)
+#define SD_CMD_BLKCNT_EN            (1 << 1)
+#define SD_CMD_DMA                  (1)
+#define SD_RESP_NONE                SD_CMD_RSPNS_TYPE_NONE
+#define SD_RESP_R1                  (SD_CMD_RSPNS_TYPE_48)
+#define SD_RESP_R1b                 (SD_CMD_RSPNS_TYPE_48B)
+#define SD_RESP_R2                  (SD_CMD_RSPNS_TYPE_136)
+#define SD_RESP_R3                  SD_CMD_RSPNS_TYPE_48
+#define SD_RESP_R4                  SD_CMD_RSPNS_TYPE_136
+#define SD_RESP_R5                  (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R5b                 (SD_CMD_RSPNS_TYPE_48B | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R6                  (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN)
+#define SD_RESP_R7                  (SD_CMD_RSPNS_TYPE_48 | SD_CMD_CRCCHK_EN)
+#define SD_DATA_READ                (SD_CMD_ISDATA | SD_CMD_DAT_DIR_CH)
+#define SD_DATA_WRITE               (SD_CMD_ISDATA | SD_CMD_DAT_DIR_HC)
+#endif

bsp/raspberry-pi/raspi4-64/driver/drv_uart.c

@@ -22,6 +22,26 @@ struct hw_uart_device
     rt_uint32_t irqno;
 };
 
+#ifdef RT_USING_UART0
+static struct rt_serial_device _serial0;
+#endif
+
+#ifdef RT_USING_UART1
+static struct rt_serial_device _serial1;
+#endif
+
+#ifdef RT_USING_UART3
+static struct rt_serial_device _serial3;
+#endif
+
+#ifdef RT_USING_UART4
+static struct rt_serial_device _serial4;
+#endif
+
+#ifdef RT_USING_UART5
+static struct rt_serial_device _serial5;
+#endif
+
 static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     struct hw_uart_device *uart;
@@ -30,26 +50,54 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
 
     RT_ASSERT(serial != RT_NULL);
     uart = (struct hw_uart_device *)serial->parent.user_data;
-    if(uart->hw_base == PL011_BASE)
+
+    if(uart->hw_base == AUX_BASE)
     {
-        uint32_t gpfsel = 0;
-
-        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
-        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-
-        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
-        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-
-        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
-        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
-        PL011_REG_IBRD(uart->hw_base) = ibrd;
-        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
-        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
-        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+        prev_raspi_pin_mode(GPIO_PIN_14, ALT5);
+        prev_raspi_pin_mode(GPIO_PIN_15, ALT5);
+
+        AUX_ENABLES(uart->hw_base)      = 1;    /* Enable UART1 */
+        AUX_MU_IER_REG(uart->hw_base)   = 0;    /* Disable interrupt */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 0;    /* Disable Transmitter and Receiver */
+        AUX_MU_LCR_REG(uart->hw_base)   = 3;    /* Works in 8-bit mode */
+        AUX_MU_MCR_REG(uart->hw_base)   = 0;    /* Disable RTS */
+        AUX_MU_IIR_REG(uart->hw_base)   = 0xC6; /* Enable FIFO, Clear FIFO */
+        AUX_MU_BAUD_REG(uart->hw_base)  = 270;  /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
+        AUX_MU_CNTL_REG(uart->hw_base)  = 3;    /* Enable Transmitter and Receiver */
+        return RT_EOK;
     }
 
+    if(uart->hw_base == UART0_BASE)
+    {
+        prev_raspi_pin_mode(GPIO_PIN_14, ALT0);
+        prev_raspi_pin_mode(GPIO_PIN_15, ALT0);
+    }
+
+    if(uart->hw_base == UART3_BASE)
+    {
+        prev_raspi_pin_mode(GPIO_PIN_4, ALT4);
+        prev_raspi_pin_mode(GPIO_PIN_5, ALT4);
+    }
+
+    if(uart->hw_base == UART4_BASE)
+    {
+        prev_raspi_pin_mode(GPIO_PIN_8, ALT4);
+        prev_raspi_pin_mode(GPIO_PIN_9, ALT4);
+    }
+
+    if(uart->hw_base == UART5_BASE)
+    {
+        prev_raspi_pin_mode(GPIO_PIN_12, ALT4);
+        prev_raspi_pin_mode(GPIO_PIN_13, ALT4);
+    }
+
+    PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
+    PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+    PL011_REG_IBRD(uart->hw_base) = ibrd;
+    PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
+    PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
+    PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+
     return RT_EOK;
 }
 
@@ -70,7 +118,14 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
 
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        if(uart->hw_base == AUX_BASE)
+        {
+            AUX_MU_IER_REG(uart->hw_base) = 0x1;
+        }
+        else
+        {
+            PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        }
         rt_hw_interrupt_umask(uart->irqno);
         break;
     }
@@ -85,8 +140,16 @@ static int uart_putc(struct rt_serial_device *serial, char c)
     RT_ASSERT(serial != RT_NULL);
     uart = (struct hw_uart_device *)serial->parent.user_data;
 
-    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
-    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+    if(uart->hw_base == AUX_BASE)
+    {
+        while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
+        AUX_MU_IO_REG(uart->hw_base) = c;
+    }
+    else
+    {
+        while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
+        PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+    }
 
     return 1;
 }
@@ -99,9 +162,19 @@ static int uart_getc(struct rt_serial_device *serial)
     RT_ASSERT(serial != RT_NULL);
     uart = (struct hw_uart_device *)serial->parent.user_data;
 
-    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+    if(uart->hw_base == AUX_BASE)
+    {
+        if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
+        {
+            ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
+        }
+    }
+    else
     {
-        ch = PL011_REG_DR(uart->hw_base) & 0xff;
+        if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+        {
+            ch = PL011_REG_DR(uart->hw_base) & 0xff;
+        }
     }
 
     return ch;
@@ -115,38 +188,180 @@ static const struct rt_uart_ops _uart_ops =
     uart_getc,
 };
 
-static void rt_hw_uart_isr(int irqno, void *param)
+#ifdef RT_USING_UART1
+static void rt_hw_aux_uart_isr(int irqno, void *param)
 {
     struct rt_serial_device *serial = (struct rt_serial_device*)param;
     rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
 }
+#endif
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+#ifdef RT_USING_UART0
+    if((PACTL_CS & IRQ_UART0) == IRQ_UART0)
+    {
+        PACTL_CS &=  ~(IRQ_UART0);
+        rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND);
+        PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+    }
+#endif
+
+#ifdef RT_USING_UART3
+    if((PACTL_CS & IRQ_UART3) == IRQ_UART3)
+    {
+        PACTL_CS &=  ~(IRQ_UART3);
+        rt_hw_serial_isr(&_serial3, RT_SERIAL_EVENT_RX_IND);
+        PL011_REG_ICR(uart3_addr) = PL011_INTERRUPT_RECEIVE;
+    }
+#endif
+
+#ifdef RT_USING_UART4
+    if((PACTL_CS & IRQ_UART4) == IRQ_UART4)
+    {
+        PACTL_CS &=  ~(IRQ_UART4);
+        rt_hw_serial_isr(&_serial4, RT_SERIAL_EVENT_RX_IND);
+        PL011_REG_ICR(uart4_addr) = PL011_INTERRUPT_RECEIVE;
+    }
+#endif
 
+#ifdef RT_USING_UART5
+    if((PACTL_CS & IRQ_UART5) == IRQ_UART5)
+    {
+        PACTL_CS &=  ~(IRQ_UART5);
+        rt_hw_serial_isr(&_serial5, RT_SERIAL_EVENT_RX_IND);
+        PL011_REG_ICR(uart5_addr) = PL011_INTERRUPT_RECEIVE;
+    }
+#endif
+}
 
+#ifdef RT_USING_UART0
 /* UART device driver structure */
 static struct hw_uart_device _uart0_device =
 {
-    PL011_BASE,
+    UART0_BASE,
     IRQ_PL011,
 };
+#endif
+
+#ifdef RT_USING_UART1
+/* UART device driver structure */
+static struct hw_uart_device _uart1_device =
+{
+    AUX_BASE,
+    IRQ_AUX_UART,
+};
+#endif
+
+#ifdef RT_USING_UART3
+static struct hw_uart_device _uart3_device =
+{
+    UART3_BASE,
+    IRQ_PL011,
+};
+#endif
+
+#ifdef RT_USING_UART4
+static struct hw_uart_device _uart4_device =
+{
+    UART4_BASE,
+    IRQ_PL011,
+};
+#endif
+
+#ifdef RT_USING_UART5
+static struct hw_uart_device _uart5_device =
+{
+    UART5_BASE,
+    IRQ_PL011,
+};
+#endif
 
 static struct rt_serial_device _serial0;
 
 int rt_hw_uart_init(void)
 {
-    struct hw_uart_device *uart;
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-    uart = &_uart0_device;
+#ifdef RT_USING_UART0
+    struct hw_uart_device *uart0;
+    uart0 = &_uart0_device;
 
     _serial0.ops    = &_uart_ops;
     _serial0.config = config;
 
+    uart0->hw_base = UART0_BASE;
+
+
+    /* register UART0 device */
+    rt_hw_serial_register(&_serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart0);
+    rt_hw_interrupt_install(uart0->irqno, rt_hw_uart_isr, &_serial0, "uart0");
+
+#endif
+
+#ifdef RT_USING_UART1
+    struct hw_uart_device *uart1;
+    uart1 = &_uart1_device;
+
+    _serial1.ops    = &_uart_ops;
+    _serial1.config = config;
+
+    uart1->hw_base = AUX_BASE;
+
     /* register UART1 device */
-    rt_hw_serial_register(&_serial0, "uart",
+    rt_hw_serial_register(&_serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart1);
+    rt_hw_interrupt_install(uart1->irqno, rt_hw_aux_uart_isr, &_serial1, "uart1");
+#endif
+
+#ifdef RT_USING_UART3
+    struct hw_uart_device *uart3;
+    uart3 = &_uart3_device;
+
+    _serial3.ops    = &_uart_ops;
+    _serial3.config = config;
+
+    uart3_addr = UART3_BASE;
+
+    /* register UART3 device */
+    rt_hw_serial_register(&_serial3, "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart3);
+    rt_hw_interrupt_install(uart3->irqno, rt_hw_uart_isr, &_serial3, "uart3");
+#endif
+
+#ifdef RT_USING_UART4
+    struct hw_uart_device *uart4;
+    uart4 = &_uart4_device;
+
+    _serial4.ops    = &_uart_ops;
+    _serial4.config = config;
+
+    uart4_addr = UART4_BASE;
+
+    /* register UART4 device */
+    rt_hw_serial_register(&_serial4, "uart4",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
+                          uart4);
+    rt_hw_interrupt_install(uart4->irqno, rt_hw_uart_isr, &_serial4, "uart4");
+#endif
+
+#ifdef RT_USING_UART5
+    struct hw_uart_device *uart5;
+    uart5 = &_uart5_device;
+
+    _serial5.ops    = &_uart_ops;
+    _serial5.config = config;
 
+    uart5_addr = UART5_BASE;
+
+    /* register UART5 device */
+    rt_hw_serial_register(&_serial5, "uart5",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart5);
+    rt_hw_interrupt_install(uart5->irqno, rt_hw_uart_isr, &_serial5, "uart5");
+#endif
     return 0;
 }

bsp/raspberry-pi/raspi4-64/driver/drv_uart.h

@@ -78,6 +78,30 @@
 #define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
 #define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
 
+/*
+ *  Auxiliary
+ */
+#define AUX_IRQ(BASE)                   HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
+#define AUX_ENABLES(BASE)               HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
+#define AUX_MU_IO_REG(BASE)             HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
+#define AUX_MU_IER_REG(BASE)            HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
+#define AUX_MU_IIR_REG(BASE)            HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
+#define AUX_MU_LCR_REG(BASE)            HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
+#define AUX_MU_MCR_REG(BASE)            HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
+#define AUX_MU_LSR_REG(BASE)            HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
+#define AUX_MU_MSR_REG(BASE)            HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
+#define AUX_MU_SCRATCH(BASE)            HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
+#define AUX_MU_CNTL_REG(BASE)           HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
+#define AUX_MU_STAT_REG(BASE)           HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
+#define AUX_MU_BAUD_REG(BASE)           HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
+#define AUX_SPI0_CNTL0_REG(BASE)        HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
+#define AUX_SPI0_CNTL1_REG(BASE)        HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
+#define AUX_SPI0_STAT_REG(BASE)         HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
+#define AUX_SPI0_IO_REG(BASE)           HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
+#define AUX_SPI0_PEEK_REG(BASE)         HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
+#define AUX_SPI1_CNTL0_REG(BASE)        HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
+#define AUX_SPI1_CNTL1_REG(BASE)        HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
+
 int rt_hw_uart_init(void);
 
 #endif /* DRV_UART_H__ */

bsp/raspberry-pi/raspi4-64/driver/mbox.c

@@ -0,0 +1,519 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2019-08-29     zdzn           first version
+ * 2020-09-10     bigmagic       add other mbox option
+ */
+
+/* mailbox message buffer */
+#include "mbox.h"
+#include "mmu.h"
+
+volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
+#define BUS_ADDRESS(phys)   (((phys) & ~0xC0000000)  |  0xC0000000)
+
+/**
+ * Make a mailbox call. Returns 0 on failure, non-zero on success
+ */
+int mbox_call(unsigned char ch, int mmu_enable)
+{
+    unsigned int r = (((MBOX_ADDR) & ~0xF) | (ch & 0xF));
+    if (mmu_enable)
+    {
+        r = BUS_ADDRESS(r);
+    }
+    /* wait until we can write to the mailbox */
+    do
+    {
+        __asm__ volatile ("nop");
+    }
+    while (*MBOX_STATUS & MBOX_FULL);
+    /* write the address of our message to the mailbox with channel identifier */
+    *MBOX_WRITE = r;
+    /* now wait for the response */
+    while (1)
+    {
+        /* is there a response? */
+        do
+        {
+            __asm__ volatile ("nop");
+        }
+        while (*MBOX_STATUS & MBOX_EMPTY);
+        /* is it a response to our message? */
+        if (r == *MBOX_READ)
+        {
+            /* is it a valid successful response? */
+            return mbox[1] == MBOX_RESPONSE;
+        }
+    }
+    return 0;
+}
+
+int bcm271x_mbox_get_touch(void)
+{
+    mbox[0] = 8 * 4;                    // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+
+    mbox[2] = MBOX_TAG_GET_TOUCHBUF;
+    mbox[3] = 4;                        // buffer size
+    mbox[4] = 0;                        // len
+
+    mbox[5] = 0;                       // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    return (int)(mbox[5] &  ~0xC0000000);
+}
+
+int bcm271x_notify_reboot(void)
+{
+    mbox[0] = 7 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+    mbox[2] = MBOX_TAG_NOTIFY_REBOOT;       // (the tag id)
+    mbox[3] = 0x00000004;                   // length + 4
+    mbox[4] = 0x00000000;                   // size of the data
+    mbox[5] = 0x00000000;                   // request
+
+    mbox[6] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+    return 0;
+}
+
+int bcm271x_notify_xhci_reset(void)
+{
+    mbox[0] = 7 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+    mbox[2] = MBOX_TAG_NOTIFY_XHCI_RESET;   // (the tag id)
+    mbox[3] = 0x00000004;                   // length + 4
+    mbox[4] = 0x00000004;                   // size of the data
+    mbox[5] = 0x00100000;                   // request
+    mbox[6] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+    return 0;
+}
+
+int bcm271x_gpu_enable(void)
+{
+    mbox[0] = 12 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                  // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_SET_RATE;
+    mbox[3] = 0x00000008;                   // (the tag id)
+    mbox[4] = 0x00000008;                   // (the tag id)
+    mbox[5] = 5;                            // V3D
+    mbox[6] = 250 * 1000 * 1000;
+    mbox[7] = MBOX_TAG_ENABLE_QPU;                   // (the tag id)
+    mbox[8] = 0x00000004;                   // (size of the buffer)
+    mbox[9] = 0x00000004;                   // (size of the data)
+    mbox[10] = 0x00000001;
+    mbox[11] = MBOX_TAG_LAST;               // end tag
+    mbox_call(8, MMU_DISABLE);
+    return mbox[1];
+}
+
+int bcm271x_mbox_hardware_get_model(void)
+{
+    mbox[0] = 8 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL;
+    mbox[3] = 4;                            // buffer size
+    mbox[4] = 0;                            // len
+
+    mbox[5] = 0;
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    return mbox[5];
+}
+
+int bcm271x_mbox_hardware_get_revison(void)
+{
+    mbox[0] = 8 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_REV;
+    mbox[3] = 4;                            // buffer size
+    mbox[4] = 0;                            // len
+
+    mbox[5] = 0;
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    return mbox[5];
+}
+
+int bcm271x_mbox_hardware_get_mac_address(uint8_t *mac)
+{
+    mbox[0] = 8 * 4;                               // length of the message
+    mbox[1] = MBOX_REQUEST;                        // this is a request message
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS;
+    mbox[3] = 6;                                   // buffer size
+    mbox[4] = 0;                                   // len
+
+    mbox[5] = 0;
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    char *mac_str = (char *)&mbox[5];
+    mac[0] = mac_str[0];
+    mac[1] = mac_str[1];
+    mac[2] = mac_str[2];
+    mac[3] = mac_str[3];
+    mac[4] = mac_str[4];
+    mac[5] = mac_str[5];
+    return 0;
+}
+
+
+int bcm271x_mbox_hardware_get_serial(rt_uint64_t *sn)
+{
+    mbox[0] = 8 * 4;                            // length of the message
+    mbox[1] = MBOX_REQUEST;                     // this is a request message
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL;
+    mbox[3] = 8;                                // buffer size
+    mbox[4] = 0;                                // len
+
+    mbox[5] = 0;
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    sn = (rt_uint64_t *)&mbox[5];
+
+    return 0;
+}
+
+int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t *base, rt_uint32_t *size)
+{
+    mbox[0] = 8 * 4;                                // length of the message
+    mbox[1] = MBOX_REQUEST;                         // this is a request message
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY;
+    mbox[3] = 8;                                    // buffer size
+    mbox[4] = 0;                                    // len
+
+    mbox[5] = 0;
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    *base = mbox[5];
+    *size = mbox[6];
+
+    return 0;
+
+}
+
+int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t *base, rt_uint32_t *size)
+{
+    mbox[0] = 8 * 4;                             // length of the message
+    mbox[1] = MBOX_REQUEST;                      // this is a request message
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY;
+    mbox[3] = 8;                                 // buffer size
+    mbox[4] = 0;                                 // len
+
+    mbox[5] = 0;
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    *base = mbox[5];
+    *size = mbox[6];
+
+    return 0;
+}
+
+int bcm271x_mbox_clock_get_turbo(void)
+{
+    mbox[0] = 8 * 4;                    // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_TURBO;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 4;                        // len
+
+    mbox[5] = 0;                        // id
+    mbox[6] = 0;                        // val
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_clock_set_turbo(int level)
+{
+    mbox[0] = 8 * 4;                    // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_SET_TURBO;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = 0;                        // id
+    mbox[6] = level ? 1 : 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_clock_get_state(int id)
+{
+    mbox[0] = 8 * 4;                     // length of the message
+    mbox[1] = MBOX_REQUEST;              // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_STATE;
+    mbox[3] = 8;                         // buffer size
+    mbox[4] = 4;                         // len
+
+    mbox[5] = id;                        // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm271x_mbox_clock_set_state(int id, int state)
+{
+    mbox[0] = 8 * 4;                    // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_SET_STATE;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = id;                       // id
+    mbox[6] = state & 0x3;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm271x_mbox_clock_get_rate(int id)
+{
+    mbox[0] = 8 * 4;                    // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_RATE;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 4;                        // len
+
+    mbox[5] = id;                       // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_clock_set_rate(int id, int rate)
+{
+    mbox[0] = 8 * 4;                    // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_SET_RATE;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = id;                       // id
+    mbox[6] = rate;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_clock_get_max_rate(int id)
+{
+    mbox[0] = 8 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE;
+    mbox[3] = 8;                            // buffer size
+    mbox[4] = 4;                            // len
+
+    mbox[5] = id;                           // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_clock_get_min_rate(int id)
+{
+    mbox[0] = 8 * 4;                        // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE;
+    mbox[3] = 8;                            // buffer size
+    mbox[4] = 4;                            // len
+
+    mbox[5] = id;                           // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_power_get_state(int id)
+{
+    mbox[0] = 8 * 4;                // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+
+    mbox[2] = MBOX_TAG_POWER_GET_STATE;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 4;                    // len
+
+    mbox[5] = id;                   // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm271x_mbox_power_set_state(int id, int state)
+{
+    mbox[0] = 8 * 4;                // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+
+    mbox[2] = MBOX_TAG_POWER_SET_STATE;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 8;                    // len
+
+    mbox[5] = id;                    // id
+    mbox[6] = state & 0x3;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm271x_mbox_temp_get(void)
+{
+    mbox[0] = 8 * 4;                // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+
+    mbox[2] = MBOX_TAG_TEMP_GET;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 4;                    // len
+
+    mbox[5] = 0;                    //id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm271x_mbox_temp_get_max(void)
+{
+    mbox[0] = 8 * 4;                // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+
+    mbox[2] = MBOX_TAG_TEMP_GET_MAX;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 4;                    // len
+
+    mbox[5] = 0;                    // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if (mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}

bsp/raspberry-pi/raspi4-64/driver/mbox.h

@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-09-10     bigmagic       first version
+ */
+
+#ifndef __MBOX_H__
+#define __MBOX_H__
+
+#include <rtthread.h>
+#include <stdint.h>
+
+// https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
+// https://github.com/hermanhermitage/videocoreiv
+
+/* a properly aligned buffer */
+extern volatile unsigned int *mbox;
+
+#define MBOX_REQUEST            0
+
+/* channels */
+#define MBOX_CH_POWER           0
+#define MBOX_CH_FB              1
+#define MBOX_CH_VUART           2
+#define MBOX_CH_VCHIQ           3
+#define MBOX_CH_LEDS            4
+#define MBOX_CH_BTNS            5
+#define MBOX_CH_TOUCH           6
+#define MBOX_CH_COUNT           7
+#define MBOX_CH_PROP            8
+
+/* tags */
+#define MBOX_TAG_SETPOWER       0x28001
+#define MBOX_TAG_SETCLKRATE     0x38002
+#define MBOX_GET_MAC_ADDRESS    0x10003
+#define MBOX_TAG_LAST           0
+
+#define MMIO_BASE               0xFE000000
+#define VIDEOCORE_MBOX          (MMIO_BASE+0x0000B880)
+#define MBOX_READ               ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
+#define MBOX_POLL               ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
+#define MBOX_SENDER             ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
+#define MBOX_STATUS             ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
+#define MBOX_CONFIG             ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
+#define MBOX_WRITE              ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
+#define MBOX_RESPONSE           0x80000000
+#define MBOX_FULL               0x80000000
+#define MBOX_EMPTY              0x40000000
+
+#define DEVICE_ID_SD_CARD       (0)
+#define DEVICE_ID_USB_HCD       (3)
+#define POWER_STATE_OFF         (0 << 0)
+#define POWER_STATE_ON          (1 << 0)
+#define POWER_STATE_WAIT        (1 << 1)
+#define POWER_STATE_NO_DEVICE   (1 << 1)    // in response
+#define MMU_ENABLE              (1)
+#define MMU_DISABLE             (0)
+
+/*
+ * raspi hardware info
+ */
+enum
+{
+    MBOX_TAG_HARDWARE_GET_MODEL         = 0x00010001,
+    MBOX_TAG_HARDWARE_GET_REV           = 0x00010002,
+    MBOX_TAG_HARDWARE_GET_MAC_ADDRESS   = 0x00010003,
+    MBOX_TAG_HARDWARE_GET_SERIAL        = 0x00010004,
+    MBOX_TAG_HARDWARE_GET_ARM_MEMORY    = 0x00010005,
+    MBOX_TAG_HARDWARE_GET_VC_MEMORY     = 0x00010006,
+    MBOX_TAG_HARDWARE_GET_CLOCKS        = 0x00010007,
+};
+
+/*
+ * raspi clock
+ */
+enum
+{
+    MBOX_TAG_CLOCK_GET_TURBO    = 0x00030009,
+    MBOX_TAG_CLOCK_SET_TURBO    = 0x00038009,
+    MBOX_TAG_CLOCK_GET_STATE    = 0x00030001,
+    MBOX_TAG_CLOCK_SET_STATE    = 0x00038001,
+    MBOX_TAG_CLOCK_GET_RATE     = 0x00030002,
+    MBOX_TAG_CLOCK_SET_RATE     = 0x00038002,
+    MBOX_TAG_CLOCK_GET_MAX_RATE = 0x00030004,
+    MBOX_TAG_CLOCK_GET_MIN_RATE = 0x00030007,
+};
+
+/*
+ * raspi power
+ */
+enum
+{
+    MBOX_TAG_POWER_GET_STATE    = 0x00020001,
+    MBOX_TAG_POWER_SET_STATE    = 0x00028001,
+};
+
+/*
+ * raspi temperature
+ */
+enum
+{
+    MBOX_TAG_TEMP_GET       = 0x00030006,
+    MBOX_TAG_TEMP_GET_MAX   = 0x0003000A,
+};
+
+/*
+ * raspi Memory
+ */
+enum
+{
+    MBOX_TAG_ALLOCATE_MEMORY = 0x0003000C,  // Memory: Allocates Contiguous Memory On The GPU (Response: Handle)
+    MBOX_TAG_LOCK_MEMORY     = 0x0003000D,  // Memory: Unlock Buffer (Response: Status)
+    MBOX_TAG_UNLOCK_MEMORY   = 0x0003000E,  // Memory: Unlock Buffer (Response: Status)
+    MBOX_TAG_RELEASE_MEMORY  = 0x0003000F,  // Memory: Free The Memory Buffer (Response: Status)
+    MBOX_TAG_EXECUTE_CODE    = 0x00030010,  // Memory: Calls The Function At Given (Bus) Address And With Arguments Given
+};
+
+/*
+ * raspi GPU
+ */
+enum
+{
+    MBOX_TAG_EXECUTE_QPU = 0x00030011,      // QPU: Calls The QPU Function At Given (Bus) Address And With Arguments Given
+    //      (Response: Number Of QPUs, Control, No Flush, Timeout In ms)
+    MBOX_TAG_ENABLE_QPU  = 0x00030012,      // QPU: Enables The QPU (Response: Enable State)
+};
+
+/*
+ * raspi HDMI
+ */
+#define MBOX_TAG_GET_EDID_BLOCK        0x00030020   // HDMI: Read Specificed EDID Block From Attached HDMI/DVI Device
+//      (Response: Block Number, Status, EDID Block (128 Bytes))
+
+/*
+ * raspi NOTIFY
+ */
+#define MBOX_TAG_NOTIFY_REBOOT         0x00030048
+#define MBOX_TAG_NOTIFY_XHCI_RESET     0x00030058
+
+/*
+* touch
+*/
+#define MBOX_TAG_GET_TOUCHBUF          (0x0004000F)
+
+#define MBOX_ADDR 0x08000000
+
+#define RES_CLK_ID                      (0x000000000)
+#define EMMC_CLK_ID                     (0x000000001)
+#define UART_CLK_ID                     (0x000000002)
+#define ARM_CLK_ID                      (0x000000003)
+#define CORE_CLK_ID                     (0x000000004)
+#define V3D_CLK_ID                      (0x000000005)
+#define H264_CLK_ID                     (0x000000006)
+#define ISP_CLK_ID                      (0x000000007)
+#define SDRAM_CLK_ID                    (0x000000008)
+#define PIXEL_CLK_ID                    (0x000000009)
+#define PWM_CLK_ID                      (0x00000000a)
+
+int mbox_call(unsigned char ch, int mmu_enable);
+int bcm271x_mbox_get_touch(void);
+int bcm271x_notify_reboot(void);
+int bcm271x_notify_xhci_reset(void);
+int bcm271x_gpu_enable(void);
+int bcm271x_mbox_hardware_get_model(void);
+int bcm271x_mbox_hardware_get_revison(void);
+int bcm271x_mbox_hardware_get_mac_address(uint8_t *mac);
+int bcm271x_mbox_hardware_get_serial(rt_uint64_t *sn);
+int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t *base, rt_uint32_t *size);
+int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t *base, rt_uint32_t *size);
+int bcm271x_mbox_clock_get_turbo(void);
+int bcm271x_mbox_clock_set_turbo(int level);
+int bcm271x_mbox_clock_get_state(int id);
+int bcm271x_mbox_clock_set_state(int id, int state);
+int bcm271x_mbox_clock_get_rate(int id);
+int bcm271x_mbox_clock_set_rate(int id, int rate);
+int bcm271x_mbox_clock_get_max_rate(int id);
+int bcm271x_mbox_clock_get_min_rate(int id);
+int bcm271x_mbox_power_get_state(int id);
+int bcm271x_mbox_power_set_state(int id, int state);
+int bcm271x_mbox_temp_get(void);
+int bcm271x_mbox_temp_get_max(void);
+
+#endif

bsp/raspberry-pi/raspi4-64/driver/raspi4.h

@@ -1,29 +1,145 @@
 #ifndef __RASPI4_H__
 #define __RASPI4_H__
 
+#include <rthw.h>
+
+#define __REG32(x)              (*((volatile unsigned int *)(x)))
+
+//base address
+#define PER_BASE                (0xFE000000)
+
+//gpio offset
+#define GPIO_BASE_OFFSET        (0x00200000)
+
+//pl011 offset
+#define PL011_UART_BASE_OFFSET  (0x00201000)
+
+//pactl cs offset
+#define PACTL_CS_OFFSET         (0x00204E00)
+
+//aux offset
+#define AUX_BASE_OFFSET         (0x00215000)
+
 //gpio
-#define GPIO_BASE (0xFE000000 + 0x00200000)
+#define GPIO_BASE               (PER_BASE + GPIO_BASE_OFFSET)
+#define GPIO_IRQ_NUM            (3)         //40 pin mode
+#define IRQ_GPIO0               (96 + 49)   //bank0 (0 to 27)
+#define IRQ_GPIO1               (96 + 50)   //bank1 (28 to 45)
+#define IRQ_GPIO2               (96 + 51)   //bank2 (46 to 57)
+#define IRQ_GPIO3               (96 + 52)   //bank3
+
+//system timer
+#define ARM_TIMER_IRQ           (64)
+#define ARM_TIMER_BASE          (PER_BASE + 0xB000)
+#define ARM_TIMER_LOAD          HWREG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE         HWREG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL          HWREG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR        HWREG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ        HWREG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ       HWREG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD        HWREG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV        HWREG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR          HWREG32(ARM_TIMER_BASE + 0x420)
 
 //uart
-#define UART0_BASE                  (0xFE000000 + 0x00201000)
-#define PL011_BASE                  UART0_BASE
-#define IRQ_PL011                   (121 + 32)
-#define UART_REFERENCE_CLOCK        (48000000)
+#define UART_BASE               (PER_BASE + PL011_UART_BASE_OFFSET)
+#define UART0_BASE              (UART_BASE + 0x0)
+#define UART2_BASE              (UART_BASE + 0x400)
+#define UART3_BASE              (UART_BASE + 0x600)
+#define UART4_BASE              (UART_BASE + 0x800)
+#define UART5_BASE              (UART_BASE + 0xA00)
+#define IRQ_AUX_UART            (96 + 29)
+#define UART_REFERENCE_CLOCK    (48000000)
+
+//aux
+#define AUX_BASE                (PER_BASE + AUX_BASE_OFFSET)
+#define IRQ_PL011               (96 + 57)
+
+//pactl cs
+#define PACTL_CS_ADDR           (PER_BASE + PACTL_CS_OFFSET)
+#define PACTL_CS                HWREG32(PACTL_CS_ADDR)
+typedef enum
+{
+    IRQ_SPI0 = 0x00000000,
+    IRQ_SPI1 = 0x00000002,
+    IRQ_SPI2 = 0x00000004,
+    IRQ_SPI3 = 0x00000008,
+    IRQ_SPI4 = 0x00000010,
+    IRQ_SPI5 = 0x00000020,
+    IRQ_SPI6 = 0x00000040,
+    IRQ_I2C0 = 0x00000100,
+    IRQ_I2C1 = 0x00000200,
+    IRQ_I2C2 = 0x00000400,
+    IRQ_I2C3 = 0x00000800,
+    IRQ_I2C4 = 0x00001000,
+    IRQ_I2C5 = 0x00002000,
+    IRQ_I2C6 = 0x00004000,
+    IRQ_I2C7 = 0x00008000,
+    IRQ_UART5 = 0x00010000,
+    IRQ_UART4 = 0x00020000,
+    IRQ_UART3 = 0x00040000,
+    IRQ_UART2 = 0x00080000,
+    IRQ_UART0 = 0x00100000
+} PACTL_CS_VAL;
 
 // 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
 #define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
 #define TIMER_IRQ               30
 #define NON_SECURE_TIMER_IRQ    (1 << 1)
 
+//core timer
+#define ST_BASE_OFFSET          (0x003000)
+#define STIMER_BASE             (PER_BASE  + ST_BASE_OFFSET)
+#define STIMER_CS               HWREG32(STIMER_BASE + 0x0000)
+#define STIMER_CLO              HWREG32(STIMER_BASE + 0x0004)
+#define STIMER_CHI              HWREG32(STIMER_BASE + 0x0008)
+#define STIMER_C0               HWREG32(STIMER_BASE + 0x000C)
+#define STIMER_C1               HWREG32(STIMER_BASE + 0x0010)
+#define STIMER_C2               HWREG32(STIMER_BASE + 0x0014)
+#define STIMER_C3               HWREG32(STIMER_BASE + 0x0018)
+
+#define DELAY_MICROS(micros) \
+do { \
+    rt_uint32_t compare = STIMER_CLO + micros * 25; \
+    while (STIMER_CLO < compare); \
+} while (0) \
+
+//mmc
+#define MMC0_BASE_ADDR          (PER_BASE + 0x300000)
+#define MMC2_BASE_ADDR          (PER_BASE + 0x340000)
+
+//eth
+#define MAC_REG_BASE_ADDR       (void *)(0xfd580000)
+#define ETH_IRQ                 (160 + 29)
+#define SEND_DATA_NO_CACHE      (0x08200000)
+#define RECV_DATA_NO_CACHE      (0x08400000)
+
 //gic max
+#define MAX_HANDLERS                (256)
 #define ARM_GIC_NR_IRQS             (512)
 #define INTC_BASE                   (0xff800000)
+#define ARM_GIC_MAX_NR              (512)
+#define GIC_V2_BASE                 (INTC_BASE + 0x00040000)
 #define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
 #define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
 #define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
 #define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
 
+#define GIC_IRQ_START               0
+#define GIC_ACK_INTID_MASK          0x000003ff
+
 #define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
 #define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
 
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return GIC_PL400_DISTRIBUTOR_PPTR;
+}
+
+rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
+{
+    return GIC_PL400_CONTROLLER_PPTR;
+}
+
 #endif

bsp/raspberry-pi/raspi4-64/rtconfig.h

@@ -19,6 +19,9 @@
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 2048
+
+/* kservice optimization */
+
 #define RT_DEBUG
 
 /* Inter-Thread communication */
@@ -40,8 +43,8 @@
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart"
-#define RT_VER_NUM 0x40003
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40004
 #define ARCH_CPU_64BIT
 #define ARCH_ARMV8
 
@@ -58,16 +61,17 @@
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -77,16 +81,42 @@
 #define DFS_FILESYSTEMS_MAX 2
 #define DFS_FILESYSTEM_TYPES_MAX 2
 #define DFS_FD_MAX 16
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
+#define RT_USING_RTC
+#define RT_USING_ALARM
+#define RT_USING_SDIO
+#define RT_SDIO_STACK_SIZE 512
+#define RT_SDIO_THREAD_PRIORITY 15
+#define RT_MMCSD_STACK_SIZE 2048
+#define RT_MMCSD_THREAD_PREORITY 22
+#define RT_MMCSD_MAX_PARTITION 16
 
 /* Using USB */
 
@@ -95,17 +125,73 @@
 
 #define RT_USING_LIBC
 #define RT_USING_POSIX
+#define RT_LIBC_DEFAULT_TIMEZONE 8
 
 /* Network */
 
 /* Socket abstraction layer */
 
+#define RT_USING_SAL
+#define SAL_INTERNET_CHECK
+
+/* protocol stack implement */
+
+#define SAL_USING_LWIP
+#define SAL_SOCKETS_NUM 16
 
 /* Network interface device */
 
+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0
 
 /* light weight TCP/IP stack */
 
+#define RT_USING_LWIP
+#define RT_USING_LWIP203
+#define RT_LWIP_MEM_ALIGNMENT 4
+#define RT_LWIP_IGMP
+#define RT_LWIP_ICMP
+#define RT_LWIP_DNS
+#define RT_LWIP_DHCP
+#define IP_SOF_BROADCAST 1
+#define IP_SOF_BROADCAST_RECV 1
+
+/* Static IPv4 Address */
+
+#define RT_LWIP_IPADDR "192.168.1.30"
+#define RT_LWIP_GWADDR "192.168.1.1"
+#define RT_LWIP_MSKADDR "255.255.255.0"
+#define RT_LWIP_UDP
+#define RT_LWIP_TCP
+#define RT_LWIP_RAW
+#define RT_MEMP_NUM_NETCONN 8
+#define RT_LWIP_PBUF_NUM 16
+#define RT_LWIP_RAW_PCB_NUM 4
+#define RT_LWIP_UDP_PCB_NUM 4
+#define RT_LWIP_TCP_PCB_NUM 4
+#define RT_LWIP_TCP_SEG_NUM 40
+#define RT_LWIP_TCP_SND_BUF 8196
+#define RT_LWIP_TCP_WND 8196
+#define RT_LWIP_TCPTHREAD_PRIORITY 10
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 2048
+#define RT_LWIP_ETHTHREAD_PRIORITY 12
+#define RT_LWIP_ETHTHREAD_STACKSIZE 2048
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#define LWIP_NETIF_LINK_CALLBACK 1
+#define SO_REUSE 1
+#define LWIP_SO_RCVTIMEO 1
+#define LWIP_SO_SNDTIMEO 1
+#define LWIP_SO_RCVBUF 1
+#define LWIP_SO_LINGER 0
+#define LWIP_NETIF_LOOPBACK 0
+#define RT_LWIP_USING_PING
 
 /* AT commands */
 
@@ -115,6 +201,11 @@
 
 /* Utilities */
 
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+
+/* RT-Thread Utestcases */
+
 
 /* RT-Thread online packages */
 
@@ -146,16 +237,27 @@
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
 
 /* peripheral libraries and drivers */
 
 
-/* miscellaneous packages */
+/* AI packages */
+
 
+/* miscellaneous packages */
 
 /* samples: kernel and components samples */
 
+
+/* entertainment: terminal games and other interesting software packages */
+
 #define BCM2711_SOC
+#define BSP_SUPPORT_FPU
 
 /* Hardware Drivers Config */
 
@@ -167,6 +269,11 @@
 #define BSP_USING_GIC400
 #define BSP_USING_PIN
 #define BSP_USING_CORETIMER
+#define BSP_USING_ETH
+#define BSP_USING_RTC
+#define BSP_USING_ALARM
+#define BSP_USING_SDIO
+#define BSP_USING_SDIO0
 
 /* Board Peripheral Drivers */
 

bsp/raspberry-pi/raspi4-64/rtconfig.py

@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH        ='aarch64'
-CPU         ='cortex-a72'
+CPU         ='cortex-a'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):

bsp/simulator/.config

@@ -21,6 +21,13 @@ CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
 CONFIG_RT_DEBUG=y
 CONFIG_RT_DEBUG_COLOR=y
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -65,7 +72,8 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="console"
-CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
 # CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
@@ -86,19 +94,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Command shell
 #
 CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
 CONFIG_FINSH_ARG_MAX=10
 
 #
@@ -143,6 +151,8 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
@@ -181,6 +191,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
 CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 
 #
 # Network
@@ -217,6 +228,12 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
 
 #
 # RT-Thread online packages
@@ -265,6 +282,7 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
 
 #
 # IoT Cloud
@@ -303,6 +321,10 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_RAPIDJSON is not set
 # CONFIG_PKG_USING_BSAL is not set
 # CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_HM is not set
 
 #
 # security packages
@@ -319,6 +341,7 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
 
 #
 # multimedia packages
@@ -328,9 +351,13 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
 # CONFIG_PKG_USING_HELIX is not set
 # CONFIG_PKG_USING_AZUREGUIX is not set
 # CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
 
 #
 # tools packages
@@ -339,6 +366,7 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
@@ -367,14 +395,36 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_ANV_MEMLEAK is not set
 # CONFIG_PKG_USING_ANV_TESTSUIT is not set
 # CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
 
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
 # CONFIG_PKG_USING_FLASHDB is not set
@@ -386,6 +436,7 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_LITTLEFS is not set
 # CONFIG_PKG_USING_DFS_JFFS2 is not set
 # CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
 # CONFIG_PKG_USING_EV is not set
@@ -395,25 +446,15 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_RAMDISK is not set
 # CONFIG_PKG_USING_MININI is not set
 # CONFIG_PKG_USING_QBOOT is not set
-
-#
-# Micrium: Micrium software products porting for RT-Thread
-#
-# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
-# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
-# CONFIG_PKG_USING_UC_CRC is not set
-# CONFIG_PKG_USING_UC_CLK is not set
-# CONFIG_PKG_USING_UC_COMMON is not set
-# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
-# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
-# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
-# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
-# CONFIG_PKG_USING_QFPLIB_M3 is not set
 # CONFIG_PKG_USING_LPM is not set
 # CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
 
 #
 # peripheral libraries and drivers
@@ -438,7 +479,6 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@@ -481,6 +521,13 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_LIBNFC is not set
 # CONFIG_PKG_USING_MFOC is not set
 # CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 
 #
 # AI packages
@@ -493,10 +540,32 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
 
 #
 # miscellaneous packages
 #
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
 # CONFIG_PKG_USING_LIBCSV is not set
 # CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
@@ -507,20 +576,13 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_UPACKER is not set
 # CONFIG_PKG_USING_UPARAM is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
@@ -528,19 +590,10 @@ CONFIG_RT_LIBC_USING_TIME=y
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
-
-#
-# entertainment: terminal games and other interesting software packages
-#
-# CONFIG_PKG_USING_THREES is not set
-# CONFIG_PKG_USING_2048 is not set
-# CONFIG_PKG_USING_SNAKE is not set
-# CONFIG_PKG_USING_TETRIS is not set
-# CONFIG_PKG_USING_DONUT is not set
-# CONFIG_PKG_USING_ACLOCK is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
 # CONFIG_PKG_USING_MCURSES is not set
 # CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
 CONFIG_SOC_SIMULATOR=y
 CONFIG_RT_USING_DFS_WINSHAREDIR=y

bsp/simulator/drivers/SConscript

@@ -7,6 +7,8 @@ LIBS = []
 LIBPATH = []
 CPPPATH = [cwd]
 
+CPPDEFINES = ['_CRT_DECLARE_NONSTDC_NAMES=0'] # avoid to conflict with the inherent STDC in VS
+
 # remove no need file.
 if GetDepend('PKG_USING_GUIENGINE') == False:
     SrcRemove(src, 'sdl_fb.c')
@@ -30,6 +32,6 @@ if sys.platform[0:5]=="linux": #check whether under linux
     SrcRemove(src, ['module_win32.c', 'dfs_win32.c'])
 
 group = DefineGroup('Drivers', src, depend = [''],
-                    CPPPATH = CPPPATH, LIBS=LIBS, LIBPATH=LIBPATH)
+                    CPPPATH = CPPPATH, LIBS=LIBS, LIBPATH=LIBPATH, CPPDEFINES = CPPDEFINES)
 
 Return('group')

bsp/simulator/drivers/dfs_win32.c

@@ -10,7 +10,6 @@
  * 2017-10-20     urey         support rt-thread 3.0
  */
 #include <rtthread.h>
-#include <rtlibc.h>
 
 #include <dfs_fs.h>
 #include <dfs_file.h>
@@ -24,22 +23,6 @@
 #include <WinError.h>
 #include <windows.h>
 
-#if defined(__MINGW32__) && defined(_NO_OLDNAMES)
-#define O_RDONLY    _O_RDONLY
-#define O_WRONLY    _O_WRONLY
-#define O_RDWR      _O_RDWR
-#define O_ACCMODE   _O_ACCMODE
-#define O_APPEND    _O_APPEND
-#define O_CREAT     _O_CREAT
-#define O_TRUNC     _O_TRUNC
-#define O_EXCL      _O_EXCL
-#define O_TEXT      _O_TEXT
-#define O_BINARY    _O_BINARY
-#define O_TEMPORARY _O_TEMPORARY
-#define O_NOINHERIT _O_NOINHERIT
-#define O_SEQUENTIAL   _O_SEQUENTIAL
-#define O_RANDOM    _O_RANDOM
-#endif
 /*
  * RT-Thread DFS Interface for win-directory as an disk device
  */

bsp/simulator/rtconfig.h

@@ -16,6 +16,9 @@
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
 
@@ -39,7 +42,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "console"
-#define RT_VER_NUM 0x40003
+#define RT_VER_NUM 0x40004
 
 /* RT-Thread Components */
 
@@ -54,16 +57,17 @@
 /* Command shell */
 
 #define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
 #define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_USING_HISTORY
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_DEFAULT
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -94,6 +98,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 
@@ -103,6 +108,7 @@
 /* POSIX layer and C standard library */
 
 #define RT_LIBC_USING_TIME
+#define RT_LIBC_DEFAULT_TIMEZONE 8
 
 /* Network */
 
@@ -124,6 +130,9 @@
 /* Utilities */
 
 
+/* RT-Thread Utestcases */
+
+
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
@@ -154,6 +163,8 @@
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
 
 /* Micrium: Micrium software products porting for RT-Thread */
 
@@ -166,7 +177,6 @@
 
 /* miscellaneous packages */
 
-
 /* samples: kernel and components samples */
 
 

bsp/stm32/libraries/.ignore_format.yml

@@ -0,0 +1,15 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- STM32F0xx_HAL
+- STM32F2xx_HAL
+- STM32F4xx_HAL
+- STM32F7xx_HAL
+- STM32G0xx_HAL
+- STM32G4xx_HAL
+- STM32L4xx_HAL
+- STM32MPxx_HAL
+- STM32WBxx_HAL
+- STM32H7xx_HAL

bsp/stm32/libraries/HAL_Drivers/drv_sdram.c

@@ -24,7 +24,7 @@ static struct rt_memheap system_heap;
 #endif
 
 /**
-  * @brief  Perform the SDRAM exernal memory inialization sequence
+  * @brief
   * @param  hsdram: SDRAM handle
   * @param  Command: Pointer to SDRAM command structure
   * @retval None
@@ -51,7 +51,7 @@ static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM
 
     /* Insert 100 ms delay */
     /* interrupt is not enable, just to delay some time. */
-    for (tmpmrd = 0; tmpmrd < 0xffffff; tmpmrd ++)
+    for (tmpmrd = 0; tmpmrd < 0xffff; tmpmrd ++)
         ;
 
     /* Configure a PALL (precharge all) command */

bsp/stm32/libraries/STM32H7xx_HAL/SConscript

@@ -56,7 +56,7 @@ if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
     src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c']
     src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c']
 
-if GetDepend(['BSP_USING_ETH']):
+if GetDepend(['BSP_USING_ETH']) or GetDepend(['BSP_USING_ETH_H750']):
     src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c']
     src += ['STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c']
 

bsp/stm32/stm32h750-artpi-h750/applications/main.c

@@ -15,10 +15,20 @@
 /* defined the LED0 pin: PI8 */
 #define LED0_PIN    GET_PIN(I, 8)
 
+#ifdef RT_USING_WIFI
+    extern void wlan_autoconnect_init(void);
+#endif
+
 int main(void)
 {
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+    #ifdef RT_USING_WIFI
+    /* init Wi-Fi auto connect feature */
+    wlan_autoconnect_init();
+    /* enable auto reconnect on WLAN device */
+    rt_wlan_config_autoreconnect(RT_TRUE);
+    #endif
 
     while (1)
     {

bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h

@@ -51,7 +51,7 @@ extern "C" {
 /* USER CODE END EM */
 
 /* Exported functions prototypes ---------------------------------------------*/
-
+void Error_Handler(void);
 
 /* USER CODE BEGIN EFP */
 

bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h

@@ -45,12 +45,12 @@
 /* #define HAL_DAC_MODULE_ENABLED   */
 /* #define HAL_DCMI_MODULE_ENABLED   */
 /* #define HAL_DMA2D_MODULE_ENABLED   */
-/* #define HAL_ETH_MODULE_ENABLED   */
+#define HAL_ETH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED   */
 /* #define HAL_NOR_MODULE_ENABLED   */
 /* #define HAL_OTFDEC_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED   */
-/* #define HAL_SDRAM_MODULE_ENABLED   */
+#define HAL_SDRAM_MODULE_ENABLED
 /* #define HAL_HASH_MODULE_ENABLED   */
 /* #define HAL_HRTIM_MODULE_ENABLED   */
 /* #define HAL_HSEM_MODULE_ENABLED   */
@@ -61,17 +61,17 @@
 /* #define HAL_OSPI_MODULE_ENABLED   */
 /* #define HAL_I2S_MODULE_ENABLED   */
 /* #define HAL_SMBUS_MODULE_ENABLED   */
-/* #define HAL_IWDG_MODULE_ENABLED   */
+#define HAL_IWDG_MODULE_ENABLED
 /* #define HAL_LPTIM_MODULE_ENABLED   */
-/* #define HAL_LTDC_MODULE_ENABLED   */
+#define HAL_LTDC_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED   */
 /* #define HAL_RNG_MODULE_ENABLED   */
 /* #define HAL_RTC_MODULE_ENABLED   */
 /* #define HAL_SAI_MODULE_ENABLED   */
-/* #define HAL_SD_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
 /* #define HAL_MMC_MODULE_ENABLED   */
 /* #define HAL_SPDIFRX_MODULE_ENABLED   */
-/* #define HAL_SPI_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
 /* #define HAL_SWPMI_MODULE_ENABLED   */
 /* #define HAL_TIM_MODULE_ENABLED   */
 #define HAL_UART_MODULE_ENABLED
@@ -79,7 +79,7 @@
 /* #define HAL_IRDA_MODULE_ENABLED   */
 /* #define HAL_SMARTCARD_MODULE_ENABLED   */
 /* #define HAL_WWDG_MODULE_ENABLED   */
-/* #define HAL_PCD_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
 /* #define HAL_HCD_MODULE_ENABLED   */
 /* #define HAL_DFSDM_MODULE_ENABLED   */
 /* #define HAL_DSI_MODULE_ENABLED   */
@@ -105,11 +105,11 @@
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSE_VALUE)
-#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#define HSE_VALUE    (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -117,7 +117,7 @@
   *        This value is the default CSI value after Reset.
   */
 #if !defined  (CSI_VALUE)
-  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+  #define CSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
 #endif /* CSI_VALUE */
 
 /**
@@ -126,7 +126,7 @@
   *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    (64000000UL) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
@@ -134,11 +134,11 @@
   *        This value is used by the UART, RTC HAL module to compute the system frequency
   */
 #if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+  #define LSE_VALUE    (32768UL) /*!< Value of the External oscillator in Hz*/
 #endif /* LSE_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+  #define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
 #if !defined  (LSI_VALUE)
@@ -153,7 +153,7 @@
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+  #define EXTERNAL_CLOCK_VALUE    12288000UL /*!< Value of the External clock in Hz*/
 #endif /* EXTERNAL_CLOCK_VALUE */
 
 /* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -163,9 +163,9 @@
 /**
   * @brief This is the HAL system configuration section
   */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
+#define  VDD_VALUE                    (3300UL) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0UL) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
 #define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
 #define  USE_SPI_CRC	              0U               /*!< use CRC in SPI */
 
@@ -222,12 +222,12 @@
 #define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
 #define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
 
-#define ETH_MAC_ADDR0    ((uint8_t)0x02)
-#define ETH_MAC_ADDR1    ((uint8_t)0x00)
-#define ETH_MAC_ADDR2    ((uint8_t)0x00)
-#define ETH_MAC_ADDR3    ((uint8_t)0x00)
-#define ETH_MAC_ADDR4    ((uint8_t)0x00)
-#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+#define ETH_MAC_ADDR0    (0x02UL)
+#define ETH_MAC_ADDR1    (0x00UL)
+#define ETH_MAC_ADDR2    (0x00UL)
+#define ETH_MAC_ADDR3    (0x00UL)
+#define ETH_MAC_ADDR4    (0x00UL)
+#define ETH_MAC_ADDR5    (0x00UL)
 
 /* ########################## Assert Selection ############################## */
 /**
@@ -277,6 +277,10 @@
   #include "stm32h7xx_hal_dfsdm.h"
 #endif /* HAL_DFSDM_MODULE_ENABLED */
 
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
 #ifdef HAL_ETH_MODULE_ENABLED
   #include "stm32h7xx_hal_eth.h"
 #endif /* HAL_ETH_MODULE_ENABLED */
@@ -306,7 +310,7 @@
 #endif /* HAL_COMP_MODULE_ENABLED */
 
 #ifdef HAL_CORDIC_MODULE_ENABLED
-   #include "stm32h7xx_hal_cordic.h"
+  #include "stm32h7xx_hal_cordic.h"
 #endif /* HAL_CORDIC_MODULE_ENABLED */
 
 #ifdef HAL_CRC_MODULE_ENABLED
@@ -325,14 +329,14 @@
   #include "stm32h7xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
-#ifdef HAL_FMAC_MODULE_ENABLED
-  #include "stm32h7xx_hal_fmac.h"
-#endif /* HAL_FMAC_MODULE_ENABLED */
-
 #ifdef HAL_GFXMMU_MODULE_ENABLED
   #include "stm32h7xx_hal_gfxmmu.h"
 #endif /* HAL_GFXMMU_MODULE_ENABLED */
 
+#ifdef HAL_FMAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
 #ifdef HAL_HRTIM_MODULE_ENABLED
   #include "stm32h7xx_hal_hrtim.h"
 #endif /* HAL_HRTIM_MODULE_ENABLED */
@@ -390,13 +394,17 @@
 #endif /* HAL_OPAMP_MODULE_ENABLED */
 
 #ifdef HAL_OSPI_MODULE_ENABLED
-  #include "stm32h7xx_hal_ospi.h"
+ #include "stm32h7xx_hal_ospi.h"
 #endif /* HAL_OSPI_MODULE_ENABLED */
 
 #ifdef HAL_OTFDEC_MODULE_ENABLED
 #include "stm32h7xx_hal_otfdec.h"
 #endif /* HAL_OTFDEC_MODULE_ENABLED */
 
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
 #ifdef HAL_PWR_MODULE_ENABLED
  #include "stm32h7xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
@@ -407,7 +415,7 @@
 
 #ifdef HAL_RAMECC_MODULE_ENABLED
  #include "stm32h7xx_hal_ramecc.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
+#endif /* HAL_RAMECC_MODULE_ENABLED */
 
 #ifdef HAL_RNG_MODULE_ENABLED
  #include "stm32h7xx_hal_rng.h"
@@ -477,14 +485,6 @@
  #include "stm32h7xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
 
-#ifdef HAL_PSSI_MODULE_ENABLED
-  #include "stm32h7xx_hal_pssi.h"
-#endif /* HAL_PSSI_MODULE_ENABLED */
-
-#ifdef HAL_DTS_MODULE_ENABLED
-  #include "stm32h7xx_hal_dts.h"
-#endif /* HAL_DTS_MODULE_ENABLED */
-
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
@@ -497,7 +497,7 @@
   */
   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(uint8_t *file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
@@ -506,6 +506,6 @@
 }
 #endif
 
-#endif /* __STM32H7xx_HAL_CONF_H */
+#endif /* STM32H7xx_HAL_CONF_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c

@@ -76,6 +76,545 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
+/**
+* @brief ETH MSP Initialization
+* This function configures the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(heth->Instance==ETH)
+  {
+  /* USER CODE BEGIN ETH_MspInit 0 */
+
+  /* USER CODE END ETH_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ETH1MAC_CLK_ENABLE();
+    __HAL_RCC_ETH1TX_CLK_ENABLE();
+    __HAL_RCC_ETH1RX_CLK_ENABLE();
+
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**ETH GPIO Configuration
+    PG11     ------> ETH_TX_EN
+    PG14     ------> ETH_TXD1
+    PG13     ------> ETH_TXD0
+    PC1     ------> ETH_MDC
+    PA2     ------> ETH_MDIO
+    PA1     ------> ETH_REF_CLK
+    PA7     ------> ETH_CRS_DV
+    PC4     ------> ETH_RXD0
+    PC5     ------> ETH_RXD1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* ETH interrupt Init */
+    HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(ETH_IRQn);
+  /* USER CODE BEGIN ETH_MspInit 1 */
+
+  /* USER CODE END ETH_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ETH MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
+{
+  if(heth->Instance==ETH)
+  {
+  /* USER CODE BEGIN ETH_MspDeInit 0 */
+
+  /* USER CODE END ETH_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ETH1MAC_CLK_DISABLE();
+    __HAL_RCC_ETH1TX_CLK_DISABLE();
+    __HAL_RCC_ETH1RX_CLK_DISABLE();
+
+    /**ETH GPIO Configuration
+    PG11     ------> ETH_TX_EN
+    PG14     ------> ETH_TXD1
+    PG13     ------> ETH_TXD0
+    PC1     ------> ETH_MDC
+    PA2     ------> ETH_MDIO
+    PA1     ------> ETH_REF_CLK
+    PA7     ------> ETH_CRS_DV
+    PC4     ------> ETH_RXD0
+    PC5     ------> ETH_RXD1
+    */
+    HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_13);
+
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_7);
+
+    /* ETH interrupt DeInit */
+    HAL_NVIC_DisableIRQ(ETH_IRQn);
+  /* USER CODE BEGIN ETH_MspDeInit 1 */
+
+  /* USER CODE END ETH_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief LTDC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hltdc: LTDC handle pointer
+* @retval None
+*/
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hltdc->Instance==LTDC)
+  {
+  /* USER CODE BEGIN LTDC_MspInit 0 */
+
+  /* USER CODE END LTDC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LTDC_CLK_ENABLE();
+
+    __HAL_RCC_GPIOK_CLK_ENABLE();
+    __HAL_RCC_GPIOJ_CLK_ENABLE();
+    __HAL_RCC_GPIOI_CLK_ENABLE();
+    /**LTDC GPIO Configuration
+    PK5     ------> LTDC_B6
+    PK4     ------> LTDC_B5
+    PJ15     ------> LTDC_B3
+    PK6     ------> LTDC_B7
+    PK3     ------> LTDC_B4
+    PK7     ------> LTDC_DE
+    PJ14     ------> LTDC_B2
+    PJ12     ------> LTDC_B0
+    PJ13     ------> LTDC_B1
+    PI12     ------> LTDC_HSYNC
+    PI13     ------> LTDC_VSYNC
+    PI14     ------> LTDC_CLK
+    PK2     ------> LTDC_G7
+    PK0     ------> LTDC_G5
+    PK1     ------> LTDC_G6
+    PJ11     ------> LTDC_G4
+    PJ10     ------> LTDC_G3
+    PJ9     ------> LTDC_G2
+    PJ0     ------> LTDC_R1
+    PJ8     ------> LTDC_G1
+    PJ7     ------> LTDC_G0
+    PJ6     ------> LTDC_R7
+    PI15     ------> LTDC_R0
+    PJ1     ------> LTDC_R2
+    PJ5     ------> LTDC_R6
+    PJ2     ------> LTDC_R3
+    PJ3     ------> LTDC_R4
+    PJ4     ------> LTDC_R5
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_3
+                          |GPIO_PIN_7|GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+    HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_14|GPIO_PIN_12|GPIO_PIN_13
+                          |GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_0
+                          |GPIO_PIN_8|GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_1
+                          |GPIO_PIN_5|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+    HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+    HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN LTDC_MspInit 1 */
+
+  /* USER CODE END LTDC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief LTDC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hltdc: LTDC handle pointer
+* @retval None
+*/
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+{
+  if(hltdc->Instance==LTDC)
+  {
+  /* USER CODE BEGIN LTDC_MspDeInit 0 */
+
+  /* USER CODE END LTDC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LTDC_CLK_DISABLE();
+
+    /**LTDC GPIO Configuration
+    PK5     ------> LTDC_B6
+    PK4     ------> LTDC_B5
+    PJ15     ------> LTDC_B3
+    PK6     ------> LTDC_B7
+    PK3     ------> LTDC_B4
+    PK7     ------> LTDC_DE
+    PJ14     ------> LTDC_B2
+    PJ12     ------> LTDC_B0
+    PJ13     ------> LTDC_B1
+    PI12     ------> LTDC_HSYNC
+    PI13     ------> LTDC_VSYNC
+    PI14     ------> LTDC_CLK
+    PK2     ------> LTDC_G7
+    PK0     ------> LTDC_G5
+    PK1     ------> LTDC_G6
+    PJ11     ------> LTDC_G4
+    PJ10     ------> LTDC_G3
+    PJ9     ------> LTDC_G2
+    PJ0     ------> LTDC_R1
+    PJ8     ------> LTDC_G1
+    PJ7     ------> LTDC_G0
+    PJ6     ------> LTDC_R7
+    PI15     ------> LTDC_R0
+    PJ1     ------> LTDC_R2
+    PJ5     ------> LTDC_R6
+    PJ2     ------> LTDC_R3
+    PJ3     ------> LTDC_R4
+    PJ4     ------> LTDC_R5
+    */
+    HAL_GPIO_DeInit(GPIOK, GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_3
+                          |GPIO_PIN_7|GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1);
+
+    HAL_GPIO_DeInit(GPIOJ, GPIO_PIN_15|GPIO_PIN_14|GPIO_PIN_12|GPIO_PIN_13
+                          |GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_0
+                          |GPIO_PIN_8|GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_1
+                          |GPIO_PIN_5|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4);
+
+    HAL_GPIO_DeInit(GPIOI, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+  /* USER CODE BEGIN LTDC_MspDeInit 1 */
+
+  /* USER CODE END LTDC_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC1 GPIO Configuration
+    PC10     ------> SDMMC1_D2
+    PC11     ------> SDMMC1_D3
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    PC8     ------> SDMMC1_D0
+    PC9     ------> SDMMC1_D1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8
+                          |GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* SDMMC1 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+  else if(hsd->Instance==SDMMC2)
+  {
+  /* USER CODE BEGIN SDMMC2_MspInit 0 */
+
+  /* USER CODE END SDMMC2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC2_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC2 GPIO Configuration
+    PB4 (NJTRST)     ------> SDMMC2_D3
+    PD6     ------> SDMMC2_CK
+    PB3 (JTDO/TRACESWO)     ------> SDMMC2_D2
+    PD7     ------> SDMMC2_CMD
+    PB15     ------> SDMMC2_D1
+    PB14     ------> SDMMC2_D0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_15|GPIO_PIN_14;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_SDIO2;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* SDMMC2 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
+  /* USER CODE BEGIN SDMMC2_MspInit 1 */
+
+  /* USER CODE END SDMMC2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+  /* USER CODE END SDMMC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+    /**SDMMC1 GPIO Configuration
+    PC10     ------> SDMMC1_D2
+    PC11     ------> SDMMC1_D3
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    PC8     ------> SDMMC1_D0
+    PC9     ------> SDMMC1_D1
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8
+                          |GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+    /* SDMMC1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+  /* USER CODE END SDMMC1_MspDeInit 1 */
+  }
+  else if(hsd->Instance==SDMMC2)
+  {
+  /* USER CODE BEGIN SDMMC2_MspDeInit 0 */
+
+  /* USER CODE END SDMMC2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC2_CLK_DISABLE();
+
+    /**SDMMC2 GPIO Configuration
+    PB4 (NJTRST)     ------> SDMMC2_D3
+    PD6     ------> SDMMC2_CK
+    PB3 (JTDO/TRACESWO)     ------> SDMMC2_D2
+    PD7     ------> SDMMC2_CMD
+    PB15     ------> SDMMC2_D1
+    PB14     ------> SDMMC2_D0
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_15|GPIO_PIN_14);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* SDMMC2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SDMMC2_IRQn);
+  /* USER CODE BEGIN SDMMC2_MspDeInit 1 */
+
+  /* USER CODE END SDMMC2_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration
+    PB5     ------> SPI1_MOSI
+    PG9     ------> SPI1_MISO
+    PA5     ------> SPI1_SCK
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+  else if(hspi->Instance==SPI4)
+  {
+  /* USER CODE BEGIN SPI4_MspInit 0 */
+
+  /* USER CODE END SPI4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI4_CLK_ENABLE();
+
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    /**SPI4 GPIO Configuration
+    PE2     ------> SPI4_SCK
+    PE5     ------> SPI4_MISO
+    PE6     ------> SPI4_MOSI
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_5|GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI4_MspInit 1 */
+
+  /* USER CODE END SPI4_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+
+    /**SPI1 GPIO Configuration
+    PB5     ------> SPI1_MOSI
+    PG9     ------> SPI1_MISO
+    PA5     ------> SPI1_SCK
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
+
+    HAL_GPIO_DeInit(GPIOG, GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+  else if(hspi->Instance==SPI4)
+  {
+  /* USER CODE BEGIN SPI4_MspDeInit 0 */
+
+  /* USER CODE END SPI4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI4_CLK_DISABLE();
+
+    /**SPI4 GPIO Configuration
+    PE2     ------> SPI4_SCK
+    PE5     ------> SPI4_MISO
+    PE6     ------> SPI4_MOSI
+    */
+    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_5|GPIO_PIN_6);
+
+  /* USER CODE BEGIN SPI4_MspDeInit 1 */
+
+  /* USER CODE END SPI4_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief UART MSP Initialization
 * This function configures the hardware resources used in this example
@@ -101,21 +640,18 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
     */
     GPIO_InitStruct.Pin = GPIO_PIN_9;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
     GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
     HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
 
     GPIO_InitStruct.Pin = GPIO_PIN_0;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
     GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
-    /* UART4 interrupt Init */
-    HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
-    HAL_NVIC_EnableIRQ(UART4_IRQn);
   /* USER CODE BEGIN UART4_MspInit 1 */
 
   /* USER CODE END UART4_MspInit 1 */
@@ -139,22 +675,17 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
     GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
     GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
     GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
     GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
     HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 
-    /* USART3 interrupt Init */
-    HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
-    HAL_NVIC_EnableIRQ(USART3_IRQn);
-
-    NVIC_EnableIRQ(USART3_IRQn);
   /* USER CODE BEGIN USART3_MspInit 1 */
 
   /* USER CODE END USART3_MspInit 1 */
@@ -186,8 +717,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
 
     HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
 
-    /* UART4 interrupt DeInit */
-    HAL_NVIC_DisableIRQ(UART4_IRQn);
   /* USER CODE BEGIN UART4_MspDeInit 1 */
 
   /* USER CODE END UART4_MspDeInit 1 */
@@ -210,8 +739,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
 
     HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11|GPIO_PIN_12);
 
-    /* USART3 interrupt DeInit */
-    HAL_NVIC_DisableIRQ(USART3_IRQn);
   /* USER CODE BEGIN USART3_MspDeInit 1 */
 
   /* USER CODE END USART3_MspDeInit 1 */
@@ -219,6 +746,282 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
 
 }
 
+/**
+* @brief PCD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hpcd->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 0 */
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USB_OTG_FS GPIO Configuration
+    PA12     ------> USB_OTG_FS_DP
+    PA11     ------> USB_OTG_FS_DM
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+    /* USB_OTG_FS interrupt Init */
+    HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief PCD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
+{
+  if(hpcd->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
+
+    /**USB_OTG_FS GPIO Configuration
+    PA12     ------> USB_OTG_FS_DP
+    PA11     ------> USB_OTG_FS_DM
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12|GPIO_PIN_11);
+
+    /* USB_OTG_FS interrupt DeInit */
+    HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 1 */
+  }
+
+}
+
+static uint32_t FMC_Initialized = 0;
+
+static void HAL_FMC_MspInit(void){
+  /* USER CODE BEGIN FMC_MspInit 0 */
+
+  /* USER CODE END FMC_MspInit 0 */
+  GPIO_InitTypeDef GPIO_InitStruct ={0};
+  if (FMC_Initialized) {
+    return;
+  }
+  FMC_Initialized = 1;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_FMC_CLK_ENABLE();
+
+  /** FMC GPIO Configuration
+  PE1   ------> FMC_NBL1
+  PE0   ------> FMC_NBL0
+  PG15   ------> FMC_SDNCAS
+  PD0   ------> FMC_D2
+  PD1   ------> FMC_D3
+  PG8   ------> FMC_SDCLK
+  PF2   ------> FMC_A2
+  PF1   ------> FMC_A1
+  PF0   ------> FMC_A0
+  PG5   ------> FMC_BA1
+  PF3   ------> FMC_A3
+  PG4   ------> FMC_BA0
+  PG2   ------> FMC_A12
+  PF5   ------> FMC_A5
+  PF4   ------> FMC_A4
+  PC2   ------> FMC_SDNE0
+  PC3   ------> FMC_SDCKE0
+  PE10   ------> FMC_D7
+  PH5   ------> FMC_SDNWE
+  PF13   ------> FMC_A7
+  PF14   ------> FMC_A8
+  PE9   ------> FMC_D6
+  PE11   ------> FMC_D8
+  PD15   ------> FMC_D1
+  PD14   ------> FMC_D0
+  PF12   ------> FMC_A6
+  PF15   ------> FMC_A9
+  PE12   ------> FMC_D9
+  PE15   ------> FMC_D12
+  PF11   ------> FMC_SDNRAS
+  PG0   ------> FMC_A10
+  PE8   ------> FMC_D5
+  PE13   ------> FMC_D10
+  PD10   ------> FMC_D15
+  PD9   ------> FMC_D14
+  PG1   ------> FMC_A11
+  PE7   ------> FMC_D4
+  PE14   ------> FMC_D11
+  PD8   ------> FMC_D13
+  */
+  GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_8
+                          |GPIO_PIN_13|GPIO_PIN_7|GPIO_PIN_14;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
+                          |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
+                          |GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3
+                          |GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_13|GPIO_PIN_14
+                          |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_11;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN FMC_MspInit 1 */
+
+  /* USER CODE END FMC_MspInit 1 */
+}
+
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
+  /* USER CODE BEGIN SDRAM_MspInit 0 */
+
+  /* USER CODE END SDRAM_MspInit 0 */
+  HAL_FMC_MspInit();
+  /* USER CODE BEGIN SDRAM_MspInit 1 */
+
+  /* USER CODE END SDRAM_MspInit 1 */
+}
+
+static uint32_t FMC_DeInitialized = 0;
+
+static void HAL_FMC_MspDeInit(void){
+  /* USER CODE BEGIN FMC_MspDeInit 0 */
+
+  /* USER CODE END FMC_MspDeInit 0 */
+  if (FMC_DeInitialized) {
+    return;
+  }
+  FMC_DeInitialized = 1;
+  /* Peripheral clock enable */
+  __HAL_RCC_FMC_CLK_DISABLE();
+
+  /** FMC GPIO Configuration
+  PE1   ------> FMC_NBL1
+  PE0   ------> FMC_NBL0
+  PG15   ------> FMC_SDNCAS
+  PD0   ------> FMC_D2
+  PD1   ------> FMC_D3
+  PG8   ------> FMC_SDCLK
+  PF2   ------> FMC_A2
+  PF1   ------> FMC_A1
+  PF0   ------> FMC_A0
+  PG5   ------> FMC_BA1
+  PF3   ------> FMC_A3
+  PG4   ------> FMC_BA0
+  PG2   ------> FMC_A12
+  PF5   ------> FMC_A5
+  PF4   ------> FMC_A4
+  PC2   ------> FMC_SDNE0
+  PC3   ------> FMC_SDCKE0
+  PE10   ------> FMC_D7
+  PH5   ------> FMC_SDNWE
+  PF13   ------> FMC_A7
+  PF14   ------> FMC_A8
+  PE9   ------> FMC_D6
+  PE11   ------> FMC_D8
+  PD15   ------> FMC_D1
+  PD14   ------> FMC_D0
+  PF12   ------> FMC_A6
+  PF15   ------> FMC_A9
+  PE12   ------> FMC_D9
+  PE15   ------> FMC_D12
+  PF11   ------> FMC_SDNRAS
+  PG0   ------> FMC_A10
+  PE8   ------> FMC_D5
+  PE13   ------> FMC_D10
+  PD10   ------> FMC_D15
+  PD9   ------> FMC_D14
+  PG1   ------> FMC_A11
+  PE7   ------> FMC_D4
+  PE14   ------> FMC_D11
+  PD8   ------> FMC_D13
+  */
+  HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_8
+                          |GPIO_PIN_13|GPIO_PIN_7|GPIO_PIN_14);
+
+  HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
+                          |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1);
+
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
+                          |GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8);
+
+  HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3
+                          |GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_13|GPIO_PIN_14
+                          |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_11);
+
+  HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3);
+
+  HAL_GPIO_DeInit(GPIOH, GPIO_PIN_5);
+
+  /* USER CODE BEGIN FMC_MspDeInit 1 */
+
+  /* USER CODE END FMC_MspDeInit 1 */
+}
+
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
+  /* USER CODE BEGIN SDRAM_MspDeInit 0 */
+
+  /* USER CODE END SDRAM_MspDeInit 0 */
+  HAL_FMC_MspDeInit();
+  /* USER CODE BEGIN SDRAM_MspDeInit 1 */
+
+  /* USER CODE END SDRAM_MspDeInit 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */

bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc

@@ -1,29 +1,135 @@
 #MicroXplorer Configuration settings - do not modify
+ETH.IPParameters=MediaInterface
+ETH.MediaInterface=HAL_ETH_RMII_MODE
 File.Version=6
-GPIO.groupedBy=Group By Peripherals
+GPIO.groupedBy=
 KeepUserPlacement=false
 Mcu.Family=STM32H7
 Mcu.IP0=CORTEX_M7
-Mcu.IP1=NVIC
-Mcu.IP2=RCC
-Mcu.IP3=SYS
-Mcu.IP4=UART4
-Mcu.IP5=USART3
-Mcu.IPNb=6
+Mcu.IP1=ETH
+Mcu.IP10=SPI4
+Mcu.IP11=SYS
+Mcu.IP12=UART4
+Mcu.IP13=USART3
+Mcu.IP14=USB_OTG_FS
+Mcu.IP2=FMC
+Mcu.IP3=IWDG1
+Mcu.IP4=LTDC
+Mcu.IP5=NVIC
+Mcu.IP6=RCC
+Mcu.IP7=SDMMC1
+Mcu.IP8=SDMMC2
+Mcu.IP9=SPI1
+Mcu.IPNb=15
 Mcu.Name=STM32H750XBHx
 Mcu.Package=TFBGA240
-Mcu.Pin0=PI9
-Mcu.Pin1=PI8
-Mcu.Pin10=VP_SYS_VS_Systick
-Mcu.Pin2=PI11
-Mcu.Pin3=PH1-OSC_OUT (PH1)
-Mcu.Pin4=PH0-OSC_IN (PH0)
-Mcu.Pin5=PA0
-Mcu.Pin6=PB10
-Mcu.Pin7=PB11
-Mcu.Pin8=PD11
-Mcu.Pin9=PD12
-Mcu.PinsNb=11
+Mcu.Pin0=PB5
+Mcu.Pin1=PK5
+Mcu.Pin10=PC11
+Mcu.Pin100=PE7
+Mcu.Pin101=PE14
+Mcu.Pin102=PB14
+Mcu.Pin103=PD8
+Mcu.Pin104=VP_IWDG1_VS_IWDG
+Mcu.Pin105=VP_SYS_VS_Systick
+Mcu.Pin11=PE2
+Mcu.Pin12=PE0
+Mcu.Pin13=PB3 (JTDO/TRACESWO)
+Mcu.Pin14=PK6
+Mcu.Pin15=PK3
+Mcu.Pin16=PD7
+Mcu.Pin17=PC12
+Mcu.Pin18=PE5
+Mcu.Pin19=PG15
+Mcu.Pin2=PG9
+Mcu.Pin20=PK7
+Mcu.Pin21=PG14
+Mcu.Pin22=PG13
+Mcu.Pin23=PJ14
+Mcu.Pin24=PJ12
+Mcu.Pin25=PD2
+Mcu.Pin26=PD0
+Mcu.Pin27=PI9
+Mcu.Pin28=PE6
+Mcu.Pin29=PJ13
+Mcu.Pin3=PC10
+Mcu.Pin30=PD1
+Mcu.Pin31=PC8
+Mcu.Pin32=PC9
+Mcu.Pin33=PA12
+Mcu.Pin34=PA11
+Mcu.Pin35=PG8
+Mcu.Pin36=PF2
+Mcu.Pin37=PF1
+Mcu.Pin38=PF0
+Mcu.Pin39=PG5
+Mcu.Pin4=PE1
+Mcu.Pin40=PI12
+Mcu.Pin41=PI13
+Mcu.Pin42=PI14
+Mcu.Pin43=PF3
+Mcu.Pin44=PG4
+Mcu.Pin45=PG2
+Mcu.Pin46=PK2
+Mcu.Pin47=PH1-OSC_OUT (PH1)
+Mcu.Pin48=PH0-OSC_IN (PH0)
+Mcu.Pin49=PF5
+Mcu.Pin5=PB4 (NJTRST)
+Mcu.Pin50=PF4
+Mcu.Pin51=PK0
+Mcu.Pin52=PK1
+Mcu.Pin53=PJ11
+Mcu.Pin54=PJ10
+Mcu.Pin55=PC1
+Mcu.Pin56=PC2
+Mcu.Pin57=PC3
+Mcu.Pin58=PJ9
+Mcu.Pin59=PA2
+Mcu.Pin6=PK4
+Mcu.Pin60=PA1
+Mcu.Pin61=PA0
+Mcu.Pin62=PJ0
+Mcu.Pin63=PE10
+Mcu.Pin64=PJ8
+Mcu.Pin65=PJ7
+Mcu.Pin66=PJ6
+Mcu.Pin67=PH5
+Mcu.Pin68=PI15
+Mcu.Pin69=PJ1
+Mcu.Pin7=PG11
+Mcu.Pin70=PF13
+Mcu.Pin71=PF14
+Mcu.Pin72=PE9
+Mcu.Pin73=PE11
+Mcu.Pin74=PB10
+Mcu.Pin75=PB11
+Mcu.Pin76=PD15
+Mcu.Pin77=PD14
+Mcu.Pin78=PA7
+Mcu.Pin79=PF12
+Mcu.Pin8=PJ15
+Mcu.Pin80=PF15
+Mcu.Pin81=PE12
+Mcu.Pin82=PE15
+Mcu.Pin83=PJ5
+Mcu.Pin84=PD11
+Mcu.Pin85=PD12
+Mcu.Pin86=PA5
+Mcu.Pin87=PC4
+Mcu.Pin88=PJ2
+Mcu.Pin89=PF11
+Mcu.Pin9=PD6
+Mcu.Pin90=PG0
+Mcu.Pin91=PE8
+Mcu.Pin92=PE13
+Mcu.Pin93=PB15
+Mcu.Pin94=PD10
+Mcu.Pin95=PD9
+Mcu.Pin96=PC5
+Mcu.Pin97=PJ3
+Mcu.Pin98=PJ4
+Mcu.Pin99=PG1
+Mcu.PinsNb=106
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32H750XBHx
@@ -31,47 +137,384 @@ MxCube.Version=6.2.1
 MxDb.Version=DB.6.0.21
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SDMMC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.SDMMC2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-NVIC.UART4_IRQn=true\:0\:0\:false\:false\:true\:true\:true
-NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PA0.GPIOParameters=GPIO_PuPd
-PA0.GPIO_PuPd=GPIO_PULLUP
 PA0.Locked=true
 PA0.Mode=Asynchronous
 PA0.Signal=UART4_TX
-PB10.GPIOParameters=GPIO_PuPd
-PB10.GPIO_PuPd=GPIO_PULLUP
+PA1.GPIOParameters=GPIO_Speed
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA1.Mode=RMII
+PA1.Signal=ETH_REF_CLK
+PA11.GPIOParameters=GPIO_Speed
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA11.Mode=Device_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.GPIOParameters=GPIO_Speed
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA12.Mode=Device_Only
+PA12.Signal=USB_OTG_FS_DP
+PA2.GPIOParameters=GPIO_Speed
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Mode=RMII
+PA2.Signal=ETH_MDIO
+PA5.GPIOParameters=GPIO_Speed
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA7.GPIOParameters=GPIO_Speed
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA7.Mode=RMII
+PA7.Signal=ETH_CRS_DV
 PB10.Mode=Asynchronous
 PB10.Signal=USART3_TX
-PB11.GPIOParameters=GPIO_PuPd
-PB11.GPIO_PuPd=GPIO_PULLUP
 PB11.Mode=Asynchronous
 PB11.Signal=USART3_RX
+PB14.Mode=SD_4_bits_Wide_bus
+PB14.Signal=SDMMC2_D0
+PB15.Mode=SD_4_bits_Wide_bus
+PB15.Signal=SDMMC2_D1
+PB3\ (JTDO/TRACESWO).Mode=SD_4_bits_Wide_bus
+PB3\ (JTDO/TRACESWO).Signal=SDMMC2_D2
+PB4\ (NJTRST).Mode=SD_4_bits_Wide_bus
+PB4\ (NJTRST).Signal=SDMMC2_D3
+PB5.GPIOParameters=GPIO_Speed
+PB5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB5.Mode=Full_Duplex_Master
+PB5.Signal=SPI1_MOSI
+PC1.GPIOParameters=GPIO_Speed
+PC1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC1.Mode=RMII
+PC1.Signal=ETH_MDC
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDMMC1_D2
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDMMC1_D3
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDMMC1_CK
+PC2.GPIOParameters=GPIO_Speed_High_Default
+PC2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC2.Mode=SdramChipSelect1_1
+PC2.Signal=FMC_SDNE0
+PC3.GPIOParameters=GPIO_Speed_High_Default
+PC3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC3.Mode=SdramChipSelect1_1
+PC3.Signal=FMC_SDCKE0
+PC4.GPIOParameters=GPIO_Speed
+PC4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC4.Mode=RMII
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Speed
+PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC5.Mode=RMII
+PC5.Signal=ETH_RXD1
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDMMC1_D0
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDMMC1_D1
+PD0.GPIOParameters=GPIO_Speed_High_Default
+PD0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD0.Signal=FMC_D2_DA2
+PD1.GPIOParameters=GPIO_Speed_High_Default
+PD1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD1.Signal=FMC_D3_DA3
+PD10.GPIOParameters=GPIO_Speed_High_Default
+PD10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD10.Signal=FMC_D15_DA15
 PD11.Mode=CTS_RTS
 PD11.Signal=USART3_CTS
 PD12.Mode=CTS_RTS
 PD12.Signal=USART3_RTS
+PD14.GPIOParameters=GPIO_Speed_High_Default
+PD14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD14.Signal=FMC_D0_DA0
+PD15.GPIOParameters=GPIO_Speed_High_Default
+PD15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD15.Signal=FMC_D1_DA1
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDMMC1_CMD
+PD6.Mode=SD_4_bits_Wide_bus
+PD6.Signal=SDMMC2_CK
+PD7.Mode=SD_4_bits_Wide_bus
+PD7.Signal=SDMMC2_CMD
+PD8.GPIOParameters=GPIO_Speed_High_Default
+PD8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD8.Signal=FMC_D13_DA13
+PD9.GPIOParameters=GPIO_Speed_High_Default
+PD9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD9.Signal=FMC_D14_DA14
+PE0.GPIOParameters=GPIO_Speed_High_Default
+PE0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE0.Signal=FMC_NBL0
+PE1.GPIOParameters=GPIO_Speed_High_Default
+PE1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE1.Signal=FMC_NBL1
+PE10.GPIOParameters=GPIO_Speed_High_Default
+PE10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE10.Signal=FMC_D7_DA7
+PE11.GPIOParameters=GPIO_Speed_High_Default
+PE11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE11.Signal=FMC_D8_DA8
+PE12.GPIOParameters=GPIO_Speed_High_Default
+PE12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE12.Signal=FMC_D9_DA9
+PE13.GPIOParameters=GPIO_Speed_High_Default
+PE13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE13.Signal=FMC_D10_DA10
+PE14.GPIOParameters=GPIO_Speed_High_Default
+PE14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE14.Signal=FMC_D11_DA11
+PE15.GPIOParameters=GPIO_Speed_High_Default
+PE15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE15.Signal=FMC_D12_DA12
+PE2.GPIOParameters=GPIO_Speed
+PE2.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PE2.Mode=Full_Duplex_Master
+PE2.Signal=SPI4_SCK
+PE5.GPIOParameters=GPIO_Speed
+PE5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PE5.Mode=Full_Duplex_Master
+PE5.Signal=SPI4_MISO
+PE6.GPIOParameters=GPIO_Speed
+PE6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PE6.Mode=Full_Duplex_Master
+PE6.Signal=SPI4_MOSI
+PE7.GPIOParameters=GPIO_Speed_High_Default
+PE7.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE7.Signal=FMC_D4_DA4
+PE8.GPIOParameters=GPIO_Speed_High_Default
+PE8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE8.Signal=FMC_D5_DA5
+PE9.GPIOParameters=GPIO_Speed_High_Default
+PE9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE9.Signal=FMC_D6_DA6
+PF0.GPIOParameters=GPIO_Speed_High_Default
+PF0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF0.Signal=FMC_A0
+PF1.GPIOParameters=GPIO_Speed_High_Default
+PF1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF1.Signal=FMC_A1
+PF11.GPIOParameters=GPIO_Speed_High_Default
+PF11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF11.Signal=FMC_SDNRAS
+PF12.GPIOParameters=GPIO_Speed_High_Default
+PF12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF12.Signal=FMC_A6
+PF13.GPIOParameters=GPIO_Speed_High_Default
+PF13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF13.Signal=FMC_A7
+PF14.GPIOParameters=GPIO_Speed_High_Default
+PF14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF14.Signal=FMC_A8
+PF15.GPIOParameters=GPIO_Speed_High_Default
+PF15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF15.Signal=FMC_A9
+PF2.GPIOParameters=GPIO_Speed_High_Default
+PF2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF2.Signal=FMC_A2
+PF3.GPIOParameters=GPIO_Speed_High_Default
+PF3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF3.Signal=FMC_A3
+PF4.GPIOParameters=GPIO_Speed_High_Default
+PF4.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF4.Signal=FMC_A4
+PF5.GPIOParameters=GPIO_Speed_High_Default
+PF5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF5.Signal=FMC_A5
+PG0.GPIOParameters=GPIO_Speed_High_Default
+PG0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG0.Signal=FMC_A10
+PG1.GPIOParameters=GPIO_Speed_High_Default
+PG1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG1.Signal=FMC_A11
+PG11.GPIOParameters=GPIO_Speed
+PG11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG11.Locked=true
+PG11.Mode=RMII
+PG11.Signal=ETH_TX_EN
+PG13.GPIOParameters=GPIO_Speed
+PG13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG13.Mode=RMII
+PG13.Signal=ETH_TXD0
+PG14.GPIOParameters=GPIO_Speed
+PG14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG14.Locked=true
+PG14.Mode=RMII
+PG14.Signal=ETH_TXD1
+PG15.GPIOParameters=GPIO_Speed_High_Default
+PG15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG15.Signal=FMC_SDNCAS
+PG2.GPIOParameters=GPIO_Speed_High_Default
+PG2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG2.Signal=FMC_A12
+PG4.GPIOParameters=GPIO_Speed_High_Default
+PG4.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG4.Signal=FMC_A14_BA0
+PG5.GPIOParameters=GPIO_Speed_High_Default
+PG5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG5.Signal=FMC_A15_BA1
+PG8.GPIOParameters=GPIO_Speed_High_Default
+PG8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG8.Signal=FMC_SDCLK
+PG9.GPIOParameters=GPIO_Speed
+PG9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PG9.Mode=Full_Duplex_Master
+PG9.Signal=SPI1_MISO
 PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
 PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
 PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
 PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
-PI11.Locked=true
-PI11.Signal=GPIO_Output
-PI8.Locked=true
-PI8.Signal=GPIO_Output
-PI9.GPIOParameters=GPIO_PuPd
-PI9.GPIO_PuPd=GPIO_PULLUP
+PH5.GPIOParameters=GPIO_Speed_High_Default
+PH5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH5.Locked=true
+PH5.Signal=FMC_SDNWE
+PI12.GPIOParameters=GPIO_Speed
+PI12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI12.Locked=true
+PI12.Mode=RGB888
+PI12.Signal=LTDC_HSYNC
+PI13.GPIOParameters=GPIO_Speed
+PI13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI13.Locked=true
+PI13.Mode=RGB888
+PI13.Signal=LTDC_VSYNC
+PI14.GPIOParameters=GPIO_Speed
+PI14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI14.Locked=true
+PI14.Mode=RGB888
+PI14.Signal=LTDC_CLK
+PI15.GPIOParameters=GPIO_Speed
+PI15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI15.Locked=true
+PI15.Mode=RGB888
+PI15.Signal=LTDC_R0
 PI9.Locked=true
 PI9.Mode=Asynchronous
 PI9.Signal=UART4_RX
+PJ0.GPIOParameters=GPIO_Speed
+PJ0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ0.Mode=RGB888
+PJ0.Signal=LTDC_R1
+PJ1.GPIOParameters=GPIO_Speed
+PJ1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ1.Mode=RGB888
+PJ1.Signal=LTDC_R2
+PJ10.GPIOParameters=GPIO_Speed
+PJ10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ10.Locked=true
+PJ10.Mode=RGB888
+PJ10.Signal=LTDC_G3
+PJ11.GPIOParameters=GPIO_Speed
+PJ11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ11.Locked=true
+PJ11.Mode=RGB888
+PJ11.Signal=LTDC_G4
+PJ12.GPIOParameters=GPIO_Speed
+PJ12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ12.Locked=true
+PJ12.Mode=RGB888
+PJ12.Signal=LTDC_B0
+PJ13.GPIOParameters=GPIO_Speed
+PJ13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ13.Locked=true
+PJ13.Mode=RGB888
+PJ13.Signal=LTDC_B1
+PJ14.GPIOParameters=GPIO_Speed
+PJ14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ14.Mode=RGB888
+PJ14.Signal=LTDC_B2
+PJ15.GPIOParameters=GPIO_Speed
+PJ15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ15.Mode=RGB888
+PJ15.Signal=LTDC_B3
+PJ2.GPIOParameters=GPIO_Speed
+PJ2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ2.Locked=true
+PJ2.Mode=RGB888
+PJ2.Signal=LTDC_R3
+PJ3.GPIOParameters=GPIO_Speed
+PJ3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ3.Locked=true
+PJ3.Mode=RGB888
+PJ3.Signal=LTDC_R4
+PJ4.GPIOParameters=GPIO_Speed
+PJ4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ4.Locked=true
+PJ4.Mode=RGB888
+PJ4.Signal=LTDC_R5
+PJ5.GPIOParameters=GPIO_Speed
+PJ5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ5.Locked=true
+PJ5.Mode=RGB888
+PJ5.Signal=LTDC_R6
+PJ6.GPIOParameters=GPIO_Speed
+PJ6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ6.Locked=true
+PJ6.Mode=RGB888
+PJ6.Signal=LTDC_R7
+PJ7.GPIOParameters=GPIO_Speed
+PJ7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ7.Mode=RGB888
+PJ7.Signal=LTDC_G0
+PJ8.GPIOParameters=GPIO_Speed
+PJ8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ8.Mode=RGB888
+PJ8.Signal=LTDC_G1
+PJ9.GPIOParameters=GPIO_Speed
+PJ9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ9.Locked=true
+PJ9.Mode=RGB888
+PJ9.Signal=LTDC_G2
+PK0.GPIOParameters=GPIO_Speed
+PK0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK0.Locked=true
+PK0.Mode=RGB888
+PK0.Signal=LTDC_G5
+PK1.GPIOParameters=GPIO_Speed
+PK1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK1.Locked=true
+PK1.Mode=RGB888
+PK1.Signal=LTDC_G6
+PK2.GPIOParameters=GPIO_Speed
+PK2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK2.Locked=true
+PK2.Mode=RGB888
+PK2.Signal=LTDC_G7
+PK3.GPIOParameters=GPIO_Speed
+PK3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK3.Locked=true
+PK3.Mode=RGB888
+PK3.Signal=LTDC_B4
+PK4.GPIOParameters=GPIO_Speed
+PK4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK4.Locked=true
+PK4.Mode=RGB888
+PK4.Signal=LTDC_B5
+PK5.GPIOParameters=GPIO_Speed
+PK5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK5.Locked=true
+PK5.Mode=RGB888
+PK5.Signal=LTDC_B6
+PK6.GPIOParameters=GPIO_Speed
+PK6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK6.Locked=true
+PK6.Mode=RGB888
+PK6.Signal=LTDC_B7
+PK7.GPIOParameters=GPIO_Speed
+PK7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK7.Mode=RGB888
+PK7.Signal=LTDC_DE
 PinOutPanel.CurrentBGAView=Top
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
@@ -98,10 +541,10 @@ ProjectManager.ProjectFileName=CubeMX_Config.ioc
 ProjectManager.ProjectName=CubeMX_Config
 ProjectManager.RegisterCallBack=
 ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=MDK-ARM V5
+ProjectManager.TargetToolchain=MDK-ARM V5.27
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_UART4_Init-UART4-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ETH_Init-ETH-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_LTDC_Init-LTDC-false-HAL-true,6-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,7-MX_SDMMC2_SD_Init-SDMMC2-false-HAL-true,8-MX_SPI4_Init-SPI4-false-HAL-true,9-MX_UART4_Init-UART4-false-HAL-true,10-MX_SPI1_Init-SPI1-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true,12-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 RCC.ADCFreq_Value=400000000
 RCC.AHB12Freq_Value=240000000
 RCC.AHB4Freq_Value=240000000
@@ -129,15 +572,20 @@ RCC.DIVN2=64
 RCC.DIVN3=160
 RCC.DIVP1Freq_Value=480000000
 RCC.DIVP2Freq_Value=400000000
-RCC.DIVP3Freq_Value=400000000
+RCC.DIVP3=8
+RCC.DIVP3Freq_Value=100000000
 RCC.DIVQ1Freq_Value=480000000
 RCC.DIVQ2Freq_Value=400000000
-RCC.DIVQ3Freq_Value=400000000
+RCC.DIVQ3=8
+RCC.DIVQ3Freq_Value=100000000
 RCC.DIVR1Freq_Value=480000000
-RCC.DIVR2Freq_Value=400000000
-RCC.DIVR3Freq_Value=400000000
+RCC.DIVR2=4
+RCC.DIVR2Freq_Value=200000000
+RCC.DIVR3=24
+RCC.DIVR3Freq_Value=33333333.333333332
 RCC.FDCANFreq_Value=480000000
-RCC.FMCFreq_Value=240000000
+RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_PLL2
+RCC.FMCFreq_Value=200000000
 RCC.FamilyName=M
 RCC.HCLK3ClockFreq_Value=240000000
 RCC.HCLKFreq_Value=240000000
@@ -145,16 +593,15 @@ RCC.HPRE=RCC_HCLK_DIV2
 RCC.HRTIMFreq_Value=240000000
 RCC.I2C123Freq_Value=120000000
 RCC.I2C4Freq_Value=120000000
-RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
 RCC.LPTIM1Freq_Value=120000000
 RCC.LPTIM2Freq_Value=120000000
 RCC.LPTIM345Freq_Value=120000000
 RCC.LPUART1Freq_Value=120000000
-RCC.LTDCFreq_Value=400000000
+RCC.LTDCFreq_Value=33333333.333333332
 RCC.MCO1PinFreq_Value=64000000
 RCC.MCO2PinFreq_Value=480000000
 RCC.PLL2FRACN=0
-RCC.PLL3FRACN=0
 RCC.PLLFRACN=0
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 RCC.QSPIFreq_Value=240000000
@@ -164,28 +611,122 @@ RCC.SAI1Freq_Value=480000000
 RCC.SAI23Freq_Value=480000000
 RCC.SAI4AFreq_Value=480000000
 RCC.SAI4BFreq_Value=480000000
-RCC.SDMMCFreq_Value=480000000
+RCC.SDMMC1CLockSelection=RCC_SDMMCCLKSOURCE_PLL2
+RCC.SDMMCFreq_Value=200000000
 RCC.SPDIFRXFreq_Value=480000000
-RCC.SPI123Freq_Value=480000000
-RCC.SPI45Freq_Value=120000000
+RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL2
+RCC.SPI123Freq_Value=400000000
+RCC.SPI45Freq_Value=100000000
 RCC.SPI6Freq_Value=120000000
 RCC.SWPMI1Freq_Value=120000000
 RCC.SYSCLKFreq_VALUE=480000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Spi45ClockSelection=RCC_SPI45CLKSOURCE_PLL3
 RCC.Tim1OutputFreq_Value=240000000
 RCC.Tim2OutputFreq_Value=240000000
 RCC.TraceFreq_Value=64000000
 RCC.USART16Freq_Value=120000000
 RCC.USART234578Freq_Value=120000000
-RCC.USBFreq_Value=480000000
+RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48
+RCC.USBFreq_Value=48000000
 RCC.VCO1OutputFreq_Value=960000000
 RCC.VCO2OutputFreq_Value=800000000
 RCC.VCO3OutputFreq_Value=800000000
 RCC.VCOInput1Freq_Value=5000000
 RCC.VCOInput2Freq_Value=12500000
 RCC.VCOInput3Freq_Value=5000000
+SH.FMC_A0.0=FMC_A0,13b-sda1
+SH.FMC_A0.ConfNb=1
+SH.FMC_A1.0=FMC_A1,13b-sda1
+SH.FMC_A1.ConfNb=1
+SH.FMC_A10.0=FMC_A10,13b-sda1
+SH.FMC_A10.ConfNb=1
+SH.FMC_A11.0=FMC_A11,13b-sda1
+SH.FMC_A11.ConfNb=1
+SH.FMC_A12.0=FMC_A12,13b-sda1
+SH.FMC_A12.ConfNb=1
+SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
+SH.FMC_A14_BA0.ConfNb=1
+SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
+SH.FMC_A15_BA1.ConfNb=1
+SH.FMC_A2.0=FMC_A2,13b-sda1
+SH.FMC_A2.ConfNb=1
+SH.FMC_A3.0=FMC_A3,13b-sda1
+SH.FMC_A3.ConfNb=1
+SH.FMC_A4.0=FMC_A4,13b-sda1
+SH.FMC_A4.ConfNb=1
+SH.FMC_A5.0=FMC_A5,13b-sda1
+SH.FMC_A5.ConfNb=1
+SH.FMC_A6.0=FMC_A6,13b-sda1
+SH.FMC_A6.ConfNb=1
+SH.FMC_A7.0=FMC_A7,13b-sda1
+SH.FMC_A7.ConfNb=1
+SH.FMC_A8.0=FMC_A8,13b-sda1
+SH.FMC_A8.ConfNb=1
+SH.FMC_A9.0=FMC_A9,13b-sda1
+SH.FMC_A9.ConfNb=1
+SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
+SH.FMC_D0_DA0.ConfNb=1
+SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
+SH.FMC_D10_DA10.ConfNb=1
+SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
+SH.FMC_D11_DA11.ConfNb=1
+SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
+SH.FMC_D12_DA12.ConfNb=1
+SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
+SH.FMC_D13_DA13.ConfNb=1
+SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
+SH.FMC_D14_DA14.ConfNb=1
+SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
+SH.FMC_D15_DA15.ConfNb=1
+SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
+SH.FMC_D1_DA1.ConfNb=1
+SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
+SH.FMC_D2_DA2.ConfNb=1
+SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
+SH.FMC_D3_DA3.ConfNb=1
+SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
+SH.FMC_D4_DA4.ConfNb=1
+SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
+SH.FMC_D5_DA5.ConfNb=1
+SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
+SH.FMC_D6_DA6.ConfNb=1
+SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
+SH.FMC_D7_DA7.ConfNb=1
+SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
+SH.FMC_D8_DA8.ConfNb=1
+SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
+SH.FMC_D9_DA9.ConfNb=1
+SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
+SH.FMC_NBL0.ConfNb=1
+SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
+SH.FMC_NBL1.ConfNb=1
+SH.FMC_SDCLK.0=FMC_SDCLK,13b-sda1
+SH.FMC_SDCLK.ConfNb=1
+SH.FMC_SDNCAS.0=FMC_SDNCAS,13b-sda1
+SH.FMC_SDNCAS.ConfNb=1
+SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1
+SH.FMC_SDNRAS.ConfNb=1
+SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1
+SH.FMC_SDNWE.ConfNb=1
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+SPI1.CalculateBaudRate=200.0 MBits/s
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.VirtualType=VM_MASTER
+SPI4.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+SPI4.CalculateBaudRate=50.0 MBits/s
+SPI4.Direction=SPI_DIRECTION_2LINES
+SPI4.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI4.Mode=SPI_MODE_MASTER
+SPI4.VirtualType=VM_MASTER
 USART3.IPParameters=VirtualMode-Asynchronous
 USART3.VirtualMode-Asynchronous=VM_ASYNC
+USB_OTG_FS.IPParameters=VirtualMode
+USB_OTG_FS.VirtualMode=Device_Only
+VP_IWDG1_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG1_VS_IWDG.Signal=IWDG1_VS_IWDG
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
 board=custom

bsp/stm32/stm32h750-artpi-h750/board/Kconfig

@@ -15,6 +15,51 @@ menu "Onboard Peripheral Drivers"
         select BSP_USING_UART4
         default n
 
+    config BSP_USING_SPI_FLASH
+        bool "Enable SPI FLASH (spi1)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI1
+        select PKG_USING_FAL
+        select FAL_USING_SFUD_PORT
+        select RT_USING_SFUD
+        default n
+        
+    config BSP_USING_QSPI_FLASH
+        bool "Enable QSPI FLASH (w25q64 qspi)"
+        select BSP_USING_QSPI
+        select FAL_USING_SFUD_PORT
+        select RT_USING_SFUD
+        select RT_SFUD_USING_QSPI
+        default n
+
+    menuconfig BSP_USING_FS
+        bool "Enable filesystem"
+        select RT_USING_DFS
+        select RT_USING_DFS_ROMFS
+        default n
+        if BSP_USING_FS
+            config BSP_USING_SDCARD_FS
+                bool "Enable SDCARD filesystem"
+                select BSP_USING_SDIO_ARTPI
+                select BSP_USING_SDIO1
+                select RT_USING_DFS_ELMFAT
+                default n        
+            config BSP_USING_SPI_FLASH_FS
+                bool "Enable SPI FLASH filesystem"
+                select BSP_USING_SPI_FLASH
+                select RT_USING_MTD_NOR
+                select PKG_USING_LITTLEFS
+                default n
+        endif
+
+    config BSP_USING_WIFI
+        bool "Enable wifi (AP6212)"
+        select ART_PI_USING_WIFI_6212_LIB
+        select BSP_USING_SPI_FLASH
+        select RT_USING_WIFI
+        select RT_USING_SAL
+        default n
+
 endmenu
 
 menu "On-chip Peripheral Drivers"
@@ -116,11 +161,110 @@ menu "On-chip Peripheral Drivers"
                 endif
         endif
         
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                default n
+        endif
+        
+    config BSP_USING_QSPI
+        bool "Enable QSPI BUS"
+        select RT_USING_QSPI
+        select RT_USING_SPI
+        default n
+
+    config BSP_USING_SDRAM
+        bool "Enable SDRAM"
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    config BSP_USING_LCD
+        bool "Enable LCD"
+        select BSP_USING_LTDC
+        select BSP_USING_GPIO
+        select BSP_USING_SDRAM
+        select RT_USING_MEMHEAP
+        default n
+
+    menuconfig BSP_USING_SDIO_ARTPI
+        bool "Enable SDIO"
+        default n
+        select RT_USING_SDIO
+        if BSP_USING_SDIO_ARTPI
+            config BSP_USING_SDIO1
+                bool "Enable SDIO1"
+                default n
+            config BSP_USING_SDIO2
+                bool "Enable SDIO2"
+                default n
+        endif
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB_DEVICE
+        default n
+
+    menuconfig BSP_USING_USBH
+        bool "Enable USB Host"
+        select RT_USING_USB_HOST
+        default n
+        if BSP_USING_USBH
+            menuconfig RT_USBH_MSTORAGE
+                bool "Enable Udisk Drivers"
+                select RT_USING_DFS
+                select RT_USING_DFS_ELMFAT
+                default n
+                if RT_USBH_MSTORAGE
+                    config UDISK_MOUNTPOINT
+                        string "Udisk mount dir"
+                        default "/"
+                endif
+        endif
+        
+    menuconfig BSP_USING_ETH_H750
+        bool "Enable Ethernet"
+        default n        
+        select RT_USING_LWIP
+        if BSP_USING_ETH_H750
+            config ETH_RESET_PIN
+                string "ETH RESET PIN"
+                default "PA.3"
+        endif
+        if BSP_USING_ETH_H750
+            choice
+                prompt "Choose ETH PHY"
+                default PHY_USING_LAN8720A
+                        config PHY_USING_LAN8720A
+                    bool "USING LAN8720A"
+                    default n
+            endchoice
+        endif
+
+    config BSP_USING_LTDC
+        bool
+        default n        
     source "../libraries/HAL_Drivers/Kconfig"
 
 endmenu
 
-menu "Board extended module Drivers"
+menu "External Libraries"
+
+    config ART_PI_USING_WIFI_6212_LIB
+        bool "Using Wifi(AP6212) Library"
+        select PKG_USING_EASYFLASH        
+        select BSP_USING_SDIO_ARTPI
+        select BSP_USING_SDIO2
+        select RT_USING_LWIP
+        select RT_USING_WIFI
+        default n
 
 endmenu
 

bsp/stm32/stm32h750-artpi-h750/board/SConscript

@@ -1,20 +1,47 @@
+import os
 import rtconfig
 from building import *
 
+objs = []
 cwd = GetCurrentDir()
+list = os.listdir(cwd)
 
 # add the general drivers.
 src = Glob('board.c')
 src += Glob('CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c')
 
 if GetDepend(['BSP_USING_QSPI_FLASH']):
-    src += Glob('ports/drv_qspi_flash.c')
+    src += Glob('port/drv_qspi_flash.c')
 
-if GetDepend('BSP_USING_SPI_LCD'):
-    src = src + ['ports/drv_lcd.c']
+if GetDepend(['BSP_USING_SPI_LCD_ILI9488']):
+    src += Glob('drv_spi_ili9488.c')
+
+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('port/spi_flash_init.c')
+
+if GetDepend(['BSP_USING_FS']):
+    src += Glob('port/filesystem.c')
+
+if GetDepend(['BSP_USING_SDIO_ARTPI']):
+    src += Glob('port/drv_sdio.c')
+
+if GetDepend(['BSP_USING_WIFI']):
+    src += Glob('port/wifi_config.c')
+    src += Glob('port/drv_wlan.c')    
+
+if GetDepend(['BSP_USING_ETH_H750']):
+    src += Glob('port/drv_eth.c')
+
+if GetDepend(['PKG_USING_EASYFLASH']):
+    src += Glob('port/ef_fal_port.c')
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
 
 path = [cwd]
 path += [cwd + '/CubeMX_Config/Core/Inc']
+path += [cwd + '/port']
 
 if rtconfig.CROSS_TOOL == 'gcc':
     src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s']
@@ -22,7 +49,7 @@ elif rtconfig.CROSS_TOOL == 'keil':
     src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s']
 elif rtconfig.CROSS_TOOL == 'iar':
     src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s']
-
+    
 # STM32H743xx || STM32H750xx || STM32F753xx
 # You can select chips from the list above
 CPPDEFINES = ['STM32H750xx']

bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.lds

@@ -1,13 +1,15 @@
 /*
- * linker script for STM32F4xx with GNU ld
- * bernard.xiong 2009-10-14
+ * linker script for STM32H750XBHx with GNU ld
  */
 
 /* Program Entry, set to mark it as "used" and avoid gc */
 MEMORY
 {
-    ROM (rx) : ORIGIN = 0x08000000, LENGTH =  128k /* 128KB flash */
-    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k /* 128K DTCM */
+ROM (rx) : ORIGIN =0x90000000,LENGTH =8192k
+RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
+RxDecripSection (rw) : ORIGIN =0x30040000,LENGTH =32k
+TxDecripSection (rw) : ORIGIN =0x30040060,LENGTH =32k
+RxArraySection (rw) : ORIGIN =0x30040200,LENGTH =32k
 }
 ENTRY(Reset_Handler)
 _system_stack_size = 0x200;
@@ -40,6 +42,25 @@ SECTIONS
         KEEP(*(VSymTab))
         __vsymtab_end = .;
 
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for at server */
+        . = ALIGN(4);
+        __rtatcmdtab_start = .;
+        KEEP(*(RtAtCmdTab))
+        __rtatcmdtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
         /* section information for initial. */
         . = ALIGN(4);
         __rt_init_start = .;
@@ -81,6 +102,7 @@ SECTIONS
         *(.data.*)
         *(.gnu.linkonce.d*)
 
+
         PROVIDE(__dtors_start__ = .);
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
@@ -119,6 +141,33 @@ SECTIONS
     } > RAM
     __bss_end = .;
 
+    .RxDecripSection (NOLOAD) : ALIGN(4)
+    {
+    . = ALIGN(4);
+    *(.RxDecripSection)
+    *(.RxDecripSection.*)
+    . = ALIGN(4);
+    __RxDecripSection_free__ = .;
+    } > RxDecripSection
+    
+    .TxDecripSection (NOLOAD) : ALIGN(4)
+    {
+    . = ALIGN(4);
+    *(.TxDecripSection)
+    *(.TxDecripSection.*)
+    . = ALIGN(4);
+    __TxDecripSection_free__ = .;
+    } > TxDecripSection
+    
+    .RxArraySection (NOLOAD) : ALIGN(4)
+    {
+    . = ALIGN(4);
+    *(.RxArraySection)
+    *(.RxArraySection.*)
+    . = ALIGN(4);
+    __RxArraySection_free__ = .;
+    } > RxArraySection
+
     _end = .;
 
     /* Stabs debugging sections.  */

bsp/stm32/stm32h750-artpi-h750/board/port/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

bsp/stm32/stm32h750-artpi-h750/board/port/drv_eth.c

@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-19     SummerGift   first version
+ * 2018-12-25     zylx         fix some bugs
+ * 2019-06-10     SummerGift   optimize PHY state detection process
+ * 2019-09-03     xiaofan      optimize link change detection process
+ * 2020-07-17     wanghaijing  support h7
+ * 2020-11-30     wanghaijing  add phy reset
+ */
+
+#include<rtthread.h>
+#include<rtdevice.h>
+#include "board.h"
+#include "drv_config.h"
+
+#ifdef BSP_USING_ETH_ARTPI
+
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+#include "drv_eth.h"
+
+/*
+* Emac driver uses CubeMX tool to generate emac and phy's configuration,
+* the configuration files can be found in CubeMX_Config folder.
+*/
+
+/* debug option */
+#define LOG_TAG             "drv.emac"
+#include <drv_log.h>
+
+#define MAX_ADDR_LEN 6
+
+struct rt_stm32_eth
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+    #ifndef PHY_USING_INTERRUPT_MODE
+    rt_timer_t poll_link_timer;
+    #endif
+
+    /* interface address info, hw address */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];
+    /* ETH_Speed */
+    uint32_t    ETH_Speed;
+    /* ETH_Duplex_Mode */
+    uint32_t    ETH_Mode;
+};
+
+static ETH_HandleTypeDef EthHandle;
+static ETH_TxPacketConfig TxConfig;
+static struct rt_stm32_eth stm32_eth_device;
+static uint8_t PHY_ADDR = 0x1F;
+static rt_uint32_t reset_pin = 0;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+    #pragma location=0x30040000
+    ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+    #pragma location=0x30040060
+    ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+    #pragma location=0x30040200
+    uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */
+
+#elif defined ( __CC_ARM )  /* MDK ARM Compiler */
+    __attribute__((at(0x30040000))) ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+    __attribute__((at(0x30040060))) ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+    __attribute__((at(0x30040200))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffer */
+
+#elif defined ( __GNUC__ ) /* GNU Compiler */
+    ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
+    ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection")));   /* Ethernet Tx DMA Descriptors */
+    uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __attribute__((section(".RxArraySection"))); /* Ethernet Receive Buffers */
+#endif
+
+#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
+{
+    unsigned char *buf = (unsigned char *)ptr;
+    int i, j;
+
+    for (i = 0; i < buflen; i += 16)
+    {
+        rt_kprintf("%08X: ", i);
+
+        for (j = 0; j < 16; j++)
+            if (i + j < buflen)
+                rt_kprintf("%02X ", buf[i + j]);
+            else
+                rt_kprintf("   ");
+
+        rt_kprintf(" ");
+
+        for (j = 0; j < 16; j++)
+            if (i + j < buflen)
+                rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+
+        rt_kprintf("\n");
+    }
+}
+#endif
+
+static void phy_reset(void)
+{
+    rt_pin_write(reset_pin, PIN_LOW);
+    rt_thread_mdelay(50);
+    rt_pin_write(reset_pin, PIN_HIGH);
+}
+
+
+/* EMAC initialization function */
+static rt_err_t rt_stm32_eth_init(rt_device_t dev)
+{
+    ETH_MACConfigTypeDef MACConf;
+    uint32_t regvalue = 0;
+    uint8_t  status = RT_EOK;
+
+    __HAL_RCC_D2SRAM3_CLK_ENABLE();
+
+    phy_reset();
+
+    /* ETHERNET Configuration */
+    EthHandle.Instance = ETH;
+    EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
+    EthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE;
+    EthHandle.Init.TxDesc = DMATxDscrTab;
+    EthHandle.Init.RxDesc = DMARxDscrTab;
+    EthHandle.Init.RxBuffLen = ETH_MAX_PACKET_SIZE;
+
+    SCB_InvalidateDCache();
+
+    HAL_ETH_DeInit(&EthHandle);
+
+    /* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
+    if (HAL_ETH_Init(&EthHandle) != HAL_OK)
+    {
+        LOG_E("eth hardware init failed");
+    }
+    else
+    {
+        LOG_D("eth hardware init success");
+    }
+
+    rt_memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig));
+    TxConfig.Attributes   = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
+    TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
+    TxConfig.CRCPadCtrl   = ETH_CRC_PAD_INSERT;
+
+    for (int idx = 0; idx < ETH_RX_DESC_CNT; idx++)
+    {
+        HAL_ETH_DescAssignMemory(&EthHandle, idx, &Rx_Buff[idx][0], NULL);
+    }
+
+    HAL_ETH_SetMDIOClockRange(&EthHandle);
+
+    for(int i = 0; i <= PHY_ADDR; i ++)
+    {
+        if(HAL_ETH_ReadPHYRegister(&EthHandle, i, PHY_SPECIAL_MODES_REG, &regvalue) != HAL_OK)
+        {
+            status = RT_ERROR;
+            /* Can't read from this device address continue with next address */
+            continue;
+        }
+
+        if((regvalue & PHY_BASIC_STATUS_REG) == i)
+        {
+            PHY_ADDR = i;
+            status = RT_EOK;
+            LOG_D("Found a phy, address:0x%02X", PHY_ADDR);
+            break;
+        }
+    }
+
+    if(HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK) == HAL_OK)
+    {
+        HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_SPECIAL_MODES_REG, &regvalue);
+
+        uint32_t tickstart = rt_tick_get();
+
+        /* wait until software reset is done or timeout occured  */
+        while(regvalue & PHY_RESET_MASK)
+        {
+            if((rt_tick_get() - tickstart) <= 500)
+            {
+                if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, &regvalue) != HAL_OK)
+                {
+                    status = RT_ERROR;
+                    break;
+                }
+            }
+            else
+            {
+                status = RT_ETIMEOUT;
+            }
+        }
+    }
+
+    rt_thread_delay(2000);
+
+    if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, &regvalue) == HAL_OK)
+    {
+        regvalue |= PHY_AUTO_NEGOTIATION_MASK;
+        HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, regvalue);
+
+        eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
+        HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
+        MACConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+        MACConf.Speed = ETH_SPEED_100M;
+        HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
+
+        HAL_ETH_Start_IT(&EthHandle);
+    }
+    else
+    {
+        status = RT_ERROR;
+    }
+
+    return status;
+}
+
+static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    LOG_D("emac open");
+    return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_close(rt_device_t dev)
+{
+    LOG_D("emac close");
+    return RT_EOK;
+}
+
+static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    LOG_D("emac read");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    LOG_D("emac write");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
+{
+    switch (cmd)
+    {
+        case NIOCTL_GADDR:
+
+            /* get mac address */
+            if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+            else return -RT_ERROR;
+
+            break;
+
+        default :
+            break;
+    }
+
+    return RT_EOK;
+}
+
+/* ethernet device interface */
+/* transmit data*/
+rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
+{
+    rt_err_t ret = RT_ERROR;
+    HAL_StatusTypeDef state;
+    uint32_t i = 0, framelen = 0;
+    struct pbuf *q;
+    ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT];
+
+    rt_memset(Txbuffer, 0, ETH_TX_DESC_CNT * sizeof(ETH_BufferTypeDef));
+
+    for (q = p; q != NULL; q = q->next)
+    {
+        if (i >= ETH_TX_DESC_CNT)
+            return ERR_IF;
+
+        Txbuffer[i].buffer = q->payload;
+        Txbuffer[i].len = q->len;
+        framelen += q->len;
+
+        if (i > 0)
+        {
+            Txbuffer[i - 1].next = &Txbuffer[i];
+        }
+
+        if (q->next == NULL)
+        {
+            Txbuffer[i].next = NULL;
+        }
+
+        i++;
+    }
+
+    TxConfig.Length = framelen;
+    TxConfig.TxBuffer = Txbuffer;
+
+    #ifdef ETH_TX_DUMP
+    rt_kprintf("Tx dump, len= %d\r\n", framelen);
+    dump_hex(&Txbuffer[0]);
+    #endif
+
+    if (stm32_eth_device.parent.link_status)
+    {
+        SCB_CleanInvalidateDCache();
+        state = HAL_ETH_Transmit(&EthHandle, &TxConfig, 1000);
+
+        if (state != HAL_OK)
+        {
+            LOG_W("eth transmit frame faild: %d", EthHandle.ErrorCode);
+            EthHandle.ErrorCode = HAL_ETH_STATE_READY;
+            EthHandle.gState = HAL_ETH_STATE_READY;
+        }
+    }
+    else
+    {
+        LOG_E("eth transmit frame faild, netif not up");
+    }
+
+    ret = ERR_OK;
+
+    return ret;
+}
+
+/* receive data*/
+struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
+{
+    uint32_t framelength = 0;
+    rt_uint16_t l;
+    struct pbuf *p = RT_NULL, *q;
+    ETH_BufferTypeDef RxBuff;
+    uint32_t alignedAddr;
+
+    if(HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK)
+    {
+        HAL_ETH_GetRxDataLength(&EthHandle, &framelength);
+
+        /* Build Rx descriptor to be ready for next data reception */
+        HAL_ETH_BuildRxDescriptors(&EthHandle);
+
+        /* Invalidate data cache for ETH Rx Buffers */
+        alignedAddr = (uint32_t)RxBuff.buffer & ~0x1F;
+        SCB_InvalidateDCache_by_Addr((uint32_t *)alignedAddr, (uint32_t)RxBuff.buffer - alignedAddr + framelength);
+
+        p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
+
+        if (p != NULL)
+        {
+            for (q = p, l = 0; q != NULL; q = q->next)
+            {
+                memcpy((rt_uint8_t *)q->payload, (rt_uint8_t *)&RxBuff.buffer[l], q->len);
+                l = l + q->len;
+            }
+        }
+    }
+
+    return p;
+}
+
+/* interrupt service routine */
+void ETH_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    HAL_ETH_IRQHandler(&EthHandle);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+    rt_err_t result;
+    result = eth_device_ready(&(stm32_eth_device.parent));
+
+    if (result != RT_EOK)
+        LOG_I("RxCpltCallback err = %d", result);
+}
+
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+    LOG_E("eth err");
+}
+
+enum
+{
+    PHY_LINK        = (1 << 0),
+    PHY_100M        = (1 << 1),
+    PHY_FULL_DUPLEX = (1 << 2),
+};
+
+static void phy_linkchange()
+{
+    static rt_uint8_t phy_speed = 0;
+    rt_uint8_t phy_speed_new = 0;
+    rt_uint32_t status;
+
+    HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
+    LOG_D("phy basic status reg is 0x%X", status);
+
+    if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
+    {
+        rt_uint32_t SR = 0;
+
+        phy_speed_new |= PHY_LINK;
+
+        HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_Status_REG, (uint32_t *)&SR);
+        LOG_D("phy control status reg is 0x%X", SR);
+
+        if (PHY_Status_SPEED_100M(SR))
+        {
+            phy_speed_new |= PHY_100M;
+        }
+
+        if (PHY_Status_FULL_DUPLEX(SR))
+        {
+            phy_speed_new |= PHY_FULL_DUPLEX;
+        }
+    }
+
+    if (phy_speed != phy_speed_new)
+    {
+        phy_speed = phy_speed_new;
+
+        if (phy_speed & PHY_LINK)
+        {
+            LOG_D("link up");
+
+            if (phy_speed & PHY_100M)
+            {
+                LOG_D("100Mbps");
+                stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
+            }
+            else
+            {
+                stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
+                LOG_D("10Mbps");
+            }
+
+            if (phy_speed & PHY_FULL_DUPLEX)
+            {
+                LOG_D("full-duplex");
+                stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE;
+            }
+            else
+            {
+                LOG_D("half-duplex");
+                stm32_eth_device.ETH_Mode = ETH_HALFDUPLEX_MODE;
+            }
+
+            /* send link up. */
+            eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
+        }
+        else
+        {
+            LOG_I("link down");
+            eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
+        }
+    }
+}
+
+#ifdef PHY_USING_INTERRUPT_MODE
+static void eth_phy_isr(void *args)
+{
+    rt_uint32_t status = 0;
+
+    HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
+    LOG_D("phy interrupt status reg is 0x%X", status);
+
+    phy_linkchange();
+}
+#endif /* PHY_USING_INTERRUPT_MODE */
+
+static void phy_monitor_thread_entry(void *parameter)
+{
+    phy_linkchange();
+    #ifdef PHY_USING_INTERRUPT_MODE
+    /* configuration intterrupt pin */
+    rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
+    rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
+    rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
+
+    /* enable phy interrupt */
+    HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
+    #if defined(PHY_INTERRUPT_CTRL_REG)
+    HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
+    #endif
+    #else /* PHY_USING_INTERRUPT_MODE */
+    stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
+                                       NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
+
+    if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
+    {
+        LOG_E("Start link change detection timer failed");
+    }
+
+    #endif /* PHY_USING_INTERRUPT_MODE */
+}
+
+/* Register the EMAC device */
+static int rt_hw_stm32_eth_init(void)
+{
+    rt_err_t state = RT_EOK;
+    reset_pin = rt_pin_get(ETH_RESET_PIN);
+
+    rt_pin_mode(reset_pin, PIN_MODE_OUTPUT);
+    rt_pin_write(reset_pin, PIN_HIGH);
+
+    stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
+    stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE;
+
+    /* OUI 00-80-E1 STMICROELECTRONICS. */
+    stm32_eth_device.dev_addr[0] = 0x00;
+    stm32_eth_device.dev_addr[1] = 0x80;
+    stm32_eth_device.dev_addr[2] = 0xE1;
+    /* generate MAC addr from 96bit unique ID (only for test). */
+    stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
+    stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
+    stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
+
+    stm32_eth_device.parent.parent.init      = rt_stm32_eth_init;
+    stm32_eth_device.parent.parent.open      = rt_stm32_eth_open;
+    stm32_eth_device.parent.parent.close     = rt_stm32_eth_close;
+    stm32_eth_device.parent.parent.read      = rt_stm32_eth_read;
+    stm32_eth_device.parent.parent.write     = rt_stm32_eth_write;
+    stm32_eth_device.parent.parent.control   = rt_stm32_eth_control;
+    stm32_eth_device.parent.parent.user_data = RT_NULL;
+
+    stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
+    stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
+
+    /* register eth device */
+    state = eth_device_init(&(stm32_eth_device.parent), "e0");
+
+    if (RT_EOK == state)
+    {
+        LOG_D("emac device init success");
+    }
+    else
+    {
+        LOG_E("emac device init faild: %d", state);
+        state = -RT_ERROR;
+    }
+
+    /* start phy monitor */
+    rt_thread_t tid;
+    tid = rt_thread_create("phy",
+                           phy_monitor_thread_entry,
+                           RT_NULL,
+                           1024,
+                           RT_THREAD_PRIORITY_MAX - 2,
+                           2);
+
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        state = -RT_ERROR;
+    }
+
+    return state;
+}
+INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
+
+#endif /* BSP_USING_ETH_ARTPI */

bsp/stm32/stm32h750-artpi-h750/board/port/drv_eth.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-25     zylx         first version
+ * 2020-07-18     wanghaijing  add SPECIAL_MODES_REG
+ */
+
+#ifndef __DRV_ETH_H__
+#define __DRV_ETH_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* The PHY basic control register */
+#define PHY_BASIC_CONTROL_REG       0x00U
+#define PHY_RESET_MASK              (1<<15)
+#define PHY_AUTO_NEGOTIATION_MASK   (1<<12)
+
+/* The PHY basic status register */
+#define PHY_BASIC_STATUS_REG        0x01U
+#define PHY_LINKED_STATUS_MASK      (1<<2)
+#define PHY_AUTONEGO_COMPLETE_MASK  (1<<5)
+
+/* The PHY ID one register */
+#define PHY_ID1_REG                 0x02U
+
+/* The PHY ID two register */
+#define PHY_ID2_REG                 0x03U
+
+/* The PHY SPECIAL MODES REGISTER */
+#define PHY_SPECIAL_MODES_REG       0x12U
+
+/* The PHY auto-negotiate advertise register */
+#define PHY_AUTONEG_ADVERTISE_REG   0x04U
+
+#define PHY_Status_REG              0x1FU
+#define PHY_FULL_DUPLEX_MASK        (1<<4)
+#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr)   ((sr) & PHY_100M_MASK)
+#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
+
+#ifdef PHY_USING_LAN8720A
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x1DU
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      0x1EU
+#define PHY_LINK_DOWN_MASK          (1<<4)
+#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
+
+/*  The PHY status register. */
+#define PHY_Status_REG              0x1FU
+#define PHY_10M_MASK                (1<<2)
+#define PHY_100M_MASK               (1<<3)
+#define PHY_FULL_DUPLEX_MASK        (1<<4)
+#endif /* PHY_USING_LAN8720A */
+
+#ifdef PHY_USING_DM9161CEP
+#define PHY_Status_REG              0x11U
+#define PHY_10M_MASK                ((1<<12) || (1<<13))
+#define PHY_100M_MASK               ((1<<14) || (1<<15))
+#define PHY_FULL_DUPLEX_MASK        ((1<<15) || (1<<13))
+/*  The PHY interrupt source flag register. */
+#define PHY_INTERRUPT_FLAG_REG      0x15U
+/*  The PHY interrupt mask register. */
+#define PHY_INTERRUPT_MASK_REG      0x15U
+#define PHY_LINK_CHANGE_FLAG        (1<<2)
+#define PHY_LINK_CHANGE_MASK        (1<<9)
+#define PHY_INT_MASK                0
+
+#endif /* PHY_USING_DM9161CEP */
+
+#ifdef PHY_USING_DP83848C
+#define PHY_Status_REG              0x10U
+#define PHY_10M_MASK                (1<<1)
+#define PHY_FULL_DUPLEX_MASK        (1<<2)
+#define PHY_Status_SPEED_10M(sr)    ((sr) & PHY_10M_MASK)
+#define PHY_Status_SPEED_100M(sr)   (!PHY_Status_SPEED_10M(sr))
+#define PHY_Status_FULL_DUPLEX(sr)  ((sr) & PHY_FULL_DUPLEX_MASK)
+#define PHY_INTERRUPT_FLAG_REG      0x12U
+#define PHY_LINK_CHANGE_FLAG        (1<<13)
+#define PHY_INTERRUPT_CTRL_REG      0x11U
+#define PHY_INTERRUPT_EN            ((1<<0)|(1<<1))
+#define PHY_INTERRUPT_MASK_REG      0x12U
+#define PHY_INT_MASK                (1<<5)
+#endif /* PHY_USING_DP83848C */
+#endif /* __DRV_ETH_H__ */

bsp/stm32/stm32h750-artpi-h750/board/port/drv_sdio.c

@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-05-23     liuduanfei   first version
+ */
+#include "board.h"
+
+#ifdef RT_USING_SDIO
+
+#if !defined(BSP_USING_SDIO1) && !defined(BSP_USING_SDIO2)
+    #error "Please define at least one BSP_USING_SDIOx"
+#endif
+
+#include "drv_sdio.h"
+
+#define DBG_TAG              "drv.sdio"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+static struct rt_mmcsd_host *host1;
+static struct rt_mmcsd_host *host2;
+static rt_mutex_t mmcsd_mutex = RT_NULL;
+
+#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS    (1000000)
+
+struct sdio_pkg
+{
+    struct rt_mmcsd_cmd *cmd;
+    void *buff;
+    rt_uint32_t flag;
+};
+
+struct rthw_sdio
+{
+    struct rt_mmcsd_host *host;
+    struct stm32_sdio_des sdio_des;
+    struct rt_event event;
+    struct sdio_pkg *pkg;
+};
+
+ALIGN(SDIO_ALIGN_LEN)
+static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
+
+/**
+  * @brief  This function get order from sdio.
+  * @param  data
+  * @retval sdio order
+  */
+static int get_order(rt_uint32_t data)
+{
+    int order = 0;
+
+    switch (data)
+    {
+        case 1:
+            order = 0;
+            break;
+
+        case 2:
+            order = 1;
+            break;
+
+        case 4:
+            order = 2;
+            break;
+
+        case 8:
+            order = 3;
+            break;
+
+        case 16:
+            order = 4;
+            break;
+
+        case 32:
+            order = 5;
+            break;
+
+        case 64:
+            order = 6;
+            break;
+
+        case 128:
+            order = 7;
+            break;
+
+        case 256:
+            order = 8;
+            break;
+
+        case 512:
+            order = 9;
+            break;
+
+        case 1024:
+            order = 10;
+            break;
+
+        case 2048:
+            order = 11;
+            break;
+
+        case 4096:
+            order = 12;
+            break;
+
+        case 8192:
+            order = 13;
+            break;
+
+        case 16384:
+            order = 14;
+            break;
+
+        default :
+            order = 0;
+            break;
+    }
+
+    return order;
+}
+
+/**
+  * @brief  This function wait sdio cmd completed.
+  * @param  sdio rthw_sdio
+  * @retval None
+  */
+static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
+{
+    rt_uint32_t status;
+    struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+
+    if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                      rt_tick_from_millisecond(5000), &status) != RT_EOK)
+    {
+        LOG_E("wait cmd completed timeout");
+        cmd->err = -RT_ETIMEOUT;
+        return;
+    }
+
+    cmd->resp[0] = hw_sdio->resp1;
+
+    if (resp_type(cmd) == RESP_R2)
+    {
+        cmd->resp[1] = hw_sdio->resp2;
+        cmd->resp[2] = hw_sdio->resp3;
+        cmd->resp[3] = hw_sdio->resp4;
+    }
+
+    if (status & SDIO_ERRORS)
+    {
+        if ((status & SDMMC_STA_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
+        {
+            cmd->err = RT_EOK;
+        }
+        else
+        {
+            cmd->err = -RT_ERROR;
+        }
+    }
+    else
+    {
+        cmd->err = RT_EOK;
+    }
+
+
+    if (cmd->err == RT_EOK)
+    {
+        LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
+    }
+    else
+    {
+        LOG_D("send command error = %d", cmd->err);
+    }
+}
+
+/**
+  * @brief  This function send command.
+  * @param  sdio rthw_sdio
+  * @param  pkg  sdio package
+  * @retval None
+  */
+static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
+{
+    struct rt_mmcsd_cmd *cmd = pkg->cmd;
+    struct rt_mmcsd_data *data = cmd->data;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+    rt_uint32_t reg_cmd;
+
+    rt_event_control(&sdio->event, RT_IPC_CMD_RESET, RT_NULL);
+    /* save pkg */
+    sdio->pkg = pkg;
+
+    LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
+          cmd->cmd_code,
+          cmd->arg,
+          resp_type(cmd) == RESP_NONE ? "NONE"  : "",
+          resp_type(cmd) == RESP_R1  ? "R1"  : "",
+          resp_type(cmd) == RESP_R1B ? "R1B"  : "",
+          resp_type(cmd) == RESP_R2  ? "R2"  : "",
+          resp_type(cmd) == RESP_R3  ? "R3"  : "",
+          resp_type(cmd) == RESP_R4  ? "R4"  : "",
+          resp_type(cmd) == RESP_R5  ? "R5"  : "",
+          resp_type(cmd) == RESP_R6  ? "R6"  : "",
+          resp_type(cmd) == RESP_R7  ? "R7"  : "",
+          data ? (data->flags & DATA_DIR_WRITE ?  'w' : 'r') : '-',
+          data ? data->blks * data->blksize : 0,
+          data ? data->blksize : 0
+         );
+
+    hw_sdio->mask |= SDIO_MASKR_ALL;
+    reg_cmd = cmd->cmd_code | SDMMC_CMD_CPSMEN;
+
+    /* data pre configuration */
+    if (data != RT_NULL)
+    {
+        SCB_CleanInvalidateDCache();
+
+        reg_cmd |= SDMMC_CMD_CMDTRANS;
+        hw_sdio->mask &= ~(SDMMC_MASK_CMDRENDIE | SDMMC_MASK_CMDSENTIE);
+        hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
+        hw_sdio->dlen = data->blks * data->blksize;
+        hw_sdio->dctrl = (get_order(data->blksize) << 4) | (data->flags & DATA_DIR_READ ? SDMMC_DCTRL_DTDIR : 0);
+        hw_sdio->idmabase0r = (rt_uint32_t)cache_buf;
+        hw_sdio->idmatrlr = SDMMC_IDMA_IDMAEN;
+    }
+
+    if (resp_type(cmd) == RESP_R2)
+        reg_cmd |= SDMMC_CMD_WAITRESP;
+    else if(resp_type(cmd) != RESP_NONE)
+        reg_cmd |= SDMMC_CMD_WAITRESP_0;
+
+    hw_sdio->arg = cmd->arg;
+    hw_sdio->cmd = reg_cmd;
+    /* wait completed */
+    rthw_sdio_wait_completed(sdio);
+
+    /* Waiting for data to be sent to completion */
+    if (data != RT_NULL)
+    {
+        volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
+
+        while (count && (hw_sdio->sta & SDMMC_STA_DPSMACT))
+        {
+            count--;
+        }
+
+        if ((count == 0) || (hw_sdio->sta & SDIO_ERRORS))
+        {
+            cmd->err = -RT_ERROR;
+        }
+    }
+
+    /* data post configuration */
+    if (data != RT_NULL)
+    {
+        if (data->flags & DATA_DIR_READ)
+        {
+            rt_memcpy(data->buf, cache_buf, data->blks * data->blksize);
+            SCB_CleanInvalidateDCache();
+        }
+    }
+}
+
+/**
+  * @brief  This function send sdio request.
+  * @param  sdio  rthw_sdio
+  * @param  req   request
+  * @retval None
+  */
+static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct sdio_pkg pkg;
+    struct rthw_sdio *sdio = host->private_data;
+    struct rt_mmcsd_data *data;
+
+
+    rt_mutex_take(mmcsd_mutex, RT_WAITING_FOREVER);
+
+    if (req->cmd != RT_NULL)
+    {
+        rt_memset(&pkg, 0, sizeof(pkg));
+        data = req->cmd->data;
+        pkg.cmd = req->cmd;
+
+        if (data != RT_NULL)
+        {
+            rt_uint32_t size = data->blks * data->blksize;
+
+            RT_ASSERT(size <= SDIO_BUFF_SIZE);
+
+            if (data->flags & DATA_DIR_WRITE)
+            {
+                rt_memcpy(cache_buf, data->buf, size);
+            }
+        }
+
+        rthw_sdio_send_command(sdio, &pkg);
+    }
+
+    if (req->stop != RT_NULL)
+    {
+        rt_memset(&pkg, 0, sizeof(pkg));
+        pkg.cmd = req->stop;
+        rthw_sdio_send_command(sdio, &pkg);
+    }
+
+    mmcsd_req_complete(sdio->host);
+
+    rt_mutex_release(mmcsd_mutex);
+}
+
+
+/**
+  * @brief  This function interrupt process function.
+  * @param  host  rt_mmcsd_host
+  * @retval None
+  */
+void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
+{
+    struct rthw_sdio *sdio = host->private_data;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+    rt_uint32_t intstatus = hw_sdio->sta;
+
+    /* clear irq flag*/
+    hw_sdio->icr = intstatus;
+
+    rt_event_send(&sdio->event, intstatus);
+}
+
+/**
+  * @brief  This function config sdio.
+  * @param  host    rt_mmcsd_host
+  * @param  io_cfg  rt_mmcsd_io_cfg
+  * @retval None
+  */
+static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    rt_uint32_t temp, clk_src;
+    rt_uint32_t clk = io_cfg->clock;
+    struct rthw_sdio *sdio = host->private_data;
+    struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
+
+    LOG_D("clk:%dK width:%s%s%s power:%s%s%s",
+          clk / 1000,
+          io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
+          io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
+          io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
+          io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
+          io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
+          io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
+         );
+
+    clk_src = SDIO_CLOCK_FREQ;
+
+    if (clk > 0)
+    {
+        if (clk > host->freq_max)
+            clk = host->freq_max;
+
+        temp = DIV_ROUND_UP(clk_src, 2 * clk);
+
+        if (temp > 0x3FF)
+            temp = 0x3FF;
+    }
+
+    if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
+        temp |= SDMMC_CLKCR_WIDBUS_0;
+    else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
+        temp |= SDMMC_CLKCR_WIDBUS_1;
+
+    hw_sdio->clkcr = temp;
+
+    if (io_cfg->power_mode == MMCSD_POWER_ON)
+        hw_sdio->power |= SDMMC_POWER_PWRCTRL;
+}
+
+static const struct rt_mmcsd_host_ops ops =
+{
+    rthw_sdio_request,
+    rthw_sdio_iocfg,
+    RT_NULL,
+    RT_NULL,
+};
+
+/**
+  * @brief  This function create mmcsd host.
+  * @param  sdio_des stm32_sdio_des
+  * @retval rt_mmcsd_host
+  */
+struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
+{
+    struct rt_mmcsd_host *host;
+    struct rthw_sdio *sdio = RT_NULL;
+
+    if (sdio_des == RT_NULL)
+    {
+        return RT_NULL;
+    }
+
+    sdio = rt_malloc(sizeof(struct rthw_sdio));
+
+    if (sdio == RT_NULL)
+    {
+        LOG_E("malloc rthw_sdio fail");
+        return RT_NULL;
+    }
+
+    rt_memset(sdio, 0, sizeof(struct rthw_sdio));
+
+    host = mmcsd_alloc_host();
+
+    if (host == RT_NULL)
+    {
+        LOG_E("alloc host fail");
+        goto err;
+    }
+
+    rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
+
+    if(sdio_des->hsd.Instance == SDMMC1)
+    {
+        sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO1_BASE_ADDRESS;
+        rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
+    }
+
+    if(sdio_des->hsd.Instance == SDMMC2)
+    {
+        sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO2_BASE_ADDRESS;
+        rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO);
+    }
+
+    /* set host default attributes */
+    host->ops = &ops;
+    host->freq_min = 400 * 1000;
+    host->freq_max = SDIO_MAX_FREQ;
+    host->valid_ocr = VDD_32_33 | VDD_33_34;/* The voltage range supported is 3.2v-3.4v */
+    host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED;
+    host->max_seg_size = SDIO_BUFF_SIZE;
+    host->max_dma_segs = 1;
+    host->max_blk_size = 512;
+    host->max_blk_count = 512;
+
+    /* link up host and sdio */
+    sdio->host = host;
+    host->private_data = sdio;
+
+    return host;
+
+err:
+
+    if (sdio) rt_free(sdio);
+
+    return RT_NULL;
+}
+
+void SDMMC1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* Process All SDIO Interrupt Sources */
+    rthw_sdio_irq_process(host1);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void SDMMC2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* Process All SDIO Interrupt Sources */
+    rthw_sdio_irq_process(host2);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+int rt_hw_sdio_init(void)
+{
+    #ifdef BSP_USING_SDIO1
+    struct stm32_sdio_des sdio_des1;
+    sdio_des1.hsd.Instance = SDMMC1;
+    HAL_SD_MspInit(&sdio_des1.hsd);
+
+    host1 = sdio_host_create(&sdio_des1);
+
+    if (host1 == RT_NULL)
+    {
+        LOG_E("host create fail");
+        return RT_NULL;
+    }
+
+    #endif
+
+    #ifdef BSP_USING_SDIO2
+    //sdmmc2 wifi
+    struct stm32_sdio_des sdio_des2;
+    sdio_des2.hsd.Instance = SDMMC2;
+    HAL_SD_MspInit(&sdio_des2.hsd);
+
+    host2 = sdio_host_create(&sdio_des2);
+
+    if (host2 == RT_NULL)
+    {
+        LOG_E("host2 create fail");
+        return RT_NULL;
+    }
+
+    /* wifi auto change */
+    mmcsd_change(host2);
+    #endif
+    mmcsd_mutex = rt_mutex_create("mmutex", RT_IPC_FLAG_FIFO);
+
+    if (mmcsd_mutex == RT_NULL)
+    {
+        rt_kprintf("create mmcsd mutex failed.\n");
+        return -1;
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_sdio_init);
+
+void sdcard_change(void)
+{
+    mmcsd_change(host1);
+}
+
+#endif /* RT_USING_SDIO */

bsp/stm32/stm32h750-artpi-h750/board/port/drv_sdio.h

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-05-23     liuduanfei   first version
+ * 2020-08-25     wanghaijing  add sdmmmc2
+ */
+
+#ifndef __DRV_SDIO_H__
+#define __DRV_SDIO_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+#include <string.h>
+#include <drivers/mmcsd_core.h>
+#include <drivers/sdio.h>
+
+#define SDIO_BUFF_SIZE       4096
+#define SDIO_ALIGN_LEN       32
+
+#ifndef SDIO1_BASE_ADDRESS
+#define SDIO1_BASE_ADDRESS    (0x52007000)
+#endif
+
+#ifndef SDIO2_BASE_ADDRESS
+#define SDIO2_BASE_ADDRESS    (0x48022400)
+#endif
+
+#ifndef SDIO_CLOCK_FREQ
+#define SDIO_CLOCK_FREQ      (200U * 1000 * 1000)
+#endif
+
+#ifndef SDIO_BUFF_SIZE
+#define SDIO_BUFF_SIZE       (4096)
+#endif
+
+#ifndef SDIO_ALIGN_LEN
+#define SDIO_ALIGN_LEN       (32)
+#endif
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ        (25 * 1000 * 1000)
+#endif
+
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+
+#define SDIO_ERRORS \
+    (SDMMC_STA_IDMATE | SDMMC_STA_ACKTIMEOUT | \
+     SDMMC_STA_RXOVERR | SDMMC_STA_TXUNDERR | \
+     SDMMC_STA_DTIMEOUT | SDMMC_STA_CTIMEOUT | \
+     SDMMC_STA_DCRCFAIL | SDMMC_STA_CCRCFAIL)
+
+#define SDIO_MASKR_ALL \
+    (SDMMC_MASK_CCRCFAILIE | SDMMC_MASK_DCRCFAILIE | SDMMC_MASK_CTIMEOUTIE | \
+     SDMMC_MASK_TXUNDERRIE | SDMMC_MASK_RXOVERRIE | SDMMC_MASK_CMDRENDIE | \
+     SDMMC_MASK_CMDSENTIE | SDMMC_MASK_DATAENDIE | SDMMC_MASK_ACKTIMEOUTIE)
+
+#define HW_SDIO_DATATIMEOUT                 (0xFFFFFFFFU)
+
+struct stm32_sdio
+{
+    volatile rt_uint32_t power;         /* offset 0x00 */
+    volatile rt_uint32_t clkcr;         /* offset 0x04 */
+    volatile rt_uint32_t arg;           /* offset 0x08 */
+    volatile rt_uint32_t cmd;           /* offset 0x0C */
+    volatile rt_uint32_t respcmd;       /* offset 0x10 */
+    volatile rt_uint32_t resp1;         /* offset 0x14 */
+    volatile rt_uint32_t resp2;         /* offset 0x18 */
+    volatile rt_uint32_t resp3;         /* offset 0x1C */
+    volatile rt_uint32_t resp4;         /* offset 0x20 */
+    volatile rt_uint32_t dtimer;        /* offset 0x24 */
+    volatile rt_uint32_t dlen;          /* offset 0x28 */
+    volatile rt_uint32_t dctrl;         /* offset 0x2C */
+    volatile rt_uint32_t dcount;        /* offset 0x30 */
+    volatile rt_uint32_t sta;           /* offset 0x34 */
+    volatile rt_uint32_t icr;           /* offset 0x38 */
+    volatile rt_uint32_t mask;          /* offset 0x3C */
+    volatile rt_uint32_t acktimer;      /* offset 0x40 */
+    volatile rt_uint32_t reserved0[3];  /* offset 0x44 ~ 0x4C */
+    volatile rt_uint32_t idmatrlr;      /* offset 0x50 */
+    volatile rt_uint32_t idmabsizer;    /* offset 0x54 */
+    volatile rt_uint32_t idmabase0r;    /* offset 0x58 */
+    volatile rt_uint32_t idmabase1r;    /* offset 0x5C */
+    volatile rt_uint32_t reserved1[8];  /* offset 0x60 ~ 7C */
+    volatile rt_uint32_t fifo;          /* offset 0x80 */
+};
+
+typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
+
+struct stm32_sdio_des
+{
+    struct stm32_sdio *hw_sdio;
+    sdio_clk_get clk_get;
+    SD_HandleTypeDef hsd;
+};
+
+/* stm32 sdio dirver class */
+struct stm32_sdio_class
+{
+    struct stm32_sdio_des *des;
+    const struct stm32_sdio_config *cfg;
+    struct rt_mmcsd_host host;
+};
+
+extern void sdcard_change(void);
+
+#endif /* __DRV_SDIO_H__ */

bsp/stm32/stm32h750-artpi-h750/board/port/drv_wlan.c

@@ -0,0 +1,215 @@
+/*
+ * File      : drv_wlan.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-30     ZeroFree     the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef RT_USING_WIFI
+
+#include <drv_common.h>
+#include <wlan_mgnt.h>
+#include <wlan_prot.h>
+#include <wlan_cfg.h>
+#include <string.h>
+#include <fal.h>
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME    "WLAN"
+#define DBG_COLOR
+#define DBG_LEVEL           DBG_LOG
+#include <rtdbg.h>
+
+#define NVRAM_GENERATED_MAC_ADDRESS      "macaddr=02:0A:F7:fe:86:1c"
+#define WIFI_IMAGE_PARTITION_NAME        "wifi_image"
+#define WIFI_INIT_THREAD_STACK_SIZE      (1024 * 4)
+#define WIFI_INIT_THREAD_PRIORITY        (RT_THREAD_PRIORITY_MAX/2)
+#define WIFI_INIT_WAIT_TIME              (rt_tick_from_millisecond(1000))
+
+extern int wifi_hw_init(void);
+static rt_bool_t init_flag = 0;
+static const struct fal_partition *partition = RT_NULL;
+
+ALIGN(64)
+static const char wifi_nvram_image[] =
+    // # The following parameter values are just placeholders, need to be updated.
+    "manfid=0x2d0"                                                       "\x00"
+    "prodid=0x0726"                                                      "\x00"
+    "vendid=0x14e4"                                                      "\x00"
+    "devid=0x43e2"                                                       "\x00"
+    "boardtype=0x0726"                                                   "\x00"
+    "boardrev=0x1101"                                                    "\x00"
+    "boardnum=22"                                                        "\x00"
+    "xtalfreq=26000"                                                     "\x00"
+    "sromrev=11"                                                         "\x00"
+    "boardflags=0x00404201"                                              "\x00"
+    "boardflags3=0x08000000"                                             "\x00"
+    NVRAM_GENERATED_MAC_ADDRESS                                          "\x00"
+    "nocrc=1"                                                            "\x00"
+    "ag0=255"                                                            "\x00"
+    "aa2g=1"                                                             "\x00"
+    "ccode=ALL"
+    "\x00"
+    "swdiv_en=1"                                                         "\x00"
+    "swdiv_gpio=2"                                                       "\x00"
+
+    "pa0itssit=0x20"                                                     "\x00"
+    "extpagain2g=0"                                                      "\x00"
+    "pa2ga0=-215,5267,-656"                                              "\x00"
+    "AvVmid_c0=0x0,0xc8"                                                 "\x00"
+    "cckpwroffset0=5"                                                    "\x00"
+    "maxp2ga0=80"                                                        "\x00"
+    "txpwrbckof=6"                                                       "\x00"
+    "cckbw202gpo=0x6666"                                                 "\x00"
+    "legofdmbw202gpo=0xaaaaaaaa"                                         "\x00"
+    "mcsbw202gpo=0xbbbbbbbb"                                             "\x00"
+    "propbw202gpo=0xdd"                                                  "\x00"
+    "ofdmdigfilttype=18"                                                 "\x00"
+    "ofdmdigfilttypebe=18"                                               "\x00"
+    "papdmode=1"                                                         "\x00"
+    "papdvalidtest=1"                                                    "\x00"
+    "pacalidx2g=32"                                                      "\x00"
+    "papdepsoffset=-36"                                                  "\x00"
+    "papdendidx=61"                                                      "\x00"
+    "wl0id=0x431b"                                                       "\x00"
+    "deadman_to=0xffffffff"                                              "\x00"
+    "muxenab=0x11"                                                        "\x00"
+    "spurconfig=0x3"                                                     "\x00"
+    "\x00\x00";
+
+int wiced_platform_resource_size(int resource)
+{
+    int size = 0;
+
+    /* Download firmware */
+    if (resource == 0)
+    {
+        size = 355159;
+    }
+    else if (resource == 1)
+    {
+        size = sizeof(wifi_nvram_image);
+    }
+
+    return size;
+}
+
+int wiced_platform_resource_read(int resource, uint32_t offset, void* buffer, uint32_t buffer_size)
+{
+    if (resource == 0)
+    {
+        /* read RF firmware from partition */
+        fal_partition_read(partition, offset, buffer, buffer_size);
+    }
+    else if (resource == 1)
+    {
+        memcpy(buffer, &wifi_nvram_image[offset], buffer_size);
+    }
+
+    return buffer_size;
+}
+
+/**
+ * wait milliseconds for wifi low level initialize complete
+ *
+ * time_ms: timeout in milliseconds
+ */
+int rt_hw_wlan_wait_init_done(rt_uint32_t time_ms)
+{
+    rt_uint32_t time_cnt = 0;
+
+    /* wait wifi low level initialize complete */
+    while (time_cnt <= (time_ms / 100))
+    {
+        time_cnt++;
+        rt_thread_mdelay(100);
+
+        if (init_flag == 1)
+        {
+            break;
+        }
+    }
+
+    if (time_cnt > (time_ms / 100))
+    {
+        return -RT_ETIMEOUT;
+    }
+
+    return RT_EOK;
+}
+
+
+static void wifi_init_thread_entry(void *parameter)
+{
+    /* initialize fal */
+    fal_init();
+    partition = fal_partition_find(WIFI_IMAGE_PARTITION_NAME);
+
+    if (partition == RT_NULL)
+    {
+        LOG_E("%s partition is not exist, please check your configuration!", WIFI_IMAGE_PARTITION_NAME);
+        return;
+    }
+
+    /* initialize low level wifi(ap6212) library */
+    wifi_hw_init();
+
+    /* waiting for sdio bus stability */
+    rt_thread_delay(WIFI_INIT_WAIT_TIME);
+
+    /* set wifi work mode */
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    /* NEED TODO !!! */
+    /* rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); */
+
+    init_flag = 1;
+}
+
+int rt_hw_wlan_init(void)
+{
+    if (init_flag == 1)
+    {
+        return RT_EOK;
+    }
+
+    rt_thread_t tid = RT_NULL;
+
+    tid = rt_thread_create("wifi_init", wifi_init_thread_entry, RT_NULL, WIFI_INIT_THREAD_STACK_SIZE, WIFI_INIT_THREAD_PRIORITY, 20);
+
+    if (tid)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        LOG_E("Create wifi initialization thread fail!");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(rt_hw_wlan_init);
+
+static int ap6212_init(void)
+{
+#define AP6212_WL_REG_ON    GET_PIN(C, 13)
+
+    /* enable the WLAN REG pin */
+    rt_pin_mode(AP6212_WL_REG_ON, PIN_MODE_OUTPUT);
+    rt_pin_write(AP6212_WL_REG_ON, PIN_HIGH);
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(ap6212_init);
+
+#endif /* RT_USING_WIFI */

bsp/stm32/stm32h750-artpi-h750/board/port/ef_fal_port.c

@@ -0,0 +1,208 @@
+/*
+ * This file is part of the EasyFlash Library.
+ *
+ * Copyright (c) 2015, Armink, <armink.ztl@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Function: Portable interface for FAL (Flash Abstraction Layer) partition.
+ * Created on: 2018-05-19
+ */
+
+#include <easyflash.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <sfud.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include <fal.h>
+
+/* EasyFlash partition name on FAL partition table */
+#define FAL_EF_PART_NAME               "easyflash"
+
+/* default ENV set for user */
+static const ef_env default_env_set[] = {
+        {"boot_times", "0"}
+};
+
+static char log_buf[RT_CONSOLEBUF_SIZE];
+static struct rt_semaphore env_cache_lock;
+static const struct fal_partition *part = NULL;
+
+/**
+ * Flash port for hardware initialize.
+ *
+ * @param default_env default ENV set for user
+ * @param default_env_size default ENV size
+ *
+ * @return result
+ */
+EfErrCode ef_port_init(ef_env const **default_env, size_t *default_env_size) {
+    EfErrCode result = EF_NO_ERR;
+
+    *default_env = default_env_set;
+    *default_env_size = sizeof(default_env_set) / sizeof(default_env_set[0]);
+
+    rt_sem_init(&env_cache_lock, "env lock", 1, RT_IPC_FLAG_PRIO);
+
+    part = fal_partition_find(FAL_EF_PART_NAME);
+    EF_ASSERT(part);
+
+    return result;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_read(uint32_t addr, uint32_t *buf, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    fal_partition_read(part, addr, (uint8_t *)buf, size);
+
+    return result;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_erase(uint32_t addr, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    /* make sure the start address is a multiple of FLASH_ERASE_MIN_SIZE */
+    EF_ASSERT(addr % EF_ERASE_MIN_SIZE == 0);
+
+    if (fal_partition_erase(part, addr, size) < 0)
+    {
+        result = EF_ERASE_ERR;
+    }
+
+    return result;
+}
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_write(uint32_t addr, const uint32_t *buf, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    if (fal_partition_write(part, addr, (uint8_t *)buf, size) < 0)
+    {
+        result = EF_WRITE_ERR;
+    }
+
+    return result;
+}
+
+/**
+ * lock the ENV ram cache
+ */
+void ef_port_env_lock(void) {
+    rt_sem_take(&env_cache_lock, RT_WAITING_FOREVER);
+}
+
+/**
+ * unlock the ENV ram cache
+ */
+void ef_port_env_unlock(void) {
+    rt_sem_release(&env_cache_lock);
+}
+
+/**
+ * This function is print flash debug info.
+ *
+ * @param file the file which has call this function
+ * @param line the line number which has call this function
+ * @param format output format
+ * @param ... args
+ *
+ */
+void ef_log_debug(const char *file, const long line, const char *format, ...) {
+
+#ifdef PRINT_DEBUG
+
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    ef_print("[Flash] (%s:%ld) ", file, line);
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    ef_print("%s", log_buf);
+    va_end(args);
+
+#endif
+
+}
+
+/**
+ * This function is print flash routine info.
+ *
+ * @param format output format
+ * @param ... args
+ */
+void ef_log_info(const char *format, ...) {
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    ef_print("[Flash] ");
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    ef_print("%s", log_buf);
+    va_end(args);
+}
+/**
+ * This function is print flash non-package info.
+ *
+ * @param format output format
+ * @param ... args
+ */
+void ef_print(const char *format, ...) {
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    rt_kprintf("%s", log_buf);
+    va_end(args);
+}

bsp/stm32/stm32h750-artpi-h750/board/port/fal_cfg.h

@@ -0,0 +1,54 @@
+/*
+ * File      : fal_cfg.h
+ * This file is part of FAL (Flash Abstraction Layer) package
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-17     armink       the first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#define NOR_FLASH_DEV_NAME             "norflash0"
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                     \
+{                                                                                          \
+    {FAL_PART_MAGIC_WORD, "wifi_image", NOR_FLASH_DEV_NAME,           0,     512*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "bt_image",   NOR_FLASH_DEV_NAME,    512*1024,     512*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "download",   NOR_FLASH_DEV_NAME,   1024*1024,  2*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash",  NOR_FLASH_DEV_NAME, 3*1024*1024,  1*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */

bsp/stm32/stm32h750-artpi-h750/board/port/filesystem.c

@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2018-12-13     balanceTWK    add sdcard port file
+ * 2019-06-11     WillianChan   Add SD card hot plug detection
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_FS
+#if DFS_FILESYSTEMS_MAX < 4
+    #error "Please define DFS_FILESYSTEMS_MAX more than 4"
+#endif
+#if DFS_FILESYSTEM_TYPES_MAX < 4
+    #error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4"
+#endif
+
+#include <dfs_fs.h>
+#include "dfs_romfs.h"
+#ifdef BSP_USING_SDCARD_FS
+    #include <board.h>
+    #include "drv_sdio.h"
+#endif
+#ifdef BSP_USING_SPI_FLASH_FS
+    #include "fal.h"
+#endif
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+static const struct romfs_dirent _romfs_root[] =
+{
+    {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0},
+    {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}
+};
+
+const struct romfs_dirent romfs_root =
+{
+    ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])
+};
+
+#ifdef BSP_USING_SDCARD_FS
+
+/* SD Card hot plug detection pin */
+#define SD_CHECK_PIN GET_PIN(D, 5)
+
+static void _sdcard_mount(void)
+{
+    rt_device_t device;
+
+    device = rt_device_find("sd0");
+
+    if (device == NULL)
+    {
+        mmcsd_wait_cd_changed(0);
+        sdcard_change();
+        mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
+        device = rt_device_find("sd0");
+    }
+
+    if (device != RT_NULL)
+    {
+        if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK)
+        {
+            LOG_I("sd card mount to '/sdcard'");
+        }
+        else
+        {
+            LOG_W("sd card mount to '/sdcard' failed!");
+        }
+    }
+}
+
+static void _sdcard_unmount(void)
+{
+    rt_thread_mdelay(200);
+    dfs_unmount("/sdcard");
+    LOG_I("Unmount \"/sdcard\"");
+
+    mmcsd_wait_cd_changed(0);
+    sdcard_change();
+    mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
+}
+
+static void sd_mount(void *parameter)
+{
+    rt_uint8_t re_sd_check_pin = 1;
+    rt_thread_mdelay(200);
+
+    if (rt_pin_read(SD_CHECK_PIN))
+    {
+        _sdcard_mount();
+    }
+
+    while (1)
+    {
+        rt_thread_mdelay(200);
+
+        if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0)
+        {
+            _sdcard_mount();
+        }
+
+        if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) == 0)
+        {
+            _sdcard_unmount();
+        }
+    }
+}
+
+#endif /* BSP_USING_SDCARD_FS */
+
+int mount_init(void)
+{
+    if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0)
+    {
+        LOG_E("rom mount to '/' failed!");
+    }
+
+    #ifdef BSP_USING_SPI_FLASH_FS
+    struct rt_device *flash_dev = RT_NULL;
+
+    #ifndef RT_USING_WIFI
+    fal_init();
+    #endif
+
+    flash_dev = fal_mtd_nor_device_create("filesystem");
+
+    if (flash_dev)
+    {
+        //mount filesystem
+        if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) != 0)
+        {
+            LOG_W("mount to '/flash' failed! try to mkfs %s", flash_dev->parent.name);
+            dfs_mkfs("lfs", flash_dev->parent.name);
+
+            if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) == 0)
+            {
+                LOG_I("mount to '/flash' success!");
+            }
+        }
+        else
+        {
+            LOG_I("mount to '/flash' success!");
+        }
+    }
+    else
+    {
+        LOG_E("Can't create  block device  filesystem or bt_image partition.");
+    }
+
+    #endif
+
+    #ifdef BSP_USING_SDCARD_FS
+    rt_thread_t tid;
+
+    rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
+
+    tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+                           2048, RT_THREAD_PRIORITY_MAX - 2, 20);
+
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        LOG_E("create sd_mount thread err!");
+    }
+
+    #endif
+    return RT_EOK;
+}
+INIT_APP_EXPORT(mount_init);
+
+#endif /* BSP_USING_FS */

bsp/stm32/stm32h750-artpi-h750/board/port/lcd_port.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-08     zylx         first version
+ */
+
+#ifndef __LCD_PORT_H__
+#define __LCD_PORT_H__
+
+/* atk 4.3 inch screen, 800 * 480 */
+
+
+#define LCD_WIDTH           800
+#define LCD_HEIGHT          480
+#define LCD_BITS_PER_PIXEL  16
+#define LCD_BUF_SIZE        (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
+#define LCD_PIXEL_FORMAT    RTGRAPHIC_PIXEL_FORMAT_RGB565
+
+#define LCD_HSYNC_WIDTH     1
+#define LCD_VSYNC_HEIGHT    1
+#define LCD_HBP             40
+#define LCD_VBP             32
+#define LCD_HFP             48
+#define LCD_VFP             13
+
+#define LCD_BACKLIGHT_USING_GPIO
+#define LCD_BL_GPIO_NUM     GET_PIN(D, 4)
+#define LCD_DISP_GPIO_NUM   GET_PIN(B, 5)
+/* atk 4.3 inch screen, 800 * 480 */
+
+#endif /* __LCD_PORT_H__ */

bsp/stm32/stm32h750-artpi-h750/board/port/lcd_spi_port.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-10     zylx         first version
+ */
+
+#ifndef __LCD_PORT_H__
+#define __LCD_PORT_H__
+
+/* rt-thread 3.5 inch screen, 320 * 480 */
+#define LCD_HOR_SCREEN
+#define LCD_FULL_COLOR      BLACK
+
+#ifndef LCD_FULL_COLOR
+#define LCD_FULL_COLOR      WHITE
+#endif
+
+#ifndef LCD_HOR_SCREEN
+#define LCD_WIDTH           320
+#define LCD_HEIGHT          480
+#else
+#define LCD_WIDTH           480
+#define LCD_HEIGHT          320
+#endif
+#define LCD_BITS_PER_PIXEL  24
+#define LCD_BYTES_PER_PIXEL  (LCD_BITS_PER_PIXEL / 8)
+#define LCD_BUF_SIZE        (LCD_WIDTH * LCD_HEIGHT * LCD_BYTES_PER_PIXEL)
+#define LCD_PIXEL_FORMAT    RTGRAPHIC_PIXEL_FORMAT_RGB888
+
+#define LCD_BACKLIGHT_USING_GPIO
+#define LCD_BL_PIN          GET_PIN(C, 6)
+#define LCD_RES_PIN         GET_PIN(A, 3)
+/* rt-thread 3.5 inch screen, 320 * 480 */
+
+#endif /* __LCD_PORT_H__ */

bsp/stm32/stm32h750-artpi-h750/board/port/sdram_port.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-04     zylx         The first version for STM32F4xx
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+/* Bank1 or Bank2 */
+#define SDRAM_TARGET_BANK               1
+/* stm32h7 Bank1:0XC0000000  Bank2:0XD0000000 */
+#define SDRAM_BANK_ADDR                 ((uint32_t)0XC0000000)
+/* data width: 8, 16, 32 */
+#define SDRAM_DATA_WIDTH                16
+/* column bit numbers: 8, 9, 10, 11 */
+#define SDRAM_COLUMN_BITS               9
+/* row bit numbers: 11, 12, 13 */
+#define SDRAM_ROW_BITS                  13
+/* cas latency clock number: 1, 2, 3 */
+#define SDRAM_CAS_LATENCY               2
+/* read pipe delay: 0, 1, 2 */
+#define SDRAM_RPIPE_DELAY               0
+/* clock divid: 2, 3 */
+#define SDCLOCK_PERIOD                  2
+/* refresh rate counter */
+#define SDRAM_REFRESH_COUNT             ((uint32_t)0x02A5)
+#define SDRAM_SIZE                      ((uint32_t)0x2000000)
+
+/* Timing configuration for W9825G6KH-6 */
+/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
+/* TMRD: 2 Clock cycles */
+#define LOADTOACTIVEDELAY               2
+/* TXSR: 8x10ns */
+#define EXITSELFREFRESHDELAY            8
+/* TRAS: 5x10ns */
+#define SELFREFRESHTIME                 6
+/* TRC:  7x10ns */
+#define ROWCYCLEDELAY                   6
+/* TWR:  2 Clock cycles */
+#define WRITERECOVERYTIME               2
+/* TRP:  2x10ns */
+#define RPDELAY                         2
+/* TRCD: 2x10ns */
+#define RCDDELAY                        2
+
+/* memory mode register */
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)
+
+#endif

bsp/stm32/stm32h750-artpi-h750/board/port/spi_flash_init.c

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-11-07     wanghaijing  the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <spi_flash.h>
+#include <drv_spi.h>
+
+static int rt_flash_init(void)
+{
+    extern rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const char *spi_dev_name);
+    extern int fal_init(void);
+
+    rt_hw_spi_device_attach("spi1", "spi10", GPIOA, GPIO_PIN_4);
+
+    /* initialize SPI Flash device */
+    rt_sfud_flash_probe("norflash0", "spi10");
+
+    fal_init();
+
+    return 0;
+}
+INIT_ENV_EXPORT(rt_flash_init);

bsp/stm32/stm32h750-artpi-h750/board/port/wifi_config.c

@@ -0,0 +1,263 @@
+/*
+ * File      : wifi_config.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-09-04     ZeroFree     first implementation
+ * 2019-06-14     armink       add easyflash v4.0 support
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_WIFI
+
+#include <wlan_mgnt.h>
+#include <wlan_cfg.h>
+#include <wlan_prot.h>
+
+#include <easyflash.h>
+#include <fal.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#if (EF_SW_VERSION_NUM < 0x40000)
+
+static char *str_base64_encode_len(const void *src, char *out, int input_length);
+static int   str_base64_decode(const char *data, int input_length, char *decoded_data);
+
+static const unsigned char base64_table[65] =
+    "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/";
+
+static const char base64_decode_table[256] =
+{
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x3F,
+    0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E,
+    0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28,
+    0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static char *str_base64_encode_len(const void *src, char *out, int len)
+{
+    unsigned char *pos;
+    const unsigned char *end, *in;
+    size_t olen;
+
+    olen = len * 4 / 3 + 4; /* 3-byte blocks to 4-byte */
+    olen += olen / 72; /* line feeds */
+    olen++; /* nul termination */
+
+    end = (const unsigned char *)src + len;
+    in = (const unsigned char *)src;
+    pos = (unsigned char *)out;
+    while (end - in >= 3)
+    {
+        *pos++ = base64_table[in[0] >> 2];
+        *pos++ = base64_table[((in[0] & 0x03) << 4) | (in[1] >> 4)];
+        *pos++ = base64_table[((in[1] & 0x0f) << 2) | (in[2] >> 6)];
+        *pos++ = base64_table[in[2] & 0x3f];
+        in += 3;
+    }
+
+    if (end - in)
+    {
+        *pos++ = base64_table[in[0] >> 2];
+
+        if (end - in == 1)
+        {
+            *pos++ = base64_table[(in[0] & 0x03) << 4];
+            *pos++ = '=';
+        }
+        else
+        {
+            *pos++ = base64_table[((in[0] & 0x03) << 4) |
+                                                  (in[1] >> 4)];
+            *pos++ = base64_table[(in[1] & 0x0f) << 2];
+        }
+        *pos++ = '=';
+    }
+
+    *pos = '\0';
+    return (char *)out;
+}
+
+/*
+ * return: length, 0 is error.
+ */
+static int str_base64_decode(const char *data, int input_length, char *decoded_data)
+{
+    int out_len;
+    int i, j;
+
+    if (input_length % 4 != 0) return 0;
+
+    out_len = input_length / 4 * 3;
+
+    if (data[input_length - 1] == '=') out_len--;
+    if (data[input_length - 2] == '=') out_len--;
+
+    for (i = 0, j = 0; i < input_length;)
+    {
+        uint32_t sextet_a = data[i] == '=' ? 0 & i++ : base64_decode_table[data[i++]];
+        uint32_t sextet_b = data[i] == '=' ? 0 & i++ : base64_decode_table[data[i++]];
+        uint32_t sextet_c = data[i] == '=' ? 0 & i++ : base64_decode_table[data[i++]];
+        uint32_t sextet_d = data[i] == '=' ? 0 & i++ : base64_decode_table[data[i++]];
+
+        uint32_t triple = (sextet_a << 3 * 6)
+                          + (sextet_b << 2 * 6)
+                          + (sextet_c << 1 * 6)
+                          + (sextet_d << 0 * 6);
+
+        if (j < out_len) decoded_data[j++] = (triple >> 2 * 8) & 0xFF;
+        if (j < out_len) decoded_data[j++] = (triple >> 1 * 8) & 0xFF;
+        if (j < out_len) decoded_data[j++] = (triple >> 0 * 8) & 0xFF;
+    }
+
+    return out_len;
+}
+
+static int read_cfg(void *buff, int len)
+{
+    char *wlan_cfg_info = RT_NULL;
+
+    wlan_cfg_info = ef_get_env("wlan_cfg_info");
+    if (wlan_cfg_info != RT_NULL)
+    {
+        str_base64_decode(wlan_cfg_info, rt_strlen(wlan_cfg_info), buff);
+        return len;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+static int get_len(void)
+{
+    int len;
+    char *wlan_cfg_len = RT_NULL;
+
+    wlan_cfg_len = ef_get_env("wlan_cfg_len");
+    if (wlan_cfg_len == RT_NULL)
+    {
+        len = 0;
+    }
+    else
+    {
+        len = atoi(wlan_cfg_len);
+    }
+
+    return len;
+}
+
+static int write_cfg(void *buff, int len)
+{
+    char wlan_cfg_len[12] = {0};
+    char *base64_buf = RT_NULL;
+
+    base64_buf = rt_malloc(len * 4 / 3 + 4); /* 3-byte blocks to 4-byte, and the end. */
+    if (base64_buf == RT_NULL)
+    {
+        return -RT_ENOMEM;
+    }
+    rt_memset(base64_buf, 0, len);
+
+    /* interger to string */
+    sprintf(wlan_cfg_len, "%d", len);
+    /* set and store the wlan config lengths to Env */
+    ef_set_env("wlan_cfg_len", wlan_cfg_len);
+    str_base64_encode_len(buff, base64_buf, len);
+    /* set and store the wlan config information to Env */
+    ef_set_env("wlan_cfg_info", base64_buf);
+    ef_save_env();
+    rt_free(base64_buf);
+
+    return len;
+}
+
+#else
+
+static int read_cfg(void *buff, int len)
+{
+    size_t saved_len;
+
+    ef_get_env_blob("wlan_cfg_info", buff, len, &saved_len);
+    if (saved_len == 0)
+    {
+        return 0;
+    }
+    return len;
+}
+
+static int get_len(void)
+{
+    int len;
+    size_t saved_len;
+
+    ef_get_env_blob("wlan_cfg_len", &len, sizeof(len), &saved_len);
+    if (saved_len == 0)
+    {
+        return 0;
+    }
+
+    return len;
+}
+
+static int write_cfg(void *buff, int len)
+{
+    /* set and store the wlan config lengths to Env */
+    ef_set_env_blob("wlan_cfg_len", &len, sizeof(len));
+
+    /* set and store the wlan config information to Env */
+    ef_set_env_blob("wlan_cfg_info", buff, len);
+
+    return len;
+}
+
+#endif /* (EF_SW_VERSION_NUM < 0x40000) */
+
+static const struct rt_wlan_cfg_ops ops =
+{
+    read_cfg,
+    get_len,
+    write_cfg
+};
+
+void wlan_autoconnect_init(void)
+{
+    fal_init();
+    easyflash_init();
+
+    rt_wlan_cfg_set_ops(&ops);
+    rt_wlan_cfg_cache_refresh();
+}
+
+#endif

bsp/stm32/stm32h750-artpi-h750/board/port/wlan_wiced_lib/SConscript

@@ -0,0 +1,20 @@
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+LIBS    = []
+LIBPATH = []
+src = []
+
+LIBPATH = [cwd]
+if rtconfig.CROSS_TOOL == 'gcc':
+    LIBS += ['wifi_6212_armcm7_2.1.2_gcc']
+elif rtconfig.CROSS_TOOL == 'keil':
+    LIBS += ['libwifi_6212_armcm7_2.1.2_armcc']
+
+path = [cwd]
+
+group = DefineGroup('WICED', src, depend = ['ART_PI_USING_WIFI_6212_LIB'], CPPPATH = path, LIBS = LIBS, LIBPATH = LIBPATH)
+
+Return('group')

bsp/wch/arm/Libraries/ch32_drivers/SConscript

@@ -32,6 +32,9 @@ if  GetDepend('SOC_ARM_SERIES_CH32F103'):
     if GetDepend(['RT_USING_HWTIMER', 'BSP_USING_HWTIMER']):
         src += ['drv_hwtimer_ch32f10x.c']
 
+    if GetDepend(['RT_USING_PWM', 'BSP_USING_PWM']):
+        src += ['drv_pwm_ch32f10x.c']
+
 src += ['drv_common.c']
 
 path =  [cwd]

bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f10x.c

@@ -73,17 +73,16 @@ static void ch32f1_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t st
 
     if (state)
     {
-        ch32f1_hwtimer_clock_init(hwtimer_dev->periph);
+        ch32f1_tim_clock_init(hwtimer_dev->periph);
 
         hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_dev->periph);
 
-        clk = ch32f1_hwtimer_clock_get(hwtimer_dev->periph);
+        clk = ch32f1_tim_clock_get(hwtimer_dev->periph);
 
         prescaler_value = (rt_uint16_t)(clk / hwtimer_info->minfreq) - 1;
 
         /*
-        * set interrupt callback one or each time need total time =
-        *  (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
+        * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
         */
 
         TIM_TimeBaseInitType.TIM_Period = hwtimer_info->maxcnt - 1;
@@ -132,8 +131,7 @@ static rt_err_t ch32f1_hwtimer_start(struct rt_hwtimer_device *device, rt_uint32
     hwtimer_dev = (struct hwtimer_device *)device;
 
     /*
-    * interrupt callback one or each time need total time =
-    *  (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
+    * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
     */
 
     TIM_SetCounter(hwtimer_dev->periph, 0);
@@ -197,15 +195,14 @@ static rt_err_t ch32f1_hwtimer_control(struct rt_hwtimer_device *device, rt_uint
         rt_uint16_t prescaler_value = 0;
 
         /*
-        *set interrupt callback one or each time need total time =
-        *  (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
+        * (1 / freq) = (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
         */
         if (arg != RT_NULL)
         {
 
             freq = *((rt_uint32_t *)arg);
 
-            clk = ch32f1_hwtimer_clock_get(hwtimer_dev->periph);
+            clk = ch32f1_tim_clock_get(hwtimer_dev->periph);
 
             prescaler_value = (rt_uint16_t)(clk / freq) - 1;
 
@@ -369,4 +366,3 @@ void TIM4_IRQHandler(void)
 #endif
 
 #endif /* BSP_USING_HWTIMER */
-

bsp/wch/arm/Libraries/ch32_drivers/drv_pwm_ch32f10x.c

@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-09-23     charlown           first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef BSP_USING_PWM
+
+#define LOG_TAG "drv.pwm"
+#include <drv_log.h>
+
+#ifndef ITEM_NUM
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+#endif
+
+#define MAX_COUNTER 65535
+#define MIN_COUNTER 2
+#define MIN_PULSE 2
+
+struct rtdevice_pwm_device
+{
+  struct rt_device_pwm parent;
+  TIM_TypeDef *periph;
+  rt_uint8_t channel[4];
+  char *name;
+};
+
+/*
+* channel = 0xFF: the channel is not use.
+*/
+struct rtdevice_pwm_device pwm_device_list[] =
+    {
+#ifdef BSP_USING_TIM1_PWM
+        {
+            .periph = TIM1,
+            .name = "pwm1",
+#ifdef BSP_USING_TIM1_PWM_CH1
+            .channel[0] = TIM_Channel_1,
+#else
+            .channel[0] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM1_PWM_CH2
+            .channel[1] = TIM_Channel_2,
+#else
+            .channel[1] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM1_PWM_CH3
+            .channel[2] = TIM_Channel_3,
+#else
+            .channel[2] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM1_PWM_CH4
+            .channel[3] = TIM_Channel_4,
+#else
+            .channel[3] = 0xFF,
+#endif
+        },
+#endif
+
+#ifdef BSP_USING_TIM2_PWM
+        {
+            .periph = TIM2,
+            .name = "pwm2",
+#ifdef BSP_USING_TIM2_PWM_CH1
+            .channel[0] = TIM_Channel_1,
+#else
+            .channel[0] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM2_PWM_CH2
+            .channel[1] = TIM_Channel_2,
+#else
+            .channel[1] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM2_PWM_CH3
+            .channel[2] = TIM_Channel_3,
+#else
+            .channel[2] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM2_PWM_CH4
+            .channel[3] = TIM_Channel_4,
+#else
+            .channel[3] = 0xFF,
+#endif
+        },
+#endif
+
+#ifdef BSP_USING_TIM3_PWM
+        {
+            .periph = TIM3,
+            .name = "pwm3",
+#ifdef BSP_USING_TIM3_PWM_CH1
+            .channel[0] = TIM_Channel_1,
+#else
+            .channel[0] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM3_PWM_CH2
+            .channel[1] = TIM_Channel_2,
+#else
+            .channel[1] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM3_PWM_CH3
+            .channel[2] = TIM_Channel_3,
+#else
+            .channel[2] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM3_PWM_CH4
+            .channel[3] = TIM_Channel_4,
+#else
+            .channel[3] = 0xFF,
+#endif
+        },
+#endif
+
+#ifdef BSP_USING_TIM4_PWM
+        {
+            .periph = TIM4,
+            .name = "pwm4",
+#ifdef BSP_USING_TIM4_PWM_CH1
+            .channel[0] = TIM_Channel_1,
+#else
+            .channel[0] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM4_PWM_CH2
+            .channel[1] = TIM_Channel_2,
+#else
+            .channel[1] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM4_PWM_CH3
+            .channel[2] = TIM_Channel_3,
+#else
+            .channel[2] = 0xFF,
+#endif
+
+#ifdef BSP_USING_TIM4_PWM_CH4
+            .channel[3] = TIM_Channel_4,
+#else
+            .channel[3] = 0xFF,
+#endif
+        },
+#endif
+};
+
+static rt_err_t ch32f1_pwm_device_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+  struct rtdevice_pwm_device *pwm_device;
+  rt_uint32_t channel_index;
+  rt_uint16_t ccx_state;
+
+  pwm_device = (struct rtdevice_pwm_device *)device;
+  channel_index = configuration->channel;
+
+  if (enable == RT_TRUE)
+  {
+    ccx_state = TIM_CCx_Enable;
+  }
+  else
+  {
+    ccx_state = TIM_CCx_Disable;
+  }
+
+  if (channel_index <= 4 && channel_index > 0)
+  {
+    if (pwm_device->channel[channel_index - 1] == 0xFF)
+      return RT_EINVAL;
+
+    TIM_CCxCmd(pwm_device->periph, pwm_device->channel[channel_index - 1], ccx_state);
+  }
+  else
+  {
+    return RT_EINVAL;
+  }
+
+  TIM_Cmd(pwm_device->periph, ENABLE);
+
+  return RT_EOK;
+}
+
+static rt_err_t ch32f1_pwm_device_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+  struct rtdevice_pwm_device *pwm_device;
+  rt_uint32_t arr_counter, ccr_counter, prescaler, sample_freq;
+  rt_uint32_t channel_index;
+  rt_uint32_t tim_clock;
+
+  pwm_device = (struct rtdevice_pwm_device *)device;
+
+  tim_clock = ch32f1_tim_clock_get(pwm_device->periph);
+  channel_index = configuration->channel;
+  arr_counter = pwm_device->periph->ATRLR + 1;
+  prescaler = pwm_device->periph->PSC + 1;
+
+  sample_freq = (tim_clock / prescaler) / arr_counter;
+
+  /* unit:ns */
+  configuration->period = 1000000000 / sample_freq;
+
+  if (channel_index == 1)
+  {
+    ccr_counter = pwm_device->periph->CH1CVR + 1;
+    configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
+  }
+  else if (channel_index == 2)
+  {
+    ccr_counter = pwm_device->periph->CH2CVR + 1;
+    configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
+  }
+  else if (channel_index == 3)
+  {
+    ccr_counter = pwm_device->periph->CH3CVR + 1;
+    configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
+  }
+  else if (channel_index == 4)
+  {
+    ccr_counter = pwm_device->periph->CH4CVR + 1;
+    configuration->pulse = ((ccr_counter * 100) / arr_counter) * configuration->period / 100;
+  }
+  else
+    return RT_EINVAL;
+
+  return RT_EOK;
+}
+
+static rt_err_t ch32f1_pwm_device_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+  struct rtdevice_pwm_device *pwm_device;
+  rt_uint32_t arr_counter, ccr_counter, prescaler, sample_freq;
+  rt_uint32_t channel_index;
+  rt_uint32_t tim_clock;
+
+  TIM_TimeBaseInitTypeDef TIM_TimeBaseInitType;
+  TIM_OCInitTypeDef TIM_OCInitType;
+
+  pwm_device = (struct rtdevice_pwm_device *)device;
+
+  tim_clock = ch32f1_tim_clock_get(pwm_device->periph);
+
+  channel_index = configuration->channel;
+
+  /* change to freq, unit:Hz */
+  sample_freq = 1000000000 / configuration->period;
+
+  /*counter = (tim_clk / prescaler) / sample_freq */
+  /*normally, tim_clk is not need div, if arr_counter over 65536, need div.*/
+  prescaler = 1;
+
+  arr_counter = (tim_clock / prescaler) / sample_freq;
+
+  if (arr_counter > MAX_COUNTER)
+  {
+    /* need div tim_clock
+    * and round up the prescaler value.
+    * (tim_clock >> 16) = tim_clock / 65536
+    */
+    if ((tim_clock >> 16) % sample_freq == 0)
+      prescaler = (tim_clock >> 16) / sample_freq;
+    else
+      prescaler = (tim_clock >> 16) / sample_freq + 1;
+
+    /*counter = (tim_clk / prescaler) / sample_freq */
+    arr_counter = (tim_clock / prescaler) / sample_freq;
+  }
+  /* ccr_counter = duty cycle * arr_counter */
+  ccr_counter = (configuration->pulse * 100 / configuration->period) * arr_counter / 100;
+
+  /* check arr_counter > 1, cxx_counter > 1 */
+  if (arr_counter < MIN_COUNTER)
+  {
+    arr_counter = MIN_COUNTER;
+  }
+
+  if (ccr_counter < MIN_PULSE)
+  {
+    ccr_counter = MIN_PULSE;
+  }
+
+  /* TMRe base configuration */
+  TIM_TimeBaseStructInit(&TIM_TimeBaseInitType);
+  TIM_TimeBaseInitType.TIM_Period = arr_counter - 1;
+  TIM_TimeBaseInitType.TIM_Prescaler = prescaler - 1;
+  TIM_TimeBaseInitType.TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up;
+
+  TIM_TimeBaseInit(pwm_device->periph, &TIM_TimeBaseInitType);
+
+
+  TIM_OCStructInit(&TIM_OCInitType);
+  TIM_OCInitType.TIM_OCMode = TIM_OCMode_PWM1;
+  TIM_OCInitType.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitType.TIM_Pulse = ccr_counter - 1;
+  TIM_OCInitType.TIM_OCPolarity = TIM_OCPolarity_High;
+
+  if (channel_index == 1)
+  {
+    TIM_OC1Init(pwm_device->periph, &TIM_OCInitType);
+    TIM_OC1PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
+  }
+  else if (channel_index == 2)
+  {
+    TIM_OC2Init(pwm_device->periph, &TIM_OCInitType);
+    TIM_OC2PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
+  }
+  else if (channel_index == 3)
+  {
+    TIM_OC3Init(pwm_device->periph, &TIM_OCInitType);
+    TIM_OC3PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
+  }
+  else if (channel_index == 4)
+  {
+    TIM_OC4Init(pwm_device->periph, &TIM_OCInitType);
+    TIM_OC4PreloadConfig(pwm_device->periph, TIM_OCPreload_Disable);
+  }
+  else
+  {
+    return RT_EINVAL;
+  }
+
+  TIM_ARRPreloadConfig(pwm_device->periph, ENABLE);
+  TIM_CtrlPWMOutputs(pwm_device->periph, ENABLE);
+
+  return RT_EOK;
+}
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+  struct rt_pwm_configuration *configuration;
+
+  configuration = (struct rt_pwm_configuration *)arg;
+
+  switch (cmd)
+  {
+  case PWM_CMD_ENABLE:
+    return ch32f1_pwm_device_enable(device, configuration, RT_TRUE);
+  case PWM_CMD_DISABLE:
+    return ch32f1_pwm_device_enable(device, configuration, RT_FALSE);
+  case PWM_CMD_SET:
+    return ch32f1_pwm_device_set(device, configuration);
+  case PWM_CMD_GET:
+    return ch32f1_pwm_device_get(device, configuration);
+  default:
+    return RT_EINVAL;
+  }
+}
+
+static struct rt_pwm_ops pwm_ops =
+    {
+        .control = drv_pwm_control};
+
+static int rt_hw_pwm_init(void)
+{
+  int result = RT_EOK;
+  int index = 0;
+  int channel_index;
+
+  for (index = 0; index < ITEM_NUM(pwm_device_list); index++)
+  {
+    ch32f1_tim_clock_init(pwm_device_list[index].periph);
+    for (channel_index = 0; channel_index < sizeof(pwm_device_list[index].channel); channel_index++)
+    {
+      if (pwm_device_list[index].channel[channel_index] != 0xFF)
+      {
+        ch32f1_pwm_io_init(pwm_device_list[index].periph, pwm_device_list[index].channel[channel_index]);
+      }
+    }
+
+    if (rt_device_pwm_register(&pwm_device_list[index].parent, pwm_device_list[index].name, &pwm_ops, RT_NULL) == RT_EOK)
+    {
+      LOG_D("%s register success", pwm_device_list[index].name);
+    }
+    else
+    {
+      LOG_D("%s register failed", pwm_device_list[index].name);
+      result = -RT_ERROR;
+    }
+  }
+
+  return result;
+}
+
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
+
+#endif /* BSP_USING_PWM */

bsp/wch/arm/ch32f103c8-core/board/Kconfig

@@ -116,18 +116,18 @@ config BSP_USING_TIM
 
                         if BSP_USING_TIM1_PWM
                                 config BSP_USING_TIM1_PWM_CH1
-                                        bool "using TIM1 channel 1 as pwm"
+                                        bool "using TIM1 channel 1"
                                         default n
 
                                 config BSP_USING_TIM1_PWM_CH2
-                                        bool "using TIM1 channel 2 as pwm"
+                                        bool "using TIM1 channel 2"
                                         default n
 
                                 config BSP_USING_TIM1_PWM_CH3
-                                        bool "using TIM1 channel 3 as pwm"
+                                        bool "using TIM1 channel 3"
 
                                 config BSP_USING_TIM1_PWM_CH4
-                                        bool "using TIM1 channel 4 as pwm"
+                                        bool "using TIM1 channel 4"
 
                         endif
 
@@ -154,18 +154,18 @@ config BSP_USING_TIM
 
                         if BSP_USING_TIM2_PWM
                                 config BSP_USING_TIM2_PWM_CH1
-                                        bool "using TIM2 channel 1 as pwm"
+                                        bool "using TIM2 channel 1"
                                         default n
 
                                 config BSP_USING_TIM2_PWM_CH2
-                                        bool "using TIM2 channel 2 as pwm"
+                                        bool "using TIM2 channel 2"
                                         default n
 
                                 config BSP_USING_TIM2_PWM_CH3
-                                        bool "using TIM2 channel 3 as pwm"
+                                        bool "using TIM2 channel 3"
 
                                 config BSP_USING_TIM2_PWM_CH4
-                                        bool "using TIM2 channel 4 as pwm"
+                                        bool "using TIM2 channel 4"
 
                         endif
 
@@ -192,18 +192,18 @@ config BSP_USING_TIM
 
                         if BSP_USING_TIM3_PWM
                                 config BSP_USING_TIM3_PWM_CH1
-                                        bool "using TIM3 channel 1 as pwm"
+                                        bool "using TIM3 channel 1"
                                         default n
 
                                 config BSP_USING_TIM3_PWM_CH2
-                                        bool "using TIM3 channel 2 as pwm"
+                                        bool "using TIM3 channel 2"
                                         default n
 
                                 config BSP_USING_TIM3_PWM_CH3
-                                        bool "using TIM3 channel 3 as pwm"
+                                        bool "using TIM3 channel 3"
 
                                 config BSP_USING_TIM3_PWM_CH4
-                                        bool "using TIM3 channel 4 as pwm"
+                                        bool "using TIM3 channel 4"
 
                         endif
 
@@ -230,18 +230,18 @@ config BSP_USING_TIM
 
                         if BSP_USING_TIM4_PWM
                                 config BSP_USING_TIM4_PWM_CH1
-                                        bool "using TIM4 channel 1 as pwm"
+                                        bool "using TIM4 channel 1"
                                         default n
 
                                 config BSP_USING_TIM4_PWM_CH2
-                                        bool "using TIM4 channel 2 as pwm"
+                                        bool "using TIM4 channel 2"
                                         default n
 
                                 config BSP_USING_TIM4_PWM_CH3
-                                        bool "using TIM4 channel 3 as pwm"
+                                        bool "using TIM4 channel 3"
 
                                 config BSP_USING_TIM4_PWM_CH4
-                                        bool "using TIM4 channel 4 as pwm"
+                                        bool "using TIM4 channel 4"
 
                         endif