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@@ -39,7 +39,7 @@
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x1DU
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/* The PHY interrupt mask register. */
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-#define PHY_INTERRUPT_MSAK_REG 0x1EU
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+#define PHY_INTERRUPT_MASK_REG 0x1EU
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#define PHY_LINK_DOWN_MASK (1<<4)
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#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
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@@ -58,7 +58,7 @@
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x15U
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/* The PHY interrupt mask register. */
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-#define PHY_INTERRUPT_MSAK_REG 0x15U
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+#define PHY_INTERRUPT_MASK_REG 0x15U
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#define PHY_LINK_CHANGE_FLAG (1<<2)
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#define PHY_LINK_CHANGE_MASK (1<<9)
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#define PHY_INT_MASK 0
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