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@@ -14,13 +14,21 @@
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#ifdef RT_USING_QSPI
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#include <rtthread.h>
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+#ifdef RT_USING_SMART
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+ #include <ioremap.h>
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+#endif
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#include "rtdevice.h"
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#include "drv_qspi.h"
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#include "fqspi_flash.h"
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#include "rtdbg.h"
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#include "fiopad.h"
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+#include "fqspi_hw.h"
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+
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#define DAT_LENGTH 128
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+#define QSPI_ALIGNED_BYTE 4
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+static rt_uint8_t rd_buf[DAT_LENGTH];
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+static rt_uint8_t wr_buf[DAT_LENGTH];
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static phytium_qspi_bus phytium_qspi =
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{
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@@ -38,13 +46,17 @@ rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus)
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rt_uint32_t qspi_id = phytium_qspi_bus->fqspi_id;
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#ifdef USING_QSPI_CHANNEL0
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+#if defined CONFIG_TARGET_E2000D
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR51_REG0_OFFSET, FIOPAD_FUNC0);
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- FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR45_REG0_OFFSET, FIOPAD_FUNC0);
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-#endif
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-
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-#ifdef USING_QSPI_CHANNEL1
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+#elif defined CONFIG_TARGET_E2000Q
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR55_REG0_OFFSET, FIOPAD_FUNC0);
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+#endif
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+#elif defined USING_QSPI_CHANNEL1
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+#if defined CONFIG_TARGET_E2000D
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+ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR45_REG0_OFFSET, FIOPAD_FUNC0);
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+#elif defined CONFIG_TARGET_E2000Q
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FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR49_REG0_OFFSET, FIOPAD_FUNC0);
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+#endif
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#endif
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FQspiDeInitialize(&(phytium_qspi_bus->fqspi));
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@@ -86,7 +98,7 @@ static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_s
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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phytium_qspi_bus *qspi_bus;
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- qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
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+ qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data;
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rt_err_t ret = RT_EOK;
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ret = FQspiInit(qspi_bus);
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@@ -101,7 +113,191 @@ static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_s
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return RT_EOK;
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}
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-static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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+static FError QspiFlashWriteData(FQspiCtrl *pctrl, u8 command, uintptr addr, const u8 *buf, size_t len)
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+{
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+ RT_ASSERT(pctrl && buf);
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+ FError ret = FQSPI_SUCCESS;
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+ u32 loop = 0;
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+ const u32 mask = (u32)GENMASK(1, 0);
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+ u32 reg_val = 0;
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+ u32 val = 0;
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+ u32 aligned_bit = 0;
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+
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+ u8 tmp[QSPI_ALIGNED_BYTE] = {0xff, 0xff, 0xff, 0xff};
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+ uintptr base_addr = pctrl->config.base_addr;
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+
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+ if (FT_COMPONENT_IS_READY != pctrl->is_ready)
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+ {
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+ LOG_E("Nor flash not ready !!!");
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+ return FQSPI_NOT_READY;
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+ }
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+
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+ /* Flash write enable */
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+ FQspiFlashEnableWrite(pctrl);
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+
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+ memset(&pctrl->wr_cfg, 0, sizeof(pctrl->wr_cfg));
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+ /* set cmd region, command */
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+ pctrl->wr_cfg.wr_cmd = command;
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+ pctrl->wr_cfg.wr_wait = FQSPI_WAIT_ENABLE;
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+ /* clear addr select bit */
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+ pctrl->wr_cfg.wr_addr_sel = 0;
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+ /* set wr mode, use buffer */
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+ pctrl->wr_cfg.wr_mode = FQSPI_USE_BUFFER_ENABLE;
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+ /* set sck_sel region, clk_div */
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+ pctrl->wr_cfg.wr_sck_sel = FQSPI_SCK_DIV_128;
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+
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+ /* set addr_sel region, FQSPI_ADDR_SEL_3 or FQSPI_ADDR_SEL_4 */
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+ switch (command)
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+ {
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+ case FQSPI_FLASH_CMD_PP:
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+ case FQSPI_FLASH_CMD_QPP:
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+ pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3;
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+ break;
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+ case FQSPI_FLASH_CMD_4PP:
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+ case FQSPI_FLASH_CMD_4QPP:
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+ pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_4;
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+ break;
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+ default:
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+ ret |= FQSPI_NOT_SUPPORT;
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+ return ret;
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+ break;
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+ }
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+
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+ /*write wr_cfg to Write config register 0x08 */
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+ FQspiWrCfgConfig(pctrl);
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+ if (IS_ALIGNED(addr, QSPI_ALIGNED_BYTE)) /* if copy src is aligned by 4 bytes */
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+ {
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+ /* write alligned data into memory space */
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+ for (loop = 0; loop < (len >> 2); loop++)
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+ {
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+ FQSPI_DAT_WRITE(addr + QSPI_ALIGNED_BYTE * loop, *(u32 *)(buf + QSPI_ALIGNED_BYTE * loop));
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+ }
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+ /* write not alligned data into memory space */
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+ if (len & mask)
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+ {
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+ addr = addr + (len & ~mask);
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+ memcpy(tmp, buf + (len & ~mask), len & mask);
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+ FQSPI_DAT_WRITE(addr, *(u32 *)(tmp));
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+ }
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+ }
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+ else
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+ {
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+ aligned_bit = (addr & mask);
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+ addr = addr - aligned_bit;
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+ reg_val = FQSPI_READ_REG32(addr, 0);
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+
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+ for (loop = 0; loop < (QSPI_ALIGNED_BYTE - aligned_bit); loop++)
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+ {
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+ val = (val << 8) | (buf[loop]);
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+ reg_val &= (~(0xff << (loop * 8)));
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+ }
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+
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+ reg_val |= val;
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+ reg_val = __builtin_bswap32(reg_val);
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+ FQSPI_DAT_WRITE(addr, reg_val);
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+
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+ buf = buf + loop;
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+ len = len - loop;
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+ addr = addr + QSPI_ALIGNED_BYTE;
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+
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+ LOG_E("addr=%p, buf=%p, len=%d, value=%#x\r\n", addr, buf, len, *(u32 *)(buf));
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+
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+ for (loop = 0; loop < (len >> 2); loop++)
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+ {
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+ FQSPI_DAT_WRITE(addr + QSPI_ALIGNED_BYTE * loop, *(u32 *)(buf + QSPI_ALIGNED_BYTE * loop));
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+ }
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+
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+ if (!IS_ALIGNED(len, QSPI_ALIGNED_BYTE))
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+ {
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+ buf = buf + QSPI_ALIGNED_BYTE * loop;
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+ len = len - QSPI_ALIGNED_BYTE * loop;
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+ addr = addr + QSPI_ALIGNED_BYTE * loop;
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+ memcpy(tmp, buf, len);
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+ FQSPI_DAT_WRITE(addr, *(u32 *)(tmp));
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+ }
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+ }
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+
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+ /* flush buffer data to Flash */
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+ FQspiWriteFlush(base_addr);
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+
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+ ret = FQspiFlashWaitForCmd(pctrl);
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+
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+ return ret;
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+}
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+
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+size_t QspiFlashReadData(FQspiCtrl *pctrl, uintptr addr, u8 *buf, size_t len)
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+{
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+ /* addr of copy dst or src might be zero */
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+ RT_ASSERT(pctrl && buf);
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+ size_t loop = 0;
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+ const size_t cnt = len / QSPI_ALIGNED_BYTE; /* cnt number of 4-bytes need copy */
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+ const size_t remain = len % QSPI_ALIGNED_BYTE; /* remain number of 1-byte not aligned */
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+ u8 align_buf[QSPI_ALIGNED_BYTE];
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+ size_t copy_len = 0;
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+
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+ intptr src_addr = (intptr)addr; /* conver to 32/64 bit addr */
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+ intptr dst_addr = (intptr)buf;
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+
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+ if (FT_COMPONENT_IS_READY != pctrl->is_ready)
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+ {
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+ LOG_E("Nor flash not ready !!!");
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+ return 0;
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+ }
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+ if (0 == pctrl->rd_cfg.rd_cmd)
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+ {
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+ LOG_E("Nor flash read command is not ready !!!");
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+ return 0;
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+ }
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+
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+ if (0 == len)
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+ {
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+ return 0;
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+ }
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+
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+ if (IS_ALIGNED(src_addr, QSPI_ALIGNED_BYTE)) /* if copy src is aligned by 4 bytes */
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+ {
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+ /* read 4-bytes aligned buf part */
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+ for (loop = 0; loop < cnt; loop++)
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+ {
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+ *(u32 *)dst_addr = *(volatile u32 *)(src_addr);
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+ src_addr += QSPI_ALIGNED_BYTE;
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+ dst_addr += QSPI_ALIGNED_BYTE;
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+ }
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+
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+ copy_len += (loop << 2);
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+
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+ if (remain > 0)
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+ {
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+ *(u32 *)align_buf = *(volatile u32 *)(src_addr);
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+ }
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+
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+ /* read remain un-aligned buf byte by byte */
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+ for (loop = 0; loop < remain; loop++)
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+ {
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+ *(u8 *)dst_addr = align_buf[loop];
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+ dst_addr += 1;
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+ }
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+
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+ copy_len += loop;
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+
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+ }
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+ else /* if copy src is not aligned */
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+ {
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+ /* read byte by byte */
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+ for (loop = 0; loop < len; loop++)
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+ {
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+ *(u8 *)dst_addr = *(volatile u8 *)(src_addr);
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+ dst_addr += 1;
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+ src_addr += 1;
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+ }
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+ copy_len += loop;
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+
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+ }
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+
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+ return copy_len;
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+}
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+
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+static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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@@ -110,18 +306,18 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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rt_uint32_t cmd = qspi_message->instruction.content;
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rt_uint32_t flash_addr = qspi_message->address.content;
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- rt_uint8_t *rcvb = message->recv_buf;
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- rt_uint8_t *sndb = message->send_buf;
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+ const void *rcvb = message->recv_buf;
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+ const void *sndb = message->send_buf;
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FError ret = FT_SUCCESS;
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- qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
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+ qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data;
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+
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#ifdef USING_QSPI_CHANNEL0
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qspi_bus->fqspi.config.channel = 0;
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-#endif
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-
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-#ifdef USING_QSPI_CHANNEL1
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+#elif defined USING_QSPI_CHANNEL1
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qspi_bus->fqspi.config.channel = 1;
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#endif
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+
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uintptr addr = qspi_bus->fqspi.config.mem_start + qspi_bus->fqspi.config.channel * qspi_bus->fqspi.flash_size + flash_addr;
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#ifdef RT_USING_SMART
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@@ -130,10 +326,9 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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/*Distinguish the write mode according to different commands*/
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if (cmd == FQSPI_FLASH_CMD_PP || cmd == FQSPI_FLASH_CMD_QPP || cmd == FQSPI_FLASH_CMD_4PP || cmd == FQSPI_FLASH_CMD_4QPP)
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{
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- rt_uint8_t *wr_buf = NULL;
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- wr_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
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rt_uint8_t len = message->length;
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- rt_memcpy(wr_buf, (char *)message->send_buf, len);
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+
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+ rt_memcpy(&wr_buf, (char *)message->send_buf, len);
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ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr);
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if (FT_SUCCESS != ret)
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{
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@@ -141,7 +336,7 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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return RT_ERROR;
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}
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/* write norflash data */
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- ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, addr, wr_buf, len);
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+ ret = QspiFlashWriteData(&(qspi_bus->fqspi), cmd, addr, (u8 *)&wr_buf, len);
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if (FT_SUCCESS != ret)
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{
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@@ -152,7 +347,6 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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{
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rt_kprintf("Write successfully!!!\r\n");
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}
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- rt_free(wr_buf);
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return RT_EOK;
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}
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@@ -161,18 +355,14 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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if (cmd == FQSPI_FLASH_CMD_READ || cmd == FQSPI_FLASH_CMD_4READ || cmd == FQSPI_FLASH_CMD_FAST_READ || cmd == FQSPI_FLASH_CMD_4FAST_READ ||
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cmd == FQSPI_FLASH_CMD_DUAL_READ || cmd == FQSPI_FLASH_CMD_QIOR || cmd == FQSPI_FLASH_CMD_4QIOR)
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{
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- rt_uint8_t *rd_buf = NULL;
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- rd_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
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-
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ret |= FQspiFlashReadDataConfig(&(qspi_bus->fqspi), cmd);
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-
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if (FT_SUCCESS != ret)
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{
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rt_kprintf("Failed to config read, test result 0x%x.\r\n", ret);
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return RT_ERROR;
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}
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/* read norflash data */
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- size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), addr, rd_buf, DAT_LENGTH);
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+ size_t read_len = QspiFlashReadData(&(qspi_bus->fqspi), addr, (u8 *)&rd_buf, DAT_LENGTH);
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message->length = read_len;
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if (read_len != DAT_LENGTH)
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{
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@@ -182,8 +372,8 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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else
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{
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rt_kprintf("Read successfully!!!\r\n");
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- message->recv_buf = rd_buf;
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- rt_free(rd_buf);
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+ message->recv_buf = &rd_buf;
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+
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}
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FtDumpHexByte(message->recv_buf, read_len);
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@@ -194,7 +384,7 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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{
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if (cmd == FQSPI_FLASH_CMD_RDID || cmd == FQSPI_FLASH_CMD_RDSR1 || cmd == FQSPI_FLASH_CMD_RDSR2 || cmd == FQSPI_FLASH_CMD_RDSR3)
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{
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- ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, rcvb, sizeof(rcvb));
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+ ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, (u8 *)rcvb, sizeof(rcvb));
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if (FT_SUCCESS != ret)
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{
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LOG_E("Failed to read flash information.\n");
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@@ -214,7 +404,7 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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return RT_ERROR;
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}
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- ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, sndb, 1);
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+ ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, (u8 *)sndb, 1);
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if (FT_SUCCESS != ret)
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{
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LOG_E("Failed to write flash reg.\n");
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@@ -223,6 +413,8 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi
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return RT_EOK;
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}
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+ rt_kprintf("cmd not found!!!\r\n");
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+ return ret;
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}
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static struct rt_spi_ops phytium_qspi_ops =
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@@ -253,11 +445,9 @@ __exit:
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if (qspi_device)
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{
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rt_free(qspi_device);
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-
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}
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-
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- return result;
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}
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+ return result;
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}
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int rt_hw_qspi_init(void)
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@@ -341,15 +531,13 @@ void qspi_thread(void *parameter)
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RT_ASSERT(res != RT_EOK);
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rt_kprintf("The status reg = %x \n", recv);
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-
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- return 0;
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}
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rt_err_t qspi_sample(int argc, char *argv[])
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{
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rt_thread_t thread;
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rt_err_t res;
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- thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 2048, 25, 10);
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+ thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 4096, 25, 10);
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res = rt_thread_startup(thread);
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RT_ASSERT(res == RT_EOK);
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@@ -358,4 +546,3 @@ rt_err_t qspi_sample(int argc, char *argv[])
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/* Enter qspi_sample command for testing */
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MSH_CMD_EXPORT(qspi_sample, qspi sample);
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#endif
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-
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zhangyan