|
|
@@ -53,6 +53,24 @@
|
|
|
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
|
|
#endif /* PHY_USING_LAN8720A */
|
|
|
|
|
|
+#ifdef PHY_USING_LAN8742A
|
|
|
+/* The PHY interrupt source flag register. */
|
|
|
+#define PHY_INTERRUPT_FLAG_REG 0x1DU
|
|
|
+/* The PHY interrupt mask register. */
|
|
|
+#define PHY_INTERRUPT_MASK_REG 0x1EU
|
|
|
+#define PHY_LINK_DOWN_MASK (1<<4)
|
|
|
+#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
|
|
|
+
|
|
|
+/* The PHY status register. */
|
|
|
+#define PHY_Status_REG 0x1FU
|
|
|
+#define PHY_10M_MASK (1<<2)
|
|
|
+#define PHY_100M_MASK (1<<3)
|
|
|
+#define PHY_FULL_DUPLEX_MASK (1<<4)
|
|
|
+#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
|
|
+#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
|
|
|
+#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
|
|
+#endif /* PHY_USING_LAN8742A */
|
|
|
+
|
|
|
#ifdef PHY_USING_DM9161CEP
|
|
|
#define PHY_Status_REG 0x11U
|
|
|
#define PHY_10M_MASK ((1<<12) || (1<<13))
|
Ouxiaolong