Format some File

bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/cycfg_pins.h

@@ -115,7 +115,7 @@ extern "C" {
 #define CYBSP_WCO_IN_HAL_PORT_PIN P21_0
 #define CYBSP_WCO_IN P21_0
 #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif /* defined (CY_USING_HAL) */
 
@@ -136,7 +136,7 @@ extern "C" {
 #define CYBSP_WCO_OUT_HAL_PORT_PIN P21_1
 #define CYBSP_WCO_OUT P21_1
 #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif /* defined (CY_USING_HAL) */
 
@@ -157,7 +157,7 @@ extern "C" {
 #define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
 #define CYBSP_ECO_IN P21_2
 #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif /* defined (CY_USING_HAL) */
 
@@ -178,7 +178,7 @@ extern "C" {
 #define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
 #define CYBSP_ECO_OUT P21_3
 #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #define CYBSP_USER_BTN1 (P21_4)
 #define CYBSP_USER_BTN CYBSP_USER_BTN1
@@ -206,7 +206,7 @@ extern "C" {
 #define CYBSP_SWO_HAL_PORT_PIN P23_4
 #define CYBSP_SWO P23_4
 #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
 #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
 #endif /* defined (CY_USING_HAL) */
 
@@ -227,7 +227,7 @@ extern "C" {
 #define CYBSP_SWDCK_HAL_PORT_PIN P23_5
 #define CYBSP_SWDCK P23_5
 #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
 #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
 #endif /* defined (CY_USING_HAL) */
 
@@ -248,7 +248,7 @@ extern "C" {
 #define CYBSP_SWDIO_HAL_PORT_PIN P23_6
 #define CYBSP_SWDIO P23_6
 #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
 #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
 #define CYBSP_WIFI_SDIO_CLK (P24_2)
 #define CYBSP_WIFI_SDIO_CMD (P24_3)

bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/cycfg_system.c

@@ -604,51 +604,51 @@ void init_cycfg_system(void)
             #warning Power system will not be configured. Update power personality to v1.20 or later.
         #endif /* CY_CFG_PWR_INIT */
     #endif /* CY_CFG_PWR_ENABLED */
-    
+
     /* Disable FLL */
         Cy_SysClk_FllDeInit();
-    
+
     #ifdef CY_CFG_SYSCLK_ILO0_ENABLED
         Cy_SysClk_Ilo0Init();
     #else
         Cy_SysClk_Ilo0DeInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_ILO1_ENABLED
         Cy_SysClk_Ilo1Init();
     #else
         Cy_SysClk_Ilo1DeInit();
     #endif
-    
+
     /* Enable all source clocks */
     #ifdef CY_CFG_SYSCLK_PILO_ENABLED
         Cy_SysClk_PiloInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_WCO_ENABLED
         Cy_SysClk_WcoInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_ECO_ENABLED
         Cy_SysClk_EcoInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
         Cy_SysClk_ClkLfInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
         Cy_SysClk_ExtClkInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
         Cy_SysClk_AltHfInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
         Cy_SysClk_ClkPeriInit();
     #endif
-    
+
     /* Configure Path Clocks */
     #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
         Cy_SysClk_ClkPath1Init();
@@ -695,7 +695,7 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
         Cy_SysClk_ClkPath15Init();
     #endif
-    
+
     /* Configure and enable PLLs */
     #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
         Cy_SysClk_Pll0Init();
@@ -742,7 +742,7 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
         Cy_SysClk_Pll14Init();
     #endif
-    
+
     /* Configure HF clocks */
     #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
         Cy_SysClk_ClkHf1Init();
@@ -789,19 +789,19 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
         Cy_SysClk_ClkHf15Init();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
         Cy_SysClk_ClkAltSysTickInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
         Cy_SysClk_ClkPumpInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
         Cy_SysClk_ClkBakInit();
     #endif
-    
+
     /* Configure default enabled clocks */
     #ifdef CY_CFG_SYSCLK_ILO_ENABLED
         Cy_SysClk_IloInit();
@@ -810,7 +810,7 @@ void init_cycfg_system(void)
     #ifndef CY_CFG_SYSCLK_IMO_ENABLED
         #error the IMO must be enabled for proper chip operation
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_MFO_ENABLED
         Cy_SysClk_MfoInit();
     #endif
@@ -818,16 +818,16 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
         Cy_SysClk_ClkMfInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPWR_ENABLED
         Cy_SysClk_ClkPwrInit();
     #endif
-    
+
         /* Set accurate flash wait states */
         #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF1_ENABLED))
             Cy_SysLib_SetWaitStates(false, CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ);
         #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
         Cy_SysClk_ClkPath0Init();
     #endif
@@ -835,32 +835,32 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_FLL_ENABLED
         Cy_SysClk_FllInit();
     #endif
-    
+
     Cy_SysClk_ClkHf0Init();
     
     #ifdef CY_CFG_SYSCLK_CLKFAST_0_ENABLED
         Cy_SysClk_ClkFast_0_Init();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKFAST_1_ENABLED
         Cy_SysClk_ClkFast_1_Init();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
         Cy_SysClk_ClkSlowInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKMEM_ENABLED
         Cy_SysClk_ClkMemInit();
     #endif
-    
+
 #if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
         Cy_SysClk_EcoPrescalerInit();
 #endif /* defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) */
     #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
         Cy_SysClk_ClkAltSysTickInit();
     #endif
-    
+
     /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
     SystemCoreClockUpdate();
 #if defined (CY_USING_HAL)

bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/cycfg_pins.h

@@ -115,7 +115,7 @@ extern "C" {
 #define CYBSP_WCO_IN_HAL_PORT_PIN P21_0
 #define CYBSP_WCO_IN P21_0
 #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif /* defined (CY_USING_HAL) */
 
@@ -136,7 +136,7 @@ extern "C" {
 #define CYBSP_WCO_OUT_HAL_PORT_PIN P21_1
 #define CYBSP_WCO_OUT P21_1
 #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif /* defined (CY_USING_HAL) */
 
@@ -157,7 +157,7 @@ extern "C" {
 #define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
 #define CYBSP_ECO_IN P21_2
 #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif /* defined (CY_USING_HAL) */
 
@@ -178,7 +178,7 @@ extern "C" {
 #define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
 #define CYBSP_ECO_OUT P21_3
 #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
 #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #define CYBSP_USER_BTN1 (P21_4)
 #define CYBSP_USER_BTN CYBSP_USER_BTN1
@@ -206,7 +206,7 @@ extern "C" {
 #define CYBSP_SWO_HAL_PORT_PIN P23_4
 #define CYBSP_SWO P23_4
 #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
 #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
 #endif /* defined (CY_USING_HAL) */
 
@@ -227,7 +227,7 @@ extern "C" {
 #define CYBSP_SWDCK_HAL_PORT_PIN P23_5
 #define CYBSP_SWDCK P23_5
 #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
 #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
 #endif /* defined (CY_USING_HAL) */
 
@@ -248,7 +248,7 @@ extern "C" {
 #define CYBSP_SWDIO_HAL_PORT_PIN P23_6
 #define CYBSP_SWDIO P23_6
 #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
 #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
 #define CYBSP_WIFI_SDIO_CLK (P24_2)
 #define CYBSP_WIFI_SDIO_CMD (P24_3)

bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/cycfg_system.c

@@ -604,51 +604,51 @@ void init_cycfg_system(void)
             #warning Power system will not be configured. Update power personality to v1.20 or later.
         #endif /* CY_CFG_PWR_INIT */
     #endif /* CY_CFG_PWR_ENABLED */
-    
+
     /* Disable FLL */
         Cy_SysClk_FllDeInit();
-    
+
     #ifdef CY_CFG_SYSCLK_ILO0_ENABLED
         Cy_SysClk_Ilo0Init();
     #else
         Cy_SysClk_Ilo0DeInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_ILO1_ENABLED
         Cy_SysClk_Ilo1Init();
     #else
         Cy_SysClk_Ilo1DeInit();
     #endif
-    
+
     /* Enable all source clocks */
     #ifdef CY_CFG_SYSCLK_PILO_ENABLED
         Cy_SysClk_PiloInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_WCO_ENABLED
         Cy_SysClk_WcoInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_ECO_ENABLED
         Cy_SysClk_EcoInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
         Cy_SysClk_ClkLfInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
         Cy_SysClk_ExtClkInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
         Cy_SysClk_AltHfInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
         Cy_SysClk_ClkPeriInit();
     #endif
-    
+
     /* Configure Path Clocks */
     #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
         Cy_SysClk_ClkPath1Init();
@@ -695,7 +695,7 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
         Cy_SysClk_ClkPath15Init();
     #endif
-    
+
     /* Configure and enable PLLs */
     #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
         Cy_SysClk_Pll0Init();
@@ -742,7 +742,7 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
         Cy_SysClk_Pll14Init();
     #endif
-    
+
     /* Configure HF clocks */
     #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
         Cy_SysClk_ClkHf1Init();
@@ -789,40 +789,40 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
         Cy_SysClk_ClkHf15Init();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
         Cy_SysClk_ClkAltSysTickInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
         Cy_SysClk_ClkPumpInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
         Cy_SysClk_ClkBakInit();
     #endif
-    
+
     /* Configure default enabled clocks */
     #ifdef CY_CFG_SYSCLK_ILO_ENABLED
         Cy_SysClk_IloInit();
     #endif
-    
+
     #ifndef CY_CFG_SYSCLK_IMO_ENABLED
         #error the IMO must be enabled for proper chip operation
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_MFO_ENABLED
         Cy_SysClk_MfoInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
         Cy_SysClk_ClkMfInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKPWR_ENABLED
         Cy_SysClk_ClkPwrInit();
     #endif
-    
+
         /* Set accurate flash wait states */
         #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF1_ENABLED))
             Cy_SysLib_SetWaitStates(false, CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ);
@@ -835,7 +835,7 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_FLL_ENABLED
         Cy_SysClk_FllInit();
     #endif
-    
+
     Cy_SysClk_ClkHf0Init();
     
     #ifdef CY_CFG_SYSCLK_CLKFAST_0_ENABLED
@@ -845,22 +845,22 @@ void init_cycfg_system(void)
     #ifdef CY_CFG_SYSCLK_CLKFAST_1_ENABLED
         Cy_SysClk_ClkFast_1_Init();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
         Cy_SysClk_ClkSlowInit();
     #endif
-    
+
     #ifdef CY_CFG_SYSCLK_CLKMEM_ENABLED
         Cy_SysClk_ClkMemInit();
     #endif
-    
+
 #if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
         Cy_SysClk_EcoPrescalerInit();
 #endif /* defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) */
     #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
         Cy_SysClk_ClkAltSysTickInit();
     #endif
-    
+
     /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
     SystemCoreClockUpdate();
 #if defined (CY_USING_HAL)