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@@ -10,9 +10,9 @@
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#include "common.h"
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-CSL_BootcfgRegs * gpBootCfgRegs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
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-CSL_CgemRegs * gpCGEM_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
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-CSL_TmrPlusRegs * gpTimerRegs[9] = {
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+CSL_BootcfgRegs * gp_bootcfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
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+CSL_CgemRegs * gp_cgem_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
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+CSL_TmrPlusRegs * gp_timer_regs[9] = {
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(CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
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(CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
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@@ -29,22 +29,22 @@ void cpu_interrupt_init(void)
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//clear interrupt and excpetion events
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ICR = IFR;
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ECR = EFR;
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- IER= 3; //disable all interrupts
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+ IER = 3; //disable all interrupts
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/* disable event combine */
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- gpCGEM_regs->EVTMASK[0] = 0xffffffff;
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- gpCGEM_regs->EVTMASK[1] = 0xffffffff;
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- gpCGEM_regs->EVTMASK[2] = 0xffffffff;
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- gpCGEM_regs->EVTMASK[3] = 0xffffffff;
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+ gp_cgem_regs->EVTMASK[0] = 0xffffffff;
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+ gp_cgem_regs->EVTMASK[1] = 0xffffffff;
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+ gp_cgem_regs->EVTMASK[2] = 0xffffffff;
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+ gp_cgem_regs->EVTMASK[3] = 0xffffffff;
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/*Clear all CPU events*/
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- gpCGEM_regs->EVTCLR[0]= 0xFFFFFFFF;
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- gpCGEM_regs->EVTCLR[1]= 0xFFFFFFFF;
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- gpCGEM_regs->EVTCLR[2]= 0xFFFFFFFF;
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- gpCGEM_regs->EVTCLR[3]= 0xFFFFFFFF;
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+ gp_cgem_regs->EVTCLR[0] = 0xFFFFFFFF;
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+ gp_cgem_regs->EVTCLR[1] = 0xFFFFFFFF;
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+ gp_cgem_regs->EVTCLR[2] = 0xFFFFFFFF;
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+ gp_cgem_regs->EVTCLR[3] = 0xFFFFFFFF;
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/*Interrupt Service Table Pointer to begining of LL2 memory*/
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- ISTP= 0x800000;
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+ ISTP = 0x800000;
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}
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void keystone_cpu_init(void)
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@@ -56,10 +56,10 @@ void keystone_cpu_init(void)
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/*===============================Timer=================================*/
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void reset_timer(int timer_num)
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{
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- if(gpTimerRegs[timer_num]->TGCR)
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+ if(gp_timer_regs[timer_num]->TGCR)
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{
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- gpTimerRegs[timer_num]->TGCR = 0;
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- gpTimerRegs[timer_num]->TCR= 0;
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+ gp_timer_regs[timer_num]->TGCR = 0;
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+ gp_timer_regs[timer_num]->TCR= 0;
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}
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}
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@@ -67,8 +67,8 @@ void timer64_init(Timer64_Config * tmrCfg)
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{
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reset_timer(tmrCfg->timer_num);
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- gpTimerRegs[tmrCfg->timer_num]->CNTLO = 0;
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- gpTimerRegs[tmrCfg->timer_num]->CNTHI = 0;
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+ gp_timer_regs[tmrCfg->timer_num]->CNTLO = 0;
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+ gp_timer_regs[tmrCfg->timer_num]->CNTHI = 0;
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/*please note, in clock mode, two timer periods generate a clock,
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one timer period output high voltage level, the other timer period
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@@ -80,17 +80,17 @@ void timer64_init(Timer64_Config * tmrCfg)
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}
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/*the value written into period register is the expected value minus one*/
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- gpTimerRegs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
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- gpTimerRegs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
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+ gp_timer_regs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
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+ gp_timer_regs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
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if(tmrCfg->reload_period>1)
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{
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- gpTimerRegs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
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- gpTimerRegs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
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+ gp_timer_regs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
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+ gp_timer_regs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
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}
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if(TIMER_WATCH_DOG == tmrCfg->timerMode)
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{
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- gpTimerRegs[tmrCfg->timer_num]->TGCR =
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+ gp_timer_regs[tmrCfg->timer_num]->TGCR =
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/*Select watch-dog mode*/
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(CSL_TMR_TIMMODE_WDT << CSL_TMR_TGCR_TIMMODE_SHIFT)
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/*Remove the timer from reset*/
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@@ -99,18 +99,18 @@ void timer64_init(Timer64_Config * tmrCfg)
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}
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else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
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{
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- gpTimerRegs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
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+ gp_timer_regs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
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/*for plus featuers, dual 32-bit unchained timer mode should be used*/
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| (CSL_TMR_TIMMODE_DUAL_UNCHAINED << CSL_TMR_TGCR_TIMMODE_SHIFT)
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/*Remove the timer from reset*/
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| (CSL_TMR_TGCR_TIMLORS_MASK);
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//in plus mode, interrupt/event must be enabled manually
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- gpTimerRegs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
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+ gp_timer_regs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
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}
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else
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{
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- gpTimerRegs[tmrCfg->timer_num]->TGCR =
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+ gp_timer_regs[tmrCfg->timer_num]->TGCR =
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/*Select 64-bit general timer mode*/
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(CSL_TMR_TIMMODE_GPT << CSL_TMR_TGCR_TIMMODE_SHIFT)
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/*Remove the timer from reset*/
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@@ -119,16 +119,16 @@ void timer64_init(Timer64_Config * tmrCfg)
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}
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/*make timer stop with emulation*/
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- gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
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+ gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
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~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
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if(TIMER_WATCH_DOG == tmrCfg->timerMode)
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{
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/*enable watchdog timer*/
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- gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
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+ gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
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| (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT);
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- gpTimerRegs[tmrCfg->timer_num]->TCR=
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+ gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously*/
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@@ -141,12 +141,12 @@ void timer64_init(Timer64_Config * tmrCfg)
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| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
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/*active watchdog timer*/
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- gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
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+ gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
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| (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT);
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}
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else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode)
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{
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- gpTimerRegs[tmrCfg->timer_num]->TCR =
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+ gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled one-shot*/
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@@ -160,7 +160,7 @@ void timer64_init(Timer64_Config * tmrCfg)
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}
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else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
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{
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- gpTimerRegs[tmrCfg->timer_num]->TCR =
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+ gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously*/
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@@ -174,7 +174,7 @@ void timer64_init(Timer64_Config * tmrCfg)
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}
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else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
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{
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- gpTimerRegs[tmrCfg->timer_num]->TCR =
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+ gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously with period reload*/
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@@ -188,7 +188,7 @@ void timer64_init(Timer64_Config * tmrCfg)
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}
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else /*TIMER_PERIODIC_PULSE*/
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{
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- gpTimerRegs[tmrCfg->timer_num]->TCR =
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+ gp_timer_regs[tmrCfg->timer_num]->TCR =
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(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
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| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
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/*The timer is enabled continuously*/
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