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@@ -369,7 +369,7 @@ static void SetSysClockTo48(void)
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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- /* PCLK1 = HCLK */
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+ /* PCLK1 = HCLK/2 */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
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/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
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@@ -441,7 +441,7 @@ static void SetSysClockTo56(void)
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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- /* PCLK1 = HCLK */
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+ /* PCLK1 = HCLK/2 */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
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/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
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@@ -514,7 +514,7 @@ static void SetSysClockTo72(void)
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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- /* PCLK1 = HCLK */
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+ /* PCLK1 = HCLK/2 */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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@@ -588,7 +588,7 @@ static void SetSysClockTo96(void)
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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- /* PCLK1 = HCLK */
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+ /* PCLK1 = HCLK/2 */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
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/* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
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@@ -662,7 +662,7 @@ static void SetSysClockTo120(void)
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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- /* PCLK1 = HCLK */
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+ /* PCLK1 = HCLK/2 */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
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/* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
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@@ -736,7 +736,7 @@ static void SetSysClockTo144(void)
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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- /* PCLK1 = HCLK */
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+ /* PCLK1 = HCLK/2 */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
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/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
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