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@@ -0,0 +1,670 @@
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+/*
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+ * Copyright (c) 2006-2021, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2021-08-19 JasonHu first version
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+ */
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+
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+#include <board.h>
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+#include <rtthread.h>
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+#include <rtdevice.h>
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+#include <rthw.h>
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+#include <netif/ethernetif.h>
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+#include <pci.h>
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+#include <mmu.h>
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+
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+#define DBG_LVL DBG_INFO
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+#define DBG_TAG "PCNET32"
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+#include <rtdbg.h>
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+
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+#include "drv_pcnet32.h"
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+
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+#define DEV_NAME "e0"
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+
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+#define GET_PCNET32(eth) (struct eth_device_pcnet32 *)(eth)
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+
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+/**
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+ * rx ring desc struct
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+ */
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+struct pcnet32_rx_desc
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+{
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+ rt_uint32_t base; /* buffer base addr */
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+ rt_uint16_t buf_length; /* two`s complement of length */
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+ rt_uint16_t status; /* desc status */
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+ rt_uint16_t msg_length; /* Message Byte Count is the length in bytes of the received message. */
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+ rt_uint16_t rpc_rcc;
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+ rt_uint32_t reserved;
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+} __attribute__ ((packed));
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+
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+/**
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+ * tx ring desc struct
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+ */
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+struct pcnet32_tx_desc
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+{
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+ rt_uint32_t base; /* buffer base addr */
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+ rt_uint16_t buf_length; /* two`s complement of length */
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+ rt_uint16_t status; /* desc status */
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+ rt_uint32_t misc;
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+ rt_uint32_t reserved;
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+} __attribute__ ((packed));
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+
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+/**
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+ * The PCNET32 32-Bit initialization block, described in databook.
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+ * The Mode Register (CSR15) allows alteration of the chip's operating
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+ * parameters. The Mode field of the Initialization Block is copied directly
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+ * into CSR15. Normal operation is the result of configuring the Mode field
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+ * with all bits zero.
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+ */
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+struct pcnet32_init_block
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+{
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+ rt_uint16_t mode;
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+ rt_uint16_t tlen_rlen;
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+ rt_uint8_t phys_addr[6];
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+ rt_uint16_t reserved;
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+ rt_uint32_t filter[2];
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+ /* Receive and transmit ring base, along with extra bits. */
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+ rt_uint32_t rx_ring;
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+ rt_uint32_t tx_ring;
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+} __attribute__ ((packed));
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+
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+struct eth_device_pcnet32
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+{
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+ /* inherit from Ethernet device */
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+ struct eth_device parent;
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+ /* interface address info. */
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+ rt_uint8_t dev_addr[ETH_ALEN]; /* MAC address */
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+
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+ rt_pci_device_t *pci_dev; /* pci device info */
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+
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+ rt_uint32_t iobase; /* io port base */
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+ rt_uint32_t irqno; /* irq number */
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+
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+ rt_mq_t rx_mqueue; /* msg queue for rx */
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+
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+ struct pcnet32_init_block *init_block;
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+
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+ rt_uint16_t rx_len_bits;
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+ rt_uint16_t tx_len_bits;
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+
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+ rt_ubase_t rx_ring_dma_addr;
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+ rt_ubase_t tx_ring_dma_addr;
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+
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+ rt_ubase_t init_block_dma_addr;
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+
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+ rt_ubase_t rx_buffer_ptr;
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+ rt_ubase_t tx_buffer_ptr; /* pointers to transmit/receive buffers */
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+
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+ rt_size_t rx_buffer_count; /* total number of receive buffers */
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+ rt_size_t tx_buffer_count; /* total number of transmit buffers */
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+
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+ rt_size_t buffer_size; /* length of each packet buffer */
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+
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+ rt_size_t de_size; /* length of descriptor entry */
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+
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+ struct pcnet32_rx_desc *rdes; /* pointer to ring buffer of receive des */
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+ struct pcnet32_tx_desc *tdes; /* pointer to ring buffer of transmit des */
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+
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+ rt_uint32_t rx_buffers; /* physical address of actual receive buffers (< 4 GiB) */
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+ rt_uint32_t tx_buffers; /* physical address of actual transmit buffers (< 4 GiB) */
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+};
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+static struct eth_device_pcnet32 eth_dev;
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+static rt_uint8_t rx_cache_send_buf[RX_MSG_SIZE] = {0}; /* buf for rx packet, put size and data into mq */
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+static rt_uint8_t rx_cache_recv_buf[RX_MSG_SIZE] = {0}; /* buf for rx packet, get size and data from mq */
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+static rt_uint8_t tx_cache_pbuf[TX_CACHE_BUF_SIZE] = {0}; /* buf for tx packet, get data from pbuf payload */
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+
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+/**
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+ * does the driver own the particular buffer?
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+ */
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+rt_inline rt_bool_t pcnet32_is_driver_own(struct eth_device_pcnet32 *dev, rt_bool_t is_tx, rt_uint32_t idx)
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+{
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+ return (rt_bool_t)(is_tx ? ((dev->tdes[idx].status & PCNET32_DESC_STATUS_OWN) == 0) :
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+ ((dev->rdes[idx].status & PCNET32_DESC_STATUS_OWN) == 0));
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+}
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+
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+/*
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+ * get the next desc buffer index
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+ */
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+rt_inline rt_uint32_t pcnet32_get_next_desc(struct eth_device_pcnet32 *dev, rt_uint32_t cur_idx, rt_uint32_t buf_count)
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+{
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+ return (cur_idx + 1) % buf_count;
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+}
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+
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+static void pcnet32_init_rx_desc_entry(struct eth_device_pcnet32 *dev, rt_uint32_t idx)
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+{
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+ struct pcnet32_rx_desc *des = dev->rdes + idx;
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+ rt_memset(des, 0, dev->de_size);
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+
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+ des->base = dev->rx_buffers + idx * dev->buffer_size;
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+
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+ /* next 2 bytes are 0xf000 OR'd with the first 12 bits of the 2s complement of the length */
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+ rt_uint16_t bcnt = (rt_uint16_t)(-dev->buffer_size);
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+ bcnt &= 0x0fff;
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+ bcnt |= 0xf000; /* high 4 bits fixed 1 */
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+ des->buf_length = bcnt;
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+
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+ /* finally, set ownership bit - transmit buffers are owned by us, receive buffers by the card */
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+ des->status = PCNET32_DESC_STATUS_OWN;
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+}
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+
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+static void pcnet32_init_tx_desc_entry(struct eth_device_pcnet32 *dev, rt_uint32_t idx)
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+{
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+ struct pcnet32_tx_desc *des = dev->tdes + idx;
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+ rt_memset(des, 0, dev->de_size);
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+
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+ des->base = dev->tx_buffers + idx * dev->buffer_size;
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+
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+ /* next 2 bytes are 0xf000 OR'd with the first 12 bits of the 2s complement of the length */
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+ rt_uint16_t bcnt = (rt_uint16_t)(-dev->buffer_size);
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+ bcnt &= 0x0fff;
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+ bcnt |= 0xf000; /* high 4 bits fixed 1 */
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+ des->buf_length = bcnt;
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+}
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+
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+static rt_uint16_t pcnet32_wio_read_mac(rt_uint32_t addr, int index)
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+{
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+ return inw(addr + index);
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+}
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+
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+/*
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+ * write index to RAP, read data from RDP
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+ */
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+static rt_uint16_t pcnet32_wio_read_csr(rt_uint32_t addr, int index)
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+{
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+ outw(addr + PCNET32_WIO_RAP, index);
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+ return inw(addr + PCNET32_WIO_RDP);
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+}
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+
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+/**
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+ * write index to RAP, write data to RDP
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+ */
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+static void pcnet32_wio_write_csr(rt_uint32_t addr, int index, rt_uint16_t val)
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+{
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+ outw(addr + PCNET32_WIO_RAP, index);
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+ outw(addr + PCNET32_WIO_RDP, val);
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+}
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+
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+static void pcnet32_wio_write_bcr(rt_uint32_t addr, int index, rt_uint16_t val)
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+{
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+ outw(addr + PCNET32_WIO_RAP, index);
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+ outw(addr + PCNET32_WIO_BDP, val);
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+}
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+
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+/*
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+ * Reset causes the device to cease operation and clear its internal logic.
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+ */
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+static void pcnet32_wio_reset(rt_uint32_t addr)
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+{
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+ inw(addr + PCNET32_WIO_RESET);
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+}
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+
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+static int pcnet32_get_pci(struct eth_device_pcnet32 *dev)
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+{
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+ /* get pci device */
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+ rt_pci_device_t *pci_dev = rt_pci_device_get(PCNET32_VENDOR_ID, PCNET32_DEVICE_ID);
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+ if (pci_dev == RT_NULL)
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+ {
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+ LOG_E("device not find on pci device.\n");
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+ return -1;
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+ }
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+ dev->pci_dev = pci_dev;
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+ dbg_log(DBG_LOG, "find device, vendor id: 0x%x, device id: 0x%x\n",
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+ pci_dev->vendor_id, pci_dev->device_id);
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+
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+ /* enable bus mastering */
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+ rt_pci_enable_bus_mastering(pci_dev);
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+
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+ /* get io port address */
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+ dev->iobase = rt_pci_device_get_io_addr(pci_dev);
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+ if (dev->iobase == 0)
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+ {
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+ LOG_E("invalid pci device io address.\n");
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+ return -1;
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+ }
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+ dbg_log(DBG_LOG, "io base address: 0x%x\n", dev->iobase);
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+ /* get irq */
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+ dev->irqno = rt_pci_device_get_irq_line(pci_dev);
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+ if (dev->irqno == 0xff)
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+ {
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+ LOG_E("invalid irqno.\n");
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+ return -1;
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+ }
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+ dbg_log(DBG_LOG, "irqno %d\n", dev->irqno);
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+ return 0;
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+}
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+
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+static int pcnet32_transmit(struct eth_device_pcnet32 *dev, rt_uint8_t *buf, rt_size_t len)
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+{
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+ if(len > ETH_FRAME_LEN)
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+ {
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+ len = ETH_FRAME_LEN;
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+ }
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+
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+ rt_uint32_t tx_retry = PCNET32_TX_RETRY;
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+
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+ while (tx_retry > 0)
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+ {
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+ /* the next available descriptor entry index is in tx_buffer_ptr */
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+ if(!pcnet32_is_driver_own(dev, RT_TRUE, dev->tx_buffer_ptr))
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+ {
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+ /* try encourage the card to send all buffers. */
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+ pcnet32_wio_write_csr(dev->iobase, CSR0, pcnet32_wio_read_csr(dev->iobase, CSR0) | CSR0_TXPOLL);
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+ }
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+ else
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+ {
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+ break;
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+ }
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+ --tx_retry;
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+ }
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+
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+ if (!tx_retry) /* retry end, no entry available */
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+ {
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+ dbg_log(DBG_ERROR, "transmit no available descriptor entry\n")
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+ return -1;
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+ }
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+
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+ rt_memcpy((void *)(dev->tx_buffers + dev->tx_buffer_ptr * dev->buffer_size), buf, len);
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+
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+ struct pcnet32_tx_desc *tdes = dev->tdes + dev->tx_buffer_ptr;
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+ /**
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+ * set the STP bit in the descriptor entry (signals this is the first
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+ * frame in a split packet - we only support single frames)
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+ */
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+ tdes->status |= PCNET32_DESC_STATUS_STP;
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+
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+ /* similarly, set the ENP bit to state this is also the end of a packet */
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+ tdes->status |= PCNET32_DESC_STATUS_ENP;
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+
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+ rt_uint16_t bcnt = (rt_uint16_t)(-len);
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+ bcnt &= 0xfff;
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+ bcnt |= 0xf000; /* high 4 bits fixed 1 */
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+ tdes->buf_length = bcnt;
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+
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+ /* finally, flip the ownership bit back to the card */
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+ tdes->status |= PCNET32_DESC_STATUS_OWN;
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+
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+ dev->tx_buffer_ptr = pcnet32_get_next_desc(dev, dev->tx_buffer_ptr, dev->tx_buffer_count);
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+ return 0;
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+}
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+
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+static rt_err_t pcnet32_tx(rt_device_t device, struct pbuf *p)
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+{
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+ rt_err_t err = RT_EOK;
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+ /* copy data from pbuf to tx cache */
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+ pbuf_copy_partial(p, (void *)&tx_cache_pbuf[0], p->tot_len, 0);
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+ if (pcnet32_transmit(GET_PCNET32(device), tx_cache_pbuf, p->tot_len) < 0)
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+ {
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+ err = RT_ERROR;
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+ }
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+ return err;
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+}
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+
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+static struct pbuf *pcnet32_rx(rt_device_t device)
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+{
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+ struct eth_device_pcnet32 *dev = GET_PCNET32(device);
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+ int recv_len = 0;
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+ struct pbuf *pbuf = RT_NULL;
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+ rt_err_t err;
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+
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+ /* get data from rx queue. */
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+ err = rt_mq_recv_interruptible(dev->rx_mqueue, rx_cache_recv_buf, RX_MSG_SIZE, 0);
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+ if (err != RT_EOK)
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+ {
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+ return pbuf;
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+ }
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+ /* get recv len from rx cache, 0~3: recv len, 3-n: frame data */
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+ recv_len = *(int *)rx_cache_recv_buf;
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+ if (recv_len > 0)
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+ {
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+ pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
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+ rt_memcpy(pbuf->payload, (char *)rx_cache_recv_buf + 4, recv_len);
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+ }
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+ return pbuf;
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+}
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+
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+static rt_err_t pcnet32_control(rt_device_t device, int cmd, void *args)
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+{
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+ struct eth_device_pcnet32 *dev = GET_PCNET32(device);
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+ switch(cmd)
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+ {
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+ case NIOCTL_GADDR:
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+ /* get MAC address */
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+ if(args)
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+ {
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+ rt_memcpy(args, dev->dev_addr, ETH_ALEN);
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+ }
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+ else
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+ {
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+ return -RT_ERROR;
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+ }
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+ break;
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+ default :
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+ break;
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+ }
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+ return RT_EOK;
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+}
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+
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+static void pcnet32_rx_packet(struct eth_device_pcnet32 *dev)
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+{
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+ while (pcnet32_is_driver_own(dev, RT_FALSE, dev->rx_buffer_ptr))
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+ {
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+ struct pcnet32_rx_desc *rdes = dev->rdes + dev->rx_buffer_ptr;
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+ rt_uint32_t plen = rdes->msg_length; /* msg len no need to negate it unlike BCNT above */
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+
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+ void *pbuf = (void *)(dev->rx_buffers + dev->rx_buffer_ptr * dev->buffer_size);
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+ dbg_log(DBG_LOG, "recv packet on ring %d: buf=%p, len=%d\n", dev->rx_buffer_ptr, pbuf, plen);
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+ /* merge size and data into receive pkg */
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+ rt_memcpy(rx_cache_send_buf, &plen, 4);
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+ rt_memcpy(&rx_cache_send_buf[4], pbuf, plen);
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+
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+ rt_mq_send_interrupt(dev->rx_mqueue, rx_cache_send_buf, plen + 4);
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+ eth_device_ready(&dev->parent); /* notify eth thread to read packet */
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+
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+ /* hand the buffer back to the card */
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+ rdes->status = PCNET32_DESC_STATUS_OWN;
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+
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+ dev->rx_buffer_ptr = pcnet32_get_next_desc(dev, dev->rx_buffer_ptr, dev->rx_buffer_count);
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+ }
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+}
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+
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+static void rt_hw_pcnet32_isr(int vector, void *param)
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+{
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+ struct eth_device_pcnet32 *dev = GET_PCNET32(param);
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+ rt_uint32_t iobase = dev->iobase;
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+ rt_uint32_t csr0 = pcnet32_wio_read_csr(iobase, 0);
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+
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|
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+ if (csr0 & CSR0_RINT) /* recv packet */
|
|
|
+ {
|
|
|
+ dbg_log(DBG_LOG, "RX intr occur!\n");
|
|
|
+ pcnet32_rx_packet(dev);
|
|
|
+ }
|
|
|
+ else if ((csr0 & CSR0_TINT)) /* packet transmitted */
|
|
|
+ {
|
|
|
+ dbg_log(DBG_LOG, "TX intr occur!\n");
|
|
|
+ }
|
|
|
+ else if ((csr0 & CSR0_IDON))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_INFO, "init done\n");
|
|
|
+ }
|
|
|
+ else if ((csr0 & CSR0_MERR))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_WARNING, "memory error!\n");
|
|
|
+ }
|
|
|
+ else if ((csr0 & CSR0_MISS))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_WARNING, "missed frame!\n");
|
|
|
+ }
|
|
|
+ else if ((csr0 & CSR0_CERR))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_WARNING, "collision error!\n");
|
|
|
+ }
|
|
|
+ else if ((csr0 & CSR0_BABL))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_WARNING, "transmitter time-out error!\n");
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ dbg_log(DBG_WARNING, "unknown intr\n");
|
|
|
+ }
|
|
|
+ /* ack pcnet32 interrupt as handled */
|
|
|
+ pcnet32_wio_write_csr(iobase, 0, csr0);
|
|
|
+}
|
|
|
+
|
|
|
+static rt_err_t pcnet32_alloc_ring_buffer(struct eth_device_pcnet32 *dev)
|
|
|
+{
|
|
|
+ dev->rdes = rt_malloc_align(dev->rx_buffer_count * dev->de_size, 16);
|
|
|
+ if (dev->rdes == RT_NULL)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "alloc memory for rx ring failed!");
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+ dev->tdes = rt_malloc_align(dev->tx_buffer_count * dev->de_size, 16);
|
|
|
+ if (dev->tdes == RT_NULL)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "alloc memory for tx ring failed!");
|
|
|
+ rt_free_align(dev->rdes);
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev->rx_buffers = (uint32_t)rt_malloc_align(dev->rx_buffer_count * dev->buffer_size, 16);
|
|
|
+ if (dev->rx_buffers == 0)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "alloc memory for rx ring buffer failed!");
|
|
|
+ rt_free_align(dev->rdes);
|
|
|
+ rt_free_align(dev->tdes);
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev->tx_buffers = (uint32_t)rt_malloc_align(dev->tx_buffer_count * dev->buffer_size, 16);
|
|
|
+ if (dev->tx_buffers == 0)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "alloc memory for tx ring buffer failed!");
|
|
|
+ rt_free_align(dev->rdes);
|
|
|
+ rt_free_align(dev->tdes);
|
|
|
+ rt_free_align((void *)dev->rx_buffers);
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+ dbg_log(DBG_LOG, "rdes:%p tdes:%p rbuf:%p tbuf:%p\n", dev->rdes, dev->tdes, dev->rx_buffers, dev->tx_buffers);
|
|
|
+
|
|
|
+ int i = 0;
|
|
|
+ for (i = 0; i < dev->rx_buffer_count; i++)
|
|
|
+ {
|
|
|
+ pcnet32_init_rx_desc_entry(dev, i);
|
|
|
+ }
|
|
|
+ for (i = 0; i < dev->tx_buffer_count; i++)
|
|
|
+ {
|
|
|
+ pcnet32_init_tx_desc_entry(dev, i);
|
|
|
+ }
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+static void pcnet32_free_ring_buffer(struct eth_device_pcnet32 *dev)
|
|
|
+{
|
|
|
+ rt_free_align(dev->rdes);
|
|
|
+ rt_free_align(dev->tdes);
|
|
|
+ rt_free_align((void *)dev->rx_buffers);
|
|
|
+ rt_free_align((void *)dev->tx_buffers);
|
|
|
+}
|
|
|
+
|
|
|
+static void pcnet32_print_init_block(struct eth_device_pcnet32 *dev)
|
|
|
+{
|
|
|
+ rt_uint32_t iobase = dev->iobase;
|
|
|
+
|
|
|
+ struct pcnet32_init_block *init_block = dev->init_block;
|
|
|
+ dbg_log(DBG_LOG, "============\nprint init block\n");
|
|
|
+ dbg_log(DBG_LOG, "mode: %x, tlen_rlen:%x\n", init_block->mode, init_block->tlen_rlen);
|
|
|
+ dbg_log(DBG_LOG, "mac: %x:%x:%x:%x:%x:%x\n",
|
|
|
+ init_block->phys_addr[0],
|
|
|
+ init_block->phys_addr[1],
|
|
|
+ init_block->phys_addr[2],
|
|
|
+ init_block->phys_addr[3],
|
|
|
+ init_block->phys_addr[4],
|
|
|
+ init_block->phys_addr[5]);
|
|
|
+ dbg_log(DBG_LOG, "filter0: %x, filter1: %x\n", init_block->filter[0], init_block->filter[1]);
|
|
|
+ dbg_log(DBG_LOG, "rx ring dma: %x, tx ring dma: %x\n", init_block->rx_ring, init_block->tx_ring);
|
|
|
+ dbg_log(DBG_LOG, "init block dma: %x\n", dev->init_block_dma_addr);
|
|
|
+
|
|
|
+ int i = 0;
|
|
|
+ for (; i <= 46; i++)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_LOG, "csr%d=%x\n", i, pcnet32_wio_read_csr(iobase, i));
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static rt_err_t pcnet32_init(rt_device_t device)
|
|
|
+{
|
|
|
+ struct eth_device_pcnet32 *dev = GET_PCNET32(device);
|
|
|
+ rt_uint32_t iobase = dev->iobase;
|
|
|
+
|
|
|
+ /* init buffer info */
|
|
|
+ dev->rx_buffer_ptr = 0;
|
|
|
+ dev->tx_buffer_ptr = 0;
|
|
|
+
|
|
|
+ dev->rx_buffer_count = PCNET32_RX_BUFFERS;
|
|
|
+ dev->tx_buffer_count = PCNET32_TX_BUFFERS;
|
|
|
+
|
|
|
+ dev->buffer_size = ETH_FRAME_LEN;
|
|
|
+ dev->de_size = PCNET32_RING_DE_SIZE;
|
|
|
+
|
|
|
+ if (pcnet32_alloc_ring_buffer(dev) != RT_EOK)
|
|
|
+ {
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev->rx_ring_dma_addr = (rt_ubase_t)rt_hw_vir2phy(dev->rdes);
|
|
|
+ dev->tx_ring_dma_addr = (rt_ubase_t)rt_hw_vir2phy(dev->tdes);
|
|
|
+
|
|
|
+ /* create msg queue for eth rx */
|
|
|
+ dev->rx_mqueue = rt_mq_create("rx_mqueue", RX_MSG_SIZE, RX_MSG_CNT, 0);
|
|
|
+ if (dev->rx_mqueue == RT_NULL)
|
|
|
+ {
|
|
|
+ LOG_E("crete msg queue for rx buffer failed!\n");
|
|
|
+ pcnet32_free_ring_buffer(dev);
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* alloc init block, must 16 bit align */
|
|
|
+ dev->init_block = rt_malloc_align(sizeof(struct pcnet32_init_block), 16);
|
|
|
+ if (dev->init_block == RT_NULL)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "alloc memory for init block failed!");
|
|
|
+ rt_mq_delete(dev->rx_mqueue);
|
|
|
+ pcnet32_free_ring_buffer(dev);
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+ dev->init_block_dma_addr = (rt_ubase_t)rt_hw_vir2phy(dev->init_block);
|
|
|
+
|
|
|
+ dbg_log(DBG_LOG, "init block addr:%p size:%d\n", dev->init_block, sizeof(struct pcnet32_init_block));
|
|
|
+
|
|
|
+ /* fill init block */
|
|
|
+ dev->init_block->mode = 0;
|
|
|
+ dev->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 4);
|
|
|
+ dev->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
|
|
|
+ dev->init_block->tlen_rlen = (dev->tx_len_bits << 8) | dev->rx_len_bits;
|
|
|
+ int i = 0;
|
|
|
+ for (i = 0; i < ETH_ALEN; i++)
|
|
|
+ {
|
|
|
+ dev->init_block->phys_addr[i] = dev->dev_addr[i];
|
|
|
+ }
|
|
|
+ dev->init_block->filter[0] = 0x00000000;
|
|
|
+ dev->init_block->filter[1] = 0x00000000;
|
|
|
+ dev->init_block->rx_ring = dev->rx_ring_dma_addr;
|
|
|
+ dev->init_block->tx_ring = dev->tx_ring_dma_addr;
|
|
|
+
|
|
|
+ /* register init block, CSR1 save low 16 bit, CSR1 save high 16 bit */
|
|
|
+ pcnet32_wio_write_csr(iobase, CSR1, (dev->init_block_dma_addr & 0xffff));
|
|
|
+ pcnet32_wio_write_csr(iobase, CSR2, (dev->init_block_dma_addr >> 16) & 0xffff);
|
|
|
+
|
|
|
+ /* register intr */
|
|
|
+ if (rt_hw_interrupt_install(dev->irqno, rt_hw_pcnet32_isr, (void *) dev, "pcnet32") < 0)
|
|
|
+ {
|
|
|
+ LOG_E("install IRQ failed!\n");
|
|
|
+ rt_free_align(dev->init_block);
|
|
|
+ rt_mq_delete(dev->rx_mqueue);
|
|
|
+ pcnet32_free_ring_buffer(dev);
|
|
|
+ return RT_ERROR;
|
|
|
+ }
|
|
|
+ rt_hw_interrupt_umask(dev->irqno);
|
|
|
+
|
|
|
+ /* Start init */
|
|
|
+ pcnet32_wio_write_csr(iobase, CSR0, CSR0_INIT | CSR0_INTEN);
|
|
|
+ dbg_log(DBG_LOG, "card init done.\n");
|
|
|
+
|
|
|
+ /* add auto pad amd strip recv */
|
|
|
+ rt_uint16_t csr4 = pcnet32_wio_read_csr(iobase, CSR4);
|
|
|
+ pcnet32_wio_write_csr(iobase, CSR4, csr4 | CSR4_ASTRP_RCV | CSR4_APAD_XMT);
|
|
|
+
|
|
|
+ /* start work */
|
|
|
+ pcnet32_wio_write_csr(iobase, CSR0, CSR0_START | CSR0_INTEN);
|
|
|
+
|
|
|
+ pcnet32_print_init_block(dev);
|
|
|
+
|
|
|
+ eth_device_linkchange(&dev->parent, RT_TRUE);
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef RT_USING_DEVICE_OPS
|
|
|
+const static struct rt_device_ops pcnet32_ops =
|
|
|
+{
|
|
|
+ pcnet32_init,
|
|
|
+ RT_NULL,
|
|
|
+ RT_NULL,
|
|
|
+ RT_NULL,
|
|
|
+ RT_NULL,
|
|
|
+ pcnet32_control
|
|
|
+};
|
|
|
+#endif
|
|
|
+
|
|
|
+static rt_err_t pcnet32_init_hw(struct eth_device_pcnet32 *dev)
|
|
|
+{
|
|
|
+ rt_uint32_t iobase = dev->iobase;
|
|
|
+
|
|
|
+ /* reset card to 16 bit io mode */
|
|
|
+ pcnet32_wio_reset(iobase);
|
|
|
+
|
|
|
+ /* use dealy to wait reset done, at least 1 microsecond */
|
|
|
+ rt_thread_delay(1);
|
|
|
+
|
|
|
+ /* switch to 32 bit soft-style mode, use 32 bit struct */
|
|
|
+ pcnet32_wio_write_bcr(iobase, 20, 0x102);
|
|
|
+
|
|
|
+ /* stop card work */
|
|
|
+ pcnet32_wio_write_csr(iobase, 0, 0x4);
|
|
|
+
|
|
|
+ /* read mac addr */
|
|
|
+ rt_uint16_t mac0 = pcnet32_wio_read_mac(iobase, 0);
|
|
|
+ rt_uint16_t mac1 = pcnet32_wio_read_mac(iobase, 2);
|
|
|
+ rt_uint16_t mac2 = pcnet32_wio_read_mac(iobase, 4);
|
|
|
+
|
|
|
+ dev->dev_addr[0] = mac0 & 0xff;
|
|
|
+ dev->dev_addr[1] = (mac0 >> 8) & 0xff;
|
|
|
+ dev->dev_addr[2] = mac1 & 0xff;
|
|
|
+ dev->dev_addr[3] = (mac1 >> 8) & 0xff;
|
|
|
+ dev->dev_addr[4] = mac2 & 0xff;
|
|
|
+ dev->dev_addr[5] = (mac2 >> 8) & 0xff;
|
|
|
+
|
|
|
+ dbg_log(DBG_INFO, "MAC addr: %x:%x:%x:%x:%x:%x\n",
|
|
|
+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
|
|
|
+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+static int rt_hw_pcnet32_init(void)
|
|
|
+{
|
|
|
+ rt_memset(ð_dev, 0x0, sizeof(eth_dev));
|
|
|
+
|
|
|
+ if (pcnet32_get_pci(ð_dev) < 0)
|
|
|
+ {
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (pcnet32_init_hw(ð_dev) != RT_EOK)
|
|
|
+ {
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* set device opts */
|
|
|
+#ifdef RT_USING_DEVICE_OPS
|
|
|
+ eth_dev.parent.parent.ops = &pcnet32_ops;
|
|
|
+#else
|
|
|
+ eth_dev.parent.parent.init = pcnet32_init;
|
|
|
+ eth_dev.parent.parent.open = RT_NULL;
|
|
|
+ eth_dev.parent.parent.close = RT_NULL;
|
|
|
+ eth_dev.parent.parent.read = RT_NULL;
|
|
|
+ eth_dev.parent.parent.write = RT_NULL;
|
|
|
+ eth_dev.parent.parent.control = pcnet32_control;
|
|
|
+#endif
|
|
|
+ eth_dev.parent.parent.user_data = RT_NULL;
|
|
|
+ eth_dev.parent.eth_rx = pcnet32_rx;
|
|
|
+ eth_dev.parent.eth_tx = pcnet32_tx;
|
|
|
+
|
|
|
+ /* register ETH device */
|
|
|
+ if (eth_device_init(&(eth_dev.parent), DEV_NAME) != RT_EOK)
|
|
|
+ {
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+INIT_DEVICE_EXPORT(rt_hw_pcnet32_init);
|
jasonhu