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@@ -12,17 +12,11 @@
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* 2017-06-08 tanek first implementation
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*/
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#include <rtthread.h>
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+#include <netif/ethernetif.h>
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+#include "lwipopts.h"
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#include "board.h"
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#include <rtdevice.h>
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-
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-#ifdef RT_USING_FINSH
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#include <finsh.h>
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-#endif
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-
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-#ifdef RT_USING_LWIP
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-
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-#include <netif/ethernetif.h>
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-#include "lwipopts.h"
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/* debug option */
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//#define DEBUG
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@@ -35,68 +29,39 @@
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#define STM32_ETH_PRINTF(...)
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#endif
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-#define MAX_ADDR_LEN 6
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-
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-#define DM9161_PHY_ADDRESS 0x01U
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-
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-
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-/* DP83848C and DM9161 PHY Registers is the same */
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-#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
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-#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
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-#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
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-#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
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-#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
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-#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
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-#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
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-#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX .DM9161 NO */
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-
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-/* PHY Extended Registers only for DP83848C */
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-#define PHY_REG_STS 0x10 /* Status Register */
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-#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
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-#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
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-#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
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-#define PHY_REG_RECR 0x15 /* Receive Error Counter */
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-#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
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-#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
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-#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
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-#define PHY_REG_PHYCR 0x19 /* PHY Control Register */
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-#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
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-#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
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-#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
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-
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-/* PHY Extended Registers only for DM9161 */
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-#define PHY_REG_DSCR 0x10 /* Specified Congfiguration Register */
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-#define PHY_REG_DSCSR 0x11 /* Specified Congfiguration and Status Register */
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-#define PHY_REG_10BTCSR 0x12 /* 10Base-T Status/Control Register */
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-#define PHY_REG_PWDOR 0x13 /* Power Down Control Register */
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-#define PHY_REG_CONGFIG 0x14 /* Specified Congfig Register */
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-#define PHY_REG_INTERRUPT 0x15 /* Specified interrupt Register */
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-#define PHY_REG_SRECR 0x16 /* Specified Receive Error Counter */
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-#define PHY_REG_DISCR 0x17 /* Specified Disconnect Counter Register */
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-#define PHY_REG_RLSR 0x18 /* Hardware reset latch state Register */
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-#define PHY_REG_PSCR 0x1D /* Power Saving control register */
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-
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-/* Register BMCR bit defination */
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-#define PHY_BMCR_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
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-#define PHY_BMCR_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
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-#define PHY_BMCR_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
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-#define PHY_BMCR_HALFD_10M 0x0000 /* Half Duplex 10MBit */
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-#define PHY_BMCR_AUTO_NEG 0x1000 /* Select Auto Negotiation */
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-
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-#define PHY_BMCR_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
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-#define PHY_BMCR_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
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-
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-#define PHY_BMSR_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
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-#define PHY_BMSR_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
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-
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-#define PHY_DSCSR_100FDX ((uint16_t)0x8000U)
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-#define PHY_DSCSR_100HDX ((uint16_t)0x4000U)
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-#define PHY_DSCSR_10FDX ((uint16_t)0x2000U)
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-#define PHY_DSCSR_10HDX ((uint16_t)0x1000U)
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-
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-#define PHY_INT_LINK_MASK ((uint16_t)0x0C00U)
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-#define PHY_INT_LINK_CHANGE ((uint16_t)0x0004U)
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+/* RMII GPIO
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+ ETH_MDIO -------------------------> PA2
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+ ETH_MDC --------------------------> PC1
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+ ETH_RMII_REF_CLK------------------> PA1
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+ ETH_RMII_CRS_DV ------------------> PA7
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+ ETH_RMII_RXD0 --------------------> PC4
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+ ETH_RMII_RXD1 --------------------> PC5
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+ ETH_RMII_TX_EN -------------------> PB11
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+ ETH_RMII_TXD0 --------------------> PG13
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+ ETH_RMII_TXD1 --------------------> PG14
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+*/
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+#define ETH_MDIO_PORN GPIOA
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+#define ETH_MDIO_PIN GPIO_PIN_2
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+#define ETH_MDC_PORN GPIOC
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+#define ETH_MDC_PIN GPIO_PIN_1
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+#define ETH_RMII_REF_CLK_PORN GPIOA
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+#define ETH_RMII_REF_CLK_PIN GPIO_PIN_1
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+#define ETH_RMII_CRS_DV_PORN GPIOA
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+#define ETH_RMII_CRS_DV_PIN GPIO_PIN_7
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+#define ETH_RMII_RXD0_PORN GPIOC
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+#define ETH_RMII_RXD0_PIN GPIO_PIN_4
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+#define ETH_RMII_RXD1_PORN GPIOC
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+#define ETH_RMII_RXD1_PIN GPIO_PIN_5
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+#define ETH_RMII_TX_EN_PORN GPIOG
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+#define ETH_RMII_TX_EN_PIN GPIO_PIN_11
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+#define ETH_RMII_TXD0_PORN GPIOG
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+#define ETH_RMII_TXD0_PIN GPIO_PIN_13
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+#define ETH_RMII_TXD1_PORN GPIOB
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+#define ETH_RMII_TXD1_PIN GPIO_PIN_13
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+
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+#define PHY_ADDRESS 0x01
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+#define MAX_ADDR_LEN 6
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struct rt_stm32_eth
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{
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/* inherit from ethernet device */
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@@ -110,75 +75,13 @@ struct rt_stm32_eth
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};
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-ALIGN(4) ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB];
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-ALIGN(4) ETH_DMADescTypeDef DMATxDscrTab[ETH_TXBUFNB];
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-ALIGN(4) rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE];
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-ALIGN(4) rt_uint8_t Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
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+static ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
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+static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
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static rt_bool_t tx_is_waiting = RT_FALSE;
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static ETH_HandleTypeDef EthHandle;
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static struct rt_stm32_eth stm32_eth_device;
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static struct rt_semaphore tx_wait;
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-void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
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-{
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- GPIO_InitTypeDef GPIO_InitStruct;
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- if(heth->Instance==ETH)
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- {
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- /* USER CODE BEGIN ETH_MspInit 0 */
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-
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- /* USER CODE END ETH_MspInit 0 */
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- /* Peripheral clock enable */
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- __HAL_RCC_ETH_CLK_ENABLE();
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- __HAL_RCC_GPIOA_CLK_ENABLE();
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- __HAL_RCC_GPIOC_CLK_ENABLE();
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- __HAL_RCC_GPIOG_CLK_ENABLE();
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-
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- /**ETH GPIO Configuration
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- PC1 ------> ETH_MDC
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- PA1 ------> ETH_REF_CLK
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- PA2 ------> ETH_MDIO
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- PA7 ------> ETH_CRS_DV
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- PC4 ------> ETH_RXD0
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- PC5 ------> ETH_RXD1
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- PG11 ------> ETH_TX_EN
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- PG13 ------> ETH_TXD0
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- PB13 ------> ETH_TXD1
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- */
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- GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
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- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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- GPIO_InitStruct.Pull = GPIO_NOPULL;
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- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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- GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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-
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- GPIO_InitStruct.Pin = GPIO_PIN_13;
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- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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- GPIO_InitStruct.Pull = GPIO_NOPULL;
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- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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- GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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- HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
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-
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- GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
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- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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- GPIO_InitStruct.Pull = GPIO_NOPULL;
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- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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- GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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-
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- GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13;
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- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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- GPIO_InitStruct.Pull = GPIO_NOPULL;
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- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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- GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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- HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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-
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- /* ETH interrupt Init */
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- HAL_NVIC_SetPriority(ETH_IRQn, 1, 0);
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- HAL_NVIC_EnableIRQ(ETH_IRQn);
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- }
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-
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-}
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-
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/* interrupt service routine */
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void ETH_IRQHandler(void)
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{
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@@ -213,165 +116,7 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
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rt_kprintf("eth err\n");
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}
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-/**
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-* @brief This function handles EXTI line[9:5] interrupts.
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-*/
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-void EXTI9_5_IRQHandler(void)
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-{
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- HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
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-}
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-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
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-{
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- uint32_t reg_value = 0;
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- int i = 10;
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-
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- if (GPIO_Pin == GPIO_PIN_6)
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- {
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- HAL_ETH_ReadPHYRegister(&EthHandle, PHY_REG_INTERRUPT, ®_value);
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-
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- if (reg_value & PHY_INT_LINK_CHANGE)
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- {
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- do
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- {
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- HAL_ETH_ReadPHYRegister(&EthHandle, PHY_REG_BMSR, ®_value);
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- if (reg_value & PHY_BMSR_LINKED_STATUS)
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- {
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- eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
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- STM32_ETH_PRINTF("eth phy link up\n");
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- return ;
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- }
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- }
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- while (i--);
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-
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- eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
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- STM32_ETH_PRINTF("eth phy link down\n");
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- }
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- }
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-}
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-
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-static void phy_register_read(int reg)
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-{
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- uint32_t value;
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- if (reg > 0xFF || reg < 0)
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- rt_kprintf("reg address error: %d", reg);
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-
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- HAL_ETH_ReadPHYRegister(&EthHandle, reg, &value);
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-
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- rt_kprintf("reg: %02X ==> %08X\n", reg, value);
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-
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-}
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-#ifdef RT_USING_FINSH
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-FINSH_FUNCTION_EXPORT_ALIAS(phy_register_read, phyrd, read phy registers);
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-#endif
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-
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-static void phy_register_write(rt_uint16_t reg, rt_uint32_t value)
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-{
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- if (reg > 0xFF)
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- rt_kprintf("reg address error: %d", reg);
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-
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- HAL_ETH_WritePHYRegister(&EthHandle, reg, value);
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-
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- rt_kprintf("reg: %02X ==> %08X\n", reg, value);
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-
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-}
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-#ifdef RT_USING_FINSH
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-FINSH_FUNCTION_EXPORT_ALIAS(phy_register_write, phywr, write phy registers);
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-#endif
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-
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-
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-void eth_link_exit_config(void)
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-{
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- GPIO_InitTypeDef GPIO_InitStruct;
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-
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- __HAL_RCC_GPIOH_CLK_ENABLE();
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-
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- /*Configure GPIO pin : PH6 */
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- GPIO_InitStruct.Pin = GPIO_PIN_6;
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- GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
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- GPIO_InitStruct.Pull = GPIO_NOPULL;
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- HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
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-
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- /* EXTI9_5_IRQn interrupt configuration */
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- HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);
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- HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
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-}
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-
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-rt_err_t eth_phy_init(void)
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-{
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- uint32_t reg_value = 0;
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- int i, j, k;
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-
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- HAL_ETH_WritePHYRegister(&EthHandle, PHY_REG_BMCR, PHY_RESET);
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-
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- for (i = 0x10000; i > 0; i--)
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- {
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- HAL_ETH_ReadPHYRegister(&EthHandle, PHY_REG_BMCR, ®_value);
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- if (!(reg_value & (PHY_BMCR_RESET | PHY_BMCR_POWERDOWN)))
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- {
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- STM32_ETH_PRINTF("PHY Reset Finsh\n");
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- break;
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- }
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- }
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- if (i <= 0)
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- {
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- STM32_ETH_PRINTF("PHY Power Up Error: %08X\n", reg_value);
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- return -RT_ETIMEOUT;
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- }
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-
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- HAL_ETH_WritePHYRegister(&EthHandle, PHY_REG_BMCR, PHY_AUTONEGOTIATION);
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- for (j = 0x10000; j > 0; j--)
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- {
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- HAL_ETH_ReadPHYRegister(&EthHandle, PHY_REG_BMSR, ®_value);
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- if (reg_value & PHY_BMSR_AUTONEGO_COMPLETE)
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- {
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- STM32_ETH_PRINTF("Autonegotiation Complete\n");
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- /* Autonegotiation Complete. */
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- break;
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- }
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- }
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- if (j <= 0)
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- {
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- STM32_ETH_PRINTF("Autonegotiation failed: %08X\n", reg_value);
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- return -RT_ETIMEOUT;
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- }
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-
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- /* Check the link status. */
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- for (k = 0x10000; k > 0; k--)
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- {
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- HAL_ETH_ReadPHYRegister(&EthHandle, PHY_REG_BMSR, ®_value);
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- if (reg_value & PHY_LINKED_STATUS)
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- {
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- /* Link */
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- /* Link is on, get connection info */
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- HAL_ETH_ReadPHYRegister(&EthHandle, PHY_REG_DSCSR, ®_value);
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- if ((reg_value & (PHY_DSCSR_100FDX | PHY_DSCSR_100HDX)))
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- STM32_ETH_PRINTF("100M ");
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- else
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- STM32_ETH_PRINTF("10M ");
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-
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- if ((reg_value & (PHY_DSCSR_100FDX | PHY_DSCSR_10FDX)))
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- STM32_ETH_PRINTF("Full");
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- else
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- STM32_ETH_PRINTF("Half");
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- STM32_ETH_PRINTF(" Duplex Operation Mode\n");
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- break;
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- }
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- }
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- if (k <= 0)
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- {
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- STM32_ETH_PRINTF("check link status failed: %08X\n", reg_value);
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- return -RT_ETIMEOUT;
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- }
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-
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- HAL_ETH_WritePHYRegister(&EthHandle, PHY_REG_INTERRUPT, PHY_INT_LINK_MASK);
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-
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- STM32_ETH_PRINTF("Reset try: %d\n", i);
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- STM32_ETH_PRINTF("Autonegotiation try: %d\n", j);
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- STM32_ETH_PRINTF("Check try: %d\n", k);
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-
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- return RT_EOK;
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-}
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/* initialize the interface */
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static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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@@ -380,6 +125,7 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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__HAL_RCC_ETH_CLK_ENABLE();
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+
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/* ETHERNET Configuration --------------------------------------------------*/
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EthHandle.Instance = ETH;
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EthHandle.Init.MACAddr = (rt_uint8_t*)&stm32_eth_device.dev_addr[0];
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@@ -389,8 +135,7 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
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EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
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- //EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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- EthHandle.Init.PhyAddress = DM9161_PHY_ADDRESS;
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+ EthHandle.Init.PhyAddress = PHY_ADDRESS;
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HAL_ETH_DeInit(&EthHandle);
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@@ -403,7 +148,7 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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{
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STM32_ETH_PRINTF("eth hardware init faild...\n");
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}
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-
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+
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/* Initialize Tx Descriptors list: Chain Mode */
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HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
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@@ -420,8 +165,6 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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STM32_ETH_PRINTF("eth hardware start faild...\n");
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}
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- eth_phy_init();
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- eth_link_exit_config();
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return RT_EOK;
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}
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@@ -526,9 +269,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
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while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
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{
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/* Copy data to Tx buffer*/
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- memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset),
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- (uint8_t*)((uint8_t*)q->payload + payloadoffset),
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- (ETH_TX_BUF_SIZE - bufferoffset) );
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+ memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
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/* Point to next descriptor */
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DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
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@@ -550,9 +291,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
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}
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/* Copy the remaining bytes */
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- memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset),
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- (uint8_t*)((uint8_t*)q->payload + payloadoffset),
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- byteslefttocopy );
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+ memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
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bufferoffset = bufferoffset + byteslefttocopy;
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framelength = framelength + byteslefttocopy;
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}
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@@ -627,7 +366,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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state = HAL_ETH_GetReceivedFrame_IT(&EthHandle);
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if (state != HAL_OK)
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{
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- //STM32_ETH_PRINTF("receive frame faild\n");
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+ STM32_ETH_PRINTF("receive frame faild\n");
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return NULL;
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}
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@@ -721,6 +460,72 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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return p;
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}
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|
+static void NVIC_Configuration(void)
|
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+{
|
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+ /* Enable the Ethernet global Interrupt */
|
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+ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
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+ HAL_NVIC_EnableIRQ(ETH_IRQn);
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+}
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+
|
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+/*
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+ * GPIO Configuration for ETH
|
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+ */
|
|
|
+static void GPIO_Configuration(void)
|
|
|
+{
|
|
|
+ GPIO_InitTypeDef GPIO_InitStructure;
|
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|
+
|
|
|
+ STM32_ETH_PRINTF("GPIO_Configuration...\n");
|
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|
+
|
|
|
+ /* Enable SYSCFG clock */
|
|
|
+ __HAL_RCC_ETH_CLK_ENABLE();
|
|
|
+ __HAL_RCC_GPIOA_CLK_ENABLE();
|
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|
+ __HAL_RCC_GPIOB_CLK_ENABLE();
|
|
|
+ __HAL_RCC_GPIOC_CLK_ENABLE();
|
|
|
+ __HAL_RCC_GPIOG_CLK_ENABLE();
|
|
|
+
|
|
|
+ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
|
|
+ GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
|
|
+ GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
|
|
+ GPIO_InitStructure.Pull = GPIO_NOPULL;
|
|
|
+
|
|
|
+ GPIO_InitStructure.Pin = ETH_MDIO_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_MDIO_PORN,&GPIO_InitStructure);
|
|
|
+ GPIO_InitStructure.Pin = ETH_MDC_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_MDC_PORN,&GPIO_InitStructure);
|
|
|
+
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_REF_CLK_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_REF_CLK_PORN,&GPIO_InitStructure);
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_CRS_DV_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_CRS_DV_PORN,&GPIO_InitStructure);
|
|
|
+
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_REF_CLK_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_REF_CLK_PORN,&GPIO_InitStructure);
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_CRS_DV_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_CRS_DV_PORN,&GPIO_InitStructure);
|
|
|
+
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_RXD0_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_RXD0_PORN,&GPIO_InitStructure);
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_RXD1_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_RXD1_PORN,&GPIO_InitStructure);
|
|
|
+
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_TX_EN_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_TX_EN_PORN,&GPIO_InitStructure);
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_TXD0_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_TXD0_PORN,&GPIO_InitStructure);
|
|
|
+ GPIO_InitStructure.Pin = ETH_RMII_TXD1_PIN;
|
|
|
+ HAL_GPIO_Init(ETH_RMII_TXD1_PORN,&GPIO_InitStructure);
|
|
|
+
|
|
|
+ HAL_NVIC_SetPriority(ETH_IRQn,1,0);
|
|
|
+ HAL_NVIC_EnableIRQ(ETH_IRQn);
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
|
|
+{
|
|
|
+ GPIO_Configuration();
|
|
|
+ NVIC_Configuration();
|
|
|
+}
|
|
|
+
|
|
|
static int rt_hw_stm32_eth_init(void)
|
|
|
{
|
|
|
rt_err_t state;
|
|
|
@@ -763,7 +568,9 @@ static int rt_hw_stm32_eth_init(void)
|
|
|
{
|
|
|
STM32_ETH_PRINTF("eth_device_init faild: %d\r\n", state);
|
|
|
}
|
|
|
+
|
|
|
+ eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); //linkup the e0 for lwip to check
|
|
|
+
|
|
|
return state;
|
|
|
}
|
|
|
-INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
|
|
|
-#endif
|
|
|
+INIT_APP_EXPORT(rt_hw_stm32_eth_init);
|
Bernard Xiong