Merge remote-tracking branch 'remotes/origin/gitee_master'

bsp/ti-tms320c6678/.ccsproject

@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+	<deviceVariant value="TMS320C66XX.TMS320C6678"/>
+	<deviceFamily value="C6000"/>
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+	<isElfFormat value="true"/>
+	<rts value="libc.a"/>
+	<templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/>
+	<isTargetManual value="false"/>
+</projectOptions>

bsp/ti-tms320c6678/.cproject

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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+				<externalSettings/>
+				<extensions>
+					<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
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+					<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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bsp/ti-tms320c6678/.project

@@ -0,0 +1,154 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ti-tms320c6678</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
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+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
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+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
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+	<natures>
+		<nature>com.ti.ccstudio.core.ccsNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>clock.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/clock.c</locationURI>
+		</link>
+		<link>
+			<name>components.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/components.c</locationURI>
+		</link>
+		<link>
+			<name>context.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/context.asm</locationURI>
+		</link>
+		<link>
+			<name>contextinc.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/contextinc.asm</locationURI>
+		</link>
+		<link>
+			<name>cpu.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/cpu.c</locationURI>
+		</link>
+		<link>
+			<name>cpuport.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/cpuport.c</locationURI>
+		</link>
+		<link>
+			<name>device.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/device.c</locationURI>
+		</link>
+		<link>
+			<name>idle.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/idle.c</locationURI>
+		</link>
+		<link>
+			<name>interrupt.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/interrupt.c</locationURI>
+		</link>
+		<link>
+			<name>intexc.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/intexc.asm</locationURI>
+		</link>
+		<link>
+			<name>ipc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/ipc.c</locationURI>
+		</link>
+		<link>
+			<name>irq.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/irq.c</locationURI>
+		</link>
+		<link>
+			<name>kservice.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/kservice.c</locationURI>
+		</link>
+		<link>
+			<name>mem.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/mem.c</locationURI>
+		</link>
+		<link>
+			<name>memheap.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/memheap.c</locationURI>
+		</link>
+		<link>
+			<name>mempool.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/mempool.c</locationURI>
+		</link>
+		<link>
+			<name>object.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/object.c</locationURI>
+		</link>
+		<link>
+			<name>scheduler.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/scheduler.c</locationURI>
+		</link>
+		<link>
+			<name>signal.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/signal.c</locationURI>
+		</link>
+		<link>
+			<name>slab.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/slab.c</locationURI>
+		</link>
+		<link>
+			<name>stack.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/stack.c</locationURI>
+		</link>
+		<link>
+			<name>thread.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/thread.c</locationURI>
+		</link>
+		<link>
+			<name>timer.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/src/timer.c</locationURI>
+		</link>
+		<link>
+			<name>trap.c</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/trap.c</locationURI>
+		</link>
+		<link>
+			<name>vector.asm</name>
+			<type>1</type>
+			<locationURI>PARENT-2-PROJECT_LOC/git-source/rt-thread/libcpu/ti-dsp/c6x/vector.asm</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

bsp/ti-tms320c6678/.settings/org.eclipse.cdt.codan.core.prefs

@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false

bsp/ti-tms320c6678/.settings/org.eclipse.cdt.debug.core.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker

bsp/ti-tms320c6678/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,12 @@
+eclipse.preferences.version=1
+encoding//Debug/applications/subdir_rules.mk=UTF-8
+encoding//Debug/applications/subdir_vars.mk=UTF-8
+encoding//Debug/common/subdir_rules.mk=UTF-8
+encoding//Debug/common/subdir_vars.mk=UTF-8
+encoding//Debug/driver/subdir_rules.mk=UTF-8
+encoding//Debug/driver/subdir_vars.mk=UTF-8
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8

bsp/ti-tms320c6678/KeyStone.cmd

@@ -0,0 +1,47 @@
+/****************************************************************************/
+/*                                                                          */
+/*                               M6678.cmd                                  */
+/*                         Copyright (c): NUDT                              */
+/*                                                                          */
+/*                                                                          */
+/*    Description: This file is a sample linker command file that can be    */
+/*                 used for linking programs built with the C compiler and  */
+/*                 running the resulting .out file on an M6678              */
+/*                 device.  Use it as a guideline.  You will want to        */
+/*                 change the memory layout to match your specific C6xxx    */
+/*                 target system.  You may want to change the allocation    */
+/*                 scheme according to the size of your program.            */
+/*                                                                          */
+/*                                                                          */
+/****************************************************************************/
+
+-heap  0x800
+-stack 0x1000
+
+MEMORY
+{
+	VECTORS:		o = 0x00800000  l = 0x00000200
+	LL2_CODE:		o = 0x00800200  l = 0x0001FE00
+	LL2_RW_DATA: 	o = 0x00820000  l = 0x00020000   /*set memory protection attribitue as read/write*/
+}
+
+SECTIONS
+{
+	.vecs       	>    VECTORS
+
+	.text           >    LL2_CODE
+	.cinit          >    LL2_CODE
+	.const          >    LL2_CODE
+	.switch         >    LL2_CODE
+	.stack          >    LL2_RW_DATA
+	GROUP
+	{
+		.neardata
+		.rodata
+		.bss
+	} 		>    LL2_RW_DATA
+	.far            >    LL2_RW_DATA
+	.fardata        >    LL2_RW_DATA
+	.cio            >    LL2_RW_DATA
+	.sysmem         >    LL2_RW_DATA
+}

bsp/ti-tms320c6678/README.md

@@ -0,0 +1,49 @@
+### 1. 简介
+
+TMS320C6678是TI基于KeyStone的多核固定浮点数字信号处理器，DSP集成C66x CorePac，每个核心在1GHz至1.25 GHz的运行。该设备支持高性能的信号处理应用，如任务关键，医疗成像，测试和自动化。
+
+### 2. 编译说明
+
+TMS320C6678 工程的编译和下载要使用的是 TI 官方提供的 Code Composer Studio。在本工程使用的是 CCS5.5 版本编译调试，CCS5.5 Compiler version:TIv8.3.5进行编译，需要安装TI提供的CSL库pdk_C6678_1_1_2_6。
+
+### 2.1 导入工程
+
+首先打开 Code Composer Studio，点击 Project -> Import CCS Projects...
+
+![输入图片说明](figures/import(1).png)
+
+在打开的对话框中，点击 Select search -> directory 右边的 Browse... 选择 TMS320C6678 BSP 所在文件夹，如图所示。选择完成后点击 Finish 完成导入。
+
+![输入图片说明](figures/import(2).png)
+
+### 2.2 检查工程路径和编译器
+
+- 检查工程路径是否正确，是否成功安装pdk_C6678_1_1_2_6，本工程安装路径为C盘。
+
+![输入图片说明](figures/filepath.png)
+
+- 检查编译器版本，本工程使用的是TIv8.3.5
+
+![输入图片说明](figures/general.jpg)
+
+### 3. 编译工程
+
+导入工程后，选中导入的 ti-tms320c6678 工程，右键点击，在弹出的菜单中选择 Build Project 即可开始编译。
+
+### 4. 加载和调试
+
+编译完成后，可以开始加载和调试。将板子和 XDS560 仿真器连接，仿真器可以将编译生成的可执行文件加载到L2或MSMC执行。
+
+- 如下图ti-tms320c6678.out是编译之后生成的可执行文件。
+
+![输入图片说明](figures/debug(1).png)
+
+- 本工程目前只支持单核运行，按如下图加载可执行文件。
+
+![输入图片说明](figures/load.png)
+
+- 加载可执行文件完成后，CCS将进入调试模式，可以选择继续运行、单步调试、复位等操作。
+
+![输入图片说明](figures/debug(2).png)
+
+到此，可以开启tms320c6678 + rt-thread的愉快旅程了 :smile: 。

bsp/ti-tms320c6678/applications/board.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include "board.h"
+#include "interrupt.h"
+#include "drv_timer.h"
+#include "common.h"
+
+#include <rtthread.h>
+
+/**
+ * This function will initial board.
+ */
+void rt_hw_board_init(void)
+{
+    // initial CPU core
+    keystone_cpu_init();
+
+    // initial interrupt controller
+    rt_hw_interrupt_init();
+
+    // initial system timer
+    rt_hw_system_timer_init();
+
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    rt_hw_system_timer_start();
+}

bsp/ti-tms320c6678/applications/board.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define RT_HW_HEAP_BEGIN    (void*)0x0C000000
+#define RT_HW_HEAP_END      (void*)0x0C100000
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+

bsp/ti-tms320c6678/applications/main.c

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+void rt_init_thread_entry(void *parameter)
+{
+    rt_kprintf("hello rt-thread\n");
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 4096, 3, 200);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    } else {
+        return -1;
+    }
+
+    return 0;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+	
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+void main(void)
+{
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    for(;;){}
+}
+

bsp/ti-tms320c6678/common/common.c

@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include "common.h"
+
+CSL_BootcfgRegs * gp_bootcfg_regs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
+CSL_CgemRegs * gp_cgem_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
+CSL_TmrPlusRegs * gp_timer_regs[9] = {
+    (CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_3_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_4_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_5_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_6_REGS,
+    (CSL_TmrPlusRegs *)CSL_TIMER_7_REGS,
+    (CSL_TmrPlusRegs *)(CSL_TIMER_7_REGS+(CSL_TIMER_7_REGS-CSL_TIMER_6_REGS))
+};
+
+void cpu_interrupt_init(void)
+{
+    //clear interrupt and excpetion events
+    ICR = IFR;
+    ECR = EFR;
+    IER = 3;     //disable all interrupts
+
+    /* disable event combine */
+    gp_cgem_regs->EVTMASK[0] = 0xffffffff;
+    gp_cgem_regs->EVTMASK[1] = 0xffffffff;
+    gp_cgem_regs->EVTMASK[2] = 0xffffffff;
+    gp_cgem_regs->EVTMASK[3] = 0xffffffff;
+
+     /*Clear all CPU events*/
+    gp_cgem_regs->EVTCLR[0] = 0xFFFFFFFF;
+    gp_cgem_regs->EVTCLR[1] = 0xFFFFFFFF;
+    gp_cgem_regs->EVTCLR[2] = 0xFFFFFFFF;
+    gp_cgem_regs->EVTCLR[3] = 0xFFFFFFFF;
+
+    /*Interrupt Service Table Pointer to begining of LL2 memory*/
+    ISTP = 0x800000;
+}
+
+void keystone_cpu_init(void)
+{
+    /* clear all interrupt flag/status, setup ISTP to begining of LL2 */
+    cpu_interrupt_init();
+}
+
+/*===============================Timer=================================*/
+void reset_timer(int timer_num)
+{
+    if(gp_timer_regs[timer_num]->TGCR)
+    {
+        gp_timer_regs[timer_num]->TGCR = 0;
+        gp_timer_regs[timer_num]->TCR= 0;
+    }
+}
+
+void timer64_init(Timer64_Config * tmrCfg)
+{
+    reset_timer(tmrCfg->timer_num);
+
+    gp_timer_regs[tmrCfg->timer_num]->CNTLO = 0;
+    gp_timer_regs[tmrCfg->timer_num]->CNTHI = 0;
+
+    /*please note, in clock mode, two timer periods generate a clock,
+    one timer period output high voltage level, the other timer period
+    output low voltage level, so, the timer period should be half to the
+    desired output clock period*/
+    if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
+    {
+        tmrCfg->period = tmrCfg->period/2;
+    }
+
+    /*the value written into period register is the expected value minus one*/
+    gp_timer_regs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
+    gp_timer_regs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
+    if(tmrCfg->reload_period>1)
+    {
+        gp_timer_regs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
+        gp_timer_regs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
+    }
+
+    if(TIMER_WATCH_DOG == tmrCfg->timerMode)
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TGCR =
+            /*Select watch-dog mode*/
+            (CSL_TMR_TIMMODE_WDT << CSL_TMR_TGCR_TIMMODE_SHIFT)
+            /*Remove the timer from reset*/
+            | (CSL_TMR_TGCR_TIMLORS_MASK)
+            | (CSL_TMR_TGCR_TIMHIRS_MASK);
+    }
+    else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
+            /*for plus featuers, dual 32-bit unchained timer mode should be used*/
+            | (CSL_TMR_TIMMODE_DUAL_UNCHAINED << CSL_TMR_TGCR_TIMMODE_SHIFT)
+            /*Remove the timer from reset*/
+            | (CSL_TMR_TGCR_TIMLORS_MASK);
+
+        //in plus mode, interrupt/event must be enabled manually
+        gp_timer_regs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
+    }
+    else
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TGCR =
+            /*Select 64-bit general timer mode*/
+            (CSL_TMR_TIMMODE_GPT << CSL_TMR_TGCR_TIMMODE_SHIFT)
+            /*Remove the timer from reset*/
+            | (CSL_TMR_TGCR_TIMLORS_MASK)
+            | (CSL_TMR_TGCR_TIMHIRS_MASK);
+    }
+
+    /*make timer stop with emulation*/
+    gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gp_timer_regs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
+        ~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
+
+    if(TIMER_WATCH_DOG == tmrCfg->timerMode)
+    {
+        /*enable watchdog timer*/
+        gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
+            | (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT);
+
+        gp_timer_regs[tmrCfg->timer_num]->TCR =
+            (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
+            | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
+            /*The timer is enabled continuously*/
+            | (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
+            | ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
+            /*select pulse mode*/
+            | (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
+            | (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
+            | (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
+            | (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
+
+        /*active watchdog timer*/
+        gp_timer_regs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
+            | (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT);
+    }
+    else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode)
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TCR =
+            (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
+            | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
+            /*The timer is enabled one-shot*/
+            | (CSL_TMR_ENAMODE_ENABLE << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
+            | ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
+            /*select pulse mode*/
+            | (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
+            | (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
+            | (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
+            | (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
+    }
+    else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TCR =
+            (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
+            | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
+            /*The timer is enabled continuously*/
+            | (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
+            | ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
+            /*select clock mode*/
+            | (CSL_TMR_CP_CLOCK << CSL_TMR_TCR_CP_LO_SHIFT)
+            | (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
+            | (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
+            | (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
+    }
+    else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TCR =
+            (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
+            | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
+            /*The timer is enabled continuously with period reload*/
+            | (CSL_TMR_ENAMODE_CONT_RELOAD << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
+            | ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
+            /*select clock mode*/
+            | (CSL_TMR_CP_CLOCK << CSL_TMR_TCR_CP_LO_SHIFT)
+            | (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
+            | (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
+            | (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
+    }
+    else     /*TIMER_PERIODIC_PULSE*/
+    {
+        gp_timer_regs[tmrCfg->timer_num]->TCR =
+            (CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
+            | (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
+            /*The timer is enabled continuously*/
+            | (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
+            | ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
+            /*select clock mode*/
+            | (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
+            | (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
+            | (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
+            | (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
+    }
+}

bsp/ti-tms320c6678/common/common.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __COMMON_H__
+#define __COMMON_H__
+
+#include <c6x.h>
+#include <cslr_cgem.h>
+#include <cslr_device.h>
+#include <cslr_bootcfg.h>
+#include <cslr_tmr.h>
+#include <csl_tmr.h>
+
+/* DSP core clock speed in Hz */
+#define DSP_CORE_SPEED_HZ 	1000000000
+
+extern CSL_CgemRegs * gp_cgem_regs;
+extern CSL_BootcfgRegs * gp_bootcfg_regs;
+
+/*----------------------Timer plus registers definition----------------*/
+typedef struct {
+    volatile unsigned int PID12;
+    volatile unsigned int EMUMGT_CLKSPD;
+    volatile unsigned int GPINT_EN;
+    volatile unsigned int GPDIR_DAT;
+    volatile unsigned int CNTLO;
+    volatile unsigned int CNTHI;
+    volatile unsigned int PRDLO;
+    volatile unsigned int PRDHI;
+    volatile unsigned int TCR;
+    volatile unsigned int TGCR;
+    volatile unsigned int WDTCR;
+    volatile unsigned int TLGC;
+    volatile unsigned int TLMR;
+    volatile unsigned int RELLO;
+    volatile unsigned int RELHI;
+    volatile unsigned int CAPLO;
+    volatile unsigned int CAPHI;
+    volatile unsigned int INTCTL_STAT;
+    volatile unsigned char  RSVD0[24];
+    volatile unsigned int TIMERLO_COMPARE_REG[8];
+    volatile unsigned char  RSVD1[32];
+} CSL_TmrPlusRegs;
+
+#define TMR_TCR_READRSTMODE_HI_SHIFT   (26)
+#define TMR_TCR_CAPEVTMODE_LO_SHIFT    (12)
+#define TMR_TCR_CAPMODE_LO_SHIFT       (11)
+#define TMR_TCR_READRSTMODE_LO_SHIFT   (10)
+
+#define TMR_TCR_READRSTMODE_HI_MASK    (1<<26)
+#define TMR_TCR_CAPEVTMODE_LO_MASK     (3<<12)
+#define TMR_TCR_CAPMODE_LO_MASK        (1<<11)
+#define TMR_TCR_READRSTMODE_LO_MASK    (1<<10)
+
+#define TMR_TGCR_PLUSEN_SHIFT          4
+#define TMR_TGCR_PLUSEN_MASK           (1<<4)
+
+#define TMR_INTCTLSTAT_EN_ALL_CLR_ALL  0x000F000F
+
+#define CSL_TMR_WDTCR_WDKEY_CMD1       (0x0000A5C6u)
+#define CSL_TMR_WDTCR_WDKEY_CMD2       (0x0000DA7Eu)
+
+#define CSL_TMR_ENAMODE_CONT_RELOAD    3
+
+extern CSL_TmrPlusRegs * gp_timer0_regs;
+extern CSL_TmrPlusRegs * gp_timer1_regs;
+extern CSL_TmrPlusRegs * gp_timer2_regs;
+extern CSL_TmrPlusRegs * gp_timer3_regs;
+extern CSL_TmrPlusRegs * gp_timer4_regs;
+extern CSL_TmrPlusRegs * gp_timer5_regs;
+extern CSL_TmrPlusRegs * gp_timer6_regs;
+extern CSL_TmrPlusRegs * gp_timer7_regs;
+extern CSL_TmrPlusRegs * gp_timer8_regs;
+extern CSL_TmrPlusRegs * gp_timer_regs[];
+
+typedef enum
+{
+    TIMER_ONE_SHOT_PULSE = 0,     /*generate one shot pulse with timer*/
+    TIMER_PERIODIC_PULSE,         /*generate periodic pulse with timer*/
+    TIMER_PERIODIC_CLOCK,         /*generate periodic clock with timer*/
+    /*generate periodic square wave with period reload feature, the difference
+    between wave and clock is the duty cycle of clock is always 50%*/
+    TIMER_PERIODIC_WAVE,
+    TIMER_WATCH_DOG               /*configure timer as watch dog*/
+}TTimerMode;
+
+typedef struct  {
+    int timer_num;                /*select one timer*/
+    TTimerMode timerMode;         /*select function of the timer*/
+    unsigned long long period;    /*in the unit of DSP core clock/6*/
+    unsigned long long reload_period;     /*the reload value of period*/
+    int pulseWidth;               /*pulse width between 0~3*/
+}Timer64_Config;
+
+/* Reset a 64-bit timer */
+extern void reset_timer(int timer_num);
+
+/* Initailize a 64-bit timer */
+extern void timer64_init(Timer64_Config * tmrCfg);
+
+extern void keystone_cpu_init(void);
+
+#endif /* __COMMON_H__ */

bsp/ti-tms320c6678/driver/drv_timer.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include "drv_timer.h"
+#include "interrupt.h"
+#include "common.h"
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_systick_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * The function initial system timer interrupt.
+ */
+void rt_hw_system_timer_init(void)
+{
+    // initial system timer interrupt, map local timer interrupt to INT14
+	gp_cgem_regs->INTMUX3 = (CSL_GEM_TINTLN << CSL_CGEM_INTMUX3_INTSEL14_SHIFT);
+    // enable CPU INT14
+    rt_hw_interrupt_umask(1 << 14);
+
+    return ;
+}
+
+/**
+ * The function initial system timer.
+ * Use local timer (== DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
+ *
+ */
+void rt_hw_system_timer_start(void)
+{
+    Timer64_Config tmrCfg;
+
+    // select output on TIMO0 from local timer.
+    gp_bootcfg_regs->TOUTSEL = (DNUM*2) << CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT;
+
+    // configure the timer to generate clocks and interrupts
+    tmrCfg.timer_num = DNUM;
+    tmrCfg.timerMode = TIMER_PERIODIC_CLOCK;
+    tmrCfg.period = (unsigned long long) RT_TICK_PER_SECOND * DSP_CORE_SPEED_HZ / 6000;
+    tmrCfg.reload_period = 0;
+
+    // initial timer
+    timer64_init(&tmrCfg);
+}

bsp/ti-tms320c6678/driver/drv_timer.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#ifndef __SYS_TIMER_H__
+#define __SYS_TIMER_H__
+
+#include <c6x.h>
+#include <tistdtypes.h>
+
+void rt_hw_system_timer_init(void);
+
+void rt_hw_system_timer_start(void);
+
+#endif	/* __SYS_TIMER_H__ */
+

bsp/ti-tms320c6678/rtconfig.h

@@ -0,0 +1,122 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+#define SOC_C6678
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_USING_ARCH_DATA_TYPE
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_8
+#define RT_THREAD_PRIORITY_MAX 8
+#define RT_TICK_PER_SECOND 100
+//#define RT_USING_HOOK
+//#define RT_USING_IDLE_HOOK
+//#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+//#define RT_DEBUG
+//#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+/* RT-Thread Components */
+
+/* C++ features */
+
+
+/* Command shell */
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+/* Using WiFi */
+
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#include "rtconfig_project.h"
+
+#endif

bsp/ti-tms320c6678/rtconfig_project.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-27     xuzhuoyi     the first version
+ */
+
+#ifndef __RTCONFIG_PROJECT_H__
+#define __RTCONFIG_PROJECT_H__
+
+typedef signed   char                   rt_int8_t;      /**<  8bit integer type */
+typedef signed   short                  rt_int16_t;     /**< 16bit integer type */
+typedef signed   long                   rt_int32_t;     /**< 32bit integer type */
+typedef signed   long long              rt_int64_t;     /**< 64bit integer type */
+typedef unsigned char                   rt_uint8_t;     /**<  8bit unsigned integer type */
+typedef unsigned short                  rt_uint16_t;    /**< 16bit unsigned integer type */
+typedef unsigned long                   rt_uint32_t;    /**< 32bit unsigned integer type */
+typedef unsigned long long              rt_uint64_t;    /**< 64bit unsigned integer type */
+
+#endif