添加支持中断栈部分代码，修改格式

bsp/ti-c6678/applications/main.c

@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-11-16     Dystopia     the first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-void rt_init_thread_entry(void *parameter)
-{
-
-    while(1)
-    {
-        rt_thread_sleep(10);
-    }
-}
-
-void rt_my_thread_entry(void *parameter)
-{
-    while(1)
-    {
-        rt_thread_sleep(20);
-    }
-}
-
-int rt_application_init(void)
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 4096, 3, 200);
-    if (tid != RT_NULL)
-    {
-        rt_thread_startup(tid);
-    } else {
-        return -1;
-    }
-    /******************************************************************/
-    tid = rt_thread_create("mythread", rt_my_thread_entry, RT_NULL, 4096, 3, 200);
-    if (tid != RT_NULL)
-    {
-        rt_thread_startup(tid);
-    } else {
-        return -1;
-    }
-
-    return 0;
-}
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* disable interrupt first */
-    rt_hw_interrupt_disable();
-
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-    /* init timer system */
-    rt_system_timer_init();
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-    /* init application */
-    rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-void main(void)
-{
-    /* startup RT-Thread RTOS */
-    rtthread_startup();
-
-    for ( ; ; );
-}
-

bsp/ti-c6678/driver/KeyStone_common.c

@@ -1,4355 +0,0 @@
-/******************************************************************************
-
-  Copyright (C), 2001-2012, Texas Instrument.
-
- ******************************************************************************
-  File Name     : KeyStone_common.c
-  Version       : Initial Draft
-  Author        : Brighton Feng
-  Created       : 2010-12-12
-  Last Modified : 
-  Description   : KeyStone common miscellaneous functions and definitions
-  History       :
-  1.Date        : 2010-12-12
-    Author      : Brighton Feng
-    Modification: Created file
-
-  2.Date         : 2012-10-6
-    Author       : Brighton Feng
-    Modification : Add memory protection and EDC configuration
-
-  3.Date         : 2014-12-8
-    Author       : Brighton Feng
-    Modification : Add common device, CPU, interrupt initialization functions.
-                   Print device information including device type, speed grade, 
-                   boot mode, required voltage, ID��
-                   Add EDMA enable/disable functions.
-                   To support square wave generation by timer.
-******************************************************************************/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <tistdtypes.h>
-#include <csl_bootcfgAux.h>
-#include <csl_pscAux.h>
-#include <cslr_chip.h>
-#include <csl_edma3.h>
-#include "CSL_msmc.h"
-#include "CSL_msmcAux.h"
-#include "KeyStone_common.h"
-
-/*----------------------------------------------*
- * external variables                           *
- *----------------------------------------------*/
-
-/*----------------------------------------------*
- * external routine prototypes                  *
- *----------------------------------------------*/
-
-/*----------------------------------------------*
- * internal routine prototypes                  *
- *----------------------------------------------*/
-
-/*----------------------------------------------*
- * project-wide global variables                *
- *----------------------------------------------*/
-CSL_XmcRegs * gpXMC_regs = (CSL_XmcRegs *) CSL_XMC_CONFIG_REGS;
-CSL_CgemRegs * gpCGEM_regs = (CSL_CgemRegs *)CSL_CGEM0_5_REG_BASE_ADDRESS_REGS;
-CSL_BootcfgRegs * gpBootCfgRegs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
-CSL_PllcRegs * gpPLLC_regs = (CSL_PllcRegs * )CSL_PLL_CONTROLLER_REGS;
-CSL_PscRegs *  gpPSC_regs =   (CSL_PscRegs *)CSL_PSC_REGS;
-CSL_MsmcRegs * gpMSMC_regs = (CSL_MsmcRegs *)CSL_MSMC_CONFIG_REGS;
-CSL_GpioRegs * gpGPIO_regs= (CSL_GpioRegs * )CSL_GPIO_REGS;
-
-CSL_CPINTCRegs* gpCIC0_regs = (CSL_CPINTCRegs*)CSL_CP_INTC_0_REGS;
-CSL_CPINTCRegs* gpCIC1_regs = (CSL_CPINTCRegs*)CSL_CP_INTC_1_REGS;
-/*The register pointer for the CIC routing events DSP core.
-By default, it is CIC0; but for core 4~7 of C6678, it is CIC1*/
-CSL_CPINTCRegs* gpCIC_regs= (CSL_CPINTCRegs*)CSL_CP_INTC_0_REGS;
-
-CSL_TpccRegs*  gpEDMA_CC0_regs  = (CSL_TpccRegs*)CSL_EDMA0CC_REGS;
-CSL_TpccRegs*  gpEDMA_CC1_regs  = (CSL_TpccRegs*)CSL_EDMA1CC_REGS;
-CSL_TpccRegs*  gpEDMA_CC2_regs  = (CSL_TpccRegs*)CSL_EDMA2CC_REGS;
-CSL_TpccRegs*  gpEDMA_CC_regs[3]  = {
-	(CSL_TpccRegs*)CSL_EDMA0CC_REGS,
-	(CSL_TpccRegs*)CSL_EDMA1CC_REGS,
-	(CSL_TpccRegs*)CSL_EDMA2CC_REGS
-};
-
-CSL_TptcRegs * gpEDMA_TC_0_0_regs=(CSL_TptcRegs *) CSL_EDMA0TC0_REGS;
-CSL_TptcRegs * gpEDMA_TC_0_1_regs=(CSL_TptcRegs *) CSL_EDMA0TC1_REGS;
-CSL_TptcRegs * gpEDMA_TC_1_0_regs=(CSL_TptcRegs *) CSL_EDMA1TC0_REGS;
-CSL_TptcRegs * gpEDMA_TC_1_1_regs=(CSL_TptcRegs *) CSL_EDMA1TC1_REGS;
-CSL_TptcRegs * gpEDMA_TC_1_2_regs=(CSL_TptcRegs *) CSL_EDMA1TC2_REGS;
-CSL_TptcRegs * gpEDMA_TC_1_3_regs=(CSL_TptcRegs *) CSL_EDMA1TC3_REGS;
-CSL_TptcRegs * gpEDMA_TC_2_0_regs=(CSL_TptcRegs *) CSL_EDMA2TC0_REGS;
-CSL_TptcRegs * gpEDMA_TC_2_1_regs=(CSL_TptcRegs *) CSL_EDMA2TC1_REGS;
-CSL_TptcRegs * gpEDMA_TC_2_2_regs=(CSL_TptcRegs *) CSL_EDMA2TC2_REGS;
-CSL_TptcRegs * gpEDMA_TC_2_3_regs=(CSL_TptcRegs *) CSL_EDMA2TC3_REGS;
-
-CSL_TptcRegs * gpEDMA_TC_regs[10]= {
-	(CSL_TptcRegs *) CSL_EDMA0TC0_REGS,
-	(CSL_TptcRegs *) CSL_EDMA0TC1_REGS,
-	(CSL_TptcRegs *) CSL_EDMA1TC0_REGS,
-	(CSL_TptcRegs *) CSL_EDMA1TC1_REGS,
-	(CSL_TptcRegs *) CSL_EDMA1TC2_REGS,
-	(CSL_TptcRegs *) CSL_EDMA1TC3_REGS,
-	(CSL_TptcRegs *) CSL_EDMA2TC0_REGS,
-	(CSL_TptcRegs *) CSL_EDMA2TC1_REGS,
-	(CSL_TptcRegs *) CSL_EDMA2TC2_REGS,
-	(CSL_TptcRegs *) CSL_EDMA2TC3_REGS
-};
-
-CSL_TmrPlusRegs * gpTimer0Regs = (CSL_TmrPlusRegs *)CSL_TIMER_0_REGS;
-CSL_TmrPlusRegs * gpTimer1Regs = (CSL_TmrPlusRegs *)CSL_TIMER_1_REGS;
-CSL_TmrPlusRegs * gpTimer2Regs = (CSL_TmrPlusRegs *)CSL_TIMER_2_REGS;
-CSL_TmrPlusRegs * gpTimer3Regs = (CSL_TmrPlusRegs *)CSL_TIMER_3_REGS;
-CSL_TmrPlusRegs * gpTimer4Regs = (CSL_TmrPlusRegs *)CSL_TIMER_4_REGS;
-CSL_TmrPlusRegs * gpTimer5Regs = (CSL_TmrPlusRegs *)CSL_TIMER_5_REGS;
-CSL_TmrPlusRegs * gpTimer6Regs = (CSL_TmrPlusRegs *)CSL_TIMER_6_REGS;
-CSL_TmrPlusRegs * gpTimer7Regs = (CSL_TmrPlusRegs *)CSL_TIMER_7_REGS;
-CSL_TmrPlusRegs * gpTimer8Regs = (CSL_TmrPlusRegs *)(CSL_TIMER_7_REGS+(CSL_TIMER_7_REGS-CSL_TIMER_6_REGS));
-CSL_TmrPlusRegs * gpTimerRegs[9] = {
-	(CSL_TmrPlusRegs *)CSL_TIMER_0_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_1_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_2_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_3_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_4_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_5_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_6_REGS,
-	(CSL_TmrPlusRegs *)CSL_TIMER_7_REGS,
-	(CSL_TmrPlusRegs *)(CSL_TIMER_7_REGS+(CSL_TIMER_7_REGS-CSL_TIMER_6_REGS))
-};
-
-/*MPU for peripherals registers and data space*/
-CSL_MpuRegs * gpMPU0_regs= (CSL_MpuRegs *)CSL_MPU_0_REGS;
-CSL_MpuRegs * gpMPU1_regs= (CSL_MpuRegs *)CSL_MPU_1_REGS;
-CSL_MpuRegs * gpMPU2_regs= (CSL_MpuRegs *)CSL_MPU_2_REGS;
-CSL_MpuRegs * gpMPU3_regs= (CSL_MpuRegs *)CSL_MPU_3_REGS;
-
-CSL_Emif4fRegs * gpDDR_regs= (CSL_Emif4fRegs *)CSL_DDR3_EMIF_CONFIG_REGS;
-unsigned int gDSP_Core_Speed_Hz= 1000000000; 	//DSP core clock speed in Hz
-TDSP_Board_Type gDSP_board_type= UNKNOWN;
-
-/*----------------------------------------------*
- * module-wide global variables                 *
- *----------------------------------------------*/
-
-/*----------------------------------------------*
- * constants                                    *
- *----------------------------------------------*/
-
-/*----------------------------------------------*
- * macros                                       *
- *----------------------------------------------*/
-
-/*----------------------------------------------*
- * routines' implementations                    *
- *----------------------------------------------*/
-
-/*****************************************************************************
- Prototype    : KeyStone_main_PLL_init
- Description  : DSP core PLL configuration
-  	DSP core will be configured to run at ref_clock_MHz*multiplier/divisor
- Input        : float ref_clock_MHz     
-                unsigned int multiplier: 1~4096  
-                unsigned int divisor: 1~64  
- Output       : 
- Return Value : 
- 
-  History        :
-  1.Date         : 2010-12-12
-    Author       : Brighton Feng
-    Modification : Created function
-  2.Date         : May 19, 2013
-    Author       : Brighton Feng
-    Modification : update parameter check; replace constant with macro
-
-*****************************************************************************/
-void KeyStone_main_PLL_init (float ref_clock_MHz,
-	unsigned int multiplier, unsigned int divisor)
-{
-	unsigned int i;
-
-	if(0==divisor)
-	{
-		puts("Error: PLL input divider = 0");
-		return;
-	}
-
-	if(64<divisor)
-	{
-		puts("Error: PLL input divider too large");
-		return;
-	}
-
-	if(0==multiplier)
-	{
-		puts("Error: PLL multiplier = 0");
-		return;
-	}
-
-	if(4096<multiplier)
-	{
-		puts("Error: PLL multiplier too large");
-		return;
-	}
-
-	CSL_BootCfgUnlockKicker();
-
-	gDSP_Core_Speed_Hz= ref_clock_MHz*1000000/divisor*multiplier;
-
-	printf("Initialize DSP main clock = %.2fMHz/%dx%d = %dMHz\n", 
-		ref_clock_MHz, divisor, multiplier, gDSP_Core_Speed_Hz/1000000);
-
-	/*1. If executing this sequence immediately after device power-up, you must allow for*/
-	/*the PLL to become stable. PLL stabilization time is 100 ��s.                       */
-	for(i=0; i< 20000; i++)
-		asm(" nop 5");
-
-	/*2. Check the status of BYPASS bit in SECCTL register, execute following steps if   */
-	/*BYPASS == 1 (if bypass enabled):                         */
-	if(gpPLLC_regs->SECCTL & PLLCTL_BYPASS_MASK)
-	{		
-		/*a. In MAINPLLCTL1, write ENSAT = 1 (for optimal PLL operation)                     */
-		gpBootCfgRegs->CORE_PLL_CTL1 |= PLLCTL1_ENSAT_MASK;      /*Set ENSAT bit = 1*/
-
-		/*b. In PLLCTL, write PLLEN = 0 (bypass enabled in PLL controller mux)               */
-		gpPLLC_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLEN_MASK;
-
-		/*c. In PLLCTL, write PLLENSRC = 0 (enable PLLEN to control PLL controller mux       */
-		gpPLLC_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLENSRC_MASK;
-
-		/*d. Wait 4 cycles of the reference clock CLKIN (to make sure the PLL controller     */
-		/*mux switches properly to the bypass)                                               */
-		for(i=0; i< 4; i++)
-			asm(" nop 5");
-
-		/*e. In SECCTL, write BYPASS = 1 (bypass enabled in PLL mux)                         */
-		gpPLLC_regs->SECCTL |= PLLCTL_BYPASS_MASK;
-
-		/*f. In PLLCTL, write PLLPWRDN = 1 (power down the PLL)                              */
-		gpPLLC_regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLPWRDN_MASK;	//Power down the PLL
-
-		/*g. Wait for at least 5 ��s based on the reference clock CLKIN (PLL power down      */
-		/*toggling time)                                                                     */
-		for(i=0; i< 1000; i++)
-			asm(" nop 5");
-
-		/*h. In PLLCTL, write PLLPWRDN = 0 (power up the PLL)                                */
-		gpPLLC_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLPWRDN_MASK;         // Power up PLL
-	}
-	else
-	{
-		/*a. In PLLCTL, write PLLEN = 0 (bypass enabled in PLL controller mux)               */
-		gpPLLC_regs->PLLCTL &= (~CSL_PLLC_PLLCTL_PLLEN_MASK);
-
-		/*b. In PLLCTL, write PLLENSRC = 0 (enable PLLEN to control PLL controller mux       */
-		gpPLLC_regs->PLLCTL &= (~CSL_PLLC_PLLCTL_PLLENSRC_MASK);
-
-		/*c. Wait 4 cycles of the reference clock CLKIN (to make sure the PLL controller     */
-		/*mux switches properly to the bypass)                                               */
-		for(i=0; i< 4*multiplier/divisor; i++)
-			asm(" nop 5");
-	}
-
-	/*4. PLLM is split in two different registers. Program PLLM[5:0] in PLL multiplier   */
-	/*control register (PLLM) and PLLM[12:6] in MAINPLLCTL0 register                     */
-	/*5. BWADJ is split in two different registers. Program BWADJ[7:0] in                */
-	/*MAINPLLCTL0 and BWADJ[11:8] in MAINPLLCTL1 register. BWADJ value                   */
-	/*must be set to ((PLLM + 1) >> 1) - 1)                                              */
-	/*6. Program PLLD in MAINPLLCTL0 register                                            */
-	gpBootCfgRegs->CORE_PLL_CTL0 = ((multiplier-1)<<PLLCTL0_BWADJ_SHIFT)|
-		(((multiplier*2-1)&0x1FC0)<<PLLCTL0_PLLM_SHIFT)|(divisor-1);
-	
-	gpPLLC_regs->PLLM= (multiplier*2-1)&0x3F;
-	gpBootCfgRegs->CORE_PLL_CTL1 &= ~PLLCTL1_BWADJ_MASK; 
-	gpBootCfgRegs->CORE_PLL_CTL1 |= (multiplier-1)>>8;	/*BWADJ[11:8]*/
-
-	/*7. In SECCTL, write OD (Output Divide) = 1 (that is divide-by-2)                   */
-	gpPLLC_regs->SECCTL &= ~PLLCTL_OD_MASK;
-	gpPLLC_regs->SECCTL |= 1<<PLLCTL_OD_SHIFT;
-	
-#if 0
-	/*8. If necessary, program PLLDIVn. Note that you must apply the GO operation to     */
-	/*change these dividers to a new ratios (see Section 3.2 ����Divider n (D1 to Dn) and*/
-	/*GO Operation ���� on page 3-3).                                                    */
-	/* Step 8a: Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
-	operation is currently in progress*/
-	while((gpPLLC_regs->PLLSTAT) & CSL_PLLC_PLLSTAT_GOSTAT_MASK);
-
-	/* Step 8b: Program the RATIO field in PLLDIVn to the desired new divide-down rate.
-	If RATIO field is changed, the PLL controller will flag the change in the
-	corresponding bit of DCHANGE*/
-	gpPLLC_regs->PLLDIV1_3[3-1] = (3-1) | CSL_PLLC_PLLDIV1_3_DNEN_MASK;  //Set PLLDIV3
-	gpPLLC_regs->PLLDIV4_16[4-4] = (5-1) | CSL_PLLC_PLLDIV4_16_DNEN_MASK;  //Set PLLDIV4
-	gpPLLC_regs->PLLDIV4_16[7-4] = (6-1) | CSL_PLLC_PLLDIV4_16_DNEN_MASK;  //Set PLLDIV7
-
-	/* Step 8c: Set GOSET bit in PLLCMD to initiate the GO operation to change the divide
-	values and align the SYSCLKs as programmed */
-	gpPLLC_regs->PLLCMD |= CSL_PLLC_PLLCMD_GOSET_MASK;
-
-	/*Step 8d/e: Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0 to
-	indicate that the GO operation has completed */
-	while((gpPLLC_regs->PLLSTAT) & CSL_PLLC_PLLSTAT_GOSTAT_MASK);
-#endif
-
-	/*9. In PLLCTL , write PLLRST = 1 (PLL reset is asserted)*/
-	gpPLLC_regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLRST_MASK;
-	
-	/*10. Wait for at least 7 ��s based on the reference clock CLKIN (PLL reset time)     */
-	for(i=0; i< 2000; i++)
-		asm(" nop 5");
-
-	/*11. In PLLCTL, write PLLRST = 0 (PLL reset is released)                            */
-	gpPLLC_regs->PLLCTL &= ~CSL_PLLC_PLLCTL_PLLRST_MASK;
-
-	/*12. Wait for at least 2000 �� CLKIN cycles �� (PLLD + 1) (PLL lock time)            */
-	for(i=0; i< 400*multiplier; i++)
-		asm(" nop 5");
-
-	/*13. In SECCTL, write BYPASS = 0 (enable PLL mux to switch to PLL mode)             */
-	gpPLLC_regs->SECCTL &= ~PLLCTL_BYPASS_MASK;
-	
-	/*14. Set the PLLEN bit in PLLCTL to 1 to enable PLL mode*/
-	gpPLLC_regs->PLLCTL |= CSL_PLLC_PLLCTL_PLLEN_MASK;
-
-}
-/*****************************************************************************
- Prototype    : KeyStone_PLL_init
- Description  : Config the PLL of PA and DDR
- 	target clock speed will be ref_clock_MHz/inputDivisor*multiplier/outputDivisor
- Input        : unsigned int inputDivisor  
-                unsigned int multiplier  
-                unsigned int outputDivisor  
- Output       : None
- Return Value : 0 for success, other value for error
- 
-  History        :
-  1.Date         : May 18, 2013
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-int KeyStone_PLL_init (PLL_ControlRegs * PLL_Regs, unsigned int inputDivisor, 
-	unsigned int multiplier, unsigned int outputDivisor)
-{
-	if(0==inputDivisor)
-	{
-		puts("Error: PLL input divider = 0");
-		return 1;
-	}
-
-	if(64<inputDivisor)
-	{
-		puts("Error: PLL input divider too large");
-		return 2;
-	}
-
-	if(0==multiplier)
-	{
-		puts("Error: PLL multiplier = 0");
-		return 3;
-	}
-
-	if(8192<multiplier)
-	{
-		puts("Error: PLL multiplier too large");
-		return 4;
-	}
-
-	if(0==outputDivisor)
-	{
-		puts("Error: PLL output divider = 0");
-		return 5;
-	}
-
-	if(16<outputDivisor)
-	{
-		puts("Error: PLL output divider too larger");
-		return 6;
-	}
-
-	CSL_BootCfgUnlockKicker();
-
-	/*1. In PLLCTL1, write ENSAT = 1 (for optimal PLL operation)*/
-	PLL_Regs->PLL_CTL1 = PLLCTL1_ENSAT_MASK;
-
-	/*2. In PLLCTL0, write BYPASS = 1 (set the PLL in Bypass)*/
-	PLL_Regs->PLL_CTL0 |= PLLCTL_BYPASS_MASK;
-
-	/*3. Program PLLM and PLLD in PLLCTL0 register*/
-	/*4. Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in PLLCTL1 register. 
-	BWADJ value must be set to ((PLLM + 1) >> 1) �C 1)*/
-	PLL_Regs->PLL_CTL0 = ((multiplier/2-1)<<PLLCTL0_BWADJ_SHIFT)
-		|((outputDivisor-1)<<PLLCTL_OD_SHIFT)
-		|((multiplier-1)<<PLLCTL0_PLLM_SHIFT)
-		|(inputDivisor-1);
-
-	PLL_Regs->PLL_CTL1 &= ~PLLCTL1_BWADJ_MASK;
-	PLL_Regs->PLL_CTL1 |= (multiplier/2-1)>>8; /*BWADJ[11:8]*/
-
-	/*5. In PLLCTL1, write PLLRST = 1 (PLL is reset)*/
-	PLL_Regs->PLL_CTL1 |= PLLCTL1_PLLRESET_MASK;      //Set RESET bit = 1
-
-	/*6. Wait for at least 7 us based on the reference clock (PLL reset time)*/
-	TSC_delay_us(7);
-
-	/*For PASS, In PASSPLLCTL1, write PLLSELECT = 1 
-	(for selecting the output of PA PLL as the input to PASS)*/
-	if(PLL_Regs==(PLL_ControlRegs *)gpBootCfgRegs->PA_PLL_CTL0)
-		PLL_Regs->PLL_CTL1 |= PLLCTL1_PAPLL_MASK;
-
-	/*7. In PLLCTL1, write PLLRST = 0 (PLL reset is released)*/
-	PLL_Regs->PLL_CTL1 &= ~PLLCTL1_PLLRESET_MASK;   //Clear RESET bit
-
-	/*8. Wait for at least 500 * REFCLK cycles * (PLLD + 1) (PLL lock time)*/
-	TSC_delay_us(500);
-
-	/*9. In PLLCTL0, write BYPASS = 0 (switch to PLL mode)*/
-	PLL_Regs->PLL_CTL0 &= ~PLLCTL_BYPASS_MASK ;
-
-	return 0;
-}
-/*****************************************************************************
- Prototype    : KeyStone_PASS_PLL_init
- Description  : Config the PASS PLL
- 	target clock speed will be ref_clock_MHz/divisor*multiplier
- Input        : float ref_clock_MHz
-                unsigned int multiplier: 1~4096
-                unsigned int divisor: 1~64
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2013-2-14
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_PASS_PLL_init (float ref_clock_MHz,
-	unsigned int multiplier, unsigned int divisor)
-{
-	//output divisor for PASS PLL should be 2
-	if(0==KeyStone_PLL_init((PLL_ControlRegs *)&gpBootCfgRegs->PA_PLL_CTL0, 
-		divisor, multiplier*2, 2))
-	{
-		printf("Initialize PASS PLL clock = %.2fMHz/%dx%d = %.3fMHz\n", 
-			ref_clock_MHz, divisor, multiplier, 
-			ref_clock_MHz*multiplier/divisor);
-	}
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_DDR_PLL_init
- Description  : Config the DDR PLL
- 	target clock speed will be ref_clock_MHz/divisor*multiplier
- Input        : float ref_clock_MHz
-                unsigned int multiplier: 1~4096
-                unsigned int divisor: 1~64
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2013-8-18
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_DDR_PLL_init (float ref_clock_MHz,
-	unsigned int multiplier, unsigned int divisor)
-{
-	//output divisor for DDR PLL should be 2
-	if(0==KeyStone_PLL_init((PLL_ControlRegs *)&gpBootCfgRegs->DDR3_PLL_CTL0, 
-		divisor, multiplier, 2))
-	{
-		printf("Initialize DDR speed = %.2fMHzx/%dx%d = %.3fMTS\n", 
-			ref_clock_MHz, divisor, multiplier, 
-			ref_clock_MHz*multiplier/divisor);
-	}
-}
-
-/*===============================TSC===================================*/
-unsigned int cycle_measure_overhead=50;
-/*****************************************************************************
- Prototype    : calc_cycle_measure_overhead
- Description  : calclucate the cycles measurement overhead
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void calc_cycle_measure_overhead()
-{
-	unsigned int cycle_cold, cycle_warm;
-	cycle_cold= TSCL;
-	cycle_cold = TSC_getDelay(cycle_cold);
-	cycle_warm= TSCL;
-	cycle_warm = TSC_getDelay(cycle_warm);
-	cycle_measure_overhead = (cycle_cold + cycle_warm)/2;
-}
-
-/*****************************************************************************
- Prototype    : TSC_init
- Description  : Initialize Time stamp counter to measure cycles
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void TSC_init()
-{
-	TSCL = 0; 	/* Enable the TSC */
-	calc_cycle_measure_overhead();
-}
-
-/*****************************************************************************
- Prototype    : TSC_delay_ms
- Description  : Implement the delay function in millisecond
- Input        : Uint32 ms  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void TSC_delay_ms(Uint32 ms)
-{
-	volatile unsigned long long startTSC, currentTSC;
-	unsigned long long delay_cycles;
-	Uint32 tscl, tsch;
-
-	tscl= TSCL;
-	tsch= TSCH;
-	startTSC= _itoll(tsch,tscl); 
-	
-	delay_cycles= ((unsigned long long)ms*gDSP_Core_Speed_Hz/1000);
-
-	do
-	{
-		tscl= TSCL;
-		tsch= TSCH;
-		currentTSC= _itoll(tsch,tscl); 
-	}
-	while((currentTSC-startTSC)<delay_cycles);
-}
-
-/*****************************************************************************
- Prototype    : TSC_delay_us
- Description  : Implement the delay function in microsecond
- Input        : Uint32 us  
- Output       : None
- Return Value : 
-*****************************************************************************/
-void TSC_delay_us(Uint32 us)
-{
-	volatile unsigned long long startTSC, currentTSC;
-	unsigned long long delay_cycles;
-	Uint32 tscl, tsch;
-
-	tscl= TSCL;
-	tsch= TSCH;
-	startTSC= _itoll(tsch,tscl); 
-	
-	delay_cycles= ((unsigned long long)us*gDSP_Core_Speed_Hz/1000000);
-
-	do
-	{
-		tscl= TSCL;
-		tsch= TSCH;
-		currentTSC= _itoll(tsch,tscl); 
-	}
-	while((currentTSC-startTSC)<delay_cycles);
-}
-
-/*===============================Timer=================================*/
-/*****************************************************************************
- Prototype    : Reset_Timer
- Description  : Reset the general timer value
- Input        : int timer_num  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void Reset_Timer(int timer_num)
-{
-	if(gpTimerRegs[timer_num]->TGCR)
-	{
-		gpTimerRegs[timer_num]->TGCR= 0;
-		gpTimerRegs[timer_num]->TCR= 0;
-	}
-}
-
- /*****************************************************************************
- Prototype    : Timer64_Init
- Description  : Initialize a 64-bit timer
- Input        : Timer64_Config * tmrCfg  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void Timer64_Init(Timer64_Config * tmrCfg)
-{
-	Reset_Timer(tmrCfg->timer_num);
-
-	gpTimerRegs[tmrCfg->timer_num]->CNTLO= 0;
-	gpTimerRegs[tmrCfg->timer_num]->CNTHI= 0;
-
-	/*please note, in clock mode, two timer periods generate a clock, 
-	one timer period output high voltage level, the other timer period 
-	output low voltage level, so, the timer period should be half to the 
-	desired output clock period*/
-	if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode)
-		tmrCfg->period= tmrCfg->period/2;
-
-	/*the value written into period register is the expected value minus one*/
-	gpTimerRegs[tmrCfg->timer_num]->PRDLO= _loll(tmrCfg->period-1);
-	gpTimerRegs[tmrCfg->timer_num]->PRDHI= _hill(tmrCfg->period-1);
-	if(tmrCfg->reload_period>1)
-	{
-		gpTimerRegs[tmrCfg->timer_num]->RELLO= _loll(tmrCfg->reload_period-1);
-		gpTimerRegs[tmrCfg->timer_num]->RELHI= _hill(tmrCfg->reload_period-1);
-	}
-	
-	if(TIMER_WATCH_DOG==tmrCfg->timerMode)
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TGCR= 
-			/*Select watch-dog mode*/
-			(CSL_TMR_TIMMODE_WDT<<CSL_TMR_TGCR_TIMMODE_SHIFT)
-			/*Remove the timer from reset*/
-			|(CSL_TMR_TGCR_TIMLORS_MASK)
-			|(CSL_TMR_TGCR_TIMHIRS_MASK);
-	}
-	else if(TIMER_PERIODIC_WAVE==tmrCfg->timerMode)
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TGCR= TMR_TGCR_PLUSEN_MASK
-			/*for plus featuers, dual 32-bit unchained timer mode should be used*/
-			|(CSL_TMR_TIMMODE_DUAL_UNCHAINED<<CSL_TMR_TGCR_TIMMODE_SHIFT)
-			/*Remove the timer from reset*/
-			|(CSL_TMR_TGCR_TIMLORS_MASK);
-
-		//in plus mode, interrupt/event must be enabled manually
-		gpTimerRegs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
-	}
-	else
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TGCR= 
-			/*Select 64-bit general timer mode*/
-			(CSL_TMR_TIMMODE_GPT<<CSL_TMR_TGCR_TIMMODE_SHIFT)
-			/*Remove the timer from reset*/
-			|(CSL_TMR_TGCR_TIMLORS_MASK)
-			|(CSL_TMR_TGCR_TIMHIRS_MASK);
-	}
-
-	/*make timer stop with emulation*/
-	gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
-		~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
-
-	if(TIMER_WATCH_DOG==tmrCfg->timerMode)
-	{
-		/*enable watchdog timer*/
-		gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
-			|(CSL_TMR_WDTCR_WDKEY_CMD1<<CSL_TMR_WDTCR_WDKEY_SHIFT);
-
-		gpTimerRegs[tmrCfg->timer_num]->TCR= 
-			(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT   ) 
-			|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT ) 
-			/*The timer is enabled continuously*/
-			|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT) 
-			|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) 
-			/*select pulse mode*/
-			|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT     ) 
-			|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT ) 
-			|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT) 
-			|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT  );
-
-		/*active watchdog timer*/
-		gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
-			|(CSL_TMR_WDTCR_WDKEY_CMD2<<CSL_TMR_WDTCR_WDKEY_SHIFT);
-	}
-	else if(TIMER_ONE_SHOT_PULSE==tmrCfg->timerMode)
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TCR= 
-			(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT   ) 
-			|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT ) 
-			/*The timer is enabled one-shot*/
-			|(CSL_TMR_ENAMODE_ENABLE<<CSL_TMR_TCR_ENAMODE_LO_SHIFT) 
-			|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) 
-			/*select pulse mode*/
-			|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT     ) 
-			|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT ) 
-			|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT) 
-			|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT  );
-	}
-	else if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode)
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TCR= 
-			(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT   ) 
-			|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT ) 
-			/*The timer is enabled continuously*/
-			|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT) 
-			|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) 
-			/*select clock mode*/
-			|(CSL_TMR_CP_CLOCK<<CSL_TMR_TCR_CP_LO_SHIFT     ) 
-			|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT ) 
-			|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT) 
-			|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT  );
-	}
-	else if(TIMER_PERIODIC_WAVE==tmrCfg->timerMode)
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TCR= 
-			(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT   ) 
-			|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT ) 
-			/*The timer is enabled continuously with period reload*/
-			|(CSL_TMR_ENAMODE_CONT_RELOAD<<CSL_TMR_TCR_ENAMODE_LO_SHIFT) 
-			|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) 
-			/*select clock mode*/
-			|(CSL_TMR_CP_CLOCK<<CSL_TMR_TCR_CP_LO_SHIFT     ) 
-			|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT ) 
-			|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT) 
-			|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT  );
-	}
-	else 	/*TIMER_PERIODIC_PULSE*/
-	{
-		gpTimerRegs[tmrCfg->timer_num]->TCR= 
-			(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT   ) 
-			|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT ) 
-			/*The timer is enabled continuously*/
-			|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT) 
-			|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK) 
-			/*select clock mode*/
-			|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT     ) 
-			|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT ) 
-			|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT) 
-			|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT  );
-	}
-}
-
-
-/*****************************************************************************
- Prototype    : Service_Watchdog
- Description  : Implement the watch dog service
- Input        : int timer_num  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void Service_Watchdog(int timer_num)
-{
-    /*write sequence of a A5C6h followed by a DA7Eh 
-    to services the watchdog timer.*/
-    
-	gpTimerRegs[timer_num]->WDTCR =
-		(CSL_TMR_WDTCR_WDKEY_CMD1<<CSL_TMR_WDTCR_WDKEY_SHIFT);
-	gpTimerRegs[timer_num]->WDTCR =
-		(CSL_TMR_WDTCR_WDKEY_CMD2<<CSL_TMR_WDTCR_WDKEY_SHIFT);
-}
-
-/*===============================PSC===================================*/
-/*****************************************************************************
- Prototype    : KeyStone_enable_PSC_module
- Description  : Enable the PSC module in KeyStone device
- Input        : Uint32 pwrDmnNum  
-                Uint32 moduleNum  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-Int32 KeyStone_enable_PSC_module (Uint32 pwrDmnNum, Uint32 moduleNum)
-{
-	Uint32 uiStartTSC= TSCL;
-
-    if (CSL_PSC_getPowerDomainState(pwrDmnNum) != PSC_PDSTATE_ON)
-    {
-	    /* Set Power domain to ON */
-	    CSL_PSC_enablePowerDomain (pwrDmnNum);
-
-	    /* Start the state transition */
-	    CSL_PSC_startStateTransition (pwrDmnNum);
-
-	    /* Wait until the state transition process is completed. */
-	    while (!CSL_PSC_isStateTransitionDone (pwrDmnNum))
-		{
-			if(TSC_count_cycle_from(uiStartTSC)>0x3FFFFFFF)
-			{
-				printf("Enable power domain %d timeout!\n", pwrDmnNum);
-				return -2;
-			}
-		}
-	}
-
-    /* Enable the clocks too*/
-    CSL_PSC_setModuleNextState (moduleNum, PSC_MODSTATE_ENABLE);
-
-    /* Start the state transition */
-    CSL_PSC_startStateTransition (pwrDmnNum);
-
-    /* Wait until the state transition process is completed. */
-    while (!CSL_PSC_isStateTransitionDone (pwrDmnNum))
-	{
-		if(TSC_count_cycle_from(uiStartTSC)>0x3FFFFFFF)
-		{
-			printf("Enable clock domain %d timeout!\n", moduleNum);
-			return -2;
-		}
-	}
-
-    /* Return PSC status */
-    if ((CSL_PSC_getPowerDomainState(pwrDmnNum) == PSC_PDSTATE_ON) &&
-        (CSL_PSC_getModuleState (moduleNum) == PSC_MODSTATE_ENABLE))
-    {
-        /*Ready for use */
-        return 0;
-    }
-    else
-    {
-        /*Return error */
-        return -1;
-    }
-}
-/*****************************************************************************
- Prototype    : KeyStone_disable_PSC_module
- Description  : Disable the PSC module in KeyStone device
- Input        : Uint32 pwrDmnNum  
-                Uint32 moduleNum  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/2/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-Int32 KeyStone_disable_PSC_module (Uint32 pwrDmnNum, Uint32 moduleNum)
-{
-	Uint32 uiStartTSC= TSCL;
-	
-    /* disable the clocks*/
-    CSL_PSC_setModuleNextState (moduleNum, PSC_MODSTATE_SWRSTDISABLE);
-
-    /* Start the state transition */
-    CSL_PSC_startStateTransition (pwrDmnNum);
-
-    /* Wait until the state transition process is completed. */
-    while (!CSL_PSC_isStateTransitionDone (pwrDmnNum))
-	{
-		if(TSC_count_cycle_from(uiStartTSC)>0x3FFFFFFF)
-		{
-			printf("Disable clock domain %d timeout!\n", moduleNum);
-			return -2;
-		}
-	}
-
-    /* Return PSC status */
-    if (CSL_PSC_getModuleState (moduleNum) == PSC_MODSTATE_SWRSTDISABLE)
-    {
-        /*Ready for use */
-        return 0;
-    }
-    else
-    {
-        /*Return error */
-        return -1;
-    }
-
-}
-/*****************************************************************************
- Prototype    : KeyStone_disable_PSC_Power_Domain
- Description  : Disable the PSC power domain
- Input        : Uint32 pwrDmnNum  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-Int32 KeyStone_disable_PSC_Power_Domain (Uint32 pwrDmnNum)
-{
-	Uint32 uiStartTSC= TSCL;
-
-    /* Set Power domain to OFF */
-    CSL_PSC_disablePowerDomain (pwrDmnNum);
-
-    /* Start the state transition */
-    CSL_PSC_startStateTransition (pwrDmnNum);
-
-    /* Wait until the state transition process is completed. */
-    while (!CSL_PSC_isStateTransitionDone (pwrDmnNum))
-	{
-		if(TSC_count_cycle_from(uiStartTSC)>0x3FFFFFFF)
-		{
-			printf("Disable power domain %d timeout!\n", pwrDmnNum);
-			return -2;
-		}
-	}
-
-    /* Return PSC status */
-    if (CSL_PSC_getPowerDomainState(pwrDmnNum) == PSC_PDSTATE_OFF)
-    {
-        /*Ready for use */
-        return 0;
-    }
-    else
-    {
-        /*Return error */
-        return -1;
-    }
-
-}
-
-/*============================EDMA=====================================*/
- /*****************************************************************************
- Prototype    : EDMA_channel_TC_cfg
- Description  : Setup uiChannel of an EDMA to use uiTC
- Input        : Uint32 uiCC  
-                Uint32 uiChannel            
-                Uint32 uiTC                 
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_channel_TC_cfg (Uint32 uiCC, 
-	Uint32 uiChannel, Uint32 uiTC)
-{
-	gpEDMA_CC_regs[uiCC]->TPCC_DMAQNUM[uiChannel/8] = 
-		(gpEDMA_CC_regs[uiCC]->TPCC_DMAQNUM[uiChannel/8]&(~(0xF<<((uiChannel&7)*4))))
-		|(uiTC<<((uiChannel&7)*4));
-}
-/*****************************************************************************
- Prototype    : EDMA_TC_priority_cfg
- Description  : Setup uiChannel of an EDMA TC priority
- Input        : Uint32 uiCC  
-                Uint32 uiPri                
-                Uint32 uiTC                 
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_TC_priority_cfg(Uint32 uiCC, 
-	Uint32 uiPri, Uint32 uiTC)
-{
-	gpEDMA_CC_regs[uiCC]->TPCC_QUEPRI= 
-		(gpEDMA_CC_regs[uiCC]->TPCC_QUEPRI&(~(0xF<<((uiTC&3)*4))))
-		|(uiPri<<((uiTC&3)*4));
-}
-/*****************************************************************************
- Prototype    : EDMA_init
- Description  : Initialize all EDMA registers and clear the event
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_init ()
-{
-	int i;
-	unsigned int * uipPaRAM;
-
-	/*clear PaRAM*/
-	uipPaRAM= (unsigned int *)&(gpEDMA_CC0_regs->PARAMSET[0]);
-	for(i=0; i<8*CSL_EDMA3_TPCC0_NUM_PARAMSETS; i++) 	
-		*uipPaRAM++=0;
-
-	uipPaRAM= (unsigned int *)&(gpEDMA_CC1_regs->PARAMSET[0]);
-	for(i=0; i<8*CSL_EDMA3_TPCC1_NUM_PARAMSETS; i++) 	
-		*uipPaRAM++=0;
-
-	uipPaRAM= (unsigned int *)&(gpEDMA_CC2_regs->PARAMSET[0]);
-	for(i=0; i<8*CSL_EDMA3_TPCC2_NUM_PARAMSETS; i++) 	
-		*uipPaRAM++=0;
-		
-	/*Assign PaRAM for different channels*/
-	for(i=0; i<CSL_EDMA3_TPCC0_NUM_DMACH; i++) 	
-		gpEDMA_CC0_regs->TPCC_DCHMAP[i] = i<< CSL_TPCC_TPCC_DCHMAP0_PAENTRY_SHIFT;
-
-	for(i=0; i<CSL_EDMA3_TPCC1_NUM_DMACH; i++) 	
-		gpEDMA_CC1_regs->TPCC_DCHMAP[i] = i<< CSL_TPCC_TPCC_DCHMAP0_PAENTRY_SHIFT;
-
-	for(i=0; i<CSL_EDMA3_TPCC2_NUM_DMACH; i++) 	
-		gpEDMA_CC2_regs->TPCC_DCHMAP[i] = i<< CSL_TPCC_TPCC_DCHMAP0_PAENTRY_SHIFT;
-
-	/*Assign TC/Queue for different channels*/
-	gpEDMA_CC0_regs->TPCC_DMAQNUM[0]= 0x10101010;
-	gpEDMA_CC0_regs->TPCC_DMAQNUM[1]= 0x10101010;
-
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[0]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[1]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[2]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[3]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[4]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[5]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[6]= 0x32103210;
-	gpEDMA_CC1_regs->TPCC_DMAQNUM[7]= 0x32103210;
-
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[0]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[1]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[2]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[3]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[4]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[5]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[6]= 0x32103210;
-	gpEDMA_CC2_regs->TPCC_DMAQNUM[7]= 0x32103210;
-
-	/*clear any events and status*/
-	gpEDMA_CC0_regs->TPCC_ECR=  0xFFFF;
-	gpEDMA_CC0_regs->TPCC_EECR= 0xFFFF;
-	gpEDMA_CC0_regs->TPCC_ICR=  0xFFFF;
-	gpEDMA_CC0_regs->TPCC_IECR= 0xFFFF;
-	gpEDMA_CC0_regs->TPCC_EMCR= 0xFFFF;
-	gpEDMA_CC0_regs->TPCC_QEMCR= 0xFFFF;
-    gpEDMA_CC0_regs->TPCC_CCERRCLR= 0xFFFF;
-	gpEDMA_CC0_regs->TPCC_SECR= 0xFFFF;
-
-	gpEDMA_CC1_regs->TPCC_ECR= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_ECRH= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_EECR= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_EECRH= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_ICR= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_ICRH= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_IECR= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_IECRH= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_EMCR= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_EMCRH= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_QEMCR= 0xFFFFFFFF;
-    gpEDMA_CC1_regs->TPCC_CCERRCLR= 0xFFFF;
-	gpEDMA_CC1_regs->TPCC_SECR= 0xFFFFFFFF;
-	gpEDMA_CC1_regs->TPCC_SECRH= 0xFFFFFFFF;
-
-	gpEDMA_CC2_regs->TPCC_ECR= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_ECRH= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_EECR= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_EECRH= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_ICR= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_ICRH= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_IECR= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_IECRH= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_EMCR= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_EMCRH= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_QEMCR= 0xFFFFFFFF;
-    gpEDMA_CC2_regs->TPCC_CCERRCLR= 0xFFFF;
-	gpEDMA_CC2_regs->TPCC_SECR= 0xFFFFFFFF;
-	gpEDMA_CC2_regs->TPCC_SECRH= 0xFFFFFFFF;
-
-	for(i=0; i<NUM_EDMA_TC; i++)
-	{
-		//Clear TC error
-		gpEDMA_TC_regs[i]->TPTC_ERRCLR= 0xF;
-
-		//enable error interrupt
-		gpEDMA_TC_regs[i]->TPTC_ERREN= 
-			(1<<CSL_TPTC_TPTC_ERREN_MMRAERR_SHIFT)
-			|(1<<CSL_TPTC_TPTC_ERREN_TRERR_SHIFT)
-			|(1<<CSL_TPTC_TPTC_ERREN_BUSERR_SHIFT);
-	}
-}
-
-
-void EDMA_event_enable(Uint32 uiCC, Uint32 uiChannel)
-{
-	if(uiChannel<32)
-	{
-		//enable the EDMA channel
-		gpEDMA_CC_regs[uiCC]->TPCC_EESR= 1<<(uiChannel);
-	}
-	else
-	{
-		//enable the EDMA channel
-		gpEDMA_CC_regs[uiCC]->TPCC_EESRH= 1<<(uiChannel-32);
-	}	
-}
-
-void EDMA_event_disable(Uint32 uiCC, Uint32 uiChannel)
-{
-	if(uiChannel<32)
-	{
-		//disable the EDMA channel
-		gpEDMA_CC_regs[uiCC]->TPCC_EECR= 1<<(uiChannel);
-	}
-	else
-	{
-		//disable the EDMA channel
-		gpEDMA_CC_regs[uiCC]->TPCC_EECRH= 1<<(uiChannel-32);
-	}	
-}
-
-void EDMA_interrupt_enable(Uint32 uiCC, Uint32 uiIntNum)
-{
-	if(uiIntNum<32)
-	{
-		//enable the EDMA channel interrupt
-		gpEDMA_CC_regs[uiCC]->TPCC_IESR= 1<<(uiIntNum);
-	}
-	else
-	{
-		//enable the EDMA channel interrupt
-		gpEDMA_CC_regs[uiCC]->TPCC_IESRH= 1<<(uiIntNum-32);
-	}	
-}
-
-void EDMA_interrupt_disable(Uint32 uiCC, Uint32 uiIntNum)
-{
-	if(uiIntNum<32)
-	{
-		//disable the EDMA channel interrupt
-		gpEDMA_CC_regs[uiCC]->TPCC_IECR= 1<<(uiIntNum);
-	}
-	else
-	{
-		//disable the EDMA channel interrupt
-		gpEDMA_CC_regs[uiCC]->TPCC_IECRH= 1<<(uiIntNum-32);
-	}	
-}
-
-/*****************************************************************************
- Prototype    : EDMA_wait
- Description  : wait the pending EDMA complete
- Input        : EDMA_CC_Channel_Num CC_channel
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/30
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_wait(EDMA_CC_Channel_Num CC_channel)
-{
-	CSL_TpccRegs*  EDMACCRegs;
-	unsigned int uiChannel;
-    volatile Uint32 * TPCC_IPR;
-    volatile Uint32 * TPCC_ICR;
-
-	EDMACCRegs= gpEDMA_CC_regs[CC_channel>>16];
-	uiChannel = CC_channel&0xFF;
-
-	if(uiChannel<32)
-	{
-		TPCC_IPR= &EDMACCRegs->TPCC_IPR;
-		TPCC_ICR= &EDMACCRegs->TPCC_ICR;
-	}
-	else
-	{
-		TPCC_IPR= &EDMACCRegs->TPCC_IPRH;
-		TPCC_ICR= &EDMACCRegs->TPCC_ICRH;
-		uiChannel -= 32;
-	}
-	
-	/*wait for completion*/
-	while(0==((*TPCC_IPR)&(1<<(uiChannel))));
-
-	/*clear completion flag*/
-	(*TPCC_ICR)= 1<<(uiChannel);
-}
-
-/*****************************************************************************
- Prototype    : EDMA_Copy
- Description  : EDMA copy function with manual trigger
- Input        : unsigned int srcAddr     
-                unsigned int dstAddr     
-                unsigned int byteCount, <64KB   
-                EDMA_CC_Channel_Num CC_channel  
-                DMA_Wait wait
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/30
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_copy(unsigned int srcAddr, unsigned int dstAddr, 
-	unsigned int byteCount, EDMA_CC_Channel_Num CC_channel, DMA_Wait wait)
-{
-	CSL_TpccRegs*  EDMACCRegs;
-	unsigned int uiChannel;
-    volatile Uint32 * TPCC_ESR;
-    volatile Uint32 * TPCC_IPR;
-    volatile Uint32 * TPCC_ICR;
-
-	EDMACCRegs= gpEDMA_CC_regs[CC_channel>>16];
-	uiChannel = CC_channel&0xFF;
-
-	EDMACCRegs->PARAMSET[uiChannel].OPT= 
-		CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, 
-			CSL_EDMA3_TCCH_DIS, 
-			CSL_EDMA3_ITCINT_DIS, 
-			CSL_EDMA3_TCINT_EN,
-			uiChannel,
-			CSL_EDMA3_TCC_NORMAL,
-			CSL_EDMA3_FIFOWIDTH_NONE, 
-			CSL_EDMA3_STATIC_DIS, 
-			CSL_EDMA3_SYNC_A, 
-			CSL_EDMA3_ADDRMODE_INCR, 
-			CSL_EDMA3_ADDRMODE_INCR);
-	EDMACCRegs->PARAMSET[uiChannel].SRC= GLOBAL_ADDR(srcAddr);
-	EDMACCRegs->PARAMSET[uiChannel].A_B_CNT=CSL_EDMA3_CNT_MAKE(byteCount&0xFFFF, 1);
-	EDMACCRegs->PARAMSET[uiChannel].DST= GLOBAL_ADDR(dstAddr);
-	EDMACCRegs->PARAMSET[uiChannel].SRC_DST_BIDX= 0;
-	EDMACCRegs->PARAMSET[uiChannel].LINK_BCNTRLD= CSL_EDMA3_LINKBCNTRLD_MAKE(0xFFFF, 1);
-	EDMACCRegs->PARAMSET[uiChannel].SRC_DST_CIDX= 0;
-	EDMACCRegs->PARAMSET[uiChannel].CCNT= 1;
-
-	if(uiChannel<32)
-	{
-		TPCC_ESR= &EDMACCRegs->TPCC_ESR;
-		TPCC_IPR= &EDMACCRegs->TPCC_IPR;
-		TPCC_ICR= &EDMACCRegs->TPCC_ICR;
-	}
-	else
-	{
-		TPCC_ESR= &EDMACCRegs->TPCC_ESRH;
-		TPCC_IPR= &EDMACCRegs->TPCC_IPRH;
-		TPCC_ICR= &EDMACCRegs->TPCC_ICRH;
-		uiChannel -= 32;
-	}
-	
-	/*Manually trigger the EDMA*/
-	(*TPCC_ESR)= 1<<(uiChannel);
- 
-	if(wait)
-	{
-		/*wait for completion*/
-		while(0==((*TPCC_IPR)&(1<<(uiChannel))));
-
-		/*clear completion flag*/
-		(*TPCC_ICR)= 1<<(uiChannel);
-	}
-}
-
-/*****************************************************************************
- Prototype    : EDMA_fill
- Description  : EDMA fill function with manual trigger
- Input        : unsigned int address, must align to 8 bytes boundary     
-                unsigned long long data     
-                unsigned int byteCount, must be multiple of 8   
-                EDMA_CC_Channel_Num CC_channel  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2013/8/11
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_fill(unsigned int address, unsigned long long data, 
-	unsigned int byteCount, EDMA_CC_Channel_Num CC_channel)
-{
-	int i;
-	CSL_TpccRegs*  EDMACCRegs;
-	unsigned int uiChannel, uiChannelShift, uiBCNT;
-    volatile Uint32 * TPCC_ESR;
-    volatile Uint32 * TPCC_IPR;
-    volatile Uint32 * TPCC_ICR;
-    unsigned long long tempBuf[128/8];
-    Uint32 tempBufSize=128, headerSize, tailSize;
-
-	if(tempBufSize>byteCount)
-		tempBufSize=byteCount;
-
-	for(i=0; i< tempBufSize/8; i++)
-		tempBuf[i]= data;
-
-	/*split the transfer into 3 sections at 128 byte boundary*/
-	if(address&127)	//header address not start on 128 byte boundary
-	{
-		headerSize= 128- (address&127);
-		if(headerSize>byteCount)
-			headerSize=byteCount;
-		EDMA_copy((Uint32)tempBuf, address, headerSize, CC_channel, DMA_WAIT);
-		address+= headerSize;
-		byteCount-= headerSize;
-	}
-
-	if(byteCount&&((address+byteCount)&127))//tail address not start on 128 byte boundary
-	{
-		tailSize= (address+byteCount)&127;
-		EDMA_copy((Uint32)tempBuf, address+byteCount-tailSize, tailSize, CC_channel, DMA_WAIT);
-		byteCount-= tailSize;
-	}
-	
-	EDMACCRegs= gpEDMA_CC_regs[CC_channel>>16];
-	uiChannel = CC_channel&0xFF;
-	if(uiChannel<32)
-	{
-		TPCC_ESR= &EDMACCRegs->TPCC_ESR;
-		TPCC_IPR= &EDMACCRegs->TPCC_IPR;
-		TPCC_ICR= &EDMACCRegs->TPCC_ICR;
-		uiChannelShift= uiChannel;
-	}
-	else
-	{
-		TPCC_ESR= &EDMACCRegs->TPCC_ESRH;
-		TPCC_IPR= &EDMACCRegs->TPCC_IPRH;
-		TPCC_ICR= &EDMACCRegs->TPCC_ICRH;
-		uiChannelShift= uiChannel - 32;
-	}	
-
-	EDMACCRegs->PARAMSET[uiChannel].OPT= 
-		CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, 
-			CSL_EDMA3_TCCH_DIS, 
-			CSL_EDMA3_ITCINT_DIS, 
-			CSL_EDMA3_TCINT_EN,
-			uiChannel,
-			CSL_EDMA3_TCC_NORMAL,
-			CSL_EDMA3_FIFOWIDTH_NONE, 
-			CSL_EDMA3_STATIC_EN, //keep PARAM unchanged
-			CSL_EDMA3_SYNC_AB, 
-			CSL_EDMA3_ADDRMODE_INCR, 
-			CSL_EDMA3_ADDRMODE_INCR);
-	EDMACCRegs->PARAMSET[uiChannel].SRC= GLOBAL_ADDR(tempBuf);
-	EDMACCRegs->PARAMSET[uiChannel].SRC_DST_BIDX= CSL_EDMA3_BIDX_MAKE(0, 128);
-	EDMACCRegs->PARAMSET[uiChannel].LINK_BCNTRLD= CSL_EDMA3_LINKBCNTRLD_MAKE(0xFFFF, 0);
-	EDMACCRegs->PARAMSET[uiChannel].SRC_DST_CIDX= 0;
-	EDMACCRegs->PARAMSET[uiChannel].CCNT= 1;
-
-	while(byteCount) 	//the reminding must be multiple of 128 bytes
-	{
-		uiBCNT= byteCount/128;
-		if(uiBCNT>65535)
-			uiBCNT= 65535;
-	
-		EDMACCRegs->PARAMSET[uiChannel].A_B_CNT= CSL_EDMA3_CNT_MAKE(128, uiBCNT);
-		EDMACCRegs->PARAMSET[uiChannel].DST= GLOBAL_ADDR(address);
-		
-		/*Manually trigger the EDMA*/
-		(*TPCC_ESR)= 1<<(uiChannelShift);
-	 
-		/*wait for completion*/
-		while(0==((*TPCC_IPR)&(1<<(uiChannelShift))));
-
-		/*clear completion flag*/
-		(*TPCC_ICR)= 1<<(uiChannelShift);
-
-		byteCount -= uiBCNT*128;
-		address += uiBCNT*128;
-	}
-}
-
-/*****************************************************************************
- Prototype    : IDMA_wait
- Description  : wait the pending IDMA complete
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void IDMA_wait()
-{
-	/* Wait until copying is completed */
-	while (gpCGEM_regs->IDMA1_STAT); 
-}
-/*****************************************************************************
- Prototype    : IDMA_copy
- Description  : implement the data copy via IDMA
- Input        : unsigned int srcAddr    
-                unsigned int dstAddr    
-                unsigned int byteCount, <64KB  
-                IDMA_Wait wait          
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brigthon
-    Modification : Created function
-
-*****************************************************************************/
-void IDMA_copy(unsigned int srcAddr, unsigned int dstAddr, 
-	unsigned int byteCount, DMA_Wait wait)
-{
-	gpCGEM_regs->IDMA1_SOURCE= srcAddr;
-	gpCGEM_regs->IDMA1_DEST= dstAddr;
-	gpCGEM_regs->IDMA1_COUNT= byteCount&0xFFFC;
-
-	if(wait)
-	{
-		/* Wait until copying is completed */
-		while (gpCGEM_regs->IDMA1_STAT); 
-	}
-}
-/*****************************************************************************
- Prototype    : EDMA_CC_error_handler
- Description  : Edma channel controller error processing
- Input        : Uint32 edmaNum, EDMA module number (0~2)  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/11/7
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_CC_error_handler(Uint32 edmaNum)
-{
-	int i;
-	CSL_TpccRegs*  EDMACCRegs= gpEDMA_CC_regs[edmaNum];
-	Uint32 EMR, EMRH= 0, QEMR, CCERR;
-
-	//read error status
-	EMR= EDMACCRegs->TPCC_EMR;
-	QEMR= EDMACCRegs->TPCC_QEMR;
-	CCERR= EDMACCRegs->TPCC_CCERR;
-	exception_record.status.ext_sts.info.edma.CC_info.EMR= EMR;
-	exception_record.status.ext_sts.info.edma.CC_info.QEMR= QEMR;
-	exception_record.status.ext_sts.info.edma.CC_info.CCERR= CCERR;
-
-	//clear error status
-	EDMACCRegs->TPCC_EMCR= EMR;
-	EDMACCRegs->TPCC_QEMCR= QEMR;
-	EDMACCRegs->TPCC_CCERRCLR= CCERR;
-
-	//channel 32~63 for EDMA CC1 and CC2
-	if(0<edmaNum)
-	{
-		//read error status
-		EMRH= EDMACCRegs->TPCC_EMRH;
-		exception_record.status.ext_sts.info.edma.CC_info.EMRH= EMRH;
-
-		//clear error status
-		EDMACCRegs->TPCC_EMCRH= EMRH;
-	}
-
-	for(i=0; i<32; i++)
-	{
-		if((EMR>>i)&1)
-			printf("    EDMA Channel %d event missed.\n", i);
-		if((EMRH>>i)&1)
-			printf("    EDMA Channel %d event missed.\n", i+32);
-	}
-
-	for(i=0; i<8; i++)
-	{
-		if((QEMR>>i)&1)
-			printf("    QDMA Channel %d event missed.\n", i);
-	}
-
-	for(i=0; i<4; i++)
-	{
-		if((CCERR>>i)&1)
-			printf("    Queue %d Watermark/threshold has been exceeded.\n", i);
-	}
-
-	if(CCERR&CSL_TPCC_TPCC_CCERR_TCCERR_MASK)
-		puts("    Total number of allowed TCCs has been reached.");
-	
-}
-/*****************************************************************************
- Prototype    : EDMA_TC_error_handler
- Description  : Edma transfer controller error processing
- Input        : CSL_TptcRegs * edmaTCRegs  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/11/7
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_TC_error_handler(CSL_TptcRegs * edmaTCRegs)
-{
-	Uint32 ERRSTAT, ERRDET, STAT;
-
-	//read error status
-	ERRSTAT= edmaTCRegs->TPTC_ERRSTAT;
-	ERRDET= edmaTCRegs->TPTC_ERRDET;
-	exception_record.status.ext_sts.info.edma.TC_info.ERRSTAT=ERRSTAT ;
-	exception_record.status.ext_sts.info.edma.TC_info.ERRDET= ERRDET;
-
-	//clear error
-	edmaTCRegs->TPTC_ERRCLR= ERRSTAT;
-
-	if(ERRSTAT&CSL_TPTC_TPTC_ERRSTAT_MMRAERR_MASK)
-		puts("      User attempted to read or write to an invalid address in configuration memory map.");
-	if(ERRSTAT&CSL_TPTC_TPTC_ERRSTAT_TRERR_MASK)
-		puts("      TR detected that violates constant addressing mode transfer (SAM or DAM is set) alignment rules or has ACNT or BCNT== 0.");
-	if(ERRSTAT&CSL_TPTC_TPTC_ERRSTAT_BUSERR_MASK)
-	{
-		puts("      EDMA3TC has detected an error at source or destination address.");
-
-		STAT= ERRDET&CSL_TPTC_TPTC_ERRDET_STAT_MASK;
-
-		if(STAT>=8)
-			printf("      write error (%d). ",STAT);
-		else if(STAT>=1)
-			printf("      read error (%d). ",STAT);
-		else
-			printf("      no error!?");
-
-		printf("TCC= %d. TCINTEN= %d. TCCHEN= %d\n",
-			(ERRDET&CSL_TPTC_TPTC_ERRDET_TCC_MASK)>>CSL_TPTC_TPTC_ERRDET_TCC_SHIFT,
-			(ERRDET&CSL_TPTC_TPTC_ERRDET_TCINTEN_MASK)>>CSL_TPTC_TPTC_ERRDET_TCINTEN_SHIFT,
-			(ERRDET&CSL_TPTC_TPTC_ERRDET_TCCHEN_MASK)>>CSL_TPTC_TPTC_ERRDET_TCCHEN_SHIFT);
-	}
-		
-}
-/*****************************************************************************
- Prototype    : EDMA_error_handler
- Description  : EDMA error processing function
- Input        : Uint32 edmaNum    
-                Uint32 errorFlag  
-					error flag bit fields are defined as below 
-					(follow the sequence in CIC)
-					0 EDMACC_ERRINT EDMA3CC error interrupt          
-					2 EDMATC_ERRINT0 EDMA3TC0 error interrupt
-					3 EDMATC_ERRINT1 EDMA3TC1 error interrupt
-					4 EDMATC_ERRINT2 EDMA3TC2 error interrupt
-					5 EDMATC_ERRINT3 EDMA3TC3 error interrupt
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EDMA_error_handler(Uint32 edmaNum, Uint32 errorFlag)
-{
-	int i;
-	
-	printf("  EDMA module %d error\n", edmaNum);
-	if(errorFlag&1)
-		EDMA_CC_error_handler(edmaNum);
-
-	errorFlag >>= 2;
-
-	for(i=0; i<4; i++)
-	{
-		if(errorFlag&(1<<i))
-		{
-			printf("    TC %d error happened\n", i);
-			if(0==edmaNum)
-				EDMA_TC_error_handler(gpEDMA_TC_regs[i]);
-			else if(1==edmaNum)
-				EDMA_TC_error_handler(gpEDMA_TC_regs[2+i]);
-			else if(2==edmaNum)
-				EDMA_TC_error_handler(gpEDMA_TC_regs[6+i]);
-		}
-	}
-}
-
-/*======================memory protection==============================*/
-/*code and data related to CorePac MPAX configuration should be allocated in LL2*/
-#pragma DATA_SECTION(mem_prot_key,".far:Core_MPAX")
-unsigned int mem_prot_key[4] = {0xBFBFBFBF, 0xFE29, 3, 4};
-/*****************************************************************************
- Prototype    : lock_mem_prot_regs
- Description  : lock memory protection registers
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-#pragma CODE_SECTION (lock_mem_prot_regs, ".text:Core_MPAX")
-void lock_mem_prot_regs()
-{
-	int i;
-	
-	/*1. Write a 1 to the KEYR field of the MPLKCMD register. This resets some internal
-	status for the MPLK0 through MPLK3 registers.*/
-	gpCGEM_regs->MPLKCMD = (1<<CSL_CGEM_MPLKCMD_KEYR_SHIFT);
-	
-	/*2. Write the key to MPLK0 through MPLK3. All four registers must be written
-	exactly once. They may be written in any order.*/
-	for(i=0; i<4; i++)
-	{
-		gpCGEM_regs->MPLK[i] = mem_prot_key[i];
-	}
-
-	/*3. Write a 1 to the LOCK field of the MPLKCMD register. This engages the lock.*/
-	gpCGEM_regs->MPLKCMD = (1<<CSL_CGEM_MPLKCMD_LOCK_SHIFT);
-
-	/*wait to make sure it is locked*/
-	while(0==(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK));
-}
-
-/*****************************************************************************
- Prototype    : unlock_mem_prot_regs
- Description  : unlock memory protection registers
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-#pragma CODE_SECTION (unlock_mem_prot_regs, ".text:Core_MPAX")
-void unlock_mem_prot_regs()
-{
-	int i;
-	
-	/*1. Write a 1 to the KEYR field in the MPLKCMD register. This resets some internal
-	status for the MPLK0 through the MPLK3 registers.*/
-	gpCGEM_regs->MPLKCMD = (1<<CSL_CGEM_MPLKCMD_KEYR_SHIFT);
-
-	/*2. Write the unlock key to MPLK0 through the MPLK3 registers. The hardware
-	compares the written value with the stored key value. Software must write to all
-	four registers exactly once. The writes can arrive in any order.*/
-	for(i=0; i<4; i++)
-	{
-		gpCGEM_regs->MPLK[i] = mem_prot_key[i];
-	}
-
-	/*3. Write a 1 to the UNLOCK field in the MPLKCMD register. If the key written in
-	step 2 matches the stored key, the hardware disengages the lock. If the key written
-	in step 2 does not match, the hardware signals an exception. The hardware
-	reports the fault address as the address of the MPLKCMD register.*/
-	gpCGEM_regs->MPLKCMD = (1<<CSL_CGEM_MPLKCMD_UNLOCK_SHIFT);
-
-	/*wait to make sure it is unlocked*/
-	while(1==(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK));
-}
-
-/*****************************************************************************
- Prototype    : L1_MPPA_setup
- Description  : setup the memory protection for local L1 memory
- Input        : volatile Uint32 MPPA_regs[], Uint32 MPPA[]  
- Output       : None
- Return Value : 
-
-usage example:
- Uint32 MPPA[16]=
- {
-	MP_LOCAL|MP_SR|MP_UR, 			//page 0 for read only
-	MP_LOCAL|MP_SR|MP_SW|MP_UR|MP_UW, 	//page 1 for read/write
-	......
- }
- ......
-	L1_MPPA_setup(gpCGEM_regs->L1PMPPA, MPPA);
-
-  History        :
-  1.Date         : 2012/12/6
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void L1_MPPA_setup(volatile Uint32 MPPA_regs[], Uint32 MPPA[])
-{
-	int i;
-
-	if(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK)
-		unlock_mem_prot_regs();
-		
-	/*clear any memory protection fault*/
-	gpCGEM_regs->L1PMPFCR = 1;
-	gpCGEM_regs->L1DMPFCR = 1;
-
-	/*setup the memory protection attributes for 32 pages*/
-	for(i=0; i<16; i++)
-	{
-		MPPA_regs[i] = MPPA[i];
-	}
-
-	lock_mem_prot_regs();
-}
-
-/*****************************************************************************
- Prototype    : L1P_memory_protection_cfg
- Description  : config "AccessPermisionMask" for L1P
- Input        : Uint32 AccessPermisionMask  
- Output       : None
- Return Value : 
-*****************************************************************************/
-void L1P_memory_protection_cfg(Uint32 AccessPermisionMask)
-{
-	int i;
-
-	if(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK)
-		unlock_mem_prot_regs();
-
-	/*clear any memory protection fault*/
-	gpCGEM_regs->L1PMPFCR = 1;
-
-	/*set L1P only for cacheable local execution, disable all external access*/
-	for(i=0; i<16; i++)
-	{
-		gpCGEM_regs->L1PMPPA[i] = AccessPermisionMask;
-	}
-
-	lock_mem_prot_regs();
-}
-
-/*****************************************************************************
- Prototype    : L1D_memory_protection_cfg
- Description  : config "AccessPermisionMask" for L1P
- Input        : Uint32 AccessPermisionMask  
- Output       : None
- Return Value : 
-*****************************************************************************/
-void L1D_memory_protection_cfg(Uint32 AccessPermisionMask)
-{
-	int i;
-
-	if(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK)
-		unlock_mem_prot_regs();
-
-	/*clear any memory protection fault*/
-	gpCGEM_regs->L1DMPFCR = 1;
-
-	/*set L1P only for cacheable local execution, disable all external access*/
-	for(i=0; i<16; i++)
-	{
-		gpCGEM_regs->L1DMPPA[i] = AccessPermisionMask;
-	}
-
-	lock_mem_prot_regs();
-}
-
-/*****************************************************************************
- Prototype    : L1_cache_protection
- Description  : protect L1 as cache
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void L1_cache_protection()
-{
-	/*set L1P only for cacheable local execution, disable all external access*/
-	L1P_memory_protection_cfg(0);
-	
-	/*set L1D only for cacheable local read/write, disable all external access*/
-	L1D_memory_protection_cfg(0);
-}
-
-
-/*****************************************************************************
- Prototype    : LL2_MPPA_setup
- Description  : setup the memory protection for local L2 memory
- Input        : Uint32 MPPA[]  
- Output       : None
- Return Value : 
-usage example:
- Uint32 MPPA[32]=
- {
-	MP_LOCAL|MP_SX|MP_UX, 			//page 0 for local code only
-	MP_LOCAL|MP_SR|MP_SW|MP_UR|MP_UW, 	//page 1 for local data only
-	......
- }
- ......
-	LL2_MPPA_setup(MPPA);
-
-  History        :
-  1.Date         : 2012/10/5
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void LL2_MPPA_setup(Uint32 MPPA[])
-{
-	int i;
-
-	if(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK)
-		unlock_mem_prot_regs();
-		
-	/*clear any memory protection fault*/
-	gpCGEM_regs->L2MPFCR = 1;
-
-	/*setup the memory protection attributes for 32 pages*/
-	for(i=0; i<32; i++)
-	{
-		gpCGEM_regs->L2MPPA[i] = MPPA[i];
-	}
-
-	lock_mem_prot_regs();
-}
-
-/*****************************************************************************
- Prototype    : LL2_Memory_Protection_cfg
- Description  : config "AccessPermisionMask" for local L2 memory section from 
-				"startAddress" with "byteCount" size
- Input        : Uint32 startAddress         
-                Uint32 byteCount            
-                Uint32 AccessPermisionMask  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/5
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void LL2_Memory_Protection_cfg(Uint32 startAddress,
-	Uint32 byteCount, Uint32 AccessPermisionMask)
-{
-	int i;
-	Uint32 uiEndAddress;
-	Uint32 uiPageIndex, uiNumPages, uiPageSize, uiPageAddressMask, uiPageShift;
-	TDSP_Board_Type DSP_Board_Type;
-
-	if(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK)
-		unlock_mem_prot_regs();
-
-	DSP_Board_Type = KeyStone_Get_dsp_board_type();
-
-	/*L2 memory protection size is 32KB for TCI6614, C6670,
-	it is 16KB for C6678*/
-	uiPageSize= 32*1024;
-	uiPageAddressMask= 32*1024-1;
-	uiPageShift= 15;
-	if(C6678_EVM == DSP_Board_Type)
-	{
-		uiPageSize= 16*1024;
-		uiPageAddressMask= 16*1024-1;
-		uiPageShift= 14;
-	}
-
-	if(startAddress>=0x10800000)
-	{
-		printf("LL2 memory protection start Address 0x%x is not a local address\n",
-			startAddress);
-		startAddress &= 0xFFFFFF;	 /*convert to local address*/
-	}
-	uiEndAddress= startAddress+ byteCount;
-
-	if(startAddress&uiPageAddressMask)
-	{
-		printf("LL2 memory protection start Address 0x%x does not align to page boundary\n",
-			startAddress);
-		startAddress &= (~uiPageAddressMask);
-	}
-	uiPageIndex= (startAddress-0x800000)>>uiPageShift;
-
-	byteCount= uiEndAddress- startAddress;
-	if(byteCount&uiPageAddressMask)
-	{
-		printf("LL2 memory protection section size 0x%x is not multiple of page size\n",
-			byteCount);
-		byteCount = (byteCount+uiPageSize)&(~uiPageAddressMask);
-	}
-	uiNumPages= byteCount>>uiPageShift;
-
-	for(i= 0; i<uiNumPages; i++)
-		gpCGEM_regs->L2MPPA[uiPageIndex+i] = AccessPermisionMask;
-
-	lock_mem_prot_regs();
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_CorePac_AID_map
- Description  : map CorePac AID to PrivID:
-        map_table[0] assign the PrivID for AID0,
-        map_table[1] assign the PrivID for AID1
-        ......
-        map_table[5] assign the PrivID for AID5
- Input        : Uint8 map_table[]  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/5
-    Author       : Zhan
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_CorePac_AID_map(Uint8 map_table[])
-{
-	int i;
-	Uint32 *PAMAP= (Uint32 *)&(gpCGEM_regs->PAMAP0);
-
-	/*map all PrivID to AIDx by default*/
-	for(i=0; i<16; i++)
-		PAMAP[i]= CSL_CGEM_PAMAP0_AID_MASK;
-
-	/*map AID0~AID5*/
-	for(i=0; i<6; i++)
-	{
-		if(map_table[i]<16) /*PrivID must be less than 16*/
-			PAMAP[map_table[i]]= i;
-	}
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_PrivID_Remap
- Description  : privilege ID remap to AID
- Input        : int privID  
-                int AID     
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/5
-    Author       : Zhan
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_PrivID_Remap(int privID, int AID)
-{
-	volatile unsigned int * pamapReg = NULL;
-	unsigned int val = 0;
-
-	pamapReg = (volatile unsigned int *)(&gpCGEM_regs->PAMAP0 + privID);
-
-	if(AID >= MAX_AID_NUM)
-		AID = 0;
-	val = *pamapReg;
-
-	val &= (~CSL_CGEM_PAMAP0_AID_MASK);
-
-	val |= ((AID<<CSL_CGEM_PAMAP0_AID_SHIFT) & CSL_CGEM_PAMAP0_AID_MASK);
-
-	*pamapReg = val;
-
-	return;
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MPAX_seg_setup
- Description  : configure one MPAX segment
- Input        : MPAX_Regs * MPAX_regs       
-                Uint32 BADDR                
-                Uint32 RADDR                
-                Uint32 SegementSize         
-                Uint32 AccessPermisionMask  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-#pragma CODE_SECTION (KeyStone_MPAX_seg_setup, ".text:Core_MPAX")
-void KeyStone_MPAX_seg_setup(MPAX_Regs * MPAX_regs, Uint32 BADDR, 
-	Uint32 RADDR, Uint32 SegementSize, Uint32 AccessPermisionMask)
-{
-	Uint32 SegSizeMask, SegSizeBits;
-
-	if(SegementSize<4*1024)
-	{
-		printf("Segment size %d is less than 4KB. ", SegementSize);
-		SegementSize = 4*1024;
-		printf("Extended segment size to 4KB.\n");
-	}
-	
-	SegSizeBits= 31 - _lmbd(1, SegementSize);
-	SegSizeMask= (1<<SegSizeBits)-1;
-	if(SegementSize&SegSizeMask)
-	{
-		printf("Segment size 0x%x is not power of 2. ", SegementSize);
-		SegSizeBits += 1;
-		SegementSize= (1<<SegSizeBits);
-		SegSizeMask= (1<<SegSizeBits)-1;
-		printf("Extended segment size to 0x%x.\n", SegementSize);
-	}
-
-	if(BADDR&SegSizeMask)
-	{
-		printf("Segment base address 0x%x does not start from power-of-2 boundary corresponds to segment size 0x%x.\n", 
-			BADDR, SegementSize);
-		BADDR &= (~SegSizeMask);
-		printf("Extended base address to 0x%x.\n", BADDR);
-	}
-	if(RADDR&(SegSizeMask>>4))
-	{
-		printf("Segment replacement address 0x%x does not start from power-of-2 boundary corresponds to segment size 0x%x.\n", 
-			RADDR, SegementSize);
-		RADDR &= (~(SegSizeMask>>4));
-		printf("Extended replacement address to 0x%x.\n", RADDR);
-	}
-	
-	MPAX_regs->MPAXH= BADDR|(SegSizeBits-1); 
-	MPAX_regs->MPAXL= RADDR|AccessPermisionMask; 
-
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_XMC_MPAX_setup
- Description  : configure multiple MPAX segments in XMC with a configuration
-                table.
-	Please note, the code of this function or the data used by this function
-	(stack, parameters...) can not be put in the segment that will be modified
-	by this function. Normally, to put this function and its related data in 
-	LL2 is a good idea.
- Input        : MPAX_Config MPAX_cfg[]  
-                Uint32 firstSeg         
-                Uint32 numSegs          
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-#pragma CODE_SECTION (KeyStone_XMC_MPAX_setup, ".text:Core_MPAX")
-void KeyStone_XMC_MPAX_setup(MPAX_Config MPAX_cfg[], 
-	Uint32 firstSeg, Uint32 numSegs)
-{
-	int i;
-
-    if(firstSeg >= 16)
-    {
-        printf("The XMC MPAX segment number %d >= 16, not supported.\n ", firstSeg);
-        return;
-    }
-
-	if(gpCGEM_regs->MPLKSTAT&CSL_CGEM_MPLKSTAT_LK_MASK)
-		unlock_mem_prot_regs();
-
-	/*CAUTION:
-	A MPAX segment can only be modified when there is no access to the space 
-	of this segment. Any data in cache or prefetch buffer from the space of this 
-	segment must be writeback and invalidated before the segment modification.	
-	It is recommended to configure the MPAX at the very beginning of application
-	software before any shared memory is used. Code and data for CorePac MPAX 
-	configuration should be allocated in LL2.
-	If a MPAX segment must be modified on-the-fly, the safer way is, to write 
-	the new configuration to a unused higher segment, and then clear the old 
-	segment. This is based on the fact that higher numbered segments take 
-	precedence over lower numbered segments.	*/
-	CACHE_wbInvAllL2(CACHE_WAIT);
-	CSL_XMC_invalidatePrefetchBuffer();
-	_mfence();
-	_mfence(); 	//ensure all writeback invalidate have completed.
-
-	for(i=numSegs-1; i>=0 ; i--)
-    {   
-		KeyStone_MPAX_seg_setup((MPAX_Regs *)&gpXMC_regs->XMPAX[firstSeg+i], 
-			MPAX_cfg[i].BADDR, MPAX_cfg[i].RADDR, 
-			MPAX_cfg[i].SegementSize, MPAX_cfg[i].AccessPermisionMask);
-    }
-
-	lock_mem_prot_regs();
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_SMS_MPAX_setup
- Description  : configure multiple MPAX segments in SMS of MSMC with a conf-
-                iguration table
- Input        : MPAX_Config MPAX_cfg[]  
-                Uint32 firstSeg         
-                Uint32 numSegs          
-                Uint32 PrivID           
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_SMS_MPAX_setup(MPAX_Config MPAX_cfg[], 
-	Uint32 firstSeg, Uint32 numSegs, Uint32 PrivID)
-{
-	int i;
-
-	if(	gpMSMC_regs->SMS_MPAX_LCKSTAT&(1<<PrivID))
-		CSL_MSMC_unlockSMS(PrivID);
-
-	/*CAUTION:
-	A MPAX segment can only be modified when there is no access to this segment. 
-	It is recommended to configure the MPAX at the very beginning of application
-	software before any shared memory is used. 
-	If a MPAX segment must be modified on-the-fly, the safer way is, to write 
-	the new configuration to a unused higher segment, and then clear the old 
-	segment. This is based on the fact that higher numbered segments take 
-	precedence over lower numbered segments.	*/
-	for(i=numSegs-1; i>=0 ; i--)
-		KeyStone_MPAX_seg_setup(
-			(MPAX_Regs *)&gpMSMC_regs->SMS_MPAX_PER_PRIVID[PrivID].SMS[firstSeg+i], 
-			MPAX_cfg[i].BADDR, MPAX_cfg[i].RADDR, 
-			MPAX_cfg[i].SegementSize, MPAX_cfg[i].AccessPermisionMask);
-
-	CSL_MSMC_lockSMS(PrivID);
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_SES_MPAX_setup
- Description  : configure multiple MPAX segments in SES of MSMC with a conf-
-                iguration table
- Input        : MPAX_Config MPAX_cfg[]  
-                Uint32 firstSeg         
-                Uint32 numSegs          
-                Uint32 PrivID           
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_SES_MPAX_setup(MPAX_Config MPAX_cfg[], 
-	Uint32 firstSeg, Uint32 numSegs, Uint32 PrivID)
-{
-	int i;
-
-	if(	gpMSMC_regs->SES_MPAX_LCKSTAT&(1<<PrivID))
-		CSL_MSMC_unlockSES(PrivID);
-
-	/*CAUTION:
-	A MPAX segment can only be modified when there is no access to this segment. 
-	It is recommended to configure the MPAX at the very beginning of application
-	software before any shared memory is used. 
-	If a MPAX segment must be modified on-the-fly, the safer way is, to write 
-	the new configuration to a unused higher segment, and then clear the old 
-	segment. This is based on the fact that higher numbered segments take 
-	precedence over lower numbered segments.	*/
-	for(i=numSegs-1; i>=0 ; i--)
-		KeyStone_MPAX_seg_setup(
-			(MPAX_Regs *)&gpMSMC_regs->SES_MPAX_PER_PRIVID[PrivID].SES[firstSeg+i], 
-			MPAX_cfg[i].BADDR, MPAX_cfg[i].RADDR, 
-			MPAX_cfg[i].SegementSize, MPAX_cfg[i].AccessPermisionMask);
-
-	CSL_MSMC_lockSES(PrivID);
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MSMC_MP_interrupt_en
- Description  : Enable MSMC Memory protection error interrupt for PrivIDs
-                indicated by "PRIVID_MASK"
- Input        : Uint32 PRIVID_MASK  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Zhan
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_MSMC_MP_interrupt_en(Uint32 PRIVID_MASK)
-{
-	if(gpMSMC_regs->CFGLCKSTAT&CSL_MSMC_CFGLCKSTAT_WSTAT_MASK)
-		CSL_MSMC_unlockNonMPAX();
-
-    /*clear MP fault record*/
-    gpMSMC_regs->SMPFCR = 1;
-
-    /*clear interrupt error status flag*/
-	gpMSMC_regs->SMIRC  = (PRIVID_MASK)<<CSL_MSMC_SMIRC_PFIC_SHIFT;
-
-	//enable the interrupt
-	gpMSMC_regs->SMIESTAT |= (PRIVID_MASK<<CSL_MSMC_SMIESTAT_PFIESTAT_SHIFT);
-
-	CSL_MSMC_lockNonMPAX();
-}
-/*****************************************************************************
- Prototype    : memory_protection_exception_handler
- Description  : memory protection processing
- Input        : unsigned int MPFAR  
-                unsigned int MPFSR  
- Output       : None
- Return Value : 
-*****************************************************************************/
-void memory_protection_exception_handler(unsigned int MPFAR, 
-	unsigned int MPFSR)
-{
-	unsigned int master_id;
-
-	if(0 == MPFSR)
-		return;
-
-	exception_record.status.ext_sts.info.memory.fault_address= MPFAR;
-	exception_record.status.ext_sts.info.memory.fault_status.MPFSR= MPFSR;
-
-	if (MPFSR & CSL_CGEM_L2MPFSR_LOCAL_MASK) {
-		printf("  memory protection exception caused by local access at 0x%x\n", 
-			MPFAR);
-	}
-	else
-	{
-		master_id = (MPFSR&CSL_CGEM_L2MPFSR_FID_MASK)>>
-			CSL_CGEM_L2MPFSR_FID_SHIFT;
-
-		printf("  memory protection exception caused by master with ID %d at 0x%x\n", 
-			master_id, MPFAR);
-	}
-	
-	if (MPFSR & CSL_CGEM_L2MPFSR_UX_MASK) {
-		puts("  User Execute violation");
-	}
-	if (MPFSR & CSL_CGEM_L2MPFSR_UW_MASK) {
-		puts("  User Write violation");
-	}
-	if (MPFSR & CSL_CGEM_L2MPFSR_UR_MASK) {
-		puts("  User Read violation");
-	}
-	if (MPFSR & CSL_CGEM_L2MPFSR_SX_MASK) {
-		puts("  Supervisor Execute violation");
-	}
-	if (MPFSR & CSL_CGEM_L2MPFSR_SW_MASK) {
-		puts("  Supervisor Write violation");
-	}
-	if (MPFSR & CSL_CGEM_L2MPFSR_SR_MASK) {
-		puts("  Supervisor Read violation");
-	}
-	
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MSMC_protection_exception_handler
- Description  : MSMC memory protection processing
- Input        : None
- Output       : None
- Return Value : 
-*****************************************************************************/
-void KeyStone_MSMC_protection_exception_handler()
-{
-	unsigned int master_id;
-    unsigned int priv_id;
-    unsigned int address;
-    unsigned int NM;
-
-	address = gpMSMC_regs->SMPFAR;
-	
-	master_id = (gpMSMC_regs->SMPFR&CSL_MSMC_SMPFR_FMSTID_MASK)>>
-		CSL_MSMC_SMPFR_FMSTID_SHIFT;
-    priv_id = (gpMSMC_regs->SMPFR&CSL_MSMC_SMPFR_FPID_MASK)>>
-		CSL_MSMC_SMPFR_FPID_SHIFT;
-
-	exception_record.status.ext_sts.info.memory.fault_address= address;
-	exception_record.status.ext_sts.info.memory.fault_status.SMPFR= gpMSMC_regs->SMPFR;
-
-    NM = (gpMSMC_regs->SMPFXR & CSL_MSMC_SMPFXR_NM_MASK) >> CSL_MSMC_SMPFXR_NM_SHIFT;
-
-	printf("  memory protection exception caused by master %d (PrivID= %d) at address 0x%x\n", 
-		master_id, priv_id, address);
-
-    if(1 == NM)
-    {
-        printf("  Fault is caused by the address not matching any of the segment BADDR\n");        
-    }
-
-	if(gpMSMC_regs->CFGLCKSTAT&CSL_MSMC_CFGLCKSTAT_WSTAT_MASK)
-	    CSL_MSMC_unlockNonMPAX();
-    /*clear fault record*/
-    gpMSMC_regs->SMPFCR = 1;
-    /*clear interrupt error status flag*/
-	gpMSMC_regs->SMIRC  = (1<<priv_id)<<CSL_MSMC_SMIRC_PFIC_SHIFT;
-    CSL_MSMC_lockNonMPAX();            
-}
-
-/*==========Peripherals registers and internal data buffer MPU=============*/
-CSL_MpuRegs * gpMPU_regs[8]= {
-	(CSL_MpuRegs *)CSL_MPU_0_REGS,
-	(CSL_MpuRegs *)CSL_MPU_1_REGS,
-	(CSL_MpuRegs *)CSL_MPU_2_REGS,
-	(CSL_MpuRegs *)CSL_MPU_3_REGS,
-
-	//for C6670, TCI6614
-	(CSL_MpuRegs *)(CSL_MPU_3_REGS+ 1*(CSL_MPU_1_REGS- CSL_MPU_0_REGS)),
-
-	//for TCI6614 only
-	(CSL_MpuRegs *)(CSL_MPU_3_REGS+ 2*(CSL_MPU_1_REGS- CSL_MPU_0_REGS)),
-	(CSL_MpuRegs *)(CSL_MPU_3_REGS+ 3*(CSL_MPU_1_REGS- CSL_MPU_0_REGS)),
-	(CSL_MpuRegs *)(CSL_MPU_3_REGS+ 4*(CSL_MPU_1_REGS- CSL_MPU_0_REGS))
-};	
-
-/*number of used MPU ranges*/
-unsigned int gUsed_MPPA_ranges [8] = {0,0,0,0,0,0,0,0};
-
-MPU_Addr gstruMpuAddrRange[] = 
-{
-        {0x01D00000, 0x026203FF},
-        {0x34000000, 0x340BFFFF},
-        {0x02A00000, 0x02ABFFFF},
-        {0x02640000, 0x026407FF},
-		//for C6670, TCI6614
-        {0x01F80000, 0x0215FFFF},
-		//for TCI6614
-        {0x33600000, 0x337FFFFF},
-        {0x00000000, 0xFFFFFFFF},
-        {0x70000000, 0x7FFFFFFF}
-};
-
-/*****************************************************************************
- Prototype    : TN_MPU5_constant
- Description  : special intial constant for MPU5 on Turbo Nyquist
- Input        : None
- Output       : None
- Return Value : 
-*****************************************************************************/
-void TN_MPU5_constant()
-{
-	TDSP_Board_Type DSP_Board_Type = KeyStone_Get_dsp_board_type();
-
-	/*For Turbo Nyquist, add following code to modify initial value,
-	Or user can modify the initail values directly*/
-	if(C6670_EVM== DSP_Board_Type)
-	{
-		gpMPU_regs[5]= (CSL_MpuRegs *)0x35000000;
-		gstruMpuAddrRange[5].StartAddr= 0x35020000;
-		gstruMpuAddrRange[5].EndAddr= 0x3521FFFF;
-	}
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MPU_range_setup
- Description  : configure one range in peripheral MPU
- Input        : CSL_MpuProg_regionRegs *MPPA_regs  
-                Uint32 uiStartAddress              
-                Uint32 uiEndAddress                
-                Uint32 AccessPermisionMask         
- Output       : None
- Return Value : 
-*****************************************************************************/
-void KeyStone_MPU_range_setup(CSL_MpuProg_regionRegs *MPPA_regs, 
-	Uint32 uiStartAddress, Uint32 uiEndAddress, Uint32 AccessPermisionMask)
-{
-    unsigned int boundaryMask; 
-
-	//the address must align to 1KB boundary on KeyStone DSPs
-	boundaryMask= 0x3FF; 
-	
-    if(0 != (uiStartAddress&boundaryMask))
-    {
-    	printf("aligned start address 0x%x to 0x%x\n",
-    		uiStartAddress,	uiStartAddress&(~boundaryMask));
-    	uiStartAddress= uiStartAddress&(~boundaryMask);
-    }
-
-    MPPA_regs->PROG_START_ADDRESS = uiStartAddress;
-    MPPA_regs->PROG_END_ADDRESS = uiEndAddress;   
-    MPPA_regs->PROG_MPPA = AccessPermisionMask;
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MPU_setup
- Description  : peripherals MPU ranges configuration
- Input        : Uint32 uiMPU_num: number of the MPU to be setup
-                MPU_Range_Config MPU_cfg[]: MPU ranges configuration table
-                Uint32 numRangeCfg: number of ranges to be configured          
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/12/15
-    Author       : Brighton Feng
-    Modification : Created function
-*****************************************************************************/
-void KeyStone_MPU_setup(Uint32 uiMPU_num, 
-	MPU_Range_Config MPU_cfg[], Uint32 numRangeCfg)
-{
-    int i;
-    unsigned int mpuNumProgmableRange;
-    CSL_MpuRegs * mpuRegs;
-
-	/*For Turbo Nyquist, add following code to modify initial value,
-	Or user can modify the initail values directly*/
-	if(5==uiMPU_num)
-		TN_MPU5_constant();
-
-	mpuRegs= gpMPU_regs[uiMPU_num];
-
-    mpuNumProgmableRange = (mpuRegs->CONFIG & CSL_MPU_CONFIG_NUM_PROG_MASK)>>CSL_MPU_CONFIG_NUM_PROG_SHIFT;
-    if(mpuNumProgmableRange == 0)
-    {   
-        mpuNumProgmableRange = 16;
-    }
-
-	if(numRangeCfg>mpuNumProgmableRange)
-    {
-        printf("MPU %d programmable ranges %d < %d.\n", 
-        	uiMPU_num, mpuNumProgmableRange, numRangeCfg);
-        numRangeCfg=mpuNumProgmableRange;            
-    }
-    else if(numRangeCfg<mpuNumProgmableRange)
-    {
-        printf("MPU %d setup %d of %d ranges.\n", 
-        	uiMPU_num, numRangeCfg, mpuNumProgmableRange);
-    }
-
-    for(i=0; i<numRangeCfg; i++)
-    {
-	    if((MPU_cfg[i].StartAddr < gstruMpuAddrRange[uiMPU_num].StartAddr) 
-	      ||(MPU_cfg[i].EndAddr > gstruMpuAddrRange[uiMPU_num].EndAddr) )
-	    {
-	        printf("The configuration address is out of MPU %d protection range\n", 
-	        	uiMPU_num);
-	        continue;
-	    }
-
-        KeyStone_MPU_range_setup(&mpuRegs->PROG_REGION[i], 
-            MPU_cfg[i].StartAddr, MPU_cfg[i].EndAddr, 
-            MPU_cfg[i].AccessPermisionMask); 
-
-    }
-
-    //clear unused ranges
-	for( ;i<mpuNumProgmableRange; i++)
-	{
-		mpuRegs->PROG_REGION[i].PROG_MPPA = 0;
-	}
-
-	//clear status
-	mpuRegs->FAULT_CLEAR = 1;
-	mpuRegs->INT_ENABLED_STATUS_CLEAR = 
-		CSL_MPU_INT_ENABLED_STATUS_CLEAR_ENABLED_ADDR_ERR_MASK
-		|CSL_MPU_INT_ENABLED_STATUS_CLEAR_ENABLED_PROT_ERR_MASK;
-
-	/* enable the interrupt */
-	mpuRegs->INT_ENABLE = CSL_MPU_INT_ENABLE_ADDR_ERR_EN_MASK 
-		| CSL_MPU_INT_ENABLE_PROT_ERR_EN_MASK;                
-
-    return;
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MPU_MPPA_modify
- Description  : search the range which match a address and then modify
-                the access permission of that range.
- Input        : Uint32 uiMPU_num: number of the MPU to be modifed  
-                Uint32 uiAddress: address which need modify permision              
-                Uint32 AccessPermisionMask: permission mask for that range         
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/12/13
-    Author       : Brighton Feng
-    Modification : Created function
-*****************************************************************************/
-void KeyStone_MPU_MPPA_modify(Uint32 uiMPU_num, 
-	Uint32 uiAddress, Uint32 AccessPermisionMask)
-{
-    int i;
-    unsigned int mpuNumProgmableRange;
-    CSL_MpuRegs * mpuRegs;
-
-	/*For Turbo Nyquist, add following code to modify initial value,
-	Or user can modify the initail values directly*/
-	if(5==uiMPU_num)
-		TN_MPU5_constant();
-
-	mpuRegs= gpMPU_regs[uiMPU_num];
-
-    mpuNumProgmableRange = (mpuRegs->CONFIG & CSL_MPU_CONFIG_NUM_PROG_MASK)>>CSL_MPU_CONFIG_NUM_PROG_SHIFT;
-    if(mpuNumProgmableRange == 0)
-    {   
-        mpuNumProgmableRange = 16;
-    }
-
-	/*search through all ranges*/
-	for(i=0; i< mpuNumProgmableRange; i++)
-	{
-		/*match with one range*/
-		if((uiAddress >= mpuRegs->PROG_REGION[i].PROG_START_ADDRESS) 
-      		&&(uiAddress <= mpuRegs->PROG_REGION[i].PROG_END_ADDRESS))
-      	{
-      		mpuRegs->PROG_REGION[i].PROG_MPPA = AccessPermisionMask;
-      		return;
-      	}
-	}
-
-	printf("address 0x%08x does not match any range in MPU %d\n", 
-		uiAddress, uiMPU_num);
-    
-    return;
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_MPU_interrupts_enable
- Description  : enable the all MPU interrupts
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_MPU_interrupt_enable(Uint32 uiMPU_num)
-{
-	if((gpMPU_regs[uiMPU_num]->REVISION&0xFFFF0000)!=
-		(CSL_MPU_REVISION_RESETVAL&0xFFFF0000))
-	{	
-		printf("Can't read MPU%d ID register, make sure corresponding power domain is enabled.", uiMPU_num);
-		return;
-	}
-	
-    gpMPU_regs[uiMPU_num]->FAULT_CLEAR = 1;
-    gpMPU_regs[uiMPU_num]->INT_ENABLED_STATUS_CLEAR = 
-    	CSL_MPU_INT_ENABLED_STATUS_CLEAR_ENABLED_ADDR_ERR_MASK
-    	|CSL_MPU_INT_ENABLED_STATUS_CLEAR_ENABLED_PROT_ERR_MASK;
-	gpMPU_regs[uiMPU_num]->INT_ENABLE = CSL_MPU_INT_ENABLE_ADDR_ERR_EN_MASK 
-    	|CSL_MPU_INT_ENABLE_PROT_ERR_EN_MASK;                
-
-}
-void KeyStone_MPU_interrupts_enable()
-{
-	int i;
-	TDSP_Board_Type DSP_Board_Type = KeyStone_Get_dsp_board_type();
-
-	TN_MPU5_constant();
-	
-	for(i=0; i<4; i++)
-	{
-		KeyStone_MPU_interrupt_enable(i);
-	}
-	
-	if((C6670_EVM== DSP_Board_Type)
-		||(TCI6614_EVM== DSP_Board_Type))
-	{
-		for(i=4; i<6; i++)
-		{
-	    	/*MPU5 (for BCP) of TCI6614 is only accessible 
-	    	when BCP is enabled through PSC*/
-	    	if((5==i)&&(TCI6614_EVM== DSP_Board_Type)&&
-		    	((CSL_PSC_getPowerDomainState(5) != PSC_PDSTATE_ON) ||
-		        (CSL_PSC_getModuleState (12) != PSC_MODSTATE_ENABLE)))
-			{
-				puts("Enable power domain for MPU5 before configure it.");
-		        continue;
-		    }
-
-			KeyStone_MPU_interrupt_enable(i);
-		}
-    }
-
-	if(TCI6614_EVM== DSP_Board_Type)
-	{
-		for(i=6; i<8; i++)
-		{
-			KeyStone_MPU_interrupt_enable(i);
-		}
-	}
-	
-    return;
-}
-
-char * Peri_MPU_err_type_str[]=
-{
-    "User execution fault!",
-    "User write fault!",
-    "User read fault!",
-    "Supervisor execution fault!",
-    "Supervisor write fault!",
-    "Supervisor read fault!"
-};
-
-char * Ns_str[]=
-{
-    "secure",
-    "non-secure"
-};
-/*****************************************************************************
- Prototype    : KeyStone_peripherals_MPU_fault_status
- Description  : Print the MPU error information
- Input        : unsigned int uwFltStatus  
-                unsigned int uwFltAddr    
- Output       : None
- Return Value : 
-*****************************************************************************/
-void KeyStone_peripherals_MPU_fault_status(unsigned int uwFltStatus, 
-    unsigned int uwFltAddr)
-{
-    unsigned int MSTID;
-    unsigned int PRIVID;
-    unsigned int NS;
-    unsigned int FaultType;
-    unsigned int BitsCnt;
-    
-    MSTID = (uwFltStatus & CSL_MPU_FAULT_STATUS_MSTID_MASK)>>CSL_MPU_FAULT_STATUS_MSTID_SHIFT;
-    PRIVID = (uwFltStatus & CSL_MPU_FAULT_STATUS_PRIVID_MASK)>>CSL_MPU_FAULT_STATUS_PRIVID_SHIFT;
-    NS = (uwFltStatus & CSL_MPU_FAULT_STATUS_NS_MASK)>>CSL_MPU_FAULT_STATUS_NS_SHIFT;        
-    printf("  The MSTID %d (PRIVID %d) triggered MPU error at 0x%x with %s access\n", 
-    	MSTID, PRIVID, uwFltAddr, Ns_str[NS]);  
-
-    FaultType = (uwFltStatus & CSL_MPU_FAULT_STATUS_FAULT_TYPE_MASK) >> CSL_MPU_FAULT_STATUS_FAULT_TYPE_SHIFT;
-    if(1==(_dotpu4(_bitc4(FaultType), 0x01010101)))
-    {
-    	BitsCnt= 31 - _lmbd(1, FaultType);
-        printf("  %s\n",Peri_MPU_err_type_str[BitsCnt]);
-    }
-    else if(0x3F == FaultType)
-    {
-        puts("  Relaxed cache line fill fault!");            
-    }
-    else if(0x12 == FaultType)
-    {
-        puts("  Relaxed cache write back fault!");                
-    }    
-}
-/*****************************************************************************
- Prototype    : KeyStone_peripherals_MPU_excepiton_handler
- Description  : peripheral MPU processing
- Input        : Uint32 uwMpuNum  
- Output       : None
- Return Value : 
-*****************************************************************************/
-void KeyStone_peripherals_MPU_excepiton_handler(Uint32 uwMpuNum)
-{
-    Uint32 uwStatus;
-    Uint32 uwFltAddr;
-    Uint32 uwFltStatus;
-	CSL_MpuRegs *pstruMpuRegs= gpMPU_regs[uwMpuNum];
-	
-    uwStatus = pstruMpuRegs->INT_ENABLED_STATUS_CLEAR;
-    if(uwStatus & 0x2)
-    {   
-        printf("  MPU %d address violation error\n", uwMpuNum);
-        pstruMpuRegs->INT_ENABLED_STATUS_CLEAR = 2;
-    }        
-
-    if(uwStatus & 0x1)
-    {   
-        printf("  MPU %d protection violation error\n", uwMpuNum);
-        pstruMpuRegs->INT_ENABLED_STATUS_CLEAR = 1;
-    }
-      
-    uwFltAddr = pstruMpuRegs->FAULT_ADDRESS;
-    uwFltStatus = pstruMpuRegs->FAULT_STATUS;
-	exception_record.status.ext_sts.info.memory.fault_address= uwFltAddr;
-	exception_record.status.ext_sts.info.memory.fault_status.MPU_FAULT_STATUS= uwFltStatus;
-    
-    KeyStone_peripherals_MPU_fault_status(uwFltStatus,uwFltAddr);        
-    pstruMpuRegs->FAULT_CLEAR = 1;
-
-    pstruMpuRegs->EOI = 0;     
-}
-
-
-/*======================memory EDC=====================================*/
-/*****************************************************************************
- Prototype    : KeyStone_SL2_EDC_enable
- Description  : Enable MSMC EDC
- Input        : scrubCnt, number of MSMC clock cycles between scrubbing
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_SL2_EDC_enable(Uint32 scrubCnt)
-{
-	if(gpMSMC_regs->CFGLCKSTAT&CSL_MSMC_CFGLCKSTAT_WSTAT_MASK)
-		CSL_MSMC_unlockNonMPAX();
-
-	/*Software must wait for the PRR (Parity RAM Ready) bit before making 
-	the first read access to MSMC RAM after reset.*/
-	while(0==(gpMSMC_regs->SMEDCC&CSL_MSMC_SMEDCC_PRR_MASK));
-
-	/* set scrubbing period value */
-	if(scrubCnt>255)
-		scrubCnt= 255;
-	CSL_MSMC_setCounterBankRefreshRead(scrubCnt); //the scrubbing engine works every scrubCnt*1024 cycle*/
-
-	/* clear EDC errors and enable EDC event*/
-	gpMSMC_regs->SMIRC = 0xf;
-	gpMSMC_regs->SMIESTAT |= (CSL_MSMC_SMIESTAT_NCSIE_MASK
-			           | CSL_MSMC_SMIESTAT_CSIE_MASK
-			           | CSL_MSMC_SMIESTAT_NCEIE_MASK
-			           | CSL_MSMC_SMIESTAT_CEIE_MASK);
-
-	//enable SL2 EDC
-	CSL_MSMC_setECM(1);
-
-	CSL_MSMC_lockNonMPAX();
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_SL2_EDC_interrupt_en
- Description  : Enable MSMC EDC error interrupt
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/15
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_SL2_EDC_interrupt_en()
-{
-	if(gpMSMC_regs->CFGLCKSTAT&CSL_MSMC_CFGLCKSTAT_WSTAT_MASK)
-		CSL_MSMC_unlockNonMPAX();
-
-	/* clear EDC errors*/
-	gpMSMC_regs->SMIRC = 0xf;
-
-	/* Enable EDC error interrupt */
-	gpMSMC_regs->SMIESTAT |= (CSL_MSMC_SMIESTAT_NCSIE_MASK
-			           | CSL_MSMC_SMIESTAT_CSIE_MASK
-			           | CSL_MSMC_SMIESTAT_NCEIE_MASK
-			           | CSL_MSMC_SMIESTAT_CEIE_MASK);
-
-	CSL_MSMC_lockNonMPAX();
-}
-
-/*****************************************************************************
- Prototype    : LL2_EDC_setup
- Description  : Eenable LL2 EDC and scrub whole LL2
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/10
-    Author       : Jane
-    Modification : Created function
-
-  2.Date         : 2012/10/20
-    Author       : Brighton Feng
-
-*****************************************************************************/
-void LL2_EDC_setup()
-{
-	int i;
-	unsigned int uiByteCnt= 512*1024;
-	TDSP_Board_Type DSP_Board_Type;
-	
-	/* 1. Disable the EDC */
-	CSL_CGEM_disableL2EDC();
-
-	/* 2. Clear any EDC errors */
-	CSL_CGEM_clearL2EDCErrorStatus(1, 1, 1, 1);
-
-	/* 3. Memory Scrubbing with IDMA, generate the parity bits*/
-	DSP_Board_Type = KeyStone_Get_dsp_board_type();
-	if((DUAL_NYQUIST_EVM == DSP_Board_Type)
-		||(C6670_EVM == DSP_Board_Type)
-		||(TCI6614_EVM == DSP_Board_Type))
-	{
-		uiByteCnt= 1024*1024;
-	}
-
-	/*Each IDMA can transfer up to 65532 bytes,
-	here we transfer 32KB each time*/
-	for(i=0; i< (uiByteCnt>>15); i++)
-	{
-		IDMA_copy((0x00800000 + i*(1<<15)), (0x00800000 + i*(1<<15)), 
-			(1<<15), DMA_WAIT);
-	}
-
-	/* 4. Enable the EDC*/
-	CSL_CGEM_enableL2EDC();
-	gpCGEM_regs->L2EDCEN= (1<<CSL_CGEM_L2EDCEN_DL2CEN_SHIFT)
-		|(1<<CSL_CGEM_L2EDCEN_DL2SEN_SHIFT)
-		|(1<<CSL_CGEM_L2EDCEN_PL2CEN_SHIFT)
-		|(1<<CSL_CGEM_L2EDCEN_PL2SEN_SHIFT)
-		|(1<<CSL_CGEM_L2EDCEN_SDMAEN_SHIFT);
-	
-}
-
-Uint32 uiLL2_scrub_addr=0x800000;
-/*****************************************************************************
- Prototype    : LL2_EDC_scrub
- Description  : scrub a block in LL2 for EDC. 
-
-    Number of bytes must be multiple of 128 bits and less than 64KB.
-This function should be called periodically, for example, 
-if every 1 minute, call it with:	LL2_EDC_scrub(1024);
-For 1MB LL2, the whole space will be scrubbed in 1024 minutes(17 hours)
-
- Input        : Uint32 uiByteCnt  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/20
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void LL2_EDC_scrub(Uint32 uiByteCnt)
-{
-	Uint32	uiLL2EndAddress= 0x00880000;
-	TDSP_Board_Type DSP_Board_Type;
-
-	uiByteCnt &= 0xFFF0;	//size must be multiple of 128 bits and less than 64KB
-
-#if 1
-	int i;
-	volatile Uint32 * uipAddress= (volatile Uint32 *)uiLL2_scrub_addr;
-	for(i=0; i< uiByteCnt/64; i++)
-	{
-		/*read one word to fetch a cache line, write to make it dirty*/
-		*uipAddress= *uipAddress;
-		uipAddress+= 16; 	//skip to the next cach line
-	}
-	CACHE_wbInvL1d((void *)uiLL2_scrub_addr, uiByteCnt, CACHE_NOWAIT);
-#else 	//use IDMA ONLY for read ONLY space
-	/*if IDMA scrub memory which is modifying by other masters at the same time, 
-	there may be race condtion that the new value is overwritter by the IDMA 
-	with old value.*/
-	IDMA_copy(uiLL2_scrub_addr, uiLL2_scrub_addr, uiByteCnt, DMA_NO_WAIT);
-#endif
-
-	uiLL2_scrub_addr+= uiByteCnt;
-
-	DSP_Board_Type = KeyStone_Get_dsp_board_type();
-	if((DUAL_NYQUIST_EVM == DSP_Board_Type)
-		||(C6670_EVM == DSP_Board_Type)
-		||(TCI6614_EVM == DSP_Board_Type))
-	{
-		uiLL2EndAddress= 0x00900000;
-	}
-
-	//wrap back
-	if(uiLL2_scrub_addr >= uiLL2EndAddress)
-		uiLL2_scrub_addr=0x800000;
-		
-}
-
-/*****************************************************************************
- Prototype    : L1P_EDC_setup
- Description  : enable L1P ED and scrub whole L1P
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/10
-    Author       : Jane
-    Modification : Created function
-
-  2.Date         : 2012/10/30
-    Author       : Brighton Feng
-*****************************************************************************/
-void L1P_EDC_setup()
-{
-	Uint32 preL1PMPPA[16];
-
-	/* 1. Disable the EDC */
-	CSL_CGEM_disablePMCErrorDetection();
-
-	/* 2. Clear any EDC errors */
-	CSL_CGEM_clearPMCErrorDetectionStatus(1, 1);
-
-	/* 3. Memory Scrubbing with IDMA, generate the parity bits*/
-	memcpy(preL1PMPPA, (void *)gpCGEM_regs->L1PMPPA, 64);//save protection attributes
-	L1P_memory_protection_cfg(0xFFFF); //enable IDMA access to L1P
-	IDMA_copy(0x00E00000, 0x00E00000, 32*1024, DMA_WAIT);
-	L1_MPPA_setup(gpCGEM_regs->L1PMPPA, preL1PMPPA);//restore protection for L1
-
-	/* 4. Enable the EDC*/
-	CSL_CGEM_enablePMCErrorDetection();
-}
-
-char * LL2_EDC_victim_err_str="LL2 victims";
-char * LL2_EDC_DMA_err_str=	"DMA access";
-char * LL2_EDC_L1D_err_str=	"L1D access";
-char * LL2_EDC_L1P_err_str=	"L1P access";
-
-/*****************************************************************************
- Prototype    : LL2_EDC_handler
- Description  : LL2 EDC exception/interrupt handler
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void LL2_EDC_handler(Bool bCorrected)
-{
-	/* EDC error during the L1D access */
-    Uint8  derr;
-    /* EDC error during the L1P access */
-    Uint8  perr;
-    /* EDC error during the DMA access*/
-    Uint8  dmaerr;
-    /* EDC error during the L2 victim occurred */
-    Uint8  verr;
-    /* single bit or dual bit EDC error */
-    Uint8  nerr;
-
-    char *errStr;
-    Uint32 errAddr;
-
-	/* Get the all LL2 error status */
-	CSL_CGEM_getL2EDCErrorStatus(&derr, &perr, &dmaerr, &verr, &nerr);
-
-	if(derr|perr|dmaerr|verr)
-	{
-		errAddr= gpCGEM_regs->L2EDADDR&CSL_CGEM_L2EDADDR_ADDR_MASK;
-		
-		exception_record.status.ext_sts.info.memory.fault_address= errAddr;
-		exception_record.status.ext_sts.info.memory.fault_status.L2EDSTAT= 
-			gpCGEM_regs->L2EDSTAT;
-
-		if(bCorrected)
-		{
-			printf("  LL2 EDC (correctable) at bit %d of ",(gpCGEM_regs->L2EDSTAT&
-				CSL_CGEM_L2EDSTAT_BITPOS_MASK)>>CSL_CGEM_L2EDSTAT_BITPOS_SHIFT);
-
-			//scrub 64 bytes including the error address to correct the error
-			if(perr) //by L1P access
-				IDMA_copy(errAddr&0xFFFFFFC0, errAddr&0xFFFFFFC0, 64, DMA_WAIT);
-			else
-			{
-				volatile Uint32 * uipAddress= (volatile Uint32 *)(errAddr&0xFFFFFFC0);
-				/*read one word into a cache line, and write to make it dirty, 
-				which will be automatically written back sooner or later*/
-				*uipAddress= *uipAddress;
-			}
-		}
-		else
-		{      
-			printf("  LL2 EDC error (non-correctable) at ");
-		}
-		errStr = (char *)(perr * (Uint32)LL2_EDC_L1P_err_str
-			+ derr * (Uint32)LL2_EDC_L1D_err_str
-			+ verr * (Uint32)LL2_EDC_victim_err_str
-			+ dmaerr * (Uint32)LL2_EDC_DMA_err_str);
-
-		printf("address 0x%x caused by %s.\n",
-			errAddr,
-			errStr);        
-
-		if(0==(gpCGEM_regs->L2EDADDR&CSL_CGEM_L2EDADDR_RAM_MASK))
-		{      
-			printf("  Error detected in Way %d of L2 cache\n",
-				(gpCGEM_regs->L2EDADDR&CSL_CGEM_L2EDADDR_WAY_MASK)>>CSL_CGEM_L2EDADDR_WAY_SHIFT);
-		}    
-			
-		printf("  total non-correctable error number= %d, total correctable error number= %d.\n",
-			gpCGEM_regs->L2EDCNEC, gpCGEM_regs->L2EDCPEC);
-
-		CSL_CGEM_clearL2EDCErrorStatus(derr, perr, dmaerr, verr);
-	}
-	else
-	{   
-		puts("  Enter LL2 EDC handler, but no error flag is set!");
-	}
-}
-/*****************************************************************************
- Prototype    : L1P_ED_handler
- Description  : L1P EDC processing
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void L1P_ED_handler()
-{
-	Uint32 errAddr;
-	Uint8 errRAM;
-
-	/* EDC error during DMA access */
-    Uint8  dmaerr;
-    /* EDC error during program fetch access */
-    Uint8  perr;
-
-	/* Read PMC EDC status*/
-	CSL_CGEM_getPMCErrorDetectionStatus(&dmaerr, &perr);
-
-	if(perr|dmaerr)
-	{
-		CSL_CGEM_getPMCErrorInfo(&errAddr, &errRAM);
-
-		exception_record.status.ext_sts.info.memory.fault_address= errAddr*32;
-		exception_record.status.ext_sts.info.memory.fault_status.L1PEDSTAT= 
-			gpCGEM_regs->L1PEDSTAT;
-			
-		if(errRAM)
-			printf("  L1P RAM ");
-		else
-			printf("  L1P Cache ");
-
-		printf("parity check error caused by ");
-
-		if(perr == 1)
-		{
-			printf("program fetch ");
-
-			/*flush wrong code in L1P. Code will be refetched from L2*/
-			CACHE_invL1p((void *)NRP, 64, CACHE_WAIT);
-		}
-		else if(dmaerr == 1)
-		{
-			printf("DMA ");
-		}
-		printf("at address 0x%x\n", errAddr*32);
-
-		CSL_CGEM_clearPMCErrorDetectionStatus(dmaerr,perr);
-	}
-}
-
-
-/*****************************************************************************
- Prototype    : KeyStone_SL2_EDC_handler
- Description  : SL2 EDC Processing
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void KeyStone_SL2_EDC_handler()
-{
-	/* EDC correctable error during scrubbing cycle */
-    Uint8  cses;
-	/* EDC non-correctable error during scrubbing cycle */
-    Uint8  ncses;
-    /* EDC correctable error during SRAM access*/
-    Uint8  cees;
-    /* EDC non-correctable error during SRAM access*/
-    Uint8  ncees;
-    /* protection fault status*/
-    Uint16  pfeStat;
-
-    /*  error address  */
-    Uint32 errAddr, bitPos, PrivID;
-
-	if(gpMSMC_regs->CFGLCKSTAT&CSL_MSMC_CFGLCKSTAT_WSTAT_MASK)
-		CSL_MSMC_unlockNonMPAX();
-
-    CSL_MSMC_getPendingInterrupts(&pfeStat, &cees, &ncees, &cses, &ncses);
-
-	exception_record.status.ext_sts.info.memory.fault_status.SMESTAT= 
-		gpMSMC_regs->SMESTAT;
-		
-	if((cses == 1)||(ncses == 1))
-	{
-		if(cses == 1)
-		{
-			/*scrubbing engine report address offset from 0*/
-			errAddr = (gpMSMC_regs->SMCEA&0xFFFFFF)+0xc000000;
-			exception_record.status.ext_sts.info.memory.fault_address= errAddr;
-			
-			bitPos = (gpMSMC_regs->SMCEA&CSL_MSMC_SMCEA_ESYN_MASK)
-				>>CSL_MSMC_SMCEA_ESYN_SHIFT;
-			printf("SL2 Correctable error occurred at bit %d of address 0x%x by scrubbing\n", 
-				bitPos, errAddr);
-		}
-		 if(ncses == 1)
-		{
-			/*scrubbing engine report address offset from 0*/
-			errAddr = gpMSMC_regs->SMNCEA+0xc000000;
-			exception_record.status.ext_sts.info.memory.fault_address= errAddr;
-			
-			printf("SL2 Non-correctable error occurred at address 0x%x by scrubbing\n", errAddr);
-		}
-		printf("%d correctable errors, %d non-correctable errors occurred during scrubbing.\n",
-			(gpMSMC_regs->SMSECC&CSL_MSMC_SMSECC_SCEC_MASK)
-				>>CSL_MSMC_SMSECC_SCEC_SHIFT,
-			(gpMSMC_regs->SMSECC&CSL_MSMC_SMSECC_SNCEC_MASK)
-				>>CSL_MSMC_SMSECC_SNCEC_SHIFT);
-	}
-	if(cees == 1)
-	{
-		volatile Uint32 scrubValue;
-		
-		errAddr =  gpMSMC_regs->SMCERRAR;
-		exception_record.status.ext_sts.info.memory.fault_address= errAddr;
-
-		//scrub the address to correct the error
-		scrubValue= *(volatile Uint32 *)errAddr; //touch to cach
-		*(volatile Uint32 *)errAddr= scrubValue; //make cache dirty
-		CACHE_wbInvL2((void *)errAddr, 32, CACHE_WAIT);
-		
-		bitPos = (gpMSMC_regs->SMCERRXR&CSL_MSMC_SMCERRXR_ESYN_MASK)
-			>>CSL_MSMC_SMCERRXR_ESYN_SHIFT;
-		PrivID = (gpMSMC_regs->SMCERRXR&CSL_MSMC_SMCERRXR_SEPID_MASK)
-			>>CSL_MSMC_SMCERRXR_SEPID_SHIFT;
-		printf("SL2 Correctable error occurred at bit %d of address 0x%x by PrivID %d ", 
-			bitPos, errAddr, PrivID);
-		if(gpMSMC_regs->SMCERRXR&CSL_MSMC_SMCERRXR_SER_MASK)
-			printf("(not from C66x CorePacs)\n");
-		else
-			printf("(from C66x CorePacs)\n");
-	}
-	if(ncees ==1)
-	{
-		errAddr =  gpMSMC_regs->SMNCERRAR;
-		exception_record.status.ext_sts.info.memory.fault_address= errAddr;
-		
-		PrivID = (gpMSMC_regs->SMNCERRXR&CSL_MSMC_SMNCERRXR_SEPID_MASK)
-			>>CSL_MSMC_SMNCERRXR_SEPID_SHIFT;
-		printf("SL2 Non-correctable error occurred at address 0x%x by PrivID %d ", 
-			errAddr, PrivID);
-		if(gpMSMC_regs->SMNCERRXR&CSL_MSMC_SMNCERRXR_SER_MASK)
-			printf("(not from C66x CorePacs)\n");
-		else
-			printf("(from C66x CorePacs)\n");
-	}
-
-	/* clear EDC error status  */
-	CSL_MSMC_clearRawInterruptStatus(0, cees,ncees, cses, ncses);
-
-	CSL_MSMC_lockNonMPAX();
-}
-
-/*===============================Exception=============================*/
-//data structure to save exception info
-Exception_Record exception_record;
-
-/*some exception events routed from CIC to INTC and then to exception moduel,
-all these events are routed to one input of INTC*/
-Uint32 guwIntcCICExcEvtIdx= 95; /*INTC event number mapping to CIC exception events*/
-Uint32 gCIC_EXC_out_num = 15; 	//CIC output event number
-Uint32 gCIC_EXC_EN_MASK[8]= {0,0,0,0,0,0,0,0};
-/*****************************************************************************
- Prototype    : KeyStone_CIC_exception_events_mapping
- Description  : CIC exception event mapping to the NMI external exception
- Input        : void  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/5
-    Author       : Brighton Feng
-    Modification : Created function
-
-  2.Date         : 2012/10/20
-    Author       : Zhan
-    Modification : Add event for TCI6614
-
-  3.Date         : 2012/10/28
-    Author       : Brighton Feng
-*****************************************************************************/
-void KeyStone_CIC_exception_events_mapping(void)
-{
-	TDSP_Board_Type DSP_Board_Type= KeyStone_Get_dsp_board_type();
-
-#if 1
-	if(C6670_EVM==DSP_Board_Type
-		||DUAL_NYQUIST_EVM==DSP_Board_Type
-		||TCI6614_EVM==DSP_Board_Type)
-	{	
-		gCIC_EXC_out_num= 15+16*DNUM;
-	}
-	else if(C6678_EVM==DSP_Board_Type)
-	{	
-		if(DNUM<4)
-			gCIC_EXC_out_num= 7+8*DNUM;
-		else
-		{
-			gCIC_EXC_out_num= 7+8*(DNUM-4);
-			gpCIC_regs= gpCIC1_regs;
-		}
-	}
-	else
-	{
-		puts("Unknown DSP board type!");
-		return;
-	}	
-#endif
-
-	/*-----------------------CP_INTC configuration---------------------*/
-	/* Disable Global host interrupts. */
-	gpCIC_regs->GLOBAL_ENABLE_HINT_REG= 0;
-
-	/* route following system events to CIC out (event 22 of INTC), and then to exception
-	TCI6614, C6670, C6678:
-	CIC: 0 EDMA3CC1 EDMACC_ERRINT EDMA3CC1 error interrupt
-	CIC: 2 EDMA3CC1 EDMATC_ERRINT0 EDMA3CC1 EDMA3TC0 error interrupt
-	CIC: 3 EDMA3CC1 EDMATC_ERRINT1 EDMA3CC1 EDMA3TC1 error interrupt
-	CIC: 4 EDMA3CC1 EDMATC_ERRINT2 EDMA3CC1 EDMA3TC2 error interrupt
-	CIC: 5 EDMA3CC1 EDMATC_ERRINT3 EDMA3CC1 EDMA3TC3 error interrupt
-	CIC: 16 EDMA3CC2 EDMACC_ERRINT EDMA3CC2 error interrupt
-	CIC: 18 EDMA3CC2 EDMATC_ERRINT0 EDMA3CC2 EDMA3TC0 error interrupt
-	CIC: 19 EDMA3CC2 EDMATC_ERRINT1 EDMA3CC2 EDMA3TC1 error interrupt
-	CIC: 20 EDMA3CC2 EDMATC_ERRINT2 EDMA3CC2 EDMA3TC2 error interrupt
-	CIC: 21 EDMA3CC2 EDMATC_ERRINT3 EDMA3CC2 EDMA3TC3 error interrupt
-	CIC: 32 EDMA3CC0 EDMACC_ERRINT EDMA3CC0 error interrupt
-	CIC: 34 EDMA3CC0 EDMATC_ERRINT0 EDMA3CC0 EDMA3TC0 error interrupt
-	CIC: 35 EDMA3CC0 EDMATC_ERRINT1 EDMA3CC0 EDMA3TC1 error interrupt
-	CIC: 99 MSMC_dedc_nc_error Non-correctable soft error detected on SRAM read
-	CIC: 100 MSMC_scrub_nc_error Non-correctable soft error detected during scrub cycle
-	CIC: 102 MSMC_mpf_error8 Memory protection fault indicators for each system master PrivID
-	CIC: 103 MSMC_mpf_error9 Memory protection fault indicators for each system master PrivID
-	CIC: 104 MSMC_mpf_error10 Memory protection fault indicators for each system master PrivID
-	CIC: 105 MSMC_mpf_error11 Memory protection fault indicators for each system master PrivID
-	CIC: 106 MSMC_mpf_error12 Memory protection fault indicators for each system master PrivID
-	CIC: 107 MSMC_mpf_error13 Memory protection fault indicators for each system master PrivID
-	CIC: 108 MSMC_mpf_error14 Memory protection fault indicators for each system master PrivID
-	CIC: 109 MSMC_mpf_error15 Memory protection fault indicators for each system master PrivID
-	CIC: 110 DDR3_ERR DDR3 ECC Error Interrupt
-	TCI6614, C6670:
-	CIC: 170 MSMC_mpf_error4 Memory protection fault indicators for each system master PrivID
-	CIC: 171 MSMC_mpf_error5 Memory protection fault indicators for each system master PrivID
-	CIC: 172 MSMC_mpf_error6 Memory protection fault indicators for each system master PrivID
-	CIC: 173 MSMC_mpf_error7 Memory protection fault indicators for each system master PrivID
-	*/
-	KeyStone_CIC_event_map(gpCIC_regs, 0 , gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 2 , gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 3 , gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 4 , gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 5 , gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 16, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 18, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 19, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 20, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 21, gCIC_EXC_out_num);
-	gCIC_EXC_EN_MASK[0] |=  
-                 (1<<0 )
-                |(1<<2 )
-                |(1<<3 )
-                |(1<<4 )
-                |(1<<5 )
-                |(1<<16)
-                |(1<<18)
-                |(1<<19)
-                |(1<<20)
-                |(1<<21);
-		
-	KeyStone_CIC_event_map(gpCIC_regs, 32, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 34, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 35, gCIC_EXC_out_num);
-	gCIC_EXC_EN_MASK[1] |=  
-                 (1<<(32-32))
-                |(1<<(34-32))
-                |(1<<(35-32));
-
-	KeyStone_CIC_event_map(gpCIC_regs, 99, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 100, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 102, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 103, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 104, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 105, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 106, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 107, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 108, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 109, gCIC_EXC_out_num);
-	KeyStone_CIC_event_map(gpCIC_regs, 110, gCIC_EXC_out_num);
-	gCIC_EXC_EN_MASK[3] |=  
-                 (1<<(99 -32*3))
-                |(1<<(100-32*3))
-                |(1<<(102-32*3))
-                |(1<<(103-32*3))
-                |(1<<(104-32*3))
-                |(1<<(105-32*3))
-                |(1<<(106-32*3))
-                |(1<<(107-32*3))
-                |(1<<(108-32*3))
-                |(1<<(109-32*3))
-                |(1<<(110-32*3));
-
-	if(C6670_EVM==DSP_Board_Type
-		||DUAL_NYQUIST_EVM==DSP_Board_Type
-		||TCI6614_EVM==DSP_Board_Type)
-	{	
-		KeyStone_CIC_event_map(gpCIC_regs, 170, gCIC_EXC_out_num);
-		KeyStone_CIC_event_map(gpCIC_regs, 171, gCIC_EXC_out_num);
-		KeyStone_CIC_event_map(gpCIC_regs, 172, gCIC_EXC_out_num);
-		KeyStone_CIC_event_map(gpCIC_regs, 173, gCIC_EXC_out_num);
-		gCIC_EXC_EN_MASK[5] |=  
-	                 (1<<(170-32*5))
-	                |(1<<(171-32*5))
-	                |(1<<(172-32*5))
-	                |(1<<(173-32*5)); 
-	}
-    
-    /* ----------- Mapping MPU interrupt for different chips start -----------------------*/
-    if(C6670_EVM==DSP_Board_Type
-		||DUAL_NYQUIST_EVM==DSP_Board_Type
-		||C6678_EVM==DSP_Board_Type)
-    {
-    /*  route the following system events to CIC out
-        CIC: 90 MPU0 addressing violation interrupt and protection violation interrupt 
-    	CIC: 92 MPU1 addressing violation interrupt and protection violation interrupt
-    	CIC: 94 MPU2 addressing violation interrupt and protection violation interrupt
-    	CIC: 96 MPU3 addressing violation interrupt and protection violation interrupt     	
-    */
-        KeyStone_CIC_event_map(gpCIC_regs, 90, gCIC_EXC_out_num);
-		KeyStone_CIC_event_map(gpCIC_regs, 92, gCIC_EXC_out_num);
-		KeyStone_CIC_event_map(gpCIC_regs, 94, gCIC_EXC_out_num);
-		KeyStone_CIC_event_map(gpCIC_regs, 96, gCIC_EXC_out_num);
-		gCIC_EXC_EN_MASK[2] |=  
-	                  (1<<(90 -32*2))
-	                 |(1<<(92 -32*2))
-	                 |(1<<(94 -32*2));
-		gCIC_EXC_EN_MASK[3] |=  
-	                 (1<<(96 -32*3));
-
-        /* 6618_6670 only */
-        if(C6670_EVM==DSP_Board_Type
-		||DUAL_NYQUIST_EVM==DSP_Board_Type)
-        {
-        /*
-            CIC: 174 MPU4 addressing violation interrupt and protection violation interrupt 
-            CIC: 180 MPU5 addressing violation interrupt and protection violation interrupt
-        */        
-            KeyStone_CIC_event_map(gpCIC_regs, 174, gCIC_EXC_out_num);
-		    KeyStone_CIC_event_map(gpCIC_regs, 180, gCIC_EXC_out_num);
-			gCIC_EXC_EN_MASK[5] |=  
-		                 (1<<(174-32*5))
-		                |(1<<(180-32*5)); 
-        }
-    }
-
-    if(TCI6614_EVM==DSP_Board_Type)
-    {
-    /*  route the following system events to CIC out
-        CIC: 23 MPU0~7 addressing violation interrupt combine output 
-    	CIC: 37 MPU0~7 protection violation interrupt combine output    	
-    */
-        KeyStone_CIC_event_map(gpCIC_regs, 23, gCIC_EXC_out_num);
-	    KeyStone_CIC_event_map(gpCIC_regs, 37, gCIC_EXC_out_num);
-		gCIC_EXC_EN_MASK[0] |=  
-	                  (1<<23);
-		gCIC_EXC_EN_MASK[1] |=  
-	                  (1<<(37 -32));
-        
-    }
-    /* ----------- Mapping MPU interrupt for different chips end -----------------------*/
-
-	/* Enable Global host interrupts. */
-	gpCIC_regs->GLOBAL_ENABLE_HINT_REG= 1;
-
-}
-/*****************************************************************************
- Prototype    : KeyStone_Exception_cfg
- Description  : Config the system  err and external exception to generate the NMI.
-                Call this function as last step after all 
-                configuration/initialization complete
- Input        : Bool bGlobalExceptionMaster. If TRUE, the global exception events 
-                from CIC will be routed to exception model of this CPU core.
- Output       : None
- Return Value : 
-*****************************************************************************/
-void KeyStone_Exception_cfg(Bool bGlobalExceptionMaster)
-{
-
-	puts("Enable Exception handling...");
-
-	TSCL = 0; 	/* Enable the TSC */
-
-	memset(&exception_record, 0, sizeof(exception_record));
-#if 0
-	 /*Clear all CPU events*/
-	gpCGEM_regs->EVTCLR[0]= 	0xFFFFFFFF;
-	gpCGEM_regs->EVTCLR[1]= 	0xFFFFFFFF;
-	gpCGEM_regs->EVTCLR[2]= 	0xFFFFFFFF;
-	gpCGEM_regs->EVTCLR[3]= 	0xFFFFFFFF;
-#endif
-	/*clear memory fault*/
-	gpCGEM_regs->L1PMPFCR = 1;
-	gpCGEM_regs->L1DMPFCR = 1;
-	gpCGEM_regs->L2MPFCR = 1;
-	gpXMC_regs->XMPFCR = 1;
-
-	/*clear configuration bus error*/
-	gpCGEM_regs->ICFGMPFCR= 1;
-	gpCGEM_regs->ECFGERRCLR= 1;
-
-	/* clear the MDMAERR */
-	gpCGEM_regs->MDMAERRCLR = 1;
-
-	/*clear interrupt drop staus*/
-	gpCGEM_regs->INTXCLR = 1;
-
-	gpCGEM_regs->INTDMASK= ~IER; /*only monitor drop of enabled interrupts*/
-
-	/*enable events:
-	10 MSMC_mpf_error_n MSMC Memory protection fault  caused by local CorePac
-	96 INTERR Dropped CPU interrupt event
-	97 EMC_IDMAERR Invalid IDMA parameters
-	110 MDMAERREVT XMC VBUSM error event
-	113 PMC_ED Single bit error detected during DMA accesses L1P
-	117 UMC_ED2 Uncorrected bit error detected LL2
-	119 SYS_CMPA CPU Memory Protection Fault for local configuration of INTC and power control
-	120 PMC_CMPA CPU memory protection fault for L1P
-	121 PMC_DMPA DMA memory protection fault for L1P
-	122 DMC_CMPA CPU memory protection fault for L1D (and other memory read finally goes through the L1D controller)
-	123 DMC_DMPA DMA memory protection fault for L1D
-	124 UMC_CMPA CPU memory protection fault for LL2
-	125 UMC_DMPA DMA memory protection fault for LL2
-	126 EMC_CMPA CPU memory protection fault for other local configuration space between 0x01000000 - 0x01BFFFFF 
-	127 EMC_BUSERR Bus Error Interrupt for global configuration space between 0x01C00000 - 0x07FFFFFF 
-	*/
-	gpCGEM_regs->EXPMASK[0]= ~(1<<CSL_GEM_MSMC_MPF_ERRORN);
-	gpCGEM_regs->EXPMASK[1]= 0xFFFFFFFF;
-	gpCGEM_regs->EXPMASK[2]= 0xFFFFFFFF;
-	gpCGEM_regs->EXPMASK[3]= ~((1<<(CSL_GEM_INTERR - 96))|
-		(1<<(CSL_GEM_EMC_IDMAERR-96))|
-		(1<<(CSL_GEM_MDMAERREVT-96))|
-		(1<<(CSL_GEM_PMC_ED-96))|
-		(1<<(CSL_GEM_UMC_ED2-96))|
-		(1<<(CSL_GEM_SYS_CMPA-96))|
-		(1<<(CSL_GEM_PMC_CMPA-96))|
-		(1<<(CSL_GEM_PMC_DMPA-96))|
-		(1<<(CSL_GEM_DMC_CMPA-96))|
-		(1<<(CSL_GEM_DMC_DMPA-96))|
-		(1<<(CSL_GEM_UMC_CMPA-96))|
-		(1<<(CSL_GEM_UMC_DMPA-96))|
-		(1<<(CSL_GEM_EMC_CMPA-96))|
-		(1<<(CSL_GEM_EMC_BUSERR-96)));
-
-
-	if(bGlobalExceptionMaster)
-	{
-		/*enable exception events routed from CIC,
-		please note, this should be only configured for one CPU*/
-		KeyStone_CIC_exception_events_mapping();
-		gpCGEM_regs->EXPMASK[guwIntcCICExcEvtIdx>>5] &= (~(1<<(guwIntcCICExcEvtIdx&0x1F)));        
-	}
-
-	/*clear exception flag*/
-	ECR = EFR;
-	IERR = 0; 
-    
-	/*Eanble external exception, global exception enable*/
-	TSR = TSR|
-		(1<<CSL_CHIP_TSR_XEN_SHIFT)|
-		(1<<CSL_CHIP_TSR_GEE_SHIFT)|
-		(1<<CSL_CHIP_TSR_GIE_SHIFT);
-
-	/*enable NMI exception*/
-	IER = IER|(1<<CSL_CHIP_IER_NMI_SHIFT);
-	
-}
-
-char * bus_err_stat_str[]=
-{
-	"unrecognized RID/WID (should cause error to be latched)",
-	"Addressing error",
-	"Privilege error",
-	"Timeout error",
-	"Data error",
-	"Reserved error",
-	"Reserved error",
-	"Exclusive - operation failure"
-};
-/*****************************************************************************
- Prototype    : Bus_error_handler
- Description  : System bus error processing
- Input        : unsigned int ERR_REG  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2012/10/25
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void Bus_error_handler(unsigned int ERR_REG)
-{
-	unsigned int err, stat;
-
-	if(0 == ERR_REG)
-		return;
-
-	exception_record.status.ext_sts.info.memory.BUS_ERROR= ERR_REG;
-
-	err= (ERR_REG & CSL_CGEM_MDMAERR_ERR_MASK)>>CSL_CGEM_MDMAERR_ERR_SHIFT;
-	if (1==err) {
-		puts("  MDMA read status error detected");
-	}
-	else if (2==err) {
-		puts("  MDMA write status error detected");
-	}
-	else if (3==err) {
-		puts("  CFG read status error detected");
-	}
-	else if (4==err) {
-		puts("  CFG write status error detected");
-	}
-
-	printf("  XID (Transaction ID)= %d\n", 
-		(ERR_REG & CSL_CGEM_MDMAERR_XID_MASK)>>CSL_CGEM_MDMAERR_XID_SHIFT);	
-
-	stat= (ERR_REG & CSL_CGEM_MDMAERR_STAT_MASK)>>CSL_CGEM_MDMAERR_STAT_SHIFT;
-	printf("  %s\n", bus_err_stat_str[stat]);
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_CIC_EXC_handler
- Description  : This function handle the exception events from CIC
- Input        : void
- Output       : None
- Return Value : void
- 
-  History        :
-  1.Date         : 2012/10/18
-    Author       : Zhan
-    Modification : Created function
-
-  2.Date         : 2012/10/28
-    Author       : Brighton Feng
-    Modification : Add EDMA error processing
-
-*****************************************************************************/
-void KeyStone_CIC_EXC_handler()
-{
-    int i;
-    Uint32 status[4], status5 = 0;
-    
-	TDSP_Board_Type DSP_Board_Type;
-
-	DSP_Board_Type= KeyStone_Get_dsp_board_type();
-
-    /*Step1: Disable CIC host interrupt*/
-    KeyStone_CIC_disable_host_int(gpCIC_regs, gCIC_EXC_out_num);
-
-	status[0]= gpCIC_regs->ENA_STATUS_REG[0]&gCIC_EXC_EN_MASK[0];
-	status[1]= gpCIC_regs->ENA_STATUS_REG[1]&gCIC_EXC_EN_MASK[1];
-	status[2]= gpCIC_regs->ENA_STATUS_REG[2]&gCIC_EXC_EN_MASK[2];
-	status[3]= gpCIC_regs->ENA_STATUS_REG[3]&gCIC_EXC_EN_MASK[3];
-	exception_record.status.ext_sts.CIC_STATUS[0]= status[0];
-	exception_record.status.ext_sts.CIC_STATUS[1]= status[1];
-	exception_record.status.ext_sts.CIC_STATUS[2]= status[2];
-	exception_record.status.ext_sts.CIC_STATUS[3]= status[3];
-
-	/*Step2: clear system events*/
-	gpCIC_regs->ENA_STATUS_REG[0]= status[0];
-	gpCIC_regs->ENA_STATUS_REG[1]= status[1];
-	gpCIC_regs->ENA_STATUS_REG[2]= status[2];
-	gpCIC_regs->ENA_STATUS_REG[3]= status[3];
-
-    /* The different device INTC number is different, if read the non-exist space will 
-        trigger the L1D memory protection error.
-    */
-	if((C6670_EVM == DSP_Board_Type)
-		||(DUAL_NYQUIST_EVM == DSP_Board_Type)
-		||(TCI6614_EVM == DSP_Board_Type))
-	{
-		status5  = gpCIC_regs->ENA_STATUS_REG[5]&gCIC_EXC_EN_MASK[5];
-		exception_record.status.ext_sts.CIC_STATUS[5]= status5;
-
-		/*Step2: clear system events*/
-		gpCIC_regs->ENA_STATUS_REG[5]= status5  ;
-	}
-
-	/*----------------------------EDMA error-----------------------------*/
-	/*
-	CIC: 0 EDMA3CC1 EDMACC_ERRINT EDMA3CC1 error interrupt
-	CIC: 2 EDMA3CC1 EDMATC_ERRINT0 EDMA3CC1 EDMA3TC0 error interrupt
-	CIC: 3 EDMA3CC1 EDMATC_ERRINT1 EDMA3CC1 EDMA3TC1 error interrupt
-	CIC: 4 EDMA3CC1 EDMATC_ERRINT2 EDMA3CC1 EDMA3TC2 error interrupt
-	CIC: 5 EDMA3CC1 EDMATC_ERRINT3 EDMA3CC1 EDMA3TC3 error interrupt*/
-	if(status[0]&0x3D)
-		EDMA_error_handler(1, status[0]&0x3D);
-
-    /*
-	CIC: 16 EDMA3CC2 EDMACC_ERRINT EDMA3CC2 error interrupt
-	CIC: 18 EDMA3CC2 EDMATC_ERRINT0 EDMA3CC2 EDMA3TC0 error interrupt
-	CIC: 19 EDMA3CC2 EDMATC_ERRINT1 EDMA3CC2 EDMA3TC1 error interrupt
-	CIC: 20 EDMA3CC2 EDMATC_ERRINT2 EDMA3CC2 EDMA3TC2 error interrupt
-	CIC: 21 EDMA3CC2 EDMATC_ERRINT3 EDMA3CC2 EDMA3TC3 error interrupt*/
-	if((status[0]>>16)&0x3D)
-		EDMA_error_handler(2, (status[0]>>16)&0x3D);
-    
-	/*
-	CIC: 32 EDMA3CC0 EDMACC_ERRINT EDMA3CC0 error interrupt
-	CIC: 34 EDMA3CC0 EDMATC_ERRINT0 EDMA3CC0 EDMA3TC0 error interrupt
-	CIC: 35 EDMA3CC0 EDMATC_ERRINT1 EDMA3CC0 EDMA3TC1 error interrupt*/
-	if(status[1]&0xD)
-		EDMA_error_handler(0, status[1]&0xD);
-
-	/*----------------------------MPU error-----------------------------*/
-	if(TCI6614_EVM == DSP_Board_Type)
-	{
-        //CIC: 23 MPU0~7 addressing violation interrupt combine output 
-    	//CIC: 37 MPU0~7 protection violation interrupt combine output    	
-		if((status[0]&(1<<23))||(status[1]&(1<<(37-32))))
-		{
-		    for(i=0; i<8; i++)
-		    {
-		    	/*MPU5 (for BCP) of TCI6614 is only accessible 
-		    	when BCP is enabled through PSC*/
-		    	if((5==i)&&
-			    	((CSL_PSC_getPowerDomainState(5) != PSC_PDSTATE_ON) ||
-			        (CSL_PSC_getModuleState (12) != PSC_MODSTATE_ENABLE)))
-			        continue;
-			        
-		        if(gpMPU_regs[i]->INT_RAW_STATUS_SET & 0x3)
-		        {   
-		            KeyStone_peripherals_MPU_excepiton_handler(i);
-		        }
-		    }
-
-		    /*The MPU events in TCI6614 are different from other KeyStone 
-		    devices. All the MPU0~7 events are combined into single event 
-		    and connected to the CIC0 as one system event.
-			We have to clear the MPU event flag at the source level first 
-			and then are able to clear the CIC flags because the INTD for the 
-			MPU events is for the combination purpose but do not convert 
-			the level interrupt to pulse.*/
-			/*clear system events*/
-			gpCIC_regs->ENA_STATUS_REG[0]= status[0];
-			gpCIC_regs->ENA_STATUS_REG[1]= status[1];
-		}
-	}
-	else
-	{
-        //CIC: 90 MPU0 addressing violation interrupt and protection violation interrupt 
-		if(status[2]&(1<<(90-64)))
-		{
-			KeyStone_peripherals_MPU_excepiton_handler(0);
-		}
-    	//CIC: 92 MPU1 addressing violation interrupt and protection violation interrupt
-		if(status[2]&(1<<(92-64)))
-		{
-			KeyStone_peripherals_MPU_excepiton_handler(1);
-		}
-    	//CIC: 94 MPU2 addressing violation interrupt and protection violation interrupt
-		if(status[2]&(1<<(94-64)))
-		{
-			KeyStone_peripherals_MPU_excepiton_handler(2);
-		}
-    	//CIC: 96 MPU3 addressing violation interrupt and protection violation interrupt     	
-		if(status[3]&(1<<(96-96)))
-		{
-			KeyStone_peripherals_MPU_excepiton_handler(3);
-		}
-
-		if((C6670_EVM == DSP_Board_Type)
-			||(DUAL_NYQUIST_EVM == DSP_Board_Type))
-		{
-            //CIC: 174 MPU4 addressing violation interrupt and protection violation interrupt 
-            //CIC: 180 MPU5 addressing violation interrupt and protection violation interrupt
-			if(status5&(1<<(174-160)))
-			{
-				KeyStone_peripherals_MPU_excepiton_handler(4);
-			}
-			if(status5&(1<<(180-160)))
-			{
-				KeyStone_peripherals_MPU_excepiton_handler(5);
-			}
-		}
-	}
-    
-	/*----------------------------MSMC error-----------------------------*/
-	//CIC: 99 MSMC_dedc_nc_error Non-correctable (2-bit) soft error detected on SRAM read
-	if(status[3]&(1<<(99-96)))
-	{
-		KeyStone_SL2_EDC_handler();
-	}
-	//CIC: 100 MSMC_scrub_nc_error Non-correctable (2-bit) soft error detected during scrub cycle
-	if(status[3]&(1<<(100-96)))
-	{
-		KeyStone_SL2_EDC_handler();
-	}
-
-	/*
-	CIC: 102 MSMC_mpf_error8 Memory protection fault indicators for each system master PrivID
-	CIC: 103 MSMC_mpf_error9 Memory protection fault indicators for each system master PrivID
-	CIC: 104 MSMC_mpf_error10 Memory protection fault indicators for each system master PrivID
-	CIC: 105 MSMC_mpf_error11 Memory protection fault indicators for each system master PrivID
-	CIC: 106 MSMC_mpf_error12 Memory protection fault indicators for each system master PrivID
-	CIC: 107 MSMC_mpf_error13 Memory protection fault indicators for each system master PrivID
-	CIC: 108 MSMC_mpf_error14 Memory protection fault indicators for each system master PrivID
-	CIC: 109 MSMC_mpf_error15 Memory protection fault indicators for each system master PrivID*/
-	if((status[3]>>(102-96))&0xFF)
-		KeyStone_MSMC_protection_exception_handler();
-
-	if((C6670_EVM == DSP_Board_Type)
-		||(DUAL_NYQUIST_EVM == DSP_Board_Type)
-		||(TCI6614_EVM == DSP_Board_Type))
-	{
-		/*
-		CIC: 170 MSMC_mpf_error4 Memory protection fault indicators for each system master PrivID
-		CIC: 171 MSMC_mpf_error5 Memory protection fault indicators for each system master PrivID
-		CIC: 172 MSMC_mpf_error6 Memory protection fault indicators for each system master PrivID
-		CIC: 173 MSMC_mpf_error7 Memory protection fault indicators for each system master PrivID*/
-		if((status5>>(170-160))&0xF)
-			KeyStone_MSMC_protection_exception_handler();
-	
-	}
-
-	/*----------------------------DDR ECC error-------------------------*/
-	//CIC: 110 DDR3_ERR DDR3_EMIF Error Interrupt
-	if(status[3]&(1<<(110-96)))
-	{
-		printf("  DDR ECC error happened during ");
-
-		exception_record.status.ext_sts.info.memory.fault_status.DDR_IRQSTATUS_SYS= 
-			gpDDR_regs->IRQSTATUS_SYS;
-
-		if(gpDDR_regs->IRQSTATUS_SYS&CSL_EMIF4F_IRQSTATUS_SYS_REG_RD_ECC_ERR_SYS_MASK)
-			printf("read ");
-		if(gpDDR_regs->IRQSTATUS_SYS&CSL_EMIF4F_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_MASK)
-			printf("write ");
-		printf(".\n");
-
-		//clear the status
-		gpDDR_regs->IRQSTATUS_SYS= CSL_EMIF4F_IRQSTATUS_SYS_REG_RD_ECC_ERR_SYS_MASK
-			|CSL_EMIF4F_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_MASK;
-	}
-
-    /*Step3: Enable the CIC host interrupt */
-    KeyStone_CIC_enable_host_int(gpCIC_regs, gCIC_EXC_out_num);    
-
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_EXC_external
- Description  : external exception processing
- Input        : void  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-*****************************************************************************/
-void KeyStone_EXC_external(void)
-{
-	int i;
-	unsigned int INTXSTAT, flag[4];
-
-	for(i= 0; i<4; i++)
-	{
-		flag[i] = gpCGEM_regs->MEXPFLAG[i];
-		if(flag[i])
-		{
-			exception_record.status.ext_sts.MEXPFLAG[i]= flag[i];
-			printf("External exception happened. MEXPFLAG[%d]=0x%x.\n", 
-				i, flag[i]);
-			gpCGEM_regs->EVTCLR[i] = flag[i];
-		}
-	}
-
-	if(0 == (flag[0]|flag[1]|flag[2]|flag[3]))	
-	{
-		puts("Enter external Exception service routine, but external excpetion flage is 0!");
-		return;
-	}
-
-    /*Exception events routed from CIC*/
-    if(flag[guwIntcCICExcEvtIdx>>5] & (1<<(guwIntcCICExcEvtIdx&0x1F)))
-    {
-		KeyStone_CIC_EXC_handler();
-	}
-
-	/*MSMC memory protection exception*/
-	if(flag[0]&(1<<CSL_GEM_MSMC_MPF_ERRORN))
-	{
-		puts("  Event 10 : MSMC_mpf_error_n MSMC Memory protection fault indicators for local CorePac");
-
-         KeyStone_MSMC_protection_exception_handler();
-
- 	}
-
-	/*96 INTERR Dropped CPU interrupt event   */
-	if(flag[3]&(1<<(CSL_GEM_INTERR-96)))
-	{
-		INTXSTAT= gpCGEM_regs->INTXSTAT;
-		exception_record.status.ext_sts.info.INTXSTAT= INTXSTAT;
-
-		if(INTXSTAT&CSL_CGEM_INTXSTAT_DROP_MASK)
-			printf("  Event 96: DSP Interrupt %d (INTC input Event %d) dropped\n",
-				(INTXSTAT&CSL_CGEM_INTXSTAT_CPUINT_MASK)>>CSL_CGEM_INTXSTAT_CPUINT_SHIFT,
-				(INTXSTAT&CSL_CGEM_INTXSTAT_SYSINT_MASK)>>CSL_CGEM_INTXSTAT_SYSINT_SHIFT);
-	}
-
-	if(flag[3]&(1<<(CSL_GEM_EMC_IDMAERR-96)))
-		puts("  Event 97: EMC_IDMAERR Invalid IDMA parameters");
-
-	/*MDMA XMC VBUSM error*/
-	if(flag[3]&(1<<(CSL_GEM_MDMAERREVT-96)))
-	{
-		puts("  Event 110: MDMAERREVT XMC VBUSM error event");
-		if(gpXMC_regs->XMPFSR)
-		{
-			/*XMC protection error*/
-			memory_protection_exception_handler(gpXMC_regs->XMPFAR, gpXMC_regs->XMPFSR);
-			gpXMC_regs->XMPFCR = 1;
-		}
-		else
-		{
-			/*other VBUSM error*/
-			Bus_error_handler(gpCGEM_regs->MDMAERR);
-		}
-		/* clear the MDMAERR */
-		gpCGEM_regs->MDMAERRCLR = 1;
-	}
-
-	/*L1P Single bit error detected during DMA read*/
-	if(flag[3]&(1<<(CSL_GEM_PMC_ED-96)))
-	{
-		puts("  Event 113: PMC_ED Single bit error detected during DMA read");
-		L1P_ED_handler();
-	}
-
-	/*LL2 Uncorrected bit error detected*/
-	if(flag[3]&(1<<(CSL_GEM_UMC_ED2-96)))
-	{
-		puts("  Event 117: UMC_ED2 Uncorrected bit error detected");
-		LL2_EDC_handler(FALSE);
-	}
-
-	/*local register memory protection exception*/
-	if(flag[3]&(1<<(CSL_GEM_SYS_CMPA-96)))
-	{
-		puts("  Event 119: SYS_CMPA CPU Memory Protection Fault for local configuration of INTC and power control");
-	}
-
-	/*L1P memory protection exception*/
-	if(flag[3]&(3<<(CSL_GEM_PMC_CMPA-96)))
-	{
-		if(flag[3]&(1<<(CSL_GEM_PMC_CMPA-96)))
-			puts("  Event 120: PMC_CMPA CPU memory protection fault for L1P");
-		if(flag[3]&(1<<(CSL_GEM_PMC_DMPA-96)))
-			puts("  Event 121: PMC_DMPA DMA memory protection fault for L1P");
-		memory_protection_exception_handler(gpCGEM_regs->L1PMPFAR, gpCGEM_regs->L1PMPFSR);
-		gpCGEM_regs->L1PMPFCR = 1;
-	}
-
-	/*L1D memory protection exception*/
-	if(flag[3]&(3<<(CSL_GEM_DMC_CMPA-96)))
-	{
-		if(flag[3]&(1<<(CSL_GEM_DMC_CMPA-96)))
-			puts("  Event 122: DMC_CMPA CPU memory protection fault for L1D (and other memory read finally goes through the L1D controller)");
-		if(flag[3]&(1<<(CSL_GEM_DMC_DMPA-96)))
-			puts("  Event 123: DMC_DMPA DMA memory protection fault for L1D");
-		memory_protection_exception_handler(gpCGEM_regs->L1DMPFAR, gpCGEM_regs->L1DMPFSR);
-		gpCGEM_regs->L1DMPFCR = 1;
-	}
-
-	/*LL2 memory protection exception*/
-	if(flag[3]&(3<<(CSL_GEM_UMC_CMPA-96)))
-	{
-		if(flag[3]&(1<<(CSL_GEM_UMC_CMPA-96)))
-			puts("  Event 124: UMC_CMPA CPU memory protection fault for L2 ");
-		if(flag[3]&(1<<(CSL_GEM_UMC_DMPA-96)))
-			puts("  Event 125: UMC_DMPA DMA memory protection fault for L2 ");
-		memory_protection_exception_handler(gpCGEM_regs->L2MPFAR, gpCGEM_regs->L2MPFSR);
-		gpCGEM_regs->L2MPFCR = 1;
-	}
-
-	/*local registers protection exception*/
-	if(flag[3]&(1<<(CSL_GEM_EMC_CMPA-96)))
-	{
-		puts("  Event 126: EMC_CMPA CPU memory protection fault for local configuration space between 0x01000000-0x01BFFFFF");
-		memory_protection_exception_handler(gpCGEM_regs->ICFGMPFAR, gpCGEM_regs->ICFGMPFSR);
-		gpCGEM_regs->ICFGMPFCR= 1;
-	}
-
-	/*external configuration bus error*/
-	if(flag[3]&(Uint32)(1<<(CSL_GEM_EMC_BUSERR-96)))
-	{
-		puts("  Event 127: EMC_BUSERR Bus Error Interrupt for global configuration space between 0x01C00000 - 0x07FFFFFF");
-		Bus_error_handler(gpCGEM_regs->ECFGERR);
-		gpCGEM_regs->ECFGERRCLR= 1;
-	}
-}
-
-char * internal_exception_str[]=
-{
-	"Instruction fetch exception",
-	"Fetch packet exception",
-	"Execute packet exception",
-	"Opcode exception",
-	"Resource conflict exception",
-	"Resource access exception",
-	"Privilege exception",
-	"SPLOOP buffer exception",
-	"Missed stall exception"
-};
-
-/*****************************************************************************
- Prototype    : EXC_internal
- Description  : internal exception handler
- Input        : void  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-/*internal exception handler*/
-void EXC_internal(void)
-{
-	int i;
-	unsigned int ierr;
-
-	/*record IERR */    
-	ierr = IERR;
-	exception_record.status.IERR= ierr;
-
-	if(ierr)
-	{
-		/*Clear internal excpeiton flag*/
-		IERR= 0;
-
-		printf("internal excpetion happened. IERR=0x%x.\n", ierr);
-		for(i=0; i<9; i++)
-		{
-			if((ierr>>i)&1)
-				printf("  %s\n", internal_exception_str[i]);
-		}
-		if (ierr & CSL_CHIP_IERR_IFX_MASK) {
-			/* L1P EDC Processing*/
-			L1P_ED_handler();
-		}
-	}
-	else
-		puts("Enter Internal Exception service routine, but internal excpetion flage is 0!");
-	
-}
-/*****************************************************************************
- Prototype    : EXC_nmi
- Description  : NMI processing
- Input        : void  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-void EXC_NMI(void)
-{
-	puts("NMI exception happened, normally you should reset the DSP to recover from the problem!");
-}
-
-/*****************************************************************************
- Prototype    : EXC_swgen
- Description  : software generated exception handler
- Input        : void  
- Output       : None
- Return Value : 
-*****************************************************************************/
-void EXC_swgen(void)
-{	
-	puts("Software generated exception happened.");
-}
-
-/*****************************************************************************
- Prototype    : Exception_service_routine
- Description  : Exception service routine
- Input        : void  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-#pragma NMI_INTERRUPT( Exception_service_routine );
-void Exception_service_routine(void)
-{
-	unsigned int efr, nrp, ntsr, tscl, tsch, irp, itsr;
-
-	/*record timestamp*/
-	tscl = TSCL;
-	exception_record.TSCL= tscl;
-	tsch = TSCH;
-	exception_record.TSCH= tsch;
-	
-	nrp = NRP;   /*record NRP */
-	exception_record.NRP= nrp;
-	ntsr = NTSR; /*record NTSR */
-	exception_record.NTSR= ntsr;
-	efr = EFR;   /*record EFR */
-	exception_record.EFR= efr;
-
-	irp = IRP;   /*record IRP */
-	itsr = ITSR; /*record ITSR */
-	exception_record.IRP= irp;
-	exception_record.ITSR= itsr;
-
-	if(efr)
-	{
-		/*Clear excpeiton flag*/
-		ECR = efr;
-
-		/*check all possible exceptions*/
-		if (efr & CSL_CHIP_EFR_OXF_MASK) {
-			/* S/W generated exception */
-			EXC_swgen();		
-		}
-		if (efr & CSL_CHIP_EFR_IXF_MASK) {
-			/* internal exception */
-			EXC_internal();		
-		}
-		if (efr & CSL_CHIP_EFR_EXF_MASK) {
-			/* external exception */
-			KeyStone_EXC_external();		
-		}
-		if (efr & CSL_CHIP_EFR_NXF_MASK) {
-			/* legacy NMI exception */
-			EXC_NMI();		
-		}
-	}
-	else
-		puts("Enter Exception service routine, but excpetion flage is 0!");
-		
-	printf("NRP=0x%x, NTSR=0x%x, IRP=0x%x, ITSR=0x%x, TSCH= 0x%x, TSCL= 0x%x\n", 
-		nrp, ntsr, irp, itsr, tsch, tscl);
-
-	printf(" B3=0x%x, A4=0x%x, B4= 0x%x, B14= 0x%x, B15= 0x%x\n", 
-		exception_record.B3, exception_record.A4,
-		exception_record.B4, exception_record.B14,
-		exception_record.B15);
-
-	/*
-	It is not always possible to safely exit the exception handling routine. Conditions that
-	can prevent a safe return from exceptions include:
-	1. SPLOOPs that are terminated by an exception cannot be resumed correctly. The
-	SPLX bit in NTSR should be verified to be 0 before returning.
-	2. Exceptions that occur when interrupts are blocked cannot be resumed correctly.
-	The IB bit in NTSR should be verified to be 0 before returning.
-	3. Exceptions that occur at any point in the code that cannot be interrupted safely
-	(for example, a tight loop containing multiple assignments) cannot be safely
-	returned to. The compiler will normally disable interrupts at these points in the
-	program; check the GIE bit in NTSR to be 1 to verify that this condition is met.
-	4. NRP is not in valid address space*/
-	if((ntsr&CSL_CHIP_TSR_SPLX_MASK)
-		||(ntsr&CSL_CHIP_TSR_IB_MASK)
-		||(0==(ntsr&CSL_CHIP_TSR_GIE_MASK))
-		||(0x800000>NRP))
-	{
-		puts("Exception happened at a place can not safely return!");
-		//while(1);		//trap
-		exit(0);
-	}
-
-}
-
-/*****************************************************************************
- Prototype    : Nested_Exception_service_routine
- Description  : Nested Exception service routine
-  	When a non-maskable exception happens in the first exception service routine,
-  	then the reset vector is used when redirecting program execution to service the second
-	exception. In this case, NTSR and NRP are left unchanged. TSR is copied to ITSR and
-	the current PC is copied to IRP. TSR is set to the default exception processing value and
-	the NMIE bit in IER is cleared in this case preventing any further external exceptions.
- Input        : void  
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/29
-    Author       : Brighton Feng
-    Modification : Created function
-
-*****************************************************************************/
-interrupt void Nested_Exception_service_routine(void)
-{
-	unsigned int tscl, tsch;
-
-	/*record timestamp*/
-	tscl = TSCL;
-	tsch = TSCH;
-
-	if(0==exception_record.TSCL)
-		exception_record.TSCL= tscl;
-	if(0==exception_record.TSCH)
-		exception_record.TSCH= tsch;
-	if(0==exception_record.NRP)
-		exception_record.NRP= NRP;
-	if(0==exception_record.NTSR)
-		exception_record.NTSR= NTSR;
-	if(0==exception_record.EFR)
-		exception_record.EFR= EFR;
-	if(0==exception_record.status.IERR)
-		exception_record.status.IERR= IERR;
-
-	exception_record.IRP= IRP;
-	exception_record.ITSR= ITSR;
-
-	printf("Nested exception happened! IRP=0x%x, ITSR=0x%x\n",
-		IRP, ITSR);
-		
-	printf("NRP=0x%x, NTSR=0x%x, EFR=0x%x, IERR=0x%x, TSCH= 0x%x, TSCL= 0x%x\n", 
-		NRP, NTSR, EFR, IERR, tsch, tscl);
-
-	while(1);		//trap
-//	exit(0);
-}
-
-/*=========================other utility functions==========================*/
-/*clear all interrupt flag/status, setup ISTP to begining of LL2*/
-void CPU_interrupt_init()
-{
-	//clear interrupt and excpetion events
-	ICR = IFR;
-	ECR = EFR;
-	IER= 3; 	//disable all interrupts
-    
-	/* disable event combine */
-	gpCGEM_regs->EVTMASK[0] = 0xffffffff;
-	gpCGEM_regs->EVTMASK[1] = 0xffffffff;
-	gpCGEM_regs->EVTMASK[2] = 0xffffffff;
-	gpCGEM_regs->EVTMASK[3] = 0xffffffff;
-
-	 /*Clear all CPU events*/
-	gpCGEM_regs->EVTCLR[0]= 	0xFFFFFFFF;
-	gpCGEM_regs->EVTCLR[1]= 	0xFFFFFFFF;
-	gpCGEM_regs->EVTCLR[2]= 	0xFFFFFFFF;
-	gpCGEM_regs->EVTCLR[3]= 	0xFFFFFFFF;
-
-	/*Interrupt Service Table Pointer to begining of LL2 memory*/
-	ISTP= 0x800000;
-}
-
-/*enable interrupt to CPU: IER |= uiIER_en_mask; GIE=1*/
-void CPU_interrupt_enable(Uint32 uiIER_en_mask)
-{
-	ICR= uiIER_en_mask;
-	IER |= uiIER_en_mask;
-
-	//enable GIE
-	//TSR = TSR|1;
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_get_device_info
- Description  : Get device information
- Input        : None
- Output       : None
- Return Value : 
- 
-  History        :
-  1.Date         : 2010/12/12
-    Author       : Brighton Feng
-    Modification : Created function
-  2.Date         : 2014/12/2
-    Author       : Brighton Feng
-    Modification : Update to parser device type, boot mode, endian information,
-                   speed grade, required CVDD
-
-*****************************************************************************/
-//get device speed grade from the EFUSE register
-void KeyStone_get_device_speed_grade()
-{
-	Uint32 uiDevSpeed, uiSpeedCode;
-
-	uiSpeedCode= (DEVSPEED&DEVSPEED_DSP_SPEED_MASK)>>DEVSPEED_DSP_SPEED_SHIFT;
-
-	if(uiSpeedCode&DEVSPEED_800_MHZ_MASK_H)       uiDevSpeed= 800;
-	else if(uiSpeedCode&DEVSPEED_1000_MHZ_MASK_H) uiDevSpeed= 1000;
-	else if(uiSpeedCode&DEVSPEED_1200_MHZ_MASK_H) uiDevSpeed= 1200;
-	else if(uiSpeedCode&DEVSPEED_1250_MHZ_MASK_H) uiDevSpeed= 1250;
-	else if(uiSpeedCode&DEVSPEED_1400_MHZ_MASK_H) uiDevSpeed= 1400;
-	else if(uiSpeedCode&DEVSPEED_1400_MHZ_MASK_L) uiDevSpeed= 1400;
-	else if(uiSpeedCode&DEVSPEED_1250_MHZ_MASK_L) uiDevSpeed= 1250;
-	else if(uiSpeedCode&DEVSPEED_1200_MHZ_MASK_L) uiDevSpeed= 1200;
-	else if(uiSpeedCode&DEVSPEED_1000_MHZ_MASK_L) uiDevSpeed= 1000;
-	else                                          uiDevSpeed= 800;
-
-	printf("Device speed grade = %dMHz.\n", uiDevSpeed);
-}
-
-char * device_type_str[]=
-{
-	"TCI6616",
-	"C6670/TCI6618",
-	"C6678/TCI6608",
-	"TCI6614",
-	"unknown"
-};
-char * endian_str[]=
-{
-	"big",
-	"little"
-};
-char * boot_mode_str[]=
-{
-	"No boot or EMIF16(NOR FLASH) or UART",
-	"Serial Rapid I/O",
-	"Ethernet (SGMII)",
-	"Ethernet (SGMII) or NAND FLASH",
-	"PCIE",
-	"I2C",
-	"SPI",
-	"HyperLink"
- };
-char * input_clk_str[]=
-{
-	"50MHz",
-	"66.67MHz",
-	"80MHz",
-	"100MHz",
-	"156.25MHz",
-	"250MHz",
-	"312.5MHz",
-	"122.88MHz",
-	"bypassed"
-};
-void KeyStone_get_device_info()
-{
-	char * boot_mode;
-	Uint8 ucBootMode, ucBootMaster;
-	Uint32 uiVID;
-	Uint8 ucPLL_cfg= 8; //8 means bypassed
-	Uint32 * DieID= (Uint32 *)&gpBootCfgRegs->DIE_ID_REG0;
-	Uint32 uiJTAG_ID = gpBootCfgRegs->DEVICE_ID_REG0;
-	Uint32 uiDevStat = gpBootCfgRegs->BOOT_REG0;
-
-	gDSP_board_type=KeyStone_Get_dsp_board_type();
-
-	ucBootMode= (uiDevStat&DEVSTAT_BOOTMODE_MASK)>>DEVSTAT_BOOTMODE_SHIFT; 
-	ucBootMaster= (uiDevStat&DEVSTAT_BOOTMASTER_MASK)>>DEVSTAT_BOOTMASTER_SHIFT;
-
-	if((TCI6614_EVM==gDSP_board_type)&&(1==ucBootMaster))
-	{
-		boot_mode= "ARM";	//ARM boot
-	}
-	else
-		boot_mode= boot_mode_str[ucBootMode];
-
-	//PLL is not configured with SPI and I2C master boot mode
-	if((5!=ucBootMode)&&(6!=ucBootMode)) 	
-		ucPLL_cfg= (uiDevStat&DEVSTAT_SYSPLL_MASK)>>DEVSTAT_SYSPLL_SHIFT;
-
-	printf("JTAG ID= 0x%08x. This is %s device, version variant = %d.\n", uiJTAG_ID, 
-		device_type_str[gDSP_board_type], uiJTAG_ID>>28);
-
-	printf("DEVSTAT= 0x%08x. %s endian, %s boot, PLL configuration implies the input clock for core is %s.\n", 
-		uiDevStat, endian_str[uiDevStat&DEVSTAT_LENDIAN_MASK], boot_mode, 
-		 input_clk_str[ucPLL_cfg]);
-
-	uiVID= (gpPSC_regs->VCNTLID&CSL_PSC_VCNTLID_VCNTL_MASK)>>CSL_PSC_VCNTLID_VCNTL_SHIFT;
-	printf("SmartReflex VID= %d, required core voltage= %.3fV.\n", uiVID, 0.7+(float)uiVID*0.41/64.f);
-	
-	printf("Die ID= 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", DieID[0], DieID[1], DieID[2], DieID[3]);
-
-	KeyStone_get_device_speed_grade();
-}
-/*****************************************************************************
- Prototype    : KeyStone_common_device_init
- Description  : common initialization for internal modules in K2 device 
- enable memory protection interrupts, EDC for MSMC RAM 
-  History        :
-  1.Date         : July 11, 2014
-    Author       : Brighton Feng
-    Modification : Created function
-*****************************************************************************/
-void KeyStone_common_device_init()
-{
-	int i;
-	KeyStone_get_device_info();
-
-	/* enable common MPU interrupts */
-	for(i=0; i<4; i++)
-	{
-		KeyStone_MPU_interrupt_enable(i);
-	}
-
-	/*Enable MSMC EDC and setup scrubbing cycle counter= 255*1024*/
-	KeyStone_SL2_EDC_enable(255);
-}
-
-/*****************************************************************************
- Prototype    : KeyStone_common_CPU_init
- Description  : common initialization for internal modules in K2 device 
- enable TSC, EDC for local RAM; clear cache; protect L1 as cache 
-  History        :
-  1.Date         : September 1, 2014
-    Author       : Brighton Feng
-    Modification : Created function
-*****************************************************************************/
-void KeyStone_common_CPU_init()
-{
-    TSC_init();	//initialize TSC to measure cycle
-
-	/*clear all interrupt flag/status, setup ISTP to begining of LL2*/
-	CPU_interrupt_init();
-
-	/*clean cache from previous run, not required from power on or cold reset*/
-	CACHE_wbInvAllL2(CACHE_WAIT);
-	CSL_XMC_invalidatePrefetchBuffer();
-	_mfence();
-	_mfence();
-
-	/* protect L1 as cache */
-   	L1_cache_protection();
-   	
-	//Enable MSMC Memory protection error interrupt for local core, refer to MSMC user guide section3.8
-	// KeyStone_MSMC_MP_interrupt_en(1<<DNUM);
-    
-	/*enable L1P ED and scrub whole L1P*/
-	L1P_EDC_setup();
-
-   	/*enable LL2 EDC and scrub whole LL2*/
-	LL2_EDC_setup();
-
-}
-
-

bsp/ti-c6678/driver/KeyStone_common.h

@@ -1,1090 +0,0 @@
-/******************************************************************************
-
-  Copyright (C), 2001-2012, Texas Instrument.
-
- ******************************************************************************
-  File Name     : KeyStone_common.h
-  Version       : Initial Draft
-  Author        : Zhan
-  Created       : 2012/10/30
-  Last Modified :
-  Description   : KeyStone_common.c header file, KeyStone common miscellaneous functions and definitions
-  Function List :
-  History       :
-  1.Date        : 2010-12-12
-    Author      : Brighton Feng
-    Modification: Created file
-
-  2.Date         : 2012/10/6
-    Author       : Brighton Feng
-    Modification : For memory protection configuration
-
-  3.Date         : 2014-12-8
-    Author       : Brighton Feng
-    Modification : Add common device, CPU, interrupt initialization functions.
-                   Print device information including device type, speed grade, 
-                   boot mode, required voltage, ID¡­
-                   Add EDMA enable/disable functions.
-                   To support square wave generation by timer.
-******************************************************************************/
-#ifndef _KEYSTONE_COMMON_H_
-#define _KEYSTONE_COMMON_H_
-
-#include <c6x.h>
-#include <tistdtypes.h>
-#include <cslr_pllc.h>
-#include <cslr_xmc.h>
-#include <cslr_cgem.h>
-#include <csl_cgemAux.h>
-#include <cslr_bootcfg.h>
-#include <cslr_tpcc.h>
-#include <cslr_tptc.h>
-#include <cslr_device.h>
-#include <cslr_cpintc.h>
-#include <cslr_tmr.h>
-#include <cslr_srio.h>
-#include <cslr_vusr.h>
-#include <csl_psc.h>
-#include <csl_tmr.h>
-#include <csl_cache.h>
-#include <csl_cacheAux.h>
-#include <csl_xmcAux.h>
-#include <cslr_msmc.h>
-#include <csl_idma.h>
-#include <cslr_mpu.h>
-#include <cslr_gpio.h>
-#include <cslr_emif4f.h>
-#include <stdio.h>
-
-/*----------------------PLL registers definition----------------*/
-#define PLLCTL0_PLLD_SHIFT   (0)
-#define PLLCTL0_PLLD_MASK    (0x3F<<PLLCTL0_PLLD_SHIFT)
-#define PLLCTL0_PLLM_SHIFT   (6)
-#define PLLCTL0_PLLM_MASK    (0x1FFF<<PLLCTL0_PLLM_SHIFT)
-#define PLLCTL_OD_SHIFT      (19)
-#define PLLCTL_OD_MASK       (0xF<<PLLCTL_OD_SHIFT)
-#define PLLCTL_BYPASS_SHIFT  (23)
-#define PLLCTL_BYPASS_MASK   (0x1<<PLLCTL_BYPASS_SHIFT)
-#define PLLCTL0_BWADJ_SHIFT  (24)
-#define PLLCTL0_BWADJ_MASK   (0xFF<<PLLCTL0_BWADJ_SHIFT)
-
-#define PLLCTL1_BWADJ_SHIFT    (0)
-#define PLLCTL1_BWADJ_MASK     (0xF<<PLLCTL1_BWADJ_SHIFT)
-#define PLLCTL1_ENSAT_SHIFT    (6)
-#define PLLCTL1_ENSAT_MASK     (0x1<<PLLCTL1_ENSAT_SHIFT)
-#define PLLCTL1_PAPLL_SHIFT    (13)
-#define PLLCTL1_PAPLL_MASK     (0x1<<PLLCTL1_PAPLL_SHIFT)
-#define PLLCTL1_PLLRESET_SHIFT (14)
-#define PLLCTL1_PLLRESET_MASK  (0x1<<PLLCTL1_PLLRESET_SHIFT)
-
-/*----------------------Boot Config registers definition----------------*/
-#define DEVSPEED (*(unsigned int *)0x026203F8u)
-
-#define DEVSPEED_1000_MHZ_MASK_L  (1<<0)
-#define DEVSPEED_1200_MHZ_MASK_L  (1<<1)
-#define DEVSPEED_1250_MHZ_MASK_L  (1<<2)
-#define DEVSPEED_1400_MHZ_MASK_L  (1<<3)
-#define DEVSPEED_1400_MHZ_MASK_H  (1<<4)
-#define DEVSPEED_1250_MHZ_MASK_H  (1<<5)
-#define DEVSPEED_1200_MHZ_MASK_H  (1<<6)
-#define DEVSPEED_1000_MHZ_MASK_H  (1<<7)
-#define DEVSPEED_800_MHZ_MASK_H   (1<<8)
-
-#define DEVSPEED_DSP_SPEED_MASK  (0x1FFu<<23u)
-#define DEVSPEED_DSP_SPEED_SHIFT  (23u)
-
-#define DEVSTAT_LENDIAN_SHIFT     (0)
-#define DEVSTAT_BOOTMODE_SHIFT    (1)
-#define DEVSTAT_SYSPLL_SHIFT      (11)
-#define DEVSTAT_BOOTMASTER_SHIFT  (14)
-
-#define DEVSTAT_LENDIAN_MASK     (1<<0)
-#define DEVSTAT_BOOTMODE_MASK    (7<<1)
-#define DEVSTAT_SYSPLL_MASK      (7<<11)
-#define DEVSTAT_BOOTMASTER_MASK  (1<<14)
-/*----------------------Timer plus registers definition----------------*/
-typedef struct {
-    volatile Uint32 PID12;
-    volatile Uint32 EMUMGT_CLKSPD;
-    volatile Uint32 GPINT_EN;
-    volatile Uint32 GPDIR_DAT;
-    volatile Uint32 CNTLO;
-    volatile Uint32 CNTHI;
-    volatile Uint32 PRDLO;
-    volatile Uint32 PRDHI;
-    volatile Uint32 TCR;
-    volatile Uint32 TGCR;
-    volatile Uint32 WDTCR;
-    volatile Uint32 TLGC;
-    volatile Uint32 TLMR;
-    volatile Uint32 RELLO;
-    volatile Uint32 RELHI;
-    volatile Uint32 CAPLO;
-    volatile Uint32 CAPHI;
-    volatile Uint32 INTCTL_STAT;
-    volatile Uint8  RSVD0[24];
-    volatile Uint32 TIMERLO_COMPARE_REG[8];
-    volatile Uint8  RSVD1[32];
-} CSL_TmrPlusRegs;
-
-#define TMR_TCR_READRSTMODE_HI_SHIFT    (26)
-#define TMR_TCR_CAPEVTMODE_LO_SHIFT     (12)
-#define TMR_TCR_CAPMODE_LO_SHIFT        (11)
-#define TMR_TCR_READRSTMODE_LO_SHIFT    (10)
-
-#define TMR_TCR_READRSTMODE_HI_MASK    (1<<26)
-#define TMR_TCR_CAPEVTMODE_LO_MASK     (3<<12)
-#define TMR_TCR_CAPMODE_LO_MASK        (1<<11)
-#define TMR_TCR_READRSTMODE_LO_MASK    (1<<10)
-
-#define TMR_TGCR_PLUSEN_SHIFT 	       4
-#define TMR_TGCR_PLUSEN_MASK 	       (1<<4)
-
-#define TMR_INTCTLSTAT_EN_ALL_CLR_ALL   0x000F000F
-
-#define CSL_TMR_WDTCR_WDKEY_CMD1         (0x0000A5C6u)
-#define CSL_TMR_WDTCR_WDKEY_CMD2         (0x0000DA7Eu)
-
-#define CSL_TMR_ENAMODE_CONT_RELOAD 	3
-
-/*----------------------------------------------*
- * macros                                       *
- *----------------------------------------------*/
-/*convert local address to global address for DMA on multi-core DSP*/
-#define GLOBAL_ADDR(addr) ((Uint32)addr<0x1000000?\
-						(Uint32)addr+(0x10000000+DNUM*0x1000000):\
-						(Uint32)addr)
-
-/*according to default mapping, convert DDR3 logic address to 
-32-bit physical address (36-bit physical address right shift by 4)*/
-#define DDR_PHY_ADDR(addr) ((((Uint32)addr & 0x7FFFFFFF)>>4) | 0x80000000)
-
-/*max number in two numbers*/
-#define MAX(a, b) (a>b?a:b)
-/*min number in two numbers*/
-#define MIN(a, b) (a<b?a:b)
-
-extern CSL_XmcRegs * gpXMC_regs;
-extern CSL_CgemRegs * gpCGEM_regs;
-extern CSL_BootcfgRegs * gpBootCfgRegs;
-extern CSL_PllcRegs * gpPLLC_regs;
-extern CSL_PscRegs *  gpPSC_regs;
-extern CSL_MsmcRegs * gpMSMC_regs;
-extern CSL_GpioRegs * gpGPIO_regs;
-
-extern CSL_CPINTCRegs* gpCIC0_regs;
-extern CSL_CPINTCRegs* gpCIC1_regs;
-/*The register pointer for the CIC routing events DSP core.
-By default, it is CIC0; but for core 4~7 of C6678, it is CIC1*/
-extern CSL_CPINTCRegs* gpCIC_regs; 	
-
-extern CSL_TpccRegs*  gpEDMA_CC0_regs;
-extern CSL_TpccRegs*  gpEDMA_CC1_regs;
-extern CSL_TpccRegs*  gpEDMA_CC2_regs;
-extern CSL_TpccRegs*  gpEDMA_CC_regs[];
-extern CSL_TptcRegs * gpEDMA_TC_0_0_regs;
-extern CSL_TptcRegs * gpEDMA_TC_0_1_regs;
-extern CSL_TptcRegs * gpEDMA_TC_1_0_regs;
-extern CSL_TptcRegs * gpEDMA_TC_1_1_regs;
-extern CSL_TptcRegs * gpEDMA_TC_1_2_regs;
-extern CSL_TptcRegs * gpEDMA_TC_1_3_regs;
-extern CSL_TptcRegs * gpEDMA_TC_2_0_regs;
-extern CSL_TptcRegs * gpEDMA_TC_2_1_regs;
-extern CSL_TptcRegs * gpEDMA_TC_2_2_regs;
-extern CSL_TptcRegs * gpEDMA_TC_2_3_regs;
-extern CSL_TptcRegs * gpEDMA_TC_regs[];
-extern CSL_TmrPlusRegs * gpTimer0Regs;
-extern CSL_TmrPlusRegs * gpTimer1Regs;
-extern CSL_TmrPlusRegs * gpTimer2Regs;
-extern CSL_TmrPlusRegs * gpTimer3Regs;
-extern CSL_TmrPlusRegs * gpTimer4Regs;
-extern CSL_TmrPlusRegs * gpTimer5Regs;
-extern CSL_TmrPlusRegs * gpTimer6Regs;
-extern CSL_TmrPlusRegs * gpTimer7Regs;
-extern CSL_TmrPlusRegs * gpTimer8Regs;
-extern CSL_TmrPlusRegs * gpTimerRegs[];
-
-/*MPU for peripherals registers and data space*/
-extern CSL_MpuRegs * gpMPU0_regs;
-extern CSL_MpuRegs * gpMPU1_regs;
-extern CSL_MpuRegs * gpMPU2_regs;
-extern CSL_MpuRegs * gpMPU_regs[];
-extern CSL_Emif4fRegs * gpDDR_regs;
-extern CSL_MpuRegs * gpMPU3_regs;
-
-extern unsigned int gDSP_Core_Speed_Hz; //DSP core clock speed in Hz
-
-/*DSP core PLL configuration
-DSP core will be configured to run at ref_clock_MHz*multiplier/divisor
- Input        : float ref_clock_MHz     
-                unsigned int main_PLLM: 1~4096  
-                unsigned int multiplier: 1~64  
-*/
-extern void KeyStone_main_PLL_init (float ref_clock_MHz,
-	unsigned int multiplier, unsigned int divisor);
-
-
-typedef struct  {
-    volatile Uint32 PLL_CTL0;
-    volatile Uint32 PLL_CTL1;
-}PLL_ControlRegs;
-
- /*****************************************************************************
- Prototype    : KeyStone_PLL_init
- Description  : Config the PLL of ARM, PA and DDR
- 	target clock speed will be ref_clock_MHz/inputDivisor*multiplier/outputDivisor
- Input        : unsigned int inputDivisor  
-                unsigned int multiplier  
-                unsigned int outputDivisor  
-  Return Value : 0 for success, other value for error
- *****************************************************************************/
-extern int KeyStone_PLL_init (PLL_ControlRegs * PLL_Regs, unsigned int inputDivisor, 
-	unsigned int multiplier, unsigned int outputDivisor);
-
-/*****************************************************************************
- Prototype    : KeyStone_PASS_PLL_init
- Description  : Config the PASS PLL
- 	target clock speed will be ref_clock_MHz/divisor*multiplier
- Input        : float ref_clock_MHz
-                unsigned int multiplier: 1~4096
-                unsigned int divisor: 1~64
-*****************************************************************************/
-extern void KeyStone_PASS_PLL_init (float ref_clock_MHz,
-	unsigned int multiplier, unsigned int divisor);
-
-/*****************************************************************************
- Prototype    : KeyStone_DDR_PLL_init
- Description  : Config the DDR PLL
- 	target clock speed will be ref_clock_MHz/divisor*multiplier
- Input        : float ref_clock_MHz
-                unsigned int multiplier: 1~4096
-                unsigned int divisor: 1~64
-*****************************************************************************/
-extern void KeyStone_DDR_PLL_init (float ref_clock_MHz,
-	unsigned int multiplier, unsigned int divisor);
-
-/*===============================TSC===================================*/
-extern unsigned int cycle_measure_overhead;
-/*get the delay between current and prvious TSC
-The delay must be less than 32 bit
-enable the TSC with "TSCL= 0;" before use this macro*/
-#define TSC_getDelay(startTSC) 	((unsigned int)((0xFFFFFFFFl+TSCL)- (unsigned long long)startTSC)+ 1)
-#define TSC_count_cycle_from(startTSC) 	(TSC_getDelay(startTSC)- cycle_measure_overhead)
-
-/* Initialize Time stamp counter to measure cycles*/
-extern void TSC_init();
-
-/*delay in millisecond*/
-extern void TSC_delay_ms(Uint32 ms);
-
-/*delay in microsecond*/
-extern void TSC_delay_us(Uint32 us);
-
-/*===============================Timer=================================*/
-typedef enum
-{
-	TIMER_ONE_SHOT_PULSE = 0, 	/*generate one shot pulse with timer*/
-	TIMER_PERIODIC_PULSE, 	/*generate periodic pulse with timer*/
-	TIMER_PERIODIC_CLOCK, 	/*generate periodic clock with timer*/
-	/*generate periodic square wave with period reload feature, the difference 
-	between wave and clock is the duty cycle of clock is always 50%*/
-	TIMER_PERIODIC_WAVE, 	
-	TIMER_WATCH_DOG 		/*configure timer as watch dog*/
-}TTimerMode;
-
-typedef struct  {
-	int timer_num; 				/*select one timer*/
-	TTimerMode timerMode; 		/*select function of the timer*/
-	unsigned long long period; 	/*in the unit of DSP core clock/6*/
-	unsigned long long reload_period; 	/*the reload value of period*/
-	int pulseWidth; 			/*pulse width between 0~3*/	
-}Timer64_Config;
-
-extern void	Reset_Timer(int timer_num);
-
-/*Initailize a 64-bit timer*/
-extern void Timer64_Init(Timer64_Config * tmrCfg);
-
-typedef enum
-{
-	WD_OUT_NONE = 0,
-	WD_RESET_LOCAL = 2,
-	WD_TRIGGER_NMI = 3,
-	WD_TRIGGER_NMI_RESET_LOCAL = 4,
-	WD_RESET_DEVICE = 5
-}TWatchdogOutputMode;
-
-/*write sequence of a A5C6h followed by a DA7Eh 
-to services the watchdog timer.*/
-extern void Service_Watchdog(int timer_num);
-
-/*===============================PSC===================================*/
-extern Int32 KeyStone_enable_PSC_module (Uint32 pwrDmnNum, Uint32 moduleNum);
-extern Int32 KeyStone_disable_PSC_module (Uint32 pwrDmnNum, Uint32 moduleNum);
-extern Int32 KeyStone_disable_PSC_Power_Domain (Uint32 pwrDmnNum);
-
-/*============================EDMA=====================================*/
-#define NUM_EDMA_TC 	10
-#define NUM_EDMA_CC 	3
-
-//enum to indicate the EDMA CC number, and channel number
-typedef enum
-{
-	EDMA_CC0_CH0 = ((0<<16)|0 ),
-	EDMA_CC0_CH1 = ((0<<16)|1 ),
-	EDMA_CC0_CH2 = ((0<<16)|2 ),
-	EDMA_CC0_CH3 = ((0<<16)|3 ),
-	EDMA_CC0_CH4 = ((0<<16)|4 ),
-	EDMA_CC0_CH5 = ((0<<16)|5 ),
-	EDMA_CC0_CH6 = ((0<<16)|6 ),
-	EDMA_CC0_CH7 = ((0<<16)|7 ),
-	EDMA_CC0_CH8 = ((0<<16)|8 ),
-	EDMA_CC0_CH9 = ((0<<16)|9 ),
-	EDMA_CC0_CH10= ((0<<16)|10),
-	EDMA_CC0_CH11= ((0<<16)|11),
-	EDMA_CC0_CH12= ((0<<16)|12),
-	EDMA_CC0_CH13= ((0<<16)|13),
-	EDMA_CC0_CH14= ((0<<16)|14),
-	EDMA_CC0_CH15= ((0<<16)|15),
-
-	EDMA_CC1_CH0 = ((1<<16)|0 ),
-	EDMA_CC1_CH1 = ((1<<16)|1 ),
-	EDMA_CC1_CH2 = ((1<<16)|2 ),
-	EDMA_CC1_CH3 = ((1<<16)|3 ),
-	EDMA_CC1_CH4 = ((1<<16)|4 ),
-	EDMA_CC1_CH5 = ((1<<16)|5 ),
-	EDMA_CC1_CH6 = ((1<<16)|6 ),
-	EDMA_CC1_CH7 = ((1<<16)|7 ),
-	EDMA_CC1_CH8 = ((1<<16)|8 ),
-	EDMA_CC1_CH9 = ((1<<16)|9 ),
-	EDMA_CC1_CH10= ((1<<16)|10),
-	EDMA_CC1_CH11= ((1<<16)|11),
-	EDMA_CC1_CH12= ((1<<16)|12),
-	EDMA_CC1_CH13= ((1<<16)|13),
-	EDMA_CC1_CH14= ((1<<16)|14),
-	EDMA_CC1_CH15= ((1<<16)|15),
-	EDMA_CC1_CH16= ((1<<16)|16),
-	EDMA_CC1_CH17= ((1<<16)|17),
-	EDMA_CC1_CH18= ((1<<16)|18),
-	EDMA_CC1_CH19= ((1<<16)|19),
-	EDMA_CC1_CH20= ((1<<16)|20),
-	EDMA_CC1_CH21= ((1<<16)|21),
-	EDMA_CC1_CH22= ((1<<16)|22),
-	EDMA_CC1_CH23= ((1<<16)|23),
-	EDMA_CC1_CH24= ((1<<16)|24),
-	EDMA_CC1_CH25= ((1<<16)|25),
-	EDMA_CC1_CH26= ((1<<16)|26),
-	EDMA_CC1_CH27= ((1<<16)|27),
-	EDMA_CC1_CH28= ((1<<16)|28),
-	EDMA_CC1_CH29= ((1<<16)|29),
-	EDMA_CC1_CH30= ((1<<16)|30),
-	EDMA_CC1_CH31= ((1<<16)|31),
-	EDMA_CC1_CH32= ((1<<16)|32),
-	EDMA_CC1_CH33= ((1<<16)|33),
-	EDMA_CC1_CH34= ((1<<16)|34),
-	EDMA_CC1_CH35= ((1<<16)|35),
-	EDMA_CC1_CH36= ((1<<16)|36),
-	EDMA_CC1_CH37= ((1<<16)|37),
-	EDMA_CC1_CH38= ((1<<16)|38),
-	EDMA_CC1_CH39= ((1<<16)|39),
-	EDMA_CC1_CH40= ((1<<16)|40),
-	EDMA_CC1_CH41= ((1<<16)|41),
-	EDMA_CC1_CH42= ((1<<16)|42),
-	EDMA_CC1_CH43= ((1<<16)|43),
-	EDMA_CC1_CH44= ((1<<16)|44),
-	EDMA_CC1_CH45= ((1<<16)|45),
-	EDMA_CC1_CH46= ((1<<16)|46),
-	EDMA_CC1_CH47= ((1<<16)|47),
-	EDMA_CC1_CH48= ((1<<16)|48),
-	EDMA_CC1_CH49= ((1<<16)|49),
-	EDMA_CC1_CH50= ((1<<16)|50),
-	EDMA_CC1_CH51= ((1<<16)|51),
-	EDMA_CC1_CH52= ((1<<16)|52),
-	EDMA_CC1_CH53= ((1<<16)|53),
-	EDMA_CC1_CH54= ((1<<16)|54),
-	EDMA_CC1_CH55= ((1<<16)|55),
-	EDMA_CC1_CH56= ((1<<16)|56),
-	EDMA_CC1_CH57= ((1<<16)|57),
-	EDMA_CC1_CH58= ((1<<16)|58),
-	EDMA_CC1_CH59= ((1<<16)|59),
-	EDMA_CC1_CH60= ((1<<16)|60),
-	EDMA_CC1_CH61= ((1<<16)|61),
-	EDMA_CC1_CH62= ((1<<16)|62),
-	EDMA_CC1_CH63= ((1<<16)|63),
-
-	EDMA_CC2_CH0 = ((2<<16)|0 ),
-	EDMA_CC2_CH1 = ((2<<16)|1 ),
-	EDMA_CC2_CH2 = ((2<<16)|2 ),
-	EDMA_CC2_CH3 = ((2<<16)|3 ),
-	EDMA_CC2_CH4 = ((2<<16)|4 ),
-	EDMA_CC2_CH5 = ((2<<16)|5 ),
-	EDMA_CC2_CH6 = ((2<<16)|6 ),
-	EDMA_CC2_CH7 = ((2<<16)|7 ),
-	EDMA_CC2_CH8 = ((2<<16)|8 ),
-	EDMA_CC2_CH9 = ((2<<16)|9 ),
-	EDMA_CC2_CH10= ((2<<16)|10),
-	EDMA_CC2_CH11= ((2<<16)|11),
-	EDMA_CC2_CH12= ((2<<16)|12),
-	EDMA_CC2_CH13= ((2<<16)|13),
-	EDMA_CC2_CH14= ((2<<16)|14),
-	EDMA_CC2_CH15= ((2<<16)|15),
-	EDMA_CC2_CH16= ((2<<16)|16),
-	EDMA_CC2_CH17= ((2<<16)|17),
-	EDMA_CC2_CH18= ((2<<16)|18),
-	EDMA_CC2_CH19= ((2<<16)|19),
-	EDMA_CC2_CH20= ((2<<16)|20),
-	EDMA_CC2_CH21= ((2<<16)|21),
-	EDMA_CC2_CH22= ((2<<16)|22),
-	EDMA_CC2_CH23= ((2<<16)|23),
-	EDMA_CC2_CH24= ((2<<16)|24),
-	EDMA_CC2_CH25= ((2<<16)|25),
-	EDMA_CC2_CH26= ((2<<16)|26),
-	EDMA_CC2_CH27= ((2<<16)|27),
-	EDMA_CC2_CH28= ((2<<16)|28),
-	EDMA_CC2_CH29= ((2<<16)|29),
-	EDMA_CC2_CH30= ((2<<16)|30),
-	EDMA_CC2_CH31= ((2<<16)|31),
-	EDMA_CC2_CH32= ((2<<16)|32),
-	EDMA_CC2_CH33= ((2<<16)|33),
-	EDMA_CC2_CH34= ((2<<16)|34),
-	EDMA_CC2_CH35= ((2<<16)|35),
-	EDMA_CC2_CH36= ((2<<16)|36),
-	EDMA_CC2_CH37= ((2<<16)|37),
-	EDMA_CC2_CH38= ((2<<16)|38),
-	EDMA_CC2_CH39= ((2<<16)|39),
-	EDMA_CC2_CH40= ((2<<16)|40),
-	EDMA_CC2_CH41= ((2<<16)|41),
-	EDMA_CC2_CH42= ((2<<16)|42),
-	EDMA_CC2_CH43= ((2<<16)|43),
-	EDMA_CC2_CH44= ((2<<16)|44),
-	EDMA_CC2_CH45= ((2<<16)|45),
-	EDMA_CC2_CH46= ((2<<16)|46),
-	EDMA_CC2_CH47= ((2<<16)|47),
-	EDMA_CC2_CH48= ((2<<16)|48),
-	EDMA_CC2_CH49= ((2<<16)|49),
-	EDMA_CC2_CH50= ((2<<16)|50),
-	EDMA_CC2_CH51= ((2<<16)|51),
-	EDMA_CC2_CH52= ((2<<16)|52),
-	EDMA_CC2_CH53= ((2<<16)|53),
-	EDMA_CC2_CH54= ((2<<16)|54),
-	EDMA_CC2_CH55= ((2<<16)|55),
-	EDMA_CC2_CH56= ((2<<16)|56),
-	EDMA_CC2_CH57= ((2<<16)|57),
-	EDMA_CC2_CH58= ((2<<16)|58),
-	EDMA_CC2_CH59= ((2<<16)|59),
-	EDMA_CC2_CH60= ((2<<16)|60),
-	EDMA_CC2_CH61= ((2<<16)|61),
-	EDMA_CC2_CH62= ((2<<16)|62),
-	EDMA_CC2_CH63= ((2<<16)|63)
-}EDMA_CC_Channel_Num;
-
-typedef enum
-{
-	DMA_NO_WAIT= 0,	/*do not wait DMA complete*/
-	DMA_WAIT 			/*wait DMA complete*/
-}DMA_Wait;
-
-/*a structure to define a EDMA channel*/
-typedef struct
-{
-	Uint8 CC_num; 		//number of the CC for the channel
-	Uint8 channel_num;
-	Uint8 TC_num; 		//number of the TC used for the channel
-}EDMA_CC_Chanel_TC;
-
-/*setup uiChannel of an EDMA to use uiTC*/
-extern void EDMA_channel_TC_cfg (Uint32 uiCC, 
-	Uint32 uiChannel, Uint32 uiTC);
-extern void EDMA_TC_priority_cfg(Uint32 uiCC, 
-	Uint32 uiPri, Uint32 uiTC);
-extern void EDMA_init();
-
-extern void EDMA_event_enable(Uint32 uiCC, Uint32 uiChannel);
-extern void EDMA_event_disable(Uint32 uiCC, Uint32 uiChannel);
-extern void EDMA_interrupt_enable(Uint32 uiCC, Uint32 uiIntNum);
-extern void EDMA_interrupt_disable(Uint32 uiCC, Uint32 uiIntNum);
-
-/*wait the pending EDMA complete*/
-extern void EDMA_wait(EDMA_CC_Channel_Num CC_channel);
-extern void EDMA_copy(unsigned int srcAddr, unsigned int dstAddr, 
-	unsigned int byteCount, EDMA_CC_Channel_Num CC_channel, DMA_Wait wait);
-extern void EDMA_fill(unsigned int address, unsigned long long data, 
-	unsigned int byteCount, EDMA_CC_Channel_Num CC_channel);
-
-/*wait the pending IDMA complete*/
-extern void IDMA_wait();
-extern void IDMA_copy(unsigned int srcAddr, unsigned int dstAddr, 
-	unsigned int byteCount, DMA_Wait wait);
-
-/*======================memory protection==============================*/
-/*Memory Protection access permision mask*/
-#define MP_NONE 0
-#define MP_UX 	(1<<0) 
-#define MP_UW 	(1<<1) 
-#define MP_UR 	(1<<2) 
-#define MP_SX 	(1<<3) 
-#define MP_SW 	(1<<4) 
-#define MP_SR 	(1<<5) 
-
-/*for peripheral MPU only*/
-#define MP_NS   (1<<7)
-#define MP_EMU  (1<<6)
-
-/*Memory Protection mask for enabling AIDs*/
-#define MP_LOCAL    (1<<8)
-#define MP_AIDX     (1<<9)
-#define MP_AID0     (1<<10)
-#define MP_AID1     (1<<11)
-#define MP_AID2     (1<<12)
-#define MP_AID3     (1<<13)
-#define MP_AID4     (1<<14)
-#define MP_AID5     (1<<15)
-#define MP_AID0_5   0xFC00
-
-/*for peripheral MPU only*/
-#define MP_AID6     (1<<16)
-#define MP_AID7     (1<<17)
-#define MP_AID8     (1<<18)
-#define MP_AID9     (1<<19)
-#define MP_AID10    (1<<20)
-#define MP_AID11    (1<<21)
-#define MP_AID12    (1<<22)
-#define MP_AID13    (1<<23)
-#define MP_AID14    (1<<24)
-#define MP_AID15    (1<<25)
-#define MP_AID0_15  0x03FFFC00
-#define MP_AID0_7   0x0003FC00
-#define MP_AID8_15  0x03FC0000
-#define MPU_DENY_ALL 	(MP_AID0_15|MP_NONE)
-
-#define MAX_AID_NUM 	16
-
-typedef enum
-{
-	PRIVID_COREPAC0 = 0,
-	PRIVID_COREPAC1 = 1,
-	PRIVID_COREPAC2 = 2,
-	PRIVID_COREPAC3 = 3,
-
-	PRIVID_COREPAC4 = 4, 	/*C6678 ONLY*/
-	PRIVID_COREPAC5 = 5, 	/*C6678 ONLY*/
-	PRIVID_COREPAC6 = 6, 	/*C6678 ONLY*/
-	PRIVID_COREPAC7 = 7, 	/*C6678 ONLY*/
-
-	PRIVID_AIF2 = 4,	/*TCI6614/8 ONLY*/
-	PRIVID_TAC = 5,		/*TCI6614/8 ONLY*/
-	PRIVID_RAC = 6,		/*TCI6614/8 ONLY*/
-	PRIVID_ARM = 7, 	/*TCI6614 ONLY*/
-
-	PRIVID_PCIE= 11,
-	PRIVID_DEBUG_SS = 12,
-	PRIVID_HYPERLINK_FIRST_ID = 13,
-	PRIVID_HYPERLINK_SECOND_ID = 14,
-
-	/*--------FOR C6678/4/2----------*/
-	PRIVID_NETCP_C6678 = 8,
-	PRIVID_SRIO_C6678 = 9,
-	PRIVID_QMSS_C6678 = 10,
-	PRIVID_TSIP = 15, 	
-
-	/*--------FOR C6670----------*/
-	PRIVID_FFTC_C6670 = 7,
-	PRIVID_QMSS_SECOND_C6670 = 8,
-	PRIVID_SRIO_C6670 = 9,
-	PRIVID_QMSSPKTDMA_NETCP_C6670= 10,
-	PRIVID_TE_SCR_3M_C6670 = 15, /*BCP, TCP3D_C, FFTC_C*/
-
-	/*--------FOR TCI6614/2----------*/
-	PRIVID_PASS_FFTC_BCPPKTDMA_SRIOPKTDMA_QMSSPKTDMA_TCI6614 = 8, 
-	PRIVID_SRIODIO_TCI6614 = 9,
-	PRIVID_QMSS_SECOND_TCI6614 = 10,
-	PRIVID_BCP_DIO_TCI6614 = 15,
-	
-	PRIVID_ERROR = 16
-}KeyStone_PrivID;
-
-extern unsigned int mem_prot_key[4];
-extern void lock_mem_prot_regs();
-extern void unlock_mem_prot_regs();
-/*setup the memory protection for local L1 memory*/
-extern void L1_MPPA_setup(volatile Uint32 MPPA_regs[], Uint32 MPPA[]);
-/*config "AccessPermisionMask" for L1P*/
-extern void L1P_memory_protection_cfg(Uint32 AccessPermisionMask);
-/*config "AccessPermisionMask" for L1D*/
-extern void L1D_memory_protection_cfg(Uint32 AccessPermisionMask);
-/*----	protect L1 as cache ----*/
-extern void L1_cache_protection();
-/*----setup the memory protection for local L2 memory----
-usage example:
-Uint32 MPPA[32]=
-{
-	MP_LOCAL|MP_SX|MP_UX, 	//page 0 for local code only
-	MP_LOCAL|MP_SR|MP_SW|MP_UR|MP_UW, 	//page 1 for local data only
-	......
-}
-......
-	LL2_MPPA_setup(MPPA);
-*/
-extern void LL2_MPPA_setup(Uint32 MPPA[]);
-/*config "AccessPermisionMask" for local L2 memory section from 
-"startAddress" with "byteCount" size*/
-extern void LL2_Memory_Protection_cfg(Uint32 startAddress,
-	Uint32 byteCount, Uint32 AccessPermisionMask);
-
-/*map CorePac AID to PrivID:
-map_table[0] assign the PrivID for AID0,
-map_table[1] assign the PrivID for AID1
-......
-map_table[5] assign the PrivID for AID5*/
-extern void KeyStone_CorePac_AID_map(Uint8 map_table[]);
-
-/* privilege ID remap to AID */
-extern void KeyStone_PrivID_Remap(int privID, int AID);
-
-/* Register Overlay Structure MPAX*/
-typedef struct
-{
-    volatile Uint32 MPAXL;
-    volatile Uint32 MPAXH;
-}MPAX_Regs;
-
-/*memory protection and address extension configuration*/
-typedef struct
-{
-    Uint32 BADDR; 	/*32-bit virtual base address*/
-    /*36-bit physical replace address, right shift by 4 to get the value here)*/
-    Uint32 RADDR; 
-    Uint32 SegementSize; 	/*Segment size in byte, must be power of 2*/
-    Uint32 AccessPermisionMask; 	/*Access types allowed in this address range.*/
-}MPAX_Config;
-
-/*configure one MPAX segment*/
-extern void KeyStone_MPAX_seg_setup(MPAX_Regs * MPAX_regs, Uint32 BADDR, 
-	Uint32 RADDR, Uint32 SegementSize, Uint32 AccessPermisionMask);
-
-/*configure multiple MPAX segments in XMC with a configuration table*/
-extern void KeyStone_XMC_MPAX_setup(MPAX_Config MPAX_cfg[], 
-	Uint32 firstSeg, Uint32 numSegs);
-
-/*configure multiple MPAX segments in SMS of MSMC with a configuration table*/
-extern void KeyStone_SMS_MPAX_setup(MPAX_Config MPAX_cfg[], 
-	Uint32 firstSeg, Uint32 numSegs, Uint32 PrivID);
-	
-/*configure multiple MPAX segments in SES of MSMC with a configuration table*/
-extern void KeyStone_SES_MPAX_setup(MPAX_Config MPAX_cfg[], 
-	Uint32 firstSeg, Uint32 numSegs, Uint32 PrivID);
-	
-/*Enable MSMC Memory protection error interrupt for PrivIDs indicated by "PRIVID_MASK"*/
-extern void KeyStone_MSMC_MP_interrupt_en(Uint32 PRIVID_MASK);
-
-/*==========Peripherals registers and internal data buffer MPU=============*/
-/*peripherals memory protection unit configuration*/
-typedef struct
-{
-    Uint32 StartAddr; 	            /*32-bit start address*/
-    Uint32 EndAddr;                 /*32-bit end address*/
-    Uint32 AccessPermisionMask; 	/*Access types allowed in this address range.*/
-}MPU_Range_Config;
-
-typedef struct
-{
-    Uint32 StartAddr; 	            /*32-bit start address*/
-    Uint32 EndAddr;                 /*32-bit end address*/
-}MPU_Addr;
-
-extern CSL_MpuRegs * gpMPU_regs[];
-
-/*configure one range in peripheral MPU*/
-extern void KeyStone_MPU_range_setup(CSL_MpuProg_regionRegs *MPPA_regs, 
-	Uint32 uiStartAddress, Uint32 uiEndAddress, Uint32 AccessPermisionMask);
-
-/*peripherals MPU ranges configuration*/
-extern void KeyStone_MPU_setup(Uint32 uiMPU_num, 
-	MPU_Range_Config MPU_cfg[], Uint32 numRangeCfg);
-
-/*search the range which match a address and then modify
-the access permission of that range.*/
-extern void KeyStone_MPU_MPPA_modify(Uint32 uiMPU_num, 
-	Uint32 uiAddress, Uint32 AccessPermisionMask);
-
-/* enable one MPU interrupt */
-extern void KeyStone_MPU_interrupt_enable(Uint32 uiMPU_num);
-/* enable all MPU interrupts */
-extern void KeyStone_MPU_interrupts_enable();
-
-/*======================memory EDC=====================================*/
-/*Enable MSMC EDC and setup scrubbing cycle counter*/
-extern void KeyStone_SL2_EDC_enable(Uint32 scrubCnt);
-
-/*Enable MSMC EDC error interrupt*/
-extern void KeyStone_SL2_EDC_interrupt_en();
-
-/*enable LL2 EDC and scrub whole LL2*/
-extern void LL2_EDC_setup();
-
-/*----	L1P EDC setup ----*/
-extern void L1P_EDC_setup();
-
-/*scrub a block in LL2 for EDC. 
-Number of bytes must be multiple of 128 bits and less than 64KB.
-This function should be called periodically, for example, 
-if every 1 minute, call it with:	LL2_EDC_scrub(1024);
-For 1MB LL2, the whole space will be scrubbed in 1024 minutes(17 hours)*/
-extern void LL2_EDC_scrub(Uint32 uiByteCnt);
-
-/*LL2 EDC exception/interrupt handler*/
-extern void LL2_EDC_handler(Bool bCorrected);
-
-/*SL2 EDC handler*/
-extern void KeyStone_SL2_EDC_handler();
-/*===============================Exception=============================*/
-typedef	union	{
-	volatile Uint32 MPFSR; /*copy of MPFSR register for L1P, L1D or LL2*/
-	volatile Uint32 SMPFR; /*copy of SMPFR register for MSMC*/
-	volatile Uint32 MPU_FAULT_STATUS; /*copy of FAULT_STATUS register for MPU*/
-	volatile Uint32 L1PEDSTAT; /*copy of L1PEDSTAT register*/
-	volatile Uint32 L2EDSTAT; /*copy of L2EDSTAT register*/
-	volatile Uint32 SMESTAT; /*copy of SMESTAT register for SL2 EDC*/
-	volatile Uint32 DDR_IRQSTATUS_SYS; /*copy of IRQSTATUS_SYS for DDR ECC*/
-} Memory_Fault_Info;
-
-typedef	struct{
-	Uint32 fault_address;
-	Memory_Fault_Info fault_status; 	
-	volatile Uint32 BUS_ERROR; /*copy of MDMAERR or ECFGERR register*/
-} Memory_Exception_Info;
-
-typedef	struct{
-	volatile Uint32 EMR; /*copy of TPTC_EMR register*/
-	volatile Uint32 EMRH; /*copy of TPTC_EMRH register*/
-	volatile Uint32 QEMR; /*copy of TPTC_QEMR register*/
-	volatile Uint32 CCERR; /*copy of TPTC_CCERR register*/
-} EDMA_CC_Exception_Info;
-
-typedef	struct{
-	volatile Uint32 ERRSTAT; /*copy of TPTC_ERRSTAT register*/
-	volatile Uint32 ERRDET; /*copy of TPTC_ERRDET register*/
-} EDMA_TC_Exception_Info;
-
-typedef	union{
-	EDMA_CC_Exception_Info CC_info;
-	EDMA_TC_Exception_Info TC_info;
-} EDMA_Exception_Info;
-
-typedef	union	{
-	volatile Uint32 INTXSTAT; /*copy of INTXSTAT register*/
-	Memory_Exception_Info memory;
-	EDMA_Exception_Info edma;
-} Exception_Info;
-
-typedef	struct{
-	volatile Uint32 MEXPFLAG[4];  /*copy of the MEXPFLAG0..3 registers */
-	volatile Uint32 CIC_STATUS[7];  /*copy of the CIC status registers */
-	Exception_Info info;
-} External_Exception_Status;
-
-typedef	union	{
-	volatile Uint32 IERR; /*copy of the IERR register */
-	External_Exception_Status ext_sts;
-} Exception_Status;
-/**
-This structure is used to record exception information during 
-exception processing. 
-Please note, if multiple exceptions happens at the same time,
-only the last excpetion are record.
-Multiple unions are used in the structure to save space.
- * */
-typedef struct {
-	volatile Uint32 B3; /*copy of B3 register (return pointer of caller) */
-	volatile Uint32 A4; /*copy of the A4 register (first input parameter of caller)*/
-	volatile Uint32 B4; /*copy of the B4 register (second input parameter of caller)*/
-	volatile Uint32 B14; /*copy of the B14 register (data pointer)*/
-	volatile Uint32 B15; /*copy of the B15 register (stack pointer)*/
-	volatile Uint32 TSCL; /*copy of the TSCL register (time stamp)*/
-	volatile Uint32 TSCH; /*copy of the TSCH register (time stamp)*/
-	volatile Uint32 NTSR; /*copy of the NTSR register */
-	volatile Uint32 NRP; /*copy of the NRP register */
-	volatile Uint32 EFR; /*copy of the EFR register */
-	volatile Uint32 ITSR; /*copy of the ITSR register */
-	volatile Uint32 IRP; /*copy of the IRP register */
-	Exception_Status status;
-} Exception_Record;
-
-//data structure to save exception info
-extern Exception_Record exception_record;
-
-/*some exception events routed from CIC to INTC and then to exception moduel,
-all these events are routed to one input of INTC*/
-extern Uint32 guwIntcCICExcEvtIdx; /*INTC event number mapping to CIC exception events*/
-extern Uint32 gCIC_EXC_out_num; 	//CIC output event number
-
-/* Config the system error and exception to generate the NMI.
-If bGlobalExceptionMaster==TRUE, the global exception events 
-from CIC will be routed to exception model of this CPU core.
-Call this function as last step after all configuration/initialization complete*/
-extern void KeyStone_Exception_cfg(Bool bGlobalExceptionMaster);
-
-extern void Bus_error_handler(unsigned int ERR_REG);
-
-/*===============================Cache=================================*/
-/*enable workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices.
-Check your device errata to see if this is needed*/
-#define CACHE_DISABLE_INT 	1
-static inline void InvalidCache(void * blockPtr, Uint32 byteCnt)
-{
-#if CACHE_DISABLE_INT
-/*workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices*/
-	Uint32 uiOldGIE= _disable_interrupts();
-#endif
-
-	if(byteCnt>0xFFFF*4)
-		byteCnt= 0xFFFF*4;
-	if((Uint32)blockPtr>=0x0C000000&&(Uint32)blockPtr<0x0D000000)	//SL2
-	{
-		CACHE_invL1d((void *)blockPtr, byteCnt, CACHE_WAIT);
-		CSL_XMC_invalidatePrefetchBuffer();
-	}
-	else if((Uint32)blockPtr>=0x10000000) 	//DDR or other cores
-	{
-		CACHE_invL2((void *)blockPtr, byteCnt, CACHE_WAIT);
-		CSL_XMC_invalidatePrefetchBuffer();
-	}
-	_mfence();
-	_mfence();
-
-#if CACHE_DISABLE_INT
-/*workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices*/
-	asm(" nop 8");
-	asm(" nop 8");
-	_restore_interrupts(uiOldGIE); 	//restore interrupt
-#endif
-}
-
-static inline void WritebackCache(void * blockPtr, Uint32 byteCnt)
-{
-	if(byteCnt>0xFFFF*4)
-		byteCnt= 0xFFFF*4;
-	if((Uint32)blockPtr>=0x0C000000&&(Uint32)blockPtr<0x0D000000)	//SL2
-	{
-		CACHE_wbL1d((void *)blockPtr, byteCnt, CACHE_WAIT);
-	}
-	else if((Uint32)blockPtr>=0x10000000) 	//DDR or other cores
-	{
-		CACHE_wbL2((void *)blockPtr, byteCnt, CACHE_WAIT);
-	}
-	_mfence();
-	_mfence();
-}
- 
-static inline void WritebackAllCache(void * blockPtr)
-{
-	if((Uint32)blockPtr>=0x0C000000&&(Uint32)blockPtr<0x0D000000)	//SL2
-	{
-		CACHE_wbAllL1d(CACHE_WAIT);;
-	}
-	else if((Uint32)blockPtr>=0x10000000) 	//DDR or other cores
-	{
-		CACHE_wbAllL2(CACHE_WAIT);
-	}
-	_mfence();
-	_mfence();
-}
-
-static inline void WritebackInvalidCache(void * blockPtr, Uint32 byteCnt)
-{
-#if CACHE_DISABLE_INT
-/*workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices*/
-	Uint32 uiOldGIE= _disable_interrupts();
-#endif
-
-	if(byteCnt>0xFFFF*4)
-		byteCnt= 0xFFFF*4;
-	if((Uint32)blockPtr>=0x0C000000&&(Uint32)blockPtr<0x0D000000)	//SL2
-	{
-		CACHE_wbInvL1d((void *)blockPtr, byteCnt, CACHE_WAIT);
-		CSL_XMC_invalidatePrefetchBuffer();
-	}
-	else if((Uint32)blockPtr>=0x10000000) 	//DDR or other cores
-	{
-		CACHE_wbInvL2((void *)blockPtr, byteCnt, CACHE_WAIT);
-		CSL_XMC_invalidatePrefetchBuffer();
-	}
-	_mfence();
-	_mfence();
-
-#if CACHE_DISABLE_INT
-/*workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices*/
-	asm(" nop 8");
-	asm(" nop 8");
-	_restore_interrupts(uiOldGIE); 	//restore interrupt
-#endif
-}
- 
-static inline void WritebackInvalidAllCache(void * blockPtr)
-{
-#if CACHE_DISABLE_INT
-/*workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices*/
-	Uint32 uiOldGIE= _disable_interrupts();
-#endif
-
-	if((Uint32)blockPtr>=0x0C000000&&(Uint32)blockPtr<0x0D000000)	//SL2
-	{
-		CACHE_wbInvAllL1d(CACHE_WAIT);//CACHE_invL1d((void *)blockPtr, byteCnt, CACHE_WAIT);
-		CSL_XMC_invalidatePrefetchBuffer();
-	}
-	else if((Uint32)blockPtr>=0x10000000) 	//DDR or other cores
-	{
-		//CACHE_invL2((void *)blockPtr, byteCnt, CACHE_WAIT);
-		CACHE_wbInvAllL2(CACHE_WAIT);
-		CSL_XMC_invalidatePrefetchBuffer();
-	}
-	_mfence();
-	_mfence();
-
-#if CACHE_DISABLE_INT
-/*workaround for the "L2 Cache Corruption During Block and Global Coherence Operations
-Issue" described in errata of some devices*/
-	asm(" nop 8");
-	asm(" nop 8");
-	_restore_interrupts(uiOldGIE); 	//restore interrupt
-#endif
-}
-
-static inline unsigned int SWAP_ENDIAN(unsigned int byte_index)
-{
-#ifdef _BIG_ENDIAN
-	return ((byte_index&0xFFFFFFFC)+(3-byte_index&3));
-#else
-	return byte_index;
-#endif
-}
-
-static inline void KeyStone_CIC_clear_system_event(CSL_CPINTCRegs* cpIntcRegs,
-	int input_event_num)
-{
-	volatile Uint32 dummy_value;
-
-	/*clear input interrupts events*/
-	cpIntcRegs->STATUS_CLR_INDEX_REG= input_event_num;
-
-	/*dummy read to make sure the previous write data land into the register*/
-	dummy_value= cpIntcRegs->STATUS_CLR_INDEX_REG;
-}
-
-static inline void KeyStone_CIC_disable_host_int(CSL_CPINTCRegs* cpIntcRegs,
-	int host_int_num)
-{
-	volatile Uint32 dummy_value;
-
-	/* Disable the host interrupt */
-	cpIntcRegs->HINT_ENABLE_CLR_INDEX_REG = host_int_num;
-
-	/*dummy read to make sure the previous write data land into the register*/
-	dummy_value= cpIntcRegs->HINT_ENABLE_CLR_INDEX_REG;
-}
-
-static inline void KeyStone_CIC_enable_host_int(CSL_CPINTCRegs* cpIntcRegs,
-	int host_int_num)
-{
-	volatile Uint32 dummy_value;
-
-	/* Enable the host interrupt */
-	cpIntcRegs->HINT_ENABLE_SET_INDEX_REG = host_int_num;
-
-	/*dummy read to make sure the previous write data land into the register*/
-	dummy_value= cpIntcRegs->HINT_ENABLE_SET_INDEX_REG;
-}
-
-static inline void KeyStone_CIC_event_map(CSL_CPINTCRegs* cpIntcRegs,
-	int input_event_num, int out_num)
-{
-	/*Map input event to output*/
-	cpIntcRegs->CH_MAP[SWAP_ENDIAN(input_event_num)]= out_num;
-
-	/*clear input interrupts events*/
-	cpIntcRegs->STATUS_CLR_INDEX_REG= input_event_num; 
-
-	/*enable input interrupts events*/
-	cpIntcRegs->ENABLE_SET_INDEX_REG= input_event_num;
-
-	/*enable output*/
-	cpIntcRegs->HINT_ENABLE_SET_INDEX_REG= out_num;
-}
-
-
-typedef enum
-{
-	DUAL_NYQUIST_EVM = 0, 						
-	C6670_EVM, 						
-	C6678_EVM,
-	TCI6614_EVM,
-	C6657_EVM,
-	UNKNOWN
-}TDSP_Board_Type;
-
-extern TDSP_Board_Type gDSP_board_type;
-
-static inline TDSP_Board_Type KeyStone_Get_dsp_board_type()
-{	
-	Uint32 deviceID= gpBootCfgRegs->DEVICE_ID_REG0&0x0FFFFFFF;
-
-	gDSP_board_type= UNKNOWN;
-	if(0x0009D02F == deviceID)
-		gDSP_board_type= DUAL_NYQUIST_EVM;
-	if(0x0B94102F == deviceID)
-	{
-		gDSP_board_type= C6670_EVM;
-		//DSP_Board_Type= DUAL_NYQUIST_EVM;
-	}
-	if(0x0009E02F == deviceID)
-		gDSP_board_type= C6678_EVM;
-	if(0x0B96202F == deviceID)
-		gDSP_board_type= TCI6614_EVM;
-	if(0x0B97A02F == deviceID)
-		gDSP_board_type= C6657_EVM;
-
-	return gDSP_board_type;
-}
-
-static inline Uint32 KeyStone_Get_DSP_Number()
-{
-	TDSP_Board_Type DSP_Board_Type= KeyStone_Get_dsp_board_type();
-
-	if(DUAL_NYQUIST_EVM==DSP_Board_Type)
-	{
-		/*Nyquist EVM use boot configure pin 4 and 5 to identify DSPs*/
-		return (( gpBootCfgRegs->BOOT_REG0 >> (3+1) ) & 0x03);
-	}
-
-	/*if use DNUM to differentiate DSPs for two DSPs test,
-	the program must be run on core 0 of DSP 0 and core 1 of DSP1*/
-	return DNUM;
-}
-
-/*clear all interrupt flag/status, setup ISTP to begining of LL2*/
-extern void CPU_interrupt_init();
-/*enable interrupt to CPU: IER |= uiIER_en_mask; GIE=1*/
-extern void CPU_interrupt_enable(Uint32 uiIER_en_mask);
-
-//get device speed grade from the EFUSE register
-extern void KeyStone_get_device_speed_grade();
-
-/*Get device information including device type, boot mode, endian information,
-speed grade, required voltage...*/
-extern void KeyStone_get_device_info();
-
-/*common initialization for internal modules in K2 device.
-enable memory protection interrupts, EDC for MSMC RAM*/
-extern void KeyStone_common_device_init();
-
-/* enable TSC, EDC for local RAM; clear cache; protect L1 as cache */
-extern void KeyStone_common_CPU_init();
-
-
-#endif

bsp/ti-c6678/applications/board.c → bsp/ti-tms320c6678/applications/board.c

@@ -22,13 +22,13 @@
  */
 void rt_hw_systick_isr(void)
 {
-    /* enter interrupt */
-    rt_interrupt_enter();
+	/* enter interrupt */
+	rt_interrupt_enter();
 
-    rt_tick_increase();
+	rt_tick_increase();
 
-    /* leave interrupt */
-    rt_interrupt_leave();
+	/* leave interrupt */
+	rt_interrupt_leave();
 }
 
 /**
@@ -46,15 +46,12 @@ void rt_hw_board_init(void)
 	rt_trap_init();
 
 	// initial system timer
-    hw_system_timer_init();
+	hw_system_timer_init();
 
-#ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-#endif
-    // ......
+	/* initialize memory system */
+	rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+	rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
 
-    hw_system_timer_start();
+	hw_system_timer_start();
 }
 

bsp/ti-tms320c6678/applications/main.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-16     Dystopia     the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+void rt_init_thread_entry(void *parameter)
+{
+	rt_kprintf("hello rt-thread\n");
+	return 0;
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 4096, 3, 200);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    } else {
+        return -1;
+    }
+
+    return 0;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+	/* init application */
+	rt_application_init();
+
+	/* init timer thread */
+	rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+void main(void)
+{
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	for ( ; ; );
+}
+

bsp/ti-tms320c6678/readme.txt

@@ -0,0 +1,3 @@
+	本工程使用TI公司编译器CCS5.5进行编译，工程中使用到了TI官方提供的K1_STK_v1.1，
+如有需要的请到TI官方论坛自行下载，并将K1_STK_v1.1中的KeyStone_common.c和KeyStone_common.h文件
+放置到本工程的driver目录下。

libcpu/ti-dsp/c6x/c66xx.h

@@ -91,14 +91,13 @@ extern cregister volatile unsigned int DNUM;    /* Core number */
 
 #define __dint()				asm(" DINT")
 #define __rint()				asm(" RINT")
-
 #define __system_call()			asm(" SWE")
 #define __enter_idle()			asm(" IDLE")
 #define __nop()					asm(" NOP")
 #define __mfence()				asm(" MFENCE")
 
-#define __SYSREG(ADDR, TYPE) 	(*(volatile TYPE*)(ADDR))
-#define __SYSREGA(ADDR, TYPE) 	((volatile TYPE*)(ADDR))
+#define __SYSREG(ADDR, TYPE)	(*(volatile TYPE*)(ADDR))
+#define __SYSREGA(ADDR, TYPE)	((volatile TYPE*)(ADDR))
 
 extern void rt_hw_enable_exception(void);
 

libcpu/ti-dsp/c6x/context.asm

@@ -12,12 +12,17 @@
 ; context switch for C6678 DSP
 ;-----------------------------------------------------------
 
+	.include "contextinc.asm"
 ;-----------------------------------------------------------
 ; 						macro definition
 ;-----------------------------------------------------------
 DP	.set	B14
 SP	.set	B15
 
+;-----------------------------------------------------------
+; 						extern variable
+;-----------------------------------------------------------
+	.ref rt_system_stack_top
 ;
 ;-----------------------------------------------------------
 ;
@@ -28,7 +33,6 @@ SP	.set	B15
 	.global	rt_interrupt_from_thread
 	.global	rt_interrupt_to_thread
 	.global	rt_thread_switch_interrupt_flag
-
 ;
 ;-----------------------------------------------------------
 ;
@@ -100,18 +104,17 @@ rt_hw_context_switch:
 	STDW	.D2T2	B13:B12,*SP--[1]	; Store PC:CSR
  ||	MVC	.S2	TSR,B5
 
-	MVC	ILC,B11							;
-	MVC	RILC,B10						;
+	MVC	.S2	ILC,B11						;
+	MVC	.S2	RILC,B10					;
 	STDW	.D2T2	B11:B10,*SP--[1]	; Store RILC:ILC
  ||	MV	.S1X	B5,A3
 
 	ZERO	A2          				;
 	STDW	.D2T1	A3:A2,*SP--[1]		; Store TSR:stack type
 	STW	SP,*A4							; Save thread's stack pointer
-
-	MV	B4,A4							;
 	B	rt_hw_context_switch_to
-	NOP	5
+	MV	B4,A4							;
+	NOP	4
 ;}
 
 ;
@@ -138,13 +141,13 @@ rt_hw_context_switch_to:
 	MV	B13,B3							; Restore PC
 	MVC	.S2	B12,CSR						; Restore CSR
 
-	LDDW	*++SP[1],B11:B10
-  	LDDW	*++SP[1],B13:B12
-	LDDW	*++SP[1],A11:A10
-	LDDW	*++SP[1],A13:A12
-	LDDW	*++SP[1],A15:A14
+	LDDW	.D2T2	*++SP[1],B11:B10
+  	LDDW	.D2T2	*++SP[1],B13:B12
+	LDDW	.D2T1	*++SP[1],A11:A10
+	LDDW	.D2T1	*++SP[1],A13:A12
+	LDDW	.D2T1	*++SP[1],A15:A14
 	B	B3                              ; Return to caller
-	ADDAW	SP,2,SP
+	ADDAW	.D2	SP,2,SP
 	NOP	4                               ; Delay slots
 _rt_thread_interrupt_stack:
 	ADDAW	.D1X	SP,30,A15
@@ -204,6 +207,7 @@ _rt_thread_interrupt_stack:
 ; void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
 ; A4 --> from
 ; B4 --> to
+;{
 	.global	rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
 	SUB		B15,0x8,B15
@@ -285,14 +289,26 @@ rt_interrupt_context_restore:
  ||	LDDW	.D2T2	*++SP[1],B13:B12
 
 	MV	.D2X	A15,SP
+ ||	MVKL	.S1	rt_system_stack_top,A15
+	MVKH	.S1	rt_system_stack_top,A15
+ ||	ADDAW	.D1X	SP,6,A14
+	STW	.D1T1	A14,*A15				; save system stack pointer
+
  	LDDW	.D2T1	*++SP[1],A15:A14
 	B	.S2	IRP							; return from interruption
 	LDDW	.D2T2	*+SP[1],SP:DP
 	NOP		4
-
 rt_preempt_context_restore:
 	ZERO	A12
-	STW	A12,*A3								; clear rt_thread_switch_interrupt_flag
+	STW	A12,*A3							; clear rt_thread_switch_interrupt_flag
+;
+; restore saved registers by system stack
+;
+	RESTORE_ALL	IRP,ITSR
+;
+; store registers to thread stack
+;
+	THREAD_SAVE_ALL	IRP,ITSR
 
     MVKL	rt_interrupt_from_thread,A11
     MVKH	rt_interrupt_from_thread,A11
@@ -302,10 +318,10 @@ rt_preempt_context_restore:
     MVKH	rt_interrupt_to_thread,B10
     LDW		*B10,B11
     NOP		3
-    STW		SP,*A10	    					; store sp in preempted tasks's TCB
-	MV		B11,A4							;
-	B		rt_hw_context_switch_to
-	NOP		5
+    STW		SP,*A10	    				; store sp in preempted tasks's TCB
+    B		rt_hw_context_switch_to
+	MV		B11,A4						;
+	NOP		4
 ;}
 
 	.end

libcpu/ti-dsp/c6x/contextinc.asm

@@ -0,0 +1,187 @@
+;
+; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Change Logs:
+; Date           Author       Notes
+; 2021-11-16     Dystopia     the first version
+;
+
+;-----------------------------------------------------------
+;					macro definition
+;-----------------------------------------------------------
+SAVE_ALL	.macro  __rp, __tsr
+	STW	.D2T2	B0,*SP--[2]				; save original B0
+	MVKL	.S2	rt_system_stack_top,B0
+	MVKH	.S2	rt_system_stack_top,B0
+	LDW	.D2T2	*B0,B1					; system stack
+
+	NOP	3
+	STW	.D2T2	B1,*+SP[1]				; save original B1
+	XOR	.D2	SP,B1,B0					; (SP ^ KSP, check current stack types)
+	LDW	.D2T2	*+SP[1],B1				; restore B0/B1
+	LDW	.D2T2	*++SP[2],B0
+	SHR	.S2	B0,12,B0					; 0 if already using system stack
+ [B0]	STDW	.D2T2	SP:DP,*--B1[1]	; thread: save thread sp/dp system stack
+ [B0]	MV	.S2	B1,SP					; and switch to system stack
+||[!B0] STDW	.D2T2	SP:DP,*--SP[1]	; kernel: nest interrupt save(not support)
+
+	SUBAW	.D2	SP,2,SP
+
+	ADD	.D1X	SP,-8,A15
+ ||	STDW	.D2T1	A15:A14,*SP--[16]	; save A15:A14
+
+	STDW	.D2T2	B13:B12,*SP--[1]
+ ||	STDW	.D1T1	A13:A12,*A15--[1]
+ ||	MVC	.S2	__rp,B13
+	STDW	.D2T2	B11:B10,*SP--[1]
+ ||	STDW	.D1T1	A11:A10,*A15--[1]
+ ||	MVC	.S2	CSR,B12
+
+	STDW	.D2T2	B9:B8,*SP--[1]
+ ||	STDW	.D1T1	A9:A8,*A15--[1]
+ ||	MVC	.S2	RILC,B11
+	STDW	.D2T2	B7:B6,*SP--[1]
+ ||	STDW	.D1T1	A7:A6,*A15--[1]
+ ||	MVC	.S2	ILC,B10
+	STDW	.D2T2	B5:B4,*SP--[1]
+ ||	STDW	.D1T1	A5:A4,*A15--[1]
+	STDW	.D2T2	B3:B2,*SP--[1]
+ ||	STDW	.D1T1	A3:A2,*A15--[1]
+ ||	MVC	.S2	__tsr,B5
+	STDW	.D2T2	B1:B0,*SP--[1]
+ ||	STDW	.D1T1	A1:A0,*A15--[1]
+ ||	MV	.S1X	B5,A5
+
+	STDW	.D2T2	B31:B30,*SP--[1]
+ ||	STDW	.D1T1	A31:A30,*A15--[1]
+ || MVKL	1,A4
+
+	STDW	.D2T2	B29:B28,*SP--[1]
+ ||	STDW	.D1T1	A29:A28,*A15--[1]
+	STDW	.D2T2	B27:B26,*SP--[1]
+ ||	STDW	.D1T1	A27:A26,*A15--[1]
+	STDW	.D2T2	B25:B24,*SP--[1]
+ ||	STDW	.D1T1	A25:A24,*A15--[1]
+	STDW	.D2T2	B23:B22,*SP--[1]
+ ||	STDW	.D1T1	A23:A22,*A15--[1]
+	STDW	.D2T2	B21:B20,*SP--[1]
+ ||	STDW	.D1T1	A21:A20,*A15--[1]
+	STDW	.D2T2	B19:B18,*SP--[1]
+ ||	STDW	.D1T1	A19:A18,*A15--[1]
+	STDW	.D2T2	B17:B16,*SP--[1]
+ ||	STDW	.D1T1	A17:A16,*A15--[1]
+
+	STDW	.D2T2	B13:B12,*SP--[1]	; save PC and CSR
+	STDW	.D2T2	B11:B10,*SP--[1]	; save RILC and ILC
+	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and orig A4
+			.endm
+
+RESTORE_ALL	.macro  __rp, __tsr
+	LDDW	.D2T2	*++SP[1],B9:B8		; get TSR (B9)
+	LDDW	.D2T2	*++SP[1],B11:B10	; get RILC (B11) and ILC (B10)
+	LDDW	.D2T2	*++SP[1],B13:B12	; get PC (B13) and CSR (B12)
+
+	ADDAW	.D1X	SP,30,A15
+
+	LDDW	.D1T1	*++A15[1],A17:A16
+ ||	LDDW	.D2T2	*++SP[1],B17:B16
+	LDDW	.D1T1	*++A15[1],A19:A18
+ ||	LDDW	.D2T2	*++SP[1],B19:B18
+	LDDW	.D1T1	*++A15[1],A21:A20
+ ||	LDDW	.D2T2	*++SP[1],B21:B20
+	LDDW	.D1T1	*++A15[1],A23:A22
+ ||	LDDW	.D2T2	*++SP[1],B23:B22
+	LDDW	.D1T1	*++A15[1],A25:A24
+ ||	LDDW	.D2T2	*++SP[1],B25:B24
+	LDDW	.D1T1	*++A15[1],A27:A26
+ ||	LDDW	.D2T2	*++SP[1],B27:B26
+	LDDW	.D1T1	*++A15[1],A29:A28
+ ||	LDDW	.D2T2	*++SP[1],B29:B28
+	LDDW	.D1T1	*++A15[1],A31:A30
+ ||	LDDW	.D2T2	*++SP[1],B31:B30
+
+	LDDW	.D1T1	*++A15[1],A1:A0
+ ||	LDDW	.D2T2	*++SP[1],B1:B0
+	LDDW	.D1T1	*++A15[1],A3:A2
+ ||	LDDW	.D2T2	*++SP[1],B3:B2
+ ||	MVC	.S2	B9,__tsr
+	LDDW	.D1T1	*++A15[1],A5:A4
+ ||	LDDW	.D2T2	*++SP[1],B5:B4
+ ||	MVC	.S2	B11,RILC
+	LDDW	.D1T1	*++A15[1],A7:A6
+ ||	LDDW	.D2T2	*++SP[1],B7:B6
+ ||	MVC	.S2	B10,ILC
+	LDDW	.D1T1	*++A15[1],A9:A8
+ ||	LDDW	.D2T2	*++SP[1],B9:B8
+ ||	MVC	.S2	B13,__rp
+
+	LDDW	.D1T1	*++A15[1],A11:A10
+ ||	LDDW	.D2T2	*++SP[1],B11:B10
+ ||	MVC	.S2	B12,CSR
+	LDDW	.D1T1	*++A15[1],A13:A12
+ ||	LDDW	.D2T2	*++SP[1],B13:B12
+
+	MV	.D2X	A15,SP
+ ||	MVKL	.S1	rt_system_stack_top,A15
+	MVKH	.S1	rt_system_stack_top,A15
+ ||	ADDAW	.D1X	SP,6,A14
+	STW	.D1T1	A14,*A15				; save system stack pointer
+
+ 	LDDW	.D2T1	*++SP[1],A15:A14
+	LDDW	.D2T2	*+SP[1],SP:DP
+	NOP		4
+			.endm
+
+THREAD_SAVE_ALL	.macro  __rp, __tsr
+	STDW	.D2T2	SP:DP,*--SP[1]
+	SUBAW	.D2	SP,2,SP
+
+	ADD	.D1X	SP,-8,A15
+ ||	STDW	.D2T1	A15:A14,*SP--[16]	; save A15:A14
+
+	STDW	.D2T2	B13:B12,*SP--[1]
+ ||	STDW	.D1T1	A13:A12,*A15--[1]
+ ||	MVC	.S2	__rp,B13
+	STDW	.D2T2	B11:B10,*SP--[1]
+ ||	STDW	.D1T1	A11:A10,*A15--[1]
+ ||	MVC	.S2	CSR,B12
+
+	STDW	.D2T2	B9:B8,*SP--[1]
+ ||	STDW	.D1T1	A9:A8,*A15--[1]
+ ||	MVC	.S2	RILC,B11
+	STDW	.D2T2	B7:B6,*SP--[1]
+ ||	STDW	.D1T1	A7:A6,*A15--[1]
+ ||	MVC	.S2	ILC,B10
+	STDW	.D2T2	B5:B4,*SP--[1]
+ ||	STDW	.D1T1	A5:A4,*A15--[1]
+	STDW	.D2T2	B3:B2,*SP--[1]
+ ||	STDW	.D1T1	A3:A2,*A15--[1]
+ ||	MVC	.S2	__tsr,B5
+	STDW	.D2T2	B1:B0,*SP--[1]
+ ||	STDW	.D1T1	A1:A0,*A15--[1]
+ ||	MV	.S1X	B5,A5
+
+	STDW	.D2T2	B31:B30,*SP--[1]
+ ||	STDW	.D1T1	A31:A30,*A15--[1]
+ || MVKL	1,A4
+	STDW	.D2T2	B29:B28,*SP--[1]
+ ||	STDW	.D1T1	A29:A28,*A15--[1]
+	STDW	.D2T2	B27:B26,*SP--[1]
+ ||	STDW	.D1T1	A27:A26,*A15--[1]
+	STDW	.D2T2	B25:B24,*SP--[1]
+ ||	STDW	.D1T1	A25:A24,*A15--[1]
+	STDW	.D2T2	B23:B22,*SP--[1]
+ ||	STDW	.D1T1	A23:A22,*A15--[1]
+	STDW	.D2T2	B21:B20,*SP--[1]
+ ||	STDW	.D1T1	A21:A20,*A15--[1]
+	STDW	.D2T2	B19:B18,*SP--[1]
+ ||	STDW	.D1T1	A19:A18,*A15--[1]
+	STDW	.D2T2	B17:B16,*SP--[1]
+ ||	STDW	.D1T1	A17:A16,*A15--[1]
+
+	STDW	.D2T2	B13:B12,*SP--[1]	; save PC and CSR
+	STDW	.D2T2	B11:B10,*SP--[1]	; save RILC and ILC
+	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and orig A4
+				.endm

libcpu/ti-dsp/c6x/cpuport.c

@@ -27,7 +27,6 @@ RT_WEAK void rt_hw_cpu_shutdown(void)
 
     RT_ASSERT(0);
 }
-//-----------------------------------------------------------------------------
 
 /*------------ nested_exception_handler() function ---------------------------
  * DESCRIPTION: Function handles Nested Exception
@@ -40,8 +39,6 @@ void nested_exception_handler(void)
 {
 	for ( ; ; );
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_nmi_handler() function --------------------------------------
  * DESCRIPTION: Function handles NMI interrupt
@@ -53,8 +50,6 @@ void hw_nmi_handler(struct rt_hw_exp_stack_register *regs)
 {
 	for ( ; ; );
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_bad_handler() function --------------------------------------
  * DESCRIPTION: Function handles Bad interrupt
@@ -66,8 +61,6 @@ void hw_bad_handler(void)
 {
 	for ( ; ; );
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int4_handler() function -------------------------------------
  * DESCRIPTION: Function handles INT4 interrupt
@@ -79,8 +72,6 @@ void hw_int4_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int5_handler() function -------------------------------------
  * DESCRIPTION: Function handles INT5 interrupt
@@ -92,8 +83,6 @@ void hw_int5_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int6_handler() function -------------------------------------
  * DESCRIPTION: Function handles INT6 interrupt
@@ -105,8 +94,6 @@ void hw_int6_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int7_handler() function -------------------------------------
  * DESCRIPTION: Function handles INT7 interrupt
@@ -118,8 +105,6 @@ void hw_int7_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int8_handler() function -------------------------------------
  * DESCRIPTION: Function handles INT8 interrupt
@@ -131,8 +116,6 @@ void hw_int8_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int9_handler() function -------------------------------------
  * DESCRIPTION: Function handles INT9 interrupt
@@ -144,8 +127,6 @@ void hw_int9_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int10_handler() function ------------------------------------
  * DESCRIPTION: Function handles INT10 interrupt
@@ -157,8 +138,6 @@ void hw_int10_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int11_handler() function ------------------------------------
  * DESCRIPTION: Function handles INT11 interrupt
@@ -170,8 +149,6 @@ void hw_int11_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int12_handler() function ------------------------------------
  * DESCRIPTION: Function handles INT12 interrupt
@@ -181,9 +158,8 @@ void hw_int11_handler(void)
 -----------------------------------------------------------------------------*/
 void hw_int12_handler(void)
 {
+	
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int13_handler() function ------------------------------------
  * DESCRIPTION: Function handles INT13 interrupt
@@ -195,8 +171,6 @@ void hw_int13_handler(void)
 {
 
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------------ hw_int14_handler() function ------------------------------
  * DESCRIPTION: Function handles INT14 interrupt
@@ -209,8 +183,6 @@ void hw_int14_handler(void)
 extern void rt_hw_systick_isr();
 	rt_hw_systick_isr();
 }
-//-----------------------------------------------------------------------------
-
 
 /*------------ hw_int15_handler() function ------------------------------------
  * DESCRIPTION: Function handles INT15 interrupt

libcpu/ti-dsp/c6x/interrupt.c

@@ -8,7 +8,6 @@
  * 2021-11-16     Dystopia     the first version
  */
 
-
 #include "c66xx.h"
 #include "interrupt.h"
 

libcpu/ti-dsp/c6x/inct.asm → libcpu/ti-dsp/c6x/intexc.asm

@@ -9,7 +9,7 @@
 ;
 
 ;-----------------------------------------------------------
-; interrupt handler for C6678 DSP
+; interrupt and execption handler for C6678 DSP
 ;-----------------------------------------------------------
 
 ;-----------------------------------------------------------
@@ -20,7 +20,7 @@ SP	.set	B15
 ;
 ;-----------------------------------------------------------
 ;
-
+	.include "contextinc.asm"
 ;-----------------------------------------------------------
 ; 						global function
 ;-----------------------------------------------------------
@@ -65,121 +65,14 @@ SP	.set	B15
 ;-----------------------------------------------------------
 ;
 
-;
 ;-----------------------------------------------------------
-;
-
+; 						extern variable
 ;-----------------------------------------------------------
-; 						macro definition
+	.ref rt_system_stack_top
+;
 ;-----------------------------------------------------------
-SAVE_ALL	.macro  __rp, __tsr
-	STDW	.D2T2	SP:DP,*--SP[1]
-	SUBAW	.D2	SP,2,SP
-	ADD	.D1X	SP,-8,A15
- ||	STDW	.D2T1	A15:A14,*SP--[16]	; save A15:A14
-
-	STDW	.D2T2	B13:B12,*SP--[1]
- ||	STDW	.D1T1	A13:A12,*A15--[1]
- ||	MVC	.S2	__rp,B13
-
-	STDW	.D2T2	B11:B10,*SP--[1]
- ||	STDW	.D1T1	A11:A10,*A15--[1]
- ||	MVC	.S2	CSR,B12
-
-	STDW	.D2T2	B9:B8,*SP--[1]
- ||	STDW	.D1T1	A9:A8,*A15--[1]
- ||	MVC	.S2	RILC,B11
-	STDW	.D2T2	B7:B6,*SP--[1]
- ||	STDW	.D1T1	A7:A6,*A15--[1]
- ||	MVC	.S2	ILC,B10
-
-	STDW	.D2T2	B5:B4,*SP--[1]
- ||	STDW	.D1T1	A5:A4,*A15--[1]
-
-	STDW	.D2T2	B3:B2,*SP--[1]
- ||	STDW	.D1T1	A3:A2,*A15--[1]
- ||	MVC	.S2	__tsr,B5
-
-	STDW	.D2T2	B1:B0,*SP--[1]
- ||	STDW	.D1T1	A1:A0,*A15--[1]
- ||	MV	.S1X	B5,A5
-
-	STDW	.D2T2	B31:B30,*SP--[1]
- ||	STDW	.D1T1	A31:A30,*A15--[1]
- || MVKL	1,A4
-
-	STDW	.D2T2	B29:B28,*SP--[1]
- ||	STDW	.D1T1	A29:A28,*A15--[1]
-	STDW	.D2T2	B27:B26,*SP--[1]
- ||	STDW	.D1T1	A27:A26,*A15--[1]
-	STDW	.D2T2	B25:B24,*SP--[1]
- ||	STDW	.D1T1	A25:A24,*A15--[1]
-	STDW	.D2T2	B23:B22,*SP--[1]
- ||	STDW	.D1T1	A23:A22,*A15--[1]
-	STDW	.D2T2	B21:B20,*SP--[1]
- ||	STDW	.D1T1	A21:A20,*A15--[1]
-	STDW	.D2T2	B19:B18,*SP--[1]
- ||	STDW	.D1T1	A19:A18,*A15--[1]
-	STDW	.D2T2	B17:B16,*SP--[1]
- ||	STDW	.D1T1	A17:A16,*A15--[1]
-
-	STDW	.D2T2	B13:B12,*SP--[1]	; save PC and CSR
-
-	STDW	.D2T2	B11:B10,*SP--[1]	; save RILC and ILC
-	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and orig A4
-			.endm
-
-RESTORE_ALL	.macro  __rp, __tsr
-	LDDW	.D2T2	*++SP[1],B9:B8		; get TSR (B9)
-	LDDW	.D2T2	*++SP[1],B11:B10	; get RILC (B11) and ILC (B10)
-	LDDW	.D2T2	*++SP[1],B13:B12	; get PC (B13) and CSR (B12)
-
-	ADDAW	.D1X	SP,30,A15
-
-	LDDW	.D1T1	*++A15[1],A17:A16
- ||	LDDW	.D2T2	*++SP[1],B17:B16
-	LDDW	.D1T1	*++A15[1],A19:A18
- ||	LDDW	.D2T2	*++SP[1],B19:B18
-	LDDW	.D1T1	*++A15[1],A21:A20
- ||	LDDW	.D2T2	*++SP[1],B21:B20
-	LDDW	.D1T1	*++A15[1],A23:A22
- ||	LDDW	.D2T2	*++SP[1],B23:B22
-	LDDW	.D1T1	*++A15[1],A25:A24
- ||	LDDW	.D2T2	*++SP[1],B25:B24
-	LDDW	.D1T1	*++A15[1],A27:A26
- ||	LDDW	.D2T2	*++SP[1],B27:B26
-	LDDW	.D1T1	*++A15[1],A29:A28
- ||	LDDW	.D2T2	*++SP[1],B29:B28
-	LDDW	.D1T1	*++A15[1],A31:A30
- ||	LDDW	.D2T2	*++SP[1],B31:B30
-
-	LDDW	.D1T1	*++A15[1],A1:A0
- ||	LDDW	.D2T2	*++SP[1],B1:B0
-	LDDW	.D1T1	*++A15[1],A3:A2
- ||	LDDW	.D2T2	*++SP[1],B3:B2
- ||	MVC	.S2	B9,__tsr
-	LDDW	.D1T1	*++A15[1],A5:A4
- ||	LDDW	.D2T2	*++SP[1],B5:B4
- ||	MVC	.S2	B11,RILC
-	LDDW	.D1T1	*++A15[1],A7:A6
- ||	LDDW	.D2T2	*++SP[1],B7:B6
- ||	MVC	.S2	B10,ILC
-	LDDW	.D1T1	*++A15[1],A9:A8
- ||	LDDW	.D2T2	*++SP[1],B9:B8
- ||	MVC	.S2	B13,__rp
-
-	LDDW	.D1T1	*++A15[1],A11:A10
- ||	LDDW	.D2T2	*++SP[1],B11:B10
- ||	MVC	.S2	B12,CSR
-	LDDW	.D1T1	*++A15[1],A13:A12
- ||	LDDW	.D2T2	*++SP[1],B13:B12
+;
 
-	MV	.D2X	A15,SP
- 	LDDW	.D2T1	*++SP[1],A15:A14
-	B	.S2	__rp		; return from interruption
-	LDDW	.D2T2	*+SP[1],SP:DP
-	NOP		4
-			.endm
 ;-----------------------------------------------------------
 ; 				interrupt macro definition
 ;-----------------------------------------------------------
@@ -190,8 +83,8 @@ RT_INTERRUPT_ENTRY	.macro
 RT_CALL_INT .macro __isr
 	CALLP	__isr,B3
 	B	.S1	rt_interrupt_context_restore
-	NOP    	5
-					.endm
+	NOP	5
+			.endm
 ;-----------------------------------------------------------
 ; 				execption macro definition
 ;-----------------------------------------------------------
@@ -201,6 +94,8 @@ RT_EXECPTION_ENTRY	.macro
 
 RT_EXECPTION_EXIT	.macro
 	RESTORE_ALL NRP,NTSR
+	B	.S2	NRP				; return from interruption
+	NOP	5
 					.endm
 
 ;

libcpu/ti-dsp/c6x/stack.asm

@@ -13,7 +13,7 @@
 ;-----------------------------------------------------------
 
 ;-----------------------------------------------------------
-; 						macro definition
+;					macro definition
 ;-----------------------------------------------------------
 ADDRESS_MSK .set    0xFFFFFFF0
 
@@ -22,6 +22,10 @@ ADDRESS_MSK .set    0xFFFFFFF0
 ;
 
     .sect   ".text"
+;
+;-----------------------------------------------------------
+;
+
 ;
 ; rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
 ; tentry  --> A4

libcpu/ti-dsp/c6x/trap.c

@@ -14,8 +14,18 @@
 #include <rthw.h>
 #include <rtthread.h>
 
+#include <rtdef.h>
+
+#define RT_SYS_STACK_SIZE	4096
+
+rt_uint8_t rt_system_stack[RT_SYS_STACK_SIZE];
+rt_uint8_t *rt_system_stack_top;
+
 void rt_trap_init(void)
 {
+	rt_system_stack_top = &rt_system_stack[RT_SYS_STACK_SIZE-1];
+	rt_system_stack_top  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)rt_system_stack_top, 8);
+
 	ack_exception(EXCEPT_TYPE_NXF);
 	ack_exception(EXCEPT_TYPE_EXC);
 	ack_exception(EXCEPT_TYPE_IXF);
@@ -319,7 +329,7 @@ int rt_hw_process_exception(struct rt_hw_exp_stack_register *regs)
 	int ie_num = 9; /* default is unknown exception */
 
 	while ((type = get_except_type()) != 0) {
-		type_num = fls(type) - 1;
+		type_num = __fls(type) - 1;
 
 		switch(type_num) {
 		case EXCEPT_TYPE_NXF:					/* NMI exception   */

libcpu/ti-dsp/c6x/trap.h

@@ -67,8 +67,8 @@ struct rt_exception_info {
 #define BKPT_OPCODE		0x56454314       /* illegal opcode */
 #define INTC_MEXPMASK	__SYSREGA(0x018000e0, unsigned int)
 
-#define __ffs(a)   (_lmbd(1, _bitr(a)))
-#define fls(a)     (!(a) ? 0 : (32 - _lmbd(1, (a))))
+#define __ffs(a)	(_lmbd(1, _bitr(a)))
+#define __fls(a)	(!(a) ? 0 : (32 - _lmbd(1, (a))))
 
 void rt_trap_init(void);
 

libcpu/ti-dsp/c6x/vector.asm

@@ -75,21 +75,21 @@ __name:
 	.align 32
 	.global vector
 vector:
-	VEC_RESET	  _c_int00
-	IRQVEC NMI,   _nmi_handler
-	IRQVEC AINT,  _bad_handler
-	IRQVEC MSGINT,_bad_handler
-	IRQVEC INT4,  _int4_handler
-	IRQVEC INT5,  _int5_handler
-	IRQVEC INT6,  _int6_handler
-	IRQVEC INT7,  _int7_handler
-	IRQVEC INT8,  _int8_handler
-	IRQVEC INT9,  _int9_handler
-	IRQVEC INT10, _int10_handler
-	IRQVEC INT11, _int11_handler
-	IRQVEC INT12, _int12_handler
-	IRQVEC INT13, _int13_handler
-	IRQVEC INT14, _int14_handler
-	IRQVEC INT15, _int15_handler
+	VEC_RESET		_c_int00
+	IRQVEC NMI,		_nmi_handler
+	IRQVEC AINT,	_bad_handler
+	IRQVEC MSGINT,	_bad_handler
+	IRQVEC INT4,	_int4_handler
+	IRQVEC INT5,	_int5_handler
+	IRQVEC INT6,	_int6_handler
+	IRQVEC INT7,	_int7_handler
+	IRQVEC INT8,	_int8_handler
+	IRQVEC INT9,	_int9_handler
+	IRQVEC INT10,	_int10_handler
+	IRQVEC INT11,	_int11_handler
+	IRQVEC INT12,	_int12_handler
+	IRQVEC INT13,	_int13_handler
+	IRQVEC INT14,	_int14_handler
+	IRQVEC INT15,	_int15_handler
 
 	.end