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@@ -1,72 +1,72 @@
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-/*
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- * Copyright (c) 2006-2018, RT-Thread Development Team
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- *
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- * SPDX-License-Identifier: Apache-2.0
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- *
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- * Change Logs:
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- * Date Author Notes
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- * 2018-11-06 SummerGift change to new framework
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- * 2019-1-10 e31207077 change to new framework
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- */
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-
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-#include "board.h"
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-
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-/**
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- * @brief System Clock Configuration
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- * @retval None
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- */
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-void SystemClock_Config(void)
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-{
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- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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-
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- /**Configure LSE Drive Capability
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- */
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- HAL_PWR_EnableBkUpAccess();
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- /**Configure the main internal regulator output voltage
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- */
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- __HAL_RCC_PWR_CLK_ENABLE();
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- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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- /**Initializes the CPU, AHB and APB busses clocks
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- */
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- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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- RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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- RCC_OscInitStruct.PLL.PLLM = 8;
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- RCC_OscInitStruct.PLL.PLLN = 432;
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- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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- RCC_OscInitStruct.PLL.PLLQ = 9;
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- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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- {
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- Error_Handler();
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- }
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- /**Activate the Over-Drive mode
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- */
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- if (HAL_PWREx_EnableOverDrive() != HAL_OK)
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- {
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- Error_Handler();
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- }
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- /**Initializes the CPU, AHB and APB busses clocks
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- */
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- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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-
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- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
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- {
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- Error_Handler();
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- }
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- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_CLK48;
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- PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
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- PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
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- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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- {
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- Error_Handler();
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- }
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-}
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-
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+/*
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+ * Copyright (c) 2006-2018, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2018-11-06 SummerGift first version
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+ * 2019-1-10 e31207077 add stm32f767-st-nucleo bsp
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+ */
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+
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+#include "board.h"
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+
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+/**
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+ * @brief System Clock Configuration
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+ * @retval None
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+ */
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+void SystemClock_Config(void)
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+{
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+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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+
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+ /**Configure LSE Drive Capability
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+ */
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+ HAL_PWR_EnableBkUpAccess();
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+ /**Configure the main internal regulator output voltage
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+ */
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+ __HAL_RCC_PWR_CLK_ENABLE();
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+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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+ /**Initializes the CPU, AHB and APB busses clocks
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+ */
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+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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+ RCC_OscInitStruct.PLL.PLLM = 8;
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+ RCC_OscInitStruct.PLL.PLLN = 432;
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+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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+ RCC_OscInitStruct.PLL.PLLQ = 9;
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+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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+ {
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+ Error_Handler();
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+ }
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+ /**Activate the Over-Drive mode
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+ */
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+ if (HAL_PWREx_EnableOverDrive() != HAL_OK)
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+ {
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+ Error_Handler();
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+ }
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+ /**Initializes the CPU, AHB and APB busses clocks
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+ */
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+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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+
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+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
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+ {
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+ Error_Handler();
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+ }
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+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_CLK48;
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+ PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
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+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
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+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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+ {
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+ Error_Handler();
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+ }
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+}
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+
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