[bsp][core-v-mcu]规范代码格式 添加英文readme_EN (#6718)

Co-authored-by: 1516081466@qq.com <ws051000>

bsp/core-v-mcu/Libraries/core_v_drivers/SConscript

@@ -5,7 +5,6 @@ from building import *
 cwd = GetCurrentDir()
 
 src = Split("""
-source/udma_uart_driver.c
 """)
 
 if  GetDepend('SOC_RISCV_FAMILY_Core_V'):

bsp/core-v-mcu/Libraries/core_v_drivers/include/camera.h

@@ -1,33 +0,0 @@
-#ifndef __CAMERA_H__
-#define __CAMERA_H__
-
-//#include <FreeRTOS.h>
-#include <queue.h>
-#include "himax.h"
-
-
-typedef struct {
-	volatile uint32_t *rx_saddr; // 0x00
-	volatile uint32_t rx_size; 	 // 0x04
-	volatile uint32_t rx_cfg;    // 0x08
-	volatile uint32_t rx_initcfg;// 0x0C
-	volatile uint32_t *tx_saddr; // 0x10
-	volatile uint32_t tx_size;   // 0x14
-	volatile uint32_t tx_cfg;    // 0x18
-	volatile uint32_t tx_initcfg;// 0x1C
-	volatile uint32_t cfg_glob;  // 0x20
-	volatile uint32_t cfg_ll;    // 0x24
-	volatile uint32_t cfg_ur;    // 0x28
-	volatile uint32_t cfg_size;  // 0x2C
-	volatile uint32_t cfg_filter;// 0x30
-	volatile uint32_t vsync_pol; // 0x34
-
-} camera_struct_t;
-
-typedef struct {
-	uint16_t addr;
-	uint8_t data;
-}reg_cfg_t;
-
-
-#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/himax.h

@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2018 ETH Zurich and University of Bologna
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * Copyright (C) 2018 GreenWaves Technologies
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __HIMAX_H__
-#define __HIMAX_H__
-
-/*
- *  HIMAX camera macros
- */
-// Register address
-// Read only registers
-#define         MODEL_ID_H          0x0000
-#define         MODEL_ID_L          0x0001
-#define         FRAME_COUNT         0x0005
-#define         PIXEL_ORDER         0x0006
-// R&W registers
-// Sensor mode control
-#define         MODE_SELECT         0x0100
-#define         IMG_ORIENTATION     0x0101
-#define         SW_RESET            0x0103
-#define         GRP_PARAM_HOLD      0x0104
-// Sensor exposure gain control
-#define         INTEGRATION_H       0x0202
-#define         INTEGRATION_L       0x0203
-#define         ANALOG_GAIN         0x0205
-#define         DIGITAL_GAIN_H      0x020E
-#define         DIGITAL_GAIN_L      0x020F
-// Frame timing control
-#define         FRAME_LEN_LINES_H   0x0340
-#define         FRAME_LEN_LINES_L   0x0341
-#define         LINE_LEN_PCK_H      0x0342
-#define         LINE_LEN_PCK_L      0x0343
-// Binning mode control
-#define         READOUT_X           0x0383
-#define         READOUT_Y           0x0387
-#define         BINNING_MODE        0x0390
-// Test pattern control
-#define         TEST_PATTERN_MODE   0x0601
-// Black level control
-#define         BLC_CFG             0x1000
-#define         BLC_TGT             0x1003
-#define         BLI_EN              0x1006
-#define         BLC2_TGT            0x1007
-//  Sensor reserved
-#define         DPC_CTRL            0x1008
-#define         SINGLE_THR_HOT      0x100B
-#define         SINGLE_THR_COLD     0x100C
-// VSYNC,HSYNC and pixel shift register
-#define         VSYNC_HSYNC_PIXEL_SHIFT_EN  0x1012
-// Automatic exposure gain control
-#define         AE_CTRL             0x2100
-#define         AE_TARGET_MEAN      0x2101
-#define         AE_MIN_MEAN         0x2102
-#define         CONVERGE_IN_TH      0x2103
-#define         CONVERGE_OUT_TH     0x2104
-#define         MAX_INTG_H          0x2105
-#define         MAX_INTG_L          0x2106
-#define         MIN_INTG            0x2107
-#define         MAX_AGAIN_FULL      0x2108
-#define         MAX_AGAIN_BIN2      0x2109
-#define         MIN_AGAIN           0x210A
-#define         MAX_DGAIN           0x210B
-#define         MIN_DGAIN           0x210C
-#define         DAMPING_FACTOR      0x210D
-#define         FS_CTRL             0x210E
-#define         FS_60HZ_H           0x210F
-#define         FS_60HZ_L           0x2110
-#define         FS_50HZ_H           0x2111
-#define         FS_50HZ_L           0x2112
-#define         FS_HYST_TH          0x2113
-// Motion detection control
-#define         MD_CTRL             0x2150
-#define         I2C_CLEAR           0x2153
-#define         WMEAN_DIFF_TH_H     0x2155
-#define         WMEAN_DIFF_TH_M     0x2156
-#define         WMEAN_DIFF_TH_L     0x2157
-#define         MD_THH              0x2158
-#define         MD_THM1             0x2159
-#define         MD_THM2             0x215A
-#define         MD_THL              0x215B
-//  Sensor timing control
-#define         QVGA_WIN_EN         0x3010
-#define         SIX_BIT_MODE_EN     0x3011
-#define         PMU_AUTOSLEEP_FRAMECNT  0x3020
-#define         ADVANCE_VSYNC       0x3022
-#define         ADVANCE_HSYNC       0x3023
-#define         EARLY_GAIN          0x3035
-//  IO and clock control
-#define         BIT_CONTROL         0x3059
-#define         OSC_CLK_DIV         0x3060
-#define         ANA_Register_11     0x3061
-#define         IO_DRIVE_STR        0x3062
-#define         IO_DRIVE_STR2       0x3063
-#define         ANA_Register_14     0x3064
-#define         OUTPUT_PIN_STATUS_CONTROL   0x3065
-#define         ANA_Register_17     0x3067
-#define         PCLK_POLARITY       0x3068
-
-/*
- * Useful value of Himax registers
- */
-#define         HIMAX_RESET         0x01
-#define         Pclk_rising_edge    0x00
-#define         Pclk_falling_edge   0x01
-
-#define         BYPASS_BIGEND       5
-
-enum{
-    HIMAX_Standby = 0x0,
-    HIMAX_Streaming = 0x1,        // I2C triggered streaming enable
-    HIMAX_Streaming2 = 0x3,       // Output N frames
-    HIMAX_Streaming3 = 0x5        // Hardware Trigger
-};
-
-#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_cam_driver.h

@@ -1,61 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
-#define DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "hal_udma_ctrl_reg_defs.h"
-#include "hal_udma_cam_reg_defs.h"
-
-typedef enum {
-		kCamReset,
-		kCamID,
-		kCamInit,
-		kCamFrame
-} udma_cam_control_type_t;
-
-typedef enum {
-	kSPIm_Cfg 	    = (0x0 << 28),
-	kSPIm_SOT	    = (0x1 << 28),
-	kSPIm_SendCmd	= (0x2 << 28),
-	kSPIm_Dummy	    = (0x4 << 28),
-	kSPIm_Wait		= (0x5 << 28),
-	kSPIm_TxData	= (0x6 << 28),
-	kSPIm_RxData  	= (0x7 << 28),
-	kSPIm_Repeat	= (0x8 << 28),
-	kSPIm_EOT		= (0x9 << 28),
-	kSPIm_RepeatEnd = (0xa << 28),
-	kSPIm_RxCheck	= (0xb << 28),
-	kSPIm_FDX 		= (0xc << 28),
-	kSPIm_UCA 		= (0xd << 28),
-	kSPIm_UCS 		= (0xe << 28)
-
-} cam_cmd_t;
-
-
-uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam);
-void cam_open (uint8_t cam_id);
-
-
-// helper functions
-void _himaxRegWrite(unsigned int addr, unsigned char value);
-
-#endif /* DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_i2cm_driver.h

@@ -1,61 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
-#define DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "hal_udma_ctrl_reg_defs.h"
-
-#define SEMAPHORE_WAIT_TIME_IN_MS	10
-
-typedef enum {
-		kI2cmReset
-} udma_i2cm_control_type_t;
-
-typedef enum {
-	kI2cmCmdStart 	= 0x00,
-	kI2cmCmdStop	= 0x20,
-	kI2cmCmdRdAck	= 0x40,
-	kI2cmCmdRdNack	= 0x60,
-	kI2cmCmdWr		= 0x80,
-	kI2cmCmdWait	= 0xA0,
-	kI2cmCmdRpt		= 0xC0,
-	kI2cmCmdCfg		= 0xE0,
-	kI2cmCmdWaitEvt	= 0x10,
-} i2cm_cmd_t;
-
-uint16_t udma_i2cm_open (uint8_t i2c_id, uint32_t i2c_clk_freq);
-uint16_t udma_i2cm_close (uint8_t i2c_id);
-uint16_t udma_i2cm_control(uint8_t i2c_id, udma_i2cm_control_type_t control_type, void* pparam);
-uint8_t udma_i2cm_write(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t write_len, uint8_t* write_data, bool more_follows);
-uint8_t udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
-uint8_t udma_i2cm_16read8(uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
-
-
-
-// helper functions
-uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr);
-uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr);
-uint8_t _udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
-uint8_t _udma_i2cm_send_stop(uint8_t i2c_id);
-
-#endif /* DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_ */
-

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_qspi_driver.h

@@ -1,64 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
-#define DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "hal_udma_ctrl_reg_defs.h"
-
-typedef enum {
-		kQSPImReset
-} udma_qspim_control_type_t;
-
-typedef enum {
-	kSPIm_Cfg 	    = (0x0 << 28),
-	kSPIm_SOT	    = (0x1 << 28),
-	kSPIm_SendCmd	= (0x2 << 28),
-	kSPIm_Dummy	    = (0x4 << 28),
-	kSPIm_Wait		= (0x5 << 28),
-	kSPIm_TxData	= (0x6 << 28),
-	kSPIm_RxData  	= (0x7 << 28),
-	kSPIm_Repeat	= (0x8 << 28),
-	kSPIm_EOT		= (0x9 << 28),
-	kSPIm_RepeatEnd = (0xa << 28),
-	kSPIm_RxCheck	= (0xb << 28),
-	kSPIm_FDX 		= (0xc << 28),
-	kSPIm_UCA 		= (0xd << 28),
-	kSPIm_UCS 		= (0xe << 28)
-
-} spim_cmd_t;
-
-uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t spi_clk_freq);
-uint16_t udma_qspim_close (uint8_t qspim_id);
-uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam);
-void udma_qspim_write(uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
-void udma_qspim_read(uint8_t qspim_id,  uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
-uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd);
-uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs);
-void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
-void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
-uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs);
-uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs);
-
-// helper functions
-
-
-#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_sdio_driver.h

@@ -1,69 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
-#define DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-
-#include "hal_udma_ctrl_reg_defs.h"
-
-typedef enum {
-		kSDIOmReset
-} udma_sdio_control_type_t;
-/*
-typedef enum {
-	kSPIm_Cfg 	    = (0x0 << 28),
-	kSPIm_SOT	    = (0x1 << 28),
-	kSPIm_SendCmd	= (0x2 << 28),
-	kSPIm_Dummy	    = (0x4 << 28),
-	kSPIm_Wait		= (0x5 << 28),
-	kSPIm_TxData	= (0x6 << 28),
-	kSPIm_RxData  	= (0x7 << 28),
-	kSPIm_Repeat	= (0x8 << 28),
-	kSPIm_EOT		= (0x9 << 28),
-	kSPIm_RepeatEnd = (0xa << 28),
-	kSPIm_RxCheck	= (0xb << 28),
-	kSPIm_FDX 		= (0xc << 28),
-	kSPIm_UCA 		= (0xd << 28),
-	kSPIm_UCS 		= (0xe << 28)
-
-} spim_cmd_t;
-*/
-uint16_t udma_sdio_open (uint8_t sdio_id);
-uint16_t udma_sdio_close (uint8_t sdio_id);
-uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam);
-uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf);
-void udma_sdio_write(uint8_t sdio_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
-void udma_sdio_read(uint8_t sdio_id,  uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
-uint8_t udma_flash_erase(uint8_t sdio_id, uint8_t cs, uint32_t addr, uint8_t cmd);
-uint32_t udma_flash_readid(uint8_t sdio_id, uint8_t cs);
-void udma_flash_read(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
-void udma_flash_write(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
-uint32_t udma_flash_reset_enable(uint8_t sdio_id, uint8_t cs);
-uint32_t udma_flash_reset_memory(uint8_t sdio_id, uint8_t cs);
-
-uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
-uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
-void udma_sdio_clearDataSetup(uint8_t sdio_id);
-
-// helper functions
-
-
-#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_cam_driver.c

@@ -1,240 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <drivers/include/camera.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdbool.h>
-//#include "FreeRTOS.h"
-#include "semphr.h"
-
-#include "target/core-v-mcu/include/core-v-mcu-config.h"
-
-#include "hal/include/hal_fc_event.h"
-#include "hal/include/hal_udma_ctrl_reg_defs.h"
-#include "hal/include/hal_udma_cam_reg_defs.h"
-
-#include <drivers/include/udma_cam_driver.h>
-#include <drivers/include/udma_i2cm_driver.h>
-
-#include "drivers/include/himax.h"
-#include "drivers/include/camera.h"
-
-reg_cfg_t himaxRegInit[] = {
-    {BLC_TGT, 0x08},            //  BLC target :8  at 8 bit mode
-    {BLC2_TGT, 0x08},           //  BLI target :8  at 8 bit mode
-    {0x3044, 0x0A},             //  Increase CDS time for settling
-    {0x3045, 0x00},             //  Make symetric for cds_tg and rst_tg
-    {0x3047, 0x0A},             //  Increase CDS time for settling
-    {0x3050, 0xC0},             //  Make negative offset up to 4x
-    {0x3051, 0x42},
-    {0x3052, 0x50},
-    {0x3053, 0x00},
-    {0x3054, 0x03},             //  tuning sf sig clamping as lowest
-    {0x3055, 0xF7},             //  tuning dsun
-    {0x3056, 0xF8},             //  increase adc nonoverlap clk
-    {0x3057, 0x29},             //  increase adc pwr for missing code
-    {0x3058, 0x1F},             //  turn on dsun
-    {0x3059, 0x1E},
-    {0x3064, 0x00},
-    {0x3065, 0x04},             //  pad pull 0
-
-    {BLC_CFG, 0x43},            //  BLC_on, IIR
-
-    {0x1001, 0x43},             //  BLC dithering en
-    {0x1002, 0x43},             //  blc_darkpixel_thd
-    {0x0350, 0x00},             //  Dgain Control
-    {BLI_EN, 0x01},             //  BLI enable
-    {0x1003, 0x00},             //  BLI Target [Def: 0x20]
-
-    {DPC_CTRL, 0x01},           //  DPC option 0: DPC off   1 : mono   3 : bayer1   5 : bayer2
-    {0x1009, 0xA0},             //  cluster hot pixel th
-    {0x100A, 0x60},             //  cluster cold pixel th
-    {SINGLE_THR_HOT, 0x90},     //  single hot pixel th
-    {SINGLE_THR_COLD, 0x40},    //  single cold pixel th
-    {0x1012, 0x00},             //  Sync. shift disable
-    {0x2000, 0x07},
-    {0x2003, 0x00},
-    {0x2004, 0x1C},
-    {0x2007, 0x00},
-    {0x2008, 0x58},
-    {0x200B, 0x00},
-    {0x200C, 0x7A},
-    {0x200F, 0x00},
-    {0x2010, 0xB8},
-    {0x2013, 0x00},
-    {0x2014, 0x58},
-    {0x2017, 0x00},
-    {0x2018, 0x9B},
-
-    {AE_CTRL,        0x01},      //Automatic Exposure Gain Control
-    {AE_TARGET_MEAN, 0x3C},      //AE target mean [Def: 0x3C]
-    {AE_MIN_MEAN,    0x0A},      //AE min target mean [Def: 0x0A]
-
-    {INTEGRATION_H,  0x00},      //Integration H [Def: 0x01]
-    {INTEGRATION_L,  0x60},      //Integration L [Def: 0x08]
-    {ANALOG_GAIN,    0x00},      //Analog Global Gain
-    {DAMPING_FACTOR, 0x20},      //Damping Factor [Def: 0x20]
-    {DIGITAL_GAIN_H, 0x01},      //Digital Gain High [Def: 0x01]
-    {DIGITAL_GAIN_L, 0x00},      //Digital Gain Low [Def: 0x00]
-
-    {0x2103, 0x03},
-
-    {0x2104, 0x05},
-    {0x2105, 0x01},
-
-    {0x2106, 0x54},
-
-    {0x2108, 0x03},
-    {0x2109, 0x04},
-
-    {0x210B, 0xC0},
-    {0x210E, 0x00}, //Flicker Control
-    {0x210F, 0x00},
-    {0x2110, 0x3C},
-    {0x2111, 0x00},
-    {0x2112, 0x32},
-
-    {0x2150, 0x30},
-    {0x0340, 0x02},
-    {0x0341, 0x16},
-    {0x0342, 0x01},
-    {0x0343, 0x78},
-    {0x3010, 0x01},
-    {0x0383, 0x01},
-    {0x0387, 0x01},
-    {0x0390, 0x00},
-    {0x3011, 0x70},
-    {0x3059, 0x02},
-    {0x3060, 0x01},
-//    {0x3060, 0x25}, //Clock gating and clock divisors
-    {0x3068, 0x20}, //PCLK0 polarity
-    {IMG_ORIENTATION, 0x01}, // change the orientation
-    {0x0104, 0x01},
-    {0x0100, 0x01},
-	//{0x0601, 0x11}	//Test pattern walking ones
-	//{0x0601, 0x01}	//Test pattern colour bar
-};
-
-SemaphoreHandle_t  cam_semaphore_rx;
-static uint8_t cam;
-static void camISR() {
-
-}
-void cam_open (uint8_t cam_id)
-{
-	int i = 0;
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-
-	/* Enable reset and enable uart clock */
-	pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
-	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
-	pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
-
-	//psdio_regs->clk_div_b.clk_div = 5;
-	//psdio_regs->clk_div_b.valid = 1;
-	hal_setpinmux(21, 0);
-	hal_setpinmux(22, 0);
-	hal_setpinmux(25, 0);
-	for(i=0; i<8; i++ )
-	{
-		//set pin muxes to sdio functionality
-		 hal_setpinmux(29+i, 0);
-	}
-
-	/* See if already initialized */
-	if (cam_semaphore_rx != NULL ){
-		return;
-	}
-
-	/* Set semaphore */
-	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	cam_semaphore_rx = shSemaphoreHandle;
-
-
-	/* Set handlers. */
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_CAM_RX(cam_id), camISR, cam_semaphore_rx);
-	/* Enable SOC events propagation to FC. */
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_CAM_RX(cam_id));
-
-	/* configure */
-	cam = 0x48; // Himax address
-	udma_cam_control(kCamReset, NULL);
-
-	return;
-}
-uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam) {
-	short retval = 0;
-	uint16_t i;
-	SemaphoreHandle_t shSemaphoreHandle;
-	camera_struct_t *camera;
-	//camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
-	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
-	shSemaphoreHandle = cam_semaphore_rx;
-
-	switch (control_type) {
-	case kCamReset:
-		_himaxRegWrite(SW_RESET, HIMAX_RESET);
-		break;
-	case kCamID:
-		udma_i2cm_16read8(0, cam, MODEL_ID_H, 2, &retval, 0);
-		retval = (retval >> 8) & 0xff | (retval <<8);
-		break;
-	case kCamInit:
-	    for(i=0; i<(sizeof(himaxRegInit)/sizeof(reg_cfg_t)); i++){
-	        _himaxRegWrite(himaxRegInit[i].addr, himaxRegInit[i].data);
-	    }
-	    camera->cfg_ll = 0<<16 | 0;
-	    	camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
-	    	camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
-	    	camera->cfg_size = 324;
-	    	camera->vsync_pol = 1;
-	    	camera->cfg_glob = (0 << 0) | //  framedrop disabled
-	    			(000000 << 1) | // number of frames to drop
-	    			(0 << 7) | // Frame slice disabled
-	    			(004 << 8) | // Format binary 100 = ByPass little endian
-	    			(0000 << 11);  // Shift value ignored in bypass
-
-	    break;
-	case kCamFrame:
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		camera->rx_saddr = pparam;
-		camera->rx_size = (244*324);
-		camera->rx_cfg = 0x12;  // start 16-bit transfers
-    	camera->cfg_glob = camera->cfg_glob |
-    			(1 << 31) ; // enable 1 == go
-
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-    	camera->cfg_glob = camera->cfg_glob &
-    			(0x7fffffff) ; // enable 1 == go
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-	}
-	return retval;
-}
-
-void _himaxRegWrite(unsigned int addr, unsigned char value){
-	uint8_t naddr;
-	uint16_t data;
-	naddr = (addr>>8) & 0xff;
-	data = (value << 8) | (addr & 0xff);
-	udma_i2cm_write (0, cam, naddr, 2, &data, 0);
-   //     i2c_16write8(cam,addr,value);
-}

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_i2cm_driver.c

@@ -1,355 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <stdbool.h>
-//#include "FreeRTOS.h"
-#include "semphr.h"
-
-#include "target/core-v-mcu/include/core-v-mcu-config.h"
-
-#include "hal/include/hal_fc_event.h"
-#include "hal/include/hal_udma_ctrl_reg_defs.h"
-#include "hal/include/hal_udma_i2cm_reg_defs.h"
-
-#include <drivers/include/udma_i2cm_driver.h>
-
-#define  unuse_freertos_in_i2cm
-
-
-SemaphoreHandle_t  i2cm_semaphores_rx[N_I2CM];
-SemaphoreHandle_t  i2cm_semaphores_tx[N_I2CM];
-
-void i2cmTXHandler(void *arg)
-{
-	uint32_t lCounter = 0;
-
-	lCounter++;
-}
-
-void i2cmRXHandler(void *arg)
-{
-	uint32_t lCounter = 0;
-
-	lCounter++;
-}
-
-static uint8_t aucclkdiv[2];
-
-uint16_t udma_i2cm_open (uint8_t i2cm_id, uint32_t clk_freq) {
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-	uint32_t					clk_divisor;
-
-	/* See if already initialized */
-	if (i2cm_semaphores_rx[i2cm_id] != NULL || i2cm_semaphores_tx[i2cm_id] != NULL) {
-		return 1;
-	}
-	/* Enable reset and enable uart clock */
-	pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
-	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
-	pudma_ctrl->reg_cg |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
-
-	/* Set semaphore */
-	#ifndef unuse_freertos_in_i2cm
-	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	i2cm_semaphores_rx[i2cm_id] = shSemaphoreHandle;
-
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	i2cm_semaphores_tx[i2cm_id] = shSemaphoreHandle;
-	#endif
-	/* Set handlers. */
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_RX(i2cm_id), i2cmRXHandler/*NULL*/, i2cm_semaphores_rx[i2cm_id]);
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_TX(i2cm_id), i2cmTXHandler/*NULL*/, i2cm_semaphores_tx[i2cm_id]);
-	/* Enable SOC events propagation to FC. */
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_RX(i2cm_id));
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_TX(i2cm_id));
-
-	/* configure */
-	clk_divisor = 5000000/clk_freq;
-	aucclkdiv[0] = (clk_divisor >> 0) & 0xFF;
-	aucclkdiv[1] = (clk_divisor >> 8) & 0xFF;
-
-	return 0;
-}
-
-uint16_t udma_i2cm_control(uint8_t i2cm_id, udma_i2cm_control_type_t control_type, void* pparam) {
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-
-	switch(control_type) {
-	case kI2cmReset:
-		pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
-		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
-		break;
-	default:
-		configASSERT(0);
-	}
-	return 0;
-}
-
-static uint8_t auccmd_rx[16];
-
-uint8_t udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
-	_udma_i2cm_write_addr_plus_regaddr(i2cm_id, i2cm_addr, reg_addr);
-	return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
-}
-uint8_t udma_i2cm_16read8(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
-	_udma_i2cm_write_addr_plus_reg16addr(i2cm_id, i2cm_addr, reg_addr);
-	return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
-}
-
-static uint8_t auccmd_tx[32];
-uint8_t udma_i2cm_write (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t write_len, uint8_t *write_data,  bool more_follows) {
-	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-	uint8_t*					pcmd = auccmd_tx;
-	uint8_t*					pdata = write_data;
-	SemaphoreHandle_t 			shSemaphoreHandleTx = i2cm_semaphores_tx[i2cm_id];
-	uint8_t lStatus = pdFALSE;
-
-	configASSERT(write_len < 256);
-
-	if( xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE ) // Wait for any prior transmission to complete
-	{
-		*pcmd++ = kI2cmCmdCfg;
-		*pcmd++ = aucclkdiv[1];
-		*pcmd++ = aucclkdiv[0];
-		*pcmd++ = kI2cmCmdStart;			// Put Start transaction on I2C bus
-		*pcmd++ = kI2cmCmdRpt; 				// Set up for several writes: i2cm_CMD_RPT
-		*pcmd++ = (uint8_t)(write_len + 2);	// I@CM_ADDR + REG_ADDR + data
-		*pcmd++ = kI2cmCmdWr; 				// Command to repeat: I2C CMD_WR
-		*pcmd++ = i2cm_addr & 0xfe; 		// Clear R/WRbar bit from i2c device's address to indicate write
-		*pcmd++ = reg_addr;					// Target address for following data
-		for (int i = 0; i != write_len; i++) {
-			*pcmd++ = *pdata++;
-		}
-		pi2cm_regs->tx_saddr = auccmd_tx;
-		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
-		pi2cm_regs->tx_cfg_b.en = 1;
-
-		// Block until UDMA transaction is completed
-		xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS );
-		xSemaphoreGive( shSemaphoreHandleTx );
-
-		if (!more_follows) {
-			_udma_i2cm_send_stop(i2cm_id);
-		}
-		lStatus = pdTRUE;
-	}
-	else
-	{
-		xSemaphoreGive( shSemaphoreHandleTx );
-	}
-	return lStatus;
-}
-
-uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr) {
-	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-	uint8_t*					pcmd = auccmd_tx;
-	uint8_t lStatus = pdFALSE;
-
-	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
-	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-	{
-		pi2cm_regs->tx_cfg_b.en = 0;
-		*pcmd++ = kI2cmCmdCfg;
-		*pcmd++ = aucclkdiv[1];
-		*pcmd++ = aucclkdiv[0];
-		*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
-		*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
-		*pcmd++ = i2cm_addr & 0xfe; 	// Clear R/WRbar bit from i2c device's address to indicate write
-		*pcmd++ = kI2cmCmdWr; 		// I2C CMD_WR
-		pi2cm_regs->tx_saddr = auccmd_tx;
-		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
-		pi2cm_regs->tx_cfg_b.en = 1;
-
-		// Block until UDMA operation is completed
-		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-		{
-			//pi2cm_regs->tx_cfg_b.en = 0;
-			pcmd = auccmd_tx;
-			*pcmd++ = reg_addr;
-			pi2cm_regs->tx_saddr = auccmd_tx;
-			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
-			pi2cm_regs->tx_cfg_b.en = 1;
-
-			// Block until UDMA operation is completed
-			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
-			xSemaphoreGive( shSemaphoreHandle );
-			lStatus = pdTRUE;
-		}
-		else
-		{
-			xSemaphoreGive( shSemaphoreHandle );
-		}
-	}
-	else
-	{
-		xSemaphoreGive( shSemaphoreHandle );
-	}
-	return lStatus;
-}
-uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr) {
-	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-	uint8_t*					pcmd = auccmd_tx;
-	uint8_t lStatus = pdFALSE;
-
-	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
-	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-	{
-		pi2cm_regs->tx_cfg_b.en = 0;
-		*pcmd++ = kI2cmCmdCfg;
-		*pcmd++ = aucclkdiv[1];
-		*pcmd++ = aucclkdiv[0];
-		*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
-		*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
-		*pcmd++ = i2cm_addr & 0xfe; 	// Clear R/WRbar bit from i2c device's address to indicate write
-		*pcmd++ = kI2cmCmdRpt;  // 2 byte register address
-		*pcmd++ = 2;
-		*pcmd++ = kI2cmCmdWr; 		// I2C CMD_WR
-		pi2cm_regs->tx_saddr = auccmd_tx;
-		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
-		pi2cm_regs->tx_cfg_b.en = 1;
-
-		// Block until UDMA operation is completed
-		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-		{
-			//pi2cm_regs->tx_cfg_b.en = 0;
-			pcmd = auccmd_tx;
-			*pcmd++ = reg_addr & 0xff;
-			*pcmd++ = (reg_addr >> 8) & 0xff;
-			pi2cm_regs->tx_saddr = auccmd_tx;
-			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
-			pi2cm_regs->tx_cfg_b.en = 1;
-
-			// Block until UDMA operation is completed
-			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
-			xSemaphoreGive( shSemaphoreHandle );
-
-			lStatus = pdTRUE;
-		}
-		else
-		{
-			xSemaphoreGive( shSemaphoreHandle );
-		}
-	}
-	else
-	{
-		xSemaphoreGive( shSemaphoreHandle );
-	}
-	return lStatus;
-}
-
-
-uint8_t _udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
-	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-	uint8_t*					pcmd = auccmd_rx;
-	uint8_t lStatus = pdFALSE;
-
-	configASSERT(read_len < 256);
-
-	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
-	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-	{
-		shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
-		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-		{
-			pi2cm_regs->tx_cfg_b.en = 0;
-			*pcmd++ = kI2cmCmdCfg;
-			*pcmd++ = aucclkdiv[1];
-			*pcmd++ = aucclkdiv[0];
-			*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
-			*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
-			*pcmd++ = i2cm_addr | 0x01;	// Device's address with read bit set
-			if (read_len > 1) {				// Do len-1 reads with ACK, and follow by 1 read with NACK
-				*pcmd++ = kI2cmCmdRpt;		// Tell controller to repeat the following command
-				*pcmd++ = (uint8_t)(read_len - 1);		// len-1 times
-				*pcmd++ = kI2cmCmdRdAck;		// command to repeat is read with ack
-			}
-			*pcmd++ = kI2cmCmdRdNack;	// Read last byte with NACK to indicate the end of the read
-
-			//
-			pi2cm_regs->rx_saddr = read_buffer;
-			pi2cm_regs->rx_size = read_len;
-			pi2cm_regs->rx_cfg_b.en = 1;
-
-			pi2cm_regs->tx_saddr = auccmd_rx;
-			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_rx);
-			pi2cm_regs->tx_cfg_b.en = 1;
-
-			// Block until UDMA operation is complete
-			shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
-			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
-			xSemaphoreGive( shSemaphoreHandle );
-
-			shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
-
-			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
-			xSemaphoreGive( shSemaphoreHandle );
-
-			if (!more_follows) {
-				_udma_i2cm_send_stop(i2cm_id);
-			}
-			lStatus = pdTRUE;
-		}
-		else
-		{
-			xSemaphoreGive( shSemaphoreHandle );
-			lStatus = pdFALSE;
-		}
-	}
-	else
-	{
-		xSemaphoreGive( shSemaphoreHandle );
-		lStatus = pdFALSE;
-	}
-	return lStatus;
-}
-
-static uint8_t auci2cm_stop_seq[] = {
-		kI2cmCmdStop,	kI2cmCmdWait, 0x0
-};
-
-uint8_t _udma_i2cm_send_stop(uint8_t i2cm_id) {
-	UdmaI2cm_t*			pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
-	SemaphoreHandle_t 	shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
-	uint8_t lStatus = pdFALSE;
-
-	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
-	{
-		pi2cm_regs->tx_saddr = auci2cm_stop_seq;
-		pi2cm_regs->tx_size = sizeof(auci2cm_stop_seq);
-		pi2cm_regs->tx_cfg_b.en = 1;
-
-		// Block until UDMA transaction is completed
-		xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
-		xSemaphoreGive( shSemaphoreHandle );
-		lStatus = pdTRUE;
-	}
-	else
-	{
-		xSemaphoreGive( shSemaphoreHandle );
-	}
-	return lStatus;
-}

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_qspi_driver.c

@@ -1,686 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <stdbool.h>
-//#include "FreeRTOS.h"
-#include "semphr.h"
-
-#include "target/core-v-mcu/include/core-v-mcu-config.h"
-#include "hal/include/hal_fc_event.h"
-#include "hal/include/hal_udma_ctrl_reg_defs.h"
-#include "hal/include/hal_udma_qspi_reg_defs.h"
-#include <drivers/include/udma_qspi_driver.h>
-
-
-
-
-SemaphoreHandle_t  qspim_semaphores_rx[N_QSPIM];
-SemaphoreHandle_t  qspim_semaphores_tx[N_QSPIM];
-SemaphoreHandle_t  qspim_semaphores_cmd[N_QSPIM];
-SemaphoreHandle_t  qspim_semaphores_eot[N_QSPIM];
-
-uint8_t aucclkdiv;
-static unsigned int isr_count;
-void spi_tx_isr() {
-	isr_count += 0x1;
-}
-void spi_rx_isr() {
-	isr_count += 0x100;
-}
-void spi_cmd_isr() {
-	isr_count += 0x10000;
-}
-void spi_eot_isr() {
-	isr_count += 0x1000000;
-}
-
-uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t clk_freq) {
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-	UdmaQspi_t*					pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t					clk_divisor;
-
-	/* See if already initialized */
-	if (qspim_semaphores_rx[qspim_id] != NULL || qspim_semaphores_tx[qspim_id] != NULL) {
-		return 1;
-	}
-	/* Enable reset and enable uart clock */
-	if( qspim_id == 0 )
-	{
-		pudma_ctrl->reg_rst |= ( UDMA_CTRL_QSPIM0_CLKEN ) ;
-		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM0_CLKEN);
-		pudma_ctrl->reg_cg |= (UDMA_CTRL_QSPIM0_CLKEN );
-	}
-	else if( qspim_id == 1 )
-	{
-#if(NEW_BIT_FILE == 1 )
-		pudma_ctrl->reg_rst |= ( UDMA_CTRL_QSPIM1_CLKEN ) ;
-		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM1_CLKEN);
-		pudma_ctrl->reg_cg |= (UDMA_CTRL_QSPIM1_CLKEN );
-#endif
-	}
-
-
-	/* Set semaphore */
-	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	qspim_semaphores_rx[qspim_id] = shSemaphoreHandle;
-
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	qspim_semaphores_tx[qspim_id] = shSemaphoreHandle;
-
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	qspim_semaphores_cmd[qspim_id] = shSemaphoreHandle;
-
-	shSemaphoreHandle = xSemaphoreCreateBinary();
-	configASSERT(shSemaphoreHandle);
-	xSemaphoreGive(shSemaphoreHandle);
-	qspim_semaphores_eot[qspim_id] = shSemaphoreHandle;
-
-	/* Set handlers. */
-	isr_count = 0;
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_RX(qspim_id), spi_rx_isr, qspim_semaphores_rx[qspim_id]);
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_TX(qspim_id), spi_tx_isr, qspim_semaphores_tx[qspim_id]);
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_CMD(qspim_id), spi_cmd_isr, qspim_semaphores_cmd[qspim_id]);
-	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_EOT(qspim_id), spi_eot_isr, qspim_semaphores_eot[qspim_id]);
-
-	/* Enable SOC events propagation to FC. */
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_RX(qspim_id));
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_TX(qspim_id));
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_CMD(qspim_id));
-	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_EOT(qspim_id));
-
-	/* configure */
-	aucclkdiv = 5000000/clk_freq;
-
-	return 0;
-}
-
-uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam) {
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-	UdmaQspi_t*					pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-
-	switch(control_type) {
-	case kQSPImReset:
-		if( qspim_id == 0 )
-		{
-			pudma_ctrl->reg_rst |= (UDMA_CTRL_QSPIM0_CLKEN);
-			pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM0_CLKEN);
-		}
-		else if( qspim_id == 1 )
-		{
-#if(NEW_BIT_FILE == 1 )
-			pudma_ctrl->reg_rst |= (UDMA_CTRL_QSPIM1_CLKEN);
-			pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM1_CLKEN);
-#endif
-		}
-		break;
-	default:
-		configASSERT(0);
-	}
-	return 0;
-}
-
-static uint32_t auccmd[16];
-
-void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-
-		configASSERT(read_len < 256);
-
-		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;  //cs 1
-		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->rx_saddr = read_buffer;
-		pqspim_regs->rx_size = read_len;
-		pqspim_regs->rx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-		// Block until UDMA operation is complete
-		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-}
-
-
-void udma_qspim_write (uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t *write_data) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	uint32_t tmp_size;
-		configASSERT(write_len < 256);
-
-		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.clr = 1;
-		pqspim_regs->tx_cfg_b.clr = 1;
-		pqspim_regs->cmd_cfg_b.clr = 1;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_TxData | 0x0470000 | write_len -1;
-		*pcmd++ = kSPIm_EOT | 1; // generate event
-
-
-		pqspim_regs->tx_saddr = write_data;
-		pqspim_regs->tx_size = write_len;
-		pqspim_regs->tx_cfg_b.datasize = 2;
-		pqspim_regs->tx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-
-
-
-
-		// Block until UDMA operation is complete
-		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-}
-
-uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs)
-{
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	uint32_t result = 0;
-
-	udma_qspim_control(qspim_id, (udma_qspim_control_type_t) kQSPImReset , (void*) 0);
-
-	pqspim_regs->cmd_cfg_b.en = 0;
-
-	pqspim_regs->cmd_cfg_b.clr = 1;
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70066); // reset enable command
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	return result;
-}
-
-uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs)
-{
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	uint32_t result = 0;
-
-	udma_qspim_control(qspim_id, (udma_qspim_control_type_t) kQSPImReset , (void*) 0);
-
-	pqspim_regs->cmd_cfg_b.en = 0;
-
-	pqspim_regs->cmd_cfg_b.clr = 1;
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70099); // reset memory command
-
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	return result;
-}
-
-static uint8_t rx_data[16];
-uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	uint32_t result = 0;
-
-	pqspim_regs->rx_cfg_b.en = 0;
-	pqspim_regs->tx_cfg_b.en = 0;
-	pqspim_regs->cmd_cfg_b.en = 0;
-
-	pqspim_regs->rx_cfg_b.clr = 1;
-	pqspim_regs->tx_cfg_b.clr = 1;
-	pqspim_regs->cmd_cfg_b.clr = 1;
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x7009f); // readid command
-	*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->rx_saddr = &rx_data;
-	pqspim_regs->rx_size = 4;
-	pqspim_regs->rx_cfg_b.en = 1;
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	while (pqspim_regs->rx_size != 0) {}
-
-	result = *(uint32_t *) rx_data;
-	return result;
-}
-
-uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	union { uint32_t w; uint8_t b[4]; } result;
-	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-    switch (cmd) {
-    case 0: cmd = 0x20;break;  // subsector (4k erase)
-    case 1: cmd = 0xd8;break; // sector erase (64K)
-    case 2: cmd == 0xc7;break; // bulk erase
-    default: configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-    	return 0xff;
-
-    }
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_SendCmd | (0x70006) ; // write enable command
-//		*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-//		pqspim_regs->rx_saddr = &result.w;
-//		pqspim_regs->rx_size = 0;
-//		pqspim_regs->rx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-		pcmd = auccmd;
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_SendCmd | (0x70000) | cmd; // write enable command
-		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((addr >> 8) & 0xffff);
-		*pcmd++ = kSPIm_SendCmd | (0x70000) | (addr & 0xff);
-//		*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		result.b[0] = 0;
-		while ((result.b[0] & 0x80) == 0x0) {
-
-			pqspim_regs->rx_cfg_b.en = 0;
-			pqspim_regs->tx_cfg_b.en = 0;
-			pqspim_regs->cmd_cfg_b.en = 0;
-			pcmd = auccmd;
-			*pcmd++ = kSPIm_Cfg | aucclkdiv;
-			*pcmd++ = kSPIm_SOT | cs;
-			*pcmd++ = kSPIm_SendCmd | (0x70070); // read flag register
-			*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
-			*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-			pqspim_regs->rx_saddr = &result.w;
-			pqspim_regs->rx_size = 4;
-			pqspim_regs->rx_cfg_b.en = 1;
-
-			pqspim_regs->cmd_saddr = auccmd;
-			pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-			pqspim_regs->cmd_cfg_b.en = 1;
-			configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		}
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-		pcmd = auccmd;
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_SendCmd | (0x70004); // write disable
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-		return result.b[0];
-}
-
-void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-
-	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-	shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT;
-		*pcmd++ = kSPIm_SendCmd | (0x70003);  // read command
-		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((flash_addr >> 8) & 0xffff);
-		*pcmd++ = kSPIm_SendCmd | (0x70000) | (flash_addr & 0xff);
-		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->rx_saddr = l2addr;
-		pqspim_regs->rx_size = read_len;
-		pqspim_regs->rx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-
-}
-void udma_flash_read_quad(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-
-	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-	shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT;
-		//*pcmd++ = kSPIm_SendCmd | (0x7000B);  // read command
-		*pcmd++ = kSPIm_SendCmd | (0x7006B);
-		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((flash_addr >> 8) & 0xffff);
-		*pcmd++ = kSPIm_SendCmd | (0x70000) | (flash_addr & 0xff);
-		//*pcmd++ = kSPIm_Dummy | 0x001F0000;
-		*pcmd++ = kSPIm_Dummy | 0x00070000;
-		//*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_RxData | (0x08470000 | (read_len-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->rx_saddr = l2addr;
-		pqspim_regs->rx_size = read_len;
-		pqspim_regs->rx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-
-}
-void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,
-		uint8_t *l2addr, uint16_t write_len ) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-
-	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-	shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-	pqspim_regs->rx_cfg_b.en = 0;
-	pqspim_regs->tx_cfg_b.en = 0;
-	pqspim_regs->cmd_cfg_b.en = 0;
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70006) ; // write enable command
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		pcmd = auccmd;
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT;
-		*pcmd++ = kSPIm_SendCmd | (0x70002);  // program command
-		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((flash_addr >> 8) & 0xffff);
-		*pcmd++ = kSPIm_SendCmd | (0x70000) | (flash_addr & 0xff);
-		*pcmd++ = kSPIm_TxData | (0x00470000 | (write_len-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->tx_saddr = l2addr;
-		pqspim_regs->tx_size = write_len;
-		pqspim_regs->tx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-
-		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-uint8_t test;
-		test = 1;
-				while ((test & 0x3) == 0x1) {
-
-					pqspim_regs->rx_cfg_b.en = 0;
-					pqspim_regs->tx_cfg_b.en = 0;
-					pqspim_regs->cmd_cfg_b.en = 0;
-					pcmd = auccmd;
-					*pcmd++ = kSPIm_Cfg | aucclkdiv;
-					*pcmd++ = kSPIm_SOT | cs;
-					*pcmd++ = kSPIm_SendCmd | (0x70005); // read status register
-					*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
-					*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-					pqspim_regs->rx_saddr = l2addr;
-					pqspim_regs->rx_size = 4;
-					pqspim_regs->rx_cfg_b.en = 1;
-
-					pqspim_regs->cmd_saddr = auccmd;
-					pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-					pqspim_regs->cmd_cfg_b.en = 1;
-					configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-					test = l2addr[0] & 0xff;
-				}
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		pcmd = auccmd;
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_SendCmd | (0x70004) ; // write disable command
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-}
-
-/*
- * https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/QSPI-flash-programming-how-to-activate-qspi-in-quad-mode/td-p/871253
- * to enable the quad mode
-1. send ENTER QUAD INPUT/OUTPUT MODE command 0x35h
-2. send write enable cmd 0x06
-3. to write into enhanced volatile configuration register - send  0x61 command.
-4. 0x7F is written in the above register to activate in quad mode
-5. poll the configuration register i.e read the enhanced volatile config register command is 0x65 and wait untill it
-becomes 0X7F
-6. then configure the controller in quad mode and send the multiple read id code 0XAF to read the ID code on all the four lines.
- */
-void udma_flash_enterQuadIOMode(uint8_t qspim_id, uint8_t cs )
-{
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	uint8_t test = 0;
-	uint8_t l2addr[4] = {0};
-
-	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	//shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-	//configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-	shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-	pqspim_regs->rx_cfg_b.en = 0;
-	pqspim_regs->tx_cfg_b.en = 0;
-	pqspim_regs->cmd_cfg_b.en = 0;
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70035) ; // Enter QUAD command
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70006) ; // write enable command
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70061) ; // write Enhanced volatile register 0x61
-	*pcmd++ = kSPIm_SendCmd | (0x7007F) ;
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-	while ((test & 0xFF) != 0x7F) {
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-		pcmd = auccmd;
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_SendCmd | (0x70065); // read status register
-		*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->rx_saddr = l2addr;
-		pqspim_regs->rx_size = 4;
-		pqspim_regs->rx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		test = l2addr[0] & 0xff;
-	}
-	pqspim_regs->rx_cfg_b.en = 0;
-	pqspim_regs->tx_cfg_b.en = 0;
-	pqspim_regs->cmd_cfg_b.en = 0;
-
-	pcmd = auccmd;
-	*pcmd++ = kSPIm_Cfg | aucclkdiv;
-	*pcmd++ = kSPIm_SOT | cs;
-	*pcmd++ = kSPIm_SendCmd | (0x70004) ; // write disable command
-	*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-	pqspim_regs->cmd_saddr = auccmd;
-	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-	pqspim_regs->cmd_cfg_b.en = 1;
-
-	shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-	configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
-}
-

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_sdio_driver.c

@@ -1,266 +0,0 @@
-/*
- * Copyright 2021 QuickLogic
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <stdbool.h>
-//#include "FreeRTOS.h"
-#include "semphr.h"
-
-#include "target/core-v-mcu/include/core-v-mcu-config.h"
-#include "hal/include/hal_fc_event.h"
-#include "hal/include/hal_udma_ctrl_reg_defs.h"
-#include "hal/include/hal_udma_sdio_reg_defs.h"
-#include <drivers/include/udma_sdio_driver.h>
-
-#define BLOCK_SIZE 512
-
-uint16_t udma_sdio_open (uint8_t sdio_id)
-{
-	int i = 0;
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-	UdmaSdio_t*					psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
-
-	/* Enable reset and enable uart clock */
-	pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
-	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
-	pudma_ctrl->reg_cg |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
-
-	psdio_regs->clk_div_b.clk_div = 7;//5;
-	psdio_regs->clk_div_b.valid = 1;
-	//Restore pin muxes
-	for(i=0; i<6; i++ )
-	{
-		//set pin muxes to sdio functionality
-		 hal_setpinmux(37+i, 0);
-	}
-	return 0;
-}
-
-uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam) {
-	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
-	UdmaSdio_t*					psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
-
-	switch(control_type) {
-	case kSDIOmReset:
-		pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
-		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
-		break;
-	default:
-		configASSERT(0);
-	}
-	return 0;
-}
-
-void udma_sdio_clearDataSetup(uint8_t sdio_id)
-{
-	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
-	psdio_regs->data_setup = 0x00000000;
-}
-uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
-{
-	uint8_t lSts = 0;
-	uint32_t lData = 0;
-	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
-
-	psdio_regs->tx_cfg_b.clr = 1;
-	psdio_regs->tx_cfg_b.en = 0;
-	psdio_regs->tx_cfg_b.datasize = 2;
-
-	psdio_regs->tx_saddr = aBuf;
-	psdio_regs->tx_size = aBufLen;
-
-	lData = 0;
-	psdio_regs->data_setup = 0x00000000;
-	lData |= 1 << 0;	//Data Enable - Enable data transfer for current command
-	lData |= 0 << 1;	//RWN: Set transfer direction 1 read; 0 write
-	lData |= 1 << 2;	//QUAD mode: Use quad mode.
-	lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
-	lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
-
-	psdio_regs->data_setup = lData;
-
-	psdio_regs->tx_cfg_b.en = 1;
-}
-
-uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
-{
-	uint8_t lSts = 0;
-	uint32_t lData = 0;
-	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
-
-	psdio_regs->rx_cfg_b.clr = 1;
-	psdio_regs->rx_cfg_b.en = 0;
-	psdio_regs->rx_cfg_b.datasize = 2;
-
-	psdio_regs->rx_saddr = aBuf;
-	psdio_regs->rx_size = aBufLen;
-
-	lData = 0;
-	psdio_regs->data_setup = 0x00000000;
-	lData |= 1 << 0;	//Data Enable - Enable data transfer for current command
-	lData |= 1 << 1;	//RWN: Set transfer direction 1 read; 0 write
-	lData |= 1 << 2;	//QUAD mode: Use quad mode.
-	lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
-	lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
-
-	psdio_regs->data_setup = lData;
-
-	psdio_regs->rx_cfg_b.en = 1;
-
-}
-
-uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf)
-{
-	uint8_t lSts = 0;
-	uint32_t lData = 0;
-	uint32_t lLoopCounter = 0;
-	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
-
-	lData |= (aRspType & REG_CMD_OP_CMD_RSP_TYPE_MASK ) << REG_CMD_OP_CMD_RSP_TYPE_LSB;
-	lData |= ( aCmdOpCode & REG_CMD_OP_CMD_OP_MASK ) << REG_CMD_OP_CMD_OP_LSB;
-	psdio_regs->cmd_op = lData;
-
-	//psdio_regs->cmd_op_b.cmd_op = ( aCmdOpCode & 0x3F );
-	//psdio_regs->cmd_op_b.cmd_rsp_type = ( aRspType & 0x07 );
-	psdio_regs->cmd_arg = aCmdArgument;
-
-	psdio_regs->start = 1;
-
-	while( ( ( psdio_regs->status & ( REG_STATUS_EOT_MASK << REG_STATUS_EOT_LSB ) ) >> REG_STATUS_EOT_LSB ) == 0 )
-	{
-		if( ( ( psdio_regs->status & ( REG_STATUS_ERROR_MASK << REG_STATUS_ERROR_LSB ) ) >> REG_STATUS_ERROR_LSB ) == 1 )
-		{
-			lSts = (psdio_regs->status & ( REG_STATUS_CMD_ERR_STATUS_MASK << REG_STATUS_CMD_ERR_STATUS_LSB ) ) >> REG_STATUS_CMD_ERR_STATUS_LSB;
-			break;
-		}
-		else
-		{
-			if(++lLoopCounter >= 0x00010000 )
-			{
-				lSts = 5;
-				break;
-			}
-		}
-	}
-
-	psdio_regs->status_b.eot = 1;	//Write 1 to EOT bit to clear it.
-
-
-	if( aResponseBuf )
-	{
-		aResponseBuf[0] = psdio_regs->rsp0;
-		aResponseBuf[1] = psdio_regs->rsp1;
-		aResponseBuf[2] = psdio_regs->rsp2;
-		aResponseBuf[3] = psdio_regs->rsp3;
-
-	}
-	return lSts;
-}
-#if 0
-static uint32_t auccmd[16];
-
-void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-
-		configASSERT(read_len < 256);
-
-		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.en = 0;
-		pqspim_regs->tx_cfg_b.en = 0;
-		pqspim_regs->cmd_cfg_b.en = 0;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;  //cs 1
-		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
-		*pcmd++ = kSPIm_EOT  | 1; // generate event
-
-		pqspim_regs->rx_saddr = read_buffer;
-		pqspim_regs->rx_size = read_len;
-		pqspim_regs->rx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-		// Block until UDMA operation is complete
-		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-}
-
-
-void udma_qspim_write (uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t *write_data) {
-	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
-	uint32_t*	pcmd = auccmd;
-	uint32_t tmp_size;
-		configASSERT(write_len < 256);
-
-		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-
-		pqspim_regs->rx_cfg_b.clr = 1;
-		pqspim_regs->tx_cfg_b.clr = 1;
-		pqspim_regs->cmd_cfg_b.clr = 1;
-
-		*pcmd++ = kSPIm_Cfg | aucclkdiv;
-		*pcmd++ = kSPIm_SOT | cs;
-		*pcmd++ = kSPIm_TxData | 0x0470000 | write_len -1;
-		*pcmd++ = kSPIm_EOT | 1; // generate event
-
-
-		pqspim_regs->tx_saddr = write_data;
-		pqspim_regs->tx_size = write_len-1;
-		pqspim_regs->tx_cfg_b.datasize = 2;
-		pqspim_regs->tx_cfg_b.en = 1;
-
-		pqspim_regs->cmd_saddr = auccmd;
-		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
-		pqspim_regs->cmd_cfg_b.en = 1;
-
-
-
-
-
-		// Block until UDMA operation is complete
-		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
-		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-}
-
-#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript

@@ -20,11 +20,13 @@ core_v_hal/source/hal_timer_irq.c
 bmsis/core-v-mcu/source/core-v-mcu.c
 bmsis/core-v-mcu/source/crt0.S
 bmsis/core-v-mcu/source/vectors.S
+core_v_udma_driver/source/udma_uart_driver.c
 """)
 
 path = [
 	cwd + '/bmsis/core-v-mcu/include',
-    cwd + '/core_v_hal/include']
+    cwd + '/core_v_hal/include',
+    cwd + '/core_v_udma_driver/include']
 
 group = DefineGroup('core_v_hal_lib', src, depend = [''], CPPPATH = path)
 

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-events.h

@@ -16,9 +16,6 @@
 
 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
-
-
-
 #include "core-v-mcu-properties.h"
 
 /* Events offsets. */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-memory-map.h

@@ -123,5 +123,4 @@
 #define UDMA_I2S(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_I2S_ID(id) << UDMA_PERIPH_SIZE_LOG2))
 #define UDMA_CPI(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_CPI_ID(id) << UDMA_PERIPH_SIZE_LOG2))
 
-
 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h

@@ -19,11 +19,6 @@
 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
 
-
-//#include "pmsis/rtos/os_frontend_api/os.h"
-//#include "pmsis/backend/implementation_specific_defines.h"
-//#include "pmsis/backend/pmsis_backend_native_task_api.h"
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -36,153 +31,4 @@
  * API implementation
  ******************************************************************************/
 
-//static inline int pmsis_kickoff(void *arg)
-//{
-//    return __os_native_kickoff(arg);
-//}
-
-//static inline void pmsis_exit(int err)
-//{
-//    __os_native_exit(err);
-//}
-
-//static inline void *pmsis_task_create(void (*entry)(void*),
-//        void *arg,
-//        char *name,
-//        int priority)
-//{
-//    return __os_native_api_create_task(entry, arg, name, priority);
-//}
-
-//static inline void pmsis_task_suspend(void *task_handler)
-//{
-//    __os_native_task_t *task = (__os_native_task_t *) task_handler;
-//    __os_native_task_suspend(task);
-//}
-
-//static inline void pi_yield()
-//{
-//    __os_native_yield();
-//}
-
-//static inline int disable_irq(void)
-//{
-//    hal_compiler_barrier();
-//    return __os_native_api_disable_irq();
-//}
-
-//static inline void restore_irq(int irq_enable)
-//{
-//    hal_compiler_barrier();
-//    __os_native_api_restore_irq(irq_enable);
-//}
-//
-//static inline int pi_sem_init(pi_sem_t *sem)
-//{
-//    hal_compiler_barrier();
-//    return  __os_native_api_sem_init(sem);
-//}
-//
-//static inline int pi_sem_deinit(pi_sem_t *sem)
-//{
-//    hal_compiler_barrier();
-//    return  __os_native_api_sem_deinit(sem);
-//}
-//
-//static inline void pi_sem_take(pi_sem_t *sem)
-//{
-//    hal_compiler_barrier();
-//    sem->take(sem->sem_object);
-//}
-//
-//static inline void pi_sem_give(pi_sem_t *sem)
-//{
-//    sem->give(sem->sem_object);
-//    hal_compiler_barrier();
-//}
-
-//static inline void pmsis_mutex_take(pmsis_mutex_t *mutex)
-//{
-//    hal_compiler_barrier();
-//#ifdef __NO_NATIVE_MUTEX__
-//    int irq_enabled;
-//    volatile int mutex_free=0;
-//    while (!mutex_free)
-//    {
-//        irq_enabled = disable_irq();
-//        hal_compiler_barrier();
-//        mutex_free = !((volatile uint32_t)mutex->mutex_object);
-//        hal_compiler_barrier();
-//        restore_irq(irq_enabled);
-//    }
-//    irq_enabled = disable_irq();
-//    mutex->mutex_object = (void*)1;
-//    restore_irq(irq_enabled);
-//#else
-//    mutex->take(mutex->mutex_object);
-//#endif
-//}
-//
-//static inline void pmsis_mutex_release(pmsis_mutex_t *mutex)
-//{
-//    hal_compiler_barrier();
-//#ifdef __NO_NATIVE_MUTEX__
-//    int irq_enabled = disable_irq();
-//    hal_compiler_barrier();
-//    mutex->mutex_object = (void*)0;
-//    hal_compiler_barrier();
-//    restore_irq(irq_enabled);
-//#else
-//    mutex->release(mutex->mutex_object);
-//    hal_compiler_barrier();
-//#endif
-//}
-//
-//static inline int pmsis_mutex_init(pmsis_mutex_t *mutex)
-//{
-//    hal_compiler_barrier();
-//#ifdef __NO_NATIVE_MUTEX__
-//    mutex->mutex_object = (void*)0;
-//    return 0;
-//#else
-//    return  __os_native_api_mutex_init(mutex);
-//#endif
-//}
-//
-//static inline int pmsis_mutex_deinit(pmsis_mutex_t *mutex)
-//{
-//    hal_compiler_barrier();
-//#ifdef __NO_NATIVE_MUTEX__
-//    mutex->mutex_object = (void*)0;
-//    return 0;
-//#else
-//    return  __os_native_api_mutex_deinit(mutex);
-//#endif
-//}
-//
-//static inline void pmsis_spinlock_init(pmsis_spinlock_t *spinlock)
-//{
-//    hal_compiler_barrier();
-//    spinlock->lock = 0;
-//}
-//
-//static inline void pmsis_spinlock_take(pmsis_spinlock_t *spinlock)
-//{
-//    int irq_enabled = disable_irq();
-//    hal_compiler_barrier();
-//    spinlock->lock = 1;
-//    hal_compiler_barrier();
-//    restore_irq(irq_enabled);
-//}
-//
-//static inline void pmsis_spinlock_release(pmsis_spinlock_t *spinlock)
-//{
-//    int irq_enabled = disable_irq();
-//    hal_compiler_barrier();
-//    spinlock->lock = 0;
-//    hal_compiler_barrier();
-//    restore_irq(irq_enabled);
-//}
-
-
 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis.h

@@ -33,36 +33,15 @@
 
 #if (!defined(HW_VERIF_ONLY))
 
-/* Backend includes. */
-//#include "pmsis/backend/implementation_specific_defines.h"
-//#include "hal/include/hal_target.h"
-/* pmsis_api includes. */
-//#include "pmsis/device.h"
-//#include "pmsis/task.h"
-//#include "pmsis_types.h"
-//#include "../../../pmsis_api/include/pmsis/rtos/rtos-orig.h"
-//#include "pmsis/rtos/assert.h"
-//#include "pmsis/mem_slab.h"
+#include "hal_fc_event.h"
+#include "hal_fll_pi.h"
+#include "hal_i2c_internal.h"
+#include "hal_uart_internal.h"
 
-/* PMSIS includes. */
-//#include "pmsis/implem/debug.h"
-//#include "pmsis/implem/drivers/drivers_data.h"
-//#include "hal/include/hal_pmsis_drivers.h"
-	#include "hal_fc_event.h"
-	#include "hal_fll_pi.h"
-	#include "hal_i2c_internal.h"
-	#include "hal_uart_internal.h"
-//#include "pmsis/rtos/os/pmsis_task.h"
-//#include "pmsis/rtos/os/pmsis_freq.h"
-//#include "target/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h"
-//#include "hal/include/hal_native_task_api.h"
 #if defined(FEATURE_CLUSTER)
-//#include "pmsis/implem/cluster/cluster.h"
 #endif  /* FEATURE_CLUSTER */
 
 #endif  /* HW_VERIF_ONLY */
-
 /* Hal includes. */
-//#include "pmsis/implem/hal/hal.h"
 
 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-properties.h

@@ -17,7 +17,6 @@
 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
 
-
 /* PULP defs */
 #define PULP
 
@@ -67,58 +66,9 @@
 /* L1 cluster TS */
 #define ARCHI_HAS_CL_L1_TS          (1)
 
-
-
-/* TODO: fix this table */
-/* UDMA peripherals */
-// #define UDMA_HAS_SPIM               (1)
-// #define UDMA_HAS_HYPER              (0)
-// #define UDMA_HAS_UART               (1)
-// #define UDMA_HAS_I2C                (1)
-// #define UDMA_HAS_DMACPY             (0)
-// #define UDMA_HAS_I2S                (1)
-// #define UDMA_HAS_CPI                (1)
-
-/* TODO: fix this table */
-/* Number of UDMA peripherals */
-// #define UDMA_NB_SPIM                (2)
-// #define UDMA_NB_HYPER               (0)
-// #define UDMA_NB_UART                (1)
-// #define UDMA_NB_I2C                 (2)
-// #define UDMA_NB_DMACPY              (0)
-// #define UDMA_NB_I2S                 (1)
-// #define UDMA_NB_CPI                 (1)
-
-/* TODO: fix this table */
-/* #define UDMA_NB_PERIPH              ((UDMA_HAS_SPIM ? UDMA_NB_SPIM) + \ */
-/*                                      (UDMA_HAS_HYPER ? UDMA_NB_HYPER) + \ */
-/*                                      (UDMA_HAS_UART ? UDMA_NB_UART) + \ */
-/*                                      (UDMA_HAS_I2C ? UDMA_NB_I2C) + \ */
-/*                                      (UDMA_HAS_DMACPY ? UDMA_NB_DMACPY) + \ */
-/*                                      (UDMA_HAS_I2S ? UDMA_NB_I2S) + \ */
-/*                                      (UDMA_HAS_CPI ? UDMA_NB_CPI)) */
 #define UDMA_NB_PERIPH              (10)
 /* Size of each UDMA peripheral */
 #define UDMA_PERIPH_SIZE_LOG2       (7)
 #define UDMA_PERIPH_SIZE            (1 << UDMA_PERIPH_SIZE_LOG2)
 
-/* UDMA peripherals ID, this maps to PER_ID_* in udma_subsystem.sv */
-//#define UDMA_SPIM_ID(id)            (1   + (id))
-/* #define UDMA_HYPER_ID(id)           (3   + (id)) */
-//#define UDMA_UART_ID(id)            (0   + (id))
-//#define UDMA_I2C_ID(id)             (2   + (id))
-/* #define UDMA_DMACPY_ID(id)          (7   + (id)) */
-//#define ARCHI_UDMA_FILTER_ID(id)          (7  + (id))
-////#define UDMA_I2S_ID(id)             (5  + (id))
-//#define UDMA_CPI_ID(id)             (6  + (id))
-//#define UDMA_SDIO_ID(id)            (4   + (id))
-
-
-/* Pads & GPIO. */
-// #define ARCHI_NB_PAD                (48)
-// #define ARCHI_NB_GPIO               (32)
-
-/* PWM. */
-/* #define ARCHI_NB_PWM                (4) */
-
 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pulp-mem-map.h

@@ -20,8 +20,6 @@
 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
 
-
-
 /*
  * SOC PERIPHERALS
  */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-system.h

@@ -25,9 +25,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-//#include "FreeRTOSConfig.h"
-
-
 extern volatile uint32_t system_core_clock;
 
 void system_init (void);

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-target.h

@@ -24,7 +24,6 @@
 #include "core_pulp.h"
 #include "core_utils.h"
 #include "core-v-mcu-periph.h"
-//#include "pmsis/targets/periph.h"
 
 static inline void hal_compiler_barrier()
 {

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp.h

@@ -30,11 +30,8 @@
 #include "core-v-mcu-memory-map.h"
 
 #include "pmsis_gcc.h"
-//#include "cores/TARGET_RISCV_32/csr.h"
 #include "csr.h"
-//#include "cores/TARGET_RISCV_32/bits.h"
 #include "bits.h"
-//#include "cores/TARGET_RISCV_32/pulp_io.h"
 #include "pulp_io.h"
 #include "core-v-mcu-periph.h"
 

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp_cluster.h

@@ -27,7 +27,6 @@
 
 #ifdef FEATURE_CLUSTER
 
-//#include "cores/TARGET_RISCV_32/core_pulp.h"
 #include "core_pulp.h"
 
 #ifdef __cplusplus
@@ -45,8 +44,6 @@
 #define FC_CLUSTER_SW_NOTIF_EVENT      0                /**< Used to notify FC*/
 #define CLUSTER_CLUSTER_SW_NOTIF_EVENT 1                /**< Used to notify CLUSTER*/
 
-
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -77,7 +74,6 @@ typedef struct
 #define SCB_FETCH_EN_Msk               (1UL /* << SCB_FETCH_EN_Pos*/)    /*!< SCB FETCH_EN Mask */
 /*@} end of group CMSIS_FC_CTRL */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_SCBC     System Control Block for Icache (SCBC)
@@ -104,7 +100,6 @@ typedef struct
 
 /*@} end of group CMSIS_SCBC */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_EU_CORE_DEMUX     Event Unit Core
@@ -138,7 +133,6 @@ typedef struct {
 
 /*@} end of group CMSIS_EU_CORE_DEMUX */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_EU_SEC_DEMUX     Event Unit Security
@@ -158,7 +152,6 @@ typedef struct {
 
 /*@} end of group CMSIS_EU_DEMUX */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_EU_LOOP_DEMUX     Event Unit Loop
@@ -201,10 +194,8 @@ typedef struct {
   __IOM  uint32_t TRIGGER_CLR[8];             /**< EU_SW_EVENTS_DEMUX trigger clear register, offset: 0x80 */
 } EU_SW_EVENTS_DEMUX_Type;
 
-
 /*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_EU_DISPATCH_DEMUX     Event Unit Dispatch
@@ -234,7 +225,6 @@ typedef struct {
 
 /*@} end of group CMSIS_EU_MUTEX_DEMUX */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_EU_BARRIER_DEMUX     Event Unit Barrier
@@ -256,7 +246,6 @@ typedef struct {
 
 /*@} end of group CMSIS_EU_BARRIER_DEMUX */
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_EU_SOC_EVENTS     Event Unit Barrier
@@ -277,9 +266,6 @@ typedef struct {
 
 /*@} end of group CMSIS_EU_SOC_EVENTS */
 
-
-
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -328,7 +314,6 @@ typedef struct
 
 /*@} end of group CMSIS_DMAMCHAN */
 
-
 /**
   \ingroup    CMSIS_core_register
   \defgroup   CMSIS_core_base     Core Definitions
@@ -377,7 +362,6 @@ typedef struct {
     __O uint32_t TCDM_STRIDE_REG;
 } decompressor_t;
 
-
 /**
   \ingroup  CMSIS_core_register
   \defgroup CMSIS_CLUSTER_EU_CORES    Cluster Event Unit Cores
@@ -412,7 +396,6 @@ typedef struct {
 #define CLUSTER_DISPATCH_IS_JOB_SHIFT                (31U)
 #define CLUSTER_DISPATCH_IS_JOB(x)                   (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_IS_JOB_SHIFT)) & CLUSTER_DISPATCH_IS_JOB_MASK)
 
-
 /* Memory map */
 
 #define CLUSTER_BASE                    (ARCHI_CLUSTER_GLOBAL_ADDR(0)) /*!< CLUSTER Base Address */
@@ -426,7 +409,6 @@ typedef struct {
 #define CLUSTER_EU_SOC_EVENTS_BASE      (ARCHI_EU_ADDR + 0x700UL) /*!< CLUSTER Event Unit SOC Events Base Address */
 #define CLUSTER_EU_EXT_EVENTS_BASE      (ARCHI_EU_ADDR + 0x780UL) /*!< CLUSTER Event Unit EXT Events Base Address */
 
-
 #define CLUSTER_EU_CORE_DEMUX_BASE      (ARCHI_DEMUX_PERIPHERALS_ADDR)        /*!< CLUSTER Event Unit Core Demux Base Address */
 #define CLUSTER_EU_SEC_DEMUX_BASE       (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x040UL)  /*!< CLUSTER Event Unit Security Demux Base Address */
 #define CLUSTER_EU_LOOP_DEMUX_BASE      (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x060UL)  /*!< CLUSTER Event Unit Loop Demux Base Address */
@@ -435,7 +417,6 @@ typedef struct {
 #define CLUSTER_EU_SW_EVENTS_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x100UL)  /*!< CLUSTER Event Unit SW Events Demux Base Address */
 #define CLUSTER_EU_BARRIER_DEMUX_BASE   (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x200UL)  /*!< CLUSTER Event Unit Barrier Demux Base Address */
 
-
 /* Cluster Core Structrue definitions */
 #define CLUSTER_EU_SW_EVENTS      ((EU_SW_EVENTS_DEMUX_Type   *)  CLUSTER_EU_SW_EVENTS_BASE) /*!< EU_SW_EVENTS_DEMUX configuration struct */
 #define EU_CORES    ((CLUSTER_EU_CORES_Type   *)   ARCHI_EU_ADDR)             /*!< CLUSTER_EU_CORES configuration struct */
@@ -446,8 +427,6 @@ typedef struct {
 #define CLUSTER_TIMERL              ((TimerL_Type    *)     CLUSTER_SysTick_BASE  )   /*!< SysTick configuration struct */
 #define CLUSTER_TIMERH              ((TimerH_Type    *)     CLUSTER_SysTick_BASE  )   /*!< SysTick configuration struct */
 
-
-
 #ifdef __cplusplus
 }
 #endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pmsis_gcc.h

@@ -128,7 +128,6 @@
 #define __get_PRIMASK()      1
 /*@} end of CMSIS_Core_RegAccFunctions */
 
-
 /* ##########################  Core Instruction Access  ######################### */
 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
   Access to dedicated instructions

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_core-v-mcu_metal.h

@@ -23,8 +23,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-//#include "FreeRTOSConfig.h"
-
 /* PULPissimo defs */
 #define PULPISSIMO
 

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/core-v-mcu.c

@@ -25,8 +25,6 @@
 
 #include <core_pulp_cluster.h>
 #include <core-v-mcu-config.h>
-
-//#include "pmsis/implem/drivers/fc_event/fc_event.h"
 #include "hal_fc_event.h"
 /* TODO: weird include */
 #include "core-v-mcu-properties.h"
@@ -34,12 +32,8 @@
 #include "hal_soc_eu.h"
 #include "hal_apb_soc_ctrl_reg_defs.h"
 #include "udma_uart_driver.h"
-#include "udma_i2cm_driver.h"
-#include "udma_qspi_driver.h"
-#include "hal_apb_i2cs.h"
 #include "hal_udma_ctrl_reg_defs.h"
 #include "hal_udma_uart_reg_defs.h"
-
 #include <rthw.h>
 #include <rtthread.h>
 #include "rtconfig.h"
@@ -235,13 +229,8 @@ void system_init(void)
 	pulp_soc_eu_event_init();
 
 	/* Setup soc events handler. */
-	// pi_fc_event_handler_init(FC_SOC_EVENT);
 	pi_fc_event_handler_init(11);
 
-	/* TODO: I$ enable*/
-	/* enable core level interrupt (mie) */
-	//irq_clint_enable();
-
 	val = csr_read(CSR_MIE);
 
 	/* TODO: enable uart */
@@ -249,44 +238,10 @@ void system_init(void)
 	{
 		udma_uart_open(id, 115200);
 	}
-	#if 0  
-	for (uint8_t id = 0; id != N_I2CM; id++)
-	{
-		udma_i2cm_open(id, 400000); // 200000
-	} 
-	for (i = 0; i < N_QSPIM; i++)
-	{
-		setQspimPinMux(i);
-		udma_qspim_open(i, 2500000);
-		udma_qspim_control((uint8_t)i, (udma_qspim_control_type_t)kQSPImReset, (void *)0);
-
-		lFlashID = udma_flash_readid(i, 0);
-		if ((lFlashID == 0xFFFFFFFF) || (lFlashID == 0))
-		{
-			gQSPIFlashPresentFlg[i] = 0;
-		}
-		else
-		{
-			gQSPIFlashPresentFlg[i] = 1;
-			if ((lFlashID & 0xFF) == 0x20)
-			{
-				gMicronFlashDetectedFlg[i] = 1;
-				gQSPIIdNum = 0;
-			}
-			else
-				gMicronFlashDetectedFlg[i] = 0;
-		}
-		restoreQspimPinMux(i);
-	}
-	#endif
 
 #if (FOR_SIMULATION_TESTING == 1)
 	forSimulationTesting();
 #endif
-
-	// hal_set_apb_i2cs_slave_on_off(1);
-	// if (hal_get_apb_i2cs_slave_address() != MY_I2C_SLAVE_ADDRESS)
-	// hal_set_apb_i2cs_slave_address(MY_I2C_SLAVE_ADDRESS);
 }
 
 void system_core_clock_update(void)
@@ -357,106 +312,3 @@ void rt_systick_config(void)
 	extern int timer_irq_init(uint32_t ticks);
 	timer_irq_init(ARCHI_FPGA_FREQUENCY / RT_TICK_PER_SECOND);
 }
-
-#if (FOR_SIMULATION_TESTING == 1)
-uint8_t gCamDataBuf[1024];
-
-void udma_cam_open(uint8_t cam_id)
-{
-	int i = 0;
-	volatile UdmaCtrl_t *pudma_ctrl = (UdmaCtrl_t *)UDMA_CH_ADDR_CTRL;
-
-	/* Enable reset and enable uart clock */
-	pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
-	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
-	pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
-
-	// psdio_regs->clk_div_b.clk_div = 5;
-	// psdio_regs->clk_div_b.valid = 1;
-	hal_setpinmux(21, 0); // cam0_vsync
-	hal_setpinmux(22, 0); // cam0_hsync
-	hal_setpinmux(25, 0); // cam0_clk
-	for (i = 0; i < 8; i++)
-	{
-		// set pin muxes to cam functionality
-		hal_setpinmux(29 + i, 0);
-	}
-	return;
-}
-
-void cam_interface_init(uint16_t x, uint16_t y, uint8_t aBitMode)
-{
-	camera_struct_t *camera;
-
-	uint16_t lXCoordOfUpperRightCorner = 0; // X coordinate of upper right corner of slice
-	uint16_t lYCoordOfUpperRightCorner = 0; // Y coordinate of upper right corner of slice
-
-	lXCoordOfUpperRightCorner = x + 3;
-	lYCoordOfUpperRightCorner = y + 3;
-	// camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
-	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
-	camera->cfg_ll = 0 << 16 | 0;
-	camera->cfg_ur = ((lYCoordOfUpperRightCorner << 16) | lXCoordOfUpperRightCorner);
-	// camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
-	camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
-	// camera->cfg_size = 324;
-	camera->cfg_size = y + 4;
-	camera->vsync_pol = 1;
-	if (aBitMode == 1)
-	{
-		camera->cfg_glob |= (1 << 17);
-	}
-	else if (aBitMode == 4)
-	{
-		camera->cfg_glob |= (1 << 16);
-	}
-	else if (aBitMode == 8)
-	{
-		camera->cfg_glob |= (0 << 0);
-	}
-	camera->cfg_glob |= (0 << 0) |	    //  framedrop disabled
-			    (000000 << 1) | // number of frames to drop
-			    (0 << 7) |	    // Frame slice disabled
-			    (004 << 8) |    // Format binary 100 = ByPass little endian
-			    (0000 << 11);   // Shift value ignored in bypass
-}
-
-uint8_t cam_grab_frame(int x, int y, uint8_t *pparam)
-{
-	uint32_t lCounter = 0;
-	uint8_t lStatus = 0;
-	uint16_t lX = x + 4;
-	uint16_t lY = y + 4;
-
-	camera_struct_t *camera;
-	// camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
-	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
-
-	camera->rx_saddr = pparam;
-	camera->rx_size = (lX * lY);
-	camera->rx_cfg = 0x12;				  // start 16-bit transfers
-	camera->cfg_glob |= camera->cfg_glob | (1 << 31); // enable 1 == go
-
-	lCounter = 0;
-	while (camera->rx_size != 0)
-	{
-		lCounter++;
-		if (lCounter >= 0x00100000)
-		{
-			lStatus = 3; // Time out
-			break;
-		}
-	}
-	// configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
-	camera->cfg_glob = camera->cfg_glob & (0x7fffffff); // enable 1 == go
-	// configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
-	return lStatus;
-}
-
-void forSimulationTesting(void)
-{
-	udma_cam_open(0);
-	cam_interface_init(240, 320, 8);
-	cam_grab_frame(240, 320, gCamDataBuf);
-}
-#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc.h

@@ -24,8 +24,6 @@
 #ifndef HAL_INCLUDE_HAL_APB_SOC_H_
 #define HAL_INCLUDE_HAL_APB_SOC_H_
 
-
-
 #define APB_SOC_BOOT_OTHER    0
 #define APB_SOC_BOOT_JTAG     1
 #define APB_SOC_BOOT_SPI      2
@@ -105,7 +103,6 @@
 #define APB_SOC_STATUS_EOC_BIT  31
 #define APB_SOC_NB_CORE_BIT     16
 
-
 #define APB_SOC_BYPASS_OFFSET   0x70
 
 #define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
@@ -113,19 +110,15 @@
 #define APB_SOC_BYPASS_USER0_BIT       14
 #define APB_SOC_BYPASS_USER1_BIT       15
 
-
 #define APB_SOC_FLL_CTRL_OFFSET         0xD0
 #define APB_SOC_CLKDIV_SOC_OFFSET       0xD4
 #define APB_SOC_CLKDIV_CLUSTER_OFFSET   0xD8
 #define APB_SOC_CLKDIV_PERIPH_OFFSET    0xDC
 
-
 #define APB_SOC_FLL_CTRL_SOC_BIT        0
 #define APB_SOC_FLL_CTRL_CLUSTER_BIT    1
 #define APB_SOC_FLL_CTRL_PERIPH_BIT     2
 
-
 #define APB_SOC_RTC_OFFSET     0x1D0
 
-
 #endif /* HAL_INCLUDE_HAL_APB_SOC_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fll.h

@@ -20,19 +20,15 @@
 #ifndef HAL_INCLUDE_HAL_FLL_H_
 #define HAL_INCLUDE_HAL_FLL_H_
 
-
 #define FLL_STATUS_OFFSET        0x000
 #define FLL_CONF1_OFFSET         0x004
 #define FLL_CONF2_OFFSET         0x008
 #define FLL_INTEGRATOR_OFFSET    0x00C
 
-
 #define FLL_STATUS_MULT_FACTOR_BIT                 0
 #define FLL_STATUS_MULT_FACTOR_WIDTH               16
 #define FLL_STATUS_MULT_FACTOR_MASK                (0xFFFF)
 
-
-
 #define FLL_CONF1_MODE_BIT                       31
 #define FLL_CONF1_MODE_WIDTH                     1
 #define FLL_CONF1_MODE_MASK                      (0x80000000)
@@ -56,8 +52,6 @@
 #define FLL_CONF1_MODE_STANDALONE                0
 #define FLL_CONF1_MODE_NORMAL                    1
 
-
-
 #define FLL_CONF2_GAIN_BIT                       0
 #define FLL_CONF2_GAIN_WIDTH                     4
 #define FLL_CONF2_GAIN_MASK                      (0x0000000F)
@@ -86,8 +80,6 @@
 #define FLL_CONF2_DITHERING_WIDTH                1
 #define FLL_CONF2_DITHERING_MASK                 (0x80000000)
 
-
-
 #define FLL_INTEGRATOR_INT_BIT                       16
 #define FLL_INTEGRATOR_INT_WIDTH                     10
 #define FLL_INTEGRATOR_INT_MASK                      (0x03FF0000)
@@ -96,8 +88,6 @@
 #define FLL_INTEGRATOR_FRACT_WIDTH                   10
 #define FLL_INTEGRATOR_FRACT_MASK                    (0x0000FFC0)
 
-
-
 #if !defined(LANGUAGE_ASSEMBLY) && !defined(_ASMLANGUAGE)
 
 typedef union {
@@ -178,8 +168,6 @@ typedef union {
 #define FLL_CONF1_MULT_FACTOR_SET(dst,src)       (__BITINSERT((dst),(src),0,16))
 #define FLL_CONF1_MULT_FACTOR(factor)            ((factor) << 0)
 
-
-
 #define FLL_CONF2_GAIN_GET(value)                ((((unsigned int)(value)) >> 0) & 0xF)
 #define FLL_CONF2_GAIN_SET(dst,src)              (__BITINSERT((dst),(src),4,0))
 #define FLL_CONF2_GAIN(value)                    ((value) << 0)
@@ -208,8 +196,6 @@ typedef union {
 #define FLL_CONF2_DITHER_SET(dst,src)            (__BITINSERT((dst),(src),1,31))
 #define FLL_CONF2_DITHER(value)                  ((value) << 31)
 
-
-
 #define FLL_INTEGRATOR_FRACT_GET(value)          ((((unsigned int)(value)) >> 6) & 0x3FF)
 #define FLL_INTEGRATOR_FRACT_SET(dst,src)        (__BITINSERT((dst),(src),6,10))
 #define FLL_INTEGRATOR_FRACT(value)              ((value) << 6)
@@ -218,11 +204,6 @@ typedef union {
 #define FLL_INTEGRATOR_INT_SET(dst,src)        (__BITINSERT((dst),(src),16,10))
 #define FLL_INTEGRATOR_INT(value)              ((value) << 16)
 
-
-
-
-
-
 /* Maximum Log2(DCO Frequency) */
 #define FLL_LOG2_MAXDCO     29
 /* Maximum Log2(Clok Divider) */
@@ -230,11 +211,9 @@ typedef union {
 /* Maximum Log2(Multiplier) */
 #define FLL_LOG2_MAXM       (FLL_LOG2_MAXDCO - ARCHI_REF_CLOCK_LOG2)
 
-
 /* TODO: doc */
 void pulp_fll_init(void);
 unsigned int __fll_init(int fll);
 unsigned int __rt_fll_set_freq(int fll, unsigned int frequency);
 
-
 #endif /* HAL_INCLUDE_HAL_FLL_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio.h

@@ -34,8 +34,6 @@ typedef struct {
 	uint32_t	number;
 }gpio_hal_typedef;
 
-
-
 void hal_write_gpio(uint8_t gpio_num, uint8_t value);
 void hal_set_gpio(uint8_t gpio_num);
 void hal_clr_gpio(uint8_t gpio_num);

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio_pulp.h

@@ -31,11 +31,8 @@
 #ifndef HAL_INCLUDE_HAL_GPIO_PULP_H_
 #define HAL_INCLUDE_HAL_GPIO_PULP_H_
 
-
-
 #include <stdint.h>
 #include <assert.h>
-
 #include "pulp_io.h"
 #include "hal_pinmux1.h"
 #include "core-v-mcu-pulp-mem-map.h"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_internal.h

@@ -19,14 +19,8 @@
 #ifndef HAL_INCLUDE_HAL_I2C_INTERNAL_H_
 #define HAL_INCLUDE_HAL_I2C_INTERNAL_H_
 
-
-
 #include "core-v-mcu-pmsis.h"
-//#include "pmsis/task.h"
 #include "hal_i2c_pi.h"
-//#include "hal/include/hal_pmsis_hal.h"
-//#include "pmsis/implem/hal/hal_pmsis_hal.h"
-//#include "pmsis/implem/hal/hal.h"
 #include "hal_soc_eu_periph.h"
 
 /*******************************************************************************

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_periph.h

@@ -20,7 +20,6 @@
 
 #include "hal_udma_core_periph.h"
 
-
 /* ----------------------------------------------------------------------------
    -- I2C Peripheral Access Layer --
    ---------------------------------------------------------------------------- */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_pi.h

@@ -17,16 +17,12 @@
 #ifndef HAL_INCLUDE_HAL_I2C_PI_H_
 #define HAL_INCLUDE_HAL_I2C_PI_H_
 
-
-
-//#include "pmsis/pmsis_types.h"
 #include "hal_pmsis_types.h"
 
 /**
 * @ingroup groupDrivers
 */
 
-
 /**
  * @defgroup I2C I2C
  *

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_irq.h

@@ -21,12 +21,9 @@
  *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
  */
 
-
 #ifndef HAL_INCLUDE_HAL_IRQ_H_
 #define HAL_INCLUDE_HAL_IRQ_H_
 
-
-
 #include "bits.h"
 
 #define IRQ_REG_MASK_OFFSET	  0x000

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pinmux1.h

@@ -24,7 +24,6 @@
 /* Author: Robert Balas (balasr@iis.ee.ethz.ch) */
 
 #include <stdint.h>
-
 #include "pulp_io.h"
 #include "hal_apb_soc.h"
 #include "core-v-mcu-pulp-mem-map.h"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_drivers-obs.h

@@ -16,40 +16,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-
 #ifndef HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_
 #define HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_
 
-/* PMSIS api includes. */
-/* Chips specifics. */
-//#include "pmsis/chips/gap8/perf.h"
-
-/* Drivers. */
-//#include "pmsis/drivers/cpi.h"
-//#include "pmsis/drivers/dmacpy.h"
-//#include "../../pmsis_api/include/pmsis/drivers/uart-orig.h"
-//#include "pmsis/drivers/gpio.h"
-//#include "pmsis/drivers/hyperbus.h"
-//#include "pmsis/drivers/i2c.h"
-//#include "pmsis/drivers/i2s.h"
-//#include "pmsis/drivers/pad.h"
-//#include "pmsis/drivers/perf.h"
-//#include "pmsis/drivers/pwm.h"
-//#include "pmsis/drivers/rtc.h"
-//#include "pmsis/drivers/spi.h"
 #include "hal_fc_event.h"
 #include "hal_fll_pi.h"
-//#include "pmsis/implem/drivers/perf/perf.h"
-//#include "pmsis/implem/drivers/pmu/pmu.h"
-//#include "pmsis/implem/drivers/pwm/pwm_internal.h"
-//#include "pmsis/implem/drivers/rtc/rtc_internal.h"
-//#include "pmsis/implem/drivers/timer/timer.h"
-//#include "pmsis/implem/drivers/udma/cpi/cpi_internal.h"
-//#include "pmsis/implem/drivers/udma/dmacpy/dmacpy_internal.h"
-//#include "pmsis/implem/drivers/udma/hyperbus/hyperbus_internal.h"
 #include "hal_i2c_internal.h"
-//#include "pmsis/implem/drivers/udma/i2s/i2s_internal.h"
 #include "hal_uart_internal.h"
 
-
 #endif /* HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_types.h

@@ -23,7 +23,6 @@
  * @defgroup groupDrivers Drivers
  */
 
-
 /// @cond IMPLEM
 
 /**

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_types_pi.h

@@ -30,7 +30,6 @@
 #ifndef __PMSIS_IMPLEM_PMSIS_TYPES_H__
 #define __PMSIS_IMPLEM_PMSIS_TYPES_H__
 
-//#include "pmsis/pmsis_types.h"
 #include "hal_pmsis_types.h"
 
 #ifndef PI_TASK_IMPLEM
@@ -58,5 +57,4 @@ typedef struct pi_task
 
 #endif  /* __PMSIS_IMPLEM_PMSIS_TYPES_H__ */
 
-
 #endif /* HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pwm_ctrl_periph.h

@@ -20,9 +20,6 @@
 #ifndef HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_
 #define HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_
 
-
-
-
 /* ----------------------------------------------------------------------------
    -- PWM_CTRL Peripheral Access Layer --
    ---------------------------------------------------------------------------- */
@@ -34,7 +31,6 @@ typedef struct
     volatile uint32_t cg; /**< ADV_TIMERS channels clock gating configuration register. */
 } pwm_ctrl_t;
 
-
 /* ----------------------------------------------------------------------------
    -- PWM_CTRL Register Bitfield Access --
    ---------------------------------------------------------------------------- */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pwm_periph.h

@@ -15,14 +15,9 @@
  * limitations under the License.
  */
 
-
 #ifndef HAL_INCLUDE_HAL_PWM_PERIPH_H_
 #define HAL_INCLUDE_HAL_PWM_PERIPH_H_
 
-
-
-
-
 /* ----------------------------------------------------------------------------
    -- PWM Peripheral Access Layer --
    ---------------------------------------------------------------------------- */
@@ -38,7 +33,6 @@ typedef struct
     volatile uint32_t counter;         /**< ADV_TIMER0 counter register. */
 } pwm_t;
 
-
 /* ----------------------------------------------------------------------------
    -- PWM Register Bitfield Access --
    ---------------------------------------------------------------------------- */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_ctrl_periph.h

@@ -15,12 +15,9 @@
  * limitations under the License.
  */
 
-
 #ifndef HAL_INCLUDE_HAL_SOC_CTRL_PERIPH_H_
 #define HAL_INCLUDE_HAL_SOC_CTRL_PERIPH_H_
 
-
-
 /* ----------------------------------------------------------------------------
    -- SOC_CTRL Peripheral Access Layer --
    ---------------------------------------------------------------------------- */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_eu_periph.h

@@ -19,9 +19,7 @@
 #ifndef HAL_INCLUDE_HAL_SOC_EU_PERIPH_H_
 #define HAL_INCLUDE_HAL_SOC_EU_PERIPH_H_
 
-//#include "pmsis/targets/target.h"
 #include "core-v-mcu-target.h"
-//#include "cores/TARGET_RISCV_32/pulp_io.h"
 #include "pulp_io.h"
 
 /*!

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_spi_periph.h

@@ -15,12 +15,9 @@
  * limitations under the License.
  */
 
-
 #ifndef HAL_INCLUDE_HAL_SPI_PERIPH_H_
 #define HAL_INCLUDE_HAL_SPI_PERIPH_H_
 
-
-
 #include "hal_udma_core_periph.h"
 
 /* ----------------------------------------------------------------------------

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_timer.h

@@ -23,8 +23,6 @@
 #ifndef HAL_INCLUDE_HAL_TIMER_H_
 #define HAL_INCLUDE_HAL_TIMER_H_
 
-
-
 #include "bits.h"
 
 /* Timer Low Configuration register. */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_internal.h

@@ -19,10 +19,8 @@
 #ifndef HAL_INCLUDE_HAL_UART_INTERNAL_H_
 #define HAL_INCLUDE_HAL_UART_INTERNAL_H_
 
-//#include "../../pmsis_api/include/pmsis/drivers/uart-orig.h"
 #include "hal_uart_pi.h"
 #include "core-v-mcu-pmsis.h"
-//#include "pmsis/task.h"
 
 /*******************************************************************************
  * Definitions
@@ -37,7 +35,6 @@
     #define UART_DRIVER_DATA_IMPLEM_SPECIFC
 #endif
 
-
 /*
  * pi_task:
  * data[0] = l2_buf

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_periph.h

@@ -20,7 +20,6 @@
 #define HAL_INCLUDE_HAL_UART_PERIPH_H_
 #include "hal_udma_core_periph.h"
 
-
 /* ----------------------------------------------------------------------------
    -- UART Peripheral Access Layer --
    ---------------------------------------------------------------------------- */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_pi.h

@@ -14,7 +14,6 @@
  * limitations under the License.
  */
 
-
 #ifndef __PMSIS_DRIVERS_UART_H__
 #define __PMSIS_DRIVERS_UART_H__
 

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_apb_i2cs.c

@@ -1,7 +1,6 @@
 #include "core-v-mcu-config.h"
 #include "hal_apb_i2cs_reg_defs.h"
 
-
 uint8_t hal_get_apb_i2cs_slave_address(void)
 {
 

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fc_event.c

@@ -23,16 +23,10 @@
  *      Author: qlblue
  */
 
-//#include "pmsis/implem/drivers/fc_event/fc_event.h"
 #include "hal_fc_event.h"
-//#include "pmsis/implem/hal/hal.h"
 #include "hal_soc_eu_periph.h"
-//#include "pmsis/implem/drivers/pmsis_it.h"
-//#include "FreeRTOS.h"
-//#include "semphr.h"
 #include "rtthread.h"
 
-#define unuse_freertos_in_event
 /*******************************************************************************
  * Variables, macros, structures,... definition
  ******************************************************************************/
@@ -44,7 +38,6 @@
 static void fc_event_null_event(void *arg);
 
 static volatile pi_fc_event_handler_t fc_event_handlers[SOC_EU_NB_FC_EVENTS];
-//static SemaphoreHandle_t  fc_event_semaphores[SOC_EU_NB_FC_EVENTS];
 
 static void fc_event_null_event(void *arg)
 {
@@ -62,20 +55,6 @@ void pi_fc_event_handler_init(uint32_t fc_event_irq)
 	//irqn_enable(fc_event_irq);
 }
 
-#if 0  
-void pi_fc_event_handler_set(uint32_t event_id,
-			     pi_fc_event_handler_t event_handler,
-					SemaphoreHandle_t semaphoreHandle)
-{
-	if (event_handler != NULL) {
-		fc_event_handlers[event_id] = event_handler;
-	}
-	if (semaphoreHandle != NULL) {
-		fc_event_semaphores[event_id] = semaphoreHandle;
-	}
-}
-#endif 
-
 void user_pi_fc_event_handler_set(uint32_t event_id,
 			     pi_fc_event_handler_t event_handler)
 {
@@ -87,14 +66,12 @@ void user_pi_fc_event_handler_set(uint32_t event_id,
 void pi_fc_event_handler_clear(uint32_t event_id)
 {
 	fc_event_handlers[event_id] = (pi_fc_event_handler_t)fc_event_null_event;
-	//fc_event_semaphores[event_id] = NULL;// remove  from  project 
 }
 
 /* TODO: Use Eric's FIRQ ABI */
 void fc_soc_event_handler1 (uint32_t mcause)
 {
 	uint32_t val = 0;
-	//static BaseType_t xHigherPriorityTaskWoken;
 
 	uint32_t event_id = *(uint32_t*)(0x1a106090); // new event fifo address
 
@@ -104,16 +81,4 @@ void fc_soc_event_handler1 (uint32_t mcause)
 	if (fc_event_handlers[event_id] != NULL) {
 		fc_event_handlers[event_id]((void *)event_id);
 	}
-	#if 0
-	if (fc_event_semaphores[event_id] != NULL) {
-		/* Unblock the task by releasing the semaphore. */
-		#ifdef  unuse_freertos_in_event
-		 SemaphoreHandle_t xSemaphoreHandle = fc_event_semaphores[event_id];
-		 xSemaphoreGiveFromISR( xSemaphoreHandle, &xHigherPriorityTaskWoken );
-		 //rt_schedule();
-		 //portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-		 //__asm volatile( "ecall" );
-		#endif 
-	}
-	#endif
 }

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fll.c

@@ -25,7 +25,6 @@
 
 #include <pulp_io.h>
 #include <stdint.h>
-
 #include "system_metal.h"
 #include "core-v-mcu-pulp-mem-map.h"
 #include "hal_fll.h"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fll_pi.c

@@ -18,7 +18,6 @@
 
 #include <stdlib.h>
 #include "hal_fll_pi.h"
-/* TODO: abstract this */
 #include "core-v-mcu-system.h"
 #include <rtthread.h>
 /*******************************************************************************

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_gpio.c

@@ -16,16 +16,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
- //#include "FreeRTOS.h"
- //#include "FreeRTOSConfig.h"
- //#include "kernel/include/task.h"		// Needed for configASSERT
-
  #include "core-v-mcu-config.h"
  #include "efpga_template_reg_defs.h"
  #include "hal_apb_gpio_reg_defs.h"
  #include "hal_gpio.h"
-
-
+ 
 void hal_efpgaio_output(uint8_t efpgaio_num, efpgaio_enum_typedef value) {
 
 Efpga_t *efpga = (Efpga_t*)EFPGAIO_START_ADDR;

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_gpio_pulp.c

@@ -25,7 +25,6 @@
 #include <hal_pinmux1.h>
 #include <bits.h>
 #include <pulp_io.h>
-
 #include "core-v-mcu-pulp-mem-map.h"
 
 int gpio_pin_conf_pad(int pin, uint32_t flags)
@@ -155,17 +154,3 @@ inline int gpio_pin_toggle(int pin)
 {
 	return gpio_port_toggle_bits(BIT(pin));
 }
-/* TODO: gpio interrupt handling and configuration */
-/* static inline int gpio_pin_interrupt_configure() */
-/* { */
-/* } */
-
-/* static inline int gpio_manage_callback(){ */
-
-/* } */
-/* static inline int gpio_enable_callback(){ */
-
-/* } */
-/* static inline int gpio_disable_callback(){ */
-
-/* } */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_irq.c

@@ -22,7 +22,6 @@
 #include <csr.h>
 #include <pulp_io.h>
 #include <stdint.h>
-
 #include "core-v-mcu-pulp-mem-map.h"
 #include "hal_irq.h"
 
@@ -57,7 +56,7 @@ uint32_t irq_clint_enable()
 	val = csr_read(CSR_MSTATUS);
 
 	val = csr_read_set(CSR_MSTATUS, MSTATUS_IE);
-	//csr_write(CSR_MIE, BIT(25));
+
 	val = csr_read(CSR_MSTATUS);
 	return val;
 }

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_pinmux.c

@@ -16,10 +16,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
  
- //#include "FreeRTOS.h"
- //#include "FreeRTOSConfig.h"
-//#include "kernel/include/task.h"		// Needed for configASSERT
- 
  #include "core-v-mcu-config.h"
  #include "hal_apb_soc_ctrl_regs.h"
  #include "hal_pinmux.h"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_pinmux1.c

@@ -23,7 +23,6 @@
 #include <assert.h>
 #include <hal_pinmux1.h>
 #include <pulp_io.h>
-
 #include "core-v-mcu-pulp-mem-map.h"
 #include "hal_apb_soc.h"
 

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_soc_eu.c

@@ -34,15 +34,6 @@ uint32_t soc_eu_mask_get(uint32_t offset)
 	return readw((uintptr_t)(SOC_EU_ADDR + offset));
 }
 
-/* void soc_eu_irq_mask_set(uint32_t mask) */
-/* { */
-/* 	writew(mask, PULP_SOC_EU_ADDR + ) */
-/* } */
-
-/* uint32_t soc_eu_irq_mask_get() */
-/* { */
-/* } */
-
 void pulp_soc_eu_event_init()
 {
 	/* deactivate all soc events */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_timer_irq.c

@@ -19,17 +19,15 @@
 /* Driver to configure PULP timer as periodic interrupt source */
 /* Author: Robert Balas (balasr@iis.ee.ethz.ch)
  *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
- */
+*/
 
 #include <bits.h>
 #include <pulp_io.h>
 #include <stdint.h>
 #include <stdbool.h>
-
 #include "core-v-mcu-pulp-mem-map.h"
 #include "hal_timer.h"
 #include "hal_timer_irq.h"
-//#include "FreeRTOSConfig.h"
 
 /* TODO: used to measure elapsed time since last "visit" */
 static uint32_t last_count;
@@ -74,8 +72,7 @@ int timer_irq_set_timeout(uint32_t ticks, bool idle)
 	writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_LO_OFFSET));
 	writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_LO_OFFSET));
 	writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_HI_OFFSET));
-//	writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_HI_OFFSET));
-
+	
 	return 0;
 }
 
@@ -88,5 +85,4 @@ uint32_t timer_irq_clock_elapsed()
 uint32_t timer_irq_cycle_get_32()
 {
 	return readw((uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CNT_LO_OFFSET));
-
 }

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_uart_driver.c → bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_udma_driver/source/udma_uart_driver.c

@@ -23,19 +23,12 @@
 #include "hal_udma_uart_reg_defs.h"
 #include <drv_usart.h>
 #include <stdint.h>
-//#include "FreeRTOS.h"
-//#include "semphr.h"
 #include "core-v-mcu-config.h"
 #include "udma_uart_driver.h"
 #include "rtthread.h"
-//#include <ringbuffer.h>
-//#include "ipc/ringbuffer.h" 
 #include "rtdevice.h" 
 #define  unuse_freertos_in_uart
 
-
-//SemaphoreHandle_t  uart_semaphores_rx[N_UART];
-//SemaphoreHandle_t  uart_semaphores_tx[N_UART];
 char u1buffer[128], u0buffer[128];
 int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
 UdmaUart_t *puart0 = (UdmaUart_t*)(UDMA_CH_ADDR_UART);
@@ -53,40 +46,12 @@ uint16_t outdata(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
 
 	return 0;
 }
-
-// ringbuffer  
+ 
 #define UART_RX_BUFFER_LEN 16
 rt_uint8_t uart_rxbuffer[UART_RX_BUFFER_LEN]={0};
 struct rt_ringbuffer uart_rxTCB;
 struct rt_semaphore  shell_rx_semaphore;
 
-// extern struct ch32_uart_config uart_config[];
-// extern void uart_isr(struct rt_serial_device *serial);
-// extern struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] ;
-// extern UART1_INDEX;
-char n_data[]="\r\n";
-// void uart_rx_isr (void *id){
-// 	rt_interrupt_enter();
-// 	if (id == 6) {
-// 		while (*(int*)0x1a102130) {
-// 			u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
-// 			u1wrptr &= 0x7f;
-// 		}
-// 	}
-// 	if (id == 2) {
-// 		while (puart0->valid) {
-// 			//u0buffer[u0wrptr++] = puart0->data_b.rx_data & 0xff;
-// 			//u0wrptr &= 0x7f;
-// 			//outdata(0,sizeof(u0buffer),u0buffer);
-// 			//outdata(0,sizeof(n_data),n_data);
-// 			//rt_ringbuffer_putchar(&uart_rxTCB,puart0->data_b.rx_data & 0xff);
-// 			//u0wrptr=0;
-// 			uart_isr(&(uart_obj[UART1_INDEX].serial));
-// 		}
-// 		//rt_sem_release(&shell_rx_semaphore);
-// 	}
-// 	rt_interrupt_leave();
-// }
 uint8_t uart_getchar (uint8_t id) {
 	uint8_t retval;
 	if (id == 1) {
@@ -112,10 +77,8 @@ uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate) {
 	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_UART0_CLKEN << uart_id);
 	pudma_ctrl->reg_cg |= (UDMA_CTRL_UART0_CLKEN << uart_id);
 
-
 	user_pi_fc_event_handler_set(SOC_EVENT_UART_RX(uart_id), uart_rx_isr);
 
-
 	/* Enable SOC events propagation to FC. */
 	hal_soc_eu_set_fc_mask(SOC_EVENT_UART_RX(uart_id));
 	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_UART_TX(uart_id));
@@ -145,12 +108,7 @@ uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate) {
 uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
 	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
 
-	// SemaphoreHandle_t shSemaphoreHandle = uart_semaphores_tx[uart_id];
-	// if( xSemaphoreTake( shSemaphoreHandle, 1000000 ) != pdTRUE ) {
-	// 	return 1;
-	// }
-
-	while (puart->status_b.tx_busy) {  // ToDo: Why is this necessary?  Thought the semaphore should have protected
+	while (puart->status_b.tx_busy) { 
 	}
 
 	puart->tx_saddr = (uint32_t)write_buffer;
@@ -165,7 +123,6 @@ uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer
 	uint8_t last_char = 0;
 	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
 
-
 	while ( (ret < (read_len - 2)) && (last_char != 0xd)) {
 		if (puart->valid_b.rx_data_valid == 1) {
 			last_char = (uint8_t)(puart->data_b.rx_data & 0xff);

bsp/core-v-mcu/core-v-cv32e40p/README_zh.md → bsp/core-v-mcu/core-v-cv32e40p/readme.md

@@ -1,6 +1,6 @@
 # Core-V-MCU BSP 说明
 
-[English](README.md) | **中文**
+[English](readme_EN.md) | **中文**
 
 ## 1 MCU简介
 

bsp/core-v-mcu/core-v-cv32e40p/readme_EN.md

@@ -0,0 +1,179 @@
+# Core-V-MCU BSP Description
+
+English| [Chinese](readme.md)
+
+## 1 MCU Introduction
+
+The purpose of Core-V-MCU is to show cv32e40p, which is a fully validated RISC-V kernel provided by Open Hardware Group (OpenHW). The cv32e40p core is connected to a group of representative peripherals.
+
+![CORE-V-MCU_Block_Diagram](figures/CORE-V-MCU_Block_Diagram.png)
+
+**Core-V-MCU resources：**
+
+- 2xUART
+- 2xI2C master
+- 1xI2C slave
+- 2xQSPI master
+- 1xCAMERA
+- 1xSDIO
+- 4xPWM
+- eFPGA with 4 math units
+
+For more information, please visit[Introduction to Core-V-MCU](https://docs.openhwgroup.org/projects/core-v-mcu/doc-src/overview.html)
+
+More resources,please visit[OpenHW official website](https://www.openhwgroup.org/)
+
+## 2 Compilation Description
+
+The board level package supports the RISC-V GCC development environment. The specific version information is as follows:
+
+| IDE/Compiler | Tested version          |
+| ------------ | ----------------------- |
+| GCC          | riscv32-unknown-elf-gcc |
+
+## 3 Instruction for user
+
+>This chapter is provided for users who use RT Thread on the Core-V-MCU. At present, the Core-V-MCU has no actual hardware and uses QEMU to implement simulation. The qemu used in this article is compiled under the ubuntu18.04 environment.
+
+### 3.1 Compile BSP with Env
+
+This section explains how to use Env tools to compile BSP projects.
+
+#### 3.1.1 编译BSP
+
+1. Preparation 1：[Download GCC compilation tool chain under Linux environment](https://github.com/Yaochenger/openhw-/tree/master/toolchain))，put the downloaded tool chain in your Linux environment.
+
+2. Preparation 2：Install ENV under Linux environment, and run the following command on the console.
+
+   ```shell
+   wget https://gitee.com/RT-Thread-Mirror/env/raw/master/install_ubuntu.sh
+   chmod 777 install_ubuntu.sh
+   ./install_ubuntu.sh --gitee
+   ```
+
+3. Preparation 3：Compile [qemu](https://github.com/plctlab/plct-qemu/tree/plct-corev-upstream-sync-dma) provided by PLCT lab in Linux environment,Refer to the compilation method given in README.rst to compile qemu in the Linux environment, or use the[qemu](https://github.com/Yaochenger/openhw-/releases/tag/qemu-linux).
+
+4. Windows environment download RT Thread[最新源码](https://github.com/RT-Thread/rt-thread/archive/refs/heads/master.zip)，This step can also be completed in the Linux environment.
+
+5. Download in the Windows environment Open the Env tool under the current BSP root directory and execute the following command to compile, 'scons -- exec path=tool chain path'. The tool chain under Windows can be downloaded directly using RT Studio. The path of the tool chain is configured according to the user's specific environment. This step can also be completed in the Linux environment. The example command is as follows:
+
+   ```shell
+   scons --exec-path=D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages
+   \RISC-V\RISC-V-GCC-RV32\2022-04-12\bin
+   ```
+
+    Compile directly while specifying the tool chain location, and then generate the rtthread.elf file.
+
+   ![compilation result of core-v-mcu ](figures/compilation result of core-v-mcu .png)
+
+6. Try running rtthread.elf, copy the rtthread.elf generated in the previous step to the bin file directory of the compiled qemu tool, and execute the following command:
+
+   ```shell
+   ./qemu-system-riscv32 -M core_v_mcu -bios none -kernel rtthread.elf -nographic -monitor none -serial stdio
+   ```
+
+   The operation results are as follows:
+
+   ![test-result1](figures/test-result1.png)
+
+   7.Run the following command to generate a complete, copyable project.
+
+```shell
+scons --dist
+```
+
+Copy the generated independent project to the Linux environment.
+
+### 3.2Compile and run the project in the Linux environment
+
+#### 3.2.1 Configuration project
+
+1.Found in the complete project root directory copied above**rtconfig.h**,remove the precompiled command from the file**#ifndef RT_CONFIG_H__**,**#define RT_CONFIG_H__**,**#ifndef RT_CONFIG_H__**,**#endif**,be sure to perform this step, or an error will be reported during compilation.
+
+![remove ifdef](figures/remove ifdef.png)
+
+2.Line the following command to generate the makefile project
+
+```shell
+scons --target=makefile
+```
+
+3.Enter **make ** at the command line to compile the project
+
+4.Run the following command to start qemu and compile rtthread.elf，`/home/wangshun/bin/qemu-riscv/bin/qemu-system-riscv32`is the tool chain path of the Linux environment. It is set here as the user's tool chain path.
+
+```shell
+/home/wangshun/bin/qemu-riscv/bin/qemu-system-riscv32 -M core_v_mcu -bios none -kernel rtthread.elf -nographic -monitor none -serial stdio
+```
+
+BSP supports the Finsh component of RT-Thread. Enter the command`version` to view the version information of RT-Thread. Click Tap to view the supported commands. The running results are as follows:
+
+![test-result2](figures/test-result2.png)
+
+So far, the configuration and running test of RT-Thread project based on Core-V-MCU have been completed.
+
+### 3.3 Import the RT Thread project into OpenHW's Core V-IDE
+
+1.Download and Install[core-v-sdk](https://github.com/openhwgroup/core-v-sdk),according [README.md](https://github.com/openhwgroup/core-v-sdk#readme)to install the IDE in a Linux environment。
+
+2.Create a workspace folder in the home directory, and open the IDE to use the workspace folder as the working path.
+
+3.Choose`Import projects Option `:
+
+![import_2](figures/import_2.png)
+
+4.Choose`Existing Code as Makefile Project`:
+
+![makefile project](figures/makefile project.png)
+
+5.The settings are as follows:![settings](figures/settings.png)
+
+6.Project configuration settings:
+
+![Properites](figures/Properites.png)
+
+7.Modify compilation command:
+
+![make](figures/make.png)
+
+8.Clear the files compiled from the project and recompile the project:
+
+![IDE-MAKE](figures/IDE-MAKE.png)
+
+9.Run the following command in the root directory of the project compiled with IDE, and the result is consistent with that of **3.2.1**. The project under IDE will be configured. So far, the import and running tests of the RT-Thread project imported from IDE to Core-V-MCU have been completed.
+
+### 3.4调试配置
+
+1.Debug Configurations settings:
+
+![debug](figures/debug.png)
+
+2.Double click`GDB OpenOCD Debugging`，build debug configuration options:
+
+![openocd](figures/openocd.png)
+
+3.Import on chip peripheral register file:
+
+PATH:`OpenHW/CORE-V-SDKv0.0.0.4/registers/csr`,the specific path is configured according to the SDK path installed by the user。
+
+![register file](figures/register file.png)
+
+3.Import on chip peripheral register file:
+
+PATH`/home/wangshun/OpenHW/CORE-V-SDKv0.0.0.4/registers/peripheral`,the specific path is configured according to the SDK path installed by the user.
+
+![svd](figures/svd.png)
+
+3.Configure the QEMU running environment:
+
+Cancle`Start OpenOCD locally`，the configuration parameters are as follows:![debug2](figures/debug2.png)
+
+4.Run the following commands:
+
+```shell
+/home/wangshun/bin/qemu-riscv/bin/qemu-system-riscv32 -M core_v_mcu -bios none -kernel rtthread.elf -nographic -monitor none -serial stdio -s -S
+```
+
+5.Click debug to start debugging:
+
+![run](figures/run.png)