|
@@ -176,7 +176,11 @@ bss_loop:
|
|
|
#ifdef RT_USING_USERSPACE
|
|
#ifdef RT_USING_USERSPACE
|
|
|
ldr r0, =MMUTable /* vaddr */
|
|
ldr r0, =MMUTable /* vaddr */
|
|
|
add r0, r5 /* to paddr */
|
|
add r0, r5 /* to paddr */
|
|
|
|
|
+#ifdef RT_LWP_ENABLE_ASID
|
|
|
|
|
+ bl rt_hw_mmu_switch_kernel
|
|
|
|
|
+#else
|
|
|
bl rt_hw_mmu_switch
|
|
bl rt_hw_mmu_switch
|
|
|
|
|
+#endif
|
|
|
#else
|
|
#else
|
|
|
bl rt_hw_mmu_init
|
|
bl rt_hw_mmu_init
|
|
|
#endif
|
|
#endif
|
|
@@ -270,13 +274,19 @@ rt_hw_set_process_id:
|
|
|
#ifdef RT_LWP_ENABLE_ASID
|
|
#ifdef RT_LWP_ENABLE_ASID
|
|
|
.global rt_hw_mmu_switch
|
|
.global rt_hw_mmu_switch
|
|
|
rt_hw_mmu_switch:
|
|
rt_hw_mmu_switch:
|
|
|
|
|
+ mov r3, #0
|
|
|
|
|
+ mcr p15, 0, r3, c13, c0, 1 /* set contextid = 0, for synchronization*/
|
|
|
|
|
+ isb
|
|
|
|
|
+
|
|
|
orr r0, #0x18
|
|
orr r0, #0x18
|
|
|
mcr p15, 0, r0, c2, c0, 0 /* ttbr0 write r0 to ttbr0*/
|
|
mcr p15, 0, r0, c2, c0, 0 /* ttbr0 write r0 to ttbr0*/
|
|
|
|
|
+ isb
|
|
|
|
|
|
|
|
- and r2, r1, #0xff
|
|
|
|
|
- mov r1, r1, LSL #0x8
|
|
|
|
|
- orr r1, r1, r2 /* r1 = (asid << 8) | (asid & 0xFFUL) */
|
|
|
|
|
|
|
+ mov r1, r1, LSL #0x8
|
|
|
|
|
+ and r2, r2, #0xff
|
|
|
|
|
+ orr r1, r1, r2 /* contextid.PROCID = pid, contextid.ASID = asid*/
|
|
|
mcr p15, 0, r1, c13, c0, 1 /* set contextid = r1*/
|
|
mcr p15, 0, r1, c13, c0, 1 /* set contextid = r1*/
|
|
|
|
|
+ isb
|
|
|
|
|
|
|
|
mcr p15, 0, r0, c7, c5, 0 /* iciallu */
|
|
mcr p15, 0, r0, c7, c5, 0 /* iciallu */
|
|
|
mcr p15, 0, r0, c7, c5, 6 /* bpiall */
|
|
mcr p15, 0, r0, c7, c5, 6 /* bpiall */
|
|
@@ -284,6 +294,25 @@ rt_hw_mmu_switch:
|
|
|
dsb
|
|
dsb
|
|
|
isb
|
|
isb
|
|
|
mov pc, lr
|
|
mov pc, lr
|
|
|
|
|
+
|
|
|
|
|
+.global rt_hw_mmu_switch_kernel
|
|
|
|
|
+rt_hw_mmu_switch_kernel:
|
|
|
|
|
+ orr r0, #0x18
|
|
|
|
|
+ mcr p15, 0, r0, c2, c0, 0 /* ttbr0 */
|
|
|
|
|
+
|
|
|
|
|
+ /* The nG bit of tlb entries of kernel is 0,
|
|
|
|
|
+ so no need to update ASID,
|
|
|
|
|
+ neither to flush TLB
|
|
|
|
|
+ */
|
|
|
|
|
+ ; mov r0, #0
|
|
|
|
|
+ ; mcr p15, 0, r0, c8, c7, 0
|
|
|
|
|
+ mcr p15, 0, r0, c7, c5, 0 /* iciallu */
|
|
|
|
|
+ mcr p15, 0, r0, c7, c5, 6 /* bpiall */
|
|
|
|
|
+
|
|
|
|
|
+ dsb
|
|
|
|
|
+ isb
|
|
|
|
|
+ mov pc, lr
|
|
|
|
|
+
|
|
|
#else
|
|
#else
|
|
|
.global rt_hw_mmu_switch
|
|
.global rt_hw_mmu_switch
|
|
|
rt_hw_mmu_switch:
|
|
rt_hw_mmu_switch:
|
|
@@ -300,6 +329,7 @@ rt_hw_mmu_switch:
|
|
|
isb
|
|
isb
|
|
|
mov pc, lr
|
|
mov pc, lr
|
|
|
#endif
|
|
#endif
|
|
|
|
|
+
|
|
|
.global rt_hw_mmu_tbl_get
|
|
.global rt_hw_mmu_tbl_get
|
|
|
rt_hw_mmu_tbl_get:
|
|
rt_hw_mmu_tbl_get:
|
|
|
mrc p15, 0, r0, c2, c0, 0 /* ttbr0 */
|
|
mrc p15, 0, r0, c2, c0, 0 /* ttbr0 */
|
|
@@ -641,8 +671,12 @@ rt_secondary_cpu_entry:
|
|
|
after_enable_mmu_n:
|
|
after_enable_mmu_n:
|
|
|
ldr r0, =MMUTable
|
|
ldr r0, =MMUTable
|
|
|
add r0, r5
|
|
add r0, r5
|
|
|
|
|
+#ifdef RT_LWP_ENABLE_ASID
|
|
|
|
|
+ bl rt_hw_mmu_switch_kernel
|
|
|
|
|
+#else
|
|
|
bl rt_hw_mmu_switch
|
|
bl rt_hw_mmu_switch
|
|
|
#endif
|
|
#endif
|
|
|
|
|
+#endif
|
|
|
|
|
|
|
|
#ifdef RT_USING_FPU
|
|
#ifdef RT_USING_FPU
|
|
|
mov r4, #0xfffffff
|
|
mov r4, #0xfffffff
|