Merge branch 'master' into master

.travis.yml

@@ -107,6 +107,7 @@ env:
   - RTT_BSP='stm32/stm32h743-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32h747-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32l4r9-st-eval' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l010-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='stm32/stm32l053-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'

README.md

@@ -86,7 +86,7 @@ RT-Thread supports many architectures, and has covered the major architectures i
 - **ARM9**：manufacturers like Allwinner、Xilinx 、GOKE
 - **ARM11**：manufacturers like Fullhan
 - **MIPS32**：manufacturers like loongson、Ingenic
-- **RISC-V**：manufacturers like Hifive、Kendryte
+- **RISC-V**：manufacturers like Hifive、Kendryte、[Nuclei](https://nucleisys.com/)
 - **ARC**：manufacturers like SYNOPSYS
 - **DSP**：manufacturers like TI
 - **C-Sky**

README_zh.md

@@ -89,7 +89,7 @@ RT-Thread RTOS 支持许多架构，并且已经涵盖了当前应用中的主
 
 - MIPS32：如芯片制造商loongson、Ingenic
 
-- RISC-V：如芯片制造商Hifive、Kendryte
+- RISC-V：如芯片制造商Hifive、Kendryte、[芯来Nuclei](https://nucleisys.com/)
 
 - ARC：如芯片制造商SYNOPSYS
 

bsp/at32/at32f403a-start/Kconfig

@@ -17,6 +17,5 @@ config PKGS_DIR
 
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
-source "../libraries/Kconfig"
+source "../Libraries/Kconfig"
 source "board/Kconfig"
-

bsp/at32/at32f403a-start/rtconfig.py

@@ -1,4 +1,5 @@
 import os
+import sys
 
 # toolchains options
 ARCH='arm'
@@ -57,7 +58,7 @@ if PLATFORM == 'gcc':
     else:
         CFLAGS += ' -O2'
 
-    CXXFLAGS = CFLAGS 
+    CXXFLAGS = CFLAGS
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
 
@@ -88,7 +89,7 @@ elif PLATFORM == 'armcc':
     else:
         CFLAGS += ' -O2'
 
-    CXXFLAGS = CFLAGS 
+    CXXFLAGS = CFLAGS
     CFLAGS += ' -std=c99'
 
     POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
@@ -136,8 +137,14 @@ elif PLATFORM == 'iar':
 
     LFLAGS = ' --config "board/linker_scripts/link.icf"'
     LFLAGS += ' --entry __iar_program_start'
-    
+
     CXXFLAGS = CFLAGS
 
     EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT):
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT)

bsp/at32/tools/sdk_dist.py

@@ -0,0 +1,19 @@
+import os
+import sys
+import shutil
+cwd_path = os.getcwd()
+sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
+
+# BSP dist function
+def dist_do_building(BSP_ROOT):
+    from mkdist import bsp_copy_files
+    import rtconfig
+    
+    dist_dir  = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT))
+    library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries')
+    library_dir  = os.path.join(dist_dir, 'Libraries')
+    print("=> copy bsp drivers")
+    bsp_copy_files(os.path.join(library_path, 'rt_drivers'), os.path.join(library_dir, 'rt_drivers'))
+    print("=> copy bsp library")
+    bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE), os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
+    shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))

bsp/k210/driver/Kconfig

@@ -2,17 +2,44 @@ config BSP_USING_UART_HS
     bool "Enable High Speed UART"
     default y
 
-config BSP_USING_UART1
-    bool "Enable UART1 (GPIO0/1)"
+menu "General Purpose UARTs"
+
+menuconfig BSP_USING_UART1
+    bool "Enable UART1"
     default n
+    if BSP_USING_UART1
+        config BSP_UART1_TXD_PIN
+            int "uart1 TXD pin number"
+            default 20
+        config BSP_UART1_RXD_PIN
+            int "uart1 RXD pin number"
+            default 21
+    endif
 
-config BSP_USING_UART2
-    bool "Enable UART2 (GPIO0/1)"
+menuconfig BSP_USING_UART2
+    bool "Enable UART2"
     default n
+    if BSP_USING_UART2
+        config BSP_UART2_TXD_PIN
+            int "uart2 TXD pin number"
+            default 28
+        config BSP_UART2_RXD_PIN
+            int "uart2 RXD pin number"
+            default 27
+    endif
 
-config BSP_USING_UART3
-    bool "Enable UART3 (GPIO0/1)"
+menuconfig BSP_USING_UART3
+    bool "Enable UART3"
     default n
+    if BSP_USING_UART3
+        config BSP_UART3_TXD_PIN
+            int "uart3 TXD pin number"
+            default 22
+        config BSP_UART3_RXD_PIN
+            int "uart3 RXD pin number"
+            default 23
+    endif
+endmenu
 
 config BSP_USING_I2C1
     bool "Enable I2C1 (GPIO0/1)"

bsp/k210/driver/drv_io_config.c

@@ -63,6 +63,18 @@ static struct io_config
 #endif
 #endif
 
+#ifdef BSP_USING_UART1
+    IOCONFIG(BSP_UART1_TXD_PIN, FUNC_UART1_TX),
+    IOCONFIG(BSP_UART1_RXD_PIN, FUNC_UART1_RX),
+#endif
+#ifdef BSP_USING_UART2
+    IOCONFIG(BSP_UART2_TXD_PIN, FUNC_UART2_TX),
+    IOCONFIG(BSP_UART2_RXD_PIN, FUNC_UART2_RX),
+#endif
+#ifdef BSP_USING_UART3
+    IOCONFIG(BSP_UART3_TXD_PIN, FUNC_UART3_TX),
+    IOCONFIG(BSP_UART3_RXD_PIN, FUNC_UART3_RX),
+#endif
 };
 
 static int print_io_config()
@@ -89,7 +101,15 @@ int io_config_init(void)
     sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
     sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
     sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
-    
+#ifdef BSP_USING_UART2
+    // for IO-27/28
+    sysctl_set_power_mode(SYSCTL_POWER_BANK4, SYSCTL_POWER_V33);
+#endif
+#if  defined(BSP_USING_UART1) || defined(BSP_USING_UART3)
+    // for IO-20~23
+    sysctl_set_power_mode(SYSCTL_POWER_BANK3, SYSCTL_POWER_V33);
+#endif
+
     for(i = 0; i < count; i++)
     {
         fpioa_set_function(io_config[i].io_num, io_config[i].func);

bsp/k210/driver/drv_uart.c

@@ -17,10 +17,12 @@
 #include <stdio.h>
 #include <sysctl.h>
 
-// #include "uart.h"
+#include "uart.h"
 #include "uarths.h"
 #include "plic.h"
 
+#define UART_DEFAULT_BAUDRATE               115200
+
 static volatile uarths_t *const _uarths = (volatile uarths_t *)UARTHS_BASE_ADDR;
 
 struct device_uart
@@ -29,22 +31,71 @@ struct device_uart
     rt_uint32_t irqno;
 };
 
-static rt_err_t  uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t  rt_uarths_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t  uarths_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int       drv_uarths_putc(struct rt_serial_device *serial, char c);
+static int       drv_uarths_getc(struct rt_serial_device *serial);
+
+static void     uarths_irq_handler(int irqno, void *param);
+
+static rt_err_t  rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
 static rt_err_t  uart_control(struct rt_serial_device *serial, int cmd, void *arg);
 static int       drv_uart_putc(struct rt_serial_device *serial, char c);
 static int       drv_uart_getc(struct rt_serial_device *serial);
 
 static void     uart_irq_handler(int irqno, void *param);
 
+const struct rt_uart_ops _uart_hs_ops =
+{
+    rt_uarths_configure,
+    uarths_control,
+    drv_uarths_putc,
+    drv_uarths_getc,
+    RT_NULL
+};
+
 const struct rt_uart_ops _uart_ops =
 {
-    uart_configure,
+    rt_uart_configure,
     uart_control,
     drv_uart_putc,
     drv_uart_getc,
+    //TODO: add DMA support
     RT_NULL
 };
 
+/* START ported from kendryte standalone sdk uart.c */
+#define __UART_BRATE_CONST  16
+
+volatile uart_t* const  _uart[3] =
+{
+    (volatile uart_t*)UART1_BASE_ADDR,
+    (volatile uart_t*)UART2_BASE_ADDR,
+    (volatile uart_t*)UART3_BASE_ADDR
+};
+
+void uart_init(uart_device_number_t channel)
+{
+    sysctl_clock_enable(SYSCTL_CLOCK_UART1 + channel);
+    sysctl_reset(SYSCTL_RESET_UART1 + channel);
+}
+
+/* END ported from kendryte standalone sdk uart.c */
+static inline uart_device_number_t _get_uart_channel(rt_uint32_t addr)
+{
+    switch (addr)
+    {
+        case UART1_BASE_ADDR:
+            return UART_DEVICE_1;
+        case UART2_BASE_ADDR:
+            return UART_DEVICE_2;
+        case UART3_BASE_ADDR:
+            return UART_DEVICE_3;
+        default:
+            return UART_DEVICE_MAX;
+    }
+}
+
 /*
  * UART Initiation
  */
@@ -62,7 +113,7 @@ int rt_hw_uart_init(void)
         serial  = &serial_hs;
         uart    = &uart_hs;
 
-        serial->ops              = &_uart_ops;
+        serial->ops              = &_uart_hs_ops;
         serial->config           = config;
         serial->config.baud_rate = 115200;
 
@@ -86,36 +137,79 @@ int rt_hw_uart_init(void)
 
         serial->ops              = &_uart_ops;
         serial->config           = config;
-        serial->config.baud_rate = 115200;
+        serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
 
         uart->hw_base   = UART1_BASE_ADDR;
         uart->irqno     = IRQN_UART1_INTERRUPT;
 
+        uart_init(UART_DEVICE_1);
+
         rt_hw_serial_register(serial,
-                              "uarths",
+                              "uart1",
                               RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                               uart);
     }
 #endif
 
 #ifdef BSP_USING_UART2
+    {
+        static struct rt_serial_device  serial2;
+        static struct device_uart       uart2;
+
+        serial  = &serial2;
+        uart    = &uart2;
+
+        serial->ops              = &_uart_ops;
+        serial->config           = config;
+        serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
+
+        uart->hw_base   = UART2_BASE_ADDR;
+        uart->irqno     = IRQN_UART2_INTERRUPT;
+
+        uart_init(UART_DEVICE_2);
+
+        rt_hw_serial_register(serial,
+                              "uart2",
+                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                              uart);
+    }
 #endif
 
 #ifdef BSP_USING_UART3
+    {
+        static struct rt_serial_device  serial3;
+        static struct device_uart       uart3;
+
+        serial  = &serial3;
+        uart    = &uart3;
+
+        serial->ops              = &_uart_ops;
+        serial->config           = config;
+        serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
+
+        uart->hw_base   = UART3_BASE_ADDR;
+        uart->irqno     = IRQN_UART3_INTERRUPT;
+
+        uart_init(UART_DEVICE_3);
+
+        rt_hw_serial_register(serial,
+                              "uart3",
+                              RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                              uart);
+    }
 #endif
 
     return 0;
 }
 
 /*
- * UART interface
+ * UARTHS interface
  */
-static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+static rt_err_t rt_uarths_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-    rt_uint32_t baud_div;
     struct device_uart *uart;
-    uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
-    uint16_t div = freq / cfg->baud_rate - 1;
+    uint32_t freq_hs = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
+    uint16_t div_hs = freq_hs / cfg->baud_rate - 1;
 
     RT_ASSERT(serial != RT_NULL);
     serial->config = *cfg;
@@ -125,7 +219,7 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
 
     if (uart->hw_base == UARTHS_BASE_ADDR)
     {
-        _uarths->div.div = div;
+        _uarths->div.div = div_hs;
         _uarths->txctrl.txen = 1;
         _uarths->rxctrl.rxen = 1;
         _uarths->txctrl.txcnt = 0;
@@ -137,13 +231,14 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
     }
     else
     {
+        return (-1);
         /* other uart */
     }
 
     return (RT_EOK);
 }
 
-static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+static rt_err_t uarths_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
     struct device_uart *uart;
 
@@ -160,7 +255,7 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
 
     case RT_DEVICE_CTRL_SET_INT:
         /* install interrupt */
-        rt_hw_interrupt_install(uart->irqno, uart_irq_handler,
+        rt_hw_interrupt_install(uart->irqno, uarths_irq_handler,
                                 serial, serial->parent.parent.name);
         rt_hw_interrupt_umask(uart->irqno);
         break;
@@ -169,38 +264,168 @@ static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg
     return (RT_EOK);
 }
 
-static int drv_uart_putc(struct rt_serial_device *serial, char c)
+
+static int drv_uarths_putc(struct rt_serial_device *serial, char c)
+{
+    struct device_uart *uart = serial->parent.user_data;
+    RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR);
+
+    while (_uarths->txdata.full);
+    _uarths->txdata.data = (uint8_t)c;
+
+    return (1);
+}
+
+static int drv_uarths_getc(struct rt_serial_device *serial)
+{
+    struct device_uart *uart = serial->parent.user_data;
+    RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR);
+
+    uarths_rxdata_t recv = _uarths->rxdata;
+    if (recv.empty)
+        return EOF;
+    else
+        return (recv.data & 0xff);
+    /* Receive Data Available */
+
+    return (-1);
+}
+
+/* UARTHS ISR */
+static void uarths_irq_handler(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+    struct device_uart *uart = serial->parent.user_data;
+    RT_ASSERT(uart->hw_base == UARTHS_BASE_ADDR);
+
+    /* read interrupt status and clear it */
+    if (_uarths->ip.rxwm)
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+/*
+ * UART interface
+ */
+static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     struct device_uart *uart;
+    uart_bitwidth_t data_width = (uart_bitwidth_t)cfg->data_bits ;
+    uart_stopbit_t stopbit = (uart_stopbit_t)cfg->stop_bits;
+    uart_parity_t parity = (uart_parity_t)cfg->parity;
+
+    uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_APB0);
+    uint32_t divisor = freq / (uint32_t)cfg->baud_rate;
+    uint8_t dlh = divisor >> 12;
+    uint8_t dll = (divisor - (dlh << 12)) / __UART_BRATE_CONST;
+    uint8_t dlf = divisor - (dlh << 12) - dll * __UART_BRATE_CONST;
+
+    RT_ASSERT(serial != RT_NULL);
+    serial->config = *cfg;
 
     uart = serial->parent.user_data;
-    if (uart->hw_base == UARTHS_BASE_ADDR)
+    RT_ASSERT(uart != RT_NULL);
+
+    uart_device_number_t channel = _get_uart_channel(uart->hw_base);
+    RT_ASSERT(channel != UART_DEVICE_MAX);
+
+    RT_ASSERT(data_width >= 5 && data_width <= 8);
+    if (data_width == 5)
     {
-        while (_uarths->txdata.full);
-        _uarths->txdata.data = (uint8_t)c;
+        RT_ASSERT(stopbit != UART_STOP_2);
     }
     else
     {
-        /* other uart */
+        RT_ASSERT(stopbit != UART_STOP_1_5);
     }
 
-    return (1);
+    uint32_t stopbit_val = stopbit == UART_STOP_1 ? 0 : 1;
+    uint32_t parity_val;
+    switch (parity)
+    {
+        case UART_PARITY_NONE:
+            parity_val = 0;
+            break;
+        case UART_PARITY_ODD:
+            parity_val = 1;
+            break;
+        case UART_PARITY_EVEN:
+            parity_val = 3;
+            break;
+        default:
+            RT_ASSERT(!"Invalid parity");
+            break;
+    }
+
+    _uart[channel]->LCR |= 1u << 7;
+    _uart[channel]->DLH = dlh;
+    _uart[channel]->DLL = dll;
+    _uart[channel]->DLF = dlf;
+    _uart[channel]->LCR = 0;
+    _uart[channel]->LCR = (data_width - 5) |
+                          (stopbit_val << 2) |
+                          (parity_val << 3);
+    _uart[channel]->LCR &= ~(1u << 7);
+    _uart[channel]->IER |= 0x80; /* THRE */
+    _uart[channel]->FCR = UART_RECEIVE_FIFO_1 << 6 |
+                          UART_SEND_FIFO_8 << 4 |
+                          0x1 << 3 |
+                          0x1;
+
+    return (RT_EOK);
 }
 
-static int drv_uart_getc(struct rt_serial_device *serial)
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
-    int ret = -1;
-    struct device_uart *uart = serial->parent.user_data;
+    struct device_uart *uart;
 
-    if (uart->hw_base == UARTHS_BASE_ADDR)
+    uart = serial->parent.user_data;
+    uart_device_number_t channel = _get_uart_channel(uart->hw_base);
+
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(channel != UART_DEVICE_MAX);
+
+    switch (cmd)
     {
-        uarths_rxdata_t recv = _uarths->rxdata;
-        if (recv.empty)
-            return EOF;
-        else
-            return (recv.data & 0xff);
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable the UART Interrupt */
+        rt_hw_interrupt_mask(uart->irqno);
+        _uart[channel]->IER &= ~0x1;
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* install interrupt */
+        rt_hw_interrupt_install(uart->irqno, uart_irq_handler,
+                                serial, serial->parent.parent.name);
+        rt_hw_interrupt_umask(uart->irqno);
+        _uart[channel]->IER |= 0x1;
+        break;
     }
 
+    return (RT_EOK);
+}
+
+static int drv_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct device_uart *uart = serial->parent.user_data;
+    uart_device_number_t channel = _get_uart_channel(uart->hw_base);
+    RT_ASSERT(channel != UART_DEVICE_MAX);
+
+    while (_uart[channel]->LSR & (1u << 5));
+    _uart[channel]->THR = c;
+
+    return (1);
+}
+
+static int drv_uart_getc(struct rt_serial_device *serial)
+{
+    struct device_uart *uart = serial->parent.user_data;
+    uart_device_number_t channel = _get_uart_channel(uart->hw_base);
+    RT_ASSERT(channel != UART_DEVICE_MAX);
+
+    if (_uart[channel]->LSR & 1)
+        return (char)(_uart[channel]->RBR & 0xff);
+    else
+        return EOF;
     /* Receive Data Available */
 
     return (-1);
@@ -209,21 +434,20 @@ static int drv_uart_getc(struct rt_serial_device *serial)
 /* UART ISR */
 static void uart_irq_handler(int irqno, void *param)
 {
-    rt_ubase_t isr;
     struct rt_serial_device *serial = (struct rt_serial_device *)param;
     struct device_uart *uart = serial->parent.user_data;
+    uart_device_number_t channel = _get_uart_channel(uart->hw_base);
+    RT_ASSERT(channel != UART_DEVICE_MAX);
 
     /* read interrupt status and clear it */
-    if (uart->hw_base == UARTHS_BASE_ADDR)
-    {
-        if (_uarths->ip.rxwm) 
-            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-    }
+    if (_uart[channel]->LSR)
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
 }
 
 /* WEAK for SDK 0.5.6 */
 
-RT_WEAK void uart_debug_init(int uart_channel)
+RT_WEAK void uart_debug_init(uart_device_number_t uart_channel)
 {
 
 }
+

bsp/lpc54608-LPCXpresso/project.ewp

@@ -2148,16 +2148,16 @@
   <group>
     <name>CPlusPlus</name>
     <file>
-      <name>$PROJ_DIR$\../../components/cplusplus/Mutex.cpp</name>
+      <name>$PROJ_DIR$\../../components/cplusplus/cxx_Mutex.cpp</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/cplusplus/Semaphore.cpp</name>
+      <name>$PROJ_DIR$\../../components/cplusplus/cxx_Semaphore.cpp</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/cplusplus/Thread.cpp</name>
+      <name>$PROJ_DIR$\../../components/cplusplus/cxx_Thread.cpp</name>
     </file>
     <file>
-      <name>$PROJ_DIR$\../../components/cplusplus/crt.cpp</name>
+      <name>$PROJ_DIR$\../../components/cplusplus/cxx_crt.cpp</name>
     </file>
     <file>
       <name>$PROJ_DIR$\../../components/cplusplus/crt_init.c</name>

bsp/lpc54608-LPCXpresso/project.ewt

@@ -2355,19 +2355,19 @@
     <group>
         <name>CPlusPlus</name>
         <file>
-            <name>$PROJ_DIR$\..\..\components\cplusplus\crt.cpp</name>
+            <name>$PROJ_DIR$\..\..\components\cplusplus\cxx_crt.cpp</name>
         </file>
         <file>
             <name>$PROJ_DIR$\..\..\components\cplusplus\crt_init.c</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\components\cplusplus\Mutex.cpp</name>
+            <name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Mutex.cpp</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\components\cplusplus\Semaphore.cpp</name>
+            <name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Semaphore.cpp</name>
         </file>
         <file>
-            <name>$PROJ_DIR$\..\..\components\cplusplus\Thread.cpp</name>
+            <name>$PROJ_DIR$\..\..\components\cplusplus\cxx_Thread.cpp</name>
         </file>
     </group>
     <group>

bsp/lpc54608-LPCXpresso/project.uvprojx

@@ -330,9 +330,9 @@
             <v6Rtti>0</v6Rtti>
             <VariousControls>
               <MiscControls>--library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186</MiscControls>
-              <Define>CPU_LPC54608J512ET180=1, CPU_LPC54608, CORE_M4, SDK_DEBUGCONSOLE=0, RT_USING_ARM_LIBC</Define>
+              <Define>SDK_DEBUGCONSOLE=0, CPU_LPC54608, CORE_M4, CPU_LPC54608J512ET180=1, RT_USING_ARM_LIBC</Define>
               <Undefine />
-              <IncludePath>.;..\..\include;applications;.;drivers;SDK_2.2_LPCXpresso54608\CMSIS\Include;SDK_2.2_LPCXpresso54608\devices\LPC54608;SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers;SDK_2.2_LPCXpresso54608\devices\LPC54608\utilities;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\inc;SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\cplusplus;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\pthreads;..\..\components\libc\time;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\netdev\include;..\..\components\net\sal_socket\include;..\..\components\net\sal_socket\include\socket;..\..\components\net\sal_socket\impl;..\..\components\net\sal_socket\include\dfs_net;..\..\components\net\sal_socket\include\dfs_net\sys_select;..\..\components\net\sal_socket\include\socket\sys_socket</IncludePath>
+              <IncludePath>.;../../include;applications;.;drivers;SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/inc;SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src;SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers;SDK_2.2_LPCXpresso54608/devices/LPC54608/utilities;SDK_2.2_LPCXpresso54608/CMSIS/Include;SDK_2.2_LPCXpresso54608/devices/LPC54608;../../libcpu/arm/common;../../libcpu/arm/cortex-m4;../../components/finsh;../../components/dfs/include;../../components/dfs/filesystems/elmfat;../../components/dfs/filesystems/devfs;../../components/net/lwip-2.0.2/src;../../components/net/lwip-2.0.2/src/include;../../components/net/lwip-2.0.2/src/include/ipv4;../../components/net/lwip-2.0.2/src/arch/include;../../components/net/lwip-2.0.2/src/include/netif;../../components/net/netdev/include;../../components/net/sal_socket/include;../../components/net/sal_socket/include/socket;../../components/net/sal_socket/impl;../../components/net/sal_socket/include/dfs_net;../../components/net/sal_socket/include/dfs_net/sys_select;../../components/net/sal_socket/include/socket/sys_socket;../../components/drivers/include;../../components/drivers/include;../../components/drivers/spi;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/cplusplus;../../components/libc/compilers/armlibc;../../components/libc/compilers/common;../../components/libc/pthreads;../../components/libc/time</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -379,112 +379,105 @@
             <File>
               <FileName>clock.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
+              <FilePath>../../src/clock.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>components.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\components.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cpu.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\cpu.c</FilePath>
+              <FilePath>../../src/components.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>device.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
+              <FilePath>../../src/device.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>idle.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\idle.c</FilePath>
+              <FilePath>../../src/idle.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>ipc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\ipc.c</FilePath>
+              <FilePath>../../src/ipc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>irq.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\irq.c</FilePath>
+              <FilePath>../../src/irq.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>kservice.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\kservice.c</FilePath>
+              <FilePath>../../src/kservice.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>mem.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\mem.c</FilePath>
+              <FilePath>../../src/mem.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>memheap.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\memheap.c</FilePath>
+              <FilePath>../../src/memheap.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>mempool.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\mempool.c</FilePath>
+              <FilePath>../../src/mempool.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>object.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
+              <FilePath>../../src/object.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler.c</FilePath>
+              <FilePath>../../src/scheduler.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>signal.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\signal.c</FilePath>
+              <FilePath>../../src/signal.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>thread.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
+              <FilePath>../../src/thread.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>timer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
+              <FilePath>../../src/timer.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -494,21 +487,21 @@
             <File>
               <FileName>application.c</FileName>
               <FileType>1</FileType>
-              <FilePath>applications\application.c</FilePath>
+              <FilePath>applications/application.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>mnt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>applications\mnt.c</FilePath>
+              <FilePath>applications/mnt.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>startup.c</FileName>
               <FileType>1</FileType>
-              <FilePath>applications\startup.c</FilePath>
+              <FilePath>applications/startup.c</FilePath>
             </File>
           </Files>
         </Group>
@@ -518,419 +511,419 @@
             <File>
               <FileName>board.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\board.c</FilePath>
+              <FilePath>drivers/board.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>clock_config.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\clock_config.c</FilePath>
+              <FilePath>drivers/clock_config.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drt_mpu.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drt_mpu.c</FilePath>
+              <FilePath>drivers/drt_mpu.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_emac.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_emac.c</FilePath>
+              <FilePath>drivers/drv_emac.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_ft5406.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_ft5406.c</FilePath>
+              <FilePath>drivers/drv_ft5406.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_i2c.c</FilePath>
+              <FilePath>drivers/drv_i2c.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_lcd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_lcd.c</FilePath>
+              <FilePath>drivers/drv_lcd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_sd.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_sd.c</FilePath>
+              <FilePath>drivers/drv_sd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_sdram.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_sdram.c</FilePath>
+              <FilePath>drivers/drv_sdram.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_sram.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_sram.c</FilePath>
+              <FilePath>drivers/drv_sram.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>drv_uart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\drv_uart.c</FilePath>
+              <FilePath>drivers/drv_uart.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_phy.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\fsl_phy.c</FilePath>
+              <FilePath>drivers/fsl_phy.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>CMSIS</GroupName>
+          <GroupName>Libraries</GroupName>
           <Files>
             <File>
-              <FileName>startup_LPC54608.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\startup_LPC54608.s</FilePath>
+              <FileName>fsl_sd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>system_LPC54608.c</FileName>
+              <FileName>fsl_sdmmc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\system_LPC54608.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sdmmc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>keil_lib_power.lib</FileName>
-              <FileType>4</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\arm\keil_lib_power.lib</FilePath>
+              <FileName>fsl_host.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_host.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
+              <FileName>fsl_sd_event.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>SDK_2.2_LPCXpresso54608/sdmmc_2.1.2/src/fsl_sd_event.c</FilePath>
             </File>
           </Files>
-        </Group>
-        <Group>
-          <GroupName>Libraries</GroupName>
           <Files>
             <File>
               <FileName>fsl_adc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_adc.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_adc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_clock.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_clock.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_clock.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_common.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_common.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_common.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_crc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_crc.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_crc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_ctimer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_ctimer.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_ctimer.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dma.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_dmic.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_dmic_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_dmic_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_dmic_dma.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_eeprom.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_eeprom.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_eeprom.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_emc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_emc.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_emc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_enet.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_enet.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_enet.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_flashiap.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flashiap.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flashiap.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_flexcomm.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_flexcomm.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_flexcomm.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_fmc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmc.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_fmeas.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_fmeas.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_fmeas.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_gint.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gint.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gint.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_gpio.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_gpio.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_gpio.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_i2c.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_i2c_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2c_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2c_dma.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_i2s.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_i2s_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_i2s_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_i2s_dma.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_inputmux.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_inputmux.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_inputmux.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_lcdc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_lcdc.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_lcdc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_mcan.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mcan.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mcan.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_mrt.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_mrt.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_mrt.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
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               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_pint.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_pint.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_power.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_power.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_power.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_reset.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_reset.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_reset.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_rit.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rit.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rit.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_rtc.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_rtc.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_rtc.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_sctimer.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sctimer.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sctimer.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_sdif.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_sdif.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_sdif.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_spi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_spi_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spi_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spi_dma.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_spifi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_spifi_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_spifi_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_spifi_dma.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_usart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_usart_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_usart_dma.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_usart_dma.c</FilePath>
             </File>
           </Files>
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             <File>
               <FileName>fsl_utick.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\devices\LPC54608\drivers\fsl_utick.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_utick.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>fsl_wwdt.c</FileName>
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-            </File>
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-              <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/drivers/fsl_wwdt.c</FilePath>
             </File>
           </Files>
+        </Group>
+        <Group>
+          <GroupName>CMSIS</GroupName>
           <Files>
             <File>
-              <FileName>fsl_sdmmc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sdmmc.c</FilePath>
+              <FileName>startup_LPC54608.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/startup_LPC54608.s</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>fsl_host.c</FileName>
+              <FileName>system_LPC54608.c</FileName>
               <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_host.c</FilePath>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/system_LPC54608.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
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-              <FileType>1</FileType>
-              <FilePath>SDK_2.2_LPCXpresso54608\sdmmc_2.1.2\src\fsl_sd_event.c</FilePath>
+              <FileName>keil_lib_power.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>SDK_2.2_LPCXpresso54608/devices/LPC54608/arm/keil_lib_power.lib</FilePath>
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           </Files>
         </Group>
@@ -940,851 +933,851 @@
             <File>
               <FileName>backtrace.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+              <FilePath>../../libcpu/arm/common/backtrace.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>div0.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+              <FilePath>../../libcpu/arm/common/div0.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>showmem.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+              <FilePath>../../libcpu/arm/common/showmem.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>cpuport.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
+              <FilePath>../../libcpu/arm/cortex-m4/cpuport.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
               <FileName>context_rvds.S</FileName>
               <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
+              <FilePath>../../libcpu/arm/cortex-m4/context_rvds.S</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>CPlusPlus</GroupName>
+          <GroupName>finsh</GroupName>
           <Files>
             <File>
-              <FileName>Mutex.cpp</FileName>
-              <FileType>8</FileType>
-              <FilePath>..\..\components\cplusplus\Mutex.cpp</FilePath>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../components/finsh/shell.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>Semaphore.cpp</FileName>
-              <FileType>8</FileType>
-              <FilePath>..\..\components\cplusplus\Semaphore.cpp</FilePath>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../components/finsh/cmd.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>Thread.cpp</FileName>
-              <FileType>8</FileType>
-              <FilePath>..\..\components\cplusplus\Thread.cpp</FilePath>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../components/finsh/msh.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>crt.cpp</FileName>
-              <FileType>8</FileType>
-              <FilePath>..\..\components\cplusplus\crt.cpp</FilePath>
+              <FileName>msh_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../../components/finsh/msh_file.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>crt_init.c</FileName>
+              <FileName>finsh_compiler.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\cplusplus\crt_init.c</FilePath>
+              <FilePath>../../components/finsh/finsh_compiler.c</FilePath>
             </File>
           </Files>
-        </Group>
-        <Group>
-          <GroupName>Filesystem</GroupName>
           <Files>
             <File>
-              <FileName>dfs.c</FileName>
+              <FileName>finsh_error.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs.c</FilePath>
+              <FilePath>../../components/finsh/finsh_error.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs_file.c</FileName>
+              <FileName>finsh_heap.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs_file.c</FilePath>
+              <FilePath>../../components/finsh/finsh_heap.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs_fs.c</FileName>
+              <FileName>finsh_init.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs_fs.c</FilePath>
+              <FilePath>../../components/finsh/finsh_init.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs_posix.c</FileName>
+              <FileName>finsh_node.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\dfs_posix.c</FilePath>
+              <FilePath>../../components/finsh/finsh_node.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>poll.c</FileName>
+              <FileName>finsh_ops.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\poll.c</FilePath>
+              <FilePath>../../components/finsh/finsh_ops.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>select.c</FileName>
+              <FileName>finsh_parser.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\src\select.c</FilePath>
+              <FilePath>../../components/finsh/finsh_parser.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>devfs.c</FileName>
+              <FileName>finsh_var.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\filesystems\devfs\devfs.c</FilePath>
+              <FilePath>../../components/finsh/finsh_var.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs_elm.c</FileName>
+              <FileName>finsh_vm.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\filesystems\elmfat\dfs_elm.c</FilePath>
+              <FilePath>../../components/finsh/finsh_vm.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>ff.c</FileName>
+              <FileName>finsh_token.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\dfs\filesystems\elmfat\ff.c</FilePath>
+              <FilePath>../../components/finsh/finsh_token.c</FilePath>
             </File>
           </Files>
         </Group>
         <Group>
-          <GroupName>DeviceDrivers</GroupName>
+          <GroupName>Filesystem</GroupName>
           <Files>
             <File>
-              <FileName>i2c_core.c</FileName>
+              <FileName>dfs.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\i2c\i2c_core.c</FilePath>
+              <FilePath>../../components/dfs/src/dfs.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>i2c_dev.c</FileName>
+              <FileName>dfs_file.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\i2c\i2c_dev.c</FilePath>
+              <FilePath>../../components/dfs/src/dfs_file.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>i2c-bit-ops.c</FileName>
+              <FileName>dfs_fs.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\i2c\i2c-bit-ops.c</FilePath>
+              <FilePath>../../components/dfs/src/dfs_fs.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>pin.c</FileName>
+              <FileName>dfs_posix.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+              <FilePath>../../components/dfs/src/dfs_posix.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>mtd_nand.c</FileName>
+              <FileName>poll.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\mtd\mtd_nand.c</FilePath>
+              <FilePath>../../components/dfs/src/poll.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>rtc.c</FileName>
+              <FileName>select.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\rtc\rtc.c</FilePath>
+              <FilePath>../../components/dfs/src/select.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>block_dev.c</FileName>
+              <FileName>dfs_elm.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\sdio\block_dev.c</FilePath>
+              <FilePath>../../components/dfs/filesystems/elmfat/dfs_elm.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>mmcsd_core.c</FileName>
+              <FileName>ff.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\sdio\mmcsd_core.c</FilePath>
+              <FilePath>../../components/dfs/filesystems/elmfat/ff.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>sd.c</FileName>
+              <FileName>devfs.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\sdio\sd.c</FilePath>
+              <FilePath>../../components/dfs/filesystems/devfs/devfs.c</FilePath>
             </File>
           </Files>
+        </Group>
+        <Group>
+          <GroupName>lwIP</GroupName>
           <Files>
             <File>
-              <FileName>sdio.c</FileName>
+              <FileName>sys_arch.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\sdio\sdio.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/arch/sys_arch.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>mmc.c</FileName>
+              <FileName>api_lib.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\sdio\mmc.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/api_lib.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>serial.c</FileName>
+              <FileName>api_msg.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/api_msg.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>spi_core.c</FileName>
+              <FileName>err.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\spi\spi_core.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/err.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>spi_dev.c</FileName>
+              <FileName>netbuf.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\spi\spi_dev.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/netbuf.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>completion.c</FileName>
+              <FileName>netdb.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/netdb.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dataqueue.c</FileName>
+              <FileName>netifapi.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/netifapi.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>pipe.c</FileName>
+              <FileName>sockets.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/sockets.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>ringblk_buf.c</FileName>
+              <FileName>tcpip.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/api/tcpip.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>ringbuffer.c</FileName>
+              <FileName>def.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/def.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>waitqueue.c</FileName>
+              <FileName>dns.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/dns.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>workqueue.c</FileName>
+              <FileName>inet_chksum.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/inet_chksum.c</FilePath>
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-          <GroupOption>
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-                  <MiscControls />
-                  <Define> </Define>
-                  <Undefine> </Undefine>
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-          </GroupOption>
-        </Group>
-        <Group>
-          <GroupName>finsh</GroupName>
           <Files>
             <File>
-              <FileName>shell.c</FileName>
+              <FileName>init.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\shell.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/init.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>cmd.c</FileName>
+              <FileName>ip.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/ip.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh.c</FileName>
+              <FileName>memp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\msh.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/memp.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>msh_file.c</FileName>
+              <FileName>netif.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\msh_file.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/netif.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>finsh_compiler.c</FileName>
+              <FileName>pbuf.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/pbuf.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>finsh_error.c</FileName>
+              <FileName>raw.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\finsh_error.c</FilePath>
+              <FilePath>../../components/net/lwip-2.0.2/src/core/raw.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>finsh_heap.c</FileName>
+              <FileName>stats.c</FileName>
               <FileType>1</FileType>
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               <FileType>1</FileType>
-              <FilePath>..\..\components\net\netdev\src\netdev_ipaddr.c</FilePath>
+              <FilePath>../../components/libc/pthreads/pthread_spin.c</FilePath>
             </File>
           </Files>
-        </Group>
-        <Group>
-          <GroupName>SAL</GroupName>
           <Files>
             <File>
-              <FileName>sal_socket.c</FileName>
+              <FileName>pthread_tls.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\net\sal_socket\src\sal_socket.c</FilePath>
+              <FilePath>../../components/libc/pthreads/pthread_tls.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>net_netdb.c</FileName>
+              <FileName>sched.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\net\sal_socket\socket\net_netdb.c</FilePath>
+              <FilePath>../../components/libc/pthreads/sched.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>af_inet_lwip.c</FileName>
+              <FileName>semaphore.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\net\sal_socket\impl\af_inet_lwip.c</FilePath>
+              <FilePath>../../components/libc/pthreads/semaphore.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>net_sockets.c</FileName>
+              <FileName>clock_time.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\net\sal_socket\socket\net_sockets.c</FilePath>
+              <FilePath>../../components/libc/time/clock_time.c</FilePath>
             </File>
           </Files>
           <Files>
             <File>
-              <FileName>dfs_net.c</FileName>
+              <FileName>posix_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\components\net\sal_socket\dfs_net\dfs_net.c</FilePath>
+              <FilePath>../../components/libc/time/posix_sleep.c</FilePath>
             </File>
           </Files>
         </Group>

bsp/mini2440/.config

@@ -161,7 +161,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SDIO=y
+CONFIG_RT_SDIO_STACK_SIZE=512
+CONFIG_RT_SDIO_THREAD_PRIORITY=15
+CONFIG_RT_MMCSD_STACK_SIZE=1024
+CONFIG_RT_MMCSD_THREAD_PREORITY=22
+CONFIG_RT_MMCSD_MAX_PARTITION=16
+# CONFIG_RT_SDIO_DEBUG is not set
 # CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set

bsp/mini2440/Kconfig

@@ -16,12 +16,33 @@ config PKGS_DIR
     default "packages"
 
 config BOARD_MINI2440
-    bool "mini2440"
+    bool
     select ARCH_ARM_ARM9
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y
 
+choice
+    prompt "Lcd for mini2440"
+    default RT_MINI2440_LCD_T35
+    depends on PKG_USING_GUIENGINE
+
+    config RT_MINI2440_LCD_A70
+        bool "A70"
+
+    config RT_MINI2440_LCD_T43
+        bool "T43"
+    
+    config RT_MINI2440_LCD_N35
+        bool "N35"
+    
+    config RT_MINI2440_LCD_T35
+        bool "T35"
+
+    config RT_MINI2440_LCD_X35
+        bool "X35"
+endchoice
+
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 

bsp/mini2440/applications/main.c

@@ -5,10 +5,25 @@
 
 #include "led.h"
 
+#ifdef PKG_USING_GUIENGINE
+#include <rtgui/driver.h>
+#endif
+
 int main(void)
 {
+    rt_device_t device;
+
     printf("hello rt-thread\n");
 
+#ifdef PKG_USING_GUIENGINE
+    device = rt_device_find("lcd");
+    if (device)
+    {
+        rtgui_graphic_set_device(device);
+    }
+#endif
+
+
     while (1)
     {
         /* light on leds for one second */

bsp/mini2440/applications/mnt.c

@@ -6,16 +6,29 @@
 
 int mnt_init(void)
 {
-	if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-	{
-		rt_kprintf("File System initialized!\n");
-	}
-	else
-	{
-		rt_kprintf("File System initialzation failed!\n");
-	}
-   
-	return RT_EOK;
+    rt_uint32_t tryCnt = 5;
+    rt_device_t dev;
+
+    while(tryCnt--)
+    {
+        dev = rt_device_find("sd0");
+        if(dev != RT_NULL)
+        {
+            break;
+        }
+        rt_thread_mdelay(500);
+    }
+
+    if(dfs_mount("sd0", "/", "elm", 0, 0) == 0)                                                                                                                                                        
+    {
+        rt_kprintf("File System initialized!\n");                                                                                                                                                       
+    }
+    else
+    {
+        rt_kprintf("File System initialzation failed!\n");
+    }
+
+    return RT_EOK;
 }
 INIT_ENV_EXPORT(mnt_init);
 #endif

bsp/mini2440/drivers/SConscript

@@ -8,30 +8,30 @@ cwd     = os.path.join(str(Dir('#')), 'drivers')
 src = Split("""
 board.c
 led.c
+key.c
 uart.c
 """)
 
-if GetDepend('RT_USING_DFS'):
-	src += ['sdcard.c']
-
 if GetDepend('RT_USING_LWIP'):
 	src += ['dm9000.c']
 
-if GetDepend('PKG_USING_GUIENGINE'):
-    src += ['touch.c', 'key.c']
+if GetDepend('RT_MINI2440_LCD_A70'):
+    src += ['lcd_a70.c']
+if GetDepend('RT_MINI2440_LCD_T43'):
+    src += ['lcd_t43.c']
+if GetDepend('RT_MINI2440_LCD_N35'):
+    src += ['lcd_n35.c']
+if GetDepend('RT_MINI2440_LCD_T35'):
+    src += ['lcd_t35.c']
+if GetDepend('RT_MINI2440_LCD_X35'):
+    src += ['lcd_x35.c']
 
-if GetDepend('RT_USING_RTI'):
-    src += ['rti_stub.c']
-		
 if GetDepend('PKG_USING_GUIENGINE'):
-	if rtconfig.RT_USING_LCD_TYPE == 'PNL_A70':
-		src += ['lcd_a70.c']
-	elif rtconfig.RT_USING_LCD_TYPE == 'PNL_N35':
-		src += ['lcd_n35.c']
-	elif rtconfig.RT_USING_LCD_TYPE == 'PNL_T35':
-		src += ['lcd_t35.c']
-	elif rtconfig.RT_USING_LCD_TYPE == 'PNL_X35':
-                src += ['lcd_x35.c']
+    src += ['touch.c']
+
+if GetDepend('RT_USING_SDIO'):
+    src += ['s3cmci.c']
+
 
 CPPPATH = [cwd]
 

bsp/mini2440/drivers/lcd.h

@@ -1,21 +0,0 @@
-/*
- * File      : lcd.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2008-03-29     Yi.Qiu
- */
-#ifndef __LCD_H__
-#define __LCD_H__
-
-#include <rtthread.h>
-
-void rt_hw_lcd_init(void);
-
-#endif

bsp/mini2440/drivers/lcd_a70.c

@@ -15,7 +15,6 @@
 #include <rtthread.h>
 #include <s3c24x0.h>
 
-#include "lcd.h"
 
 /* LCD driver for A7' */
 #define LCD_WIDTH 800
@@ -35,81 +34,81 @@
 #define SCR_XSIZE  LCD_WIDTH
 #define SCR_YSIZE  LCD_HEIGHT
 
-#define RT_HW_LCD_WIDTH		LCD_WIDTH
-#define RT_HW_LCD_HEIGHT	LCD_HEIGHT
+#define RT_HW_LCD_WIDTH     LCD_WIDTH
+#define RT_HW_LCD_HEIGHT    LCD_HEIGHT
 
-#define MVAL		(13)
-#define MVAL_USED 	(0)		//0=each frame   1=rate by MVAL
-#define INVVDEN		(1)		//0=normal       1=inverted
-#define BSWP		(0)		//Byte swap control
-#define HWSWP		(1)		//Half word swap control
+#define MVAL        (13)
+#define MVAL_USED   (0)     //0=each frame   1=rate by MVAL
+#define INVVDEN     (1)     //0=normal       1=inverted
+#define BSWP        (0)     //Byte swap control
+#define HWSWP       (1)     //Half word swap control
 
-#define GPB1_TO_OUT()		(GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
-#define GPB1_TO_1()			(GPBDAT |= 0x0002)
-#define GPB1_TO_0()			(GPBDAT &= 0xfffd)
+#define GPB1_TO_OUT()       (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
+#define GPB1_TO_1()         (GPBDAT |= 0x0002)
+#define GPB1_TO_0()         (GPBDAT &= 0xfffd)
 
 #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
-#define S3C2410_LCDCON1_MMODE	   (1<<7)
-#define S3C2410_LCDCON1_DSCAN4	   (0<<5)
-#define S3C2410_LCDCON1_STN4	   (1<<5)
-#define S3C2410_LCDCON1_STN8	   (2<<5)
-#define S3C2410_LCDCON1_TFT	       (3<<5)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
 
-#define S3C2410_LCDCON1_STN1BPP	   (0<<1)
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
 #define S3C2410_LCDCON1_STN2GREY   (1<<1)
 #define S3C2410_LCDCON1_STN4GREY   (2<<1)
-#define S3C2410_LCDCON1_STN8BPP	   (3<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
 #define S3C2410_LCDCON1_STN12BPP   (4<<1)
 
-#define S3C2410_LCDCON1_TFT1BPP	   (8<<1)
-#define S3C2410_LCDCON1_TFT2BPP	   (9<<1)
-#define S3C2410_LCDCON1_TFT4BPP	   (10<<1)
-#define S3C2410_LCDCON1_TFT8BPP	   (11<<1)
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
 #define S3C2410_LCDCON1_TFT16BPP   (12<<1)
 #define S3C2410_LCDCON1_TFT24BPP   (13<<1)
 
-#define S3C2410_LCDCON1_ENVID	   (1)
+#define S3C2410_LCDCON1_ENVID      (1)
 
 #define S3C2410_LCDCON1_MODEMASK    0x1E
 
-#define S3C2410_LCDCON2_VBPD(x)	    ((x) << 24)
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
 #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
-#define S3C2410_LCDCON2_VFPD(x)	    ((x) << 6)
-#define S3C2410_LCDCON2_VSPW(x)	    ((x) << 0)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
 
 #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
 #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
 #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
 
-#define S3C2410_LCDCON3_HBPD(x)	    ((x) << 19)
-#define S3C2410_LCDCON3_WDLY(x)	    ((x) << 19)
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
 #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
-#define S3C2410_LCDCON3_HFPD(x)	    ((x) << 0)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
 #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
 
 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON4_MVAL(x)	    ((x) << 8)
-#define S3C2410_LCDCON4_HSPW(x)	    ((x) << 0)
-#define S3C2410_LCDCON4_WLH(x)	    ((x) << 0)
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
 
 #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON5_BPP24BL	    (1<<12)
-#define S3C2410_LCDCON5_FRM565	    (1<<11)
-#define S3C2410_LCDCON5_INVVCLK	    (1<<10)
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
 #define S3C2410_LCDCON5_INVVLINE    (1<<9)
 #define S3C2410_LCDCON5_INVVFRAME   (1<<8)
-#define S3C2410_LCDCON5_INVVD	    (1<<7)
-#define S3C2410_LCDCON5_INVVDEN	    (1<<6)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
 #define S3C2410_LCDCON5_INVPWREN    (1<<5)
-#define S3C2410_LCDCON5_INVLEND	    (1<<4)
-#define S3C2410_LCDCON5_PWREN	    (1<<3)
-#define S3C2410_LCDCON5_ENLEND	    (1<<2)
-#define S3C2410_LCDCON5_BSWP	    (1<<1)
-#define S3C2410_LCDCON5_HWSWP	    (1<<0)
-#define S3C2410_LCDINT_FRSYNC	(1<<1)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
+#define S3C2410_LCDINT_FRSYNC       (1<<1)
 
 static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
 //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -128,121 +127,123 @@ static void lcd_power_enable(int invpwren, int pwren)
 
 static void lcd_envid_on_off(int onoff)
 {
-	if(onoff==1)
-		/*ENVID=ON*/
-		LCDCON1|=1;
-	else
-		/*ENVID Off*/
-		LCDCON1 =LCDCON1 & 0x3fffe;
+    if(onoff==1)
+        /*ENVID=ON*/
+        LCDCON1|=1;
+    else
+        /*ENVID Off*/
+        LCDCON1 =LCDCON1 & 0x3fffe;
 }
 
 //********************** BOARD LCD backlight ****************************
 static void LcdBkLtSet(rt_uint32_t HiRatio)
 {
-#define FREQ_PWM1		1000
-	if(!HiRatio)
-	{
-		GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;	//GPB1ÉèÖÃΪoutput
-		GPBDAT &= ~(1<<1);
-		return;
-	}
-	GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
+#define FREQ_PWM1       1000
+    if(!HiRatio)
+    {
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBDAT &= ~(1<<1);
+        return;
+    }
+    GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
 
-	if( HiRatio > 100 ) HiRatio = 100 ;
+    if( HiRatio > 100 ) HiRatio = 100 ;
 
-	TCON = TCON & (~(0xf<<8)) ;			    // clear manual update bit, stop Timer1
+    TCON = TCON & (~(0xf<<8)) ;             // clear manual update bit, stop Timer1
 
-	TCFG0 &= 0xffffff00;					// set Timer 0&1 prescaler 0
-	TCFG0 |= 15;							//prescaler = 15+1
+    TCFG0 &= 0xffffff00;                    // set Timer 0&1 prescaler 0
+    TCFG0 |= 15;                            //prescaler = 15+1
 
-	TCFG1 &= 0xffffff0f;					// set Timer 1 MUX 1/16
-	TCFG1 |= 0x00000030;					// set Timer 1 MUX 1/16
+    TCFG1 &= 0xffffff0f;                    // set Timer 1 MUX 1/16
+    TCFG1 |= 0x00000030;                    // set Timer 1 MUX 1/16
 
-	TCNTB1	 = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
-	TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ;	//if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
+    TCNTB1   = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
+    TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
 
-	TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
-	TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
 }
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{	
-	GPB1_TO_OUT();
-	GPB1_TO_1();
+{
+    GPB1_TO_OUT();
+    GPB1_TO_1();
 
-	GPCUP  = 0x00000000;
-	GPCCON = 0xaaaa02a9;
+    GPCUP  = 0x00000000;
+    GPCCON = 0xaaaa02a9;
 
-	GPDUP  = 0x00000000;
-	GPDCON = 0xaaaaaaaa;
+    GPDUP  = 0x00000000;
+    GPDCON = 0xaaaaaaaa;
 
-#define	M5D(n)	((n)&0x1fffff)
+#define M5D(n)  ((n)&0x1fffff)
 #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
-	LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
-	LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
-	LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
-	LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
+    LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
+    LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
+    LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
+    LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
 #if !defined(LCD_CON5)
 #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0))
 #endif
-	LCDCON5   =  LCD_CON5;
+    LCDCON5   =  LCD_CON5;
 
-	LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) <<  0);
-	LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
-	LCDSADDR3 = LCD_WIDTH;
+    LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) <<  0);
+    LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
+    LCDSADDR3 = LCD_WIDTH;
 
-	LCDINTMSK |= (3);
-	LPCSEL &= (~7) ;
-	TPAL=0;
+    LCDINTMSK |= (3);
+    LPCSEL &= (~7) ;
+    TPAL=0;
 
-	LcdBkLtSet(70) ;
-	lcd_power_enable(0, 1);
-	lcd_envid_on_off(1);
+    LcdBkLtSet(70) ;
+    lcd_power_enable(0, 1);
+    lcd_envid_on_off(1);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:		
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:       
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
+
+    return RT_EOK;
 }
 
-void rt_hw_lcd_init(void)
+int rt_hw_lcd_init(void)
 {
-	rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-	if (lcd == RT_NULL) return; /* no memory yet */
-
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
-	_lcd_info.framebuffer = (void*)_rt_framebuffer;
-	_lcd_info.width = LCD_WIDTH;
-	_lcd_info.height = LCD_HEIGHT;
-
-	/* init device structure */
-	lcd->type = RT_Device_Class_Unknown;
-	lcd->init = rt_lcd_init;
-	lcd->open = RT_NULL;
-	lcd->close = RT_NULL;
-	lcd->control = rt_lcd_control;
-	lcd->user_data = (void*)&_lcd_info;
-	
-	/* register lcd device to RT-Thread */
-	rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
+    if (lcd == RT_NULL) 
+            return -RT_ERROR; /* no memory yet */
+
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = LCD_WIDTH;
+    _lcd_info.height = LCD_HEIGHT;
+
+    /* init device structure */
+    lcd->type = RT_Device_Class_Unknown;
+    lcd->init = rt_lcd_init;
+    lcd->open = RT_NULL;
+    lcd->close = RT_NULL;
+    lcd->control = rt_lcd_control;
+    lcd->user_data = (void*)&_lcd_info;
+    
+    /* register lcd device to RT-Thread */
+    rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
 
+INIT_BOARD_EXPORT(rt_hw_lcd_init);

bsp/mini2440/drivers/lcd_n35.c

@@ -15,7 +15,6 @@
 #include <rtthread.h>
 #include <s3c24x0.h>
 
-#include "lcd.h"
 
 /* LCD driver for N3'5 */
 #define LCD_WIDTH 240
@@ -35,82 +34,82 @@
 #define SCR_XSIZE  LCD_WIDTH
 #define SCR_YSIZE  LCD_HEIGHT
 
-#define RT_HW_LCD_WIDTH		LCD_WIDTH
-#define RT_HW_LCD_HEIGHT	LCD_HEIGHT
+#define RT_HW_LCD_WIDTH     LCD_WIDTH
+#define RT_HW_LCD_HEIGHT    LCD_HEIGHT
 
-#define MVAL		(13)
-#define MVAL_USED 	(0)		//0=each frame   1=rate by MVAL
-#define INVVDEN		(1)		//0=normal       1=inverted
-#define BSWP		(0)		//Byte swap control
-#define HWSWP		(1)		//Half word swap control
+#define MVAL        (13)
+#define MVAL_USED   (0)     //0=each frame   1=rate by MVAL
+#define INVVDEN     (1)     //0=normal       1=inverted
+#define BSWP        (0)     //Byte swap control
+#define HWSWP       (1)     //Half word swap control
 
-#define GPB1_TO_OUT()		(GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
-#define GPB1_TO_1()			(GPBDAT |= 0x0002)
-#define GPB1_TO_0()			(GPBDAT &= 0xfffd)
+#define GPB1_TO_OUT()       (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
+#define GPB1_TO_1()         (GPBDAT |= 0x0002)
+#define GPB1_TO_0()         (GPBDAT &= 0xfffd)
 
 #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
-#define S3C2410_LCDCON1_MMODE	   (1<<7)
-#define S3C2410_LCDCON1_DSCAN4	   (0<<5)
-#define S3C2410_LCDCON1_STN4	   (1<<5)
-#define S3C2410_LCDCON1_STN8	   (2<<5)
-#define S3C2410_LCDCON1_TFT	       (3<<5)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
 
-#define S3C2410_LCDCON1_STN1BPP	   (0<<1)
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
 #define S3C2410_LCDCON1_STN2GREY   (1<<1)
 #define S3C2410_LCDCON1_STN4GREY   (2<<1)
-#define S3C2410_LCDCON1_STN8BPP	   (3<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
 #define S3C2410_LCDCON1_STN12BPP   (4<<1)
 
-#define S3C2410_LCDCON1_TFT1BPP	   (8<<1)
-#define S3C2410_LCDCON1_TFT2BPP	   (9<<1)
-#define S3C2410_LCDCON1_TFT4BPP	   (10<<1)
-#define S3C2410_LCDCON1_TFT8BPP	   (11<<1)
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
 #define S3C2410_LCDCON1_TFT16BPP   (12<<1)
 #define S3C2410_LCDCON1_TFT24BPP   (13<<1)
 
-#define S3C2410_LCDCON1_ENVID	   (1)
+#define S3C2410_LCDCON1_ENVID      (1)
 
 #define S3C2410_LCDCON1_MODEMASK    0x1E
 
-#define S3C2410_LCDCON2_VBPD(x)	    ((x) << 24)
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
 #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
-#define S3C2410_LCDCON2_VFPD(x)	    ((x) << 6)
-#define S3C2410_LCDCON2_VSPW(x)	    ((x) << 0)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
 
 #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
 #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
 #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
 
-#define S3C2410_LCDCON3_HBPD(x)	    ((x) << 19)
-#define S3C2410_LCDCON3_WDLY(x)	    ((x) << 19)
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
 #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
-#define S3C2410_LCDCON3_HFPD(x)	    ((x) << 0)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
 #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
 
 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON4_MVAL(x)	    ((x) << 8)
-#define S3C2410_LCDCON4_HSPW(x)	    ((x) << 0)
-#define S3C2410_LCDCON4_WLH(x)	    ((x) << 0)
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
 
 #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON5_BPP24BL	    (1<<12)
-#define S3C2410_LCDCON5_FRM565	    (1<<11)
-#define S3C2410_LCDCON5_INVVCLK	    (1<<10)
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
 #define S3C2410_LCDCON5_INVVLINE    (1<<9)
 #define S3C2410_LCDCON5_INVVFRAME   (1<<8)
-#define S3C2410_LCDCON5_INVVD	    (1<<7)
-#define S3C2410_LCDCON5_INVVDEN	    (1<<6)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
 #define S3C2410_LCDCON5_INVPWREN    (1<<5)
-#define S3C2410_LCDCON5_INVLEND	    (1<<4)
-#define S3C2410_LCDCON5_PWREN	    (1<<3)
-#define S3C2410_LCDCON5_ENLEND	    (1<<2)
-#define S3C2410_LCDCON5_BSWP	    (1<<1)
-#define S3C2410_LCDCON5_HWSWP	    (1<<0)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
 
-#define	S3C2410_LCDINT_FRSYNC	(1<<1)
+#define S3C2410_LCDINT_FRSYNC       (1<<1)
 
 static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
 //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -129,61 +128,61 @@ static void lcd_power_enable(int invpwren, int pwren)
 
 static void lcd_envid_on_off(int onoff)
 {
-	if(onoff==1)
-		/*ENVID=ON*/
-		LCDCON1|=1;
-	else
-		/*ENVID Off*/
-		LCDCON1 =LCDCON1 & 0x3fffe;
+    if(onoff==1)
+        /*ENVID=ON*/
+        LCDCON1|=1;
+    else
+        /*ENVID Off*/
+        LCDCON1 =LCDCON1 & 0x3fffe;
 }
 
 //********************** BOARD LCD backlight ****************************
 static void LcdBkLtSet(rt_uint32_t HiRatio)
 {
-#define FREQ_PWM1		1000
-	if(!HiRatio)
-	{
-		GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;	//GPB1ÉèÖÃΪoutput
-		GPBDAT &= ~(1<<1);
-		return;
-	}
-	GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
+#define FREQ_PWM1       1000
+    if(!HiRatio)
+    {
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBDAT &= ~(1<<1);
+        return;
+    }
+    GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
 
-	if( HiRatio > 100 ) HiRatio = 100 ;
+    if( HiRatio > 100 ) HiRatio = 100 ;
 
-	TCON = TCON & (~(0xf<<8)) ;			    // clear manual update bit, stop Timer1
+    TCON = TCON & (~(0xf<<8)) ;             // clear manual update bit, stop Timer1
 
-	TCFG0 &= 0xffffff00;					// set Timer 0&1 prescaler 0
-	TCFG0 |= 15;							//prescaler = 15+1
+    TCFG0 &= 0xffffff00;                    // set Timer 0&1 prescaler 0
+    TCFG0 |= 15;                            //prescaler = 15+1
 
-	TCFG1 &= 0xffffff0f;					// set Timer 1 MUX 1/16
-	TCFG1 |= 0x00000030;					// set Timer 1 MUX 1/16
+    TCFG1 &= 0xffffff0f;                    // set Timer 1 MUX 1/16
+    TCFG1 |= 0x00000030;                    // set Timer 1 MUX 1/16
 
-	TCNTB1	 = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
-	TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ;	//if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
+    TCNTB1   = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
+    TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
 
-	TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
-	TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
 }
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{	
-	GPB1_TO_OUT();
-	GPB1_TO_1();
+{   
+    GPB1_TO_OUT();
+    GPB1_TO_1();
 
-	GPCUP  = 0x00000000;
-	GPCCON = 0xaaaa02a9;
+    GPCUP  = 0x00000000;
+    GPCCON = 0xaaaa02a9;
 
-	GPDUP  = 0x00000000;
-	GPDCON = 0xaaaaaaaa;
+    GPDUP  = 0x00000000;
+    GPDCON = 0xaaaaaaaa;
 
-#define	M5D(n)	((n)&0x1fffff)
+#define M5D(n)  ((n)&0x1fffff)
 #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
-	LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
-   	LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
-   	LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
-   	LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
+    LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
+    LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
+    LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
+    LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
 #if !defined(LCD_CON5)
     #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0))
 #endif
@@ -193,57 +192,59 @@ static rt_err_t rt_lcd_init (rt_device_t dev)
     LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
     LCDSADDR3 = LCD_WIDTH;
 
-	LCDINTMSK |= (3);
-	LPCSEL &= (~7) ;
-	TPAL=0;
+    LCDINTMSK |= (3);
+    LPCSEL &= (~7) ;
+    TPAL=0;
 
-	LcdBkLtSet(70) ;
-	lcd_power_enable(0, 1);
-	lcd_envid_on_off(1);
+    LcdBkLtSet(70) ;
+    lcd_power_enable(0, 1);
+    lcd_envid_on_off(1);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:		
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:       
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
+
+    return RT_EOK;
 }
 
-void rt_hw_lcd_init(void)
+int rt_hw_lcd_init(void)
 {
-	rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-	if (lcd == RT_NULL) return; /* no memory yet */
-
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
-	_lcd_info.framebuffer = (void*)_rt_framebuffer;
-	_lcd_info.width = LCD_WIDTH;
-	_lcd_info.height = LCD_HEIGHT;
-
-	/* init device structure */
-	lcd->type = RT_Device_Class_Unknown;
-	lcd->init = rt_lcd_init;
-	lcd->open = RT_NULL;
-	lcd->close = RT_NULL;
-	lcd->control = rt_lcd_control;
-	lcd->user_data = (void*)&_lcd_info;
-	
-	/* register lcd device to RT-Thread */
-	rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
+    if (lcd == RT_NULL) 
+            return -RT_ERROR; /* no memory yet */
+
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = LCD_WIDTH;
+    _lcd_info.height = LCD_HEIGHT;
+
+    /* init device structure */
+    lcd->type = RT_Device_Class_Unknown;
+    lcd->init = rt_lcd_init;
+    lcd->open = RT_NULL;
+    lcd->close = RT_NULL;
+    lcd->control = rt_lcd_control;
+    lcd->user_data = (void*)&_lcd_info;
+    
+    /* register lcd device to RT-Thread */
+    rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
 
+INIT_BOARD_EXPORT(rt_hw_lcd_init);

bsp/mini2440/drivers/lcd_t35.c

@@ -15,7 +15,6 @@
 #include <rtthread.h>
 
 #include <s3c24x0.h>
-#include "lcd.h"
 
 /* LCD driver for T3'5 */
 #define LCD_WIDTH 240
@@ -35,82 +34,82 @@
 #define SCR_XSIZE  LCD_WIDTH
 #define SCR_YSIZE  LCD_HEIGHT
 
-#define RT_HW_LCD_WIDTH		LCD_WIDTH
-#define RT_HW_LCD_HEIGHT	LCD_HEIGHT
+#define RT_HW_LCD_WIDTH     LCD_WIDTH
+#define RT_HW_LCD_HEIGHT    LCD_HEIGHT
 
-#define MVAL		(13)
-#define MVAL_USED 	(0)		//0=each frame   1=rate by MVAL
-#define INVVDEN		(1)		//0=normal       1=inverted
-#define BSWP		(0)		//Byte swap control
-#define HWSWP		(1)		//Half word swap control
+#define MVAL        (13)
+#define MVAL_USED   (0)     //0=each frame   1=rate by MVAL
+#define INVVDEN     (1)     //0=normal       1=inverted
+#define BSWP        (0)     //Byte swap control
+#define HWSWP       (1)     //Half word swap control
 
-#define GPB1_TO_OUT()		(GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
-#define GPB1_TO_1()			(GPBDAT |= 0x0002)
-#define GPB1_TO_0()			(GPBDAT &= 0xfffd)
+#define GPB1_TO_OUT()       (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
+#define GPB1_TO_1()         (GPBDAT |= 0x0002)
+#define GPB1_TO_0()         (GPBDAT &= 0xfffd)
 
 #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
-#define S3C2410_LCDCON1_MMODE	   (1<<7)
-#define S3C2410_LCDCON1_DSCAN4	   (0<<5)
-#define S3C2410_LCDCON1_STN4	   (1<<5)
-#define S3C2410_LCDCON1_STN8	   (2<<5)
-#define S3C2410_LCDCON1_TFT	       (3<<5)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
 
-#define S3C2410_LCDCON1_STN1BPP	   (0<<1)
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
 #define S3C2410_LCDCON1_STN2GREY   (1<<1)
 #define S3C2410_LCDCON1_STN4GREY   (2<<1)
-#define S3C2410_LCDCON1_STN8BPP	   (3<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
 #define S3C2410_LCDCON1_STN12BPP   (4<<1)
 
-#define S3C2410_LCDCON1_TFT1BPP	   (8<<1)
-#define S3C2410_LCDCON1_TFT2BPP	   (9<<1)
-#define S3C2410_LCDCON1_TFT4BPP	   (10<<1)
-#define S3C2410_LCDCON1_TFT8BPP	   (11<<1)
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
 #define S3C2410_LCDCON1_TFT16BPP   (12<<1)
 #define S3C2410_LCDCON1_TFT24BPP   (13<<1)
 
-#define S3C2410_LCDCON1_ENVID	   (1)
+#define S3C2410_LCDCON1_ENVID      (1)
 
 #define S3C2410_LCDCON1_MODEMASK    0x1E
 
-#define S3C2410_LCDCON2_VBPD(x)	    ((x) << 24)
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
 #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
-#define S3C2410_LCDCON2_VFPD(x)	    ((x) << 6)
-#define S3C2410_LCDCON2_VSPW(x)	    ((x) << 0)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
 
 #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
 #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
 #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
 
-#define S3C2410_LCDCON3_HBPD(x)	    ((x) << 19)
-#define S3C2410_LCDCON3_WDLY(x)	    ((x) << 19)
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
 #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
-#define S3C2410_LCDCON3_HFPD(x)	    ((x) << 0)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
 #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
 
 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON4_MVAL(x)	    ((x) << 8)
-#define S3C2410_LCDCON4_HSPW(x)	    ((x) << 0)
-#define S3C2410_LCDCON4_WLH(x)	    ((x) << 0)
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
 
 #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON5_BPP24BL	    (1<<12)
-#define S3C2410_LCDCON5_FRM565	    (1<<11)
-#define S3C2410_LCDCON5_INVVCLK	    (1<<10)
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
 #define S3C2410_LCDCON5_INVVLINE    (1<<9)
 #define S3C2410_LCDCON5_INVVFRAME   (1<<8)
-#define S3C2410_LCDCON5_INVVD	    (1<<7)
-#define S3C2410_LCDCON5_INVVDEN	    (1<<6)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
 #define S3C2410_LCDCON5_INVPWREN    (1<<5)
-#define S3C2410_LCDCON5_INVLEND	    (1<<4)
-#define S3C2410_LCDCON5_PWREN	    (1<<3)
-#define S3C2410_LCDCON5_ENLEND	    (1<<2)
-#define S3C2410_LCDCON5_BSWP	    (1<<1)
-#define S3C2410_LCDCON5_HWSWP	    (1<<0)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
 
-#define	S3C2410_LCDINT_FRSYNC	(1<<1)
+#define S3C2410_LCDINT_FRSYNC       (1<<1)
 
 volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
 //volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -129,122 +128,124 @@ static void lcd_power_enable(int invpwren, int pwren)
 
 static void lcd_envid_on_off(int onoff)
 {
-	if(onoff==1)
-		/*ENVID=ON*/
-		LCDCON1|=1;
-	else
-		/*ENVID Off*/
-		LCDCON1 =LCDCON1 & 0x3fffe;
+    if(onoff==1)
+        /*ENVID=ON*/
+        LCDCON1|=1;
+    else
+        /*ENVID Off*/
+        LCDCON1 =LCDCON1 & 0x3fffe;
 }
 
 //********************** BOARD LCD backlight ****************************
 static void LcdBkLtSet(rt_uint32_t HiRatio)
 {
-#define FREQ_PWM1		1000
-	if(!HiRatio)
-	{
-		GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;	//GPB1ÉèÖÃΪoutput
-		GPBDAT &= ~(1<<1);
-		return;
-	}
-	GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
+#define FREQ_PWM1       1000
+    if(!HiRatio)
+    {
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBDAT &= ~(1<<1);
+        return;
+    }
+    GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
 
-	if( HiRatio > 100 ) HiRatio = 100 ;
+    if( HiRatio > 100 ) HiRatio = 100 ;
 
-	TCON = TCON & (~(0xf<<8)) ;			    // clear manual update bit, stop Timer1
+    TCON = TCON & (~(0xf<<8)) ;             // clear manual update bit, stop Timer1
 
-	TCFG0 &= 0xffffff00;					// set Timer 0&1 prescaler 0
-	TCFG0 |= 15;							//prescaler = 15+1
+    TCFG0 &= 0xffffff00;                    // set Timer 0&1 prescaler 0
+    TCFG0 |= 15;                            //prescaler = 15+1
 
-	TCFG1 &= 0xffffff0f;					// set Timer 1 MUX 1/16
-	TCFG1 |= 0x00000030;					// set Timer 1 MUX 1/16
+    TCFG1 &= 0xffffff0f;                    // set Timer 1 MUX 1/16
+    TCFG1 |= 0x00000030;                    // set Timer 1 MUX 1/16
 
-	TCNTB1	 = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
-	TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ;	//if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
+    TCNTB1   = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
+    TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
 
-	TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
-	TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
 }
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{	
-	GPB1_TO_OUT();
-	GPB1_TO_1();
+{   
+    GPB1_TO_OUT();
+    GPB1_TO_1();
 
-	GPCUP  = 0x00000000;
-	GPCCON = 0xaaaa02a9;
+    GPCUP  = 0x00000000;
+    GPCCON = 0xaaaa02a9;
 
-	GPDUP  = 0x00000000;
-	GPDCON = 0xaaaaaaaa;
+    GPDUP  = 0x00000000;
+    GPDCON = 0xaaaaaaaa;
 
-#define	M5D(n)	((n)&0x1fffff)
+#define M5D(n)  ((n)&0x1fffff)
 #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
-	LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
-   	LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
-   	LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
-   	LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
+    LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
+    LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
+    LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
+    LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
 
 #if !defined(LCD_CON5)
 #define LCD_CON5 ((1<<11) | (1 << 9) | (1 << 8) | (1 << 3) | (1 << 0))
 #endif
-	LCDCON5   =  LCD_CON5;
+    LCDCON5   =  LCD_CON5;
 
-	LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) <<  0);
-	LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
-	LCDSADDR3 = LCD_WIDTH;
+    LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) <<  0);
+    LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
+    LCDSADDR3 = LCD_WIDTH;
 
-	LCDINTMSK |= (3);
-	LPCSEL &= (~7) ;
-	TPAL=0;
+    LCDINTMSK |= (3);
+    LPCSEL &= (~7) ;
+    TPAL=0;
 
-	LcdBkLtSet(70) ;
-	lcd_power_enable(0, 1);
-	lcd_envid_on_off(1);
+    LcdBkLtSet(70) ;
+    lcd_power_enable(0, 1);
+    lcd_envid_on_off(1);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:		
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:       
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
+
+    return RT_EOK;
 }
 
-void rt_hw_lcd_init(void)
+int rt_hw_lcd_init(void)
 {
-	rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-	if (lcd == RT_NULL) return; /* no memory yet */
-
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
-	_lcd_info.framebuffer = (void*)_rt_framebuffer;
-	_lcd_info.width = LCD_WIDTH;
-	_lcd_info.height = LCD_HEIGHT;
-
-	/* init device structure */
-	lcd->type = RT_Device_Class_Unknown;
-	lcd->init = rt_lcd_init;
-	lcd->open = RT_NULL;
-	lcd->close = RT_NULL;
-	lcd->control = rt_lcd_control;
-	lcd->user_data = (void*)&_lcd_info;
-	
-	/* register lcd device to RT-Thread */
-	rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
+    if (lcd == RT_NULL) 
+        return -RT_ERROR; /* no memory yet */
+
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = LCD_WIDTH;
+    _lcd_info.height = LCD_HEIGHT;
+
+    /* init device structure */
+    lcd->type = RT_Device_Class_Unknown;
+    lcd->init = rt_lcd_init;
+    lcd->open = RT_NULL;
+    lcd->close = RT_NULL;
+    lcd->control = rt_lcd_control;
+    lcd->user_data = (void*)&_lcd_info;
+    
+    /* register lcd device to RT-Thread */
+    rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
 
+INIT_BOARD_EXPORT(rt_hw_lcd_init);

bsp/mini2440/drivers/lcd_t43.c

@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-12     Jonne        first version from 4.3 inch lcd(480x272)
+ */
+#include <rtthread.h>
+#include <s3c24x0.h>
+
+/* LCD driver for N3'5 */
+#define LCD_WIDTH 480
+#define LCD_HEIGHT 272
+#define LCD_PIXCLOCK 4
+
+#define LCD_RIGHT_MARGIN 2
+#define LCD_LEFT_MARGIN 2
+#define LCD_HSYNC_LEN 41
+
+#define LCD_UPPER_MARGIN 2
+#define LCD_LOWER_MARGIN 2
+#define LCD_VSYNC_LEN 10
+
+#define LCD_XSIZE  LCD_WIDTH
+#define LCD_YSIZE  LCD_HEIGHT
+#define SCR_XSIZE  LCD_WIDTH
+#define SCR_YSIZE  LCD_HEIGHT
+
+#define RT_HW_LCD_WIDTH         LCD_WIDTH
+#define RT_HW_LCD_HEIGHT        LCD_HEIGHT
+
+#define MVAL        (13)
+#define MVAL_USED   (0)     //0=each frame   1=rate by MVAL
+#define INVVDEN     (1)     //0=normal       1=inverted
+#define BSWP        (0)     //Byte swap control
+#define HWSWP       (1)     //Half word swap control
+
+#define GPB1_TO_OUT()       (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
+#define GPB1_TO_1()         (GPBDAT |= 0x0002)
+#define GPB1_TO_0()         (GPBDAT &= 0xfffd)
+
+#define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
+
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
+#define S3C2410_LCDCON1_STN2GREY   (1<<1)
+#define S3C2410_LCDCON1_STN4GREY   (2<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
+#define S3C2410_LCDCON1_STN12BPP   (4<<1)
+
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
+#define S3C2410_LCDCON1_TFT16BPP   (12<<1)
+#define S3C2410_LCDCON1_TFT24BPP   (13<<1)
+
+#define S3C2410_LCDCON1_ENVID      (1)
+
+#define S3C2410_LCDCON1_MODEMASK    0x1E
+
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
+#define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
+
+#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
+#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
+#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
+
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
+#define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
+#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
+
+#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
+#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
+
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
+
+#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
+
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
+#define S3C2410_LCDCON5_INVVLINE    (1<<9)
+#define S3C2410_LCDCON5_INVVFRAME   (1<<8)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
+#define S3C2410_LCDCON5_INVPWREN    (1<<5)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
+
+#define S3C2410_LCDINT_FRSYNC       (1<<1)
+
+static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
+//static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
+static struct rt_device_graphic_info _lcd_info;
+
+static void lcd_power_enable(int invpwren, int pwren)
+{
+    //GPG4 is setted as LCD_PWREN
+    GPGUP  = GPGUP | (1<<4); // Pull-up disable
+    GPGCON = GPGCON | (3<<8); //GPG4=LCD_PWREN
+
+    //Enable LCD POWER ENABLE Function
+    LCDCON5 = LCDCON5&(~(1<<3))|(pwren<<3);   // PWREN
+    LCDCON5 = LCDCON5&(~(1<<5))|(invpwren<<5);   // INVPWREN
+}
+
+static void lcd_envid_on_off(int onoff)
+{
+    if(onoff==1)
+        /*ENVID=ON*/
+        LCDCON1|=1;
+    else
+        /*ENVID Off*/
+        LCDCON1 =LCDCON1 & 0x3fffe;
+}
+
+//********************** BOARD LCD backlight ****************************
+static void LcdBkLtSet(rt_uint32_t HiRatio)
+{
+#define FREQ_PWM1       1000
+    if(!HiRatio)
+    {
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBDAT &= ~(1<<1);
+        return;
+    }
+    GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
+
+    if( HiRatio > 100 ) HiRatio = 100 ;
+
+    TCON = TCON & (~(0xf<<8)) ;             // clear manual update bit, stop Timer1
+
+    TCFG0 &= 0xffffff00;                    // set Timer 0&1 prescaler 0
+    TCFG0 |= 15;                            //prescaler = 15+1
+
+    TCFG1 &= 0xffffff0f;                    // set Timer 1 MUX 1/16
+    TCFG1 |= 0x00000030;                    // set Timer 1 MUX 1/16
+
+    TCNTB1   = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
+    TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
+
+    TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
+}
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_lcd_init (rt_device_t dev)
+{   
+    GPB1_TO_OUT();
+    GPB1_TO_1();
+
+    GPCUP  = 0x00000000;
+    GPCCON = 0xaaaa02a9;
+
+    GPDUP  = 0x00000000;
+    GPDCON = 0xaaaaaaaa;
+
+#define M5D(n)  ((n)&0x1fffff)
+#define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
+    LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
+    LCDCON2 = ((LCD_UPPER_MARGIN - 1) << 24) | ((LCD_HEIGHT - 1) << 14) | ((LCD_LOWER_MARGIN - 1) << 6) | ((LCD_VSYNC_LEN - 1) << 0);
+    LCDCON3 = ((LCD_RIGHT_MARGIN - 1) << 19) | ((LCD_WIDTH  - 1) <<  8) | ((LCD_LEFT_MARGIN - 1) << 0);
+    LCDCON4 = (13 <<  8) | ((LCD_HSYNC_LEN - 1) << 0);
+#if !defined(LCD_CON5)
+    #define LCD_CON5 ((1<<11) | (0<<10) | (1<<9) | (1<<8) | (1<<0))
+#endif
+    LCDCON5   =  LCD_CON5;
+
+    LCDSADDR1 = ((LCD_ADDR >> 22) << 21) | ((M5D(LCD_ADDR >> 1)) <<  0);
+    LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
+    LCDSADDR3 = LCD_WIDTH;
+
+    LCDINTMSK |= (3);
+    LPCSEL &= (~7) ;
+    TPAL=0;
+
+    LcdBkLtSet(70) ;
+    lcd_power_enable(0, 1);
+    lcd_envid_on_off(1);
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
+{
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:       
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
+
+    return RT_EOK;
+}
+
+int rt_hw_lcd_init(void)
+{
+    rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
+    if (lcd == RT_NULL) 
+            return -RT_ERROR; /* no memory yet */
+
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = LCD_WIDTH;
+    _lcd_info.height = LCD_HEIGHT;
+
+    /* init device structure */
+    lcd->type = RT_Device_Class_Unknown;
+    lcd->init = rt_lcd_init;
+    lcd->open = RT_NULL;
+    lcd->close = RT_NULL;
+    lcd->control = rt_lcd_control;
+    lcd->user_data = (void*)&_lcd_info;
+    
+    /* register lcd device to RT-Thread */
+    rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+}
+
+INIT_BOARD_EXPORT(rt_hw_lcd_init);

bsp/mini2440/drivers/lcd_x35.c

@@ -17,7 +17,6 @@
 #include <rtthread.h>
 #include <s3c24x0.h>
 
-#include "lcd.h"
 
 /* LCD driver for X3'5 */
 #define LCD_WIDTH 240   // xres
@@ -37,82 +36,82 @@
 #define SCR_XSIZE  LCD_WIDTH
 #define SCR_YSIZE  LCD_HEIGHT
 
-#define RT_HW_LCD_WIDTH		LCD_WIDTH
-#define RT_HW_LCD_HEIGHT	LCD_HEIGHT
+#define RT_HW_LCD_WIDTH     LCD_WIDTH
+#define RT_HW_LCD_HEIGHT    LCD_HEIGHT
 
-#define MVAL		(13)
-#define MVAL_USED 	(0)		//0=each frame   1=rate by MVAL
-#define INVVDEN		(1)		//0=normal       1=inverted
-#define BSWP		(0)		//Byte swap control
-#define HWSWP		(1)		//Half word swap control
+#define MVAL        (13)
+#define MVAL_USED   (0)     //0=each frame   1=rate by MVAL
+#define INVVDEN     (1)     //0=normal       1=inverted
+#define BSWP        (0)     //Byte swap control
+#define HWSWP       (1)     //Half word swap control
 
-#define GPB1_TO_OUT()		(GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
-#define GPB1_TO_1()			(GPBDAT |= 0x0002)
-#define GPB1_TO_0()			(GPBDAT &= 0xfffd)
+#define GPB1_TO_OUT()       (GPBUP &= 0xfffd, GPBCON &= 0xfffffff3, GPBCON |= 0x00000004)
+#define GPB1_TO_1()         (GPBDAT |= 0x0002)
+#define GPB1_TO_0()         (GPBDAT &= 0xfffd)
 
 #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
-#define S3C2410_LCDCON1_MMODE	   (1<<7)
-#define S3C2410_LCDCON1_DSCAN4	   (0<<5)
-#define S3C2410_LCDCON1_STN4	   (1<<5)
-#define S3C2410_LCDCON1_STN8	   (2<<5)
-#define S3C2410_LCDCON1_TFT	       (3<<5)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
 
-#define S3C2410_LCDCON1_STN1BPP	   (0<<1)
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
 #define S3C2410_LCDCON1_STN2GREY   (1<<1)
 #define S3C2410_LCDCON1_STN4GREY   (2<<1)
-#define S3C2410_LCDCON1_STN8BPP	   (3<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
 #define S3C2410_LCDCON1_STN12BPP   (4<<1)
 
-#define S3C2410_LCDCON1_TFT1BPP	   (8<<1)
-#define S3C2410_LCDCON1_TFT2BPP	   (9<<1)
-#define S3C2410_LCDCON1_TFT4BPP	   (10<<1)
-#define S3C2410_LCDCON1_TFT8BPP	   (11<<1)
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
 #define S3C2410_LCDCON1_TFT16BPP   (12<<1)
 #define S3C2410_LCDCON1_TFT24BPP   (13<<1)
 
-#define S3C2410_LCDCON1_ENVID	   (1)
+#define S3C2410_LCDCON1_ENVID      (1)
 
 #define S3C2410_LCDCON1_MODEMASK    0x1E
 
-#define S3C2410_LCDCON2_VBPD(x)	    ((x) << 24)
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
 #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
-#define S3C2410_LCDCON2_VFPD(x)	    ((x) << 6)
-#define S3C2410_LCDCON2_VSPW(x)	    ((x) << 0)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
 
 #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
 #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
 #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
 
-#define S3C2410_LCDCON3_HBPD(x)	    ((x) << 19)
-#define S3C2410_LCDCON3_WDLY(x)	    ((x) << 19)
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
 #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
-#define S3C2410_LCDCON3_HFPD(x)	    ((x) << 0)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
 #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
 
 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON4_MVAL(x)	    ((x) << 8)
-#define S3C2410_LCDCON4_HSPW(x)	    ((x) << 0)
-#define S3C2410_LCDCON4_WLH(x)	    ((x) << 0)
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
 
 #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
 
-#define S3C2410_LCDCON5_BPP24BL	    (1<<12)
-#define S3C2410_LCDCON5_FRM565	    (1<<11)
-#define S3C2410_LCDCON5_INVVCLK	    (1<<10)
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
 #define S3C2410_LCDCON5_INVVLINE    (1<<9)
 #define S3C2410_LCDCON5_INVVFRAME   (1<<8)
-#define S3C2410_LCDCON5_INVVD	    (1<<7)
-#define S3C2410_LCDCON5_INVVDEN	    (1<<6)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
 #define S3C2410_LCDCON5_INVPWREN    (1<<5)
-#define S3C2410_LCDCON5_INVLEND	    (1<<4)
-#define S3C2410_LCDCON5_PWREN	    (1<<3)
-#define S3C2410_LCDCON5_ENLEND	    (1<<2)
-#define S3C2410_LCDCON5_BSWP	    (1<<1)
-#define S3C2410_LCDCON5_HWSWP	    (1<<0)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
 
-#define	S3C2410_LCDINT_FRSYNC	(1<<1)
+#define S3C2410_LCDINT_FRSYNC       (1<<1)
 
 static volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
 //static volatile rt_uint16_t _rt_hw_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
@@ -131,61 +130,61 @@ static void lcd_power_enable(int invpwren, int pwren)
 
 static void lcd_envid_on_off(int onoff)
 {
-	if(onoff==1)
-		/*ENVID=ON*/
-		LCDCON1|=1;
-	else
-		/*ENVID Off*/
-		LCDCON1 =LCDCON1 & 0x3fffe;
+    if(onoff==1)
+        /*ENVID=ON*/
+        LCDCON1|=1;
+    else
+        /*ENVID Off*/
+        LCDCON1 =LCDCON1 & 0x3fffe;
 }
 
 //********************** BOARD LCD backlight ****************************
 static void LcdBkLtSet(rt_uint32_t HiRatio)
 {
-#define FREQ_PWM1		1000
-	if(!HiRatio)
-	{
-		GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;	//GPB1ÉèÖÃΪoutput
-		GPBDAT &= ~(1<<1);
-		return;
-	}
-	GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
+#define FREQ_PWM1       1000
+    if(!HiRatio)
+    {
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBDAT &= ~(1<<1);
+        return;
+    }
+    GPBCON = GPBCON & (~(3<<2)) | (2<<2) ;
 
-	if( HiRatio > 100 ) HiRatio = 100 ;
+    if( HiRatio > 100 ) HiRatio = 100 ;
 
-	TCON = TCON & (~(0xf<<8)) ;			    // clear manual update bit, stop Timer1
+    TCON = TCON & (~(0xf<<8)) ;             // clear manual update bit, stop Timer1
 
-	TCFG0 &= 0xffffff00;					// set Timer 0&1 prescaler 0
-	TCFG0 |= 15;							//prescaler = 15+1
+    TCFG0 &= 0xffffff00;                    // set Timer 0&1 prescaler 0
+    TCFG0 |= 15;                            //prescaler = 15+1
 
-	TCFG1 &= 0xffffff0f;					// set Timer 1 MUX 1/16
-	TCFG1 |= 0x00000030;					// set Timer 1 MUX 1/16
+    TCFG1 &= 0xffffff0f;                    // set Timer 1 MUX 1/16
+    TCFG1 |= 0x00000030;                    // set Timer 1 MUX 1/16
 
-	TCNTB1	 = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
-	TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ;	//if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
+    TCNTB1   = ( 100000000>>8 )/FREQ_PWM1;  //if set inverter off, when TCNT2<=TCMP2, TOUT is high, TCNT2>TCMP2, TOUT is low
+    TCMPB1  = ( TCNTB1*(100-HiRatio))/100 ; //if set inverter on,  when TCNT2<=TCMP2, TOUT is low,  TCNT2>TCMP2, TOUT is high
 
-	TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
-	TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0e<<8) ;
+    TCON = TCON & (~(0xf<<8)) | (0x0d<<8) ;
 }
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{	
-	GPB1_TO_OUT();
-	GPB1_TO_1();
+{   
+    GPB1_TO_OUT();
+    GPB1_TO_1();
 
-	GPCUP  = 0x00000000;
-	GPCCON = 0xaaaa02a9;
+    GPCUP  = 0x00000000;
+    GPCCON = 0xaaaa02a9;
 
-	GPDUP  = 0x00000000;
-	GPDCON = 0xaaaaaaaa;
+    GPDUP  = 0x00000000;
+    GPDCON = 0xaaaaaaaa;
 
-#define	M5D(n)	((n)&0x1fffff)
+#define M5D(n)  ((n)&0x1fffff)
 #define LCD_ADDR ((rt_uint32_t)_rt_framebuffer)
-	LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
-   	LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
-   	LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
-   	LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
+    LCDCON1 = (LCD_PIXCLOCK << 8) | (3 <<  5) | (12 << 1);
+    LCDCON2 = (LCD_UPPER_MARGIN << 24) | ((LCD_HEIGHT - 1) << 14) | (LCD_LOWER_MARGIN << 6) | (LCD_VSYNC_LEN << 0);
+    LCDCON3 = (LCD_RIGHT_MARGIN << 19) | ((LCD_WIDTH  - 1) <<  8) | (LCD_LEFT_MARGIN << 0);
+    LCDCON4 = (13 <<  8) | (LCD_HSYNC_LEN << 0);
 
 #define LCD_CON5 (S3C2410_LCDCON5_FRM565 | S3C2410_LCDCON5_INVVDEN | S3C2410_LCDCON5_INVVFRAME | \
 S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2410_LCDCON5_HWSWP)
@@ -199,57 +198,59 @@ S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVCLK | S3C2410_LCDCON5_PWREN| S3C2
     LCDSADDR2 = M5D((LCD_ADDR + LCD_WIDTH * LCD_HEIGHT * 2) >> 1);
     LCDSADDR3 = LCD_WIDTH;
 
-	LCDINTMSK |= (3);
-	LPCSEL &= (~7) ;
-	TPAL=0;
+    LCDINTMSK |= (3);
+    LPCSEL &= (~7) ;
+    TPAL=0;
 
-	LcdBkLtSet(70) ;
-	lcd_power_enable(0, 1);
-	lcd_envid_on_off(1);
+    LcdBkLtSet(70) ;
+    lcd_power_enable(0, 1);
+    lcd_envid_on_off(1);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:		
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:       
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
+
+    return RT_EOK;
 }
 
-void rt_hw_lcd_init(void)
+int rt_hw_lcd_init(void)
 {
-	rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-	if (lcd == RT_NULL) return; /* no memory yet */
-
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
-	_lcd_info.framebuffer = (void*)_rt_framebuffer;
-	_lcd_info.width = LCD_WIDTH;
-	_lcd_info.height = LCD_HEIGHT;
-
-	/* init device structure */
-	lcd->type = RT_Device_Class_Unknown;
-	lcd->init = rt_lcd_init;
-	lcd->open = RT_NULL;
-	lcd->close = RT_NULL;
-	lcd->control = rt_lcd_control;
-	lcd->user_data = (void*)&_lcd_info;
-	
-	/* register lcd device to RT-Thread */
-	rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
+    if (lcd == RT_NULL) 
+            return -RT_ERROR; /* no memory yet */
+
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = LCD_WIDTH;
+    _lcd_info.height = LCD_HEIGHT;
+
+    /* init device structure */
+    lcd->type = RT_Device_Class_Unknown;
+    lcd->init = rt_lcd_init;
+    lcd->open = RT_NULL;
+    lcd->close = RT_NULL;
+    lcd->control = rt_lcd_control;
+    lcd->user_data = (void*)&_lcd_info;
+    
+    /* register lcd device to RT-Thread */
+    rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
 
+INIT_BOARD_EXPORT(rt_hw_lcd_init);

bsp/mini2440/drivers/s3cmci.c

@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     Jonne        first version for s3c2440 mmc controller
+ */
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drivers/mmcsd_core.h>
+#include <s3c24x0.h>
+
+#define S3C_PCLK	50000000
+
+
+static void s3c_mmc_set_clk(struct rt_mmcsd_host *host, rt_uint32_t clock)
+{
+    rt_uint32_t prescale;
+    rt_uint32_t realClk;
+
+    for(prescale = 0; prescale < 256; ++prescale) 
+    {
+        realClk = S3C_PCLK / (1 + prescale);
+        if(realClk <= clock) 
+        {
+            break;
+        }
+    }
+
+    SDIPRE = prescale;
+    host->io_cfg.clock = realClk;
+}
+
+static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
+{
+    rt_uint32_t ccon;
+    rt_uint32_t cmdSta;
+
+    SDICARG = cmd->arg;
+
+    ccon = cmd->cmd_code & 0x3f;
+    ccon |= (0 << 7) | (1 << 6); /* two start bits*/
+    ccon |= (1 << 8);/* command start*/
+
+    if(cmd->flags & 0xF)
+    {
+        // Need response
+        ccon |= (1 << 9);
+    }
+
+    if((cmd->flags & 0xF) == RESP_R2)
+    {
+        // R2 need 136bit response
+        ccon |= (1 << 10);
+    }
+
+    SDICCON = ccon; /* start cmd */
+
+    if(cmd->flags & 0xF) 
+    {
+        cmdSta = SDICSTA;
+        while((cmdSta & 0x200) != 0x200 && (cmdSta & 0x400) != 0x400) 
+        {
+            cmdSta = SDICSTA;
+        }
+
+        if((cmdSta & 0x1000) == 0x1000 && (cmd->flags & 0xF) != RESP_R3 && (cmd->flags & 0xF) != RESP_R4) 
+        {
+            // crc error, but R3 R4 ignore it
+            SDICSTA = cmdSta;
+            return -RT_ERROR;
+        }
+
+        if((cmdSta & 0xF00) != 0xa00)
+        {
+            SDICSTA = cmdSta;
+            return -RT_ERROR;
+        }
+
+        cmd->resp[0] = SDIRSP0;
+        if((cmd->flags & 0xF) == RESP_R2) 
+        {
+            cmd->resp[1] = SDIRSP1;
+            cmd->resp[2] = SDIRSP2;
+            cmd->resp[3] = SDIRSP3;
+        }
+    }
+    else
+    {
+        cmdSta = SDICSTA;
+        while((cmdSta & 0x800) != 0x800)
+        {
+            cmdSta = SDICSTA;
+        } 
+    }
+
+    SDICSTA = cmdSta; // clear current status
+
+    return RT_EOK;
+
+}
+
+static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data)
+{
+    rt_uint32_t status;
+    rt_uint32_t xfer_size;
+    rt_uint32_t handled_size = 0;
+    rt_uint32_t *pBuf = RT_NULL;
+
+
+    if(data == RT_NULL)
+    {
+        return -RT_ERROR;
+    }
+
+    xfer_size = data->blks * data->blksize;
+
+    pBuf = data->buf;
+    if(data->flags & DATA_DIR_READ)
+    {
+        while(handled_size < xfer_size)
+        {
+            if ((SDIDSTA & 0x20) == 0x20)
+            {
+                SDIDSTA = (0x1 << 0x5);
+                break; 
+            }
+
+            status = SDIFSTA;
+            if ((status & 0x1000) == 0x1000)
+            {
+                *pBuf++ = SDIDAT;
+                handled_size += 4;
+            }
+        }
+    }
+    else 
+    {
+        while(handled_size < xfer_size)
+        {
+            status = SDIFSTA;
+            if ((status & 0x2000) == 0x2000)
+            {
+                SDIDAT = *pBuf++;
+                handled_size += 4;
+            }
+        }
+    }
+
+    // wait for end
+    status = SDIDSTA;
+    while((status & 0x30) == 0)
+    {
+        status = SDIDSTA;
+    }
+    SDIDSTA = status;
+
+    if ((status & 0xfc) != 0x10)
+    {
+        return -RT_ERROR;
+    }
+
+    SDIDCON = SDIDCON & ~(7<<12);
+    SDIFSTA = SDIFSTA & 0x200;
+    SDIDSTA = 0x10;
+
+    return RT_EOK;
+}
+static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    rt_uint32_t ret;
+    struct rt_mmcsd_cmd *cmd;
+    struct rt_mmcsd_data *data;
+    rt_uint32_t val;
+    rt_uint32_t tryCnt = 0;
+
+    if(req->cmd == RT_NULL)
+    {
+        goto out;
+    }
+    cmd = req->cmd;
+
+    /* prepare for data transfer*/
+    if(req->data != RT_NULL) 
+    {
+        SDIFSTA = SDIFSTA | (1<<16); // reset fifo 
+
+        while(SDIDSTA & 0x03)
+        {
+            if(tryCnt++ > 500)
+            {
+                break;
+                SDIDSTA = SDIDSTA;
+            }
+        }
+
+        data = req->data;
+
+        if((data->blksize & 0x3) != 0)
+        {
+            goto out;
+        }
+
+        val = (2 << 22)  //word transfer
+                  | (1 << 20) // transmet after response
+                  | (1 << 19) // reciveve after command sent
+                  | (1 << 17) // block data transfer
+                  | (1 << 14); // data start
+
+        if(host->io_cfg.bus_width == MMCSD_BUS_WIDTH_4)
+        {
+            val |= (1 << 16); // wide bus mode(4bit data)
+        }
+
+        if(data->flags & DATA_DIR_READ) 
+        {
+            // for data read 
+            val |= (2 << 12);
+        }
+        else 
+        {
+            val |= (3 << 12);
+        }
+
+        val |= (data->blks & 0xFFF);
+
+        SDIDCON = val;
+
+        SDIBSIZE = data->blksize;
+        SDIDTIMER = 0x7fffff;
+    }
+
+    ret = s3c_mmc_send_cmd(host,req->cmd);
+    if(ret != RT_EOK) {
+        cmd->err = ret;
+        goto out;
+    }
+
+    if(req->data != RT_NULL)
+    {
+        /*do transfer data*/
+        ret = s3c_mmc_xfer_data(data);
+        if(ret != RT_EOK)
+        {
+            data->err = ret;
+            goto out;
+        }
+    }
+
+out:
+    mmcsd_req_complete(host);
+}
+static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    switch (io_cfg->power_mode) {
+    case MMCSD_POWER_ON:
+    case MMCSD_POWER_UP:
+        /* Enable PCLK into SDI Block */
+        CLKCON |= 1 << 9;
+        
+        /* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */
+        GPEUP  = GPEUP  & (~(0x3f << 5))   | (0x01 << 5);
+        GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10);
+        break;
+
+    case MMCSD_POWER_OFF:
+    default:
+        break;                 
+    }
+
+    s3c_mmc_set_clk(host, io_cfg->clock);
+
+    SDICON =  1;
+}
+
+static rt_int32_t mmc_get_card_status(struct rt_mmcsd_host *host)
+{
+    return RT_EOK;
+}
+static void mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
+{
+}
+
+static const struct rt_mmcsd_host_ops ops = 
+{
+    mmc_request,
+    mmc_set_iocfg,
+    mmc_get_card_status,
+    mmc_enable_sdio_irq
+};
+
+int s3c_sdio_init(void)
+{
+    struct rt_mmcsd_host * host = RT_NULL;
+
+
+    host = mmcsd_alloc_host();
+    if (!host)
+    {
+        goto err;
+    }
+
+    host->ops = &ops;
+    host->freq_min = 300000;
+    host->freq_max = 50000000;
+    host->valid_ocr = VDD_32_33 | VDD_33_34;
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
+    host->max_seg_size = 2048;
+    host->max_dma_segs = 10;
+    host->max_blk_size = 512;
+    host->max_blk_count = 4096;
+
+
+    mmcsd_change(host);
+
+    return RT_EOK;
+
+err:
+    if(host)  rt_free(host);
+
+    return -RT_EIO;
+}
+
+INIT_DEVICE_EXPORT(s3c_sdio_init);

bsp/mini2440/drivers/sdcard.c

@@ -1,651 +0,0 @@
-/*
- * File      : sd.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2007, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author        Notes
- * 2007-12-02     Yi.Qiu        the first version
- * 2010-01-01     Bernard       Modify for mini2440
- * 2012-12-15     amr168        support SDHC
- * 2017-11-20     kuangdazzidd  add csd cmd support
- */
-
-#include "sdcard.h"
-#include "rtdef.h"
-
-extern   rt_uint32_t   PCLK;
-volatile rt_uint32_t   rd_cnt;
-volatile rt_uint32_t   wt_cnt;
-volatile rt_int32_t    RCA;
-volatile rt_int32_t    sd_type;
-
-struct sd_csd {
-    rt_uint16_t    bsize;
-    rt_uint32_t    nblks;
-}g_sd_csd;
-
-static void sd_delay(rt_uint32_t ms)
-{
-    ms *= 7326;
-    while(--ms);
-}
-
-static int sd_cmd_end(int cmd, int be_resp)
-{
-    int finish0;
-
-    if (!be_resp)
-    {
-        finish0 = SDICSTA;
-
-        while ((finish0&0x800) != 0x800)
-            finish0 = SDICSTA;
-
-        SDICSTA = finish0;
-
-        return RT_EOK;
-    }
-    else
-    {
-        finish0 = SDICSTA;
-
-        while (!(((finish0&0x200)==0x200) | ((finish0&0x400) == 0x400)))
-            finish0=SDICSTA;
-
-        if (cmd == 1 || cmd == 41)
-        {
-            if ((finish0 & 0xf00) != 0xa00)
-            {
-                SDICSTA = finish0;
-                    if ((finish0&0x400) == 0x400)
-                        return RT_ERROR;
-            }
-            SDICSTA = finish0;
-        }
-        else
-        {
-            if ((finish0 & 0x1f00) != 0xa00)
-            {
-                /* rt_kprintf("CMD%d:SDICSTA=0x%x, SDIRSP0=0x%x\n", cmd, SDICSTA, SDIRSP0); */
-                SDICSTA = finish0;
-                if ((finish0 & 0x400) == 0x400)
-                    return RT_ERROR;
-            }
-            SDICSTA = finish0;
-        }
-        return RT_EOK;
-    }
-}
-
-static int sd_data_end(void)
-{
-    int finish;
-
-    finish = SDIDSTA;
-
-    while (!(((finish & 0x10) == 0x10) | ((finish & 0x20) == 0x20)))
-    {
-        finish = SDIDSTA;
-    }
-
-    if ((finish & 0xfc) != 0x10)
-    {
-        SDIDSTA = 0xec;
-
-        return RT_ERROR;
-    }
-
-    return RT_EOK;
-}
-
-static void sd_cmd0(void)
-{
-    SDICARG = 0x0;
-    SDICCON = (1<<8) | 0x40;
-
-    sd_cmd_end(0, 0);
-    SDICSTA = 0x800;      /* Clear cmd_end(no rsp) */
-}
-
-static int sd_cmd55(void)
-{
-    SDICARG = RCA << 16;
-    SDICCON = (0x1 << 9) | (0x1 << 8) | 0x77;
-
-    if (sd_cmd_end(55, 1) == RT_ERROR)
-    {
-        /* rt_kprintf("CMD55 error\n"); */
-        return RT_ERROR;
-    }
-
-    SDICSTA = 0xa00;
-
-
-    return RT_EOK;
-}
-
-static int sd_cmd9(void *p_rsp)
-{
-SDICARG = RCA << 16;
-SDICCON = (1 << 10) | (1 << 9) | (0x1<<8) | (0x40 | 0x09);
-
-sd_cmd_end(9, 1);
-
-    ((rt_uint32_t *)p_rsp)[0] = SDIRSP3;
-    ((rt_uint32_t *)p_rsp)[1] = SDIRSP2;
-    ((rt_uint32_t *)p_rsp)[2] = SDIRSP1;
-    ((rt_uint32_t *)p_rsp)[3] = SDIRSP0;
-
-return RT_EOK;
-}
-
-static void sd_sel_desel(char sel_desel)
-{
-    if (sel_desel)
-    {
-RECMDS7:
-        SDICARG = RCA << 16;
-        SDICCON = (0x1 << 9) | (0x1 << 8) | 0x47;
-        if (sd_cmd_end(7, 1) == RT_ERROR)
-            goto RECMDS7;
-
-        SDICSTA = 0xa00;
-
-        if (SDIRSP0 & 0x1e00 != 0x800)
-            goto RECMDS7;
-    }
-    else
-    {
-RECMDD7:
-        SDICARG = 0 << 16;
-        SDICCON = (0x1 << 8) | 0x47;
-
-        if (sd_cmd_end(7, 0) == RT_ERROR)
-            goto RECMDD7;
-        SDICSTA = 0x800;
-    }
-}
-
-static void sd_setbus(void)
-{
-    do
-    {
-        sd_cmd55();
-
-        SDICARG = 1 << 1; /* 4bit bus */
-        SDICCON = (0x1<<9) | (0x1<<8) | 0x46; /* sht_resp, wait_resp, start, CMD55 */
-    }while (sd_cmd_end(6, 1) == RT_ERROR);
-
-    SDICSTA=0xa00;      /* Clear cmd_end(with rsp) */
-}
-
-
-static rt_uint32_t bits_str (rt_uint32_t *str, rt_uint32_t start, rt_uint8_t len)
-{
-    rt_uint32_t  mask;
-    rt_uint32_t  index;
-    rt_uint8_t   shift;
-    rt_uint32_t  value;
-
-    mask  = (int)((len < 32) ? (1 << len) : 0) - 1;
-    index = start / 32;
-    shift = start & 31;
-    value = str[index] >> shift;
-
-    if ((len + shift) > 32) {
-        value |= str[index + 1] << (32 - shift);
-    }
-    value &= mask;
-    return value;
-}
-
-
-static int sd_decode_csd (rt_uint32_t  *p_csd)
-{
-    rt_uint32_t e, m, r;
-    rt_uint8_t  structure;
-
-    structure = bits_str(p_csd, 126, 2);
-
-    switch (structure) {
-        case 0:
-            m = bits_str(p_csd, 99, 4);
-            e = bits_str(p_csd, 96, 3);
-            g_sd_csd.bsize  = 512;
-            m = bits_str(p_csd, 62, 12);
-            e = bits_str(p_csd, 47, 3);
-            r = bits_str(p_csd, 80, 4);
-            g_sd_csd.nblks = ((1 + m) << (e + r - 7));
-            break;
-
-        case 1:
-            m = bits_str(p_csd, 99, 4);
-            e = bits_str(p_csd, 96, 3);
-            g_sd_csd.bsize  = 512;
-            m = bits_str(p_csd, 48, 22);
-            g_sd_csd.nblks = (1 + m) << 10;
-            break;
-
-        default:
-            return RT_ERROR;
-    }
-    return RT_EOK;
-}
-
-
-static int sd_send_csd(rt_uint32_t  *p_csd)
-{
-    int         ret;
-    rt_uint32_t rsp[4];
-
-    ret = sd_cmd9((void*)&rsp);
-
-    if (ret != 0) {
-        return ret;
-    }
-
-    rt_memcpy((void*)p_csd, (void*)rsp, 16);
-    return RT_EOK;
-}
-
-static int sd_ocr(void)
-{
-    int i, ver=0;
-
-    /* Negotiate operating condition for SD, it makes card ready state */
-    for (i = 0; i < 50; i ++)
-    {
-        sd_cmd55();
-
-        SDICARG = 0x40ff8000; /* HCS=1, compatible v1.x and v2.0 */
-        SDICCON = (0x1<<9) | (0x1<<8) | 0x69;
-
-        /* if using real board, should replace code here. need to modify qemu in near future*/
-        /* Check end of ACMD41 */
-        if (sd_cmd_end(41, 1) == RT_EOK)
-        {
-            if (SDIRSP0 == 0x80ff8000)
-            {
-                ver = 1; /* SD V1.x, CCS=0 */
-                break;
-            }
-            else if (SDIRSP0 == 0xc0ff8000)
-            {
-                ver = 2; /* SD V2.0, CCS=1 */
-                break;
-            }
-        }
-
-        sd_delay(200);
-    }
-    SDICSTA = 0xa00;
-
-    return ver;
-}
-
-rt_err_t sd_cmd8(void)
-{
-    SDICARG = 0x000001AA; 
-    SDICCON = (0x1<<9) | (0x1<<8) | 0x48; //sht_resp, wait_resp, start
-    if (sd_cmd_end(8, 1) == RT_ERROR)
-        return RT_ERROR;
-    SDICSTA = 0xa00;
-    
-    if ((SDIRSP0&0x1aa) == 0x1aa)
-        return RT_EOK; 
-    else 
-        return RT_ERROR;
-}
-
-static rt_uint8_t sd_init(void)
-{
-    //-- SD controller & card initialize
-    int         i;
-    rt_uint32_t csd[4];
-    /* Important notice for MMC test condition */
-    /* Cmd & Data lines must be enabled by pull up resister */
-    SDIPRE    = PCLK / (INICLK) - 1;
-    SDICON    = (0<<4) | 1;   // Type A, clk enable
-    SDIFSTA   = SDIFSTA | (1<<16);
-    SDIBSIZE  = 0x200;       /* 512byte per one block */
-    SDIDTIMER = 0x7fffff;     /* timeout count */
-
-    /* Wait 74SDCLK for MMC card */
-    for (i = 0; i < 0x1000; i ++);
-
-    sd_cmd0();
-    sd_cmd8(); /* Must be use it, Host shall supports high capacity */
-
-    /* Check SD card OCR */
-    sd_type = sd_ocr();
-    if (sd_type > 0)
-    {
-        rt_kprintf("In SD ready\n");
-    }
-    else
-    {
-        rt_kprintf("Initialize fail\nNo Card assertion\n");
-
-        return RT_ERROR;
-    }
-
-RECMD2:
-    SDICARG = 0x0;
-    SDICCON = (0x1<<10)|(0x1<<9)|(0x1<<8)|0x42; /* lng_resp, wait_resp, start, CMD2 */
-    if (sd_cmd_end(2, 1) == RT_ERROR)
-        goto RECMD2;
-
-    SDICSTA = 0xa00;    /* Clear cmd_end(with rsp) */
-
-RECMD3:
-    SDICARG = 0<<16;    /* CMD3(MMC:Set RCA, SD:Ask RCA-->SBZ) */
-    SDICCON = (0x1<<9)|(0x1<<8)|0x43; /* sht_resp, wait_resp, start, CMD3 */
-    if (sd_cmd_end(3, 1) == RT_ERROR)
-        goto RECMD3;
-    SDICSTA=0xa00;  /* Clear cmd_end(with rsp) */
-
-    sd_send_csd(csd);
-    sd_decode_csd(csd);
-
-    RCA = (SDIRSP0 & 0xffff0000) >> 16;
-    SDIPRE = PCLK / (SDCLK) - 1; /* Normal clock=25MHz */
-    if (SDIRSP0 & 0x1e00 != 0x600)
-        goto RECMD3;
-
-    sd_sel_desel(1);
-    sd_delay(200);
-    sd_setbus();
-
-    return RT_EOK;
-}
-
-static rt_uint8_t sd_readblock(rt_uint32_t address, rt_uint8_t *buf)
-{
-    rt_uint32_t status, tmp;
-
-    rd_cnt = 0;
-    SDIFSTA = SDIFSTA | (1<<16);
-
-    SDIDCON = (2 << 22) | (1 << 19) | (1 << 17) | (1 << 16) | (1 << 14) | (2 << 12) | (1 << 0);
-    SDICARG = address;
-
-RERDCMD:
-    SDICCON = (0x1 << 9 ) | (0x1 << 8) | 0x51;
-    if (sd_cmd_end(17, 1) == RT_ERROR)
-    {
-        rt_kprintf("Read CMD Error\n");
-        goto RERDCMD;
-    }
-
-    SDICSTA = 0xa00;
-
-    while (rd_cnt < 128)
-    {
-        if ((SDIDSTA & 0x20) == 0x20)
-        {
-            SDIDSTA = (0x1 << 0x5);
-            break;
-        }
-        status = SDIFSTA;
-        if ((status & 0x1000) == 0x1000)
-        {
-            tmp = SDIDAT;
-            rt_memcpy(buf, &tmp, sizeof(rt_uint32_t));
-            rd_cnt ++;
-            buf += 4;
-        }
-    }
-    if (sd_data_end() == RT_ERROR)
-    {
-        rt_kprintf("Dat error\n");
-
-        return RT_ERROR;
-    }
-
-    SDIDCON = SDIDCON &~ (7<<12);
-    SDIFSTA = SDIFSTA & 0x200;
-    SDIDSTA = 0x10;
-
-    return RT_EOK;
-}
-
-static rt_uint8_t sd_writeblock(rt_uint32_t address, rt_uint8_t *buf)
-{
-    rt_uint32_t status, tmp;
-
-    wt_cnt = 0;
-    SDIFSTA = SDIFSTA | (1 << 16);
-
-    SDIDCON = (2 << 22) | (1 << 20) | (1 << 17) | (1 << 16) | (1 << 14) | (3 << 12) | (1 << 0);
-    SDICARG = address;
-
-REWTCMD:
-    SDICCON = (0x1 << 9) | (0x1 << 8) |0x58;
-
-    if (sd_cmd_end(24, 1) == RT_ERROR)
-        goto REWTCMD;
-
-    SDICSTA = 0xa00;
-
-    while (wt_cnt < 128)
-    {
-        status = SDIFSTA;
-        if ((status & 0x2000) == 0x2000)
-        {
-            rt_memcpy(&tmp, buf, sizeof(rt_uint32_t));
-            SDIDAT = tmp;
-            wt_cnt ++;
-            buf += 4;
-        }
-    }
-    if (sd_data_end() == RT_ERROR)
-    {
-        rt_kprintf("Data Error\n");
-
-        return RT_ERROR;
-    }
-    SDIDCON = SDIDCON &~ (7<<12);
-    SDIDSTA = 0x10;
-
-    return RT_EOK;
-}
-
-#ifdef RT_USING_DFS
-/* RT-Thread Device Driver Interface */
-#include <rtthread.h>
-
-#include <dfs_fs.h>
-
-struct rt_device sdcard_device[4];
-struct dfs_partition part[4];
-
-static rt_err_t rt_sdcard_init(rt_device_t dev)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_sdcard_close(rt_device_t dev)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
-{
-struct rt_device_blk_geometry *p_geometry = (struct rt_device_blk_geometry *)args;
-p_geometry->block_size = g_sd_csd.bsize;
-p_geometry->sector_count = g_sd_csd.nblks;
-p_geometry->bytes_per_sector = 512;
-    return RT_EOK;
-}
-
-static rt_size_t rt_sdcard_read(rt_device_t dev,
-                                rt_off_t    pos,
-                                void       *buffer,
-                                rt_size_t   size)
-{
-    int i, addr;
-    struct dfs_partition *part = (struct dfs_partition *)dev->user_data;
-
-    if (dev == RT_NULL)
-    {
-        rt_set_errno(-EINVAL);
-
-        return 0;
-    }
-
-    /* read all sectors */
-    for (i = 0; i < size; i ++)
-    {
-        rt_sem_take(part->lock, RT_WAITING_FOREVER);
-        if (sd_type == 1)
-            addr = (part->offset + i + pos)*SECTOR_SIZE;
-        else
-            addr = (part->offset + i + pos);
-        sd_readblock(addr, (rt_uint8_t *)((rt_uint8_t *)buffer + i * SECTOR_SIZE));
-        rt_sem_release(part->lock);
-    }
-
-    /* the length of reading must align to SECTOR SIZE */
-    return size;
-}
-
-static rt_size_t rt_sdcard_write(rt_device_t dev,
-                                 rt_off_t    pos,
-                                 const void *buffer,
-                                 rt_size_t   size)
-{
-    int i, addr;
-    struct dfs_partition *part = (struct dfs_partition *)dev->user_data;
-
-    if (dev == RT_NULL)
-    {
-        rt_set_errno(-EINVAL);
-
-        return 0;
-    }
-
-    /* read all sectors */
-    for (i = 0; i < size; i++)
-    {
-        rt_sem_take(part->lock, RT_WAITING_FOREVER);
-        if (sd_type == 1)
-            addr = (part->offset + i + pos)*SECTOR_SIZE;
-        else
-            addr = (part->offset + i + pos);
-        sd_writeblock(addr, (rt_uint8_t*)((rt_uint8_t*)buffer + i * SECTOR_SIZE));
-        rt_sem_release(part->lock);
-    }
-
-    /* the length of reading must align to SECTOR SIZE */
-    return size;
-}
-
-int rt_hw_sdcard_init(void)
-{
-    rt_uint8_t i, status;
-    rt_uint8_t *sector;
-    char dname[4];
-    char sname[8];
-
-    /* Enable PCLK into SDI Block */
-    CLKCON |= 1 << 9;
-
-    /* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */
-    GPEUP  = GPEUP  & (~(0x3f << 5))   | (0x01 << 5);
-    GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10);
-
-    RCA = 0;
-
-    if (sd_init() == RT_EOK)
-    {
-        /* get the first sector to read partition table */
-        sector = (rt_uint8_t*) rt_malloc (512);
-        if (sector == RT_NULL)
-        {
-            rt_kprintf("allocate partition sector buffer failed\n");
-
-            return -RT_ERROR;
-        }
-        status = sd_readblock(0, sector);
-        if (status == RT_EOK)
-        {
-            for (i = 0; i < 4; i ++)
-            {
-                /* get the first partition */
-                status = dfs_filesystem_get_partition(&part[i], sector, i);
-                if (status == RT_EOK)
-                {
-                    rt_snprintf(dname, 4, "sd%d",  i);
-                    rt_snprintf(sname, 8, "sem_sd%d",  i);
-                    part[i].lock = rt_sem_create(sname, 1, RT_IPC_FLAG_FIFO);
-
-                    /* register sdcard device */
-                    sdcard_device[i].type      = RT_Device_Class_Block;
-                    sdcard_device[i].init      = rt_sdcard_init;
-                    sdcard_device[i].open      = rt_sdcard_open;
-                    sdcard_device[i].close     = rt_sdcard_close;
-                    sdcard_device[i].read      = rt_sdcard_read;
-                    sdcard_device[i].write     = rt_sdcard_write;
-                    sdcard_device[i].control   = rt_sdcard_control;
-                    sdcard_device[i].user_data = &part[i];
-
-                    rt_device_register(&sdcard_device[i], dname,
-                        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
-                }
-                else
-                {
-                    if (i == 0)
-                    {
-                        /* there is no partition table */
-                        part[0].offset = 0;
-                        part[0].size   = 0;
-                        part[0].lock   = rt_sem_create("sem_sd0", 1, RT_IPC_FLAG_FIFO);
-
-                        /* register sdcard device */
-                        sdcard_device[0].type      = RT_Device_Class_Block;
-                        sdcard_device[0].init      = rt_sdcard_init;
-                        sdcard_device[0].open      = rt_sdcard_open;
-                        sdcard_device[0].close     = rt_sdcard_close;
-                        sdcard_device[0].read      = rt_sdcard_read;
-                        sdcard_device[0].write     = rt_sdcard_write;
-                        sdcard_device[0].control   = rt_sdcard_control;
-                        sdcard_device[0].user_data = &part[0];
-
-                        rt_device_register(&sdcard_device[0], "sd0",
-                            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE);
-
-                        break;
-                    }
-                }
-            }
-        }
-        else
-        {
-            rt_kprintf("read sdcard first sector failed\n");
-        }
-
-        /* release sector buffer */
-        rt_free(sector);
-
-        return -RT_ERROR; 
-    }
-    else
-    {
-        rt_kprintf("sdcard init failed\n");
-    }
-
-    return RT_EOK;
-}
-
-INIT_BOARD_EXPORT(rt_hw_sdcard_init);
-#endif

bsp/mini2440/drivers/sdcard.h

@@ -1,11 +0,0 @@
-#ifndef __SDCARD_H
-#define __SDCARD_H
-
-#include  <s3c24x0.h>
-
-#define INICLK	300000
-#define SDCLK	24000000	//PCLK=49.392MHz
-#define MMCCLK	15000000	//PCLK=49.392MHz
-
-#endif
-

bsp/mini2440/drivers/touch.c

@@ -16,483 +16,496 @@
 #include <rtthread.h>
 #include <s3c24x0.h>
 
-#ifdef RT_USING_RTGUI
+#ifdef PKG_USING_GUIENGINE
 #include <rtgui/rtgui_system.h>
 #include <rtgui/rtgui_server.h>
 #include <rtgui/event.h>
 #endif
 
-#include "lcd.h"
+#define TOUCH_SWAP_XY
+
 #include "touch.h"
 
 /* ADCCON Register Bits */
-#define S3C2410_ADCCON_ECFLG			(1<<15)
-#define S3C2410_ADCCON_PRSCEN			(1<<14)
-#define S3C2410_ADCCON_PRSCVL(x)		(((x)&0xFF)<<6)
-#define S3C2410_ADCCON_PRSCVLMASK		(0xFF<<6)
-#define S3C2410_ADCCON_SELMUX(x)		(((x)&0x7)<<3)
-#define S3C2410_ADCCON_MUXMASK			(0x7<<3)
-#define S3C2410_ADCCON_STDBM			(1<<2)
-#define S3C2410_ADCCON_READ_START		(1<<1)
-#define S3C2410_ADCCON_ENABLE_START		(1<<0)
-#define S3C2410_ADCCON_STARTMASK		(0x3<<0)
+#define S3C2410_ADCCON_ECFLG            (1<<15)
+#define S3C2410_ADCCON_PRSCEN           (1<<14)
+#define S3C2410_ADCCON_PRSCVL(x)        (((x)&0xFF)<<6)
+#define S3C2410_ADCCON_PRSCVLMASK       (0xFF<<6)
+#define S3C2410_ADCCON_SELMUX(x)        (((x)&0x7)<<3)
+#define S3C2410_ADCCON_MUXMASK          (0x7<<3)
+#define S3C2410_ADCCON_STDBM            (1<<2)
+#define S3C2410_ADCCON_READ_START       (1<<1)
+#define S3C2410_ADCCON_ENABLE_START     (1<<0)
+#define S3C2410_ADCCON_STARTMASK        (0x3<<0)
 
 /* ADCTSC Register Bits */
-#define S3C2410_ADCTSC_UD_SEN			(1<<8) /* ghcstop add for s3c2440a */
-#define S3C2410_ADCTSC_YM_SEN			(1<<7)
-#define S3C2410_ADCTSC_YP_SEN			(1<<6)
-#define S3C2410_ADCTSC_XM_SEN			(1<<5)
-#define S3C2410_ADCTSC_XP_SEN			(1<<4)
-#define S3C2410_ADCTSC_PULL_UP_DISABLE	(1<<3)
-#define S3C2410_ADCTSC_AUTO_PST			(1<<2)
-#define S3C2410_ADCTSC_XY_PST(x)		(((x)&0x3)<<0)
+#define S3C2410_ADCTSC_UD_SEN           (1<<8) /* ghcstop add for s3c2440a */
+#define S3C2410_ADCTSC_YM_SEN           (1<<7)
+#define S3C2410_ADCTSC_YP_SEN           (1<<6)
+#define S3C2410_ADCTSC_XM_SEN           (1<<5)
+#define S3C2410_ADCTSC_XP_SEN           (1<<4)
+#define S3C2410_ADCTSC_PULL_UP_DISABLE  (1<<3)
+#define S3C2410_ADCTSC_AUTO_PST         (1<<2)
+#define S3C2410_ADCTSC_XY_PST(x)        (((x)&0x3)<<0)
 
 /* ADCDAT0 Bits */
-#define S3C2410_ADCDAT0_UPDOWN			(1<<15)
-#define S3C2410_ADCDAT0_AUTO_PST		(1<<14)
-#define S3C2410_ADCDAT0_XY_PST			(0x3<<12)
-#define S3C2410_ADCDAT0_XPDATA_MASK		(0x03FF)
+#define S3C2410_ADCDAT0_UPDOWN          (1<<15)
+#define S3C2410_ADCDAT0_AUTO_PST        (1<<14)
+#define S3C2410_ADCDAT0_XY_PST          (0x3<<12)
+#define S3C2410_ADCDAT0_XPDATA_MASK     (0x03FF)
 
 /* ADCDAT1 Bits */
-#define S3C2410_ADCDAT1_UPDOWN			(1<<15)
-#define S3C2410_ADCDAT1_AUTO_PST		(1<<14)
-#define S3C2410_ADCDAT1_XY_PST			(0x3<<12)
-#define S3C2410_ADCDAT1_YPDATA_MASK		(0x03FF)
+#define S3C2410_ADCDAT1_UPDOWN          (1<<15)
+#define S3C2410_ADCDAT1_AUTO_PST        (1<<14)
+#define S3C2410_ADCDAT1_XY_PST          (0x3<<12)
+#define S3C2410_ADCDAT1_YPDATA_MASK     (0x03FF)
 
 #define WAIT4INT(x)  (((x)<<8) | \
-		     S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \
-		     S3C2410_ADCTSC_XY_PST(3))
+             S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \
+             S3C2410_ADCTSC_XY_PST(3))
 
-#define AUTOPST	     (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \
-		     S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0))
+#define AUTOPST      (S3C2410_ADCTSC_YM_SEN | S3C2410_ADCTSC_YP_SEN | S3C2410_ADCTSC_XP_SEN | \
+             S3C2410_ADCTSC_AUTO_PST | S3C2410_ADCTSC_XY_PST(0))
 
-#define X_MIN		74
-#define X_MAX		934
-#define Y_MIN		920
-#define Y_MAX		89
+#define X_MIN       74
+#define X_MAX       934
+#define Y_MIN       920
+#define Y_MAX       89
 
 struct s3c2410ts
 {
-	long xp;
-	long yp;
-	int count;
-	int shift;
+    long xp;
+    long yp;
+    int count;
+    int shift;
 
-	int delay;
-	int presc;
+    int delay;
+    int presc;
 
-	char phys[32];
+    char phys[32];
 };
 static struct s3c2410ts ts;
 
 struct rtgui_touch_device
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	rt_timer_t poll_timer;
-	rt_uint16_t x, y;
+    rt_timer_t poll_timer;
+    rt_uint16_t x, y;
 
-	rt_bool_t calibrating;
-	rt_touch_calibration_func_t calibration_func;
+    rt_bool_t calibrating;
+    rt_touch_calibration_func_t calibration_func;
 
-	rt_touch_eventpost_func_t eventpost_func;
-	void *eventpost_param;
+    rt_touch_eventpost_func_t eventpost_func;
+    void *eventpost_param;
 
-	rt_uint16_t min_x, max_x;
-	rt_uint16_t min_y, max_y;
+    rt_uint16_t min_x, max_x;
+    rt_uint16_t min_y, max_y;
 
-	rt_uint16_t width;
-	rt_uint16_t height;
-	
-	rt_bool_t first_down_report;
+    rt_uint16_t width;
+    rt_uint16_t height;
+    
+    rt_bool_t first_down_report;
 };
 static struct rtgui_touch_device *touch = RT_NULL;
 
-#ifdef RT_USING_RTGUI
+#ifdef PKG_USING_GUIENGINE
 static void report_touch_input(int updown)
 {
-	struct rtgui_event_mouse emouse;
-
-	RTGUI_EVENT_MOUSE_BUTTON_INIT(&emouse);
-	emouse.wid = RT_NULL;
-
-	/* set emouse button */
-	emouse.button = RTGUI_MOUSE_BUTTON_LEFT;
-	emouse.parent.sender = RT_NULL;
-	
-	if (updown)
-	{
-		ts.xp = ts.xp / ts.count;
-		ts.yp = ts.yp / ts.count;;
-
-		if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
-		{
-			touch->x = ts.xp;
-			touch->y = ts.yp;
-		}
-		else
-		{
-			if (touch->max_x > touch->min_x)
-			{
-				touch->x = touch->width * (ts.xp-touch->min_x)/(touch->max_x-touch->min_x);
-			}
-			else
-			{
-				touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x);
-			}
-
-			if (touch->max_y > touch->min_y)
-			{
-				touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y);
-			}
-			else
-			{
-				touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y);
-			}
-		}
-
-		emouse.x = touch->x;
-		emouse.y = touch->y;
-		if (touch->first_down_report == RT_TRUE)
-		{
-			emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
-			emouse.button |= RTGUI_MOUSE_BUTTON_DOWN;
-		}
-		else
-		{	
-			emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION;
-			emouse.button = 0;
-		}
-	}
-	else
-	{
-		emouse.x = touch->x;
-		emouse.y = touch->y;	
-		emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
-		emouse.button |= RTGUI_MOUSE_BUTTON_UP;
-		if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
-		{
-			/* callback function */
-			touch->calibration_func(emouse.x, emouse.y);
-		}
-	}
-
-	/* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up",
-	touch->x, touch->y); */	
-	
-	/* send event to server */
-	if (touch->calibrating != RT_TRUE)
-	{	
-		rtgui_server_post_event((&emouse.parent), sizeof(emouse));
-	}
+    struct rtgui_event_mouse emouse;
+
+    RTGUI_EVENT_MOUSE_BUTTON_INIT(&emouse);
+    emouse.wid = RT_NULL;
+
+    /* set emouse button */
+    emouse.button = RTGUI_MOUSE_BUTTON_LEFT;
+    emouse.parent.sender = RT_NULL;
+    
+    if (updown)
+    {
+        ts.xp = ts.xp / ts.count;
+        ts.yp = ts.yp / ts.count;;
+
+    #ifdef TOUCH_SWAP_XY
+        ts.xp = ts.xp + ts.yp;
+        ts.yp = ts.xp - ts.yp;
+        ts.xp = ts.xp - ts.yp;
+    #endif
+
+        if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
+        {
+            touch->x = ts.xp;
+            touch->y = ts.yp;
+        }
+        else
+        {
+            if (touch->max_x > touch->min_x)
+            {
+                touch->x = touch->width * (ts.xp-touch->min_x)/(touch->max_x-touch->min_x);
+            }
+            else
+            {
+                touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x);
+            }
+
+            if (touch->max_y > touch->min_y)
+            {
+                touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y);
+            }
+            else
+            {
+                touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y);
+            }
+        }
+
+        emouse.x = touch->x;
+        emouse.y = touch->y;
+        if (touch->first_down_report == RT_TRUE)
+        {
+            emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
+            emouse.button |= RTGUI_MOUSE_BUTTON_DOWN;
+        }
+        else
+        {   
+            emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION;
+            emouse.button = 0;
+        }
+    }
+    else
+    {
+        emouse.x = touch->x;
+        emouse.y = touch->y;    
+        emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
+        emouse.button |= RTGUI_MOUSE_BUTTON_UP;
+        if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
+        {
+            /* callback function */
+            touch->calibration_func(emouse.x, emouse.y);
+        }
+    }
+
+    /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up",
+    touch->x, touch->y); */ 
+    
+    /* send event to server */
+    if (touch->calibrating != RT_TRUE)
+    {   
+        rtgui_server_post_event((&emouse.parent), sizeof(emouse));
+    }
 }
 #else
 static void report_touch_input(int updown)
 {
-	struct rt_touch_event touch_event;
-
-	if (updown)
-	{
-		ts.xp = ts.xp / ts.count;
-		ts.yp = ts.yp / ts.count;
-
-		if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
-		{
-			touch->x = ts.xp;
-			touch->y = ts.yp;
-		}
-		else
-		{
-			if (touch->max_x > touch->min_x)
-			{
-				touch->x = touch->width * ( ts.xp - touch->min_x ) / (touch->max_x-touch->min_x);
-			}
-			else
-			{
-				touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x);
-			}
-
-			if (touch->max_y > touch->min_y)
-			{
-				touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y);
-			}
-			else
-			{
-				touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y);
-			}
-		}
-
-		touch_event.x = touch->x;
-		touch_event.y = touch->y;
-		touch_event.pressed = 1;
-
-		if (touch->first_down_report == RT_TRUE)
-		{
-			if (touch->calibrating != RT_TRUE && touch->eventpost_func)
-			{
-				touch->eventpost_func(touch->eventpost_param, &touch_event); 
-			}
-		}
-	}
-	else
-	{
-		touch_event.x = touch->x;
-		touch_event.y = touch->y;
-		touch_event.pressed = 0;
-		
-		if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
-		{
-			/* callback function */
-			touch->calibration_func(touch_event.x, touch_event.y);
-		}
-
-		if (touch->calibrating != RT_TRUE && touch->eventpost_func)
-		{	
-			touch->eventpost_func(touch->eventpost_param, &touch_event); 
-		}
-	}
+    struct rt_touch_event touch_event;
+
+    if (updown)
+    {
+        ts.xp = ts.xp / ts.count;
+        ts.yp = ts.yp / ts.count;
+
+        if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
+        {
+            touch->x = ts.xp;
+            touch->y = ts.yp;
+        }
+        else
+        {
+            if (touch->max_x > touch->min_x)
+            {
+                touch->x = touch->width * ( ts.xp - touch->min_x ) / (touch->max_x-touch->min_x);
+            }
+            else
+            {
+                touch->x = touch->width * ( touch->min_x - ts.xp ) / (touch->min_x-touch->max_x);
+            }
+
+            if (touch->max_y > touch->min_y)
+            {
+                touch->y = touch->height * ( ts.yp - touch->min_y ) / (touch->max_y-touch->min_y);
+            }
+            else
+            {
+                touch->y = touch->height * ( touch->min_y - ts.yp ) / (touch->min_y-touch->max_y);
+            }
+        }
+
+        touch_event.x = touch->x;
+        touch_event.y = touch->y;
+        touch_event.pressed = 1;
+
+        if (touch->first_down_report == RT_TRUE)
+        {
+            if (touch->calibrating != RT_TRUE && touch->eventpost_func)
+            {
+                touch->eventpost_func(touch->eventpost_param, &touch_event); 
+            }
+        }
+    }
+    else
+    {
+        touch_event.x = touch->x;
+        touch_event.y = touch->y;
+        touch_event.pressed = 0;
+        
+        if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
+        {
+            /* callback function */
+            touch->calibration_func(touch_event.x, touch_event.y);
+        }
+
+        if (touch->calibrating != RT_TRUE && touch->eventpost_func)
+        {   
+            touch->eventpost_func(touch->eventpost_param, &touch_event); 
+        }
+    }
 }
 #endif
 
 static void touch_timer_fire(void *parameter)
 {
-	rt_uint32_t data0;
-	rt_uint32_t data1;
-	int updown;
+    rt_uint32_t data0;
+    rt_uint32_t data1;
+    int updown;
 
-	data0 = ADCDAT0;
-	data1 = ADCDAT1;
+    data0 = ADCDAT0;
+    data1 = ADCDAT1;
 
-	updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN));
+    updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN));
 
-	if (updown)
-	{
-		if (ts.count != 0)
-		{
-			report_touch_input(updown);
-		}
+    if (updown)
+    {
+        if (ts.count != 0)
+        {
+            report_touch_input(updown);
+        }
 
-		ts.xp = 0;
-		ts.yp = 0;
-		ts.count = 0;
+        ts.xp = 0;
+        ts.yp = 0;
+        ts.count = 0;
 
-		ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST;
-		ADCCON |= S3C2410_ADCCON_ENABLE_START;
-	}
+        ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST;
+        ADCCON |= S3C2410_ADCCON_ENABLE_START;
+    }
 }
 
 static void s3c2410_adc_stylus_action(void)
 {
-	rt_uint32_t data0;
-	rt_uint32_t data1;
-
-	data0 = ADCDAT0;
-	data1 = ADCDAT1;
-	
-	ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK;
-	ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK;
-	ts.count ++;
-
-	if (ts.count < (1<<ts.shift))
-	{
-		ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST;
-		ADCCON |= S3C2410_ADCCON_ENABLE_START;
-	}
-	else
-	{
-		if (touch->first_down_report)
-		{
-			report_touch_input(1);
-			ts.xp = 0;
-			ts.yp = 0;
-			ts.count = 0;
-			touch->first_down_report = 0;
-		}
-		/* start timer */
-		rt_timer_start(touch->poll_timer);
-		ADCTSC = WAIT4INT(1);
-	}
-
-	SUBSRCPND |= BIT_SUB_ADC;
+    rt_uint32_t data0;
+    rt_uint32_t data1;
+
+    data0 = ADCDAT0;
+    data1 = ADCDAT1;
+    
+    ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK;
+    ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK;
+    ts.count ++;
+
+    if (ts.count < (1<<ts.shift))
+    {
+        ADCTSC = S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST;
+        ADCCON |= S3C2410_ADCCON_ENABLE_START;
+    }
+    else
+    {
+        if (touch->first_down_report)
+        {
+            report_touch_input(1);
+            ts.xp = 0;
+            ts.yp = 0;
+            ts.count = 0;
+            touch->first_down_report = 0;
+        }
+        /* start timer */
+        rt_timer_start(touch->poll_timer);
+        ADCTSC = WAIT4INT(1);
+    }
+
+    SUBSRCPND |= BIT_SUB_ADC;
 }
 
 static void s3c2410_intc_stylus_updown(void)
 {
-	rt_uint32_t data0;
-	rt_uint32_t data1;
-	int updown;
-
-	data0 = ADCDAT0;
-	data1 = ADCDAT1;
-
-	updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN));
-
-	/* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */
-
-	if (updown) 
-	{
-		touch_timer_fire(0);
-	}	
-	else
-	{
-		/* stop timer */
-		rt_timer_stop(touch->poll_timer);
-		touch->first_down_report = RT_TRUE;
-		if (ts.xp >= 0 && ts.yp >= 0)
-		{
-			report_touch_input(updown);
-		}
-		ts.count = 0;
-		ADCTSC = WAIT4INT(0);
-	}
-
-	SUBSRCPND |= BIT_SUB_TC;
+    rt_uint32_t data0;
+    rt_uint32_t data1;
+    int updown;
+
+    data0 = ADCDAT0;
+    data1 = ADCDAT1;
+
+    updown = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) && (!(data1 & S3C2410_ADCDAT0_UPDOWN));
+
+    /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */
+
+    if (updown) 
+    {
+        touch_timer_fire(0);
+    }   
+    else
+    {
+        /* stop timer */
+        rt_timer_stop(touch->poll_timer);
+        touch->first_down_report = RT_TRUE;
+        if (ts.xp >= 0 && ts.yp >= 0)
+        {
+            report_touch_input(updown);
+        }
+        ts.count = 0;
+        ADCTSC = WAIT4INT(0);
+    }
+
+    SUBSRCPND |= BIT_SUB_TC;
 }
 
 static void rt_touch_handler(int irqno, void *param)
 {
-	if (SUBSRCPND & BIT_SUB_ADC)
-	{
-		/* INT_SUB_ADC */
-		s3c2410_adc_stylus_action();
-	}
-
-	if (SUBSRCPND & BIT_SUB_TC)
-	{
-		/* INT_SUB_TC */
-		s3c2410_intc_stylus_updown();
-	}
-
-	/* clear interrupt */
-	INTPND |= (1ul << INTADC);
+    if (SUBSRCPND & BIT_SUB_ADC)
+    {
+        /* INT_SUB_ADC */
+        s3c2410_adc_stylus_action();
+    }
+
+    if (SUBSRCPND & BIT_SUB_TC)
+    {
+        /* INT_SUB_TC */
+        s3c2410_intc_stylus_updown();
+    }
+
+    /* clear interrupt */
+    INTPND |= (1ul << INTADC);
 }
 
 /* RT-Thread Device Interface */
 static rt_err_t rtgui_touch_init(rt_device_t dev)
 {
-	/* init touch screen structure */
-	rt_memset(&ts, 0, sizeof(struct s3c2410ts));
+    /* init touch screen structure */
+    rt_memset(&ts, 0, sizeof(struct s3c2410ts));
 
-	ts.delay = 50000;
-	ts.presc = 9;
-	ts.shift = 2;
-	ts.count = 0;
-	ts.xp = ts.yp = 0;
+    ts.delay = 50000;
+    ts.presc = 9;
+    ts.shift = 2;
+    ts.count = 0;
+    ts.xp = ts.yp = 0;
 
-	ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc);
-	ADCDLY = ts.delay;
+    ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc);
+    ADCDLY = ts.delay;
 
-	ADCTSC = WAIT4INT(0);
+    ADCTSC = WAIT4INT(0);
 
-	rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL , "INTADC");
-	rt_hw_interrupt_umask(INTADC);
+    rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL , "INTADC");
+    rt_hw_interrupt_umask(INTADC);
 
-	/* clear interrupt */
-	INTPND |= (1ul << INTADC);
+    /* clear interrupt */
+    INTPND |= (1ul << INTADC);
 
-	SUBSRCPND |= BIT_SUB_TC;
-	SUBSRCPND |= BIT_SUB_ADC;
+    SUBSRCPND |= BIT_SUB_TC;
+    SUBSRCPND |= BIT_SUB_ADC;
 
-	/* install interrupt handler */
-	INTSUBMSK &= ~BIT_SUB_ADC;
-	INTSUBMSK &= ~BIT_SUB_TC;
+    /* install interrupt handler */
+    INTSUBMSK &= ~BIT_SUB_ADC;
+    INTSUBMSK &= ~BIT_SUB_TC;
 
-	touch->first_down_report = RT_TRUE;
+    touch->first_down_report = RT_TRUE;
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rtgui_touch_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RT_TOUCH_CALIBRATION:
-		touch->calibrating = RT_TRUE;
-		touch->calibration_func = (rt_touch_calibration_func_t)args;
-		break;
-
-	case RT_TOUCH_NORMAL:
-		touch->calibrating = RT_FALSE;
-		break;
-
-	case RT_TOUCH_CALIBRATION_DATA:
-	{
-		struct calibration_data *data;
-
-		data = (struct calibration_data *)args;
-
-		/* update */
-		touch->min_x = data->min_x;
-		touch->max_x = data->max_x;
-		touch->min_y = data->min_y;
-		touch->max_y = data->max_y;
-
-		/*
-			rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n",
-				touch->min_x, touch->max_x, touch->min_y, touch->max_y);
-		*/		
-	}
-		break;
-
-	case RT_TOUCH_EVENTPOST:
-		touch->eventpost_func = (rt_touch_eventpost_func_t)args;
-		break;
-
-	case RT_TOUCH_EVENTPOST_PARAM:
-		touch->eventpost_param = args;
-		break;
-	}
-
-	return RT_EOK;
+    switch (cmd)
+    {
+    case RT_TOUCH_CALIBRATION:
+        touch->calibrating = RT_TRUE;
+        touch->calibration_func = (rt_touch_calibration_func_t)args;
+        break;
+
+    case RT_TOUCH_NORMAL:
+        touch->calibrating = RT_FALSE;
+        break;
+
+    case RT_TOUCH_CALIBRATION_DATA:
+    {
+        struct calibration_data *data;
+
+        data = (struct calibration_data *)args;
+
+        /* update */
+        touch->min_x = data->min_x;
+        touch->max_x = data->max_x;
+        touch->min_y = data->min_y;
+        touch->max_y = data->max_y;
+
+        /*
+            rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n",
+                touch->min_x, touch->max_x, touch->min_y, touch->max_y);
+        */      
+    }
+        break;
+
+    case RT_TOUCH_EVENTPOST:
+        touch->eventpost_func = (rt_touch_eventpost_func_t)args;
+        break;
+
+    case RT_TOUCH_EVENTPOST_PARAM:
+        touch->eventpost_param = args;
+        break;
+    }
+
+    return RT_EOK;
 }
 
-void rtgui_touch_hw_init(void)
+int rtgui_touch_hw_init(void)
 {
-	rt_err_t result = RT_FALSE;
-	rt_device_t device = RT_NULL;
-	struct rt_device_graphic_info info;
-
-	touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device));
-	if (touch == RT_NULL)
-		return; /* no memory yet */
-
-	/* clear device structure */
-	rt_memset(&(touch->parent), 0, sizeof(struct rt_device));
-	touch->calibrating = RT_FALSE;
-	touch->min_x = X_MIN;
-	touch->max_x = X_MAX;
-	touch->min_y = Y_MIN;
-	touch->max_y = Y_MAX;
-	touch->eventpost_func  = RT_NULL;
-	touch->eventpost_param = RT_NULL;
-
-	/* init device structure */
-	touch->parent.type = RT_Device_Class_Unknown;
-	touch->parent.init = rtgui_touch_init;
-	touch->parent.control = rtgui_touch_control;
-	touch->parent.user_data = RT_NULL;
-
-	device = rt_device_find("lcd");
-	if (device == RT_NULL)
-		return; /* no this device */	
-
-	/* get graphic device info */
-	result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info);
-	if (result != RT_EOK)
-	{
-
-		/* get device information failed */
-
-		return;
-	}
-
-	touch->width = info.width;
-	touch->height = info.height;
-	
-	/* create 1/8 second timer */
-	touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL,
-	                                    RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC);
-
-	/* register touch device to RT-Thread */
-	rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR);
+    rt_err_t result = RT_FALSE;
+    rt_device_t device = RT_NULL;
+    struct rt_device_graphic_info info;
+
+    touch = (struct rtgui_touch_device *)rt_malloc(sizeof(struct rtgui_touch_device));
+    if (touch == RT_NULL)
+        return -RT_ERROR; /* no memory yet */
+
+    /* clear device structure */
+    rt_memset(&(touch->parent), 0, sizeof(struct rt_device));
+    touch->calibrating = RT_FALSE;
+    touch->min_x = X_MIN;
+    touch->max_x = X_MAX;
+    touch->min_y = Y_MIN;
+    touch->max_y = Y_MAX;
+    touch->eventpost_func  = RT_NULL;
+    touch->eventpost_param = RT_NULL;
+
+    /* init device structure */
+    touch->parent.type = RT_Device_Class_Unknown;
+    touch->parent.init = rtgui_touch_init;
+    touch->parent.control = rtgui_touch_control;
+    touch->parent.user_data = RT_NULL;
+
+    device = rt_device_find("lcd");
+    if (device == RT_NULL) 
+    {
+        rt_kprintf("No lcd found\n");
+        return -RT_ERROR; /* no this device */  
+    }
+
+    /* get graphic device info */
+    result = rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info);
+    if (result != RT_EOK)
+    {
+        /* get device information failed */
+        rt_kprintf("Get graphic device info failed\n");
+        return -RT_ERROR;
+    }
+
+    touch->width = info.width;
+    touch->height = info.height;
+    
+    /* create 1/8 second timer */
+    touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL,
+                                        RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC);
+
+    /* register touch device to RT-Thread */
+    rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR);
+
+    return RT_EOK;
 }
+
+INIT_PREV_EXPORT(rtgui_touch_hw_init);

bsp/mini2440/drivers/touch.h

@@ -3,30 +3,30 @@
 
 #include <rtthread.h>
 
-#define RT_TOUCH_NORMAL				0
-#define RT_TOUCH_CALIBRATION_DATA	1
-#define RT_TOUCH_CALIBRATION 		2
+#define RT_TOUCH_NORMAL             0
+#define RT_TOUCH_CALIBRATION_DATA   1
+#define RT_TOUCH_CALIBRATION        2
 #define RT_TOUCH_EVENTPOST          3
 #define RT_TOUCH_EVENTPOST_PARAM    4
 
 struct calibration_data
 {
-	rt_uint16_t min_x, max_x;
-	rt_uint16_t min_y, max_y;
+    rt_uint16_t min_x, max_x;
+    rt_uint16_t min_y, max_y;
 };
 
 struct rt_touch_event
 {
- 	rt_uint16_t x;
-	rt_uint16_t y;	
-	int         pressed;
+    rt_uint16_t x;
+    rt_uint16_t y;  
+    int pressed;
 };
 
 typedef void (*rt_touch_calibration_func_t)(rt_uint16_t x, rt_uint16_t y);
 
 typedef void (*rt_touch_eventpost_func_t)(void *, struct rt_touch_event *);
 
-void rtgui_touch_hw_init(void);
+int rtgui_touch_hw_init(void);
 
 #endif
 

bsp/mini2440/rtconfig.h

@@ -107,6 +107,12 @@
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
+#define RT_USING_SDIO
+#define RT_SDIO_STACK_SIZE 512
+#define RT_SDIO_THREAD_PRIORITY 15
+#define RT_MMCSD_STACK_SIZE 1024
+#define RT_MMCSD_THREAD_PREORITY 22
+#define RT_MMCSD_MAX_PARTITION 16
 
 /* Using USB */
 

bsp/mini2440/rtconfig.py

@@ -1,9 +1,5 @@
 import os
 
-# panel options
-# 'PNL_A70','PNL_N35', 'PNL_T35' , 'PNL_X35'
-RT_USING_LCD_TYPE = 'PNL_T35'
-
 # toolchains options
 ARCH     = 'arm'
 CPU      = 's3c24x0'

bsp/nrf5x/libraries/drivers/drv_uart.c

@@ -1,59 +1,83 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-28     xckhmf       Modify for <nrfx>
+ *
+ */
 #include <rtdevice.h>
 #include <nrfx_uart.h>
 #include "drv_uart.h"
 
-static struct rt_serial_device _serial0_0;
-static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context);
+#ifdef BSP_USING_UART
 
 typedef struct
 {
     struct rt_serial_device *serial;
     nrfx_uart_t uart;
+    uint8_t rx_byte;
+    uint16_t rx_length;
     uint32_t rx_pin;
     uint32_t tx_pin;
     nrfx_uart_event_handler_t event_handler;
-} UART_CFG_T;
+} drv_uart_cfg_t;
 
-
-UART_CFG_T uart0 = {
+#ifdef BSP_USING_UART0
+static struct rt_serial_device _serial_0;
+static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context);
+drv_uart_cfg_t m_uart0_cfg = {
     .uart = NRFX_UART_INSTANCE(0),
-#ifdef RT_USING_CONSOLE
-    .rx_pin = 8,
-    .tx_pin = 6,
-    .event_handler = uart_event_hander,
-#else
-    .rx_pin = 19,
-    .tx_pin = 20
-#endif
+    .rx_byte = 0,
+    .rx_length = 0,
+    .rx_pin = BSP_UART0_RX_PIN,
+    .tx_pin = BSP_UART0_TX_PIN,
+    .event_handler = uart0_event_hander
 };
-UART_CFG_T *working_cfg = RT_NULL;
+#endif  /* BSP_USING_UART0 */
 
-static void uart_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
-{
-    
+#ifdef BSP_USING_UART1
+    #error <nrfx_uart> not support UART1. Use UART0 instead.
+#endif  /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART0
+static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
+{   
     if (p_event->type == NRFX_UART_EVT_RX_DONE)
     {
-        rt_hw_serial_isr(working_cfg->serial, RT_SERIAL_EVENT_RX_IND);
+        if(p_event->data.rxtx.bytes == 1)
+        {
+            m_uart0_cfg.rx_length = p_event->data.rxtx.bytes;
+            
+            /* rx_byte equal p_data  */
+            //m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data); 
+            
+            rt_hw_serial_isr(m_uart0_cfg.serial, RT_SERIAL_EVENT_RX_IND);
+        }
+        nrfx_uart_rx(&(m_uart0_cfg.uart),&m_uart0_cfg.rx_byte,1);
     }
     if (p_event->type == NRFX_UART_EVT_TX_DONE)
     {
-        
+        /* @TODO:[RT_DEVICE_FLAG_INT_TX]*/
     }
 }
+#endif  /* BSP_USING_UART0 */
 
 static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-    nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(uart0.tx_pin,uart0.rx_pin);
-    UART_CFG_T *instance = &uart0;
+    nrfx_uart_config_t config = NRFX_UART_DEFAULT_CONFIG(BSP_UART0_TX_PIN,BSP_UART0_RX_PIN);
+    drv_uart_cfg_t *instance = RT_NULL;
 
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-
-    if (serial->parent.user_data != RT_NULL)
+  
+    if (serial->parent.user_data == RT_NULL)
     {
-        instance = (UART_CFG_T*)serial->parent.user_data;
+        return -RT_ERROR;
     }
-
+    instance = (drv_uart_cfg_t*)serial->parent.user_data;
     nrfx_uart_uninit(&(instance->uart));
 
     switch (cfg->baud_rate)
@@ -83,28 +107,23 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
     config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED;
     config.pselrxd = instance->rx_pin;
     config.pseltxd = instance->tx_pin;
-
-    nrfx_uart_init(&(instance->uart), &config, instance->event_handler);
     
-    nrf_uart_int_enable(instance->uart.p_reg, NRF_UART_INT_MASK_RXDRDY | NRF_UART_INT_MASK_RXTO | NRF_UART_INT_MASK_ERROR);
+    nrfx_uart_init(&(instance->uart), &config, instance->event_handler);
+    nrfx_uart_rx(&(instance->uart),&(instance->rx_byte),1);
     nrf_uart_int_disable(instance->uart.p_reg, NRF_UART_INT_MASK_TXDRDY);
-    
-    nrfx_uart_rx_enable(&(instance->uart));
-    
-    working_cfg = instance;
     return RT_EOK;
 }
 
 static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
 {
-    UART_CFG_T *instance = working_cfg;
-
+    drv_uart_cfg_t *instance = NULL;
     RT_ASSERT(serial != RT_NULL);
 
-    if (serial->parent.user_data != RT_NULL)
+    if (serial->parent.user_data == RT_NULL)
     {
-        instance = (UART_CFG_T*)serial->parent.user_data;
+        return -RT_ERROR;
     }
+    instance = (drv_uart_cfg_t*)serial->parent.user_data;
 
     switch (cmd)
     {
@@ -129,10 +148,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
         break;
 
     case RT_DEVICE_CTRL_PIN:
-        if (working_cfg != instance)
-        {
-            _uart_cfg(instance->serial, &(instance->serial->config));
-        }
+        _uart_cfg(instance->serial, &(instance->serial->config));
         break;
 
     case RT_DEVICE_POWERSAVE:
@@ -152,13 +168,13 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
 
 static int _uart_putc(struct rt_serial_device *serial, char c)
 {
-    UART_CFG_T *instance = working_cfg;
+    drv_uart_cfg_t *instance = NULL;
     int rtn = 1;
     RT_ASSERT(serial != RT_NULL);
 
     if (serial->parent.user_data != RT_NULL)
     {
-        instance = (UART_CFG_T*)serial->parent.user_data;
+        instance = (drv_uart_cfg_t*)serial->parent.user_data;
     }
 
     nrf_uart_event_clear(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY);
@@ -171,23 +187,21 @@ static int _uart_putc(struct rt_serial_device *serial, char c)
     return rtn;
 }
 
-/* 
-    @note: this function is invaild ,the cause of the problem is [nrfx_uart.c - line 340] 
-*/
 static int _uart_getc(struct rt_serial_device *serial)
 {
     int ch = -1;
-    UART_CFG_T *instance = working_cfg;
-
+    drv_uart_cfg_t *instance = NULL;
     RT_ASSERT(serial != RT_NULL);
 
     if (serial->parent.user_data != RT_NULL)
     {
-        instance = (UART_CFG_T*)serial->parent.user_data;
+        instance = (drv_uart_cfg_t*)serial->parent.user_data;
+    }  
+    if(instance->rx_length)
+    {
+        ch = instance->rx_byte;
+        instance->rx_length--;
     }
-    
-    ch = (int)(nrf_uart_rxd_get(instance->uart.p_reg));
-    
     return ch;
 }
 
@@ -202,11 +216,14 @@ void rt_hw_uart_init(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
-    config.bufsz = RT_SERIAL_RB_BUFSZ;
-    _serial0_0.config = config;
-    _serial0_0.ops = &_uart_ops;
-    uart0.serial = &_serial0_0;
+#ifdef BSP_USING_UART0
+    _serial_0.config = config;
+    _serial_0.ops = &_uart_ops;
+    m_uart0_cfg.serial = &_serial_0;
+    rt_hw_serial_register(&_serial_0, "uart0", \
+                            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,  &m_uart0_cfg);
+#endif  /* BSP_USING_UART0 */
 
-    rt_hw_serial_register(&_serial0_0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,  &uart0);
 }
 
+#endif /* BSP_USING_UART */

bsp/nrf5x/nrf52840/rtconfig.h

@@ -155,10 +155,13 @@
 
 /* Onboard Peripheral Drivers */
 
+#define BSP_USING_JLINK_TO_USART
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_UART
 #define BSP_USING_UART0
+#define BSP_UART0_RX_PIN 8
+#define BSP_UART0_TX_PIN 6
 
 #endif

bsp/nuclei/.gitignore

@@ -0,0 +1,26 @@
+*.i
+*.o
+*.d
+*.elf
+*.diss
+*.map
+*.bin
+*.log
+.vscode
+
+*.dump
+*.verilog
+
+*.swp
+*.swo
+
+prebuilt_tools/
+setup_config.sh
+setup_config.bat
+
+tags
+TAGS
+TAG
+CTAGS
+Makefile.local
+Makefile.global

bsp/nuclei/gd32vf103_rvstar/.config

@@ -0,0 +1,453 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=396
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+CONFIG_RT_DEBUG_INIT_CONFIG=y
+CONFIG_RT_DEBUG_INIT=1
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+CONFIG_PKG_USING_NUCLEI_SDK=y
+CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk"
+# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set
+CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y
+CONFIG_PKG_NUCLEI_SDK_VER="latest"
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_GD32VF103V=y
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_UART_CONSOLE=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+
+#
+# Board extended module Drivers
+#
+CONFIG_SOC_GD32VF103=y

bsp/nuclei/gd32vf103_rvstar/Kconfig

@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
+config SOC_GD32VF103
+    bool
+    select ARCH_RISCV32
+    select PKG_USING_NUCLEI_SDK
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y

bsp/nuclei/gd32vf103_rvstar/README.md

@@ -0,0 +1,209 @@
+# 芯来科技RVSTAR开发板 #
+
+## 简介
+
+**RVSTAR开发板** 是由芯来科技公司推出的基于采用芯来科技RISC-V架构处理器芯片的GD32VF103的开发板。
+
+更多关于 **RVSTAR开发板** 开发板的详细资料请参见 [RVSTAR开发板快速入门](https://www.rvmcu.com/quickstart-quickstart-index-u-RV_STAR.html)
+
+### 板载资源
+
+| 硬件 | 描述 |
+| ---  | --- |
+| 内核 | Nuclei N205 |
+| 架构 | 32-bit RV32IMAC |
+| 主频 | 108 MHz |
+
+## 工具安装
+
+### 安装工具链
+
+请根据[安装Nuclei RISC-V GCC Toolchain和OpenOCD](https://doc.nucleisys.com/nuclei_sdk/quickstart.html#setup-tools-and-environment) 来安装依赖的工具。
+
+### 添加环境变量
+
+将Nuclei RISC-V GCC Toolchain和OpenOCD的环境变量进行设置。
+
+#### Windows
+
+假设工具安装在 **D:\Software\Nuclei**目录下, 则可以修改系统环境变量**PATH**,
+将**D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;**增加到**PATH**中。
+
+或者在ENV工具命令行中运行
+
+~~~cmd
+set PATH=D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;%PATH%
+~~~
+
+#### Linux
+
+假设工具安装在 **~/Software/Nuclei**目录下, 通过在Linux的``.bashrc``增加如下一行代码
+来添加环境变量。
+
+~~~bash
+export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
+~~~
+
+或者在ENV工具命令行中运行
+
+~~~bash
+export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
+~~~
+
+**注意**: 对应的RISC-V GCC和OPENOCD的路径请替换成自己安装的路径。
+
+## 烧写及执行
+
+### [驱动设置](https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html#on-board-debugger-driver)
+
+### 编译程序
+
+下载好[RT-Thread](https://github.com/RT-Thread/rt-thread)的代码和[ENV工具](https://www.rt-thread.org/document/site/tutorial/env-video/)以后。
+
+按照ENV工具的教程, 在**rt-thread\bsp\nuclei\gd32vf103_rvstar**目录打开ENV工具命令行。
+
+**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
+
+1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
+2. **可选**: 运行 ``menuconfig``来进行内核配置
+3. 运行 ``scons -c``清理之前的编译结果
+4. 运行 ``scons``来进行代码的编译
+
+### 下载程序
+
+在保证程序能够正常编译后, 在相同ENV终端执行``scons --run upload``进行代码的下载。
+
+正常下载的输出如下:
+
+~~~
+scons: Reading SConscript files ...
+Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
+Upload application rtthread.elf using openocd and gdb
+riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240"                     -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"                     --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load"                     -ex "monitor resume" -ex "monitor shutdown" -ex "quit"
+D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
+
+Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:251
+251                 if (idle_hook_list[i] != RT_NULL)
+cleared protection for sectors 0 through 127 on flash bank 0
+
+Loading section .init, size 0x264 lma 0x8000000
+Loading section .text, size 0x140de lma 0x8000280
+Loading section .rodata, size 0x37c0 lma 0x8014360
+Loading section .data, size 0x404 lma 0x8017b20
+Start address 0x800015c, load size 98054
+Transfer rate: 8 KB/sec, 10894 bytes/write.
+shutdown command invoked
+A debugging session is active.
+
+        Inferior 1 [Remote target] will be detached.
+
+Quit anyway? (y or n) [answered Y; input not from terminal]
+Remote communication error.  Target disconnected.: Success.
+~~~
+
+下载程序之后, 连接串口(115200-N-8-1), 可以看到 RT-Thread 的输出信息：
+
+```
+initialize rti_board_start:0 done
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Apr  9 2020
+ 2006 - 2020 Copyright by rt-thread team
+do components initialization.
+initialize rti_board_end:0 done
+initialize dfs_init:0 done
+initialize libc_system_init:0 done
+initialize finsh_system_init:0 done
+msh />
+```
+
+在串口终端(我这里使用的是TeraTerm)输入``ps``即可查看当前线程工作情况:
+
+~~~
+msh />ps
+thread   pri  status      sp     stack size max used left tick  error
+-------- ---  ------- ---------- ----------  ------  ---------- ---
+thread01  19  suspend 0x00000158 0x0000018c    87%   0x00000005 000
+thread00  19  suspend 0x00000158 0x0000018c    87%   0x00000005 000
+tshell    20  running 0x00000258 0x00001000    18%   0x00000004 000
+tidle0    31  ready   0x000000a8 0x0000018c    59%   0x0000000e 000
+timer      4  suspend 0x000000f8 0x00000200    49%   0x00000009 000
+main      10  suspend 0x00000168 0x00000800    36%   0x00000006 000
+msh />
+~~~
+
+### 调试程序
+
+在保证程序编译成功后, 在相同ENV终端执行``scons --run debug``进行代码在命令行下进行GDB调试。
+
+正常的调试输出如下：
+
+~~~
+scons: Reading SConscript files ...
+Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
+Debug application rtthread.elf using openocd and gdb
+riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240"                     -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"
+D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
+GNU gdb (GDB) 8.3.0.20190516-git
+Copyright (C) 2019 Free Software Foundation, Inc.
+License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+This is free software: you are free to change and redistribute it.
+There is NO WARRANTY, to the extent permitted by law.
+Type "show copying" and "show warranty" for details.
+This GDB was configured as "--host=i686-w64-mingw32 --target=riscv-nuclei-elf".
+Type "show configuration" for configuration details.
+For bug reporting instructions, please see:
+<http://www.gnu.org/software/gdb/bugs/>.
+Find the GDB manual and other documentation resources online at:
+    <http://www.gnu.org/software/gdb/documentation/>.
+
+For help, type "help".
+Type "apropos word" to search for commands related to "word"...
+Reading symbols from rtthread.elf...
+Remote debugging using | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:249
+249             for (i = 0; i < RT_IDLE_HOOK_LIST_SIZE; i++)
+(gdb)
+(gdb) b main.c:35
+Breakpoint 1 at 0x8000290: file applications\main.c, line 35.
+(gdb) c
+Continuing.
+Note: automatically using hardware breakpoints for read-only addresses.
+
+Breakpoint 1, thread_entry (parameter=0x0) at applications\main.c:35
+35              rt_thread_mdelay(500);
+(gdb)
+~~~
+
+调试例子参见如下文档:
+
+* https://doc.nucleisys.com/nuclei_sdk/quickstart.html#debug-application
+
+为了更方便的进行调试, 也可以下载**Nuclei Studio**集成开发环境, 创建一个Debug Configuration, 选择编译好的
+ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nuclei\gd32vf103_rvstar\packages\nuclei_sdk-latest\SoC\gd32vf103\Board\gd32vf103v_rvstar\openocd_gd32vf103.cfg**
+
+
+## 驱动支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | RV-STAR板载串口是UART4 |
+
+**注:**
+
+- 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。
+- 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。
+
+## 联系人信息
+
+维护人：
+- [fanghuaqi](https://github.com/fanghuaqi)
+

bsp/nuclei/gd32vf103_rvstar/SConscript

@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/nuclei/gd32vf103_rvstar/SConstruct

@@ -0,0 +1,85 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+bsp_library_type = rtconfig.NUCLEI_SDK_SOC
+rtconfig.BSP_LIBRARY_TYPE = bsp_library_type
+
+openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/')
+
+# include hal drivers
+hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript')
+
+if os.path.isfile(hal_sconscript):
+    objs.extend(SConscript(hal_sconscript))
+
+# make a building
+DoBuilding(TARGET, objs)
+
+# Run upload or debug if --run=upload or --upload=debug
+run_target = GetOption('run')
+SUPPORT_RUN_TARGETS = ["upload", "debug"]
+if run_target in SUPPORT_RUN_TARGETS:
+    if os.path.isfile(TARGET):
+        if run_target == "upload":
+            upload_cmd = '{} {} -ex "set remotetimeout 240" \
+                    -ex "target remote | openocd --pipe -f {}" \
+                    --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" \
+                    -ex "monitor resume" -ex "monitor shutdown" -ex "quit"'.format(GDB, TARGET, openocd_cfg)
+            print("Upload application {} using openocd and gdb".format(TARGET))
+            print(upload_cmd)
+            os.system(upload_cmd)
+        elif run_target == "debug":
+            debug_cmd = '{} {} -ex "set remotetimeout 240" \
+                    -ex "target remote | openocd --pipe -f {}"'.format(GDB, TARGET, openocd_cfg)
+            print("Debug application {} using openocd and gdb".format(TARGET))
+            print(debug_cmd)
+            os.system(debug_cmd)
+    else:
+        print(TARGET + ' not exist, please run scons first!!')
+    exit(0)

bsp/nuclei/gd32vf103_rvstar/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd, ]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nuclei/gd32vf103_rvstar/applications/main.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     hqfang       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+int main(int argc, char *argv[])
+{
+    return RT_EOK;
+}
+
+/******************** end of file *******************/

bsp/nuclei/gd32vf103_rvstar/board/Kconfig

@@ -0,0 +1,47 @@
+menu "Hardware Drivers Config"
+
+config SOC_GD32VF103V
+    bool
+    select SOC_SERIES_GD32VF103V
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_UART_CONSOLE
+        bool "Enable UART CONSOLE"
+        select BSP_USING_UART
+        select BSP_USING_UART4
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+        endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/nuclei/gd32vf103_rvstar/board/SConscript

@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nuclei/gd32vf103_rvstar/board/board.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-02     hqfang       first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "cpuport.h"
+
+#ifdef RT_USING_SERIAL
+    #include <drv_usart.h>
+#endif
+
+/** _end symbol defined in linker script of Nuclei SDK */
+extern void *_end;
+
+/** _heap_end symbol defined in linker script of Nuclei SDK */
+extern void *_heap_end;
+#define HEAP_BEGIN  &_end
+#define HEAP_END    &_heap_end
+
+/*
+ * - Implemented and defined in Nuclei SDK system_<Device>.c file
+ * - Required macro NUCLEI_BANNER set to 0
+ */
+extern void _init(void);
+
+/**
+ * @brief Setup hardware board for rt-thread
+ *
+ */
+void rt_hw_board_init(void)
+{
+    /* OS Tick Configuration */
+    rt_hw_ticksetup();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
+#endif
+
+    _init(); // __libc_init_array is not used in RT-Thread
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/******************** end of file *******************/
+

bsp/nuclei/gd32vf103_rvstar/board/board.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2020-04-02     hqfang          first version
+ *
+ */
+
+#ifndef __BOARD__
+#define __BOARD__
+
+#include "nuclei_sdk_hal.h"
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD__ */
+
+/******************** end of file *******************/

bsp/nuclei/gd32vf103_rvstar/rtconfig.h

@@ -0,0 +1,181 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 396
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+#define RT_DEBUG_INIT_CONFIG
+#define RT_DEBUG_INIT 1
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart4"
+#define RT_VER_NUM 0x40003
+#define ARCH_RISCV
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_NUCLEI_SDK
+#define PKG_USING_NUCLEI_SDK_LATEST_VERSION
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_GD32VF103V
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_UART_CONSOLE
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART4
+
+/* Board extended module Drivers */
+
+#define SOC_GD32VF103
+
+#endif

bsp/nuclei/gd32vf103_rvstar/rtconfig.py

@@ -0,0 +1,58 @@
+import os
+
+# toolchains options
+ARCH='risc-v'
+CPU='nuclei'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if CROSS_TOOL == 'gcc':
+    PLATFORM  = 'gcc'
+    EXEC_PATH = 'D:/Software/Nuclei/gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+# if os.getenv('RTT_EXEC_PATH'):
+#     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+# Fixed configurations below
+NUCLEI_SDK_SOC = "gd32vf103"
+NUCLEI_SDK_BOARD = "gd32vf103v_rvstar"
+NUCLEI_SDK_DOWNLOAD = "flashxip"
+NUCLEI_SDK_CORE = "n205"
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv-nuclei-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    GDB     = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    CFLAGS  = ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS  = CFLAGS
+    LFLAGS  = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections '
+    LFLAGS += ' -Wl,-cref,-Map=rtthread.map'
+    LFLAGS  += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek '
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2 -Os'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript

@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-04-08     hqfang            first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c

@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-04-09     hqfang            first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+static const struct pin_index pins[] =
+{
+
+    __GD32_PIN(0, A, 0),
+    __GD32_PIN(1, A, 1),
+    __GD32_PIN(2, A, 2),
+    __GD32_PIN(3, A, 3),
+    __GD32_PIN(4, A, 4),
+    __GD32_PIN(5, A, 5),
+    __GD32_PIN(6, A, 6),
+    __GD32_PIN(7, A, 7),
+    __GD32_PIN(8, A, 8),
+    __GD32_PIN(9, A, 9),
+    __GD32_PIN(10, A, 10),
+    __GD32_PIN(11, A, 11),
+    __GD32_PIN(12, A, 12),
+    __GD32_PIN(13, A, 13),
+    __GD32_PIN(14, A, 14),
+    __GD32_PIN(15, A, 15),
+
+    __GD32_PIN(16, B, 0),
+    __GD32_PIN(17, B, 1),
+    __GD32_PIN(18, B, 2),
+    __GD32_PIN(19, B, 3),
+    __GD32_PIN(20, B, 4),
+    __GD32_PIN(21, B, 5),
+    __GD32_PIN(22, B, 6),
+    __GD32_PIN(23, B, 7),
+    __GD32_PIN(24, B, 8),
+    __GD32_PIN(25, B, 9),
+    __GD32_PIN(26, B, 10),
+    __GD32_PIN(27, B, 11),
+    __GD32_PIN(28, B, 12),
+    __GD32_PIN(29, B, 13),
+    __GD32_PIN(30, B, 14),
+    __GD32_PIN(31, B, 15),
+
+    __GD32_PIN(32, C, 0),
+    __GD32_PIN(33, C, 1),
+    __GD32_PIN(34, C, 2),
+    __GD32_PIN(35, C, 3),
+    __GD32_PIN(36, C, 4),
+    __GD32_PIN(37, C, 5),
+    __GD32_PIN(38, C, 6),
+    __GD32_PIN(39, C, 7),
+    __GD32_PIN(40, C, 8),
+    __GD32_PIN(41, C, 9),
+    __GD32_PIN(42, C, 10),
+    __GD32_PIN(43, C, 11),
+    __GD32_PIN(44, C, 12),
+    __GD32_PIN(45, C, 13),
+    __GD32_PIN(46, C, 14),
+    __GD32_PIN(47, C, 15),
+
+    __GD32_PIN(48, D, 0),
+    __GD32_PIN(49, D, 1),
+    __GD32_PIN(50, D, 2),
+    __GD32_PIN(51, D, 3),
+    __GD32_PIN(52, D, 4),
+    __GD32_PIN(53, D, 5),
+    __GD32_PIN(54, D, 6),
+    __GD32_PIN(55, D, 7),
+    __GD32_PIN(56, D, 8),
+    __GD32_PIN(57, D, 9),
+    __GD32_PIN(58, D, 10),
+    __GD32_PIN(59, D, 11),
+    __GD32_PIN(60, D, 12),
+    __GD32_PIN(61, D, 13),
+    __GD32_PIN(62, D, 14),
+    __GD32_PIN(63, D, 15),
+
+    __GD32_PIN(64, E, 0),
+    __GD32_PIN(65, E, 1),
+    __GD32_PIN(66, E, 2),
+    __GD32_PIN(67, E, 3),
+    __GD32_PIN(68, E, 4),
+    __GD32_PIN(69, E, 5),
+    __GD32_PIN(70, E, 6),
+    __GD32_PIN(71, E, 7),
+    __GD32_PIN(72, E, 8),
+    __GD32_PIN(73, E, 9),
+    __GD32_PIN(74, E, 10),
+    __GD32_PIN(75, E, 11),
+    __GD32_PIN(76, E, 12),
+    __GD32_PIN(77, E, 13),
+    __GD32_PIN(78, E, 14),
+    __GD32_PIN(79, E, 15),
+};
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_IRQn},
+    {GPIO_PIN_1, EXTI1_IRQn},
+    {GPIO_PIN_2, EXTI2_IRQn},
+    {GPIO_PIN_3, EXTI3_IRQn},
+    {GPIO_PIN_4, EXTI4_IRQn},
+    {GPIO_PIN_5, EXTI5_9_IRQn},
+    {GPIO_PIN_6, EXTI5_9_IRQn},
+    {GPIO_PIN_7, EXTI5_9_IRQn},
+    {GPIO_PIN_8, EXTI5_9_IRQn},
+    {GPIO_PIN_9, EXTI5_9_IRQn},
+    {GPIO_PIN_10, EXTI10_15_IRQn},
+    {GPIO_PIN_11, EXTI10_15_IRQn},
+    {GPIO_PIN_12, EXTI10_15_IRQn},
+    {GPIO_PIN_13, EXTI10_15_IRQn},
+    {GPIO_PIN_14, EXTI10_15_IRQn},
+    {GPIO_PIN_15, EXTI10_15_IRQn},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    gpio_bit_write(index->gpio, index->pin, (bit_status)value);
+}
+
+static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = gpio_input_bit_get(index->gpio, index->pin);
+
+    return value;
+}
+
+static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    rt_uint32_t pin_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    pin_mode = GPIO_MODE_OUT_PP;
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        /* output setting */
+        pin_mode = GPIO_MODE_OUT_PP;
+        break;
+    case PIN_MODE_OUTPUT_OD:
+        /* output setting: od. */
+        pin_mode = GPIO_MODE_OUT_OD;
+        break;
+    case PIN_MODE_INPUT:
+        /* input setting: not pull. */
+        pin_mode = GPIO_MODE_IN_FLOATING;
+        break;
+    case PIN_MODE_INPUT_PULLUP:
+        /* input setting: pull up. */
+        pin_mode = GPIO_MODE_IPU;
+        break;
+    case PIN_MODE_INPUT_PULLDOWN:
+        /* input setting: pull down. */
+        pin_mode = GPIO_MODE_IPD;
+        break;
+    default:
+        break;
+    }
+
+    gpio_init(index->gpio, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    int i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                    rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    exti_trig_type_enum trigger_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(index->pin);
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        irqmap = &pin_irq_map[irqindex];
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            trigger_mode = EXTI_TRIG_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            trigger_mode = EXTI_TRIG_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            trigger_mode = EXTI_TRIG_BOTH;
+            break;
+        default:
+            rt_hw_interrupt_enable(level);
+            return RT_EINVAL;
+        }
+        /* connect EXTI line to  GPIO pin */
+        gpio_exti_source_select(index->gpio, index->pin);
+
+        /* configure EXTI line */
+        exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
+        exti_interrupt_flag_clear((exti_line_enum)(index->pin));
+
+        /* enable and set interrupt priority */
+        ECLIC_SetShvIRQ(irqmap->irqno, ECLIC_NON_VECTOR_INTERRUPT);
+        ECLIC_SetLevelIRQ(irqmap->irqno, 1);
+        ECLIC_EnableIRQ(irqmap->irqno);
+        pin_irq_enable_mask |= irqmap->pinbit;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_EINVAL;
+        }
+        if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
+            {
+                ECLIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
+            {
+                ECLIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else
+        {
+            ECLIC_DisableIRQ(irqmap->irqno);
+        }
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _gd32_pin_ops =
+{
+    gd32_pin_mode,
+    gd32_pin_write,
+    gd32_pin_read,
+    gd32_pin_attach_irq,
+    gd32_pin_dettach_irq,
+    gd32_pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
+{
+    if (RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
+    {
+        pin_irq_hdr(exti_line);
+        exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
+    }
+}
+
+void EXTI0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(0);
+    rt_interrupt_leave();
+}
+void EXTI1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(1);
+    rt_interrupt_leave();
+}
+void EXTI2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(2);
+    rt_interrupt_leave();
+}
+void EXTI3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(3);
+    rt_interrupt_leave();
+}
+void EXTI4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(4);
+    rt_interrupt_leave();
+}
+void EXTI5_9_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(5);
+    GD32_GPIO_EXTI_IRQHandler(6);
+    GD32_GPIO_EXTI_IRQHandler(7);
+    GD32_GPIO_EXTI_IRQHandler(8);
+    GD32_GPIO_EXTI_IRQHandler(9);
+    rt_interrupt_leave();
+}
+void EXTI10_15_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(10);
+    GD32_GPIO_EXTI_IRQHandler(11);
+    GD32_GPIO_EXTI_IRQHandler(12);
+    GD32_GPIO_EXTI_IRQHandler(13);
+    GD32_GPIO_EXTI_IRQHandler(14);
+    GD32_GPIO_EXTI_IRQHandler(15);
+    rt_interrupt_leave();
+}
+
+int rt_hw_pin_init(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_GPIOD);
+    rcu_periph_clock_enable(RCU_GPIOE);
+    rcu_periph_clock_enable(RCU_AF);
+    return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif /* RT_USING_PIN */

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-11-06     balanceTWK        first version
+ * 2020-04-15     hqfang            Modify for gd32vf103
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+#define __GD32_PORT(port)  GPIO##port
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN)
+
+#define __GD32_PIN(index, gpio, gpio_index)                                \
+    {                                                                      \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                           \
+    }
+
+#define __GD32_PIN_RESERVE                                                 \
+    {                                                                      \
+        -1, 0, 0                                                           \
+    }
+
+/* GD32 GPIO driver */
+struct pin_index
+{
+    int index;
+    uint32_t gpio;
+    uint32_t pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */
+

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c

@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ * 2020-04-02     hqfang       modified for Nuclei
+ */
+
+#include <drv_usart.h>
+
+#ifdef RT_USING_SERIAL
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
+    && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4)
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+    GDUART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    GDUART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    GDUART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    GDUART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    GDUART4_INDEX,
+#endif
+};
+
+static struct gd32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    {
+        "uart0",
+        USART0,
+        USART0_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART1
+    {
+        "uart1",
+        USART1,
+        USART1_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART2
+    {
+        "uart2",
+        USART2,
+        USART2_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART3
+    {
+        "uart3",
+        USART3,
+        USART3_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART4
+    {
+        "uart4",
+        UART4,
+        UART4_IRQn,
+    },
+#endif
+};
+
+static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static rt_err_t gd32_configure(struct rt_serial_device *serial,
+                               struct serial_configure *cfg)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_deinit(usart->uart_base);
+    usart_baudrate_set(usart->uart_base, cfg->baud_rate);
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        usart_word_length_set(usart->uart_base, USART_WL_8BIT);
+        break;
+
+    case DATA_BITS_9:
+        usart_word_length_set(usart->uart_base, USART_WL_9BIT);
+        break;
+    default:
+        usart_word_length_set(usart->uart_base, USART_WL_8BIT);
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
+        break;
+    case STOP_BITS_2:
+        usart_stop_bit_set(usart->uart_base, USART_STB_2BIT);
+        break;
+    default:
+        usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        usart_parity_config(usart->uart_base, USART_PM_NONE);
+        break;
+    case PARITY_ODD:
+        usart_parity_config(usart->uart_base, USART_PM_ODD);
+        break;
+    case PARITY_EVEN:
+        usart_parity_config(usart->uart_base, USART_PM_EVEN);
+        break;
+    default:
+        usart_parity_config(usart->uart_base, USART_PM_NONE);
+        break;
+    }
+    usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_hardware_flow_cts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE);
+    usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE);
+    usart_enable(usart->uart_base);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd,
+                             void *arg)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        ECLIC_DisableIRQ(usart->irqn);
+        usart_interrupt_disable(usart->uart_base, USART_INT_RBNE);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        ECLIC_EnableIRQ(usart->irqn);
+        /* enable USART0 receive interrupt */
+        usart_interrupt_enable(usart->uart_base, USART_INT_RBNE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int gd32_putc(struct rt_serial_device *serial, char ch)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_data_transmit(usart->uart_base, (uint8_t) ch);
+    while (usart_flag_get(usart->uart_base, USART_FLAG_TBE) == RESET);
+
+    return 1;
+}
+
+static int gd32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    ch = -1;
+    if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))
+    {
+        ch = usart_data_receive(usart->uart_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control,
+           gd32_putc, gd32_getc,
+           RT_NULL
+};
+
+static void usart_isr(struct rt_serial_device *serial)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE)
+            != RESET)
+            && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)))
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE);
+        usart_flag_clear(usart->uart_base, USART_FLAG_RBNE);
+    }
+    else
+    {
+        if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_CTSF);
+        }
+
+        if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_LBDF);
+        }
+
+        if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_TC);
+        }
+    }
+}
+
+#ifdef BSP_USING_UART0
+
+void USART0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART0_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART1
+
+void USART1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART1_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART2
+
+void USART2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART2_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART3
+
+void UART3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART3_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART4
+
+void UART4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART4_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num;
+    int index;
+
+    obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (index = 0; index < obj_num; index++)
+    {
+        /* init UART object */
+        uart_obj[index].config = &uart_config[index];
+        uart_obj[index].serial.ops = &gd32_uart_ops;
+        uart_obj[index].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[index].serial,
+                                       uart_obj[index].config->name,
+                                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */
+
+/******************** end of file *******************/

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     hqfang       first version
+ */
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_uart_config
+{
+    const char *name;
+    uint32_t uart_base;
+    IRQn_Type irqn;
+};
+
+/* gd32 uart dirver class */
+struct gd32_uart
+{
+    struct gd32_uart_config *config;
+    struct rt_serial_device serial;
+};
+
+int rt_hw_usart_init(void);
+
+#endif /* __DRV_USART_H__ */
+
+/******************* end of file *******************/

bsp/raspberry-pi/raspi3-64/README.md

@@ -17,7 +17,7 @@
 
 Windows环境下推荐使用[env工具][1]进行编译。
 
-首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
 
 将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
 
@@ -31,6 +31,16 @@ EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.0
 
 然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
 
+**window环境搭建注意**
+
+下载完成`gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf.tar.xz`交叉编译工具链后，最好采用7-zip解压工具进行两次解压。
+确保解压目录下的`/bin/aarch64-elf-ld.exe`文件的size不为0。
+否则编译会出现如下错误:
+
+```
+collect2.exe:fatal error:CreateProcess:No such file or directory
+```
+
 ### 2.2 Linux上的环境搭建
 
 Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。

bsp/raspberry-pi/raspi3-64/driver/drv_fb.c

@@ -15,9 +15,10 @@
 #include "drv_fb.h"
 #include "mmu.h"
 
-#define LCD_WIDTH     (640)
+#define LCD_WIDTH     (800)
 #define LCD_HEIGHT    (480)
 #define LCD_DEPTH     (32)
+#define LCD_BPP       (32)
 
 #define TAG_ALLOCATE_BUFFER         0x00040001
 #define TAG_SET_PHYS_WIDTH_HEIGHT   0x00048003
@@ -28,6 +29,39 @@
 #define TAG_SET_VIRT_OFFSET         0x00048009
 #define TAG_END                     0x00000000
 
+
+enum {
+    MBOX_TAG_FB_GET_GPIOVIRT        = 0x00040010,
+    MBOX_TAG_FB_ALLOCATE_BUFFER     = 0x00040001,
+    MBOX_TAG_FB_RELEASE_BUFFER      = 0x00048001,
+    MBOX_TAG_FB_BLANK_SCREEN        = 0x00040002,
+    MBOX_TAG_FB_GET_PHYS_WH         = 0x00040003,
+    MBOX_TAG_FB_TEST_PHYS_WH        = 0x00044003,
+    MBOX_TAG_FB_SET_PHYS_WH         = 0x00048003,
+    MBOX_TAG_FB_GET_VIRT_WH         = 0x00040004,
+    MBOX_TAG_FB_TEST_VIRT_WH        = 0x00044004,
+    MBOX_TAG_FB_SET_VIRT_WH         = 0x00048004,
+    MBOX_TAG_FB_GET_DEPTH           = 0x00040005,
+    MBOX_TAG_FB_TEST_DEPTH          = 0x00044005,
+    MBOX_TAG_FB_SET_DEPTH           = 0x00048005,
+    MBOX_TAG_FB_GET_PIXEL_ORDER     = 0x00040006,
+    MBOX_TAG_FB_TEST_PIXEL_ORDER    = 0x00044006,
+    MBOX_TAG_FB_SET_PIXEL_ORDER     = 0x00048006,
+    MBOX_TAG_FB_GET_ALPHA_MODE      = 0x00040007,
+    MBOX_TAG_FB_TEST_ALPHA_MODE     = 0x00044007,
+    MBOX_TAG_FB_SET_ALPHA_MODE      = 0x00048007,
+    MBOX_TAG_FB_GET_PITCH           = 0x00040008,
+    MBOX_TAG_FB_GET_VIRT_OFFSET     = 0x00040009,
+    MBOX_TAG_FB_TEST_VIRT_OFFSET    = 0x00044009,
+    MBOX_TAG_FB_SET_VIRT_OFFSET     = 0x00048009,
+    MBOX_TAG_FB_GET_OVERSCAN        = 0x0004000a,
+    MBOX_TAG_FB_TEST_OVERSCAN       = 0x0004400a,
+    MBOX_TAG_FB_SET_OVERSCAN        = 0x0004800a,
+    MBOX_TAG_FB_GET_PALETTE         = 0x0004000b,
+    MBOX_TAG_FB_TEST_PALETTE        = 0x0004400b,
+    MBOX_TAG_FB_SET_PALETTE         = 0x0004800b,
+};
+
 #define LCD_DEVICE(dev)    (struct rt_hdmi_fb_device*)(dev)
 
 static struct rt_hdmi_fb_device _hdmi;
@@ -75,7 +109,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
             info->bits_per_pixel= LCD_DEPTH;
             info->width         = lcd->width;
             info->height        = lcd->height;
-            info->framebuffer   = lcd->fb;//(rt_uint8_t *)lcd->fb;
+            info->framebuffer   = lcd->fb;
         }
         break;
     }
@@ -119,38 +153,122 @@ rt_err_t rt_hdmi_fb_device_init(struct rt_hdmi_fb_device *hdmi_fb, const char *n
     return RT_EOK;
 }
 
-int hdmi_fb_init(void)
+rt_uint32_t bcm283x_mbox_fb_get_gpiovirt(void)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT;
+    mbox[3] = 4;                        // buffer size
+    mbox[4] = 0;                        // len
+
+    mbox[5] = 0;                        // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+    return (mbox[5] & 0x3fffffff);
+}
+
+rt_uint32_t bcm283x_mbox_fb_get_pitch(void)
+{
+    mbox[0] = 8*4;                  // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+    
+    mbox[2] = MBOX_TAG_FB_GET_PITCH;
+    mbox[3] = 4;                    // buffer size
+    mbox[4] = 0;                    // len
+
+    mbox[5] = 0;                    // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+    return mbox[5];
+}
+
+void bcm283x_mbox_fb_set_porder(int rgb)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER;
+    mbox[3] = 4;                        // buffer size
+    mbox[4] = 4;                        // len
+
+    mbox[5] = rgb;                      // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+}
+
+void bcm283x_mbox_fb_setoffset(int xoffset, int yoffset)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = xoffset;                  // id
+    mbox[6] = yoffset;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+}
+
+
+void bcm283x_mbox_fb_setalpha(int alpha)
+{
+
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE;
+    mbox[3] = 4;                        // buffer size
+    mbox[4] = 4;                        // len
+
+    mbox[5] = alpha;                    // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+}
+
+void *bcm283x_mbox_fb_alloc(int width, int height, int bpp, int nrender)
 {
     mbox[0] = 4 * 35;
     mbox[1] = MBOX_REQUEST;
 
     mbox[2] = TAG_ALLOCATE_BUFFER;//get framebuffer, gets alignment on request
-    mbox[3] = 8;
-    mbox[4] = 0;
-    mbox[5] = 4096;   //FrameBufferInfo.pointer
-    mbox[6] = 0;      //FrameBufferInfo.size
+    mbox[3] = 8;                  //size
+    mbox[4] = 4;                  //len
+    mbox[5] = 4096;               //The design of MBOX driver forces us to give the virtual address 0x3C100000
+    mbox[6] = 0;                  //FrameBufferInfo.size
 
     mbox[7] = TAG_SET_PHYS_WIDTH_HEIGHT;
     mbox[8] = 8;
-    mbox[9] = 0;
-    mbox[10] = LCD_WIDTH;
-    mbox[11] = LCD_HEIGHT;
+    mbox[9] = 8;
+    mbox[10] = width;
+    mbox[11] = height;
 
     mbox[12] = TAG_SET_VIRT_WIDTH_HEIGHT;
     mbox[13] = 8;
-    mbox[14] = 0;
-    mbox[15] = LCD_WIDTH;
-    mbox[16] = LCD_HEIGHT;
+    mbox[14] = 8;
+    mbox[15] = width;
+    mbox[16] = height * nrender;
 
     mbox[17] = TAG_SET_DEPTH;
     mbox[18] = 4;
-    mbox[19] = 0;
-    mbox[20] = 16;    //FrameBufferInfo.depth RGB 565
+    mbox[19] = 4;
+    mbox[20] = bpp;
 
     mbox[21] = TAG_SET_PIXEL_ORDER;
     mbox[22] = 4;
     mbox[23] = 0;
-    mbox[24] = 1;     //RGB, not BGR preferably
+    mbox[24] = 0;                    //RGB, not BGR preferably
 
     mbox[25] = TAG_GET_PITCH;
     mbox[26] = 4;
@@ -167,17 +285,25 @@ int hdmi_fb_init(void)
 
     mbox_call(MBOX_CH_PROP, MMU_DISABLE);
 
-    _hdmi.fb = (rt_uint8_t *)(uintptr_t)(mbox[5] & 0x3FFFFFFF);
+    return (void *)((rt_uint64_t)(mbox[5] & 0x3fffffff));
+}
 
+int hdmi_fb_init(void)
+{
+    _hdmi.fb = (rt_uint8_t *)bcm283x_mbox_fb_alloc(LCD_WIDTH, LCD_HEIGHT, LCD_BPP, 1);
+    bcm283x_mbox_fb_setoffset(0, 0);
+    bcm283x_mbox_fb_set_porder(0);
     _hdmi.width = LCD_WIDTH;
     _hdmi.height = LCD_HEIGHT;
     _hdmi.depth = LCD_DEPTH;
     _hdmi.pitch = 0;
     _hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
 
-    armv8_map((unsigned long)_hdmi.fb, (unsigned long)_hdmi.fb, 0x200000, MEM_ATTR_MEMORY);
+    armv8_map((unsigned long)_hdmi.fb, (unsigned long)_hdmi.fb, 0x200000, MEM_ATTR_IO);
+
+    rt_hw_dcache_invalidate_range((unsigned long)_hdmi.fb,LCD_WIDTH * LCD_HEIGHT * 3);
 
-    rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb);
+    //rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb);
     rt_hdmi_fb_device_init(&_hdmi, "lcd");
 
     return 0;

bsp/raspberry-pi/raspi3-64/driver/mbox.c

@@ -47,3 +47,404 @@ int mbox_call(unsigned char ch, int mmu_enable)
     }
     return 0;
 }
+
+int bcm283x_mbox_hardware_get_model(void)
+{
+    mbox[0] = 8*4;                          // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+    
+    mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL;
+    mbox[3] = 4;                            // buffer size
+    mbox[4] = 0;                            // len
+
+    mbox[5] = 0;                            
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    return mbox[5];
+}
+
+int bcm283x_mbox_hardware_get_revison(void)
+{
+    mbox[0] = 8*4;                          // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+    
+    mbox[2] = MBOX_TAG_HARDWARE_GET_REV;   
+    mbox[3] = 4;                            // buffer size
+    mbox[4] = 0;                            // len
+
+    mbox[5] = 0;                    
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    return mbox[5];
+}
+
+int bcm283x_mbox_hardware_get_mac_address(uint8_t * mac)
+{
+    mbox[0] = 8*4;                                 // length of the message
+    mbox[1] = MBOX_REQUEST;                        // this is a request message
+    
+    mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS;   
+    mbox[3] = 6;                                   // buffer size
+    mbox[4] = 0;                                   // len
+
+    mbox[5] = 0;                    
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    char * mac_str = (char *)&mbox[5];
+    mac[0] = mac_str[0];
+    mac[1] = mac_str[1];
+    mac[2] = mac_str[2];
+    mac[3] = mac_str[3];
+    mac[4] = mac_str[4];
+    mac[5] = mac_str[5];
+    return 0;
+}
+
+
+int bcm283x_mbox_hardware_get_serial(rt_uint64_t* sn)
+{
+    mbox[0] = 8*4;                              // length of the message
+    mbox[1] = MBOX_REQUEST;                     // this is a request message
+    
+    mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL;    
+    mbox[3] = 8;                                // buffer size
+    mbox[4] = 0;                                // len
+
+    mbox[5] = 0;                    
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    sn = (rt_uint64_t *)&mbox[5];
+
+    return 0;
+}
+
+int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size)
+{
+    mbox[0] = 8*4;                                  // length of the message
+    mbox[1] = MBOX_REQUEST;                         // this is a request message
+    
+    mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY;   
+    mbox[3] = 8;                                    // buffer size
+    mbox[4] = 0;                                    // len
+
+    mbox[5] = 0;                    
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    *base = mbox[5];
+    *size = mbox[6];
+    
+    return 0;
+
+}
+
+int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size)
+{
+    mbox[0] = 8*4;                               // length of the message
+    mbox[1] = MBOX_REQUEST;                      // this is a request message
+    
+    mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY;
+    mbox[3] = 8;                                 // buffer size
+    mbox[4] = 0;                                 // len
+
+    mbox[5] = 0;                    
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    *base = mbox[5];
+    *size = mbox[6];
+    
+    return 0;
+}
+
+int bcm283x_mbox_clock_get_turbo(void)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; 
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 4;                        // len
+
+    mbox[5] = 0;                        // id
+    mbox[6] = 0;                        // val
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_clock_set_turbo(int level)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_SET_TURBO;  
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = 0;                        // id
+    mbox[6] = level ? 1 : 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_clock_get_state(int id)
+{
+    mbox[0] = 8*4;                       // length of the message
+    mbox[1] = MBOX_REQUEST;              // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_GET_STATE;
+    mbox[3] = 8;                         // buffer size
+    mbox[4] = 4;                         // len
+
+    mbox[5] = id;                        // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm283x_mbox_clock_set_state(int id, int state)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_SET_STATE;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = id;                       // id
+    mbox[6] = state & 0x3;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm283x_mbox_clock_get_rate(int id)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_GET_RATE; 
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 4;                        // len
+
+    mbox[5] = id;                       // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_clock_set_rate(int id, int rate)
+{
+    mbox[0] = 8*4;                      // length of the message
+    mbox[1] = MBOX_REQUEST;             // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_SET_RATE;
+    mbox[3] = 8;                        // buffer size
+    mbox[4] = 8;                        // len
+
+    mbox[5] = id;                       // id
+    mbox[6] = rate;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_clock_get_max_rate(int id)
+{
+    mbox[0] = 8*4;                          // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE;
+    mbox[3] = 8;                            // buffer size
+    mbox[4] = 4;                            // len
+
+    mbox[5] = id;                           // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_clock_get_min_rate(int id)
+{
+    mbox[0] = 8*4;                          // length of the message
+    mbox[1] = MBOX_REQUEST;                 // this is a request message
+    
+    mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; 
+    mbox[3] = 8;                            // buffer size
+    mbox[4] = 4;                            // len
+
+    mbox[5] = id;                           // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_power_get_state(int id)
+{
+    mbox[0] = 8*4;                  // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+    
+    mbox[2] = MBOX_TAG_POWER_GET_STATE;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 4;                    // len
+
+    mbox[5] = id;                   // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm283x_mbox_power_set_state(int id, int state)
+{
+    mbox[0] = 8*4;                  // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+    
+    mbox[2] = MBOX_TAG_POWER_SET_STATE;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 8;                    // len
+
+    mbox[5] = id;                    // id
+    mbox[6] = state & 0x3;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != id)
+    {
+        return -1;
+    }
+
+    return (mbox[6] & 0x3);
+}
+
+int bcm283x_mbox_temp_get(void)
+{
+    mbox[0] = 8*4;                  // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+    
+    mbox[2] = MBOX_TAG_TEMP_GET;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 4;                    // len
+
+    mbox[5] = 0;                    //id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}
+
+int bcm283x_mbox_temp_get_max(void)
+{
+    mbox[0] = 8*4;                  // length of the message
+    mbox[1] = MBOX_REQUEST;         // this is a request message
+    
+    mbox[2] = MBOX_TAG_TEMP_GET_MAX;
+    mbox[3] = 8;                    // buffer size
+    mbox[4] = 4;                    // len
+
+    mbox[5] = 0;                    // id
+    mbox[6] = 0;
+
+    mbox[7] = MBOX_TAG_LAST;
+    mbox_call(8, MMU_DISABLE);
+
+    if(mbox[5] != 0)
+    {
+        return -1;
+    }
+
+    return mbox[6];
+}

bsp/raspberry-pi/raspi3-64/driver/mbox.h

@@ -12,7 +12,7 @@
 #ifndef __MBOX_H__
 #define __MBOX_H__
 
-
+#include <rtthread.h>
 /* a properly aligned buffer */
 extern volatile unsigned int* mbox;
 
@@ -56,7 +56,69 @@ extern volatile unsigned int* mbox;
 #define MMU_ENABLE 1
 #define MMU_DISABLE 0
 
+/*
+ * raspi hardware info
+ */
+enum {
+    MBOX_TAG_HARDWARE_GET_MODEL         = 0x00010001,
+    MBOX_TAG_HARDWARE_GET_REV           = 0x00010002,
+    MBOX_TAG_HARDWARE_GET_MAC_ADDRESS   = 0x00010003,
+    MBOX_TAG_HARDWARE_GET_SERIAL        = 0x00010004,
+    MBOX_TAG_HARDWARE_GET_ARM_MEMORY    = 0x00010005,
+    MBOX_TAG_HARDWARE_GET_VC_MEMORY     = 0x00010006,
+    MBOX_TAG_HARDWARE_GET_CLOCKS        = 0x00010007,
+};
+
+/*
+ * raspi clock
+ */
+enum {
+    MBOX_TAG_CLOCK_GET_TURBO    = 0x00030009,
+    MBOX_TAG_CLOCK_SET_TURBO    = 0x00038009,
+    MBOX_TAG_CLOCK_GET_STATE    = 0x00030001,
+    MBOX_TAG_CLOCK_SET_STATE    = 0x00038001,
+    MBOX_TAG_CLOCK_GET_RATE     = 0x00030002,
+    MBOX_TAG_CLOCK_SET_RATE     = 0x00038002,
+    MBOX_TAG_CLOCK_GET_MAX_RATE = 0x00030004,
+    MBOX_TAG_CLOCK_GET_MIN_RATE = 0x00030007,
+};
+
+/*
+ * raspi power
+ */
+enum {
+    MBOX_TAG_POWER_GET_STATE    = 0x00020001,
+    MBOX_TAG_POWER_SET_STATE    = 0x00028001,
+};
+
+/*
+ * raspi temperature
+ */
+enum {
+    MBOX_TAG_TEMP_GET       = 0x00030006,
+    MBOX_TAG_TEMP_GET_MAX   = 0x0003000A,
+};
+
 #define MBOX_ADDR 0xc00000
 
 int mbox_call(unsigned char ch, int mmu_enable);
+int bcm283x_mbox_hardware_get_model(void);
+int bcm283x_mbox_hardware_get_revison(void);
+int bcm283x_mbox_hardware_get_mac_address(uint8_t * mac);
+int bcm283x_mbox_hardware_get_serial(rt_uint64_t* sn);
+int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size);
+int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size);
+int bcm283x_mbox_clock_get_turbo(void);
+int bcm283x_mbox_clock_set_turbo(int level);
+int bcm283x_mbox_clock_get_state(int id);
+int bcm283x_mbox_clock_set_state(int id, int state);
+int bcm283x_mbox_clock_get_rate(int id);
+int bcm283x_mbox_clock_set_rate(int id, int rate);
+int bcm283x_mbox_clock_get_max_rate(int id);
+int bcm283x_mbox_clock_get_min_rate(int id);
+int bcm283x_mbox_power_get_state(int id);
+int bcm283x_mbox_power_set_state(int id, int state);
+int bcm283x_mbox_temp_get(void);
+int bcm283x_mbox_temp_get_max(void);
+
 #endif

bsp/raspberry-pi/raspi4/.config

@@ -0,0 +1,455 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_CPU_64BIT=y
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
+CONFIG_BCM2711_SOC=y
+# CONFIG_BSP_SUPPORT_FPU is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART0=y
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GIC400=y
+# CONFIG_BSP_USING_GIC500 is not set
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_CORETIMER=y
+# CONFIG_BSP_USING_SYSTIMER is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board Peripheral Drivers
+#
+# CONFIG_BSP_USING_HDMI is not set

bsp/raspberry-pi/raspi4/Kconfig

@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2711_SOC
+    bool
+    select ARCH_ARM_CORTEX_A72
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_CPU_64BIT
+    default y
+
+source "driver/Kconfig"

bsp/raspberry-pi/raspi4/README.md

@@ -0,0 +1,81 @@
+# Raspberry PI 4板级支持包说明
+
+## 1. 简介
+
+树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
+
+外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
+
+这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+
+## 2. 编译说明
+
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
+
+将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
+
+```
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+```
+
+直接进入`bsp\raspberry-pi\raspi4`，输入scons编译即可。
+
+
+## 3. 执行
+
+### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
+
+首先下载镜像
+
+* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
+* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
+* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
+
+![raspi2](../raspi3-32/figures/raspberrypi-console.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+### 3.3 程序下载
+
+当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
+
+```
+enable_uart=1
+arm_64bit=1
+kernel=rtthread.bin
+```
+
+按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
+
+```text
+heap: 0x000c9350 - 0x040c9350
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Apr 16 2020
+ 2006 - 2020 Copyright by rt-thread team
+Hi, this is RT-Thread!!
+msh />
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong

bsp/raspberry-pi/raspi4/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/raspberry-pi/raspi4/SConstruct

@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
+

bsp/raspberry-pi/raspi4/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/raspberry-pi/raspi4/applications/main.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+    return 0;
+}

bsp/raspberry-pi/raspi4/driver/Kconfig

@@ -0,0 +1,97 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+            endif
+            
+        menuconfig BSP_USING_GIC
+            bool "Enable GIC"
+            select RT_USING_GIC
+            default y
+        if BSP_USING_GIC
+            config BSP_USING_GIC400
+                bool "Enable GIC400"
+                default y
+            config BSP_USING_GIC500
+                bool "Enable GIC500"
+                default n
+        endif
+
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_CORETIMER
+            bool "Using core timer"
+            select RT_USING_CORETIMER
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select BSP_USING_SYSTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+    endmenu
+
+    menu "Board Peripheral Drivers"
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            default n
+
+        if BSP_USING_HDMI
+            config BSP_USING_HDMI_DISPLAY
+                bool "HDMI DISPLAY"
+                default n
+        endif
+    endmenu
+endmenu

bsp/raspberry-pi/raspi4/driver/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/raspberry-pi/raspi4/driver/board.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include "cp15.h"
+#include "mmu.h"
+
+static rt_uint64_t timerStep;
+
+int rt_hw_get_gtimer_frq(void);
+void rt_hw_set_gtimer_val(rt_uint64_t value);
+int rt_hw_get_gtimer_val(void);
+int rt_hw_get_cntpct_val(void);
+void rt_hw_gtimer_enable(void);
+
+void core0_timer_enable_interrupt_controller(void)
+{
+    CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
+}
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    rt_hw_set_gtimer_val(timerStep);
+    rt_tick_increase();
+}
+
+void rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(TIMER_IRQ);
+    __ISB();
+    timerStep = rt_hw_get_gtimer_frq();
+    __DSB();
+    timerStep /= RT_TICK_PER_SECOND;
+    
+    rt_hw_gtimer_enable();
+    rt_hw_set_gtimer_val(timerStep);
+    core0_timer_enable_interrupt_controller();
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+/**
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  after interrupt disabled.
+ */
+void rt_hw_board_init(void)
+{
+    mmu_init();
+    armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
+    armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
+    armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
+    mmu_enable();
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
+    rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
+
+    /* initialize uart */
+    rt_hw_uart_init();      // driver/drv_uart.c
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+        /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}

bsp/raspberry-pi/raspi4/driver/board.h

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+#include "iomap.h"
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif

bsp/raspberry-pi/raspi4/driver/drv_gpio.c

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    uint32_t fselnum = pin / 10;
+    uint32_t fselrest = pin % 10;
+
+    uint32_t gpfsel = 0;
+    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
+    gpfsel |= (uint32_t)(mode << (fselrest * 3));
+
+    switch (fselnum)
+    {
+    case 0:
+        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        break;
+    case 1:
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        break;
+    case 2:
+        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        break;
+    case 3:
+        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        break;
+    case 4:
+        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        break;
+    case 5:
+        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        break;
+    default:
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    uint32_t num = pin / 32;
+
+    if(num == 0)
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
+        }
+    }
+    else
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        
+    }
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    return 0;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);

bsp/raspberry-pi/raspi4/driver/drv_gpio.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "interrupt.h"
+
+#define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
+#define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
+#define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
+#define GPIO_REG_GPFSEL3(BASE)             HWREG32(BASE + 0x0C)
+#define GPIO_REG_GPFSEL4(BASE)             HWREG32(BASE + 0x10)
+#define GPIO_REG_GPFSEL5(BASE)             HWREG32(BASE + 0x14)
+#define GPIO_REG_REV0(BASE)                HWREG32(BASE + 0x18)
+#define GPIO_REG_GPSET0(BASE)              HWREG32(BASE + 0x1C)
+#define GPIO_REG_GPSET1(BASE)              HWREG32(BASE + 0x20)
+#define GPIO_REG_REV1(BASE)                HWREG32(BASE + 0x24)
+#define GPIO_REG_GPCLR0(BASE)              HWREG32(BASE + 0x28)
+#define GPIO_REG_GPCLR1(BASE)              HWREG32(BASE + 0x2C)
+#define GPIO_REG_REV2(BASE)                HWREG32(BASE + 0x30)
+#define GPIO_REG_GPLEV0(BASE)              HWREG32(BASE + 0x34)
+#define GPIO_REG_GPLEV1(BASE)              HWREG32(BASE + 0x38)
+#define GPIO_REG_REV3(BASE)                HWREG32(BASE + 0x3C)
+#define GPIO_REG_GPEDS0(BASE)              HWREG32(BASE + 0x40)
+#define GPIO_REG_GPEDS1(BASE)              HWREG32(BASE + 0x44)
+#define GPIO_REG_REV4(BASE)                HWREG32(BASE + 0x48)
+#define GPIO_REG_GPREN0(BASE)              HWREG32(BASE + 0x4C)
+#define GPIO_REG_GPREN1(BASE)              HWREG32(BASE + 0x50)
+#define GPIO_REG_REV5(BASE)                HWREG32(BASE + 0x54)
+#define GPIO_REG_GPFEN0(BASE)              HWREG32(BASE + 0x58)
+#define GPIO_REG_GPFEN1(BASE)              HWREG32(BASE + 0x5C)
+#define GPIO_REG_REV6(BASE)                HWREG32(BASE + 0x60)
+#define GPIO_REG_GPHEN0(BASE)              HWREG32(BASE + 0x64)
+#define GPIO_REG_GPHEN1(BASE)              HWREG32(BASE + 0x68)
+#define GPIO_REG_REV7(BASE)                HWREG32(BASE + 0x6C)
+#define GPIO_REG_GPLEN0(BASE)              HWREG32(BASE + 0x70)
+#define GPIO_REG_GPLEN1(BASE)              HWREG32(BASE + 0x74)
+#define GPIO_REG_REV8(BASE)                HWREG32(BASE + 0x78)
+#define GPIO_REG_GPAREN0(BASE)             HWREG32(BASE + 0x7C)
+#define GPIO_REG_GPAREN1(BASE)             HWREG32(BASE + 0x80)
+#define GPIO_REG_REV11(BASE)               HWREG32(BASE + 0x84)
+#define GPIO_REG_GPAFEN0(BASE)             HWREG32(BASE + 0x88)
+#define GPIO_REG_GPAFEN1(BASE)             HWREG32(BASE + 0x8C)
+#define GPIO_REG_REV10(BASE)               HWREG32(BASE + 0x90)
+#define GPIO_REG_GPPUD(BASE)               HWREG32(BASE + 0x94)
+#define GPIO_REG_GPPUDCLK0(BASE)           HWREG32(BASE + 0x98)
+#define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
+#define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
+#define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
+
+typedef enum {
+    INPUT = 0b000,
+    OUTPUT = 0b001,
+    ALT0 = 0b100,
+    ALT1 = 0b101,
+    ALT2 = 0b110,
+    ALT3 = 0b111,
+    ALT4 = 0b011,
+    ALT5 = 0b010
+} GPIO_FUNC;
+
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */

bsp/raspberry-pi/raspi4/driver/drv_uart.c

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+
+struct hw_uart_device
+{
+    rt_ubase_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
+    uint32_t ibrd = bauddiv / 1000;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+    if(uart->hw_base == PL011_BASE)
+    {
+        uint32_t gpfsel = 0;
+
+        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
+        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+        PL011_REG_IBRD(uart->hw_base) = ibrd;
+        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
+        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
+        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
+    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+    {
+        ch = PL011_REG_DR(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+}
+
+
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    PL011_BASE,
+    IRQ_PL011,
+};
+
+static struct rt_serial_device _serial0;
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
+
+    return 0;
+}

bsp/raspberry-pi/raspi4/driver/drv_uart.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+// register's bit
+#define PL011_FR_RI          (1 << 8)
+#define PL011_FR_TXFE        (1 << 7)
+#define PL011_FR_RXFF        (1 << 6)
+#define PL011_FR_TXFF        (1 << 5)
+#define PL011_FR_RXFE        (1 << 4)
+#define PL011_FR_BUSY        (1 << 3)
+#define PL011_FR_DCD         (1 << 2)
+#define PL011_FR_DSR         (1 << 1)
+#define PL011_FR_CTS         (1 << 0)
+
+#define PL011_LCRH_SPS       (1 << 7)
+#define PL011_LCRH_WLEN_8    (3 << 5)
+#define PL011_LCRH_WLEN_7    (2 << 5)
+#define PL011_LCRH_WLEN_6    (1 << 5)
+#define PL011_LCRH_WLEN_5    (0 << 5)
+#define PL011_LCRH_FEN       (1 << 4)
+#define PL011_LCRH_STP2      (1 << 3)
+#define PL011_LCRH_EPS       (1 << 2)
+#define PL011_LCRH_PEN       (1 << 1)
+#define PL011_LCRH_BRK       (1 << 0)
+
+#define PL011_CR_CTSEN       (1 << 15)
+#define PL011_CR_RTSEN       (1 << 14)
+#define PL011_CR_RTS         (1 << 11)
+#define PL011_CR_DTR         (1 << 10)
+#define PL011_CR_RXE         (1 << 9)
+#define PL011_CR_TXE         (1 << 8)
+#define PL011_CR_LBE         (1 << 7)
+#define PL011_CR_SIRLP       (1 << 2)
+#define PL011_CR_SIREN       (1 << 1)
+#define PL011_CR_UARTEN      (1 << 0)
+
+#define PL011_IMSC_TXIM      (1 << 5)
+#define PL011_IMSC_RXIM      (1 << 4)
+
+#define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
+#define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
+#define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
+#define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
+#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
+#define PL011_INTERRUPT_TRANSMIT        (1 << 5)
+#define PL011_INTERRUPT_RECEIVE         (1 << 4)
+#define PL011_INTERRUPT_nUARTCTS        (1 << 1)
+
+#define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
+#define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
+#define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
+#define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
+#define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
+#define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
+#define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
+#define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
+#define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
+#define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
+#define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
+#define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
+#define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
+#define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
+#define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
+#define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
+#define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
+#define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
+#define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
+#define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
+#define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */

bsp/raspberry-pi/raspi4/driver/iomap.h

@@ -0,0 +1,29 @@
+#ifndef __RASPI4_H__
+#define __RASPI4_H__
+
+//gpio
+#define GPIO_BASE (0xFE000000 + 0x00200000)
+
+//uart
+#define UART0_BASE                  (0xFE000000 + 0x00201000)
+#define PL011_BASE                  UART0_BASE
+#define IRQ_PL011                   (121 + 32)
+#define UART_REFERENCE_CLOCK        (48000000)
+
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
+#define TIMER_IRQ               30
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
+//gic max
+#define ARM_GIC_NR_IRQS             (512)
+#define INTC_BASE                   (0xff800000)
+#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
+#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
+#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
+
+#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
+#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
+
+#endif

bsp/raspberry-pi/raspi4/link.lds

@@ -0,0 +1,153 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x80000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+        
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = (__bss_end - __bss_start)>>3;

bsp/raspberry-pi/raspi4/rtconfig.h

@@ -0,0 +1,179 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_CPU_64BIT
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+#define BCM2711_SOC
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART0
+#define BSP_USING_GIC
+#define BSP_USING_GIC400
+#define BSP_USING_PIN
+#define BSP_USING_CORETIMER
+
+/* Board Peripheral Drivers */
+
+
+#endif

bsp/raspberry-pi/raspi4/rtconfig.py

@@ -0,0 +1,51 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a72'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    # PREFIX = 'arm-none-eabi-'
+    PREFIX = 'aarch64-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/stm32/README.md

@@ -1,3 +1,4 @@
+
 # STM32 BSP 说明
 
 STM32 系列 BSP 目前支持情况如下表所示：
@@ -43,6 +44,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32h743-st-nucleo](stm32h743-st-nucleo) | ST 官方 STM32H743-nucleo 开发板 |
 | [stm32h747-st-discovery](stm32h747-st-discovery) | ST 官方 STM32H747I-discovery 开发板 |
 | **L0 系列** |  |
+| [stm32l010-st-nucleo](stm32l010-st-nucleo) | ST 官方 STM32L010-nucleo 开发板 |
 | [stm32l053-st-nucleo](stm32l053-st-nucleo) | ST 官方 STM32L053-nucleo 开发板 |
 | **L4 系列** |  |
 | [stm32l4r9-st-eval](stm32l4r9-st-eval) | ST 官方 STM32L4R9I-EVAL 开发板 |

bsp/stm32/stm32l010-st-nucleo/.config

@@ -0,0 +1,364 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M0=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=1024
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_LIBC_USING_TIME=y
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_QSDK is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32L0=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32L010RB=y
+
+#
+# Onboard Peripheral Drivers
+#
+# CONFIG_BSP_USING_USB_TO_USART is not set
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART2=y
+# CONFIG_BSP_UART2_RX_USING_DMA is not set
+# CONFIG_BSP_USING_UDID is not set
+
+#
+# Board extended module Drivers
+#

bsp/stm32/stm32l010-st-nucleo/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/stm32/stm32l010-st-nucleo/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/stm32/stm32l010-st-nucleo/README.md

@@ -0,0 +1,120 @@
+
+# NUCLEO-L010RB 开发板 BSP 说明
+
+## 简介
+
+本文档为ST官方 NUCLEO-L010RB 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+NUCLEO-L010RB 开发板是 ST 官方推出的一款基于 ARM Cortex-M0+ 内核的开发板，绿色的 Nucleo 标志显示了这款芯片是低功耗系列，板载 ST-LINK/V2-1 调试器/编程器，该开发板具有丰富的扩展接口，且与Arduino™ nano 接口兼容，可以方便验证 STM32L010RB 芯片的性能。
+
+开发板外观如下图所示：
+
+![board](figures/board.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32L010RB
+	- 主频 32MHz
+	- 128KB FLASH
+	- 20KB RAM
+	- 512 byte EEPROM
+- 常用外设
+  - LED：3个，USB communication(LD1 双色)，power LED(LD3 红色)，user LED(LD2 黄色)
+  - 按键：1个，B1（兼具唤醒功能，PC13），B2（RESET）
+- 常用接口：USB 支持 3 种不同接口：虚拟 COM 端口、大容量存储和调试端口；arduino 接口等
+- 调试接口：标准 SWD
+
+开发板更多详细信息请参考[STMicroelectronics NUCLEO-L010RB](https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-nucleo-boards/nucleo-l010rb.html#overview)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| 板载 ST-LINK 转串口        |     支持     |                             |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     | PA0, PA1... PC15 ---> PIN: 0, 1...47 |
+| UART              |     支持     | UART2                             |
+| SPI               |   暂不支持   |                            |
+| I2C               |   暂不支持   |                     |
+| RTC               |   暂不支持   |                        |
+| PWM               |   暂不支持   |                       |
+| USB Device        |   暂不支持   |                      |
+| IWG               |   暂不支持   |                         |
+| **扩展模块**      | **支持情况** | **备注**                                                                  |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 microUSB 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LED1 和 LED3 常亮、黄色 LED2 会周期性闪烁。
+
+USB 虚拟 COM 端口默认连接串口 2，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Apr  9 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh >
+
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 2 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 开机时如果不能打印 RT-Thread 版本信息，请将BSP中串口 GPIO 速率调低
+- 开机时如果不能打印 RT-Thread 版本信息，请重新选择 PC 端串口调试软件的串口号
+
+## 联系人信息
+
+- 维护人: [xph](https://github.com/xupenghu)
+- 邮箱：<xupenghu@outlook.com>

bsp/stm32/stm32l010-st-nucleo/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/stm32/stm32l010-st-nucleo/SConstruct

@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32L0xx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/stm32/stm32l010-st-nucleo/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/stm32/stm32l010-st-nucleo/applications/main.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   change to new framework
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED pin: PA5 */
+#define LED0_PIN     GET_PIN(A, 5)
+
+int main(void)
+{
+    int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/CubeMX_Config.ioc

@@ -0,0 +1,114 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32L0
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART2
+Mcu.IPNb=4
+Mcu.Name=STM32L010RBTx
+Mcu.Package=LQFP64
+Mcu.Pin0=PC14-OSC32_IN
+Mcu.Pin1=PC15-OSC32_OUT
+Mcu.Pin2=PH0-OSC_IN
+Mcu.Pin3=PH1-OSC_OUT
+Mcu.Pin4=PA2
+Mcu.Pin5=PA3
+Mcu.Pin6=VP_SYS_VS_Systick
+Mcu.PinsNb=7
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32L010RBTx
+MxCube.Version=5.3.0
+MxDb.Version=DB.5.0.30
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+PA2.Mode=Asynchronous
+PA2.Signal=USART2_TX
+PA3.Mode=Asynchronous
+PA3.Signal=USART2_RX
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PCC.Checker=true
+PCC.Line=STM32L0x0 Value Line
+PCC.MCU=STM32L010RBTx
+PCC.PartNumber=STM32L010RBTx
+PCC.Seq0=0
+PCC.Series=STM32L0
+PCC.Temperature=25
+PCC.Vdd=3.0
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+PH0-OSC_IN.Signal=RCC_OSC_IN
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32L010RBTx
+ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.11.2
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=STM32L010RB_Test.ioc
+ProjectManager.ProjectName=STM32L010RB_Test
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_Init-USART2-false-HAL-true
+RCC.AHBFreq_Value=32000000
+RCC.APB1Freq_Value=32000000
+RCC.APB1TimFreq_Value=32000000
+RCC.APB2Freq_Value=32000000
+RCC.APB2TimFreq_Value=32000000
+RCC.FCLKCortexFreq_Value=32000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=32000000
+RCC.HSE_VALUE=8000000
+RCC.HSI16_VALUE=16000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=32000000
+RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLMUL,PLLSourceVirtual,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,WatchDogFreq_Value
+RCC.LPTIMFreq_Value=32000000
+RCC.LPUARTFreq_Value=32000000
+RCC.LSI_VALUE=37000
+RCC.MCOPinFreq_Value=32000000
+RCC.MSI_VALUE=2097000
+RCC.PLLCLKFreq_Value=32000000
+RCC.PLLMUL=RCC_PLLMUL_8
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWRFreq_Value=32000000
+RCC.RTCFreq_Value=37000
+RCC.RTCHSEDivFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=32000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TIMFreq_Value=32000000
+RCC.TimerFreq_Value=32000000
+RCC.USART2Freq_Value=32000000
+RCC.VCOInputFreq_Value=8000000
+RCC.VCOOutputFreq_Value=64000000
+RCC.WatchDogFreq_Value=37000
+USART2.IPParameters=VirtualMode-Asynchronous
+USART2.VirtualMode-Asynchronous=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/main.h

@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_hal_conf.h

@@ -0,0 +1,302 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l0xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CONF_H
+#define __STM32L0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+
+#define HAL_MODULE_ENABLED  
+  /*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_FIREWALL_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_EXTI_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2097000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator for USB (HSI48) value.
+  */
+#if !defined  (HSI48_VALUE) 
+#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/   
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT  ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              0U              
+#define  PREREAD_ENABLE               1U
+#define  BUFFER_CACHE_DISABLE         0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32l0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+   
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l0xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+   
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l0xx_hal_rtc.h"
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Inc/stm32l0xx_it.h

@@ -0,0 +1,65 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_IT_H
+#define __STM32L0xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/main.c

@@ -0,0 +1,238 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart2;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART2_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+  
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART2_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
+  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
+  PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief USART2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART2_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART2_Init 0 */
+
+  /* USER CODE END USART2_Init 0 */
+
+  /* USER CODE BEGIN USART2_Init 1 */
+
+  /* USER CODE END USART2_Init 1 */
+  huart2.Instance = USART2;
+  huart2.Init.BaudRate = 115200;
+  huart2.Init.WordLength = UART_WORDLENGTH_8B;
+  huart2.Init.StopBits = UART_STOPBITS_1;
+  huart2.Init.Parity = UART_PARITY_NONE;
+  huart2.Init.Mode = UART_MODE_TX_RX;
+  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART2_Init 2 */
+
+  /* USER CODE END USART2_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_hal_msp.c

@@ -0,0 +1,149 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32l0xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspInit 0 */
+
+  /* USER CODE END USART2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART2 GPIO Configuration    
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF4_USART2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART2_MspInit 1 */
+
+  /* USER CODE END USART2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+  /* USER CODE END USART2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART2_CLK_DISABLE();
+  
+    /**USART2 GPIO Configuration    
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3);
+
+  /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+  /* USER CODE END USART2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/stm32l0xx_it.c

@@ -0,0 +1,145 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32l0xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M0+ Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable Interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVC_IRQn 0 */
+
+  /* USER CODE END SVC_IRQn 0 */
+  /* USER CODE BEGIN SVC_IRQn 1 */
+
+  /* USER CODE END SVC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32L0xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32l0xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/CubeMX_Config/Src/system_stm32l0xx.c

@@ -0,0 +1,279 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l0xx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Defines
+  * @{
+  */
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
+  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+/*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100U;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+  /*!< Disable all interrupts */
+  RCC->CIER = 0x00000000U;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+  *             value as defined by the MSI range.
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00U:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+    case 0x04U:  /* HSI used as system clock */
+      if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+      {
+        SystemCoreClock = HSI_VALUE / 4U;
+      }
+      else
+      {
+        SystemCoreClock = HSI_VALUE;
+      }
+      break;
+    case 0x08U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    default:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
+      plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
+
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+        {
+          SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
+        }
+        else
+        {
+          SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+        }
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32l010-st-nucleo/board/Kconfig

@@ -0,0 +1,48 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32L010RB
+    bool
+    select SOC_SERIES_STM32L0
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_USB_TO_USART
+        bool "Enable USB TO USART (uart2)"
+        select BSP_USING_UART2
+        default y
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default y
+				
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                default n
+        endif
+    source "../libraries/HAL_Drivers/Kconfig"
+    
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/stm32/stm32l010-st-nucleo/board/SConscript

@@ -0,0 +1,34 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+CubeMX_Config/Src/stm32l0xx_hal_msp.c
+''')
+
+path =  [cwd]
+path += [cwd + '/CubeMX_Config/Inc']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/gcc/startup_stm32l053xx.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/arm/startup_stm32l053xx.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/STM32L0xx_HAL/CMSIS/Device/ST/STM32L0xx/Source/Templates/iar/startup_stm32l053xx.s']
+
+# STM32L052xx || STM32L053xx || STM32L062xx
+# STM32L063xx || STM32L072xx || STM32L073xx
+# STM32L082xx ||  STM32L083xx
+# You can select chips from the list above	
+CPPDEFINES = ['STM32L053xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/stm32/stm32l010-st-nucleo/board/board.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#include "board.h"
+
+void SystemClock_Config(void)
+{
+
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInit;
+
+    /**Configure the main internal regulator output voltage 
+    */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /**Initializes the CPU, AHB and APB busses clocks 
+    */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = 16;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    _Error_Handler(__FILE__, __LINE__);
+  }
+
+    /**Initializes the CPU, AHB and APB busses clocks 
+    */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    _Error_Handler(__FILE__, __LINE__);
+  }
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
+  PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    _Error_Handler(__FILE__, __LINE__);
+  }
+
+    /**Configure the Systick interrupt time 
+    */
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+
+    /**Configure the Systick 
+    */
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
+
+  /* SysTick_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
+}

bsp/stm32/stm32l010-st-nucleo/board/board.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <stm32l0xx.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (128 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
+/* Internal SRAM memory size[Kbytes] <8-64>, Default: 36 */
+#define STM32_SRAM_SIZE      20
+#define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      ((void *)&__bss_end)
+#endif
+
+#define HEAP_END        STM32_SRAM_END
+
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */

bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.icf

@@ -0,0 +1,29 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20004FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.lds

@@ -0,0 +1,157 @@
+/*
+ * linker script for STM32L4XX with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  20k  /* 20KB sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } > RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } > RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/stm32/stm32l010-st-nucleo/board/linker_scripts/link.sct

@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00005000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+