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+/*
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+ * File : uart.c
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+ * This file is part of RT-Thread RTOS
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+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
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+ *
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+ * The license and distribution terms for this file may be
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+ * found in the file LICENSE in this distribution or at
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+ * http://openlab.rt-thread.com/license/LICENSE
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2013-05-27 Grissiom port to RM48x50
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+ */
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+
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+/* welcome, if you open this file, you may want to see uart driver code.
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+ * However, TI call it Serial Communication Interface(SCI) and all the low
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+ * level API is prefixed by "sci". To avoid messive renaming, I want to keep
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+ * with TI and call all the things SCI. You could safely substitude the word
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+ * "sci" with "uart". Enjoy. */
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+
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+#include <rthw.h>
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+#include <rtthread.h>
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+#include <rtdevice.h>
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+
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+#include <reg_sci.h>
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+
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+/* bring from sci.h */
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+enum sciIntFlags
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+{
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+ SCI_FE_INT = 0x04000000U, /* framing error */
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+ SCI_OE_INT = 0x02000000U, /* overrun error */
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+ SCI_PE_INT = 0x01000000U, /* parity error */
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+ SCI_RX_INT = 0x00000200U, /* receive buffer ready */
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+ SCI_TX_INT = 0x00000100U, /* transmit buffer ready */
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+ SCI_WAKE_INT = 0x00000002U, /* wakeup */
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+ SCI_BREAK_INT = 0x00000001U /* break detect */
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+};
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+
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+/* LIN1 High level interrupt. Change this if you set a different channel in
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+ * HALCoGen. */
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+#define SCI_INT_VEC 13
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+
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+#define VCLK_HZ 100000000L
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+
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+static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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+{
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+ /** - global control 1 */
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+ rt_uint32_t gcr1 = (1U << 25U) /* enable transmit */
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+ | (1U << 24U) /* enable receive */
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+ | (1U << 5U) /* internal clock (device has no clock pin) */
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+ | (1U << 1U); /* asynchronous timing mode */
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+ if (cfg->stop_bits == STOP_BITS_2)
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+ gcr1 |= (1U << 4U); /* number of stop bits */
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+ else if (cfg->stop_bits != STOP_BITS_1)
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+ return -RT_ERROR;
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+
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+ if (cfg->parity == PARITY_EVEN)
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+ {
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+ gcr1 |= (1U << 3U) | (1U << 2U);
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+ }
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+ else if (cfg->parity == PARITY_ODD)
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+ {
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+ gcr1 |= (0U << 3U) | (1U << 2U);
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+ }
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+
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+ /** - bring SCI out of reset */
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+ scilinREG->GCR0 = 1U;
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+
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+ /** - Disable all interrupts */
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+ scilinREG->CLRINT = 0xFFFFFFFFU;
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+ scilinREG->CLRINTLVL = 0xFFFFFFFFU;
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+
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+ scilinREG->GCR1 = gcr1;
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+
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+ /** - set baudrate */
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+ scilinREG->BRS = VCLK_HZ/16/cfg->baud_rate - 1; /* baudrate */
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+
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+ /** - transmission length */
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+ scilinREG->FORMAT = cfg->data_bits - 1; /* length */
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+
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+ /** - set SCI pins functional mode */
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+ scilinREG->FUN = (1U << 2U) /* tx pin */
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+ | (1U << 1U) /* rx pin */
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+ | (0U); /* clk pin */
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+
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+ /** - set SCI pins default output value */
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+ scilinREG->DOUT = (0U << 2U) /* tx pin */
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+ | (0U << 1U) /* rx pin */
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+ | (0U); /* clk pin */
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+
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+ /** - set SCI pins output direction */
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+ scilinREG->DIR = (0U << 2U) /* tx pin */
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+ | (0U << 1U) /* rx pin */
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+ | (0U); /* clk pin */
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+
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+ /** - set SCI pins open drain enable */
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+ scilinREG->ODR = (0U << 2U) /* tx pin */
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+ | (0U << 1U) /* rx pin */
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+ | (0U); /* clk pin */
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+
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+ /** - set SCI pins pullup/pulldown enable */
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+ scilinREG->PD = (0U << 2U) /* tx pin */
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+ | (0U << 1U) /* rx pin */
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+ | (0U); /* clk pin */
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+
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+ /** - set SCI pins pullup/pulldown select */
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+ scilinREG->PSL = (1U << 2U) /* tx pin */
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+ | (1U << 1U) /* rx pin */
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+ | (1U); /* clk pin */
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+
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+ /** - set interrupt level */
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+ scilinREG->SETINTLVL = (0U << 26U) /* Framing error */
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+ | (0U << 25U) /* Overrun error */
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+ | (0U << 24U) /* Parity error */
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+ | (0U << 9U) /* Receive */
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+ | (0U << 8U) /* Transmit */
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+ | (0U << 1U) /* Wakeup */
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+ | (0U); /* Break detect */
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+
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+ /** - set interrupt enable */
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+ scilinREG->SETINT = (0U << 26U) /* Framing error */
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+ | (0U << 25U) /* Overrun error */
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+ | (0U << 24U) /* Parity error */
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+ | (1U << 9U) /* Receive */
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+ | (0U << 1U) /* Wakeup */
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+ | (0U); /* Break detect */
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+
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+ /** - Finaly start SCILIN */
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+ scilinREG->GCR1 |= (1U << 7U);
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
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+{
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+ sciBASE_t *sci = (sciBASE_t*)serial->parent.user_data;
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+
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+ switch (cmd)
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+ {
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+ case RT_DEVICE_CTRL_CLR_INT:
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+ /* disable rx irq */
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+ sci->CLRINT = SCI_RX_INT;
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+ break;
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+ case RT_DEVICE_CTRL_SET_INT:
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+ /* enable rx irq */
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+ sci->SETINT = SCI_RX_INT;
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+ break;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static int _putc(struct rt_serial_device *serial, char c)
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+{
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+ sciBASE_t *sci = (sciBASE_t*)serial->parent.user_data;
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+ while ((sci->FLR & SCI_TX_INT) == 0U)
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+ ;
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+ sci->TD = c;
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+ return 1;
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+}
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+
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+static int _getc(struct rt_serial_device *serial)
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+{
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+ sciBASE_t *sci = (sciBASE_t*)serial->parent.user_data;
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+ if (sci->FLR & (1<<9))
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+ return (sci->RD & 0x000000FFU);
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+ else
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+ return -1;
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+}
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+
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+static const struct rt_uart_ops _sci_ops =
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+{
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+ _configure,
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+ _control,
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+ _putc,
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+ _getc,
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+};
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+
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+static struct rt_serial_device _sci2_serial;
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+static struct serial_ringbuffer _sci2_int_rx;
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+
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+void rt_hw_uart_init(void)
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+{
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+ struct serial_configure config;
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+
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+ /* fake configuration */
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+ config.baud_rate = BAUD_RATE_115200;
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+ config.bit_order = BIT_ORDER_LSB;
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+ config.data_bits = DATA_BITS_8;
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+ config.parity = PARITY_NONE;
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+ config.stop_bits = STOP_BITS_1;
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+ config.invert = NRZ_NORMAL;
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+
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+ _sci2_serial.ops = &_sci_ops;
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+ _sci2_serial.int_rx = &_sci2_int_rx;
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+ _sci2_serial.config = config;
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+
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+ rt_hw_serial_register(&_sci2_serial, "sci2",
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+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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+ (void*)scilinREG);
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+
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+ rt_hw_interrupt_install(SCI_INT_VEC, rt_hw_serial_isr, &_sci2_serial, "sci2");
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+ rt_hw_interrupt_umask(SCI_INT_VEC);
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+}
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