[libcpu/risc-v] remove direct use of zifencei ISA

libcpu/risc-v/t-head/c906/cpuport.h

@@ -12,6 +12,7 @@
 #define CPUPORT_H__
 
 #include <rtconfig.h>
+#include <opcode.h>
 
 /* bytes of register width  */
 #ifdef ARCH_CPU_64BIT
@@ -48,7 +49,7 @@ rt_inline void rt_hw_dmb()
 
 rt_inline void rt_hw_isb()
 {
-    asm volatile("fence.i":::"memory");
+    asm volatile(OPC_FENCE_I:::"memory");
 }
 
 int rt_hw_cpu_id(void);

libcpu/risc-v/t-head/c906/opcode.h

@@ -76,4 +76,10 @@
 #define OPC_ICACHE_IVA(rs1)     __OPC_INSN_FORMAT_CACHE(0x1, x16, rs1)
 #endif /* _TOOLCHAIN_NOT_SUPP_THEAD_ISA_ */
 
+#ifdef _TOOLCHAIN_SUPP_ZIFENCEI_ISA_
+#define OPC_FENCE_I             "fence.i"
+#else /* !_TOOLCHAIN_SUPP_ZIFENCEI_ISA_ */
+#define OPC_FENCE_I             ".long 0x0000100F"
+#endif /* _TOOLCHAIN_SUPP_ZIFENCEI_ISA_ */
+
 #endif /* __OPCODE_H__ */

libcpu/risc-v/virt64/cpuport.h

@@ -62,7 +62,7 @@ rt_inline void rt_hw_dmb()
 
 rt_inline void rt_hw_isb()
 {
-    asm volatile("fence.i":::"memory");
+    asm volatile(".long 0x0000100F":::"memory");
 }
 
 #endif