[bsp] fix mismatched function types in rt_pin_ops for all drv_gpio.c (#7457)

bsp/allwinner/libraries/drivers/drv_pin.c

@@ -2,7 +2,7 @@
 #include <rtdevice.h>
 #include <hal_gpio.h>
 
-static void hal_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void hal_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     switch (mode)
     {
@@ -27,20 +27,20 @@ static void hal_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode
     }
 }
 
-static void hal_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void hal_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     hal_gpio_set_data(pin,value);
 }
 
-static int hal_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t hal_pin_read(struct rt_device *device, rt_base_t pin)
 {
     gpio_data_t value;
     hal_gpio_get_data(pin,&value);
-    return (int)value;
+    return (rt_int8_t)value;
 }
 
-static rt_err_t hal_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                       rt_uint32_t mode, void (*hdr)(void *args),
+static rt_err_t hal_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                       rt_uint8_t mode, void (*hdr)(void *args),
                                        void *args)
 {
     rt_base_t level = 0;
@@ -68,7 +68,7 @@ static rt_err_t hal_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t hal_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t hal_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level = 0;
     uint32_t irq;
@@ -92,7 +92,7 @@ static rt_err_t hal_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-static rt_err_t hal_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t hal_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     uint32_t irq;
     int ret;

bsp/apollo2/board/gpio.c

@@ -18,7 +18,7 @@
 #define APLLO2_PIN_NUMBERS    64 //[34, 64]
 struct rt_pin_irq_hdr am_pin_irq_hdr_tab[64];
 
-void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     if (mode == PIN_MODE_OUTPUT)
     {
@@ -47,7 +47,7 @@ void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void am_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     if (value == PIN_LOW)
     {
@@ -59,9 +59,9 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-int am_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t am_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (am_hal_gpio_pin_config_read(pin) == AM_HAL_GPIO_OUTPUT)
     {
@@ -89,8 +89,8 @@ int am_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-rt_err_t am_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t am_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -121,7 +121,7 @@ rt_err_t am_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t am_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t am_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -143,7 +143,7 @@ rt_err_t am_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-rt_err_t am_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t am_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;

bsp/beaglebone/drivers/gpio.c

@@ -137,7 +137,7 @@ static const rt_isr_handler_t GPIO_ISRx[] =
     am33xx_gpio3_isr,
 };
 
-static void am33xx_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void am33xx_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     RT_ASSERT(pin >= 0 && pin < 128);
     RT_ASSERT(mode != PIN_MODE_INPUT_PULLUP); /* Mode not supported */
@@ -154,7 +154,7 @@ static void am33xx_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t m
     }
 }
 
-static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     RT_ASSERT(pin >= 0 && pin < 128);
     rt_base_t gpiox     = pin >> 5;
@@ -170,7 +170,7 @@ static void am33xx_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t
     }
 }
 
-static int am33xx_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t am33xx_pin_read(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT(pin >= 0 && pin < 128);
     rt_base_t gpiox     = pin >> 5;
@@ -179,8 +179,8 @@ static int am33xx_pin_read(struct rt_device *device, rt_base_t pin)
     return reg(GPIO_BASE[gpiox] + GPIO_DATAIN) & (1 << pinNumber) ? 1 : 0;
 }
 
-static rt_err_t am33xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                      rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t am33xx_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                      rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     RT_ASSERT(pin >= 0 && pin < 128);
     rt_base_t gpiox     = pin >> 5;
@@ -273,7 +273,7 @@ static rt_err_t am33xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return 0;
 }
 
-static rt_err_t am33xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t am33xx_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT(pin >= 0 && pin < 128);
     rt_base_t gpiox     = pin >> 5;
@@ -290,7 +290,7 @@ static rt_err_t am33xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return 0;
 }
 
-static rt_err_t am33xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t am33xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     RT_ASSERT(pin >= 0 && pin < 128);
     rt_base_t gpiox     = pin >> 5;

bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c

@@ -40,7 +40,7 @@ static void gpio_isr(int irq, void *arg)
 
 }
 
-static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     if(value)
         bflb_gpio_set(gpio, pin);
@@ -48,12 +48,12 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
         bflb_gpio_reset(gpio, pin);
 }
 
-static int _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
 {
     return bflb_gpio_read(gpio, pin);
 }
 
-static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     rt_uint32_t cfgset = 0;
 
@@ -88,8 +88,8 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     bflb_gpio_init(gpio, pin, cfgset);
 }
 
-static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                rt_uint8_t irq_mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
 
@@ -119,7 +119,7 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
 
@@ -143,7 +143,7 @@ static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                rt_uint32_t enabled)
+                                rt_uint8_t enabled)
 {
     rt_base_t level;
     rt_uint8_t trig_mode = 0;

bsp/essemi/es32f0654/drivers/drv_gpio.c

@@ -235,7 +235,7 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
     index = get_pin(pin);
@@ -246,9 +246,9 @@ void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     ald_gpio_write_pin(index->gpio, index->pin, value);
 }
 
-int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t es32f0_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
     value = PIN_LOW;
     index = get_pin(pin);
@@ -260,7 +260,7 @@ int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     gpio_init_t gpio_initstruct;
@@ -328,8 +328,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
     return &pin_irq_map[map_index];
 };
 
-rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                               rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                               rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -373,7 +373,7 @@ rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -403,7 +403,7 @@ rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                               rt_uint32_t enabled)
+                               rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/essemi/es32f369x/drivers/drv_gpio.c

@@ -236,7 +236,7 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
     index = get_pin(pin);
@@ -247,9 +247,9 @@ void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     ald_gpio_write_pin(index->gpio, index->pin, value);
 }
 
-int es32f3_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t es32f3_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
     value = PIN_LOW;
     index = get_pin(pin);
@@ -261,7 +261,7 @@ int es32f3_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     gpio_init_t gpio_initstruct;
@@ -330,8 +330,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
     return &pin_irq_map[map_index];
 };
 
-rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                               rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                               rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -375,7 +375,7 @@ rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -412,7 +412,7 @@ rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                               rt_uint32_t enabled)
+                               rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/fm33lc026/libraries/HAL_Drivers/drv_gpio.c

@@ -127,7 +127,7 @@ static rt_base_t fm33_pin_get(const char *name)
     return pin;
 }
 
-static void fm33_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void fm33_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     GPIO_Type *gpio_port;
     uint16_t gpio_pin;
@@ -148,11 +148,11 @@ static void fm33_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int fm33_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t fm33_pin_read(rt_device_t dev, rt_base_t pin)
 {
     GPIO_Type *gpio_port;
     uint16_t gpio_pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (PIN_PORT(pin) < PIN_STPORT_MAX)
     {
@@ -164,7 +164,7 @@ static int fm33_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void fm33_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void fm33_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     FL_GPIO_InitTypeDef GPIO_InitStruct;
 
@@ -237,8 +237,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_base_t pin)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t fm33_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t fm33_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -277,7 +277,7 @@ static rt_err_t fm33_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t fm33_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t fm33_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -309,7 +309,7 @@ static rt_err_t fm33_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t fm33_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                    rt_uint32_t enabled)
+                                    rt_uint8_t enabled)
 {
     const struct pin_irq_map *irqmap;
     rt_base_t level;

bsp/ft32/libraries/Drivers/drv_gpio.c

@@ -121,7 +121,7 @@ static rt_base_t ft32_pin_get(const char *name)
     return pin;
 }
 
-static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     GPIO_TypeDef *gpio_port;
     uint16_t gpio_pin;
@@ -135,11 +135,11 @@ static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int ft32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t ft32_pin_read(rt_device_t dev, rt_base_t pin)
 {
     GPIO_TypeDef *gpio_port;
     uint16_t gpio_pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (PIN_PORT(pin) < PIN_STPORT_MAX)
     {
@@ -151,7 +151,7 @@ static int ft32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void ft32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void ft32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
 
@@ -220,8 +220,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t ft32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t ft32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -260,7 +260,7 @@ static rt_err_t ft32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t ft32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t ft32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -350,7 +350,7 @@ static void rt_gpio_deinit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 
 
 static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                    rt_uint32_t enabled)
+                                    rt_uint8_t enabled)
 {
     const struct pin_irq_map *irqmap;
     rt_base_t level;

bsp/gd32/arm/libraries/gd32_drivers/drv_gpio.c

@@ -252,7 +252,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
   * @param  dev, pin, mode
   * @retval None
   */
-static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index = RT_NULL;
     rt_uint32_t pin_mode = 0;
@@ -344,7 +344,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
   * @param  dev, pin, valuie
   * @retval None
   */
-static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index = RT_NULL;
 
@@ -362,9 +362,9 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
   * @param  dev, pin
   * @retval None
   */
-static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
     const struct pin_index *index = RT_NULL;
 
     index = get_pin(pin);
@@ -415,8 +415,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
   * @param  device, pin, mode
   * @retval None
   */
-static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -462,7 +462,7 @@ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
   * @param  device, pin
   * @retval None
   */
-static rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -500,7 +500,7 @@ static rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
   * @param  device, pin, enabled
   * @retval None
   */
-static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32/risc-v/libraries/gd32_drivers/drv_gpio.c

@@ -180,7 +180,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
   * @param  dev, pin, mode
   * @retval None
   */
-static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index = RT_NULL;
     rt_uint32_t pin_mode = 0;
@@ -230,7 +230,7 @@ static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
   * @param  dev, pin, valuie
   * @retval None
   */
-static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index = RT_NULL;
 
@@ -248,9 +248,9 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
   * @param  dev, pin
   * @retval None
   */
-static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
     const struct pin_index *index = RT_NULL;
 
     index = get_pin(pin);
@@ -301,8 +301,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
   * @param  device, pin, mode
   * @retval None
   */
-static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -348,7 +348,7 @@ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
   * @param  device, pin
   * @retval None
   */
-static rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -386,7 +386,7 @@ static rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
   * @param  device, pin, enabled
   * @retval None
   */
-static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32105c-eval/drivers/drv_gpio.c

@@ -219,7 +219,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 };
 
-static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
@@ -262,7 +262,7 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
 }
 
-static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -275,9 +275,9 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-static int _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -315,8 +315,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     }
     return &pin_irq_map[mapindex];
 };
-static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -355,7 +355,7 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -386,7 +386,7 @@ static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
     return RT_EOK;
 }
-static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32107c-eval/drivers/drv_gpio.c

@@ -219,7 +219,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 };
 
-static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
@@ -262,7 +262,7 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
 }
 
-static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -275,9 +275,9 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-static int _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -315,8 +315,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     }
     return &pin_irq_map[mapindex];
 };
-static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -355,7 +355,7 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -386,7 +386,7 @@ static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
     return RT_EOK;
 }
-static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32303e-eval/drivers/drv_gpio.c

@@ -244,7 +244,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 };
 
-void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
@@ -287,7 +287,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
 }
 
-void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -300,9 +300,9 @@ void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -340,8 +340,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     }
     return &pin_irq_map[mapindex];
 };
-rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -380,7 +380,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -411,7 +411,7 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
     return RT_EOK;
 }
-rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32350r-eval/drivers/drv_gpio.c

@@ -156,7 +156,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 };
 
-void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index = RT_NULL;
     rt_uint32_t pin_mode = 0, pin_pupd = 0, pin_odpp = 0;
@@ -211,7 +211,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index = RT_NULL;
 
@@ -224,9 +224,9 @@ void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
     const struct pin_index *index = RT_NULL;
 
     index = get_pin(pin);
@@ -262,8 +262,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     return &pin_irq_map[map_index];
 };
 
-rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -304,7 +304,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index = RT_NULL;
     rt_base_t level;
@@ -337,7 +337,7 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32e230k-start/drivers/drv_gpio.c

@@ -132,7 +132,7 @@ const struct pin_index *get_pin(rt_uint8_t pin)
     return index;
 };
 
-void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
@@ -182,7 +182,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 
 }
 
-void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -195,9 +195,9 @@ void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -235,8 +235,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     }
     return &pin_irq_map[mapindex];
 };
-rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -275,7 +275,7 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -306,7 +306,7 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
     return RT_EOK;
 }
-rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/gd32vf103v-eval/drivers/drv_gpio.c

@@ -169,7 +169,7 @@ static const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-static void gd32vf_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void gd32vf_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -182,9 +182,9 @@ static void gd32vf_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value);
 }
 
-static int gd32vf_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t gd32vf_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     index = get_pin(pin);
@@ -197,7 +197,7 @@ static int gd32vf_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void gd32vf_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void gd32vf_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
 
@@ -263,8 +263,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t gd32vf_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t gd32vf_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -304,7 +304,7 @@ static rt_err_t gd32vf_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t gd32vf_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t gd32vf_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -337,7 +337,7 @@ static rt_err_t gd32vf_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled)
+                                     rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/hc32/libraries/hc32_drivers/drv_gpio.c

@@ -222,7 +222,7 @@ static void extint15_irq_handler(void)
     rt_interrupt_leave();
 }
 
-static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     stc_gpio_init_t stcGpioInit;
 
@@ -259,7 +259,7 @@ static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mod
     GPIO_Init(GPIO_PORT(pin), GPIO_PIN(pin), &stcGpioInit);
 }
 
-static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     uint8_t  gpio_port;
     uint16_t gpio_pin;
@@ -279,11 +279,11 @@ static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t va
     }
 }
 
-static int hc32_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t hc32_pin_read(struct rt_device *device, rt_base_t pin)
 {
     uint8_t  gpio_port;
     uint16_t gpio_pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (pin < PIN_MAX_NUM)
     {
@@ -302,8 +302,8 @@ static int hc32_pin_read(struct rt_device *device, rt_base_t pin)
     return value;
 }
 
-static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -341,7 +341,7 @@ static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -381,7 +381,7 @@ static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt)
     MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt);
 }
 
-static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     struct hc32_pin_irq_map *irq_map;
     rt_base_t level;

bsp/hc32l136/drivers/drv_gpio.c

@@ -41,7 +41,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
-    
+
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
@@ -58,7 +58,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
-    
+
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
@@ -75,7 +75,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
-    
+
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
@@ -92,7 +92,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
-    
+
 };
 
 static void pin_irq_handler(en_gpio_port_t port, en_gpio_pin_t pin)
@@ -110,7 +110,7 @@ void Gpio_IRQHandler(uint8_t u8Param)
 {
     en_gpio_pin_t i;
     en_gpio_port_t enPort;
-    
+
     enPort = (en_gpio_port_t)(GpioPortA + (GpioPortB - GpioPortA) * u8Param);
     rt_interrupt_enter();
     for (i=GpioPin0; i<=GpioPin15; i++)
@@ -122,10 +122,10 @@ void Gpio_IRQHandler(uint8_t u8Param)
         }
 
     }
-    rt_interrupt_leave();  
+    rt_interrupt_leave();
 }
 
-static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     uint8_t  gpio_port;
     uint16_t gpio_pin;
@@ -145,11 +145,11 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
 {
     uint8_t  gpio_port;
     uint16_t gpio_pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (pin < PIN_MAX_NUM)
     {
@@ -168,7 +168,7 @@ static int _pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     uint8_t  gpio_port;
     uint16_t gpio_pin;
@@ -179,7 +179,7 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     {
         return;
     }
-    
+
     switch (mode)
     {
     case PIN_MODE_OUTPUT:
@@ -222,12 +222,12 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg);
 }
 
-static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
-    
+
     if (pin >= PIN_MAX_NUM)
     {
         return -RT_ENOSYS;
@@ -257,7 +257,7 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -283,7 +283,7 @@ static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     rt_base_t level;
     en_gpio_port_t gpio_port;
@@ -316,7 +316,7 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
         pstcGpioCfg.enCtrlMode = GpioAHB;
         Gpio_Init(gpio_port, gpio_pin, &pstcGpioCfg);
         Gpio_ClearIrq(gpio_port, gpio_pin);
-        
+
         switch (pin_irq_hdr_tab[irqindex].mode)
         {
         case PIN_IRQ_MODE_RISING:
@@ -348,7 +348,7 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
             Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling);
             break;
         case PIN_IRQ_MODE_RISING_FALLING:
-            
+
             break;
         case PIN_IRQ_MODE_LOW_LEVEL:
             Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow);
@@ -373,7 +373,7 @@ static const struct rt_pin_ops _pin_ops =
 int rt_hw_pin_init(void)
 {
     Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE);
-    
+
     return rt_device_pin_register("pin", &_pin_ops, RT_NULL);
 }
 INIT_BOARD_EXPORT(rt_hw_pin_init);

bsp/hc32l196/drivers/drv_gpio.c

@@ -32,7 +32,7 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[PIN_MAX_NUM];
 
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
 
-static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     en_gpio_port_t gpio_port;
     en_gpio_pin_t gpio_pin;
@@ -80,7 +80,7 @@ static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     Gpio_Init(gpio_port, gpio_pin, &gpio_cfg);
 }
 
-static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     en_gpio_port_t gpio_port;
     en_gpio_pin_t gpio_pin;
@@ -103,7 +103,7 @@ static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int _pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
 {
     en_gpio_port_t gpio_port;
     en_gpio_pin_t gpio_pin;
@@ -120,8 +120,8 @@ static int _pin_read(rt_device_t dev, rt_base_t pin)
 }
 
 static rt_err_t _pin_attach_irq(struct rt_device *device,
-                                    rt_int32_t pin,
-                                    rt_uint32_t mode,
+                                    rt_base_t pin,
+                                    rt_uint8_t mode,
                                     void (*hdr)(void *args),
                                     void *args)
 {
@@ -149,7 +149,7 @@ static rt_err_t _pin_attach_irq(struct rt_device *device,
     return RT_EOK;
 }
 
-static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
 
@@ -200,7 +200,7 @@ static IRQn_Type get_irqn(rt_base_t pin)
 
 static rt_err_t _pin_irq_enable(struct rt_device *device,
                                     rt_base_t pin,
-                                    rt_uint32_t enabled)
+                                    rt_uint8_t enabled)
 {
     rt_base_t level = 0;
     en_gpio_port_t gpio_port;

bsp/hk32/libraries/rt_drivers/drv_gpio.c

@@ -94,7 +94,7 @@ static uint32_t pin_irq_enable_mask = 0;
 
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
 
-static void hk32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void hk32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     GPIO_TypeDef *gpio_port;
     uint16_t gpio_pin;
@@ -106,11 +106,11 @@ static void hk32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int hk32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t hk32_pin_read(rt_device_t dev, rt_base_t pin)
 {
     GPIO_TypeDef *gpio_port;
     uint16_t gpio_pin;
-    int value;
+    rt_int8_t value;
 
     value = PIN_LOW;
 
@@ -123,7 +123,7 @@ static int hk32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void hk32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void hk32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
 
@@ -201,8 +201,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t hk32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t hk32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -245,7 +245,7 @@ static rt_err_t hk32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t hk32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t hk32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -280,7 +280,7 @@ static rt_err_t hk32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t hk32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                    rt_uint32_t enabled)
+                                    rt_uint8_t enabled)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
     EXTI_InitTypeDef EXTI_InitStruct;

bsp/hpmicro/libraries/drivers/drv_gpio.c

@@ -163,7 +163,7 @@ SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr)
 #endif
 
 
-static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     /* TODO: Check the validity of the pin value */
     uint32_t gpio_idx = pin >> 5;
@@ -213,16 +213,16 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-static int hpm_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t hpm_pin_read(rt_device_t dev, rt_base_t pin)
 {
     /* TODO: Check the validity of the pin value */
     uint32_t gpio_idx = pin >> 5;
     uint32_t pin_idx = pin & 0x1FU;
 
-    return (int) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx);
+    return (rt_int8_t) gpio_read_pin(HPM_GPIO0, gpio_idx, pin_idx);
 }
 
-static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     /* TODO: Check the validity of the pin value */
     uint32_t gpio_idx = pin >> 5;
@@ -231,7 +231,7 @@ static void hpm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_write_pin(HPM_GPIO0, gpio_idx, pin_idx, value);
 }
 
-static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode,
+static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode,
         void (*hdr)(void *args), void *args)
 {
 
@@ -246,7 +246,7 @@ static rt_err_t hpm_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_
     return RT_EOK;
 }
 
-static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     level = rt_hw_interrupt_disable();
@@ -259,7 +259,7 @@ static rt_err_t hpm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     /* TODO: Check the validity of the pin value */
     uint32_t gpio_idx = pin >> 5;

bsp/k210/drivers/drv_gpio.c

@@ -68,7 +68,7 @@ static void free_pin_channel(rt_base_t pin_index)
 }
 
 
-static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     int pin_channel = get_pin_channel(pin);
     if(pin_channel == -1)
@@ -100,7 +100,7 @@ static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode
     }
 }
 
-static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     int pin_channel = get_pin_channel(pin);
     if(pin_channel == -1)
@@ -111,7 +111,7 @@ static void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t val
     gpiohs_set_pin(pin_channel, value == PIN_HIGH ? GPIO_PV_HIGH : GPIO_PV_LOW);
 }
 
-static int drv_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin)
 {
     int pin_channel = get_pin_channel(pin);
     if(pin_channel == -1)
@@ -165,8 +165,8 @@ static void pin_irq(int vector, void *param)
     }
 }
 
-static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                   rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                   rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     int pin_channel = get_pin_channel(pin);
     char irq_name[10];
@@ -204,7 +204,7 @@ static rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_err_t ret = RT_EOK;
 
@@ -221,7 +221,7 @@ static rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return ret;
 }
 
-static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     int pin_channel = get_pin_channel(pin);
 

bsp/loongson/ls1cdev/drivers/drv_gpio.c

@@ -17,7 +17,7 @@
 
 #ifdef RT_USING_PIN
 
-void ls1c_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+void ls1c_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     unsigned int gpio = pin;
 
@@ -34,7 +34,7 @@ void ls1c_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
 }
 
 
-void ls1c_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+void ls1c_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     unsigned int gpio = pin;
 
@@ -51,10 +51,10 @@ void ls1c_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
 }
 
 
-int ls1c_pin_read(struct rt_device *device, rt_base_t pin)
+rt_int8_t ls1c_pin_read(struct rt_device *device, rt_base_t pin)
 {
     unsigned int gpio = pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (0 == gpio_get(gpio))
     {
@@ -68,8 +68,8 @@ int ls1c_pin_read(struct rt_device *device, rt_base_t pin)
     return value;
 }
 
-rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                             rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     unsigned int gpio = pin;
     char irq_name[10];
@@ -97,12 +97,12 @@ rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-rt_err_t ls1c_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t ls1c_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     return RT_EOK;
 }
 
-rt_err_t ls1c_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t ls1c_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     unsigned int gpio = pin;
 

bsp/loongson/ls2kdev/drivers/drv_gpio.c

@@ -17,7 +17,7 @@
 #define     GPIO_IRQ_NUM                    (64)
 static struct gpio_irq_def _g_gpio_irq_tbl[GPIO_IRQ_NUM];
 
-static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     struct loongson_gpio *gpio;
     rt_uint64_t m;
@@ -48,7 +48,7 @@ static void loongson_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t
     }
 }
 
-static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     struct loongson_gpio *gpio;
     rt_uint64_t m;
@@ -67,10 +67,10 @@ static void loongson_pin_write(struct rt_device *device, rt_base_t pin, rt_base_
     else
         gpio->GPIO0_O &= ~m;
 }
-static int loongson_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t loongson_pin_read(struct rt_device *device, rt_base_t pin)
 {
     struct loongson_gpio *gpio;
-    int rc;
+    rt_int8_t rc;
 
     gpio = (void *)device->user_data;
     rt_uint64_t m;
@@ -84,7 +84,7 @@ static int loongson_pin_read(struct rt_device *device, rt_base_t pin)
 }
 
 /* TODO: add GPIO interrupt */
-static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_uint8_t index;
     rt_uint64_t m;
@@ -115,7 +115,7 @@ static rt_err_t loongson_pin_attach_irq(struct rt_device *device, rt_int32_t pin
 
     return RT_EOK;
 }
-static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     struct loongson_gpio *gpio;
 
@@ -141,7 +141,7 @@ static rt_err_t loongson_pin_detach_irq(struct rt_device *device, rt_int32_t pin
 
     return RT_EOK;
 }
-static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t loongson_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     struct loongson_gpio *gpio;
 

bsp/lpc54114-lite/drivers/drv_gpio.c

@@ -81,7 +81,7 @@ static rt_base_t lpc_pin_get(const char *name)
 }
 
 /* Configure pin mode. pin 0~63 means PIO0_0 ~ PIO1_31 */
-static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     int portx, piny, dir;
     uint32_t pin_cfg;
@@ -129,7 +129,7 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     CLOCK_DisableClock(kCLOCK_Iocon);
 }
 
-static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     int portx, piny;
     portx = get_port(pin);
@@ -141,9 +141,10 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     GPIO_PinWrite(GPIO, portx, piny, value);
 }
 
-static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t lpc_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int  portx, piny, value;
+    int  portx, piny;
+    rt_int8_t value;
 
     if(pin > PIN_MAX_VAL)
         return -RT_ERROR;
@@ -151,7 +152,7 @@ static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
     portx = get_port(pin);
     piny  = get_pin(pin);
 
-    value = (int)(GPIO_PinRead(GPIO, portx, piny));
+    value = (rt_int8_t)(GPIO_PinRead(GPIO, portx, piny));
 
     return value;
 }
@@ -181,8 +182,8 @@ void callback(pint_pin_int_t pintr, uint32_t pmatch_status)
     pin_irq_hdr(pintr, pmatch_status);
 }
 
-static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                   rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                   rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;
 
@@ -253,7 +254,7 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     int i;
 
@@ -275,7 +276,7 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                   rt_uint32_t enabled)
+                                   rt_uint8_t enabled)
 {
     int irqn_type, i;
 

bsp/maxim/libraries/HAL_Drivers/drv_gpio.c

@@ -30,7 +30,7 @@
 #define PIN_MCU_PORT(pin)  PIN_PORT(pin)
 #define PIN_MCU_PIN(pin) ((uint32_t)(1u << PIN_NO(pin)))
 
-static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     gpio_cfg_t tmp_gpio_cfg;
     tmp_gpio_cfg.port = PIN_PORT(pin);
@@ -46,9 +46,9 @@ static void mcu_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 
 }
 
-static int mcu_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t mcu_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     gpio_cfg_t tmp_gpio_cfg;
     tmp_gpio_cfg.port = PIN_PORT(pin);
     tmp_gpio_cfg.mask = PIN_MCU_PIN(pin);
@@ -65,7 +65,7 @@ static int mcu_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     gpio_cfg_t tmp_gpio_cfg;
     int ret = 0;
@@ -103,8 +103,8 @@ static void mcu_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 }
 
 
-static rt_err_t mcu_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                   rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
+static rt_err_t mcu_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                   rt_uint8_t irq_mode, void (*hdr)(void *args), void *args)
 {
     gpio_cfg_t tmp_gpio_cfg;
     tmp_gpio_cfg.port = PIN_MCU_PORT(pin);
@@ -149,7 +149,7 @@ static rt_err_t mcu_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t mcu_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t mcu_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     gpio_cfg_t tmp_gpio_cfg;
     tmp_gpio_cfg.port = PIN_MCU_PORT(pin);
@@ -163,7 +163,7 @@ static rt_err_t mcu_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t mcu_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                   rt_uint32_t enabled)
+                                   rt_uint8_t enabled)
 {
     gpio_cfg_t tmp_gpio_cfg;
     tmp_gpio_cfg.port = PIN_MCU_PORT(pin);

bsp/mm32/libraries/HAL_Drivers/drv_gpio.c

@@ -120,7 +120,7 @@ static rt_base_t mm32_pin_get(const char *name)
     return pin;
 }
 
-static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     GPIO_Type *gpio_port;
     uint16_t gpio_pin;
@@ -134,11 +134,11 @@ static void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int mm32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin)
 {
     GPIO_Type *gpio_port;
     uint16_t gpio_pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (PIN_PORT(pin) < PIN_STPORT_MAX)
     {
@@ -150,7 +150,7 @@ static int mm32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     GPIO_Init_Type GPIO_InitStruct;
 
@@ -216,8 +216,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -256,7 +256,7 @@ static rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t mm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t mm32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -288,7 +288,7 @@ static rt_err_t mm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled)
+                                     rt_uint8_t enabled)
 {
     const struct pin_irq_map *irqmap;
     rt_base_t level;

bsp/mm32f103x/drivers/drv_gpio.c

@@ -156,7 +156,7 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -175,9 +175,9 @@ void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-int mm32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -197,7 +197,7 @@ int mm32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitTypeDef  GPIO_InitStructure;
@@ -261,8 +261,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     }
     return &mm32_pin_irq_map[mapindex];
 };
-rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                             rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -302,7 +302,7 @@ rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -334,7 +334,7 @@ rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                             rt_uint32_t enabled)
+                             rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/mm32f327x/drivers/drv_gpio.c

@@ -151,7 +151,7 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -171,9 +171,9 @@ void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-int mm32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -193,7 +193,7 @@ int mm32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitTypeDef GPIO_InitStructure;
@@ -257,8 +257,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     }
     return &mm32_pin_irq_map[mapindex];
 };
-rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                             rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -297,7 +297,7 @@ rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -329,7 +329,7 @@ rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                             rt_uint32_t enabled)
+                             rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/mm32l3xx/drivers/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -140,10 +140,10 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
-	
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -155,14 +155,14 @@ void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
     else
     {
-	
+
         GPIO_SetBits(index->gpio, index->pin);
     }
 }
 
-int mm32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t mm32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -182,7 +182,7 @@ int mm32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitTypeDef  GPIO_InitStructure;
@@ -246,8 +246,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     }
     return &mm32_pin_irq_map[mapindex];
 };
-rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                             rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -287,7 +287,7 @@ rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -319,7 +319,7 @@ rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                             rt_uint32_t enabled)
+                             rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/n32/libraries/n32_drivers/drv_gpio.c

@@ -206,7 +206,7 @@ static const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-static void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -218,9 +218,9 @@ static void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     GPIO_WriteBit(index->gpio, index->pin, (Bit_OperateType)value);
 }
 
-static int n32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t n32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -277,7 +277,7 @@ static void n32_gpio_clock_enable(GPIO_Module* GPIOx)
     }
 }
 
-static void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitType GPIO_InitStructure;
@@ -412,8 +412,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -453,7 +453,7 @@ static rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -486,7 +486,7 @@ static rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled)
+                                     rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c

@@ -558,7 +558,7 @@ rt_base_t n32_pin_get(const char *name)
     return 0;
 }
 
-void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -578,9 +578,9 @@ void n32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-int n32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t n32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -603,7 +603,7 @@ int n32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void n32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitType  GPIO_InitStructure;
@@ -676,8 +676,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     }
     return &pin_irq_map[mapindex];
 };
-rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                            rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                            rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -717,7 +717,7 @@ rt_err_t n32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -749,7 +749,7 @@ rt_err_t n32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                            rt_uint32_t enabled)
+                            rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/nrf5x/libraries/drivers/drv_gpio.c

@@ -101,7 +101,7 @@ static const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -114,9 +114,9 @@ static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     nrf_gpio_pin_write(pin, value);
 }
 
-static int nrf5x_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t nrf5x_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -132,7 +132,7 @@ static int nrf5x_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void nrf5x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void nrf5x_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
 
@@ -193,8 +193,8 @@ static void pin_irq_hdr(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action)
 /*  args = true : hi_accuracy(IN_EVENT)
  *  args = false: lo_accuracy(PORT_EVENT)
  */
-static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_int32_t irqindex = -1;
@@ -270,7 +270,7 @@ static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     }
 }
 
-static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -306,7 +306,7 @@ static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t nrf5x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled)
+                                     rt_uint8_t enabled)
 {
     const struct pin_index *index;
     rt_base_t level;

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c

@@ -161,7 +161,7 @@ static const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -174,9 +174,9 @@ static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     gpio_bit_write(index->gpio, index->pin, (bit_status)value);
 }
 
-static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -192,7 +192,7 @@ static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
@@ -257,8 +257,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -298,7 +298,7 @@ static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -331,7 +331,7 @@ static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                    rt_uint32_t enabled)
+                                    rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c

@@ -101,7 +101,7 @@ void gpio_irq_enable(rt_uint8_t index, bcm_gpio_pin pin)
 
 }
 
-static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
     RT_ASSERT(!(mode & 0x8));
@@ -129,7 +129,7 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
     RT_ASSERT(!(value & 0xE));
@@ -141,13 +141,13 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t valu
 
 }
 
-static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
     return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW;
 }
 
-static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
@@ -194,7 +194,7 @@ static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, r
     return RT_EOK;
 }
 
-static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
@@ -215,7 +215,7 @@ static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 

bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c

@@ -102,7 +102,7 @@ void gpio_irq_enable(rt_uint8_t index, bcm_gpio_pin pin)
 
 }
 
-static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
     RT_ASSERT(!(mode & 0x8));
@@ -130,7 +130,7 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
     RT_ASSERT(!(value & 0xE));
@@ -142,13 +142,13 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t valu
 
 }
 
-static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
     return (BCM2835_GPIO_GPLEV(pin / 32) & (1 << (pin % 32)))? PIN_HIGH : PIN_LOW;
 }
 
-static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
@@ -195,7 +195,7 @@ static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, r
     return RT_EOK;
 }
 
-static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 
@@ -216,7 +216,7 @@ static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     RT_ASSERT((BCM_GPIO_PIN_0 <= pin) && (pin < BCM_GPIO_PIN_NULL));
 

bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c

@@ -148,7 +148,7 @@ void prev_raspi_pin_write(GPIO_PIN pin, int pin_value)
     }
 }
 
-static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
 {
     GPIO_FUNC raspi_mode = OUTPUT;
 
@@ -175,15 +175,15 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
     prev_raspi_pin_mode((GPIO_PIN)pin, raspi_mode);
 }
 
-static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
 {
     prev_raspi_pin_write(pin, value);
 }
 
-static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t raspi_pin_read(struct rt_device *device, rt_base_t pin)
 {
     uint32_t num = pin / 32;
-    uint32_t pin_level = 0;
+    rt_int8_t pin_level = 0;
 
     if(num == 0)
     {
@@ -212,7 +212,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
     return pin_level;
 }
 
-static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_uint8_t index;
     rt_uint32_t  reg_value;
@@ -300,7 +300,7 @@ static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, r
     return RT_EOK;
 }
 
-static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_uint8_t index;
     if (pin <= 27)
@@ -318,7 +318,7 @@ static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     rt_uint8_t index;
     if (pin <= 27)

bsp/raspberry-pico/drivers/drv_gpio.c

@@ -10,7 +10,7 @@
 
 #include "drv_gpio.h"
 
-static void pico_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+static void pico_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
 {
     RT_ASSERT((0 <= pin) && (pin < N_GPIOS));
 
@@ -35,13 +35,13 @@ static void pico_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-static void pico_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+static void pico_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
 {
     RT_ASSERT((0 <= pin) && (pin < N_GPIOS));
     gpio_put(pin, value);
 }
 
-static int pico_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t pico_pin_read(struct rt_device *device, rt_base_t pin)
 {
     RT_ASSERT((0 <= pin) && (pin < N_GPIOS));
     return (gpio_get(pin)? PIN_HIGH : PIN_LOW);

bsp/rockchip/common/drivers/drv_gpio.c

@@ -210,7 +210,7 @@ static rt_err_t pin_irq_enable(struct rt_device *dev, rt_base_t pin, rt_uint32_t
     return RT_EOK;
 }
 
-static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
 {
     RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
 
@@ -242,13 +242,13 @@ static void pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-static void pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+static void pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
 {
     RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
     HAL_GPIO_SetPinLevel(get_st_gpio(pin), get_st_pin(pin), value);
 }
 
-static int pin_read(struct rt_device *dev, rt_base_t pin)
+static rt_int8_t pin_read(struct rt_device *dev, rt_base_t pin)
 {
     RT_ASSERT(PIN_BANK(pin) < GPIO_BANK_NUM);
     return HAL_GPIO_GetPinLevel(get_st_gpio(pin), get_st_pin(pin));;

bsp/rv32m1_vega/ri5cy/driver/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,24 +21,24 @@
 
 struct vega_pin
 {
-    rt_uint16_t   pin; 
-    GPIO_Type    *gpio; 
-    rt_uint32_t   gpio_pin; 
-}; 
+    rt_uint16_t   pin;
+    GPIO_Type    *gpio;
+    rt_uint32_t   gpio_pin;
+};
 
 struct vega_irq
 {
-    rt_uint16_t           enable; 
-    struct rt_pin_irq_hdr irq_info; 
+    rt_uint16_t           enable;
+    struct rt_pin_irq_hdr irq_info;
 };
 
-#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0])) 
-#define __VEGA_PIN_DEFAULT {0, 0, 0} 
-#define __VEGA_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN} 
+#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
+#define __VEGA_PIN_DEFAULT {0, 0, 0}
+#define __VEGA_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN}
 
-static const struct vega_pin vega_pin_map[] = 
+static const struct vega_pin vega_pin_map[] =
 {
-    __VEGA_PIN_DEFAULT, 
+    __VEGA_PIN_DEFAULT,
 
     /* GPIOA */
     __VEGA_PIN(1, GPIOA, 0),
@@ -209,9 +209,9 @@ static const struct vega_pin vega_pin_map[] =
     __VEGA_PIN(158, GPIOE, 29),
     __VEGA_PIN(159, GPIOE, 30),
     __VEGA_PIN(160, GPIOE, 31),
-}; 
+};
 
-static struct vega_irq vega_irq_map[] = 
+static struct vega_irq vega_irq_map[] =
 {
     {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
     {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
@@ -245,13 +245,13 @@ static struct vega_irq vega_irq_map[] =
     {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
     {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
     {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
-}; 
+};
 
 void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
 {
     if((GPIO_GetPinsInterruptFlags(base) & (1 << gpio_pin)) != 0)
     {
-        GPIO_ClearPinsInterruptFlags(base, gpio_pin); 
+        GPIO_ClearPinsInterruptFlags(base, gpio_pin);
 
         if(vega_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
         {
@@ -284,19 +284,19 @@ static IRQn_Type vega_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
     {
         irq_num = PORTE_IRQn;
     }
-    
-    return irq_num; 
+
+    return irq_num;
 }
 
-static void vega_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void vega_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     clock_ip_name_t clock;
-    gpio_pin_config_t gpio; 
-    rt_uint32_t config_value = 0; 
+    gpio_pin_config_t gpio;
+    rt_uint32_t config_value = 0;
 
     if((pin > __ARRAY_LEN(vega_pin_map)) || (pin == 0))
     {
-        return; 
+        return;
     }
 
     if (vega_pin_map[pin].gpio == GPIOA)
@@ -312,50 +312,50 @@ static void vega_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 
     CLOCK_EnableClock(clock);
 
-    gpio.outputLogic = 0; 
+    gpio.outputLogic = 0;
 
     switch(mode)
     {
         case PIN_MODE_OUTPUT:
         {
             config_value = 0x1030U;
-            gpio.pinDirection = kGPIO_DigitalOutput; 
+            gpio.pinDirection = kGPIO_DigitalOutput;
         }
-        break; 
-    
+        break;
+
         case PIN_MODE_INPUT:
         {
             config_value = 0x1030U;
-            gpio.pinDirection = kGPIO_DigitalInput; 
+            gpio.pinDirection = kGPIO_DigitalInput;
         }
         break;
 
         case PIN_MODE_INPUT_PULLDOWN:
         {
             config_value = 0x1030U;
-            gpio.pinDirection = kGPIO_DigitalInput; 
+            gpio.pinDirection = kGPIO_DigitalInput;
         }
-        break; 
+        break;
 
         case PIN_MODE_INPUT_PULLUP:
         {
             config_value = 0x5030U;
-            gpio.pinDirection = kGPIO_DigitalInput; 
+            gpio.pinDirection = kGPIO_DigitalInput;
         }
         break;
 
         case PIN_MODE_OUTPUT_OD:
         {
             config_value = 0x1830U;
-            gpio.pinDirection = kGPIO_DigitalOutput; 
+            gpio.pinDirection = kGPIO_DigitalOutput;
         }
         break;
     }
 
-    GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio); 
+    GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio);
 }
 
-static int vega_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t vega_pin_read(rt_device_t dev, rt_base_t pin)
 {
     uint32_t value;
 
@@ -365,7 +365,7 @@ static int vega_pin_read(rt_device_t dev, rt_base_t pin)
     return PIN_LOW;
 }
 
-static void vega_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void vega_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     if (value == PIN_HIGH)
         GPIO_SetPinsOutput(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
@@ -373,42 +373,42 @@ static void vega_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
         GPIO_ClearPinsOutput(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
 }
 
-static rt_err_t vega_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t vega_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+    rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
-    const struct vega_pin* pin_map = RT_NULL; 
-    struct vega_irq* irq_map = RT_NULL; 
+    const struct vega_pin* pin_map = RT_NULL;
+    struct vega_irq* irq_map = RT_NULL;
+
+    pin_map = &vega_pin_map[pin];
+    irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
 
-    pin_map = &vega_pin_map[pin]; 
-    irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin]; 
-    
-    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    if(pin_map == RT_NULL || irq_map == RT_NULL)
     {
-        return -RT_ENOSYS; 
+        return -RT_ENOSYS;
     }
 
     if(irq_map->enable == PIN_IRQ_ENABLE)
     {
-        return -RT_EBUSY; 
+        return -RT_EBUSY;
     }
-    
-    irq_map->irq_info.pin  = pin; 
-    irq_map->irq_info.hdr  = hdr; 
-    irq_map->irq_info.mode = mode; 
-    irq_map->irq_info.args = args; 
-    
+
+    irq_map->irq_info.pin  = pin;
+    irq_map->irq_info.hdr  = hdr;
+    irq_map->irq_info.mode = mode;
+    irq_map->irq_info.args = args;
+
     return RT_EOK;
 }
 
-static rt_err_t vega_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t vega_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
-    const struct vega_pin* pin_map = RT_NULL; 
-    struct vega_irq* irq_map = RT_NULL; 
+    const struct vega_pin* pin_map = RT_NULL;
+    struct vega_irq* irq_map = RT_NULL;
+
+    pin_map = &vega_pin_map[pin];
+    irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
 
-    pin_map = &vega_pin_map[pin]; 
-    irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin]; 
-    
-    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    if(pin_map == RT_NULL || irq_map == RT_NULL)
     {
         return -RT_ENOSYS;
     }
@@ -426,28 +426,28 @@ static rt_err_t vega_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 
-static rt_err_t vega_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t vega_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
-    gpio_pin_config_t gpio; 
+    gpio_pin_config_t gpio;
     IRQn_Type irq_num;
-    rt_uint32_t config_value = 0x1b0a0; 
+    rt_uint32_t config_value = 0x1b0a0;
 
-    const struct vega_pin* pin_map = RT_NULL; 
-    struct vega_irq* irq_map = RT_NULL; 
-    
-    pin_map = &vega_pin_map[pin]; 
-    irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin]; 
+    const struct vega_pin* pin_map = RT_NULL;
+    struct vega_irq* irq_map = RT_NULL;
 
-    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    pin_map = &vega_pin_map[pin];
+    irq_map = &vega_irq_map[vega_pin_map[pin].gpio_pin];
+
+    if(pin_map == RT_NULL || irq_map == RT_NULL)
     {
-        return -RT_ENOSYS; 
+        return -RT_ENOSYS;
     }
 
-    if(enabled == PIN_IRQ_ENABLE) 
+    if(enabled == PIN_IRQ_ENABLE)
     {
         if(irq_map->enable == PIN_IRQ_ENABLE)
         {
-            return -RT_EBUSY; 
+            return -RT_EBUSY;
         }
 
         if(irq_map->irq_info.pin != pin)
@@ -455,40 +455,40 @@ static rt_err_t vega_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_
             return -RT_EIO;
         }
 
-        irq_map->enable = PIN_IRQ_ENABLE; 
+        irq_map->enable = PIN_IRQ_ENABLE;
 
-        gpio.pinDirection     = kGPIO_DigitalInput; 
-        gpio.outputLogic   = 0; 
+        gpio.pinDirection     = kGPIO_DigitalInput;
+        gpio.outputLogic   = 0;
 
-        irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin); 
+        irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
 
         /* TODOL enable port */
         EnableIRQ(irq_num);
 
-        GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio); 
-        // GPIO_EnablePinsInterruptFlags(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin); 
+        GPIO_PinInit(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin, &gpio);
+        // GPIO_EnablePinsInterruptFlags(vega_pin_map[pin].gpio, 1U << vega_pin_map[pin].gpio_pin);
     }
     else if(enabled == PIN_IRQ_DISABLE)
     {
         if(irq_map->enable == PIN_IRQ_DISABLE)
         {
-            return RT_EOK; 
+            return RT_EOK;
         }
 
         irq_map->enable = PIN_IRQ_DISABLE;
-        irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin); 
+        irq_num = vega_get_irqnum(vega_pin_map[pin].gpio, vega_pin_map[pin].gpio_pin);
 
         DisableIRQ(irq_num);
     }
     else
     {
-        return -RT_EINVAL; 
+        return -RT_EINVAL;
     }
-    
+
     return RT_EOK;
 }
 
-static const struct rt_pin_ops vega_pin_ops = 
+static const struct rt_pin_ops vega_pin_ops =
 {
     vega_pin_mode,
     vega_pin_write,
@@ -502,11 +502,11 @@ static const struct rt_pin_ops vega_pin_ops =
 
 int rt_hw_pin_init(void)
 {
-    int ret = RT_EOK; 
+    int ret = RT_EOK;
 
     ret = rt_device_pin_register("pin", &vega_pin_ops, RT_NULL);
     return ret;
 }
-INIT_BOARD_EXPORT(rt_hw_pin_init); 
+INIT_BOARD_EXPORT(rt_hw_pin_init);
 
 #endif /*RT_USING_PIN */

bsp/smartfusion2/drivers/drv_gpio.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -53,32 +53,32 @@ static struct rt_pin_irq_hdr sf2_pin_irq_hdr_tab[] =
 };
 
 /* configure an individual GPIO port */
-static void sf2_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void sf2_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     uint32_t config;
     switch (mode)
     {
-        case PIN_MODE_OUTPUT: 
+        case PIN_MODE_OUTPUT:
             config = MSS_GPIO_OUTPUT_MODE;
             break;
-        case PIN_MODE_INPUT: 
+        case PIN_MODE_INPUT:
             config = MSS_GPIO_INPUT_MODE;
             break;
-        default: 
-            config = MSS_GPIO_INOUT_MODE;     
+        default:
+            config = MSS_GPIO_INOUT_MODE;
             break;
     }
     MSS_GPIO_config((mss_gpio_id_t )pin, config);
 }
 
-static int sf2_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t sf2_pin_read(rt_device_t dev, rt_base_t pin)
 {
     uint32_t value;
     value = MSS_GPIO_get_inputs() & (1<<pin);
     return ((value) ? PIN_HIGH : PIN_LOW);
 }
 
-static void sf2_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void sf2_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     if (value == PIN_HIGH)
         MSS_GPIO_set_output((mss_gpio_id_t )pin, 1);
@@ -86,13 +86,13 @@ static void sf2_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
         MSS_GPIO_set_output((mss_gpio_id_t )pin, 0);
 }
 
-static rt_err_t sf2_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                        rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t sf2_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                        rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
 
     level = rt_hw_interrupt_disable();
-    
+
     if (sf2_pin_irq_hdr_tab[pin].pin == pin   &&
         sf2_pin_irq_hdr_tab[pin].hdr == hdr   &&
         sf2_pin_irq_hdr_tab[pin].mode == mode &&
@@ -110,35 +110,35 @@ static rt_err_t sf2_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     sf2_pin_irq_hdr_tab[pin].hdr = hdr;
     sf2_pin_irq_hdr_tab[pin].mode = mode;
     sf2_pin_irq_hdr_tab[pin].args = args;
-    
+
     rt_hw_interrupt_enable(level);
 
     return RT_EOK;
 }
 
-static rt_err_t sf2_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t sf2_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
 
     level = rt_hw_interrupt_disable();
-    
+
     if (sf2_pin_irq_hdr_tab[pin].pin == -1)
     {
         rt_hw_interrupt_enable(level);
         return RT_EOK;
     }
-    
+
     sf2_pin_irq_hdr_tab[pin].pin = -1;
     sf2_pin_irq_hdr_tab[pin].hdr = RT_NULL;
     sf2_pin_irq_hdr_tab[pin].mode = 0;
     sf2_pin_irq_hdr_tab[pin].args = RT_NULL;
-    
+
     rt_hw_interrupt_enable(level);
 
     return RT_EOK;
 }
 
-static rt_err_t sf2_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t sf2_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     uint32_t mode = 0;
     rt_base_t level;
@@ -171,7 +171,7 @@ static rt_err_t sf2_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u
         }
         MSS_GPIO_config((mss_gpio_id_t )pin, MSS_GPIO_INPUT_MODE | mode);
         MSS_GPIO_enable_irq((mss_gpio_id_t )pin);
-        
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
@@ -185,7 +185,7 @@ static rt_err_t sf2_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u
     return RT_EOK;
 }
 
-static const struct rt_pin_ops sf2_pin_ops = 
+static const struct rt_pin_ops sf2_pin_ops =
 {
     sf2_pin_mode,
     sf2_pin_write,
@@ -198,13 +198,13 @@ static const struct rt_pin_ops sf2_pin_ops =
 
 int rt_hw_pin_init(void)
 {
-    rt_err_t result = RT_EOK; 
+    rt_err_t result = RT_EOK;
     MSS_GPIO_init();
     result = rt_device_pin_register("pin", &sf2_pin_ops, RT_NULL);
     RT_ASSERT(result == RT_EOK);
     return result;
 }
-INIT_BOARD_EXPORT(rt_hw_pin_init); 
+INIT_BOARD_EXPORT(rt_hw_pin_init);
 
 rt_inline void pin_irq_hdr(int pin)
 {

bsp/synwit/swm320/drivers/drv_gpio.c

@@ -263,7 +263,7 @@ static const struct swm_pin_device *_pin2struct(uint8_t pin)
     return gpio_obj;
 }
 
-static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct swm_pin_device *gpio_obj;
     int dir = 0;
@@ -306,7 +306,7 @@ static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     GPIO_Init(gpio_obj->gpio, gpio_obj->pin, dir, pull_up, pull_down);
 }
 
-static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct swm_pin_device *gpio_obj;
 
@@ -325,7 +325,7 @@ static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int swm_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t swm_pin_read(rt_device_t dev, rt_base_t pin)
 {
     const struct swm_pin_device *gpio_obj;
 
@@ -334,12 +334,12 @@ static int swm_pin_read(rt_device_t dev, rt_base_t pin)
     {
         return PIN_LOW;
     }
-    return (int)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
+    return (rt_int8_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
 }
 
 static rt_err_t swm_pin_attach_irq(struct rt_device *device,
-                                   rt_int32_t pin,
-                                   rt_uint32_t mode,
+                                   rt_base_t pin,
+                                   rt_uint8_t mode,
                                    void (*hdr)(void *args),
                                    void *args)
 {
@@ -362,7 +362,7 @@ static rt_err_t swm_pin_attach_irq(struct rt_device *device,
     return RT_EOK;
 }
 
-static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
 
@@ -376,7 +376,7 @@ static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
 static rt_err_t swm_pin_irq_enable(struct rt_device *device,
                                    rt_base_t pin,
-                                   rt_uint32_t enabled)
+                                   rt_uint8_t enabled)
 {
     const struct swm_pin_device *gpio_obj;
     rt_base_t level = 0;

bsp/synwit/swm341/drivers/drv_gpio.c

@@ -284,7 +284,7 @@ static const struct swm_pin_device *_pin2struct(uint8_t pin)
     return gpio_obj;
 }
 
-static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct swm_pin_device *gpio_obj;
     int dir = 0;
@@ -328,7 +328,7 @@ static void swm_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     GPIO_Init(gpio_obj->gpio, gpio_obj->pin, dir, pull_up, pull_down, open_drain);
 }
 
-static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct swm_pin_device *gpio_obj;
 
@@ -347,7 +347,7 @@ static void swm_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int swm_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t swm_pin_read(rt_device_t dev, rt_base_t pin)
 {
     const struct swm_pin_device *gpio_obj;
 
@@ -356,12 +356,12 @@ static int swm_pin_read(rt_device_t dev, rt_base_t pin)
     {
         return PIN_LOW;
     }
-    return (int)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
+    return (rt_int8_t)GPIO_GetBit(gpio_obj->gpio, gpio_obj->pin);
 }
 
 static rt_err_t swm_pin_attach_irq(struct rt_device *device,
-                                   rt_int32_t pin,
-                                   rt_uint32_t mode,
+                                   rt_base_t pin,
+                                   rt_uint8_t mode,
                                    void (*hdr)(void *args),
                                    void *args)
 {
@@ -384,7 +384,7 @@ static rt_err_t swm_pin_attach_irq(struct rt_device *device,
     return RT_EOK;
 }
 
-static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
 
@@ -398,7 +398,7 @@ static rt_err_t swm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
 static rt_err_t swm_pin_irq_enable(struct rt_device *device,
                                    rt_base_t pin,
-                                   rt_uint32_t enabled)
+                                   rt_uint8_t enabled)
 {
     const struct swm_pin_device *gpio_obj;
     rt_base_t level = 0;

bsp/tae32f5300/drivers/drv_gpio.c

@@ -104,7 +104,7 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -123,9 +123,9 @@ void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-int _pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -145,7 +145,7 @@ int _pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitTypeDef GPIO_InitStructure;
@@ -192,19 +192,19 @@ void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     LL_GPIO_Init(index->gpio, &GPIO_InitStructure);
 }
 
-rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                              rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     return -RT_ERROR;
 }
 
-rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     return -RT_ERROR;
 }
 
 rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                              rt_uint32_t enabled)
+                              rt_uint8_t enabled)
 {
     return -RT_ERROR;
 }

bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c

@@ -24,11 +24,11 @@
 #define PIN_c28x_PORT_MAX 6 /* gpioA to GPIOF in total*/
 #define PIN_IRQ_MAX 5   /* XINT1 to XINT5 in total */
 
-static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args);
-static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin);
+static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args);
+static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_base_t pin);
 static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled);
+                                     rt_uint8_t enabled);
 
 static rt_base_t c28x_pin_get(const char *name)
 {
@@ -57,7 +57,7 @@ static rt_base_t c28x_pin_get(const char *name)
     return hw_pin_num;
 }
 
-static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     volatile Uint32 *gpioDataReg;
     Uint32 pinMask;
@@ -76,10 +76,10 @@ static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int c28x_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t c28x_pin_read(rt_device_t dev, rt_base_t pin)
 {
     volatile Uint32 *gpioDataReg;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (PIN_PORT(pin) < PIN_c28x_PORT_MAX)
     {
@@ -90,7 +90,7 @@ static int c28x_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     volatile Uint32 *gpioBaseAddr;
     volatile Uint32 *dir, *pud, *odr;
@@ -183,8 +183,8 @@ rt_inline rt_int32_t get_irq_index(rt_uint32_t pin)
 
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
 
-static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -217,7 +217,7 @@ static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -250,7 +250,7 @@ static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled)
+                                     rt_uint8_t enabled)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;

bsp/tkm32F499/drivers/drv_gpio.c

@@ -184,7 +184,7 @@ const struct pin_index *get_pin(uint8_t pin)
     return index;
 };
 
-void tkm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void tkm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     const struct pin_index *index;
 
@@ -203,9 +203,9 @@ void tkm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-int tkm32_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t tkm32_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;
+    rt_int8_t value;
     const struct pin_index *index;
 
     value = PIN_LOW;
@@ -225,7 +225,7 @@ int tkm32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-void tkm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void tkm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     const struct pin_index *index;
     GPIO_InitTypeDef  GPIO_InitStructure;
@@ -289,8 +289,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
     }
     return &tkm32_pin_irq_map[mapindex];
 };
-rt_err_t tkm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+rt_err_t tkm32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                             rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -330,7 +330,7 @@ rt_err_t tkm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
 
     return RT_EOK;
 }
-rt_err_t tkm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+rt_err_t tkm32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     const struct pin_index *index;
     rt_base_t level;
@@ -362,7 +362,7 @@ rt_err_t tkm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
     return RT_EOK;
 }
 rt_err_t tkm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                             rt_uint32_t enabled)
+                             rt_uint8_t enabled)
 {
     const struct pin_index *index;
     const struct pin_irq_map *irqmap;

bsp/w60x/drivers/drv_pin.c

@@ -19,7 +19,7 @@
 
 #ifdef BSP_USING_PIN
 
-static void wm_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void wm_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     rt_int16_t gpio_pin;
     gpio_pin = wm_get_pin(pin);
@@ -46,7 +46,7 @@ static void wm_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
     return;
 }
 
-static void wm_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void wm_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     rt_int16_t gpio_pin;
     gpio_pin = wm_get_pin(pin);
@@ -58,7 +58,7 @@ static void wm_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t valu
     return;
 }
 
-static int wm_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t wm_pin_read(struct rt_device *device, rt_base_t pin)
 {
     rt_int16_t gpio_pin;
     gpio_pin = wm_get_pin(pin);
@@ -69,8 +69,8 @@ static int wm_pin_read(struct rt_device *device, rt_base_t pin)
     return tls_gpio_read((enum tls_io_name)gpio_pin);
 }
 
-static rt_err_t wm_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                  rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t wm_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                  rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_int16_t gpio_pin;
     rt_base_t level;
@@ -110,12 +110,12 @@ static rt_err_t wm_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t wm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t wm_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     return RT_EOK;
 }
 
-static rt_err_t wm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+static rt_err_t wm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
 {
     rt_int16_t gpio_pin;
     rt_base_t level;

bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c

@@ -130,7 +130,7 @@ static rt_base_t ch32_pin_get(const char *name)
     return pin;
 }
 
-static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     GPIO_TypeDef *gpio_port;
     rt_uint16_t gpio_pin;
@@ -143,11 +143,11 @@ static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int ch32_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t ch32_pin_read(rt_device_t dev, rt_base_t pin)
 {
     GPIO_TypeDef *gpio_port;
     rt_uint16_t gpio_pin;
-    int value = PIN_LOW;
+    rt_int8_t value = PIN_LOW;
 
     if (PIN_PORT(pin) < PIN_STPORT_MAX)
     {
@@ -159,7 +159,7 @@ static int ch32_pin_read(rt_device_t dev, rt_base_t pin)
     return value;
 }
 
-static void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     GPIO_InitTypeDef GPIO_InitStruct;
 
@@ -225,8 +225,8 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit)
     return &pin_irq_map[mapindex];
 };
 
-static rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                                     rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -265,7 +265,7 @@ static rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
     rt_int32_t irqindex = -1;
@@ -297,7 +297,7 @@ static rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                     rt_uint32_t enabled)
+                                     rt_uint8_t enabled)
 {
     const struct pin_irq_map *irqmap;
     rt_base_t level;

bsp/wch/risc-v/Libraries/ch56x_drivers/ch56x_gpio.c

@@ -93,7 +93,7 @@ static struct gpio_px_regs *_gpio_px_regbase(rt_base_t pin)
         return RT_NULL;
 }
 
-static void gpio_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+static void gpio_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
 {
     volatile struct gpio_px_regs *px;
 
@@ -132,7 +132,7 @@ static void gpio_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mod
     }
 }
 
-static void gpio_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+static void gpio_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
 {
     volatile struct gpio_px_regs *px;
 
@@ -150,7 +150,7 @@ static void gpio_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t va
         BITS_SET(px->OUT, bitpos);
 }
 
-static int gpio_pin_read(struct rt_device *device, rt_base_t pin)
+static rt_int8_t gpio_pin_read(struct rt_device *device, rt_base_t pin)
 {
     volatile struct gpio_px_regs *px;
 
@@ -194,8 +194,8 @@ static rt_base_t gpio_pin_get(const char *name)
     return -1;
 }
 
-static rt_err_t gpio_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-                rt_uint32_t mode, void (*hdr)(void *args), void *args)
+static rt_err_t gpio_pin_attach_irq(struct rt_device *device, rt_base_t pin,
+                rt_uint8_t mode, void (*hdr)(void *args), void *args)
 {
     rt_base_t level;
 
@@ -243,7 +243,7 @@ static rt_err_t gpio_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     return RT_EOK;
 }
 
-static rt_err_t gpio_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t gpio_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_base_t level;
 
@@ -268,7 +268,7 @@ static rt_err_t gpio_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 }
 
 static rt_err_t gpio_pin_irq_enable(struct rt_device *device, rt_base_t pin,
-                                    rt_uint32_t enabled)
+                                    rt_uint8_t enabled)
 {
     volatile struct gpio_registers *gpio;
 

bsp/yichip/yc3121-pos/drivers/drv_gpio.c

@@ -80,7 +80,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
 };
 
-static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     /* Configure GPIO_InitStructure */
     if (mode == PIN_MODE_OUTPUT)
@@ -110,7 +110,7 @@ static void yc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     if (value)
     {
@@ -122,14 +122,14 @@ static void yc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     }
 }
 
-static int yc_pin_read(rt_device_t dev, rt_base_t pin)
+static rt_int8_t yc_pin_read(rt_device_t dev, rt_base_t pin)
 {
     return GPIO_IN(pin / 16) & (1 << (pin % 16)) ? 1 : 0;
 }
 
 static rt_err_t yc_pin_attach_irq(struct rt_device *device,
-                                  rt_int32_t pin,
-                                  rt_uint32_t mode,
+                                  rt_base_t pin,
+                                  rt_uint8_t mode,
                                   pin_callback_t cb,
                                   void *args)
 {
@@ -152,7 +152,7 @@ static rt_err_t yc_pin_attach_irq(struct rt_device *device,
     return RT_EOK;
 }
 
-static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_base_t pin)
 {
     rt_int32_t index = -1;
     rt_base_t level;
@@ -175,7 +175,7 @@ static rt_err_t yc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 
 static rt_err_t yc_pin_irq_enable(struct rt_device *device,
                                   rt_base_t pin,
-                                  rt_uint32_t enabled)
+                                  rt_uint8_t enabled)
 {
     rt_int32_t index;
     rt_base_t level = 0;

bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c

@@ -20,7 +20,7 @@
 #define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
 static XGpioPs Gpio; /* The driver instance for GPIO Device. */
 
-void xgpiops_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+void xgpiops_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
 {
     switch (mode)
     {
@@ -39,7 +39,7 @@ void xgpiops_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     }
 }
 
-void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
 {
     if (pin >= Gpio.MaxPinNum)
         return;
@@ -47,7 +47,7 @@ void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     XGpioPs_WritePin(&Gpio, pin, (value == PIN_HIGH)?1:0);
 }
 
-int xgpiops_pin_read(rt_device_t dev, rt_base_t pin)
+rt_int8_t xgpiops_pin_read(rt_device_t dev, rt_base_t pin)
 {
     if (pin >= Gpio.MaxPinNum)
         return 0;