i# This is a combination of 3 commits.

【修改】format

bsp/stm32/libraries/HAL_Drivers/drv_can.c

@@ -325,13 +325,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
                  * STD ID |     STID[10:3]  | STDID[2:0] |<-                21bit                  ->|
                  * EXT ID |    EXTID[28:21] | EXTID[20:13]    | EXTID[12:5]    | EXTID[4:0] IDE RTR 0|
                  * @note the 32bit STD ID must << 21 to fill CAN_FxR1[31:21] and EXT ID must << 3,
-                 *       -> but the id bit of struct rt_can_filter_item is 29, 
+                 *       -> but the id bit of struct rt_can_filter_item is 29,
                  *       -> so STD id << 18 and EXT id Don't need << 3, when get the high 16bit.
                  *       -> FilterIdHigh : (((STDid << 18) or (EXT id)) >> 13) & 0xFFFF,
-                 *       -> FilterIdLow:   ((STDid << 18) or (EXT id << 3)) & 0xFFFF. 
-                 * @note the mask bit of struct rt_can_filter_item is 32, 
-                 *       -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF  
-                 *       -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF  
+                 *       -> FilterIdLow:   ((STDid << 18) or (EXT id << 3)) & 0xFFFF.
+                 * @note the mask bit of struct rt_can_filter_item is 32,
+                 *       -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF
+                 *       -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF
                  */
                 if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDMASK)
                 {
@@ -341,14 +341,14 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
                 else if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDLIST)
                 {
                     /* same as CAN_FxR1 */
-                    mask_l_tail = (filter_cfg->items[i].ide << 2) | 
+                    mask_l_tail = (filter_cfg->items[i].ide << 2) |
                                    (filter_cfg->items[i].rtr << 1);
                 }
                 if (filter_cfg->items[i].ide == RT_CAN_STDID)
                 {
                     id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF;
-                    id_l = ((filter_cfg->items[i].id << 18) | 
-                            (filter_cfg->items[i].ide << 2) | 
+                    id_l = ((filter_cfg->items[i].id << 18) |
+                            (filter_cfg->items[i].ide << 2) |
                             (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
                     mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF;
                     mask_l = ((filter_cfg->items[i].mask << 21) | mask_l_tail) & 0xFFFF;
@@ -356,8 +356,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
                 else if (filter_cfg->items[i].ide == RT_CAN_EXTID)
                 {
                     id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF;
-                    id_l = ((filter_cfg->items[i].id << 3)   | 
-                            (filter_cfg->items[i].ide << 2)  | 
+                    id_l = ((filter_cfg->items[i].id << 3)   |
+                            (filter_cfg->items[i].ide << 2)  |
                             (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
                     mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF;
                     mask_l = ((filter_cfg->items[i].mask << 3) | mask_l_tail) & 0xFFFF;

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c

@@ -78,7 +78,7 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
         LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
         return -RT_EINVAL;
     }
-    
+
     if(addr % 32 != 0)
     {
         LOG_E("write addr must be 32-byte alignment");
@@ -171,7 +171,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
     {
         size_bank1 = 0;
         addr_bank2 = addr;
-        size_bank2 = size; 
+        size_bank2 = size;
     }
     else
     {
@@ -188,7 +188,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
     EraseInitStruct.TypeErase     = FLASH_TYPEERASE_SECTORS;
     EraseInitStruct.VoltageRange  = FLASH_VOLTAGE_RANGE_3;
     SCB_DisableDCache();
-    
+
     if(size_bank1)
     {
         EraseInitStruct.Sector    = (addr_bank1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE;

bsp/stm32/libraries/HAL_Drivers/drv_gpio.c

@@ -117,7 +117,7 @@ static const struct pin_irq_map pin_irq_map[] =
     {GPIO_PIN_12, EXTI15_10_IRQn},
     {GPIO_PIN_13, EXTI15_10_IRQn},
     {GPIO_PIN_14, EXTI15_10_IRQn},
-    {GPIO_PIN_15, EXTI15_10_IRQn},   
+    {GPIO_PIN_15, EXTI15_10_IRQn},
 #else
     {GPIO_PIN_0, EXTI0_IRQn},
     {GPIO_PIN_1, EXTI1_IRQn},

bsp/stm32/libraries/HAL_Drivers/drv_spi.c

@@ -263,7 +263,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
         HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
         HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
     }
-    
+
     if(spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG || spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
     {
         HAL_NVIC_SetPriority(spi_drv->config->irq_type, 2, 0);

bsp/stm32/libraries/HAL_Drivers/drv_usart.c

@@ -369,7 +369,7 @@ static void uart_isr(struct rt_serial_device *serial)
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
         {
             __HAL_UART_CLEAR_PEFLAG(&uart->handle);
-        }              
+        }
 #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
     && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
     && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
@@ -378,13 +378,13 @@ static void uart_isr(struct rt_serial_device *serial)
         {
             UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
         }
-#else        
+#else
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
         {
             UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
-        }                
+        }
+#endif
 #endif
-#endif        
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
         {
             UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);

bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/HAL_Drivers/drv_usart_v2.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h

@@ -2,17 +2,17 @@
   ******************************************************************************
   * @file    stm32f3xx.h
   * @author  MCD Application Team
-  * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
-  *            
+  * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.
+  *
   *          The file is the unique include file that the application programmer
   *          is using in the C source code, usually in main.c. This file contains:
   *           - Configuration section that allows to select:
   *              - The STM32F3xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
   *                "#define USE_HAL_DRIVER"
-  *  
+  *
   ******************************************************************************
   * @attention
   *
@@ -34,14 +34,14 @@
 /** @addtogroup stm32f3xx
   * @{
   */
-    
+
 #ifndef __STM32F3xx_H
 #define __STM32F3xx_H
 
 #ifdef __cplusplus
  extern "C" {
 #endif /* __cplusplus */
-   
+
 /** @addtogroup Library_configuration_section
   * @{
   */
@@ -54,7 +54,7 @@
 #endif /* STM32F3 */
 
 /* Uncomment the line below according to the target STM32 device used in your
-   application 
+   application
   */
 
 #if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
@@ -62,7 +62,7 @@
     !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
     !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
     !defined (STM32F373xC) && !defined (STM32F378xx)
-    
+
   /* #define STM32F301x8 */   /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
                                    STM32F301R6 and STM32F301R8 Devices */
   /* #define STM32F302x8 */   /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
@@ -71,7 +71,7 @@
                                    STM32F302VB and STM32F302VC Devices */
   /* #define STM32F302xE */   /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
                                    STM32F302VD and STM32F302ZD Devices */
-  /* #define STM32F303x8 */   /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, 
+  /* #define STM32F303x8 */   /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
                                    STM32F303R6 and STM32F303R8 Devices */
   /* #define STM32F303xC */   /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
                                    STM32F303VB and STM32F303VC Devices */
@@ -89,15 +89,15 @@
   /* #define STM32F378xx */   /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
   /* #define STM32F398xx */   /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
 #endif
-   
+
 /*  Tip: To avoid modifying this file each time you need to switch between these
         devices, you can define the device in your toolchain compiler preprocessor.
   */
 #if !defined  (USE_HAL_DRIVER)
 /**
  * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
    */
   /*#define USE_HAL_DRIVER */
 #endif /* USE_HAL_DRIVER */
@@ -160,21 +160,21 @@
 
 /** @addtogroup Exported_types
   * @{
-  */ 
-typedef enum 
+  */
+typedef enum
 {
-  RESET = 0U, 
+  RESET = 0U,
   SET = !RESET
 } FlagStatus, ITStatus;
 
-typedef enum 
+typedef enum
 {
-  DISABLE = 0U, 
+  DISABLE = 0U,
   ENABLE = !DISABLE
 } FunctionalState;
 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
 
-typedef enum 
+typedef enum
 {
   SUCCESS = 0U,
   ERROR = !SUCCESS
@@ -202,7 +202,7 @@ typedef enum
 
 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
 
 
 /**
@@ -225,7 +225,7 @@ typedef enum
 /**
   * @}
   */
-  
+
 
 
 

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h

@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    system_stm32f3xx.h
   * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
   ******************************************************************************
   * @attention
   *
@@ -23,8 +23,8 @@
 
 /** @addtogroup stm32f3xx_system
   * @{
-  */  
-  
+  */
+
 /**
   * @brief Define to prevent recursive inclusion
   */
@@ -33,7 +33,7 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 /** @addtogroup STM32F3xx_System_Includes
   * @{
@@ -83,7 +83,7 @@ extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
 /** @addtogroup STM32F3xx_System_Exported_Functions
   * @{
   */
-  
+
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
 /**
@@ -99,8 +99,8 @@ extern void SystemCoreClockUpdate(void);
 /**
   * @}
   */
-  
+
 /**
   * @}
-  */  
+  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c

@@ -6,7 +6,7 @@
   *
   * 1. This file provides two functions and one global variable to be called from
   *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
+  *      - SystemInit(): This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f3xx.s" file.
   *
@@ -84,7 +84,7 @@
 /** @addtogroup STM32F3xx_System_Private_Defines
   * @{
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSE_VALUE */
@@ -139,7 +139,7 @@
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
          Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
+               call the 2 first functions listed above, since SystemCoreClock variable is
                updated automatically.
   */
 uint32_t SystemCoreClock = 8000000;
@@ -250,7 +250,7 @@ void SystemCoreClockUpdate (void)
         /* HSI oscillator clock selected as PREDIV1 clock entry */
         SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
       }
-#else      
+#else
       if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
       {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/cmsis_armcc.h

@@ -58,9 +58,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   static __forceinline
-#endif           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __declspec(noreturn)
 #endif
@@ -443,7 +443,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
                    __schedule_barrier();\
                 } while (0U)
 
-                  
+
 /**
   \brief   Reverse byte order (32 bit)
   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/cmsis_armclang.h

@@ -43,9 +43,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static __inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -570,7 +570,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -616,7 +616,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/cmsis_gcc.h

@@ -46,9 +46,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -585,7 +585,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -630,7 +630,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -767,7 +767,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
+#if __has_builtin(__builtin_arm_get_fpscr)
 // Re-enable using built-in when GCC has been fixed
 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/core_cm0.h

@@ -61,7 +61,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/core_cm0plus.h

@@ -61,7 +61,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM0+ definitions */
 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/core_cm1.h

@@ -61,7 +61,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM1 definitions */
 #define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/core_cm23.h

@@ -1289,7 +1289,7 @@ typedef struct
 
 /* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
 
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
 #define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
 
 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -1304,11 +1304,11 @@ typedef struct
 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
+#else
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
 #endif
 
-	
+
 /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 /* The following MACROS handle generation of the register offset and byte masks */
 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/core_cm33.h

@@ -2159,7 +2159,7 @@ typedef struct
 
 /* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
 
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
 #define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
 
 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -2174,7 +2174,7 @@ typedef struct
 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
+#else
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
 #endif
 

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/mpu_armv7.h

@@ -21,13 +21,13 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #if   defined ( __ICCARM__ )
   #pragma system_include         /* treat file as system include file for MISRA check */
 #elif defined (__clang__)
   #pragma clang system_header    /* treat file as system include file */
 #endif
- 
+
 #ifndef ARM_MPU_ARMV7_H
 #define ARM_MPU_ARMV7_H
 
@@ -79,12 +79,12 @@
 
 /**
 * MPU Memory Access Attributes
-* 
+*
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
 * \param IsShareable       Region is shareable between multiple bus masters.
 * \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/  
+*/
 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
   ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
    (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
@@ -93,7 +93,7 @@
 
 /**
 * MPU Region Attribute and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
@@ -104,10 +104,10 @@
   ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
    (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
    (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
-  
+
 /**
 * MPU Region Attribute and Size Register Value
-* 
+*
 * \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
 * \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
 * \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -116,7 +116,7 @@
 * \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
 * \param SubRegionDisable  Sub-region disable field.
 * \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/                         
+*/
 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
   ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
 
@@ -126,7 +126,7 @@
 *  - Shareable
 *  - Non-cacheable
 *  - Non-bufferable
-*/ 
+*/
 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
 
 /**
@@ -137,7 +137,7 @@
 *  - Bufferable (if shareable) or non-bufferable (if non-shareable)
 *
 * \param IsShareable Configures the device memory as shareable or non-shareable.
-*/ 
+*/
 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
 
 /**
@@ -150,7 +150,7 @@
 * \param OuterCp Configures the outer cache policy.
 * \param InnerCp Configures the inner cache policy.
 * \param IsShareable Configures the memory as shareable or non-shareable.
-*/ 
+*/
 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
 
 /**
@@ -181,7 +181,7 @@ typedef struct {
   uint32_t RBAR; //!< The region base address register value (RBAR)
   uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
@@ -219,7 +219,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 /** Configure an MPU region.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 {
   MPU->RBAR = rbar;
@@ -230,7 +230,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rsar Value for RSAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
 {
   MPU->RNR = rnr;
@@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
-  for (i = 0U; i < len; ++i) 
+  for (i = 0U; i < len; ++i)
   {
     dst[i] = src[i];
   }
@@ -256,7 +256,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   while (cnt > MPU_TYPE_RALIASES) {

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/mpu_armv8.h

@@ -108,7 +108,7 @@ typedef struct {
   uint32_t RBAR;                   /*!< Region Base Address Register value */
   uint32_t RLAR;                   /*!< Region Limit Address Register value */
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
@@ -171,11 +171,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at
   const uint8_t reg = idx / 4U;
   const uint32_t pos = ((idx % 4U) * 8U);
   const uint32_t mask = 0xFFU << pos;
-  
+
   if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
     return; // invalid index
   }
-  
+
   mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
 }
 
@@ -222,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{  
+{
   ARM_MPU_ClrRegionEx(MPU_NS, rnr);
 }
 #endif
@@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
   mpu->RNR = rnr;
@@ -244,7 +244,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
   ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
@@ -255,10 +255,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
 }
 #endif
 
@@ -270,7 +270,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
-  for (i = 0U; i < len; ++i) 
+  for (i = 0U; i < len; ++i)
   {
     dst[i] = src[i];
   }
@@ -282,7 +282,7 @@ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRI
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   if (cnt == 1U) {
@@ -291,7 +291,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
   } else {
     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-    
+
     mpu->RNR = rnrBase;
     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
@@ -302,7 +302,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
       rnrBase += MPU_TYPE_RALIASES;
       mpu->RNR = rnrBase;
     }
-    
+
     orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
   }
 }
@@ -312,7 +312,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   ARM_MPU_LoadEx(MPU, rnr, table, cnt);
 }
@@ -323,7 +323,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
 }

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/Include/tz_context.h

@@ -30,41 +30,41 @@
 
 #ifndef TZ_CONTEXT_H
 #define TZ_CONTEXT_H
- 
+
 #include <stdint.h>
- 
+
 #ifndef TZ_MODULEID_T
 #define TZ_MODULEID_T
 /// \details Data type that identifies secure software modules called by a process.
 typedef uint32_t TZ_ModuleId_t;
 #endif
- 
+
 /// \details TZ Memory ID identifies an allocated memory slot.
 typedef uint32_t TZ_MemoryId_t;
-  
+
 /// Initialize secure context memory system
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_InitContextSystem_S (void);
- 
+
 /// Allocate context memory for calling secure software modules in TrustZone
 /// \param[in]  module   identifies software modules called from non-secure mode
 /// \return value != 0 id TrustZone memory slot identifier
 /// \return value 0    no memory available or internal error
 TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
- 
+
 /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
- 
+
 /// Load secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
- 
+
 /// Store secure context (called on RTOS thread context switch)
 /// \param[in]  id  TrustZone memory slot identifier
 /// \return execution status (1: success, 0: error)
 uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
- 
+
 #endif  // TZ_CONTEXT_H

bsp/stm32/libraries/STM32F3xx_HAL/CMSIS/RTOS/Template/cmsis_os.h

@@ -21,7 +21,7 @@
  * Version 1.02
  *    Control functions for short timeouts in microsecond resolution:
  *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
- *    Removed: osSignalGet 
+ *    Removed: osSignalGet
  *----------------------------------------------------------------------------
  *
  * Copyright (c) 2013-2017 ARM LIMITED
@@ -40,20 +40,20 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *---------------------------------------------------------------------------*/
- 
- 
+
+
 #ifndef _CMSIS_OS_H
 #define _CMSIS_OS_H
- 
+
 /// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
 #define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
- 
+
 /// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
-#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
- 
+#define osCMSIS_KERNEL    0x10000      ///< RTOS identification and version (main [31:16] .sub [15:0])
+
 /// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
 #define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
- 
+
 /// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
 #define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
 #define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
@@ -63,18 +63,18 @@
 #define osFeature_Semaphore    30      ///< maximum count for \ref osSemaphoreCreate function
 #define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
 #define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
- 
+
 #include <stdint.h>
 #include <stddef.h>
- 
+
 #ifdef  __cplusplus
 extern "C"
 {
 #endif
- 
- 
+
+
 // ==== Enumeration, structures, defines ====
- 
+
 /// Priority used for thread control.
 /// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
 typedef enum  {
@@ -87,11 +87,11 @@ typedef enum  {
   osPriorityRealtime      = +3,          ///< priority: realtime (highest)
   osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
 } osPriority;
- 
+
 /// Timeout value.
 /// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
 #define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
- 
+
 /// Status code values returned by CMSIS-RTOS functions.
 /// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
 typedef enum  {
@@ -111,54 +111,54 @@ typedef enum  {
   osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
   os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
 } osStatus;
- 
- 
+
+
 /// Timer type value for the timer definition.
 /// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
 typedef enum  {
   osTimerOnce             =     0,       ///< one-shot timer
   osTimerPeriodic         =     1        ///< repeating timer
 } os_timer_type;
- 
+
 /// Entry point of a thread.
 /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
 typedef void (*os_pthread) (void const *argument);
- 
+
 /// Entry point of a timer call back function.
 /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
 typedef void (*os_ptimer) (void const *argument);
- 
+
 // >>> the following data type definitions may shall adapted towards a specific RTOS
- 
+
 /// Thread ID identifies the thread (pointer to a thread control block).
 /// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_thread_cb *osThreadId;
- 
+
 /// Timer ID identifies the timer (pointer to a timer control block).
 /// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_timer_cb *osTimerId;
- 
+
 /// Mutex ID identifies the mutex (pointer to a mutex control block).
 /// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_mutex_cb *osMutexId;
- 
+
 /// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
 /// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_semaphore_cb *osSemaphoreId;
- 
+
 /// Pool ID identifies the memory pool (pointer to a memory pool control block).
 /// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_pool_cb *osPoolId;
- 
+
 /// Message ID identifies the message queue (pointer to a message queue control block).
 /// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_messageQ_cb *osMessageQId;
- 
+
 /// Mail ID identifies the mail queue (pointer to a mail queue control block).
 /// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
 typedef struct os_mailQ_cb *osMailQId;
- 
- 
+
+
 /// Thread Definition structure contains startup information of a thread.
 /// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_thread_def  {
@@ -167,25 +167,25 @@ typedef struct os_thread_def  {
   uint32_t               instances;    ///< maximum number of instances of that thread function
   uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
 } osThreadDef_t;
- 
+
 /// Timer Definition structure contains timer parameters.
 /// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_timer_def  {
   os_ptimer                 ptimer;    ///< start address of a timer function
 } osTimerDef_t;
- 
+
 /// Mutex Definition structure contains setup information for a mutex.
 /// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_mutex_def  {
   uint32_t                   dummy;    ///< dummy value.
 } osMutexDef_t;
- 
+
 /// Semaphore Definition structure contains setup information for a semaphore.
 /// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_semaphore_def  {
   uint32_t                   dummy;    ///< dummy value.
 } osSemaphoreDef_t;
- 
+
 /// Definition structure for memory block allocation.
 /// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_pool_def  {
@@ -193,7 +193,7 @@ typedef struct os_pool_def  {
   uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< pointer to memory for pool
 } osPoolDef_t;
- 
+
 /// Definition structure for message queue.
 /// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_messageQ_def  {
@@ -201,7 +201,7 @@ typedef struct os_messageQ_def  {
   uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< memory array for messages
 } osMessageQDef_t;
- 
+
 /// Definition structure for mail queue.
 /// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
 typedef struct os_mailQ_def  {
@@ -209,7 +209,7 @@ typedef struct os_mailQ_def  {
   uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< memory array for mail
 } osMailQDef_t;
- 
+
 /// Event structure contains detailed information about an event.
 /// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
 ///       However the struct may be extended at the end.
@@ -225,45 +225,45 @@ typedef struct  {
     osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
   } def;                               ///< event definition
 } osEvent;
- 
- 
+
+
 //  ==== Kernel Control Functions ====
- 
+
 /// Initialize the RTOS Kernel for creating objects.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
 osStatus osKernelInitialize (void);
- 
+
 /// Start the RTOS Kernel.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
 osStatus osKernelStart (void);
- 
+
 /// Check if the RTOS kernel is already started.
 /// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
 /// \return 0 RTOS is not started, 1 RTOS is started.
 int32_t osKernelRunning(void);
- 
+
 #if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
- 
-/// Get the RTOS kernel system timer counter 
+
+/// Get the RTOS kernel system timer counter
 /// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
-/// \return RTOS kernel system timer as 32-bit value 
+/// \return RTOS kernel system timer as 32-bit value
 uint32_t osKernelSysTick (void);
- 
+
 /// The RTOS kernel system timer frequency in Hz
 /// \note Reflects the system timer setting and is typically defined in a configuration file.
 #define osKernelSysTickFrequency 100000000
- 
+
 /// Convert a microseconds value to a RTOS kernel system timer value.
 /// \param         microsec     time value in microseconds.
 /// \return time value normalized to the \ref osKernelSysTickFrequency
 #define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
- 
+
 #endif    // System Timer available
- 
+
 //  ==== Thread Management ====
- 
+
 /// Create a Thread Definition with function, priority, and stack requirements.
 /// \param         name         name of the thread function.
 /// \param         priority     initial priority of the thread function.
@@ -279,69 +279,69 @@ extern const osThreadDef_t os_thread_def_##name
 const osThreadDef_t os_thread_def_##name = \
 { (name), (priority), (instances), (stacksz)  }
 #endif
- 
+
 /// Access a Thread definition.
 /// \param         name          name of the thread definition object.
 /// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osThread(name)  \
 &os_thread_def_##name
- 
+
 /// Create a thread and add it to Active Threads and set it to state READY.
 /// \param[in]     thread_def    thread definition referenced with \ref osThread.
 /// \param[in]     argument      pointer that is passed to the thread function as start argument.
 /// \return thread ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
 osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
- 
+
 /// Return the thread ID of the current running thread.
 /// \return thread ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
 osThreadId osThreadGetId (void);
- 
+
 /// Terminate execution of a thread and remove it from Active Threads.
 /// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
 osStatus osThreadTerminate (osThreadId thread_id);
- 
+
 /// Pass control to next thread that is in state \b READY.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
 osStatus osThreadYield (void);
- 
+
 /// Change priority of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     priority      new priority value for the thread function.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
 osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
- 
+
 /// Get current priority of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \return current priority value of the thread function.
 /// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
 osPriority osThreadGetPriority (osThreadId thread_id);
- 
- 
+
+
 //  ==== Generic Wait Functions ====
- 
+
 /// Wait for Timeout (Time Delay).
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value
 /// \return status code that indicates the execution status of the function.
 osStatus osDelay (uint32_t millisec);
- 
+
 #if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
- 
+
 /// Wait for Signal, Message, Mail, or Timeout.
 /// \param[in] millisec          \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return event that contains signal, message, or mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
 osEvent osWait (uint32_t millisec);
- 
+
 #endif  // Generic Wait available
- 
- 
+
+
 //  ==== Timer Management Functions ====
 /// Define a Timer object.
 /// \param         name          name of the timer object.
@@ -356,14 +356,14 @@ extern const osTimerDef_t os_timer_def_##name
 const osTimerDef_t os_timer_def_##name = \
 { (function) }
 #endif
- 
+
 /// Access a Timer definition.
 /// \param         name          name of the timer object.
 /// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osTimer(name) \
 &os_timer_def_##name
- 
+
 /// Create a timer.
 /// \param[in]     timer_def     timer object referenced with \ref osTimer.
 /// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
@@ -371,53 +371,53 @@ const osTimerDef_t os_timer_def_##name = \
 /// \return timer ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
 osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
- 
+
 /// Start or restart a timer.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
 osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
- 
+
 /// Stop the timer.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
 osStatus osTimerStop (osTimerId timer_id);
- 
+
 /// Delete a timer that was created by \ref osTimerCreate.
 /// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
 osStatus osTimerDelete (osTimerId timer_id);
- 
- 
+
+
 //  ==== Signal Management ====
- 
+
 /// Set the specified Signal Flags of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     signals       specifies the signal flags of the thread that should be set.
 /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
 int32_t osSignalSet (osThreadId thread_id, int32_t signals);
- 
+
 /// Clear the specified Signal Flags of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
 /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
 /// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
 int32_t osSignalClear (osThreadId thread_id, int32_t signals);
- 
+
 /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
 /// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return event flag information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
 osEvent osSignalWait (int32_t signals, uint32_t millisec);
- 
- 
+
+
 //  ==== Mutex Management ====
- 
+
 /// Define a Mutex.
 /// \param         name          name of the mutex object.
 /// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
@@ -429,44 +429,44 @@ extern const osMutexDef_t os_mutex_def_##name
 #define osMutexDef(name)  \
 const osMutexDef_t os_mutex_def_##name = { 0 }
 #endif
- 
+
 /// Access a Mutex definition.
 /// \param         name          name of the mutex object.
 /// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMutex(name)  \
 &os_mutex_def_##name
- 
+
 /// Create and Initialize a Mutex object.
 /// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
 /// \return mutex ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
 osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
- 
+
 /// Wait until a Mutex becomes available.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
 osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
- 
+
 /// Release a Mutex that was obtained by \ref osMutexWait.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
 osStatus osMutexRelease (osMutexId mutex_id);
- 
+
 /// Delete a Mutex that was created by \ref osMutexCreate.
 /// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
 osStatus osMutexDelete (osMutexId mutex_id);
- 
- 
+
+
 //  ==== Semaphore Management Functions ====
- 
+
 #if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
- 
+
 /// Define a Semaphore object.
 /// \param         name          name of the semaphore object.
 /// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
@@ -478,47 +478,47 @@ extern const osSemaphoreDef_t os_semaphore_def_##name
 #define osSemaphoreDef(name)  \
 const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 #endif
- 
+
 /// Access a Semaphore definition.
 /// \param         name          name of the semaphore object.
 /// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osSemaphore(name)  \
 &os_semaphore_def_##name
- 
+
 /// Create and Initialize a Semaphore object used for managing resources.
 /// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
 /// \param[in]     count         number of available resources.
 /// \return semaphore ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
 osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
- 
+
 /// Wait until a Semaphore token becomes available.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return number of available tokens, or -1 in case of incorrect parameters.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
 int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
- 
+
 /// Release a Semaphore token.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
 osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
- 
+
 /// Delete a Semaphore that was created by \ref osSemaphoreCreate.
 /// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
 osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
- 
+
 #endif     // Semaphore available
- 
- 
+
+
 //  ==== Memory Pool Management Functions ====
- 
+
 #if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
- 
+
 /// \brief Define a Memory Pool.
 /// \param         name          name of the memory pool.
 /// \param         no            maximum number of blocks (objects) in the memory pool.
@@ -533,46 +533,46 @@ extern const osPoolDef_t os_pool_def_##name
 const osPoolDef_t os_pool_def_##name = \
 { (no), sizeof(type), NULL }
 #endif
- 
+
 /// \brief Access a Memory Pool definition.
 /// \param         name          name of the memory pool
 /// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osPool(name) \
 &os_pool_def_##name
- 
+
 /// Create and Initialize a memory pool.
 /// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
 /// \return memory pool ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
 osPoolId osPoolCreate (const osPoolDef_t *pool_def);
- 
+
 /// Allocate a memory block from a memory pool.
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \return address of the allocated memory block or NULL in case of no memory available.
 /// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
 void *osPoolAlloc (osPoolId pool_id);
- 
+
 /// Allocate a memory block from a memory pool and set memory block to zero.
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \return address of the allocated memory block or NULL in case of no memory available.
 /// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
 void *osPoolCAlloc (osPoolId pool_id);
- 
+
 /// Return an allocated memory block back to a specific memory pool.
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
 osStatus osPoolFree (osPoolId pool_id, void *block);
- 
+
 #endif   // Memory Pool Management available
- 
- 
+
+
 //  ==== Message Queue Management Functions ====
- 
+
 #if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
- 
+
 /// \brief Create a Message Queue Definition.
 /// \param         name          name of the queue.
 /// \param         queue_sz      maximum number of messages in the queue.
@@ -587,21 +587,21 @@ extern const osMessageQDef_t os_messageQ_def_##name
 const osMessageQDef_t os_messageQ_def_##name = \
 { (queue_sz), sizeof (type)  }
 #endif
- 
+
 /// \brief Access a Message Queue Definition.
 /// \param         name          name of the queue
 /// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMessageQ(name) \
 &os_messageQ_def_##name
- 
+
 /// Create and Initialize a Message Queue.
 /// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
 /// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
 /// \return message queue ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
 osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
- 
+
 /// Put a Message to a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
 /// \param[in]     info          message information.
@@ -609,21 +609,21 @@ osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId threa
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
 osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
- 
+
 /// Get a Message or Wait for a Message from a Queue.
 /// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
 /// \return event information that includes status code.
 /// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
 osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
- 
+
 #endif     // Message Queues available
- 
- 
+
+
 //  ==== Mail Queue Management Functions ====
- 
+
 #if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
- 
+
 /// \brief Create a Mail Queue Definition.
 /// \param         name          name of the queue
 /// \param         queue_sz      maximum number of messages in queue
@@ -638,61 +638,61 @@ extern const osMailQDef_t os_mailQ_def_##name
 const osMailQDef_t os_mailQ_def_##name =  \
 { (queue_sz), sizeof (type) }
 #endif
- 
+
 /// \brief Access a Mail Queue Definition.
 /// \param         name          name of the queue
 /// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMailQ(name)  \
 &os_mailQ_def_##name
- 
+
 /// Create and Initialize mail queue.
 /// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
 /// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
 /// \return mail queue ID for reference by other functions or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
 osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
- 
+
 /// Allocate a memory block from a mail.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
- 
+
 /// Allocate a memory block from a mail and set memory block to zero.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return pointer to memory block that can be filled with mail or NULL in case of error.
 /// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
 void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
- 
+
 /// Put a mail to a queue.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
 osStatus osMailPut (osMailQId queue_id, void *mail);
- 
+
 /// Get a mail from a queue.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     millisec      \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
 /// \return event that contains mail information or error code.
 /// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
 osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
- 
+
 /// Free a memory block from a mail.
 /// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
 /// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
 osStatus osMailFree (osMailQId queue_id, void *mail);
- 
+
 #endif  // Mail Queues available
- 
- 
+
+
 #ifdef  __cplusplus
 }
 #endif
- 
+
 #endif  // _CMSIS_OS_H

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -1022,7 +1022,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
   * @{
   */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/Legacy/stm32f3xx_hal_can_legacy.h

@@ -45,10 +45,10 @@
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup CAN_Exported_Types CAN Exported Types
   * @{
-  */  
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+  */
+/**
+  * @brief  HAL State structures definition
+  */
 typedef enum
 {
   HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
@@ -66,19 +66,19 @@ typedef enum
 
 }HAL_CAN_StateTypeDef;
 
-/** 
+/**
   * @brief  CAN init structure definition
   */
 typedef struct
 {
-  uint32_t Prescaler;  /*!< Specifies the length of a time quantum. 
+  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
-  
+
   uint32_t Mode;       /*!< Specifies the CAN operating mode.
                             This parameter can be a value of @ref CAN_operating_mode */
 
-  uint32_t SJW;        /*!< Specifies the maximum number of time quanta 
-                            the CAN hardware is allowed to lengthen or 
+  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
+                            the CAN hardware is allowed to lengthen or
                             shorten a bit to perform resynchronization.
                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
 
@@ -87,14 +87,14 @@ typedef struct
 
   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-  
+
   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
                             This parameter can be set to ENABLE or DISABLE. */
-  
+
   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
                             This parameter can be set to ENABLE or DISABLE. */
 
-  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode. 
+  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
                             This parameter can be set to ENABLE or DISABLE. */
 
   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
@@ -107,33 +107,33 @@ typedef struct
                             This parameter can be set to ENABLE or DISABLE. */
 }CAN_InitTypeDef;
 
-/** 
+/**
   * @brief  CAN filter configuration structure definition
   */
 typedef struct
 {
   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
                                        configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
-                                              
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
                                        configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
                                        according to the mode (MSBs for a 32-bit configuration,
                                        first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
                                        according to the mode (LSBs for a 32-bit configuration,
                                        second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
 
   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
                                        This parameter can be a value of @ref CAN_filter_FIFO */
-  
-  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized. 
+
+  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
 
   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
@@ -144,24 +144,24 @@ typedef struct
 
   uint32_t FilterActivation;      /*!< Enable or disable the filter.
                                        This parameter can be set to ENABLE or DISABLE. */
-                                       
+
   uint32_t BankNumber;            /*!< Select the start slave bank filter
                                        F3 devices don't support CAN2 interface (Slave). Therefore this parameter
-                                       is meaningless but it has been kept for compatibility accross STM32 families */ 
-  
+                                       is meaningless but it has been kept for compatibility accross STM32 families */
+
 }CAN_FilterConfTypeDef;
 
-/** 
-  * @brief  CAN Tx message structure definition  
+/**
+  * @brief  CAN Tx message structure definition
   */
 typedef struct
 {
   uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 
-                        
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
   uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 
-                        
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
                           This parameter can be a value of @ref CAN_identifier_type */
 
@@ -171,21 +171,21 @@ typedef struct
   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
                           This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 
-  uint8_t Data[8];   /*!< Contains the data to be transmitted. 
+  uint8_t Data[8];   /*!< Contains the data to be transmitted.
                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-   
+
 }CanTxMsgTypeDef;
 
-/** 
-  * @brief  CAN Rx message structure definition  
+/**
+  * @brief  CAN Rx message structure definition
   */
 typedef struct
 {
   uint32_t StdId;       /*!< Specifies the standard identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
 
   uint32_t ExtId;       /*!< Specifies the extended identifier.
-                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
 
   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
                              This parameter can be a value of @ref CAN_identifier_type */
@@ -196,26 +196,26 @@ typedef struct
   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
                              This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
 
-  uint8_t Data[8];      /*!< Contains the data to be received. 
+  uint8_t Data[8];      /*!< Contains the data to be received.
                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
 
   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-                        
-  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number. 
+
+  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-                       
+
 }CanRxMsgTypeDef;
 
-/** 
-  * @brief  CAN handle Structure definition  
-  */ 
+/**
+  * @brief  CAN handle Structure definition
+  */
 typedef struct
 {
   CAN_TypeDef                 *Instance;  /*!< Register base address          */
-  
+
   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
-  
+
   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
 
   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure for RX FIFO0 msg */
@@ -223,12 +223,12 @@ typedef struct
   CanRxMsgTypeDef*            pRx1Msg;    /*!< Pointer to reception structure for RX FIFO1 msg */
 
   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
-  
+
   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
-  
-  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 
+
+  __IO uint32_t               ErrorCode;  /*!< CAN Error code
                                                This parameter can be a value of @ref CAN_Error_Code */
-  
+
 }CAN_HandleTypeDef;
 /**
   * @}
@@ -244,7 +244,7 @@ typedef struct
   * @{
   */
 #define HAL_CAN_ERROR_NONE          (0x00000000U)  /*!< No error             */
-#define HAL_CAN_ERROR_EWG           (0x00000001U)  /*!< EWG error            */   
+#define HAL_CAN_ERROR_EWG           (0x00000001U)  /*!< EWG error            */
 #define HAL_CAN_ERROR_EPV           (0x00000002U)  /*!< EPV error            */
 #define HAL_CAN_ERROR_BOF           (0x00000004U)  /*!< BOF error            */
 #define HAL_CAN_ERROR_STF           (0x00000008U)  /*!< Stuff error          */
@@ -389,7 +389,7 @@ typedef struct
   */
 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
    and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
    CAN_GetFlagStatus() function.  */
 
 /* Transmit Flags */
@@ -416,7 +416,7 @@ typedef struct
 #define CAN_FLAG_ERRI              (0x00000102U)  /*!< Error flag                      */
 #define CAN_FLAG_WKU               (0x00000103U)  /*!< Wake up flag                    */
 #define CAN_FLAG_SLAKI             (0x00000104U)  /*!< Sleep acknowledge flag          */
-/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. 
+/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
          In this case the SLAK bit can be polled.*/
 
 /* Error Flags */
@@ -428,10 +428,10 @@ typedef struct
   * @}
   */
 
-  
+
 /** @defgroup CAN_interrupts CAN Interrupts
   * @{
-  */ 
+  */
 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
 
 /* Receive Interrupts */
@@ -459,7 +459,7 @@ typedef struct
 
 /** @defgroup CAN_Mailboxes CAN Mailboxes
 * @{
-*/   
+*/
 /* Mailboxes definition */
 #define CAN_TXMAILBOX_0   ((uint8_t)0x00U)
 #define CAN_TXMAILBOX_1   ((uint8_t)0x01U)
@@ -604,7 +604,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
 
 /**
   * @brief  Cancel a transmit request.
@@ -620,30 +620,30 @@ typedef struct
 /**
   * @brief  Enable or disables the DBG Freeze for CAN.
   * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __NEWSTATE__ new state of the CAN peripheral. 
+  * @param  __NEWSTATE__ new state of the CAN peripheral.
   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
-  *         during debug. Reception FIFOs can still be accessed/controlled normally) 
+  *         during debug. Reception FIFOs can still be accessed/controlled normally)
   *         or DISABLE (CAN is working during debug).
   * @retval None
   */
 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
 
 /**
  * @}
- */  
- 
-/* Exported functions --------------------------------------------------------*/  
+ */
+
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
   * @{
   */
-  
-/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  * @{
  */
-  
-/* Initialization and de-initialization functions *****************************/ 
+
+/* Initialization and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
@@ -651,10 +651,10 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
 /**
  * @}
- */ 
- 
+ */
+
 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    I/O operation functions 
+ *  @brief    I/O operation functions
  * @{
  */
 /* IO operation functions *****************************************************/
@@ -670,10 +670,10 @@ void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
 /**
  * @}
- */ 
- 
+ */
+
 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions 
+ *  @brief   CAN Peripheral State functions
  * @{
  */
 /* Peripheral State and Error functions ***************************************/
@@ -681,11 +681,11 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 /**
  * @}
- */ 
- 
+ */
+
 /**
  * @}
- */ 
+ */
 
 /* Private types -------------------------------------------------------------*/
 /** @defgroup CAN_Private_Types CAN Private Types
@@ -703,7 +703,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup CAN_Private_Constants CAN Private Constants

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h

@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    stm32f3xx_hal.h
   * @author  MCD Application Team
-  * @brief   This file contains all the functions prototypes for the HAL 
+  * @brief   This file contains all the functions prototypes for the HAL
   *          module driver.
   ******************************************************************************
   * @attention
@@ -16,7 +16,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_H
@@ -35,7 +35,7 @@
 
 /** @addtogroup HAL
   * @{
-  */ 
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /** @addtogroup HAL_Private_Macros
@@ -114,7 +114,7 @@ typedef enum
 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
                                                                          1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
 #if defined(SYSCFG_CFGR3_DMA_RMP)
-#if !defined(HAL_REMAP_CFGR3_MASK) 
+#if !defined(HAL_REMAP_CFGR3_MASK)
 #define HAL_REMAP_CFGR3_MASK                 (0x01000000U)
 #endif
 
@@ -200,7 +200,7 @@ typedef enum
                                                                         0: No remap
                                                                         1: Remap (TIM1_TRG3 = TIM17_OC) */
 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
-#if !defined(HAL_REMAP_CFGR3_MASK) 
+#if !defined(HAL_REMAP_CFGR3_MASK)
 #define HAL_REMAP_CFGR3_MASK               (0x01000000U)
 #endif
 #define HAL_REMAPTRIGGER_DAC1_TRIG3        (0x01010000U)  /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
@@ -334,7 +334,7 @@ typedef enum
   */
 
 /** @brief  Fast-mode Plus driving capability on a specific GPIO
-  */  
+  */
 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
 #define SYSCFG_FASTMODEPLUS_PB6    ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP)  /*!< Enable Fast-mode Plus on PB6  */
 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
@@ -387,7 +387,7 @@ typedef enum
 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__)        (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
 #else
 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__)        (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
-#endif /* SYSCFG_RCR_PAGE8 */      
+#endif /* SYSCFG_RCR_PAGE8 */
 /**
   * @}
   */
@@ -413,10 +413,10 @@ typedef enum
 /**
   * @}
   */
-  
+
 /**
  * @}
- */ 
+ */
 
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup HAL_Exported_Macros HAL Exported Macros
@@ -513,7 +513,7 @@ typedef enum
 /**
  * @}
  */
- 
+
 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
   * @{
   */
@@ -593,7 +593,7 @@ typedef enum
 /**
  * @}
  */
- 
+
 /** @defgroup Encoder_Mode Encoder Mode
   * @{
   */
@@ -629,7 +629,7 @@ typedef enum
 /**
  * @}
  */
- 
+
 /** @defgroup DMA_Remap_Enable DMA Remap Enable
   * @{
   */
@@ -661,7 +661,7 @@ typedef enum
 /**
  * @}
  */
- 
+
 /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
   * @{
   */
@@ -696,11 +696,11 @@ typedef enum
 /**
  * @}
  */
- 
+
 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap
   * @{
-  */ 
+  */
 /** @brief  USB interrupt remapping enable/disable macros
   */
 #define __HAL_REMAPINTERRUPT_USB_ENABLE()              (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
@@ -709,11 +709,11 @@ typedef enum
  * @}
  */
 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
- 
+
 #if defined(SYSCFG_CFGR1_VBAT)
 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
   * @{
-  */  
+  */
 /** @brief  SYSCFG interrupt enable/disable macros
   */
 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE()          (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
@@ -722,7 +722,7 @@ typedef enum
  * @}
  */
 #endif /* SYSCFG_CFGR1_VBAT */
- 
+
 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
   * @{
@@ -738,7 +738,7 @@ typedef enum
  * @}
  */
 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
- 
+
 #if defined(SYSCFG_CFGR2_PVD_LOCK)
 /** @defgroup PVD_Lock_Enable PVD Lock
   * @{
@@ -770,7 +770,7 @@ typedef enum
  * @}
  */
 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
- 
+
 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
   * @{
   */
@@ -802,7 +802,7 @@ typedef enum
 /**
  * @}
  */
- 
+
 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
   * @{
@@ -820,7 +820,7 @@ typedef enum
  * @}
  */
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-                                                           
+
 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
   * @{
@@ -835,7 +835,7 @@ typedef enum
  * @}
  */
 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
- 
+
 #if defined(SYSCFG_RCR_PAGE0)
 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
   * @{
@@ -851,10 +851,10 @@ typedef enum
  * @}
  */
 #endif /* SYSCFG_RCR_PAGE0 */
- 
+
 /**
  * @}
- */ 
+ */
 /* Private macro -------------------------------------------------------------*/
 /** @defgroup HAL_Private_Macros HAL Private Macros
   * @{
@@ -864,13 +864,13 @@ typedef enum
                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
 /**
  * @}
- */ 
+ */
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
   * @{
   */
 
-/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
+/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
  *  @brief    Initialization and de-initialization functions
  * @{
  */
@@ -883,7 +883,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
 /**
  * @}
  */
- 
+
 /* Exported variables ---------------------------------------------------------*/
 /** @addtogroup HAL_Exported_Variables
   * @{
@@ -894,8 +894,8 @@ extern HAL_TickFreqTypeDef uwTickFreq;
 /**
   * @}
   */
- 
-/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions 
+
+/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
  *  @brief    HAL Control functions
  * @{
  */
@@ -930,12 +930,12 @@ void     HAL_DBGMCU_DisableDBGStandbyMode(void);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h

@@ -27,28 +27,28 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal_def.h"
-   
+
 /* Include ADC HAL Extended module */
 /* (include on top of file since ADC structures are defined in extended file) */
 #include "stm32f3xx_hal_adc_ex.h"
-   
+
 /** @addtogroup STM32F3xx_HAL_Driver
   * @{
   */
 
 /** @addtogroup ADC
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup ADC_Exported_Types ADC Exported Types
   * @{
   */
-/** 
+/**
   * @brief  HAL ADC state machine: ADC states definition (bitfields)
   * @note   ADC state machine is managed by bitfields, state must be compared
   *         with bit by bit.
-  *         For example:                                                         
+  *         For example:
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
   */
@@ -85,8 +85,8 @@
 #define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000U)    /*!< ADC in multimode slave state, controlled by another ADC master ( */
 
 
-/** 
-  * @brief  ADC handle Structure definition  
+/**
+  * @brief  ADC handle Structure definition
   */
 typedef struct __ADC_HandleTypeDef
 {
@@ -101,12 +101,12 @@ typedef struct __ADC_HandleTypeDef
   __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
 
   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */  
+  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
@@ -151,7 +151,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 
 /* Exported constants --------------------------------------------------------*/
 /* Exported macros -----------------------------------------------------------*/
-     
+
 /** @defgroup ADC_Exported_Macro ADC Exported Macros
   * @{
   */
@@ -173,18 +173,18 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 
 /**
   * @}
-  */ 
+  */
 
 
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup ADC_Exported_Functions ADC Exported Functions
   * @{
-  */ 
+  */
 
-/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 
+/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
  * @{
- */ 
+ */
 /* Initialization and de-initialization functions  **********************************/
 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
@@ -202,7 +202,7 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
 
 /** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
  * @{
- */ 
+ */
 /* Blocking mode: Polling */
 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
@@ -232,7 +232,7 @@ void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
 
 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
  * @{
- */ 
+ */
 /* Peripheral Control functions ***********************************************/
 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
@@ -241,9 +241,9 @@ HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana
   */
 
 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief   ADC Peripheral State functions 
+ *  @brief   ADC Peripheral State functions
  * @{
- */ 
+ */
 /* Peripheral State functions *************************************************/
 uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
@@ -257,7 +257,7 @@ uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h

@@ -27,14 +27,14 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal_def.h"
-   
+
 /** @addtogroup STM32F3xx_HAL_Driver
   * @{
   */
 
 /** @addtogroup ADCEx ADCEx
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
@@ -47,9 +47,9 @@ struct __ADC_HandleTypeDef;
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /**
-  * @brief  Structure definition of ADC initialization and regular group  
+  * @brief  Structure definition of ADC initialization and regular group
   * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign, 
+  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
   *            ScanConvMode, EOCSelection, LowPowerAutoWait.
   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
@@ -65,11 +65,11 @@ typedef struct
   uint32_t ClockPrescaler;                  /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
                                                  The clock is common for all the ADCs.
                                                  This parameter can be a value of @ref ADCEx_ClockPrescaler
-                                                 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 
+                                                 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
                                                        AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
-                                                 Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level. 
+                                                 Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
                                                  Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
-  uint32_t Resolution;                      /*!< Configures the ADC resolution. 
+  uint32_t Resolution;                      /*!< Configures the ADC resolution.
                                                  This parameter can be a value of @ref ADCEx_Resolution */
   uint32_t DataAlign;                       /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting)
                                                  or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U).
@@ -86,7 +86,7 @@ typedef struct
                                                  This parameter can be a value of @ref ADCEx_EOCSelection. */
   FunctionalState LowPowerAutoWait;         /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary.
                                                  New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
-                                                 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 
+                                                 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
                                                  This parameter can be set to ENABLE or DISABLE.
                                                  Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
                                                        Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
@@ -127,8 +127,8 @@ typedef struct
                                                   - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
 }ADC_InitTypeDef;
 
-/** 
-  * @brief  Structure definition of ADC channel for regular group  
+/**
+  * @brief  Structure definition of ADC channel for regular group
   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
   *         ADC state can be either:
   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
@@ -137,7 +137,7 @@ typedef struct
   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
   */
-typedef struct 
+typedef struct
 {
   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
                                         This parameter can be a value of @ref ADCEx_channels
@@ -173,8 +173,8 @@ typedef struct
                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
 }ADC_ChannelConfTypeDef;
 
-/** 
-  * @brief  Structure definition of ADC injected group and ADC channel for injected group  
+/**
+  * @brief  Structure definition of ADC injected group and ADC channel for injected group
   * @note   Parameters of this structure are shared within 2 scopes:
   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
@@ -188,7 +188,7 @@ typedef struct
   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
   */
-typedef struct 
+typedef struct
 {
   uint32_t InjectedChannel;                         /*!< Configure the ADC injected channel
                                                          This parameter can be a value of @ref ADCEx_channels
@@ -225,7 +225,7 @@ typedef struct
   uint32_t InjectedNbrOfConversion;                 /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
                                                          To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                                          This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
   FunctionalState InjectedDiscontinuousConvMode;    /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
                                                          Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
@@ -233,15 +233,15 @@ typedef struct
                                                          This parameter can be set to ENABLE or DISABLE.
                                                          Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
                                                          Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
   FunctionalState AutoInjectedConv;                 /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                                         This parameter can be set to ENABLE or DISABLE.      
+                                                         This parameter can be set to ENABLE or DISABLE.
                                                          Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
                                                          Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
                                                          Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
                                                                To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
   FunctionalState QueueInjectedContext;             /*!< Specifies whether the context queue feature is enabled.
                                                          This parameter can be set to ENABLE or DISABLE.
@@ -249,34 +249,34 @@ typedef struct
                                                          new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
                                                          Caution: This feature request that the sequence is fully configured before injected conversion start.
                                                                   Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set.
                                                          Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
   uint32_t ExternalTrigInjecConv;                   /*!< Selects the external event used to trigger the conversion start of injected group.
                                                          If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
                                                          This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
   uint32_t ExternalTrigInjecConvEdge;               /*!< Selects the external trigger edge of injected group.
                                                          This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
                                                          If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
 }ADC_InjectionConfTypeDef;
 
-/** 
-  * @brief  ADC Injection Configuration 
+/**
+  * @brief  ADC Injection Configuration
   */
 typedef struct
 {
-  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each 
+  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
                                               HAL_ADCEx_InjectedConfigChannel() call to finally initialize
                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
-                                               
-  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */                                        
+
+  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
 }ADC_InjectionConfigTypeDef;
 
-/** 
+/**
   * @brief  Structure definition of ADC analog watchdog
   * @note   The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
   *         ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
@@ -299,15 +299,15 @@ typedef struct
                                           This parameter can be set to ENABLE or DISABLE */
   uint32_t HighThreshold;            /*!< Configures the ADC analog watchdog High threshold value.
                                           Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
-                                          Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 
+                                          Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
                                                 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
   uint32_t LowThreshold;             /*!< Configures the ADC analog watchdog High threshold value.
                                           Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
-                                          Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 
+                                          Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
                                                 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
 }ADC_AnalogWDGConfTypeDef;
 
-/** 
+/**
   * @brief  Structure definition of ADC multimode
   * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
   *         ADC state can be either:
@@ -318,7 +318,7 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. 
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode.
                                    This parameter can be a value of @ref ADCEx_Common_mode */
   uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multi ADC mode:
                                    selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
@@ -338,8 +338,8 @@ typedef struct
 
 
 #if defined(STM32F373xC) || defined(STM32F378xx)
-/** 
-  * @brief  Structure definition of ADC and regular group initialization 
+/**
+  * @brief  Structure definition of ADC and regular group initialization
   * @note   Parameters of this structure are shared within 2 scopes:
   *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
@@ -381,17 +381,17 @@ typedef struct
                                                 This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
 }ADC_InitTypeDef;
 
-/** 
-  * @brief  Structure definition of ADC channel for regular group   
+/**
+  * @brief  Structure definition of ADC channel for regular group
   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
   *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */ 
-typedef struct 
+  */
+typedef struct
 {
   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
                                         This parameter can be a value of @ref ADCEx_channels
                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer 
+  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer
                                         This parameter can be a value of @ref ADCEx_regular_rank
                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
@@ -405,7 +405,7 @@ typedef struct
                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
 }ADC_ChannelConfTypeDef;
 
-/** 
+/**
   * @brief  ADC Configuration injected Channel structure definition
   * @note   Parameters of this structure are shared within 2 scopes:
   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
@@ -416,7 +416,7 @@ typedef struct
   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
   *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
   */
-typedef struct 
+typedef struct
 {
   uint32_t InjectedChannel;                         /*!< Selection of ADC channel to configure
                                                          This parameter can be a value of @ref ADCEx_channels
@@ -440,17 +440,17 @@ typedef struct
   uint32_t InjectedNbrOfConversion;                 /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
                                                          To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                                          This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
   FunctionalState InjectedDiscontinuousConvMode;    /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
                                                          Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
                                                          Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
                                                          This parameter can be set to ENABLE or DISABLE.
                                                          Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
+                                                         Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
                                                                   configure a channel on injected group can impact the configuration of other channels previously set. */
   FunctionalState AutoInjectedConv;                 /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                                         This parameter can be set to ENABLE or DISABLE.      
+                                                         This parameter can be set to ENABLE or DISABLE.
                                                          Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
                                                          Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
                                                          Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
@@ -779,7 +779,7 @@ typedef struct
   * @}
   */
 
-/** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion 
+/** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
   * @{
   */
 #define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
@@ -1410,7 +1410,7 @@ typedef struct
 /**
   * @}
   */
-       
+
 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
   * @{
   */
@@ -1509,13 +1509,13 @@ typedef struct
   */
 
 
-     
+
 /* Private constants ---------------------------------------------------------*/
 
 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
   * @{
   */
-     
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
@@ -1725,7 +1725,7 @@ typedef struct
 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO   ((uint32_t)ADC_JSQR_JEXTSEL)
 #endif /* STM32F302xE || */
        /* STM32F302xC    */
-      
+
 #if defined(STM32F303x8) || defined(STM32F328xx)
 /* List of external triggers of group ADC1&ADC2:                              */
 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
@@ -1790,13 +1790,13 @@ typedef struct
 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS  | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
                                ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
                                ADC_FLAG_JQOVF)
-      
+
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
 
-      
+
 #if defined(STM32F373xC) || defined(STM32F378xx)
 
 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
@@ -1836,7 +1836,7 @@ typedef struct
 /**
   * @}
   */
-      
+
 /** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
   * @{
   */
@@ -1887,13 +1887,13 @@ typedef struct
 /**
   * @}
   */
-     
+
 #endif /* STM32F373xC || STM32F378xx */
-     
+
 /**
   * @}
   */
-     
+
 /* Exported macro ------------------------------------------------------------*/
 
 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
@@ -1916,7 +1916,7 @@ typedef struct
   *       respected before using this macro:
   *        - ADC internal voltage regulator must be preliminarily enabled.
   *          This is performed by function HAL_ADC_Init().
-  *        - ADC state requirements: ADC must be disabled, no conversion on 
+  *        - ADC state requirements: ADC must be disabled, no conversion on
   *          going, no calibration on going.
   *          These checks are performed by functions HAL_ADC_start_xxx().
   * @retval None
@@ -1929,7 +1929,7 @@ typedef struct
   * @param __HANDLE__ ADC handle
   * @note On STM32F3 devices, some hardware constraints must be strictly
   *       respected before using this macro:
-  *        - ADC state requirements: ADC must be enabled, no conversion on 
+  *        - ADC state requirements: ADC must be enabled, no conversion on
   *          going.
   *          These checks are performed by functions HAL_ADC_start_xxx().
   * @retval None
@@ -2065,7 +2065,7 @@ typedef struct
   */
 #define __HAL_ADC_ENABLE(__HANDLE__)                                           \
   (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-  
+
 /**
   * @brief Disable the ADC peripheral
   * @param __HANDLE__ ADC handle
@@ -2073,7 +2073,7 @@ typedef struct
   */
 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
   (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-    
+
 /** @brief Enable the ADC end of conversion interrupt.
   * @param __HANDLE__ ADC handle
   * @param __INTERRUPT__ ADC Interrupt
@@ -2123,7 +2123,7 @@ typedef struct
   */
 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
   ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-    
+
 /** @brief Clear the ADC's pending flags
   * @param __HANDLE__ ADC handle
   * @param __FLAG__ ADC flag
@@ -2151,7 +2151,7 @@ typedef struct
   */
 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
 /* code of final user.                                                        */
-      
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
     defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
@@ -2247,19 +2247,19 @@ typedef struct
   * @retval None
   */
 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-         
+
 /**
   * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
   * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_ Channel number.  
+  * @param _CHANNELNB_ Channel number.
   * @retval None
   */
 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
-    
+
 /**
   * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
   * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_ Channel number.  
+  * @param _CHANNELNB_ Channel number.
   * @retval None
   */
 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
@@ -2267,7 +2267,7 @@ typedef struct
 /**
   * @brief Set the selected regular Channel rank for rank between 1 and 4.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_)))
@@ -2275,7 +2275,7 @@ typedef struct
 /**
   * @brief Set the selected regular Channel rank for rank between 5 and 9.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U)))
@@ -2283,7 +2283,7 @@ typedef struct
 /**
   * @brief Set the selected regular Channel rank for rank between 10 and 14.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U)))
@@ -2291,7 +2291,7 @@ typedef struct
 /**
   * @brief Set the selected regular Channel rank for rank between 15 and 16.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U)))
@@ -2299,7 +2299,7 @@ typedef struct
 /**
   * @brief Set the selected injected Channel rank.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.   
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U))
@@ -2317,7 +2317,7 @@ typedef struct
   * @param _CHANNEL_ ADC Channel
   * @retval None
   */
-#define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_)) 
+#define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
 
 /**
   * @brief Enable automatic conversion of injected group
@@ -2367,7 +2367,7 @@ typedef struct
   * @retval None
   */
 #define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
-    
+
 /**
   * @brief Enable ADC overrun mode.
   * @param _OVERRUN_MODE_ Overrun mode.
@@ -2389,11 +2389,11 @@ typedef struct
 #define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
 
 /**
-  * @brief For devices with 3 ADCs or more: Defines the external trigger source 
-  *        for regular group according to ADC into common group ADC1&ADC2 or 
+  * @brief For devices with 3 ADCs or more: Defines the external trigger source
+  *        for regular group according to ADC into common group ADC1&ADC2 or
   *        ADC3&ADC4 (some triggers with same source have different value to
   *        be programmed into ADC EXTSEL bits of CFGR register).
-  *        Note: No risk of trigger bits value of common group ADC1&ADC2 
+  *        Note: No risk of trigger bits value of common group ADC1&ADC2
   *        misleading to another trigger at same bits value, because the 3
   *        exceptions below are circular and do not point to any other trigger
   *        with direct treatment.
@@ -2429,7 +2429,7 @@ typedef struct
    (__EXT_TRIG_CONV__)                                                         \
  )
 #endif /* STM32F303xC || STM32F358xx */
-   
+
 #if defined(STM32F303xE) || defined(STM32F398xx)
 /* Note: Macro including external triggers specific to device STM303xE: using */
 /*       Timer20 with ADC trigger input remap.                                */
@@ -2478,11 +2478,11 @@ typedef struct
        /* STM32F303xC || STM32F358xx    */
 
 /**
-  * @brief For devices with 3 ADCs or more: Defines the external trigger source 
-  *        for injected group according to ADC into common group ADC1&ADC2 or 
+  * @brief For devices with 3 ADCs or more: Defines the external trigger source
+  *        for injected group according to ADC into common group ADC1&ADC2 or
   *        ADC3&ADC4 (some triggers with same source have different value to
   *        be programmed into ADC JEXTSEL bits of JSQR register).
-  *        Note: No risk of trigger bits value of common group ADC1&ADC2 
+  *        Note: No risk of trigger bits value of common group ADC1&ADC2
   *        misleading to another trigger at same bits value, because the 3
   *        exceptions below are circular and do not point to any other trigger
   *        with direct treatment, except trigger
@@ -2522,7 +2522,7 @@ typedef struct
    (__EXT_TRIG_INJECTCONV__)                                                   \
  )
 #endif /* STM32F303xC || STM32F358xx */
-   
+
 #if defined(STM32F303xE) || defined(STM32F398xx)
 /* Note: Macro including external triggers specific to device STM303xE: using */
 /*       Timer20 with ADC trigger input remap.                                */
@@ -2584,7 +2584,7 @@ typedef struct
   * @param _CHANNEL_ ADC Channel
   * @retval None
   */
-#define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_)) 
+#define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
 
 /**
   * @brief Calibration factor in differential mode to be set into calibration register
@@ -2599,7 +2599,7 @@ typedef struct
   * @retval None
   */
 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
-     
+
 /**
   * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
   * @param _Threshold_ Threshold value
@@ -2613,7 +2613,7 @@ typedef struct
   * @retval None
   */
 #define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U)
-    
+
 /**
   * @brief Verification of hardware constraints before ADC can be disabled
   * @param __HANDLE__ ADC handle
@@ -2623,10 +2623,10 @@ typedef struct
        (( ( ((__HANDLE__)->Instance->CR) &                                     \
             (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN   \
         ) ? SET : RESET)
-         
+
 
 /**
-  * @brief Shift the offset in function of the selected ADC resolution. 
+  * @brief Shift the offset in function of the selected ADC resolution.
   *        Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
   *        If resolution 12 bits, no shift.
   *        If resolution 10 bits, shift of 2 ranks on the left.
@@ -2694,7 +2694,7 @@ typedef struct
 #endif /* STM32F302xE                               || */
        /* STM32F302xC                               || */
        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
-       
+
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define ADC_MASTER_INSTANCE(__HANDLE__)                                        \
   (ADC1)
@@ -2723,12 +2723,12 @@ typedef struct
 #endif /* STM32F302xE                               || */
        /* STM32F302xC                               || */
        /* STM32F303x8 || STM32F328xx || STM32F334x8    */
-       
+
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define ADC_COMMON_REGISTER(__HANDLE__)                                        \
   (ADC1_COMMON)
 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-       
+
 /**
   * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
   * @param __HANDLE__ ADC handle
@@ -2745,7 +2745,7 @@ typedef struct
   )
 #endif /* STM32F303xE || STM32F398xx || */
        /* STM32F303xC || STM32F358xx    */
-    
+
 #if defined(STM32F302xE)                                                ||    \
     defined(STM32F302xC)                                                ||    \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
@@ -2851,7 +2851,7 @@ typedef struct
 #else
 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
   (RESET)
-#endif 
+#endif
 
 /**
   * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
@@ -2886,7 +2886,7 @@ typedef struct
   )
 #endif /* STM32F303xE || STM32F398xx || */
        /* STM32F303xC || STM32F358xx    */
-    
+
 #if defined(STM32F302xE)                                                || \
     defined(STM32F302xC)                                                || \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
@@ -2929,7 +2929,7 @@ typedef struct
   )
 #endif /* STM32F303xE || STM32F398xx || */
        /* STM32F303xC || STM32F358xx    */
-    
+
 #if defined(STM32F302xE)                                                || \
     defined(STM32F302xC)                                                || \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
@@ -3479,7 +3479,7 @@ typedef struct
 /**
   * @}
   */
-    
+
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
@@ -3534,7 +3534,7 @@ typedef struct
 
 /**
   * @brief Set ADC number of conversions into regular channel sequence length.
-  * @param _NbrOfConversion_ Regular channel sequence length 
+  * @param _NbrOfConversion_ Regular channel sequence length
   * @retval None
   */
 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
@@ -3543,7 +3543,7 @@ typedef struct
 /**
   * @brief Set the ADC's sample time for channel numbers between 10 and 18.
   * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_ Channel number.  
+  * @param _CHANNELNB_ Channel number.
   * @retval None
   */
 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
@@ -3552,7 +3552,7 @@ typedef struct
 /**
   * @brief Set the ADC's sample time for channel numbers between 0 and 9.
   * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_ Channel number.  
+  * @param _CHANNELNB_ Channel number.
   * @retval None
   */
 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
@@ -3561,7 +3561,7 @@ typedef struct
 /**
   * @brief Set the selected regular channel rank for rank between 1 and 6.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
@@ -3570,7 +3570,7 @@ typedef struct
 /**
   * @brief Set the selected regular channel rank for rank between 7 and 12.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
@@ -3579,7 +3579,7 @@ typedef struct
 /**
   * @brief Set the selected regular channel rank for rank between 13 and 16.
   * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_ Rank number.    
+  * @param _RANKNB_ Rank number.
   * @retval None
   */
 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
@@ -3621,7 +3621,7 @@ typedef struct
   */
 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
   (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
-   
+
 /**
   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
   * @param _SCAN_MODE_ Scan conversion mode.
@@ -3633,7 +3633,7 @@ typedef struct
   (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
    )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
   )
-    
+
 /**
   * @brief Calibration factor in differential mode to be set into calibration register
   * @param _Calibration_Factor_ Calibration factor value
@@ -3649,8 +3649,8 @@ typedef struct
   */
 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_)                             \
   ((_Calibration_Factor_) >> 16U)
-      
-      
+
+
 /**
   * @brief Get the maximum ADC conversion cycles on all channels.
   * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
@@ -3662,7 +3662,7 @@ typedef struct
   * Unit: ADC clock cycles
   * @param __HANDLE__ ADC handle
   * @retval ADC conversion cycles on all channels
-  */   
+  */
 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                     \
     (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
        (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
@@ -3697,7 +3697,7 @@ typedef struct
   )
 
 /**
-  * @brief Get the ADC clock prescaler from system clock configuration register. 
+  * @brief Get the ADC clock prescaler from system clock configuration register.
   * @retval None
   */
 #define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
@@ -3829,23 +3829,23 @@ typedef struct
 /**
   * @}
   */
-              
+
 #endif /* STM32F373xC || STM32F378xx */
 /**
   * @}
   */
 
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions
   * @{
-  */ 
-          
+  */
+
 /* Initialization/de-initialization functions *********************************/
 
 /** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
   * @{
-  */ 
+  */
 /* I/O operation functions ****************************************************/
 
 /* ADC calibration */
@@ -3880,7 +3880,7 @@ HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* ha
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /* ADC multimode */
 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc); 
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
 uint32_t                HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
@@ -3925,10 +3925,10 @@ void                    HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleT
 /**
   * @}
   */
-     
+
 /** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
   * @{
-  */ 
+  */
 /* Peripheral Control functions ***********************************************/
 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
 
@@ -3948,10 +3948,10 @@ HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleType
 /**
   * @}
   */
-  
+
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp.h

@@ -204,7 +204,7 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @param  __HANDLE__  COMP handle.
   * @retval None
   */
-  
+
 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
 #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
@@ -220,7 +220,7 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @param __HANDLE__ COMP handle
   * @retval None
   */
-#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) 
+#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
 
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_comp_ex.h

@@ -53,7 +53,7 @@ extern "C" {
 #define COMP_INVERTINGINPUT_VREFINT          (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
 #define COMP_INVERTINGINPUT_DAC1_CH1         COMP_CSR_COMPxINSEL_2                         /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
 #define COMP_INVERTINGINPUT_DAC1_CH2         (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_IO1              (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3, 
+#define COMP_INVERTINGINPUT_IO1              (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
                                                                                                 PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
                                                                                                 PC0 for COMP7) connected to comparator inverting input */
 #define COMP_INVERTINGINPUT_IO2               COMP_CSR_COMPxINSEL                          /*!< IO2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
@@ -134,7 +134,7 @@ extern "C" {
 /** @defgroup COMPEx_NonInvertingInput  COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
   * @{
   */
-#define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, 
+#define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
                                                                              PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
                                                                              PA0 for COMP7) connected to comparator non inverting input */
 #define COMP_NONINVERTINGINPUT_IO2               COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
@@ -157,7 +157,7 @@ extern "C" {
 /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
   * @{
   */
-#define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2) 
+#define COMP_NONINVERTINGINPUT_IO1               (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
                                                                              connected to comparator non inverting input */
 #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED  COMP_CSR_COMP1SW1  /*!< DAC ouput connected to comparator COMP1 non inverting input */
 /**
@@ -167,7 +167,7 @@ extern "C" {
 /** @defgroup COMPEx_NonInvertingInput  COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
   * @{
   */
-#define COMP_NONINVERTINGINPUT_IO1             (0x00000000U)   /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3, 
+#define COMP_NONINVERTINGINPUT_IO1             (0x00000000U)   /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
                                                                             PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
                                                                             PA0 for COMP7) connected to comparator non inverting input */
 #define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1      /*!< DAC ouput connected to comparator COMP1 non inverting input */
@@ -178,7 +178,7 @@ extern "C" {
 /** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices)
   * @{
   */
-#define COMP_NONINVERTINGINPUT_IO1             (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6) 
+#define COMP_NONINVERTINGINPUT_IO1             (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
                                                                            connected to comparator non inverting input */
 /**
   * @}
@@ -2341,7 +2341,7 @@ extern "C" {
       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-     
+
 #endif /* STM32F303xC || STM32F358xx */
 
 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
@@ -2680,7 +2680,7 @@ extern "C" {
       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM1OC5) ||        \
       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM8OC5) ||        \
       ((BLANKINGSRCE) == COMP_BLANKINGSRCE_TIM15OC2))))
-     
+
 #endif /* STM32F303xE || STM32F398xx */
 
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
@@ -2760,7 +2760,7 @@ extern "C" {
 /* STM32F373xB/STM32F373xC/STM32F378xx devices comparator instances blanking source values */
 #define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
    ((((INSTANCE) == COMP1) || ((INSTANCE) == COMP2))  &&     \
-     ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))         
+     ((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE))
 
 #endif /* STM32F373xC || STM32F378xx */
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_conf_template.h

@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_CONF_H
@@ -30,7 +30,7 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
 #define HAL_ADC_MODULE_ENABLED
@@ -73,15 +73,15 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 /**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+  *        Timeout value
   */
 #if !defined  (HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
@@ -90,25 +90,25 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+  *        Timeout value
   */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
+#if !defined  (HSI_STARTUP_TIMEOUT)
  #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
+#endif /* HSI_STARTUP_TIMEOUT */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (40000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (40000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -117,7 +117,7 @@
   */
 #if !defined  (LSE_VALUE)
  #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
+#endif /* LSE_VALUE */
 
 /**
   * @brief Time out for LSE start up value in ms.
@@ -128,7 +128,7 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
   *        - External clock not generated on EVAL 373
@@ -143,7 +143,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default) */
 #define  USE_RTOS                     0U
@@ -180,14 +180,14 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /*#define USE_FULL_ASSERT    1U*/
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -205,7 +205,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f3xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
  #include "stm32f3xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -256,8 +256,8 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_HRTIM_MODULE_ENABLED
  #include "stm32f3xx_hal_hrtim.h"
 #endif /* HAL_HRTIM_MODULE_ENABLED */
@@ -336,7 +336,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -345,8 +345,8 @@
   void assert_failed(uint8_t* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
+#endif /* USE_FULL_ASSERT */
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h

@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_CORTEX_H
@@ -34,7 +34,7 @@
 
 /** @addtogroup CORTEX
   * @{
-  */ 
+  */
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
   * @{
@@ -42,31 +42,31 @@
 
 #if (__MPU_PRESENT == 1U)
 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure 
+  * @brief  MPU Region initialization structure
   * @{
   */
 typedef struct
 {
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
+  uint8_t                Enable;                /*!< Specifies the status of the region.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
 }MPU_Region_InitTypeDef;
 /**
@@ -114,7 +114,7 @@ typedef struct
 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
   * @{
   */
-#define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)  
+#define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)
 #define  MPU_HARDFAULT_NMI           (0x00000002U)
 #define  MPU_PRIVILEGED_DEFAULT      (0x00000004U)
 #define  MPU_HFNMI_PRIVDEF           (0x00000006U)
@@ -182,44 +182,44 @@ typedef struct
   */
 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U) 
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U) 
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U) 
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)  
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) 
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) 
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) 
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) 
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) 
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) 
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) 
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) 
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) 
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) 
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) 
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
-/**                                
+/**
   * @}
   */
-   
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
   * @{
   */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)  
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U) 
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)  
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)  
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U) 
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00U)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01U)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02U)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03U)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05U)
 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06U)
 /**
   * @}
@@ -228,11 +228,11 @@ typedef struct
 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
   * @{
   */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)  
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U) 
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)  
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)  
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U) 
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00U)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01U)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02U)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03U)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04U)
 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05U)
 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06U)
 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07U)
@@ -266,7 +266,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
 /**
   * @}
   */
-  
+
 /** @addtogroup CORTEX_Exported_Functions_Group2
  * @{
  */
@@ -285,19 +285,19 @@ void HAL_SYSTICK_IRQHandler(void);
 void HAL_SYSTICK_Callback(void);
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
   */
 
-/* Private types -------------------------------------------------------------*/ 
+/* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
   * @{
-  */  
+  */
 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
@@ -309,10 +309,10 @@ void HAL_SYSTICK_Callback(void);
 #define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
 
 #define IS_NVIC_DEVICE_IRQ(IRQ)  ((IRQ) >= 0x00)
-                                  
+
 /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
   * @{
-  */                       
+  */
 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
 /**
@@ -391,9 +391,9 @@ void HAL_SYSTICK_Callback(void);
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/   
+/* Private functions ---------------------------------------------------------*/
 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions
-  * @brief    CORTEX private  functions 
+  * @brief    CORTEX private  functions
   * @{
   */
 
@@ -410,17 +410,17 @@ void HAL_MPU_Enable(uint32_t MPU_Control);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* __STM32F3xx_HAL_CORTEX_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac.h

@@ -27,7 +27,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal_def.h"
-   
+
 /** @addtogroup STM32F3xx_HAL_Driver
   * @{
   */
@@ -42,9 +42,9 @@
   * @{
   */
 
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+/**
+  * @brief  HAL State structures definition
+  */
 typedef enum
 {
   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
@@ -52,44 +52,44 @@ typedef enum
   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
- 
+
 }HAL_DAC_StateTypeDef;
-   
-/** 
-  * @brief   DAC Configuration regular Channel structure definition  
-  */ 
+
+/**
+  * @brief   DAC Configuration regular Channel structure definition
+  */
 typedef struct
 {
   uint32_t DAC_Trigger;                 /*!< Specifies the external trigger for the selected DAC channel.
                                         This parameter can be a value of @ref DACEx_trigger_selection */
-  
+
   uint32_t DAC_OutputBuffer;            /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                        This parameter can be a value of @ref DAC_output_buffer 
-                                        For a given DAC channel, is this paramater applies then DAC_OutputSwitch 
+                                        This parameter can be a value of @ref DAC_output_buffer
+                                        For a given DAC channel, is this paramater applies then DAC_OutputSwitch
                                         does not apply */
-  
+
   uint32_t DAC_OutputSwitch;            /*!< Specifies whether the DAC channel output switch is enabled or disabled.
-                                        This parameter can be a value of @ref DAC_OutputSwitch 
-                                        For a given DAC channel, is this paramater applies then DAC_OutputBuffer 
+                                        This parameter can be a value of @ref DAC_OutputSwitch
+                                        For a given DAC channel, is this paramater applies then DAC_OutputBuffer
                                         does not apply */
-  
+
 }DAC_ChannelConfTypeDef;
 
-/** 
-  * @brief  DAC handle Structure definition  
-  */ 
+/**
+  * @brief  DAC handle Structure definition
+  */
 typedef struct __DAC_HandleTypeDef
 {
   DAC_TypeDef                 *Instance;      /*!< Register base address             */
-  
+
   __IO HAL_DAC_StateTypeDef   State;          /*!< DAC communication state           */
 
   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-  
+
   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1U */
-  
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2U */ 
-  
+
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2U */
+
   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
 
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -100,10 +100,10 @@ typedef struct __DAC_HandleTypeDef
   void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef* hdac);
   void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef* hdac);
   void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef* hdac);
-  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef* hdac); 
+  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef* hdac);
 
   void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
-  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac); 
+  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 
 }DAC_HandleTypeDef;
@@ -125,8 +125,8 @@ typedef enum
   HAL_DAC_MSP_INIT_CB_ID                     = 0x08U,  /*!< DAC MspInit Callback ID           */
   HAL_DAC_MSP_DEINIT_CB_ID                   = 0x09U,  /*!< DAC MspDeInit Callback ID         */
   HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
-}HAL_DAC_CallbackIDTypeDef;                            
-                                                       
+}HAL_DAC_CallbackIDTypeDef;
+
 /**
   * @brief  HAL DAC Callback pointer definition
   */
@@ -151,7 +151,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 #define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 #define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */  
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -223,18 +223,18 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 
 /** @defgroup DAC_flags_definition DAC flags definition
   * @{
-  */ 
+  */
 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
 /**
   * @}
   */
 
 /** @defgroup DAC_interrupts_definition DAC interrupts definition
   * @{
-  */ 
+  */
 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_CR_DMAUDRIE1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_CR_DMAUDRIE2) 
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_CR_DMAUDRIE2)
 
 /**
   * @}
@@ -279,7 +279,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   */
 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
- 
+
 /** @brief Set DHR12R1 alignment
   * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
@@ -395,7 +395,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
                              ((ALIGN) == DAC_ALIGN_12B_L) || \
                              ((ALIGN) == DAC_ALIGN_8B_R))
 
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) 
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
 
 
 
@@ -405,9 +405,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 
 
 /* Include DAC HAL Extended module */
-#include "stm32f3xx_hal_dac_ex.h" 
+#include "stm32f3xx_hal_dac_ex.h"
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 
 /** @addtogroup DAC_Exported_Functions
   * @{
@@ -416,7 +416,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 /** @addtogroup DAC_Exported_Functions_Group1
   * @{
   */
-/* Initialization and de-initialization functions *****************************/ 
+/* Initialization and de-initialization functions *****************************/
 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
@@ -452,7 +452,7 @@ HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D
 /**
   * @}
   */
-  
+
 /** @addtogroup DAC_Exported_Functions_Group3
   * @{
   */
@@ -485,7 +485,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dac_ex.h

@@ -47,7 +47,7 @@
   */
 
 #if defined(STM32F301x8) || defined(STM32F318xx)
-#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
                                                                      has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
@@ -67,10 +67,10 @@
     defined(STM32F302xC) || \
     defined(STM32F302x8)
 
-#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
                                                                      has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */                                                                       
+#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
@@ -93,17 +93,17 @@
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
     defined(STM32F303xC) || defined(STM32F358xx)
 
-#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
                                                                      has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel 
-                                                                                           Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */                                                                       
-#define DAC_TRIGGER_T8_TRGO                DAC_TRIGGER_T3_TRGO                        /*!< TIM8 TRGO selected as external conversion trigger for DAC channel 
-                                                                                           Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */                  
+#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
+                                                                                           Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
+#define DAC_TRIGGER_T8_TRGO                DAC_TRIGGER_T3_TRGO                        /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+                                                                                           Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
 
 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
@@ -121,15 +121,15 @@
        /* STM32F303xC || STM32F358xx    */
 
 
-#if defined(STM32F303x8) || defined(STM32F328xx) 
+#if defined(STM32F303x8) || defined(STM32F328xx)
 
-#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
                                                                      has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */                                                                       
+#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
 
 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
@@ -147,8 +147,8 @@
 
 
 #if defined(STM32F373xC) || defined(STM32F378xx)
- 
-#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
                                                                      has been loaded, and not by external trigger */
 
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
@@ -157,7 +157,7 @@
 #define DAC_TRIGGER_T18_TRGO               DAC_TRIGGER_T5_TRGO                                         /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */                                                                       
+#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
 
 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
@@ -176,21 +176,21 @@
 
 #if defined(STM32F334x8)
 
-#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
                                                                      has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel 
+#define DAC_TRIGGER_T3_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
                                                                                            Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
 
 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel 
-                                                                                                            Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */ 
-#define DAC_TRIGGER_HRTIM1_DACTRG1         DAC_TRIGGER_T15_TRGO      /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC 
-                                                                          Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */ 
+#define DAC_TRIGGER_T15_TRGO               ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
+                                                                                                            Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
+#define DAC_TRIGGER_HRTIM1_DACTRG1         DAC_TRIGGER_T15_TRGO      /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
+                                                                          Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
 
 #define DAC_TRIGGER_HRTIM1_DACTRG2         ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
-                                                                                                            Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */ 
+                                                                                                            Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
 #define DAC_TRIGGER_HRTIM1_DACTRG3         DAC_TRIGGER_HRTIM1_DACTRG2                                  /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
 
 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
@@ -215,7 +215,7 @@
 /** @defgroup DACEx_Channel_selection DACEx Channel selection
   * @{
   */
- 
+
 #if defined(STM32F302xE) || \
     defined(STM32F302xC) || \
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
@@ -233,7 +233,7 @@
 
 #endif /* STM32F303xE || STM32F398xx || */
        /* STM32F303xC || STM32F358xx    */
-   
+
 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
     defined(STM32F373xC) || defined(STM32F378xx)
 
@@ -242,7 +242,7 @@
 
 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
        /* STM32F373xC || STM32F378xx                   */
-   
+
 /**
   * @}
   */
@@ -261,7 +261,7 @@
     defined(STM32F302xC) || \
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 
-#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)            
+#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
 #endif  /* STM32F302xE                               || */
         /* STM32F302xC                               || */
         /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
@@ -289,7 +289,7 @@
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 
 /** @addtogroup DACEx_Exported_Functions
   * @{
@@ -297,7 +297,7 @@
 
 /** @addtogroup DACEx_Exported_Functions_Group2
  * @{
- */    
+ */
 /* IO operation functions *****************************************************/
 
 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
@@ -339,5 +339,5 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
 #endif
 
 #endif /* STM32F3xx_HAL_HAL_EX_H */
- 
+
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_def.h
   * @author  MCD Application Team
-  * @brief   This file contains HAL common defines, enumeration, macros and 
-  *          structures definitions. 
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
   ******************************************************************************
   * @attention
   *
@@ -33,10 +33,10 @@
 
 /* Exported types ------------------------------------------------------------*/
 
-/** 
-  * @brief  HAL Status structures definition  
-  */  
-typedef enum 
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
 {
   HAL_OK       = 0x00U,
   HAL_ERROR    = 0x01U,
@@ -44,13 +44,13 @@ typedef enum
   HAL_TIMEOUT  = 0x03
 } HAL_StatusTypeDef;
 
-/** 
-  * @brief  HAL Lock structures definition  
+/**
+  * @brief  HAL Lock structures definition
   */
-typedef enum 
+typedef enum
 {
   HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01  
+  HAL_LOCKED   = 0x01
 } HAL_LockTypeDef;
 
 /* Exported macro ------------------------------------------------------------*/
@@ -98,7 +98,7 @@ typedef enum
                                     {                                      \
                                        (__HANDLE__)->Lock = HAL_LOCKED;    \
                                     }                                      \
-       	                          }while (0U)
+                                  }while (0U)
 
   #define __HAL_UNLOCK(__HANDLE__)                                          \
                                   do{                                       \
@@ -135,30 +135,30 @@ typedef enum
   #ifndef __ALIGN_END
     #define __ALIGN_END    __attribute__ ((aligned (4)))
   #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN  
+  #ifndef __ALIGN_BEGIN
     #define __ALIGN_BEGIN
   #endif /* __ALIGN_BEGIN */
 #else
   #ifndef __ALIGN_END
     #define __ALIGN_END
   #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN      
+  #ifndef __ALIGN_BEGIN
     #if defined   (__CC_ARM)      /* ARM Compiler V5*/
-      #define __ALIGN_BEGIN    __align(4)  
+      #define __ALIGN_BEGIN    __align(4)
     #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN 
+      #define __ALIGN_BEGIN
     #endif /* __CC_ARM */
   #endif /* __ALIGN_BEGIN */
 #endif /* __GNUC__ */
 
-/** 
+/**
   * @brief  __NOINLINE definition
-  */ 
+  */
 #if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
 /* ARM V4/V5 and V6 & GNU Compiler
    -------------------------------
 */
-#define __NOINLINE __attribute__ ( (noinline) )  
+#define __NOINLINE __attribute__ ( (noinline) )
 
 #elif defined ( __ICCARM__ )
 /* ICCARM Compiler

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h

@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_DMA_H
@@ -34,105 +34,105 @@
 
 /** @addtogroup DMA
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 
 /** @defgroup DMA_Exported_Types DMA Exported Types
   * @{
   */
 
-/** 
-  * @brief  DMA Configuration Structure definition  
+/**
+  * @brief  DMA Configuration Structure definition
   */
 typedef struct
 {
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral, 
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
                                            from memory to memory or from peripheral to memory.
                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
 
   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-                               
+
   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
-  
+
   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
 
   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
                                            This parameter can be a value of @ref DMA_Memory_data_size */
-                               
+
   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
                                            This parameter can be a value of @ref DMA_mode
                                            @note The circular buffer mode cannot be used if the memory-to-memory
-                                           data transfer is configured on the selected Channel */ 
+                                           data transfer is configured on the selected Channel */
 
   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
                                             This parameter can be a value of @ref DMA_Priority_level */
 } DMA_InitTypeDef;
 
 /**
-  * @brief  HAL DMA State structures definition  
+  * @brief  HAL DMA State structures definition
   */
 typedef enum
 {
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */  
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */     
-  HAL_DMA_STATE_TIMEOUT           = 0x03   /*!< DMA timeout state                   */  
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_TIMEOUT           = 0x03   /*!< DMA timeout state                   */
 }HAL_DMA_StateTypeDef;
 
-/** 
-  * @brief  HAL DMA Error Code structure definition  
-  */ 
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
 typedef enum
 {
   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;      
+}HAL_DMA_LevelCompleteTypeDef;
 
-/** 
+/**
   * @brief  HAL DMA Callback ID structure definition
   */
 typedef enum
 {
   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */ 
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */ 
-  HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */ 
-}HAL_DMA_CallbackIDTypeDef;                                                                 
-
-/** 
-  * @brief  DMA handle Structure definition  
-  */ 
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
 typedef struct __DMA_HandleTypeDef
-{  
+{
   DMA_Channel_TypeDef   *Instance;                                                    /*!< Register base address                  */
-  
-  DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */ 
-  
-  HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */  
-  
+
+  DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */
+
+  HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */
+
   HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
-  
-  void                  *Parent;                                                      /*!< Parent object state                    */  
-  
+
+  void                  *Parent;                                                      /*!< Parent object state                    */
+
   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
-  
+
   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
-  
+
   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
-  
-  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */  
-  
+
+  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */
+
   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
-  
+
   DMA_TypeDef          *DmaBaseAddress;                                               /*!< DMA Channel Base Address               */
-  
+
   uint32_t              ChannelIndex;                                                 /*!< DMA Channel Index                      */
-} DMA_HandleTypeDef;    
+} DMA_HandleTypeDef;
 /**
   * @}
   */
@@ -145,19 +145,19 @@ typedef struct __DMA_HandleTypeDef
 
 /** @defgroup DMA_Error_Code DMA Error Code
   * @{
-  */ 
+  */
 #define HAL_DMA_ERROR_NONE          (0x00000000U)    /*!< No error             */
 #define HAL_DMA_ERROR_TE            (0x00000001U)    /*!< Transfer error       */
 #define HAL_DMA_ERROR_NO_XFER       (0x00000004U)    /*!< no ongoin transfer   */
 #define HAL_DMA_ERROR_TIMEOUT       (0x00000020U)    /*!< Timeout error        */
-#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)    /*!< Not supported mode */     
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)    /*!< Not supported mode */
 /**
   * @}
   */
 
 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
   * @{
-  */ 
+  */
 #define DMA_PERIPH_TO_MEMORY         (0x00000000U)        /*!< Peripheral to memory direction */
 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
@@ -165,19 +165,19 @@ typedef struct __DMA_HandleTypeDef
 /**
   * @}
   */
-  
+
 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
   * @{
-  */ 
+  */
 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
 #define DMA_PINC_DISABLE       (0x00000000U)    /*!< Peripheral increment mode Disable */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
   * @{
-  */ 
+  */
 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 #define DMA_MINC_DISABLE        (0x00000000U)    /*!< Memory increment mode Disable */
 /**
@@ -186,16 +186,16 @@ typedef struct __DMA_HandleTypeDef
 
 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
   * @{
-  */ 
+  */
 #define DMA_PDATAALIGN_BYTE          (0x00000000U)       /*!< Peripheral data alignment : Byte     */
 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
 /**
   * @}
-  */ 
+  */
 
 /** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @{ 
+  * @{
   */
 #define DMA_MDATAALIGN_BYTE          (0x00000000U)       /*!< Memory data alignment : Byte     */
 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
@@ -206,7 +206,7 @@ typedef struct __DMA_HandleTypeDef
 
 /** @defgroup DMA_mode DMA mode
   * @{
-  */ 
+  */
 #define DMA_NORMAL         (0x00000000U)      /*!< Normal Mode                  */
 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
 /**
@@ -222,7 +222,7 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 /**
   * @}
-  */ 
+  */
 
 
 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
@@ -237,7 +237,7 @@ typedef struct __DMA_HandleTypeDef
 
 /** @defgroup DMA_flag_definitions DMA flag definitions
   * @{
-  */ 
+  */
 #define DMA_FLAG_GL1                      (0x00000001U)
 #define DMA_FLAG_TC1                      (0x00000002U)
 #define DMA_FLAG_HT1                      (0x00000004U)
@@ -306,7 +306,7 @@ typedef struct __DMA_HandleTypeDef
 /**
   * @brief  Enables the specified DMA Channel interrupts.
   * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -318,7 +318,7 @@ typedef struct __DMA_HandleTypeDef
 /**
   * @brief  Disables the specified DMA Channel interrupts.
   * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -342,7 +342,7 @@ typedef struct __DMA_HandleTypeDef
 /**
   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
   * @param  __HANDLE__ DMA handle
-  *   
+  *
   * @retval The number of remaining data units in the current DMA Channel transfer.
   */
 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
@@ -352,14 +352,14 @@ typedef struct __DMA_HandleTypeDef
   */
 
 /* Include DMA HAL Extended module */
-#include "stm32f3xx_hal_dma_ex.h"   
+#include "stm32f3xx_hal_dma_ex.h"
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup DMA_Exported_Functions
   * @{
   */
 
-/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 
+/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 /* Initialization and de-initialization functions *****************************/
@@ -369,7 +369,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
   * @}
   */
 
-/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions 
+/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
 /* Input and Output operation functions *****************************************************/
@@ -400,7 +400,7 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
   */
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup DMA_Private_Macros DMA Private Macros
-  * @brief    DMA private macros 
+  * @brief    DMA private macros
   * @{
   */
 
@@ -408,11 +408,11 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 
 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 
 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
                                             ((STATE) == DMA_PINC_DISABLE))
-											
+
 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
                                         ((STATE) == DMA_MINC_DISABLE))
 
@@ -425,21 +425,21 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 
 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR)) 
+                           ((MODE) == DMA_CIRCULAR))
 
 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 
 /**
   * @}
-  */ 
+  */
 
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h

@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_DMA_EX_H
@@ -34,9 +34,9 @@
 
 /** @addtogroup DMAEx
   * @{
-  */ 
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
@@ -70,7 +70,7 @@
   * @brief  Returns the current DMA Channel half transfer complete flag.
   * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
-  */      
+  */
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -131,7 +131,7 @@
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
   *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.   
+  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
   * @retval The state of FLAG (SET or RESET).
   */
 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
@@ -146,7 +146,7 @@
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
   *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.   
+  *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
   * @retval None
   */
 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
@@ -180,7 +180,7 @@
   * @brief  Returns the current DMA Channel half transfer complete flag.
   * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
-  */      
+  */
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -226,7 +226,7 @@
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
   *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 to select the DMA Channel flag.   
+  *         Where x can be 1_7 to select the DMA Channel flag.
   * @retval The state of FLAG (SET or RESET).
   */
 
@@ -240,7 +240,7 @@
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
   *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 to select the DMA Channel flag.   
+  *         Where x can be 1_7 to select the DMA Channel flag.
   * @retval None
   */
 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
@@ -250,14 +250,14 @@
   */
 
 #endif
-  
+
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h

@@ -27,7 +27,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal_def.h"
-   
+
 /** @addtogroup STM32F3xx_HAL_Driver
   * @{
   */
@@ -35,7 +35,7 @@
 /** @addtogroup FLASH
   * @{
   */
-  
+
 /** @addtogroup FLASH_Private_Constants
   * @{
   */
@@ -50,7 +50,7 @@
 
 #define IS_FLASH_TYPEPROGRAM(VALUE)  (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
                                       ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
-                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
+                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
 
 #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
                                        ((__LATENCY__) == FLASH_LATENCY_1) || \
@@ -58,19 +58,19 @@
 
 /**
   * @}
-  */  
+  */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup FLASH_Exported_Types FLASH Exported Types
   * @{
-  */  
+  */
 
 /**
   * @brief  FLASH Procedure structure definition
   */
-typedef enum 
+typedef enum
 {
-  FLASH_PROC_NONE              = 0U, 
+  FLASH_PROC_NONE              = 0U,
   FLASH_PROC_PAGEERASE         = 1U,
   FLASH_PROC_MASSERASE         = 2U,
   FLASH_PROC_PROGRAMHALFWORD   = 3U,
@@ -78,13 +78,13 @@ typedef enum
   FLASH_PROC_PROGRAMDOUBLEWORD = 5U
 } FLASH_ProcedureTypeDef;
 
-/** 
-  * @brief  FLASH handle Structure definition  
+/**
+  * @brief  FLASH handle Structure definition
   */
 typedef struct
 {
   __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-  
+
   __IO uint32_t               DataRemaining;    /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
 
   __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
@@ -93,7 +93,7 @@ typedef struct
 
   HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
 
-  __IO uint32_t               ErrorCode;        /*!< FLASH error code                    
+  __IO uint32_t               ErrorCode;        /*!< FLASH error code
                                                      This parameter can be a value of @ref FLASH_Error_Codes  */
 } FLASH_ProcessTypeDef;
 
@@ -104,7 +104,7 @@ typedef struct
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
   * @{
-  */  
+  */
 
 /** @defgroup FLASH_Error_Codes FLASH Error Codes
   * @{
@@ -120,7 +120,7 @@ typedef struct
 
 /** @defgroup FLASH_Type_Program FLASH Type Program
   * @{
-  */ 
+  */
 #define FLASH_TYPEPROGRAM_HALFWORD   (0x01U)  /*!<Program a half-word (16-bit) at a specified address.*/
 #define FLASH_TYPEPROGRAM_WORD       (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
 #define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U)  /*!<Program a double word (64-bit) at a specified address*/
@@ -143,35 +143,35 @@ typedef struct
 
 /** @defgroup FLASH_Flag_definition FLASH Flag definition
   * @{
-  */ 
-#define FLASH_FLAG_BSY             FLASH_SR_BSY            /*!< FLASH Busy flag                           */ 
+  */
+#define FLASH_FLAG_BSY             FLASH_SR_BSY            /*!< FLASH Busy flag                           */
 #define FLASH_FLAG_PGERR           FLASH_SR_PGERR          /*!< FLASH Programming error flag    */
 #define FLASH_FLAG_WRPERR          FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
 #define FLASH_FLAG_EOP             FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
 /**
   * @}
   */
-  
+
 /** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
   * @{
-  */ 
+  */
 #define FLASH_IT_EOP               FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
 #define FLASH_IT_ERR               FLASH_CR_ERRIE  /*!< Error Interrupt source */
 /**
   * @}
-  */  
+  */
 
 /**
   * @}
-  */  
-  
+  */
+
 /* Exported macro ------------------------------------------------------------*/
 
 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- *  @brief macros to control FLASH features 
+ *  @brief macros to control FLASH features
  *  @{
  */
- 
+
 /** @defgroup FLASH_Half_Cycle FLASH Half Cycle
  *  @brief macros to handle FLASH half cycle
  * @{
@@ -196,28 +196,28 @@ typedef struct
 /** @defgroup FLASH_EM_Latency FLASH Latency
  *  @brief macros to handle FLASH Latency
  * @{
- */ 
-  
+ */
+
 /**
   * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__ FLASH Latency                   
+  * @param  __LATENCY__ FLASH Latency
   *         This parameter can be one of the following values:
   *         @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
   *         @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
   *         @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
   * @retval None
-  */ 
+  */
 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
 
 
 /**
   * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency                   
+  * @retval FLASH Latency
   *         This parameter can be one of the following values:
   *         @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
   *         @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
   *         @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
-  */ 
+  */
 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
 
 /**
@@ -227,11 +227,11 @@ typedef struct
 /** @defgroup FLASH_Prefetch FLASH Prefetch
  *  @brief macros to handle FLASH Prefetch buffer
  * @{
- */   
+ */
 /**
   * @brief  Enable the FLASH prefetch buffer.
   * @retval None
-  */ 
+  */
 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    (FLASH->ACR |= FLASH_ACR_PRFTBE)
 
 /**
@@ -243,39 +243,39 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup FLASH_Interrupt FLASH Interrupts
  *  @brief macros to handle FLASH interrupts
  * @{
- */ 
+ */
 
 /**
   * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
+  * @param  __INTERRUPT__  FLASH interrupt
   *         This parameter can be any combination of the following values:
   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt    
+  *     @arg @ref FLASH_IT_ERR Error Interrupt
   * @retval none
-  */  
+  */
 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  SET_BIT((FLASH->CR), (__INTERRUPT__))
 
 /**
   * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
+  * @param  __INTERRUPT__  FLASH interrupt
   *         This parameter can be any combination of the following values:
   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_ERR Error Interrupt    
+  *     @arg @ref FLASH_IT_ERR Error Interrupt
   * @retval none
-  */  
+  */
 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
 
 /**
-  * @brief  Get the specified FLASH flag status. 
+  * @brief  Get the specified FLASH flag status.
   * @param  __FLAG__ specifies the FLASH flag to check.
   *          This parameter can be one of the following values:
   *            @arg @ref FLASH_FLAG_BSY         FLASH Busy flag
-  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag 
+  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag
+  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag
   *            @arg @ref FLASH_FLAG_PGERR       FLASH Programming error flag
   * @retval The new state of __FLAG__ (SET or RESET).
   */
@@ -285,8 +285,8 @@ typedef struct
   * @brief  Clear the specified FLASH flag.
   * @param  __FLAG__ specifies the FLASH flags to clear.
   *          This parameter can be any combination of the following values:
-  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag 
+  *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag
+  *            @arg @ref FLASH_FLAG_WRPERR      FLASH Write protected error flag
   *            @arg @ref FLASH_FLAG_PGERR       FLASH Programming error flag
   * @retval none
   */
@@ -294,20 +294,20 @@ typedef struct
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /* Include FLASH HAL Extended module */
-#include "stm32f3xx_hal_flash_ex.h"  
+#include "stm32f3xx_hal_flash_ex.h"
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup FLASH_Exported_Functions
   * @{
   */
-  
+
 /** @addtogroup FLASH_Exported_Functions_Group1
   * @{
   */
@@ -317,7 +317,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
 
 /* FLASH IRQ handler function */
 void       HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
+/* Callbacks in non blocking modes */
 void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
 void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h

@@ -34,7 +34,7 @@
 
 /** @addtogroup FLASHEx
   * @{
-  */ 
+  */
 
 /** @addtogroup FLASHEx_Private_Constants
   * @{
@@ -44,20 +44,20 @@
 
 /**
   * @}
-  */  
+  */
 
 /** @addtogroup FLASHEx_Private_Macros
   * @{
   */
 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
-                             ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
+                             ((VALUE) == FLASH_TYPEERASE_MASSERASE))
 
 #define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
 
 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
-                            ((VALUE) == OB_WRPSTATE_ENABLE))  
+                            ((VALUE) == OB_WRPSTATE_ENABLE))
 
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) 
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
 
 #define IS_OB_RDP_LEVEL(LEVEL)     (((LEVEL) == OB_RDP_LEVEL_0)   ||\
                                     ((LEVEL) == OB_RDP_LEVEL_1))/*||\
@@ -127,7 +127,7 @@
   * @}
   */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
   * @{
   */
@@ -141,10 +141,10 @@ typedef struct
 
   uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
                              This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
-  
+
   uint32_t NbPages;     /*!< NbPages: Number of pagess to be erased.
                              This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
-                                                          
+
 } FLASH_EraseInitTypeDef;
 
 /**
@@ -164,9 +164,9 @@ typedef struct
   uint8_t RDPLevel;     /*!< RDPLevel: Set the read protection level..
                              This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
 
-  uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte: 
+  uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte:
                              IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
-                             This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, 
+                             This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
                              @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
                              @ref FLASHEx_OB_RAM_Parity_Check_Enable.
                              @if STM32F373xC
@@ -179,13 +179,13 @@ typedef struct
 
   uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
                              This parameter can be a value of @ref FLASHEx_OB_Data_Address */
-  
+
   uint8_t DATAData;     /*!< DATAData: Data to be stored in the option byte DATA
-                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */  
+                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
 } FLASH_OBProgramInitTypeDef;
 /**
   * @}
-  */  
+  */
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
@@ -202,17 +202,17 @@ typedef struct
 
 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase
   * @{
-  */ 
+  */
 #define FLASH_TYPEERASE_PAGES     (0x00U)  /*!<Pages erase only*/
 #define FLASH_TYPEERASE_MASSERASE (0x01U)  /*!<Flash mass erase activation*/
 
 /**
   * @}
   */
-  
+
 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
   * @{
-  */ 
+  */
 
 /** @defgroup FLASHEx_OB_Type Option Bytes Type
   * @{
@@ -228,7 +228,7 @@ typedef struct
 
 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
   * @{
-  */ 
+  */
 #define OB_WRPSTATE_DISABLE   (0x00U)  /*!<Disable the write protection of the desired pages*/
 #define OB_WRPSTATE_ENABLE    (0x01U)  /*!<Enable the write protection of the desired pagess*/
 
@@ -274,7 +274,7 @@ typedef struct
 #define OB_WRP_PAGES58TO59             (0x20000000U) /* Write protection of page 58 to 59 */
 #define OB_WRP_PAGES60TO61             (0x40000000U) /* Write protection of page 60 to 61 */
 #define OB_WRP_PAGES62TO127            (0x80000000U) /* Write protection of page 62 to 127 */
-#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ 
+#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F373xC || STM32F378xx                   */
 
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
@@ -334,24 +334,24 @@ typedef struct
   */
 #define OB_RDP_LEVEL_0             ((uint8_t)0xAAU)
 #define OB_RDP_LEVEL_1             ((uint8_t)0xBBU)
-#define OB_RDP_LEVEL_2             ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 
+#define OB_RDP_LEVEL_2             ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
                                                       it's no more possible to go back to level 1 or 0U */
 /**
   * @}
   */
-  
+
 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
   * @{
-  */ 
+  */
 #define OB_IWDG_SW                 ((uint8_t)0x01U)  /*!< Software IWDG selected */
 #define OB_IWDG_HW                 ((uint8_t)0x00U)  /*!< Hardware IWDG selected */
 /**
   * @}
   */
-  
+
 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
   * @{
-  */ 
+  */
 #define OB_STOP_NO_RST             ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
 #define OB_STOP_RST                ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
 /**
@@ -360,7 +360,7 @@ typedef struct
 
 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
   * @{
-  */ 
+  */
 #define OB_STDBY_NO_RST            ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
 #define OB_STDBY_RST               ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
 /**
@@ -404,7 +404,7 @@ typedef struct
 
 /**
   * @}
-  */ 
+  */
 #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
 
 /** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
@@ -428,21 +428,21 @@ typedef struct
 /** @addtogroup FLASHEx_Exported_Functions
   * @{
   */
-  
+
 /** @addtogroup FLASHEx_Exported_Functions_Group1
   * @{
-  */   
+  */
 /* IO operation functions *****************************************************/
 HAL_StatusTypeDef  HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
 HAL_StatusTypeDef  HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
 
 /**
   * @}
-  */ 
+  */
 
 /** @addtogroup FLASHEx_Exported_Functions_Group2
   * @{
-  */   
+  */
 /* Peripheral Control functions ***********************************************/
 HAL_StatusTypeDef  HAL_FLASHEx_OBErase(void);
 HAL_StatusTypeDef  HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
@@ -456,7 +456,7 @@ uint32_t           HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
 /**
   * @}
   */
-  
+
 /**
   * @}
   */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h

@@ -58,7 +58,7 @@ typedef struct
   uint32_t Speed;      /*!< Specifies the speed for the selected pins.
                            This parameter can be a value of @ref GPIO_speed */
 
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins 
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
                             This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
 }GPIO_InitTypeDef;
 
@@ -160,7 +160,7 @@ typedef enum
 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
   * @{
   */
-  
+
 /**
   * @brief  Check whether the specified EXTI line flag is set or not.
   * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
@@ -241,16 +241,16 @@ typedef enum
 /* Include GPIO HAL Extended module */
 #include "stm32f3xx_hal_gpio_ex.h"
 
-/* Exported functions --------------------------------------------------------*/ 
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
   * @{
   */
 
-/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
  *  @brief    Initialization and Configuration functions
  * @{
  */
-     
+
 /* Initialization and de-initialization functions *****************************/
 void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
 void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
@@ -259,10 +259,10 @@ void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
   * @}
   */
 
-/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions 
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
  * @{
  */
-   
+
 /* IO operation functions *****************************************************/
 GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
 void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
@@ -281,12 +281,12 @@ void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */  
-  
+  */
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h

@@ -259,13 +259,13 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
   * @{
   */
 
-#define OPAMP_SEC_NONINVERTINGINPUT_IO0          OPAMP_CSR_VPSSEL       /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)    
+#define OPAMP_SEC_NONINVERTINGINPUT_IO0          OPAMP_CSR_VPSSEL       /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
                                                                               connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO1          (0x00000000U)          /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)  
+#define OPAMP_SEC_NONINVERTINGINPUT_IO1          (0x00000000U)          /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
                                                                              connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO2          OPAMP_CSR_VPSSEL_1     /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)     
+#define OPAMP_SEC_NONINVERTINGINPUT_IO2          OPAMP_CSR_VPSSEL_1     /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
                                                                               connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO3          OPAMP_CSR_VPSSEL_0     /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)   
+#define OPAMP_SEC_NONINVERTINGINPUT_IO3          OPAMP_CSR_VPSSEL_0     /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
                                                                               connected to OPAMPx non inverting input */
 
 #define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h

@@ -34,13 +34,13 @@
 
 /** @addtogroup PWR PWR
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup PWR_Exported_Constants PWR Exported Constants
   * @{
-  */ 
+  */
 
 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
   * @{
@@ -131,7 +131,7 @@
 /**
   * @}
   */
-  
+
 /* Private macros --------------------------------------------------------*/
 /** @addtogroup  PWR_Private_Macros   PWR Private Macros
   * @{
@@ -140,17 +140,17 @@
 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
                                 ((PIN) == PWR_WAKEUP_PIN2) || \
                                 ((PIN) == PWR_WAKEUP_PIN3))
-                                
+
 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-                                     
+
 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
 
 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
 
 /**
   * @}
-  */    
+  */
 
 /* Include PWR HAL Extended module */
 #include "stm32f3xx_hal_pwr_ex.h"
@@ -160,8 +160,8 @@
 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
   * @{
   */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 
@@ -172,7 +172,7 @@ void HAL_PWR_DeInit(void);
   * @}
   */
 
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
   * @{
   */
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h

@@ -45,7 +45,7 @@
     defined(STM32F302xC) || defined(STM32F303xC) || \
     defined(STM32F303x8) || defined(STM32F334x8) || \
     defined(STM32F301x8) || defined(STM32F302x8) || \
-    defined(STM32F373xC) 
+    defined(STM32F373xC)
 /**
   * @brief  PWR PVD configuration structure definition
   */
@@ -77,17 +77,17 @@ typedef struct
     defined(STM32F303x8) || defined(STM32F334x8) || \
     defined(STM32F301x8) || defined(STM32F302x8) || \
     defined(STM32F373xC)
-    
+
 /** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
   * @{
   */
-#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0    /*!< PVD threshold around 2.2 V */                                    
-#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1    /*!< PVD threshold around 2.3 V */                                    
-#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2    /*!< PVD threshold around 2.4 V */                                    
-#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3    /*!< PVD threshold around 2.5 V */                                    
-#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4    /*!< PVD threshold around 2.6 V */                                    
-#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5    /*!< PVD threshold around 2.7 V */                                    
-#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6    /*!< PVD threshold around 2.8 V */                                    
+#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0    /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1    /*!< PVD threshold around 2.3 V */
+#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2    /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3    /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4    /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5    /*!< PVD threshold around 2.7 V */
+#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6    /*!< PVD threshold around 2.8 V */
 #define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7    /*!< PVD threshold around 2.9 V */
 /**
   * @}
@@ -119,7 +119,7 @@ typedef struct
 /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
   * @{
   */
-#define PWR_SDADC_ANALOG1              ((uint32_t)PWR_CR_ENSD1)   /*!< Enable SDADC1 */ 
+#define PWR_SDADC_ANALOG1              ((uint32_t)PWR_CR_ENSD1)   /*!< Enable SDADC1 */
 #define PWR_SDADC_ANALOG2              ((uint32_t)PWR_CR_ENSD2)   /*!< Enable SDADC2 */
 #define PWR_SDADC_ANALOG3              ((uint32_t)PWR_CR_ENSD3)   /*!< Enable SDADC3 */
 /**
@@ -141,7 +141,7 @@ typedef struct
     defined(STM32F303x8) || defined(STM32F334x8) || \
     defined(STM32F301x8) || defined(STM32F302x8) || \
     defined(STM32F373xC)
-    
+
 /**
   * @brief Enable interrupt on PVD Exti Line 16.
   * @retval None.
@@ -229,7 +229,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /* Private macros --------------------------------------------------------*/
 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
   * @{
@@ -264,7 +264,7 @@ typedef struct
 
 /**
   * @}
-  */    
+  */
 
 /* Exported functions --------------------------------------------------------*/
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h

@@ -42,8 +42,8 @@
 
 /** @defgroup RCC_Timeout RCC Timeout
   * @{
-  */ 
-  
+  */
+
 /* Disable Backup domain write protection state change timeout */
 #define RCC_DBP_TIMEOUT_VALUE      (100U)       /* 100 ms */
 /* LSE state change timeout */
@@ -56,7 +56,7 @@
 /**
   * @}
   */
-  
+
 /** @defgroup RCC_Register_Offset Register offsets
   * @{
   */
@@ -124,7 +124,7 @@
 /**
   * @}
   */
-  
+
 /* CR register byte 2 (Bits[23:16]) base address */
 #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
 
@@ -245,8 +245,8 @@
   * @{
   */
 
-/** 
-  * @brief  RCC PLL configuration structure definition  
+/**
+  * @brief  RCC PLL configuration structure definition
   */
 typedef struct
 {
@@ -254,7 +254,7 @@ typedef struct
                               This parameter can be a value of @ref RCC_PLL_Config */
 
   uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
-                              This parameter must be a value of @ref RCC_PLL_Clock_Source */          
+                              This parameter must be a value of @ref RCC_PLL_Clock_Source */
 
   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
                               This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
@@ -265,9 +265,9 @@ typedef struct
 
 #endif
 } RCC_PLLInitTypeDef;
-   
+
 /**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
   */
 typedef struct
 {
@@ -294,12 +294,12 @@ typedef struct
   uint32_t LSIState;              /*!< The new state of the LSI.
                                        This parameter can be a value of @ref RCC_LSI_Config */
 
-  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */     
+  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
 
 } RCC_OscInitTypeDef;
 
 /**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
   */
 typedef struct
 {
@@ -460,7 +460,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
   * @{
   */
@@ -533,7 +533,7 @@ typedef struct
 /**
   * @}
   */
-  
+
 #endif
 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
 /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor
@@ -620,8 +620,8 @@ typedef struct
 #define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup RCC_Flag Flags
   *        Elements values convention: XXXYYYYYb
   *           - YYYYY  : Flag position in the register
@@ -677,7 +677,7 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
-  * @{  
+  * @{
   */
 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
@@ -769,7 +769,7 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
-  * @{   
+  * @{
   */
 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
@@ -839,13 +839,13 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
-  * @{   
+  * @{
   */
 #define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
@@ -976,7 +976,7 @@ typedef struct
 
 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
   * @brief  Force or release AHB peripheral reset.
-  * @{   
+  * @{
   */
 #define __HAL_RCC_AHB_FORCE_RESET()     (RCC->AHBRSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
@@ -999,7 +999,7 @@ typedef struct
 
 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
   * @brief  Force or release APB1 peripheral reset.
-  * @{   
+  * @{
   */
 #define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
@@ -1026,7 +1026,7 @@ typedef struct
 
 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
   * @brief  Force or release APB2 peripheral reset.
-  * @{   
+  * @{
   */
 #define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
@@ -1046,7 +1046,7 @@ typedef struct
   */
 
 /** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{   
+  * @{
   */
 
 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
@@ -1056,12 +1056,12 @@ typedef struct
   *         of the HSE used directly or indirectly as system clock (if the Clock
   *         Security System CSS is enabled).
   * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.  
+  *         you have to select another source of the system clock then stop the HSI.
   * @note   After enabling the HSI, the application software should wait on HSIRDY
   *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.  
+  *         system clock source.
   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.  
+  *         clock cycles.
   */
 #define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
@@ -1072,7 +1072,7 @@ typedef struct
   * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
   *         (default is RCC_HSICALIBRATION_DEFAULT).
   *         This parameter must be a number between 0 and 0x1F.
-  */  
+  */
 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
           (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
 
@@ -1081,20 +1081,20 @@ typedef struct
   */
 
 /** @defgroup RCC_LSI_Configuration  LSI Configuration
-  * @{   
+  * @{
   */
 
 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on 
+  * @note   After enabling the LSI, the application software should wait on
   *         LSIRDY flag to be set indicating that LSI clock is stable and can
   *         be used to clock the IWDG and/or the RTC.
   */
 #define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
 
 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
-  * @note   LSI can not be disabled if the IWDG is running.  
+  * @note   LSI can not be disabled if the IWDG is running.
   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles. 
+  *         clock cycles.
   */
 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
 
@@ -1103,7 +1103,7 @@ typedef struct
   */
 
 /** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{   
+  * @{
   */
 
 /**
@@ -1156,16 +1156,16 @@ typedef struct
   */
 
 /** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{   
+  * @{
   */
 
 /**
   * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 
+  * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
   * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using 
+  *         this domain after reset, you have to enable write access using
   *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).  
+  *         (to be done once after reset).
   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
   *         software should wait on LSERDY flag to be set indicating that LSE clock
   *         is stable and can be used to clock the RTC.
@@ -1204,9 +1204,9 @@ typedef struct
   */
 
 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
-  * @{   
+  * @{
   */
-    
+
 /** @brief  Macro to configure the USART1 clock (USART1CLK).
   * @param  __USART1CLKSOURCE__ specifies the USART1 clock source.
   *         This parameter can be one of the following values:
@@ -1357,7 +1357,7 @@ typedef struct
   */
 
 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
-  * @{   
+  * @{
   */
 
 /** @brief  Macro to configure the I2C1 clock (I2C1CLK).
@@ -1380,11 +1380,11 @@ typedef struct
   */
 
 /** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{   
+  * @{
   */
 
 /** @brief Macro to enable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on 
+  * @note   After enabling the main PLL, the application software should wait on
   *         PLLRDY flag to be set indicating that PLL clock is stable and can
   *         be used as system clock source.
   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
@@ -1410,7 +1410,7 @@ typedef struct
   */
 
 /** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{   
+  * @{
   */
 
 /**
@@ -1438,8 +1438,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 #if defined(RCC_CFGR_MCOPRE)
 /** @brief  Macro to configure the MCO clock.
@@ -1494,15 +1494,15 @@ typedef struct
   */
 
   /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-  * @{   
+  * @{
   */
 
 /** @brief Macro to configure the RTC clock (RTCCLK).
   * @note   As the RTC clock configuration bits are in the Backup domain and write
   *         access is denied to this domain after reset, you have to enable write
   *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).    
-  * @note   Once the RTC clock is configured it cannot be changed unless the  
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it cannot be changed unless the
   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
   *         a Power On Reset (POR).
   *
@@ -1520,7 +1520,7 @@ typedef struct
   *             equal to the RTCCLK frequency for a proper operation of the RTC.
   */
 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-                                                   
+
 /** @brief Macro to get the RTC clock source.
   * @retval The clock source can be one of the following values:
   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
@@ -1729,7 +1729,7 @@ void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct,
 /**
   * @}
   */
-  
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h

@@ -343,13 +343,13 @@
   * @}
   */
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
   * @{
   */
 
-/** 
-  * @brief  RCC extended clocks structure definition  
+/**
+  * @brief  RCC extended clocks structure definition
   */
 #if defined(STM32F301x8) || defined(STM32F318xx)
 typedef struct
@@ -357,37 +357,37 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;    /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;    /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
-  uint32_t Usart1ClockSelection; /*!< USART1 clock source      
+  uint32_t Usart1ClockSelection; /*!< USART1 clock source
                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
 
-  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source      
+  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
 
-  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source      
+  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source      
+  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
 
-  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source      
+  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
 
-  uint32_t I2sClockSelection;    /*!< I2S clock source      
+  uint32_t I2sClockSelection;    /*!< I2S clock source
                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
 
-  uint32_t Tim1ClockSelection;   /*!< TIM1 clock source      
+  uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
 
-  uint32_t Tim15ClockSelection;  /*!< TIM15 clock source      
+  uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
 
-  uint32_t Tim16ClockSelection;  /*!< TIM16 clock source      
+  uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
 
-  uint32_t Tim17ClockSelection;  /*!< TIM17 clock source      
+  uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
 }RCC_PeriphCLKInitTypeDef;
 #endif /* STM32F301x8 || STM32F318xx */
@@ -398,40 +398,40 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;    /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;    /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
-  uint32_t Usart1ClockSelection; /*!< USART1 clock source      
+  uint32_t Usart1ClockSelection; /*!< USART1 clock source
                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
 
-  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source      
+  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
 
-  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source      
+  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source      
+  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
 
-  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source      
+  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
 
-  uint32_t I2sClockSelection;    /*!< I2S clock source      
+  uint32_t I2sClockSelection;    /*!< I2S clock source
                                       This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
 
-  uint32_t Tim1ClockSelection;   /*!< TIM1 clock source      
+  uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
 
-  uint32_t Tim15ClockSelection;  /*!< TIM15 clock source      
+  uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
 
-  uint32_t Tim16ClockSelection;  /*!< TIM16 clock source      
+  uint32_t Tim16ClockSelection;  /*!< TIM16 clock source
                                       This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
 
-  uint32_t Tim17ClockSelection;  /*!< TIM17 clock source      
+  uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
 
-  uint32_t USBClockSelection;    /*!< USB clock source      
+  uint32_t USBClockSelection;    /*!< USB clock source
                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -443,7 +443,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -476,7 +476,7 @@ typedef struct
   uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
 
-  uint32_t USBClockSelection;    /*!< USB clock source      
+  uint32_t USBClockSelection;    /*!< USB clock source
                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -488,7 +488,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -527,7 +527,7 @@ typedef struct
   uint32_t Tim8ClockSelection;   /*!< TIM8 clock source
                                       This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
 
-  uint32_t USBClockSelection;    /*!< USB clock source      
+  uint32_t USBClockSelection;    /*!< USB clock source
                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -539,7 +539,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -563,7 +563,7 @@ typedef struct
   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source      
+  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
 
   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
@@ -580,7 +580,7 @@ typedef struct
 
   uint32_t Tim34ClockSelection;   /*!< TIM3 & TIM4 clock source
                                        This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
-				       
+
   uint32_t Tim15ClockSelection;  /*!< TIM15 clock source
                                       This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
 
@@ -590,7 +590,7 @@ typedef struct
   uint32_t Tim17ClockSelection;  /*!< TIM17 clock source
                                       This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
 
-  uint32_t USBClockSelection;    /*!< USB clock source      
+  uint32_t USBClockSelection;    /*!< USB clock source
                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -602,7 +602,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -626,7 +626,7 @@ typedef struct
   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source      
+  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
 
   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
@@ -662,7 +662,7 @@ typedef struct
   uint32_t Tim20ClockSelection;  /*!< TIM20 clock source
                                       This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
 
-  uint32_t USBClockSelection;    /*!< USB clock source      
+  uint32_t USBClockSelection;    /*!< USB clock source
                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -674,7 +674,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -698,7 +698,7 @@ typedef struct
   uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source      
+  uint32_t I2c3ClockSelection;   /*!< I2C3 clock source
                                       This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
 
   uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
@@ -743,7 +743,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -791,19 +791,19 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
-  uint32_t Usart1ClockSelection; /*!< USART1 clock source      
+  uint32_t Usart1ClockSelection; /*!< USART1 clock source
                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
 
-  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source      
+  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
 
-  uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source      
+  uint32_t Adc12ClockSelection;  /*!< ADC1 & ADC2 clock source
                                       This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
 
-  uint32_t Tim1ClockSelection;   /*!< TIM1 clock source      
+  uint32_t Tim1ClockSelection;   /*!< TIM1 clock source
                                       This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -815,7 +815,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -842,7 +842,7 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
   uint32_t Usart1ClockSelection; /*!< USART1 clock source
@@ -860,40 +860,40 @@ typedef struct
 }RCC_PeriphCLKInitTypeDef;
 #endif /* STM32F328xx */
 
-#if defined(STM32F373xC) 
+#if defined(STM32F373xC)
 typedef struct
 {
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
-  uint32_t Usart1ClockSelection; /*!< USART1 clock source      
+  uint32_t Usart1ClockSelection; /*!< USART1 clock source
                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
 
-  uint32_t Usart2ClockSelection; /*!< USART2 clock source      
+  uint32_t Usart2ClockSelection; /*!< USART2 clock source
                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
 
-  uint32_t Usart3ClockSelection; /*!< USART3 clock source      
+  uint32_t Usart3ClockSelection; /*!< USART3 clock source
                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
 
-  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source      
+  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
 
-  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source      
+  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source      
+  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
 
-  uint32_t SdadcClockSelection;   /*!< SDADC clock prescaler      
+  uint32_t SdadcClockSelection;   /*!< SDADC clock prescaler
                                       This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
 
-  uint32_t CecClockSelection;    /*!< HDMI CEC clock source      
+  uint32_t CecClockSelection;    /*!< HDMI CEC clock source
                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
 
-  uint32_t USBClockSelection;    /*!< USB clock source      
+  uint32_t USBClockSelection;    /*!< USB clock source
                                       This parameter can be a value of @ref RCCEx_USB_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -905,31 +905,31 @@ typedef struct
   uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection 
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection
                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
 
-  uint32_t Usart1ClockSelection; /*!< USART1 clock source      
+  uint32_t Usart1ClockSelection; /*!< USART1 clock source
                                       This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
 
-  uint32_t Usart2ClockSelection; /*!< USART2 clock source      
+  uint32_t Usart2ClockSelection; /*!< USART2 clock source
                                       This parameter can be a value of @ref RCC_USART2_Clock_Source */
 
-  uint32_t Usart3ClockSelection; /*!< USART3 clock source      
+  uint32_t Usart3ClockSelection; /*!< USART3 clock source
                                       This parameter can be a value of @ref RCC_USART3_Clock_Source */
 
-  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source      
+  uint32_t I2c1ClockSelection;   /*!< I2C1 clock source
                                       This parameter can be a value of @ref RCC_I2C1_Clock_Source */
 
-  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source      
+  uint32_t I2c2ClockSelection;   /*!< I2C2 clock source
                                       This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
 
-  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source      
+  uint32_t Adc1ClockSelection;   /*!< ADC1 clock source
                                       This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
 
-  uint32_t SdadcClockSelection;   /*!< SDADC clock prescaler      
+  uint32_t SdadcClockSelection;   /*!< SDADC clock prescaler
                                       This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
 
-  uint32_t CecClockSelection;    /*!< HDMI CEC clock source      
+  uint32_t CecClockSelection;    /*!< HDMI CEC clock source
                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
 
 }RCC_PeriphCLKInitTypeDef;
@@ -1753,7 +1753,7 @@ typedef struct
 #define RCC_MCODIV_128                   (0x70000000U)
 
 #else
-  
+
 #define RCC_MCODIV_1                    (0x00000000U)
 
 #endif /* RCC_CFGR_MCOPRE */
@@ -1785,8 +1785,8 @@ typedef struct
  */
 
 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
-  * @{   
-  */ 
+  * @{
+  */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
 /** @brief  Macro to configure the PLL clock source, multiplication and division factors.
   * @note   This macro must be used only when the PLL is disabled.
@@ -1831,15 +1831,15 @@ typedef struct
        /* STM32F373xC || STM32F378xx                   */
 /**
   * @}
-  */ 
-                    
+  */
+
 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
   || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
   || defined(STM32F373xC) || defined(STM32F378xx)
 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
-  * @{   
-  */ 
+  * @{
+  */
 
 /**
   * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
@@ -1864,13 +1864,13 @@ typedef struct
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
        /* STM32F373xC || STM32F378xx                   */
-                    
+
 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
   * @brief  Enable or disable the AHB peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
-  * @{   
+  * @{
   */
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
@@ -2007,7 +2007,7 @@ typedef struct
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
-  * @{   
+  * @{
   */
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
@@ -2230,7 +2230,7 @@ typedef struct
 #if defined(STM32F303xE) || defined(STM32F398xx)                        \
   || defined(STM32F303xC) || defined(STM32F358xx)                        \
   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
-  || defined(STM32F373xC) || defined(STM32F378xx)     
+  || defined(STM32F373xC) || defined(STM32F378xx)
 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
@@ -2289,13 +2289,13 @@ typedef struct
 /**
   * @}
   */
-  
+
 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
-  * @{   
+  * @{
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
@@ -2430,7 +2430,7 @@ typedef struct
 
 #define __HAL_RCC_SPI4_CLK_DISABLE()         (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      
+
 #if defined(STM32F303xE) || defined(STM32F398xx)
 #define __HAL_RCC_TIM20_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
@@ -2441,18 +2441,18 @@ typedef struct
                                       } while(0U)
 #define __HAL_RCC_TIM20_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
 #endif /* STM32F303xE || STM32F398xx */
-      
+
 /**
   * @}
   */
-      
+
 /** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
   * @brief  Get the enable or disable status of the AHB peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
   * @{
-  */ 
+  */
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()          ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
 
@@ -2505,7 +2505,7 @@ typedef struct
 /**
   * @}
   */
-      
+
 /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable  Status
   * @brief  Get the enable or disable status of the APB1 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
@@ -2584,7 +2584,7 @@ typedef struct
 #if defined(STM32F303xE) || defined(STM32F398xx)                        \
   || defined(STM32F303xC) || defined(STM32F358xx)                        \
   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
-  || defined(STM32F373xC) || defined(STM32F378xx)     
+  || defined(STM32F373xC) || defined(STM32F378xx)
 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
 
 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
@@ -2615,7 +2615,7 @@ typedef struct
 #define __HAL_RCC_I2C3_IS_CLK_ENABLED()          ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
 
 #define __HAL_RCC_I2C3_IS_CLK_DISABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */      
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 /**
   * @}
   */
@@ -2688,7 +2688,7 @@ typedef struct
 
 #define __HAL_RCC_SPI4_IS_CLK_DISABLED()         ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-      
+
 #if defined(STM32F303xE) || defined(STM32F398xx)
 #define __HAL_RCC_TIM20_IS_CLK_ENABLED()         ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
 
@@ -2697,10 +2697,10 @@ typedef struct
 /**
   * @}
   */
-      
+
 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
   * @brief  Force or release AHB peripheral reset.
-  * @{   
+  * @{
   */
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define __HAL_RCC_ADC1_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
@@ -2765,7 +2765,7 @@ typedef struct
 
 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
   * @brief  Force or release APB1 peripheral reset.
-  * @{   
+  * @{
   */
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 #define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -2838,7 +2838,7 @@ typedef struct
 #if defined(STM32F303xE) || defined(STM32F398xx)\
   || defined(STM32F303xC) || defined(STM32F358xx)\
   || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
-  || defined(STM32F373xC) || defined(STM32F378xx)      
+  || defined(STM32F373xC) || defined(STM32F378xx)
 #define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
 
 #define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
@@ -2876,7 +2876,7 @@ typedef struct
 
 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
   * @brief  Force or release APB2 peripheral reset.
-  * @{   
+  * @{
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
@@ -2952,8 +2952,8 @@ typedef struct
 
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
@@ -2992,8 +2992,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the TIM1 clock (TIM1CLK).
   * @param  __TIM1CLKSource__ specifies the TIM1 clock source.
   *         This parameter can be one of the following values:
@@ -3063,8 +3063,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the I2S clock source (I2SCLK).
   * @note   This function must be called before enabling the I2S APB clock.
   * @param  __I2SCLKSource__ specifies the I2S clock source.
@@ -3088,8 +3088,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the ADC1 clock (ADC1CLK).
   * @param  __ADC1CLKSource__ specifies the ADC1 clock source.
@@ -3137,8 +3137,8 @@ typedef struct
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
   || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
@@ -3160,8 +3160,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
   * @param  __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
@@ -3205,8 +3205,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the TIM1 clock (TIM1CLK).
   * @param  __TIM1CLKSource__ specifies the TIM1 clock source.
@@ -3228,8 +3228,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the I2S clock source (I2SCLK).
   * @note   This function must be called before enabling the I2S APB clock.
@@ -3254,8 +3254,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the UART4 clock (UART4CLK).
   * @param  __UART4CLKSource__ specifies the UART4 clock source.
@@ -3305,8 +3305,8 @@ typedef struct
 #if defined(STM32F303xE) || defined(STM32F398xx)\
   || defined(STM32F303xC) || defined(STM32F358xx)
 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
   * @param  __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
@@ -3350,8 +3350,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the TIM8 clock (TIM8CLK).
   * @param  __TIM8CLKSource__ specifies the TIM8 clock source.
@@ -3377,8 +3377,8 @@ typedef struct
 
 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 
 /** @brief  Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
   * @param  __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
@@ -3416,14 +3416,14 @@ typedef struct
   *            @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
   *            @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
   */
-#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))                    
+#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
 /**
   * @}
   */
 
 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the TIM1 clock (TIM1CLK).
   * @param  __TIM1CLKSource__ specifies the TIM1 clock source.
   *         This parameter can be one of the following values:
@@ -3446,8 +3446,8 @@ typedef struct
 
 #if defined(STM32F334x8)
 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the HRTIM1 clock.
   * @param  __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
   *         This parameter can be one of the following values:
@@ -3470,8 +3470,8 @@ typedef struct
 
 #if defined(STM32F373xC) || defined(STM32F378xx)
 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the I2C2 clock (I2C2CLK).
   * @param  __I2C2CLKSource__ specifies the I2C2 clock source.
   *         This parameter can be one of the following values:
@@ -3492,8 +3492,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the ADC1 clock (ADC1CLK).
   * @param  __ADC1CLKSource__ specifies the ADC1 clock source.
   *          This parameter can be one of the following values:
@@ -3518,8 +3518,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the SDADCx clock (SDADCxCLK).
   * @param  __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
   *         This parameter can be one of the following values:
@@ -3570,8 +3570,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the CEC clock.
   * @param  __CECCLKSource__ specifies the CEC clock source.
   *         This parameter can be one of the following values:
@@ -3599,8 +3599,8 @@ typedef struct
   || defined(STM32F373xC)
 
 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the USB clock (USBCLK).
   * @param  __USBCLKSource__ specifies the USB clock source.
   *         This parameter can be one of the following values:
@@ -3628,8 +3628,8 @@ typedef struct
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
 
 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the I2C3 clock (I2C3CLK).
   * @param  __I2C3CLKSource__ specifies the I2C3 clock source.
   *         This parameter can be one of the following values:
@@ -3650,8 +3650,8 @@ typedef struct
   */
 
 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
-  * @{   
-  */ 
+  * @{
+  */
 /** @brief  Macro to configure the TIM2 clock (TIM2CLK).
   * @param  __TIM2CLKSource__ specifies the TIM2 clock source.
   *         This parameter can be one of the following values:
@@ -3667,7 +3667,7 @@ typedef struct
   *            @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
   */
 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
-                    
+
 /** @brief  Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
   * @param  __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
   *         This parameter can be one of the following values:
@@ -3715,7 +3715,7 @@ typedef struct
   *            @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
   */
 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
- 
+
 /** @brief  Macro to configure the TIM17 clock (TIM17CLK).
   * @param  __TIM17CLKSource__ specifies the TIM17 clock source.
   *         This parameter can be one of the following values:
@@ -3731,15 +3731,15 @@ typedef struct
   *            @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
   */
 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
-                    
+
 /**
   * @}
   */
-                   
+
 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */
-                    
+
 #if defined(STM32F303xE) || defined(STM32F398xx)
-/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config 
+/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
   * @{
   */
 /** @brief  Macro to configure the TIM20 clock (TIM20CLK).
@@ -3764,7 +3764,7 @@ typedef struct
 #endif /* STM32f303xE || STM32F398xx */
 
 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
-  * @{   
+  * @{
   */
 
 /**
@@ -3776,7 +3776,7 @@ typedef struct
   *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
   *            @arg @ref RCC_LSEDRIVE_HIGH       LSE oscillator high drive capability.
   * @retval None
-  */ 
+  */
 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
         RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h

@@ -399,7 +399,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
                                                                         comparison. Only SS[12:0] are compared */
 #define RTC_ALARMSUBSECONDMASK_SS14        (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14] is don't care in Alarm
                                                                         comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS    /*!< SS[14:0] are compared and must match 
+#define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS    /*!< SS[14:0] are compared and must match
                                                                         to activate alarm. */
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h

@@ -37,7 +37,7 @@
 
 /** @addtogroup SDADC
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup SDADC_Exported_Types SDADC Exported Types
@@ -45,9 +45,9 @@
   */
 
 
-/** 
-  * @brief  HAL SDADC States definition  
-  */ 
+/**
+  * @brief  HAL SDADC States definition
+  */
 typedef enum
 {
   HAL_SDADC_STATE_RESET                   = 0x00U,    /*!< SDADC not initialized */
@@ -58,26 +58,26 @@ typedef enum
   HAL_SDADC_STATE_REG_INJ                 = 0x05U,    /*!< SDADC regular and injected conversions in progress */
   HAL_SDADC_STATE_ERROR                   = 0xFFU,    /*!< SDADC state error */
 }HAL_SDADC_StateTypeDef;
-   
-/** 
-  * @brief SDADC Init Structure definition  
-  */ 
+
+/**
+  * @brief SDADC Init Structure definition
+  */
 typedef struct
 {
   uint32_t IdleLowPowerMode;        /*!< Specifies if SDADC can enter in power down or standby when idle.
                                          This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
-  uint32_t FastConversionMode;      /*!< Specifies if Fast conversion mode is enabled or not. 
+  uint32_t FastConversionMode;      /*!< Specifies if Fast conversion mode is enabled or not.
                                          This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
-  uint32_t SlowClockMode;           /*!< Specifies if slow clock mode is enabled or not. 
+  uint32_t SlowClockMode;           /*!< Specifies if slow clock mode is enabled or not.
                                          This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
   uint32_t ReferenceVoltage;        /*!< Specifies the reference voltage.
                                          Note: This parameter is common to all SDADC instances.
                                          This parameter can be a value of @ref SDADC_Reference_Voltage */
 }SDADC_InitTypeDef;
 
-/** 
-  * @brief  SDADC handle Structure definition  
-  */  
+/**
+  * @brief  SDADC handle Structure definition
+  */
 typedef struct __SDADC_HandleTypeDef
 {
   SDADC_TypeDef            *Instance;           /*!< SDADC registers base address */
@@ -106,8 +106,8 @@ typedef struct __SDADC_HandleTypeDef
 #endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
 }SDADC_HandleTypeDef;
 
-/** 
-  * @brief  SDADC Configuration Register Parameter Structure 
+/**
+  * @brief  SDADC Configuration Register Parameter Structure
   */
 typedef struct
 {
@@ -196,7 +196,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 /** @defgroup SDADC_ConfIndex SDADC Configuration Index
   * @{
   */
-  
+
 #define SDADC_CONF_INDEX_0                     (0x00000000UL) /*!< Configuration 0 Register selected */
 #define SDADC_CONF_INDEX_1                     (0x00000001U) /*!< Configuration 1 Register selected */
 #define SDADC_CONF_INDEX_2                     (0x00000002U) /*!< Configuration 2 Register selected */
@@ -247,10 +247,10 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 /* SDADC Channels ------------------------------------------------------------*/
 /* The SDADC channels are defined as follows:
    - in 16-bit LSB the channel mask is set
-   - in 16-bit MSB the channel number is set 
-   e.g. for channel 5 definition:  
-        - the channel mask is 0x00000020 (bit 5 is set) 
-        - the channel number 5 is 0x00050000 
+   - in 16-bit MSB the channel number is set
+   e.g. for channel 5 definition:
+        - the channel mask is 0x00000020 (bit 5 is set)
+        - the channel number 5 is 0x00050000
         --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
 #define SDADC_CHANNEL_0                              (0x00000001UL)
 #define SDADC_CHANNEL_1                              (0x00010002UL)
@@ -267,7 +267,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
   * @{
-  */ 
+  */
 #define SDADC_CALIBRATION_SEQ_1                   (0x00000000UL) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
 #define SDADC_CALIBRATION_SEQ_2                   SDADC_CR2_CALIBCNT_0   /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
 #define SDADC_CALIBRATION_SEQ_3                   SDADC_CR2_CALIBCNT_1   /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
@@ -277,7 +277,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
   * @{
-  */ 
+  */
 #define SDADC_CONTINUOUS_CONV_OFF            (0x00000000UL) /*!< Conversion are not continuous */
 #define SDADC_CONTINUOUS_CONV_ON             (0x00000001UL) /*!< Conversion are continuous */
 /**
@@ -286,7 +286,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_Trigger SDADC Trigger
   * @{
-  */ 
+  */
 #define SDADC_SOFTWARE_TRIGGER               (0x00000000UL) /*!< Software trigger */
 #define SDADC_SYNCHRONOUS_TRIGGER            (0x00000001UL) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
 #define SDADC_EXTERNAL_TRIGGER               (0x00000002UL) /*!< External trigger */
@@ -296,7 +296,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
   * @{
-  */ 
+  */
 #define SDADC_EXT_TRIG_TIM13_CC1             (0x00000000UL) /*!< Trigger source for SDADC1 */
 #define SDADC_EXT_TRIG_TIM14_CC1             (0x00000100UL) /*!< Trigger source for SDADC1 */
 #define SDADC_EXT_TRIG_TIM16_CC1             (0x00000000UL) /*!< Trigger source for SDADC3 */
@@ -323,7 +323,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
   * @{
-  */ 
+  */
 #define SDADC_EXT_TRIG_RISING_EDGE           SDADC_CR2_JEXTEN_0     /*!< External rising edge */
 #define SDADC_EXT_TRIG_FALLING_EDGE          SDADC_CR2_JEXTEN_1     /*!< External falling edge */
 #define SDADC_EXT_TRIG_BOTH_EDGES            SDADC_CR2_JEXTEN       /*!< External rising and falling edges */
@@ -333,7 +333,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
   * @{
-  */ 
+  */
 #define SDADC_INJECTED_DELAY_NONE            (0x00000000UL) /*!< No delay on injected conversion */
 #define SDADC_INJECTED_DELAY                 SDADC_CR2_JDS          /*!< Delay on injected conversion */
 /**
@@ -342,7 +342,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_MultimodeType SDADC Multimode Type
   * @{
-  */ 
+  */
 #define SDADC_MULTIMODE_SDADC1_SDADC2        (0x00000000UL) /*!< Get conversion values for SDADC1 and SDADC2 */
 #define SDADC_MULTIMODE_SDADC1_SDADC3        (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
 /**
@@ -351,7 +351,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
 
 /** @defgroup SDADC_ErrorCode SDADC Error Code
   * @{
-  */ 
+  */
 #define SDADC_ERROR_NONE                     (0x00000000UL) /*!< No error */
 #define SDADC_ERROR_REGULAR_OVERRUN          (0x00000001UL) /*!< Overrun occurs during regular conversion */
 #define SDADC_ERROR_INJECTED_OVERRUN         (0x00000002UL) /*!< Overrun occurs during injected conversion */
@@ -391,14 +391,14 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
   * @}
   */
 
-/* Exported macros -----------------------------------------------------------*/  
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup SDADC_Exported_Macros SDADC Exported Macros
  * @{
  */
 
 /* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */    
-       
+/* final user.                                                                */
+
 /** @brief Enable the ADC end of conversion interrupt.
   * @param __HANDLE__ ADC handle
   * @param __INTERRUPT__ ADC Interrupt
@@ -412,7 +412,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
   */
 #define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                       \
   (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-    
+
 /** @brief Disable the ADC end of conversion interrupt.
   * @param __HANDLE__ ADC handle
   * @param __INTERRUPT__ ADC Interrupt
@@ -454,7 +454,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
   */
 #define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__)                             \
   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-    
+
 /** @brief Clear the ADC's pending flags
   * @param __HANDLE__ ADC handle
   * @param __FLAG__ ADC flag
@@ -489,7 +489,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
   * @}
   */
 
-/* Private macros ------------------------------------------------------------*/  
+/* Private macros ------------------------------------------------------------*/
 /** @defgroup SDADC_Private_Macros SDADC Private Macros
  * @{
  */
@@ -597,7 +597,7 @@ typedef  void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< point
   * @}
   */
 
-/* Exported functions --------------------------------------------------------*/  
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
   * @{
   */
@@ -627,8 +627,8 @@ HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *sdhadc, HAL_
   */
 
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, 
-                                                 uint32_t ConfIndex, 
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
+                                                 uint32_t ConfIndex,
                                                  SDADC_ConfParamTypeDef* ConfParamStruct);
 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
                                                    uint32_t Channel,
@@ -684,7 +684,7 @@ uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
-                                               
+
 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
 
 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
@@ -710,7 +710,7 @@ void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
 uint32_t               HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
 
-/* Private functions ---------------------------------------------------------*/  
+/* Private functions ---------------------------------------------------------*/
 
 /**
   * @}
@@ -722,7 +722,7 @@ uint32_t               HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h

@@ -4,17 +4,17 @@
   * @author  MCD Application Team
   * @brief   Header file of BUS LL module.
 
-  @verbatim                
+  @verbatim
                       ##### RCC Limitations #####
   ==============================================================================
-    [..]  
-      A delay between an RCC peripheral clock enable and the effective peripheral 
-      enabling should be taken into account in order to manage the peripheral read/write 
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
       from/to registers.
       (+) This delay depends on the peripheral mapping.
         (++) AHB & APB peripherals, 1 dummy read is necessary
 
-    [..]  
+    [..]
       Workarounds:
       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h

@@ -145,24 +145,24 @@ typedef struct
 {
   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-                                             
+
                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
 
   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-                                             
+
                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
 
   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
                                              If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
                                              If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
                                              @note If waveform automatic generation mode is disabled, this parameter is discarded.
-                                             
+
                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
 
   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-                                             
+
                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
 
 } LL_DAC_InitTypeDef;
@@ -231,7 +231,7 @@ typedef struct
 
 #elif defined(STM32F303x8) || defined(STM32F328xx)
 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */                                                                       
+#define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
@@ -253,7 +253,7 @@ typedef struct
 
 #elif defined(STM32F373xC) || defined(STM32F378xx)
 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */                                                                       
+#define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
@@ -449,7 +449,7 @@ typedef struct
   * @param  __CHANNEL__ This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval 1...2 (value "2" depending on DAC channel 2 availability)
@@ -469,7 +469,7 @@ typedef struct
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   */
@@ -573,7 +573,7 @@ typedef struct
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  TriggerSource This parameter can be one of the following values:
@@ -591,7 +591,7 @@ typedef struct
   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2   (1)(2)
   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3   (1)   (3)
   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
-  *         
+  *
   *         (1) On STM32F3, parameter not available on all devices
   *         (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
   *         (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
@@ -616,7 +616,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval Returned value can be one of the following values:
@@ -634,7 +634,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2   (1)(2)
   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3   (1)   (3)
   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
-  *         
+  *
   *         (1) On STM32F3, parameter not available on all devices
   *         (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
   *         (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
@@ -655,7 +655,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  WaveAutoGeneration This parameter can be one of the following values:
@@ -680,7 +680,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval Returned value can be one of the following values:
@@ -709,7 +709,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  NoiseLFSRMask This parameter can be one of the following values:
@@ -743,7 +743,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval Returned value can be one of the following values:
@@ -781,7 +781,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  TriangleAmplitude This parameter can be one of the following values:
@@ -815,7 +815,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval Returned value can be one of the following values:
@@ -847,7 +847,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  OutputBuffer This parameter can be one of the following values:
@@ -855,7 +855,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint
   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
   *         @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
   *         @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE  (1)
-  *         
+  *
   *         (1) Feature specific to STM32F303x6/8 and STM32F328:
   *             On DAC1 channel 2, output buffer is replaced by a switch
   *             to connect DAC channel output to pin PA5.
@@ -878,7 +878,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval Returned value can be one of the following values:
@@ -886,7 +886,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
   *         @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
   *         @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE  (1)
-  *         
+  *
   *         (1) Feature specific to STM32F303x6/8 and STM32F328:
   *             On DAC1 channel 2, output buffer is replaced by a switch
   *             to connect DAC channel output to pin PA5.
@@ -918,7 +918,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -939,7 +939,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -959,7 +959,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval State of bit (1 or 0).
@@ -996,7 +996,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  Register This parameter can be one of the following values:
@@ -1030,7 +1030,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -1069,7 +1069,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval State of bit (1 or 0).
@@ -1097,7 +1097,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -1116,7 +1116,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -1136,7 +1136,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval State of bit (1 or 0).
@@ -1165,7 +1165,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC
   * @param  DAC_Channel  This parameter can a combination of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval None
@@ -1186,7 +1186,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1195,7 +1195,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha
 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
 {
   register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
-  
+
   MODIFY_REG(*preg,
              DAC_DHR12R1_DACC1DHR,
              Data);
@@ -1211,7 +1211,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1220,7 +1220,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_
 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
 {
   register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
-  
+
   MODIFY_REG(*preg,
              DAC_DHR12L1_DACC1DHR,
              Data);
@@ -1236,7 +1236,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
@@ -1245,7 +1245,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t
 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
 {
   register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
-  
+
   MODIFY_REG(*preg,
              DAC_DHR8R1_DACC1DHR,
              Data);
@@ -1322,7 +1322,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
@@ -1330,7 +1330,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
-  
+
   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
 }
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h

@@ -201,7 +201,7 @@ extern "C" {
   */
 __STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
 {
-  SET_BIT(PWR->CR, Analogx); 
+  SET_BIT(PWR->CR, Analogx);
 }
 
 /**

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h

@@ -778,7 +778,7 @@ typedef struct
 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
   * @{
   */
-#define LL_RCC_PLLSOURCE_NONE              0x00000000U                                   /*!< No clock selected as main PLL entry clock source */  
+#define LL_RCC_PLLSOURCE_NONE              0x00000000U                                   /*!< No clock selected as main PLL entry clock source */
 #define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC_HSE_PREDIV                    /*!< HSE/PREDIV clock selected as PLL entry clock source */
 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
 #define LL_RCC_PLLSOURCE_HSI               RCC_CFGR_PLLSRC_HSI_PREDIV                    /*!< HSI/PREDIV clock selected as PLL entry clock source */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h

@@ -133,11 +133,11 @@ extern "C" {
 /** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
   * @{
   */
-#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP) 
+#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
 #define LL_SYSCFG_ADC24_RMP_DMA2_CH12    (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U)        /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
 #define LL_SYSCFG_ADC24_RMP_DMA2_CH34    (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP)   /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
 #endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
-#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP) 
+#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
 #define LL_SYSCFG_ADC2_RMP_DMA1_CH2      (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U)       /*!< ADC2 mapped on DMA1 channel 2 */
 #define LL_SYSCFG_ADC2_RMP_DMA1_CH4      (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
 #define LL_SYSCFG_ADC2_RMP_DMA2          (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U)       /*!< ADC2 mapped on DMA2 */
@@ -580,7 +580,7 @@ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
   */
 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
 {
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U)); 
+  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
   MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
 }
 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
@@ -723,7 +723,7 @@ __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
   */
 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
 {
-  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U)); 
+  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
   MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
 }
 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h

@@ -102,14 +102,14 @@ typedef struct
 
 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
   uint32_t PLLDiv;   /*!< Division factor for PLL VCO output clock.
-                          This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV 
-  
+                          This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
                           This feature can be modified afterwards using unitary function
                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
 #else
   uint32_t Prediv;   /*!< Division factor for HSE used as PLL clock source.
-                          This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV 
-  
+                          This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
                           This feature can be modified afterwards using unitary function
                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
@@ -223,7 +223,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
 /**
   * @brief  This function configures the Cortex-M SysTick source of the time base.
   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick 
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
   * @param  Ticks Number of ticks
   * @retval None

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c

@@ -67,7 +67,7 @@
 /**
   * @}
   */
-  
+
 /* Private macro -------------------------------------------------------------*/
 /* Exported variables --------------------------------------------------------*/
 /** @defgroup HAL_Exported_Variables HAL Exported Variables
@@ -86,7 +86,7 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
   * @{
   */
 
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
  *  @brief    Initialization and de-initialization functions
  *
 @verbatim
@@ -94,26 +94,26 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
               ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initializes the Flash interface, the NVIC allocation and initial clock 
+      (+) Initializes the Flash interface, the NVIC allocation and initial clock
           configuration. It initializes the systick also when timeout is needed
           and the backup domain when enabled.
       (+) de-Initializes common part of the HAL.
-      (+) Configure The time base source to have 1ms time base with a dedicated 
-          Tick interrupt priority. 
-        (++) SysTick timer is used by default as source of time base, but user 
-             can eventually implement his proper time base source (a general purpose 
-             timer for example or other time source), keeping in mind that Time base 
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
              handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
-             at the beginning of the program after reset by HAL_Init() or at any time 
-             when clock is configured, by HAL_RCC_ClockConfig(). 
-        (++) Source of time base is configured  to generate interrupts at regular 
-             time intervals. Care must be taken if HAL_Delay() is called from a 
-             peripheral ISR process, the Tick interrupt line must have higher priority 
-            (numerically lower) than the peripheral interrupt. Otherwise the caller 
-            ISR process will be blocked. 
-       (++) functions affecting time base configurations are declared as __Weak  
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __Weak
              to make  override possible  in case of other  implementations in user file.
 
 @endverbatim
@@ -121,14 +121,14 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
   */
 
 /**
-  * @brief  This function configures the Flash prefetch, 
+  * @brief  This function configures the Flash prefetch,
   *         Configures time base source, NVIC and Low level hardware
-  * @note   This function is called at the beginning of program after reset and before 
+  * @note   This function is called at the beginning of program after reset and before
   *         the clock configuration
-  *             
+  *
   * @note   The Systick configuration is based on HSI clock, as HSI is the clock
-  *         used after a system Reset and the NVIC configuration is set to Priority group 4 
-  *            
+  *         used after a system Reset and the NVIC configuration is set to Priority group 4
+  *
   * @note   The time base configuration is based on MSI clock when exting from Reset.
   *         Once done, time base tick start incrementing.
   *         In the default implementation,Systick is used as source of time base.
@@ -202,15 +202,15 @@ __weak void HAL_MspDeInit(void)
 }
 
 /**
-  * @brief  This function configures the source of the time base. 
-  *         The time source is configured  to have 1ms time base with a dedicated 
-  *         Tick interrupt priority. 
+  * @brief  This function configures the source of the time base.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
   * @note   This function is called  automatically at the beginning of program after
-  *         reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig(). 
-  * @note   In the default implementation , SysTick timer is the source of time base. 
-  *         It is used to generate interrupts at regular time intervals. 
-  *         Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
-  *         The SysTick interrupt must have higher priority (numerically lower) 
+  *         reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note   In the default implementation , SysTick timer is the source of time base.
+  *         It is used to generate interrupts at regular time intervals.
+  *         Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *         The SysTick interrupt must have higher priority (numerically lower)
   *         than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
   *         The function is declared as __Weak  to be overwritten  in case of other
   *         implementation  in user file.
@@ -243,7 +243,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
   * @}
   */
 
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
  *  @brief    HAL Control functions
  *
 @verbatim
@@ -261,7 +261,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
       (+) Enable/Disable Debug module during Sleep mode
       (+) Enable/Disable Debug module during STOP mode
       (+) Enable/Disable Debug module during STANDBY mode
-      
+
 @endverbatim
   * @{
   */
@@ -271,7 +271,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
   *         used as application time base.
   * @note In the default implementation, this variable is incremented each 1ms
   *         in SysTick ISR.
-  * @note This function is declared as __weak to be overwritten in case of other 
+  * @note This function is declared as __weak to be overwritten in case of other
   *         implementations  in user file.
   * @retval None
   */
@@ -282,13 +282,13 @@ __weak void HAL_IncTick(void)
 
 /**
   * @brief  Povides a tick value in millisecond.
-  * @note   The function is declared as __Weak  to be overwritten  in case of other 
+  * @note   The function is declared as __Weak  to be overwritten  in case of other
   *         implementations  in user file.
   * @retval tick value
   */
 __weak uint32_t HAL_GetTick(void)
 {
-  return uwTick;  
+  return uwTick;
 }
 
 /**
@@ -342,9 +342,9 @@ HAL_TickFreqTypeDef HAL_GetTickFreq(void)
 }
 
 /**
-  * @brief  This function provides accurate delay (in milliseconds) based 
+  * @brief  This function provides accurate delay (in milliseconds) based
   *         on variable incremented.
-  * @note   In the default implementation , SysTick timer is the source of time base. 
+  * @note   In the default implementation , SysTick timer is the source of time base.
   *         It is used to generate interrupts at regular time intervals where uwTick
   *         is incremented.
   *         The function is declared as __Weak  to be overwritten  in case of other
@@ -356,13 +356,13 @@ __weak void HAL_Delay(uint32_t Delay)
 {
   uint32_t tickstart = HAL_GetTick();
   uint32_t wait = Delay;
-  
+
   /* Add freq to guarantee minimum wait */
   if (wait < HAL_MAX_DELAY)
   {
     wait += (uint32_t)(uwTickFreq);
   }
-  
+
   while((HAL_GetTick() - tickstart) < wait)
   {
   }
@@ -370,9 +370,9 @@ __weak void HAL_Delay(uint32_t Delay)
 
 /**
   * @brief  Suspend Tick increment.
-  * @note   In the default implementation , SysTick timer is the source of time base. It is  
+  * @note   In the default implementation , SysTick timer is the source of time base. It is
   *         used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *         is called, the the SysTick interrupt will be disabled and so Tick increment 
+  *         is called, the the SysTick interrupt will be disabled and so Tick increment
   *         is suspended.
   * @note This function is declared as __weak to be overwritten in case of other
   *         implementations  in user file.
@@ -383,14 +383,14 @@ __weak void HAL_SuspendTick(void)
 {
   /* Disable SysTick Interrupt */
   SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-                                                   
+
 }
 
 /**
   * @brief  Resume Tick increment.
-  * @note   In the default implementation , SysTick timer is the source of time base. It is  
+  * @note   In the default implementation , SysTick timer is the source of time base. It is
   *         used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *         is called, the the SysTick interrupt will be enabled and so Tick increment 
+  *         is called, the the SysTick interrupt will be enabled and so Tick increment
   *         is resumed.
   *         The function is declared as __Weak  to be overwritten  in case of other
   *         implementations  in user file.
@@ -400,7 +400,7 @@ __weak void HAL_ResumeTick(void)
 {
   /* Enable SysTick Interrupt */
   SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
-  
+
 }
 
 /**

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c

@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_adc.c
   * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following 
+  * @brief   This file provides firmware functions to manage the following
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
   *           + Initialization and de-initialization functions
@@ -17,28 +17,28 @@
   *           + State functions
   *             ++ ADC state machine management
   *             ++ Interrupts and flags management
-  *          Other functions (extended functions) are available in file 
+  *          Other functions (extended functions) are available in file
   *          "stm32f3xx_hal_adc_ex.c".
   *
   @verbatim
   ==============================================================================
                      ##### ADC peripheral features #####
   ==============================================================================
-  [..] 
-  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on 
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
       STM32F30xxC devices).
 
   (+) Interrupt generation at the end of regular conversion, end of injected
       conversion, and in case of analog watchdog or overrun events.
-  
+
   (+) Single and continuous conversion modes.
-  
+
   (+) Scan mode for conversion of several channels sequentially.
-  
+
   (+) Data alignment with in-built data coherency.
-  
+
   (+) Programmable sampling time (channel wise)
-  
+
   (+) ADC conversion of regular group and injected group.
 
   (+) External trigger (timer or EXTI) with configurable polarity
@@ -47,28 +47,28 @@
   (+) DMA request generation for transfer of conversions data of regular group.
 
   (+) Multimode dual mode (available on devices with 2 ADCs or more).
-  
+
   (+) Configurable DMA data storage in Multimode Dual mode (available on devices
       with 2 DCs or more).
-  
-  (+) Configurable delay between conversions in Dual interleaved mode (available 
+
+  (+) Configurable delay between conversions in Dual interleaved mode (available
       on devices with 2 DCs or more).
-  
+
   (+) ADC calibration
 
   (+) ADC channels selectable single/differential input (available only on
       STM32F30xxC devices)
 
-  (+) ADC Injected sequencer&channels configuration context queue (available 
+  (+) ADC Injected sequencer&channels configuration context queue (available
       only on STM32F30xxC devices)
 
-  (+) ADC offset on injected and regular groups (offset on regular group 
+  (+) ADC offset on injected and regular groups (offset on regular group
       available only on STM32F30xxC devices)
 
-  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
+  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
       slower speed.
-  
-  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 
+
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
       Vdda or to an external voltage reference).
 
 
@@ -82,9 +82,9 @@
 
     (#) Enable the ADC interface
       (++) As prerequisite, ADC clock must be configured at RCC top level.
-      
+
         (++) For STM32F30x/STM32F33x devices:
-             Two possible clock sources: synchronous clock derived from AHB clock 
+             Two possible clock sources: synchronous clock derived from AHB clock
              or asynchronous clock derived from ADC dedicated PLL 72MHz.
               - Synchronous clock is mandatory since used as ADC core clock.
                 Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting.
@@ -101,22 +101,22 @@
 
              (+++) For example, in case of device with 4 ADCs:
 
-               (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))   
-               (+++) {                                                          
+               (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
+               (+++) {
                (+++)   __HAL_RCC_ADC12_CLK_ENABLE()                             (mandatory)
                (+++)   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC   (optional, if ADC conversion from asynchronous clock)
                (+++)   PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock)
                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if ADC conversion from asynchronous clock)
-               (+++) }                                                          
-               (+++) else                                                       
-               (+++) {                                                          
+               (+++) }
+               (+++) else
+               (+++) {
                (+++)   __HAL_RCC_ADC34_CLK_ENABLE()                              (mandatory)
                (+++)   PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock)
                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure);   (optional, if ADC conversion from asynchronous clock)
-               (+++) }                                                          
-      
+               (+++) }
+
         (++) For STM32F37x devices:
-             One clock setting is mandatory: 
+             One clock setting is mandatory:
              ADC clock (core and conversion clock) from APB2 clock.
              (+++) Example:
                    Into HAL_ADC_MspInit() (recommended code location) or with
@@ -134,8 +134,8 @@
     (#) Optionally, in case of usage of ADC with interruptions:
          (++) Configure the NVIC for ADC
               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
-         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
-              into the function of corresponding ADC interruption vector 
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding ADC interruption vector
               ADCx_IRQHandler().
 
     (#) Optionally, in case of usage of DMA:
@@ -143,8 +143,8 @@
               using function HAL_DMA_Init().
          (++) Configure the NVIC for DMA
               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
-         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 
-              into the function of corresponding DMA interruption vector 
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding DMA interruption vector
               DMAx_Channelx_IRQHandler().
 
      *** Configuration of ADC, groups regular/injected, channels parameters ***
@@ -155,13 +155,13 @@
         and regular group parameters (conversion trigger, sequencer, ...)
         using function HAL_ADC_Init().
 
-    (#) Configure the channels for regular group parameters (channel number, 
+    (#) Configure the channels for regular group parameters (channel number,
         channel rank into sequencer, ..., into regular group)
         using function HAL_ADC_ConfigChannel().
 
-    (#) Optionally, configure the injected group parameters (conversion trigger, 
+    (#) Optionally, configure the injected group parameters (conversion trigger,
         sequencer, ..., of injected group)
-        and the channels for injected group parameters (channel number, 
+        and the channels for injected group parameters (channel number,
         channel rank into sequencer, ..., into injected group)
         using function HAL_ADCEx_InjectedConfigChannel().
 
@@ -169,7 +169,7 @@
         monitored, thresholds, ...)
         using function HAL_ADC_AnalogWDGConfig().
 
-    (#) Optionally, for devices with several ADC instances: configure the 
+    (#) Optionally, for devices with several ADC instances: configure the
         multimode parameters
         using function HAL_ADCEx_MultiModeConfigChannel().
 
@@ -187,26 +187,26 @@
         (++) ADC conversion by polling:
           (+++) Activate the ADC peripheral and start conversions
                 using function HAL_ADC_Start()
-          (+++) Wait for ADC conversion completion 
+          (+++) Wait for ADC conversion completion
                 using function HAL_ADC_PollForConversion()
                 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
-          (+++) Retrieve conversion results 
+          (+++) Retrieve conversion results
                 using function HAL_ADC_GetValue()
                 (or for injected group: HAL_ADCEx_InjectedGetValue() )
-          (+++) Stop conversion and disable the ADC peripheral 
+          (+++) Stop conversion and disable the ADC peripheral
                 using function HAL_ADC_Stop()
 
-        (++) ADC conversion by interruption: 
+        (++) ADC conversion by interruption:
           (+++) Activate the ADC peripheral and start conversions
                 using function HAL_ADC_Start_IT()
           (+++) Wait for ADC conversion completion by call of function
                 HAL_ADC_ConvCpltCallback()
                 (this function must be implemented in user program)
                 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
-          (+++) Retrieve conversion results 
+          (+++) Retrieve conversion results
                 using function HAL_ADC_GetValue()
                 (or for injected group: HAL_ADCEx_InjectedGetValue() )
-          (+++) Stop conversion and disable the ADC peripheral 
+          (+++) Stop conversion and disable the ADC peripheral
                 using function HAL_ADC_Stop_IT()
 
         (++) ADC conversion with transfer by DMA:
@@ -217,10 +217,10 @@
                 (these functions must be implemented in user program)
           (+++) Conversion results are automatically transferred by DMA into
                 destination variable address.
-          (+++) Stop conversion and disable the ADC peripheral 
+          (+++) Stop conversion and disable the ADC peripheral
                 using function HAL_ADC_Stop_DMA()
 
-        (++) For devices with several ADCs: ADC multimode conversion 
+        (++) For devices with several ADCs: ADC multimode conversion
              with transfer by DMA:
           (+++) Activate the ADC peripheral (slave)
                 using function HAL_ADC_Start()
@@ -274,24 +274,24 @@
                (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before)
 
              (+++) For example, in case of device with 4 ADCs:
-               (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))   
-               (+++) {                                                          
+               (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
+               (+++) {
                (+++)   __HAL_RCC_ADC12_FORCE_RESET()                            (optional)
                (+++)   __HAL_RCC_ADC12_RELEASE_RESET()                          (optional)
                (+++)   __HAL_RCC_ADC12_CLK_DISABLE()                            (mandatory)
                (+++)   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC   (optional, if configured before)
                (+++)   PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF  (optional, if configured before)
                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if configured before)
-               (+++) }                                                          
-               (+++) else                                                       
-               (+++) {                                                          
+               (+++) }
+               (+++) else
+               (+++) {
                (+++)   __HAL_RCC_ADC32_FORCE_RESET()                            (optional)
                (+++)   __HAL_RCC_ADC32_RELEASE_RESET()                          (optional)
                (+++)   __HAL_RCC_ADC34_CLK_DISABLE()                            (mandatory)
                (+++)   PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF  (optional, if configured before)
                (+++)   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure)   (optional, if configured before)
-               (+++) }                                                          
-      
+               (+++) }
+
         (++) For STM32F37x devices:
              (+++) Example:
                    Into HAL_ADC_MspDeInit() (recommended code location) or with
@@ -315,7 +315,7 @@
               using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
 
     [..]
-    
+
     *** Callback registration ***
     =============================================
     [..]
@@ -380,7 +380,7 @@
      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.
-  
+
     @endverbatim
   ******************************************************************************
   * @attention
@@ -409,7 +409,7 @@
   */
 
 #ifdef HAL_ADC_MODULE_ENABLED
-    
+
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
@@ -419,47 +419,47 @@
 
 /** @defgroup ADC_Exported_Functions ADC Exported Functions
   * @{
-  */ 
+  */
 
 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
  ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC. 
-      (+) De-initialize the ADC. 
-         
+      (+) Initialize and configure the ADC.
+      (+) De-initialize the ADC.
+
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Initializes the ADC peripheral and regular group according to  
+  * @brief  Initializes the ADC peripheral and regular group according to
   *         parameters specified in structure "ADC_InitTypeDef".
   * @note   As prerequisite, ADC clock must be configured at RCC top level
   *         depending on both possible clock sources: PLL clock or AHB clock.
-  *         See commented example code below that can be copied and uncommented 
+  *         See commented example code below that can be copied and uncommented
   *         into HAL_ADC_MspInit().
   * @note   Possibility to update parameters on the fly:
   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
   *         coming from ADC state reset. Following calls to this function can
-  *         be used to reconfigure some parameters of ADC_InitTypeDef  
-  *         structure on the fly, without modifying MSP configuration. If ADC  
+  *         be used to reconfigure some parameters of ADC_InitTypeDef
+  *         structure on the fly, without modifying MSP configuration. If ADC
   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
   *         before HAL_ADC_Init().
   *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
+  *         For parameters constraints, see comments of structure
   *         "ADC_InitTypeDef".
-  * @note   This function configures the ADC within 2 scopes: scope of entire 
-  *         ADC and scope of regular group. For parameters details, see comments 
+  * @note   This function configures the ADC within 2 scopes: scope of entire
+  *         ADC and scope of regular group. For parameters details, see comments
   *         of structure "ADC_InitTypeDef".
-  * @note   For devices with several ADCs: parameters related to common ADC 
+  * @note   For devices with several ADCs: parameters related to common ADC
   *         registers (ADC clock mode) are set only if all ADCs sharing the
   *         same common group are disabled.
-  *         If this is not the case, these common parameters setting are  
+  *         If this is not the case, these common parameters setting are
   *         bypassed without error reporting: it can be the intended behaviour in
   *         case of update of a parameter of ADC_InitTypeDef on the fly,
   *         without  disabling the other ADCs sharing the same common group.
@@ -473,7 +473,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -481,15 +481,15 @@ __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Deinitialize the ADC peripheral registers to their default reset
   *         values, with deinitialization of the ADC MSP.
-  * @note   For devices with several ADCs: reset of ADC common registers is done 
+  * @note   For devices with several ADCs: reset of ADC common registers is done
   *         only if all ADCs sharing the same common group are disabled.
-  *         If this is not the case, reset of these common parameters reset is  
+  *         If this is not the case, reset of these common parameters reset is
   *         bypassed without error reporting: it can be the intended behaviour in
-  *         case of reset of a single ADC while the other ADCs sharing the same 
+  *         case of reset of a single ADC while the other ADCs sharing the same
   *         common group is still running.
   * @note   For devices with several ADCs: Global reset of all ADCs sharing a
   *         common group is possible.
-  *         As this function is intended to reset a single ADC, to not impact 
+  *         As this function is intended to reset a single ADC, to not impact
   *         other ADCs, instructions for global reset of multiple ADCs have been
   *         let commented below.
   *         If needed, the example code can be copied and uncommented into
@@ -504,11 +504,11 @@ __weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
-    
+
 /**
   * @brief  Initializes the ADC MSP.
   * @param  hadc ADC handle
@@ -521,7 +521,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_ADC_MspInit must be implemented in the user file.
-   */ 
+   */
 }
 
 /**
@@ -536,7 +536,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 
   /* NOTE : This function should not be modified. When the callback is needed,
             function HAL_ADC_MspDeInit must be implemented in the user file.
-   */ 
+   */
 }
 
 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
@@ -562,7 +562,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if (pCallback == NULL)
   {
     /* Update the error code */
@@ -570,7 +570,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
 
     return HAL_ERROR;
   }
-  
+
   if ((hadc->State & HAL_ADC_STATE_READY) != 0)
   {
     switch (CallbackID)
@@ -578,31 +578,31 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
         hadc->ConvCpltCallback = pCallback;
         break;
-      
+
       case HAL_ADC_CONVERSION_HALF_CB_ID :
         hadc->ConvHalfCpltCallback = pCallback;
         break;
-      
+
       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
         hadc->LevelOutOfWindowCallback = pCallback;
         break;
-      
+
       case HAL_ADC_ERROR_CB_ID :
         hadc->ErrorCallback = pCallback;
         break;
-      
+
       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
         hadc->InjectedConvCpltCallback = pCallback;
         break;
-      
+
       case HAL_ADC_MSPINIT_CB_ID :
         hadc->MspInitCallback = pCallback;
         break;
-      
+
       case HAL_ADC_MSPDEINIT_CB_ID :
         hadc->MspDeInitCallback = pCallback;
         break;
-      
+
       default :
         /* Update the error code */
         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
@@ -619,15 +619,15 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
       case HAL_ADC_MSPINIT_CB_ID :
         hadc->MspInitCallback = pCallback;
         break;
-      
+
       case HAL_ADC_MSPDEINIT_CB_ID :
         hadc->MspDeInitCallback = pCallback;
         break;
-      
+
       default :
         /* Update the error code */
         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-      
+
         /* Return error status */
         status = HAL_ERROR;
         break;
@@ -637,11 +637,11 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
   {
     /* Update the error code */
     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-    
+
     /* Return error status */
     status =  HAL_ERROR;
   }
-  
+
   return status;
 }
 
@@ -666,7 +666,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call
 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if ((hadc->State & HAL_ADC_STATE_READY) != 0)
   {
     switch (CallbackID)
@@ -674,35 +674,35 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
       case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
         hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
         break;
-      
+
       case HAL_ADC_CONVERSION_HALF_CB_ID :
         hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
         break;
-      
+
       case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
         hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
         break;
-      
+
       case HAL_ADC_ERROR_CB_ID :
         hadc->ErrorCallback = HAL_ADC_ErrorCallback;
         break;
-      
+
       case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
         hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
         break;
-      
+
       case HAL_ADC_MSPINIT_CB_ID :
         hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
         break;
-      
+
       case HAL_ADC_MSPDEINIT_CB_ID :
         hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
         break;
-      
+
       default :
         /* Update the error code */
         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status =  HAL_ERROR;
         break;
@@ -715,15 +715,15 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
       case HAL_ADC_MSPINIT_CB_ID :
         hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
         break;
-        
+
       case HAL_ADC_MSPDEINIT_CB_ID :
         hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
         break;
-        
+
       default :
         /* Update the error code */
         hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status =  HAL_ERROR;
         break;
@@ -733,11 +733,11 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
   {
     /* Update the error code */
     hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
-    
+
     /* Return error status */
     status =  HAL_ERROR;
   }
-  
+
   return status;
 }
 
@@ -748,12 +748,12 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
   */
 
 /** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    IO operation functions 
+ *  @brief    IO operation functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
              ##### IO operation functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Start conversion of regular group.
       (+) Stop conversion of regular group.
@@ -765,16 +765,16 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
       (+) Handle ADC interrupt request
       (+) Start conversion of regular group and enable DMA transfer.
       (+) Stop conversion of regular group and disable ADC DMA transfer.
-               
+
 @endverbatim
   * @{
   */
 /**
   * @brief  Enables ADC, starts conversion of regular group.
   *         Interruptions enabled in this function: None.
-  * @note:  Case of multimode enabled (for devices with several ADCs): This 
-  *         function must be called for ADC slave first, then ADC master. 
-  *         For ADC slave, ADC is enabled only (conversion is not started).  
+  * @note:  Case of multimode enabled (for devices with several ADCs): This
+  *         function must be called for ADC slave first, then ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
   *         For ADC master, ADC is enabled and multimode conversion is started.
   * @param  hadc ADC handle
   * @retval HAL status
@@ -789,14 +789,14 @@ __weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
 }
 
 /**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
+  * @brief  Stop ADC conversion of regular group (and injected group in
   *         case of auto_injection mode), disable ADC peripheral.
-  * @note:  ADC peripheral disable is forcing stop of potential 
+  * @note:  ADC peripheral disable is forcing stop of potential
   *         conversion on injected group. If injected group is under use, it
   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @note:  Case of multimode enabled (for devices with several ADCs): This 
+  * @note:  Case of multimode enabled (for devices with several ADCs): This
   *         function must be called for ADC master first, then ADC slave.
-  *         For ADC master, converson is stopped and ADC is disabled. 
+  *         For ADC master, converson is stopped and ADC is disabled.
   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
   *         has already stopped conversion of ADC slave).
   * @param  hadc ADC handle
@@ -809,7 +809,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -828,7 +828,7 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -855,7 +855,7 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -863,14 +863,14 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t
 /**
   * @brief  Enables ADC, starts conversion of regular group with interruption.
   *         Interruptions enabled in this function:
-  *          - EOC (end of conversion of regular group) or EOS (end of 
-  *            sequence of regular group) depending on ADC initialization 
+  *          - EOC (end of conversion of regular group) or EOS (end of
+  *            sequence of regular group) depending on ADC initialization
   *            parameter "EOCSelection" (if available)
   *          - overrun (if available)
   *         Each of these interruptions has its dedicated callback function.
-  * @note:  Case of multimode enabled (for devices with several ADCs): This 
-  *         function must be called for ADC slave first, then ADC master. 
-  *         For ADC slave, ADC is enabled only (conversion is not started).  
+  * @note:  Case of multimode enabled (for devices with several ADCs): This
+  *         function must be called for ADC slave first, then ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
   *         For ADC master, ADC is enabled and multimode conversion is started.
   * @param  hadc ADC handle
   * @retval HAL status
@@ -882,21 +882,21 @@ __weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
 
 /**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable interruption of 
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable interruption of
   *         end-of-conversion, disable ADC peripheral.
-  * @note:  ADC peripheral disable is forcing stop of potential 
+  * @note:  ADC peripheral disable is forcing stop of potential
   *         conversion on injected group. If injected group is under use, it
   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @note:  Case of multimode enabled (for devices with several ADCs): This 
+  * @note:  Case of multimode enabled (for devices with several ADCs): This
   *         function must be called for ADC master first, then ADC slave.
-  *         For ADC master, conversion is stopped and ADC is disabled. 
+  *         For ADC master, conversion is stopped and ADC is disabled.
   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
   *         has already stopped conversion of ADC slave).
   * @param  hadc ADC handle
@@ -909,7 +909,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -922,8 +922,8 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
   *          - DMA half transfer
   *          - overrun (if available)
   *         Each of these interruptions has its dedicated callback function.
-  * @note:  Case of multimode enabled (for devices with several ADCs): This 
-  *         function is for single-ADC mode only. For multimode, use the 
+  * @note:  Case of multimode enabled (for devices with several ADCs): This
+  *         function is for single-ADC mode only. For multimode, use the
   *         dedicated MultimodeStart function.
   * @param  hadc ADC handle
   * @param  pData The destination Buffer address.
@@ -939,20 +939,20 @@ __weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pD
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
 
 /**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable ADC DMA transfer, disable 
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
   *         ADC peripheral.
-  * @note:  ADC peripheral disable is forcing stop of potential 
+  * @note:  ADC peripheral disable is forcing stop of potential
   *         conversion on injected group. If injected group is under use, it
   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @note:  Case of multimode enabled (for devices with several ADCs): This 
-  *         function is for single-ADC mode only. For multimode, use the 
+  * @note:  Case of multimode enabled (for devices with several ADCs): This
+  *         function is for single-ADC mode only. For multimode, use the
   *         dedicated MultimodeStop function.
   * @param  hadc ADC handle
   * @retval HAL status.
@@ -964,7 +964,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -982,13 +982,13 @@ __weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
 {
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
-  /* Return ADC converted value */ 
+
+  /* Return ADC converted value */
   return hadc->Instance->DR;
 }
 
 /**
-  * @brief  Handles ADC interrupt request.  
+  * @brief  Handles ADC interrupt request.
   * @param  hadc ADC handle
   * @retval None
   */
@@ -1002,7 +1002,7 @@ __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 }
 
 /**
-  * @brief  Conversion complete callback in non blocking mode 
+  * @brief  Conversion complete callback in non blocking mode
   * @param  hadc ADC handle
   * @retval None
   */
@@ -1017,7 +1017,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 }
 
 /**
-  * @brief  Conversion DMA half-transfer callback in non blocking mode 
+  * @brief  Conversion DMA half-transfer callback in non blocking mode
   * @param  hadc ADC handle
   * @retval None
   */
@@ -1032,7 +1032,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 }
 
 /**
-  * @brief  Analog watchdog callback in non blocking mode. 
+  * @brief  Analog watchdog callback in non blocking mode.
   * @param  hadc ADC handle
   * @retval None
   */
@@ -1067,16 +1067,16 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
   */
 
 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
+ *  @brief    Peripheral Control functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
              ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Configure channels on regular group
       (+) Configure the analog watchdog
-      
+
 @endverbatim
   * @{
   */
@@ -1088,17 +1088,17 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
   *         Vbat/VrefInt/TempSensor.
   *         The recommended sampling time is at least:
   *          - For devices STM32F37x: 17.1us for temperature sensor
-  *          - For the other STM32F3 devices: 2.2us for each of channels 
+  *          - For the other STM32F3 devices: 2.2us for each of channels
   *            Vbat/VrefInt/TempSensor.
-  *         These internal paths can be be disabled using function 
+  *         These internal paths can be be disabled using function
   *         HAL_ADC_DeInit().
   * @note   Possibility to update parameters on the fly:
-  *         This function initializes channel into regular group, following  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting 
+  *         This function initializes channel into regular group, following
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
   *         the ADC.
   *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
+  *         For parameters constraints, see comments of structure
   *         "ADC_ChannelConfTypeDef".
   * @param  hadc ADC handle
   * @param  sConfig Structure of ADC channel for regular group.
@@ -1112,7 +1112,7 @@ __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_Chan
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -1120,12 +1120,12 @@ __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_Chan
 /**
   * @brief  Configures the analog watchdog.
   * @note   Possibility to update parameters on the fly:
-  *         This function initializes the selected analog watchdog, following  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting 
+  *         This function initializes the selected analog watchdog, following
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
   *         the ADC.
   *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
+  *         For parameters constraints, see comments of structure
   *         "ADC_AnalogWDGConfTypeDef".
   * @param  hadc ADC handle
   * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
@@ -1139,7 +1139,7 @@ __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_An
 
   /* Note : This function is defined into this file for library reference. */
   /*        Function content is located into file stm32f3xx_hal_adc_ex.c   */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -1149,27 +1149,27 @@ __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_An
   */
 
 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief   ADC Peripheral State functions 
+ *  @brief   ADC Peripheral State functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
             ##### Peripheral state and errors functions #####
  ===============================================================================
     [..]
-    This subsection provides functions to get in run-time the status of the  
+    This subsection provides functions to get in run-time the status of the
     peripheral.
       (+) Check the ADC state
       (+) Check the ADC error code
-         
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  return the ADC state
   * @note   ADC state machine is managed by bitfield, state must be compared
   *         with bit by bit.
-  *         For example:                                                         
+  *         For example:
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
   * @param  hadc ADC handle
@@ -1179,7 +1179,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
 {
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
+
   /* Return ADC state */
   return hadc->State;
 }
@@ -1197,7 +1197,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
 /**
   * @}
   */
-       
+
 /**
   * @}
   */
@@ -1205,10 +1205,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
 #endif /* HAL_ADC_MODULE_ENABLED */
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c

@@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
       {
         hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
       }
-      
+
       /* Init the low level hardware */
       hcomp->MspInitCallback(hcomp);
 #else
@@ -444,7 +444,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
     {
       hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
     }
-    
+
     /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
     hcomp->MspDeInitCallback(hcomp);
 #else
@@ -508,7 +508,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
 HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if (pCallback == NULL)
   {
     /* Update the error code */
@@ -516,7 +516,7 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
 
     return HAL_ERROR;
   }
-  
+
   if (HAL_COMP_STATE_READY == hcomp->State)
   {
     switch (CallbackID)
@@ -524,19 +524,19 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
       case HAL_COMP_TRIGGER_CB_ID :
         hcomp->TriggerCallback = pCallback;
         break;
-      
+
       case HAL_COMP_MSPINIT_CB_ID :
         hcomp->MspInitCallback = pCallback;
         break;
-      
+
       case HAL_COMP_MSPDEINIT_CB_ID :
         hcomp->MspDeInitCallback = pCallback;
         break;
-      
+
       default :
         /* Update the error code */
         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status = HAL_ERROR;
         break;
@@ -549,15 +549,15 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
       case HAL_COMP_MSPINIT_CB_ID :
         hcomp->MspInitCallback = pCallback;
         break;
-      
+
       case HAL_COMP_MSPDEINIT_CB_ID :
         hcomp->MspDeInitCallback = pCallback;
         break;
-      
+
       default :
         /* Update the error code */
         hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status = HAL_ERROR;
         break;
@@ -567,11 +567,11 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
   {
     /* Update the error code */
     hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
-    
+
     /* Return error status */
     status =  HAL_ERROR;
   }
-  
+
   return status;
 }
 
@@ -598,7 +598,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM
       case HAL_COMP_TRIGGER_CB_ID :
         hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
         break;
-      
+
       case HAL_COMP_MSPINIT_CB_ID :
         hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
         break;
@@ -1053,7 +1053,7 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
 {
   /* Check the parameters */
   assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-  
+
   return hcomp->ErrorCode;
 }
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c

@@ -39,8 +39,8 @@
     *** How to configure Systick using CORTEX HAL driver ***
     ========================================================
     [..]
-    Setup SysTick Timer for time base 
-           
+    Setup SysTick Timer for time base
+
    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
        is a CMSIS function that:
         (++) Configures the SysTick Reload register with value passed as function parameter.
@@ -49,14 +49,14 @@
         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
         (++) Enables the SysTick Interrupt.
         (++) Starts the SysTick Counter.
-    
+
    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
        inside the stm32f3xx_hal_cortex.h file.
 
    (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
 
    (+) To adjust the SysTick time base, use the following formula:
@@ -191,13 +191,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 {
   uint32_t prioritygroup = 0x00U;
-  
+
   /* Check the parameters */
   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
+
   prioritygroup = NVIC_GetPriorityGrouping();
-  
+
   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 }
 
@@ -214,7 +214,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
 {
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
+
   /* Enable interrupt */
   NVIC_EnableIRQ(IRQn);
 }
@@ -230,7 +230,7 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
 {
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
+
   /* Disable interrupt */
   NVIC_DisableIRQ(IRQn);
 }
@@ -277,24 +277,24 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
   */
 
 #if (__MPU_PRESENT == 1U)
-	
+
 /**
-  * @brief  Disables the MPU also clears the HFNMIENA bit (ARM recommendation) 
+  * @brief  Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
   * @retval None
   */
 void HAL_MPU_Disable(void)
 {
   /* Disable fault exceptions */
   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
+
   /* Disable the MPU */
   MPU->CTRL = 0U;
 }
 
 /**
   * @brief  Enables the MPU
-  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged access to the default memory 
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
+  *          NMI, FAULTMASK and privileged access to the default memory
   *          This parameter can be one of the following values:
   *            @arg MPU_HFNMI_PRIVDEF_NONE
   *            @arg MPU_HARDFAULT_NMI
@@ -306,12 +306,12 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
 {
   /* Enable the MPU */
   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
+
   /* Enable fault exceptions */
   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 }
-	
-	/**
+
+    /**
   * @brief  Initializes and configures the Region and the memory to be protected.
   * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
   *                the initialization and configuration information.
@@ -337,7 +337,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-    
+
     MPU->RBAR = MPU_Init->BaseAddress;
     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c

@@ -3,140 +3,140 @@
   * @file    stm32f3xx_hal_dac.c
   * @author  MCD Application Team
   * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
+  *         This file provides firmware functions to manage the following
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions      
+  *           + Peripheral State and Errors functions
   *
   *
- @verbatim      
+ @verbatim
   ==============================================================================
                       ##### DAC Peripheral features #####
   ==============================================================================
-    [..]        
+    [..]
       *** DAC Channels ***
-      ====================  
-    [..]  
-    The device integrates up to 3 12-bit Digital Analog Converters that can 
+      ====================
+    [..]
+    The device integrates up to 3 12-bit Digital Analog Converters that can
     be used independently or simultaneously (dual mode):
       (#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
-      (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output 
+      (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
           (for STM32F3 devices having 2 channels on DAC1)
-      (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output 
+      (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
           (for STM32F3 devices having 2 DAC)
 
       *** DAC Triggers ***
       ====================
     [..]
     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
-    and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register. 
-    [..] 
+    and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
+    [..]
     Digital to Analog conversion can be triggered by:
       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
           The used pin (GPIOx_PIN_9) must be configured in input mode.
-  
-      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
+
+      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-  
+
       (#) Software using DAC_TRIGGER_SOFTWARE
-  
+
       *** DAC Buffer mode feature ***
-      =============================== 
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to 
+      ===============================
+      [..]
+      Each DAC channel integrates an output buffer that can be used to
       reduce the output impedance, and to drive external loads directly
       without having to add an external operational amplifier.
-      To enable, the output buffer use  
+      To enable, the output buffer use
       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
       Or
-      An output switch 
+      An output switch
          (in STM32F303x4, STM32F303x6, STM32F303x8
              c, STM32F334x6, STM32F334x8
            & STM32F334xx).
       To enable, the output switch
       sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
-      [..]         
-      (@) Refer to the device datasheet for more details about output 
+      [..]
+      (@) Refer to the device datasheet for more details about output
           impedance value with and without output buffer.
 
       *** GPIO configurations guidelines ***
       =====================
-      [..] 
-      When a DAC channel is used (ex channel1 on PA4) and the other is not 
+      [..]
+      When a DAC channel is used (ex channel1 on PA4) and the other is not
       (ex channel2 on PA5 is configured in Analog and disabled).
       Channel1 may disturb channel2 as coupling effect.
       Note that there is no coupling on channel2 as soon as channel2 is turned on.
       Coupling on adjacent channel could be avoided as follows:
-      when unused PA5 is configured as INPUT PULL-UP or DOWN. 
-      PA5 is configured in ANALOG just before it is turned on.     
+      when unused PA5 is configured as INPUT PULL-UP or DOWN.
+      PA5 is configured in ANALOG just before it is turned on.
+
 
-            
        *** DAC wave generation feature ***
-       =================================== 
-       [..]     
+       ===================================
+       [..]
        Both DAC channels of DAC1 can be used to generate
        note that wave generation is not available in DAC2.
          (#) Noise wave
          (#) Triangle wave
-      
+
        Wave generation is NOT available in DAC2.
 
        *** DAC data format ***
        =======================
-       [..]   
+       [..]
        The DAC data format can be:
          (#) 8-bit right alignment using DAC_ALIGN_8B_R
          (#) 12-bit left alignment using DAC_ALIGN_12B_L
          (#) 12-bit right alignment using DAC_ALIGN_12B_R
-  
-       *** DAC data value to voltage correspondance ***  
-       ================================================ 
-       [..] 
+
+       *** DAC data value to voltage correspondance ***
+       ================================================
+       [..]
        The analog output voltage on each DAC channel pin is determined
-       by the following equation: 
-       [..] 
-       DAC_OUTx = VREF+ * DOR / 4095     
+       by the following equation:
+       [..]
+       DAC_OUTx = VREF+ * DOR / 4095
        (+) with  DOR is the Data Output Register
-       [..]  
+       [..]
           VEF+ is the input voltage reference (refer to the device datasheet)
-       [..]        
+       [..]
         e.g. To set DAC_OUT1 to 0.7V, use
        (+)  Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V
-  
+
        *** DMA requests  ***
        =====================
-       [..]    
-       A DMA1 or DMA2 request can be generated when an external trigger 
-       (but not a software trigger) occurs if DMA1 or DMA2 requests are 
+       [..]
+       A DMA1 or DMA2 request can be generated when an external trigger
+       (but not a software trigger) occurs if DMA1 or DMA2 requests are
        enabled using HAL_DAC_Start_DMA().
        [..]
        DMA1 requests are mapped as following:
          (#) DAC1 channel1: mapped either on
-         (++) DMA1 channel3 
+         (++) DMA1 channel3
          (++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
              which must be already configured
-         (#) DAC1 channel2: 
+         (#) DAC1 channel2:
              (for STM32F3 devices having 2 channels on DAC1)
              mapped either on
-         (++) DMA1 channel4 
+         (++) DMA1 channel4
          (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
              which must be already configured
-      
-         (#) DAC2 channel1: mapped either on 
+
+         (#) DAC2 channel1: mapped either on
              (for STM32F3 devices having 2 DAC)
-         (++) DMA1 channel4 
+         (++) DMA1 channel4
          (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
              which must be already configured
-    
 
-       (@) For Dual mode and specific signal (Triangle and noise) generation please 
-       refer to Extended Features Driver description        
+
+       (@) For Dual mode and specific signal (Triangle and noise) generation please
+       refer to Extended Features Driver description
 
                       ##### How to use this driver #####
   ==============================================================================
-    [..]          
+    [..]
       (+) DAC APB clock must be enabled to get write access to DAC
           registers using HAL_DAC_Init()
       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
@@ -145,27 +145,27 @@
 
      *** Polling mode IO operation ***
      =================================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start() 
+     [..]
+       (+) Start the DAC peripheral using HAL_DAC_Start()
        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
        (+) Stop the DAC peripheral using HAL_DAC_Stop()
-       
-     *** DMA mode IO operation ***    
+
+     *** DMA mode IO operation ***
      ==============================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
+     [..]
+       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
            of data to be transferred at each end of conversion
-       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
+       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
            HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
+       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
            HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
+       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
             add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
        (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
-           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
            HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
@@ -178,30 +178,30 @@
 
     Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
-      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.                 
+      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
-      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.   
-      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.        
-      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.                
+      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
+      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
-      (+) MspInitCallback         : DAC MspInit.  
+      (+) MspInitCallback         : DAC MspInit.
       (+) MspDeInitCallback       : DAC MspdeInit.
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
     Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
       weak (surcharged) function. It allows to reset following callbacks:
-      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.                 
+      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
       (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
-      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.   
-      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.        
-      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.                
+      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
+      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
       (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
-      (+) MspInitCallback         : DAC MspInit.  
+      (+) MspInitCallback         : DAC MspInit.
       (+) MspDeInitCallback       : DAC MspdeInit.
       (+) All Callbacks
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
@@ -209,7 +209,7 @@
       By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
       all callbacks are reset to the corresponding legacy weak (surcharged) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init 
+      reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
       and @ref  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
       If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -219,28 +219,28 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit 
+      using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
       or @ref HAL_DAC_Init function.
 
       When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
-      not defined, the callback registering feature is not available 
+      not defined, the callback registering feature is not available
       and weak (surcharged) callbacks are used.
 
 
      *** DAC HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DAC HAL driver.
-       
+
       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status 
-      
+      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
      [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros  
-   
- @endverbatim    
+      (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
   ******************************************************************************
   * @attention
   *
@@ -266,8 +266,8 @@
 /** @defgroup DAC DAC
   * @brief DAC HAL module driver
   * @{
-  */ 
- 
+  */
+
 #ifdef HAL_DAC_MODULE_ENABLED
 
 /* Private typedef -----------------------------------------------------------*/
@@ -290,22 +290,22 @@
   */
 
 /* Exported functions -------------------------------------------------------*/
-    
+
 /** @defgroup DAC_Exported_Functions DAC Exported Functions
   * @{
   */
 
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
-@verbatim    
+@verbatim
   ==============================================================================
               ##### Initialization and de-initialization functions #####
   ==============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC. 
-      (+) De-initialize the DAC. 
-         
+      (+) Initialize and configure the DAC.
+      (+) De-initialize the DAC.
+
 @endverbatim
   * @{
   */
@@ -318,7 +318,7 @@
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{ 
+{
   /* Check DAC handle */
   if(hdac == NULL)
   {
@@ -326,20 +326,20 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
   }
   /* Check the parameters */
   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-  
+
   if(hdac->State == HAL_DAC_STATE_RESET)
-  {  
+  {
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   /* Init the DAC Callback settings */
-  hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;    
+  hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
   hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
   hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
   hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
 #if defined(DAC_CHANNEL2_SUPPORT)
-  hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;    
+  hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
   hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
-  hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;       
-  hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2; 
+  hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
+  hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
 #endif /* DAC_CHANNEL2_SUPPORT */
   if(hdac->MspInitCallback == NULL)
   {
@@ -350,7 +350,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
     hdac->MspDeInitCallback             = HAL_DAC_MspDeInit;
   }
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-  
+
     /* Allocate lock resource and initialize it */
     hdac->Lock = HAL_UNLOCKED;
 
@@ -362,16 +362,16 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
     HAL_DAC_MspInit(hdac);
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
   }
-  
+
   /* Initialize the DAC state*/
   hdac->State = HAL_DAC_STATE_BUSY;
-       
+
   /* Set DAC error code to none */
   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-  
+
   /* Initialize the DAC state*/
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
 
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   if(hdac->MspDeInitCallback == NULL)
   {
@@ -403,15 +403,15 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
   }
   /* DeInit the low level hardware */
   hdac->MspDeInitCallback(hdac);
-  
-#else 
+
+#else
   /* DeInit the low level hardware */
   HAL_DAC_MspDeInit(hdac);
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-  
+
   /* Set DAC error code to none */
   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_RESET;
 
@@ -435,13 +435,13 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_MspInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @brief  DeInitialize the DAC MSP.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.  
+  *         the configuration information for the specified DAC.
   * @retval None
   */
 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
@@ -451,7 +451,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_DAC_MspDeInit could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -459,12 +459,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
   */
 
 /** @defgroup DAC_Exported_Functions_Group2 Input and Output operation functions
- *  @brief    IO operation functions 
+ *  @brief    IO operation functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
              ##### IO operation functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
       (+) Start conversion.
       (+) Stop conversion.
@@ -472,7 +472,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
       (+) Stop conversion and disable DMA transfer.
       (+) Get result of conversion.
       (+) Get result of dual mode conversion.
-                     
+
 @endverbatim
   * @{
   */
@@ -481,11 +481,11 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
   * @brief  Enables DAC and starts conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
-  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected  
+  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
@@ -496,7 +496,7 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel
 
   /* Note : This function is defined into this file for library reference */
   /*        Function content is located into file stm32f3xx_hal_dac_ex.c  */
-  
+
   /* Return function status */
   return HAL_ERROR;
 }
@@ -505,24 +505,24 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel
   * @brief  Disables DAC and stop conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
-  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected  
+  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-  
+
   /* Disable the Peripheral */
   __HAL_DAC_DISABLE(hdac, Channel);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -531,33 +531,33 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
   * @brief  Disables DAC and stop conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
-  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected    
+  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
 {
   HAL_StatusTypeDef status = HAL_OK;
-    
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-  
+
   /* Disable the selected DAC channel DMA request */
     hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-    
+
   /* Disable the Peripheral */
   __HAL_DAC_DISABLE(hdac, Channel);
-  
+
   /* Disable the DMA channel */
   /* Channel1 is used */
   if (Channel == DAC_CHANNEL_1)
   {
     /* Disable the DMA channel */
-    status = HAL_DMA_Abort(hdac->DMA_Handle1);   
-    
+    status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
     /* Disable the DAC DMA underrun interrupt */
     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
   }
@@ -567,25 +567,25 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
   else /* Channel2 is used */
   {
     /* Disable the DMA channel */
-    status = HAL_DMA_Abort(hdac->DMA_Handle2);   
-    
+    status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
     /* Disable the DAC DMA underrun interrupt */
     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
   }
 #endif /* DAC_CHANNEL2_SUPPORT */
-    
+
   /* Check if DMA Channel effectively disabled */
   if (status != HAL_OK)
   {
     /* Update DAC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;      
+    hdac->State = HAL_DAC_STATE_ERROR;
   }
   else
   {
     /* Change DAC state */
     hdac->State = HAL_DAC_STATE_READY;
   }
-  
+
   /* Return function status */
   return status;
 }
@@ -594,11 +594,11 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
   * @brief  Returns the last data output value of the selected DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
-  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected 
+  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
   * @retval The selected DAC channel data output value.
   */
 __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
@@ -635,21 +635,21 @@ __weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
 /**
   * @}
   */
-  
+
 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
+ *  @brief    Peripheral Control functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
              ##### Peripheral Control functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
-      (+) Configure channels. 
+      (+) Configure channels.
       (+) Configure Triangle wave generation.
       (+) Configure Noise wave generation.
       (+) Set the specified data holding register value for DAC channel.
       (+) Set the specified data holding register value for Dual DAC channels.
-      
+
 @endverbatim
   * @{
   */
@@ -659,11 +659,11 @@ __weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @param  sConfig DAC configuration structure.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
-  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected 
+  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
   * @retval HAL status
   */
 
@@ -679,7 +679,7 @@ __weak HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_Chan
 }
 
 __weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{ 
+{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hdac);
   UNUSED(Channel);
@@ -694,7 +694,7 @@ __weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Chan
 }
 
 __weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{ 
+{
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hdac);
   UNUSED(Alignment);
@@ -713,18 +713,18 @@ __weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_
   */
 
 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Error functions
- *  @brief   DAC Peripheral State and Error functions 
+ *  @brief   DAC Peripheral State and Error functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
             ##### DAC Peripheral State and Error functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Check the DAC state.
       (+) Check the DAC Errors.
 
-        
+
 @endverbatim
   * @{
   */
@@ -761,7 +761,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
   */
 
 /**
-  * @brief  Conversion complete callback in non blocking mode for Channel1 
+  * @brief  Conversion complete callback in non blocking mode for Channel1
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
@@ -777,7 +777,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
 }
 
 /**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
+  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
@@ -836,7 +836,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User DAC Callback
-  *         To be used instead of the weak (surcharged) predefined callback 
+  *         To be used instead of the weak (surcharged) predefined callback
   * @param hdac : DAC handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -845,12 +845,12 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
   *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
   *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
   *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
-  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID      
-  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID 
-  *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID         
-  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID         
-  *          @arg @ref HAL_DAC_MSP_INIT_CB_ID           DAC MSP Init Callback ID        
-  *          @arg @ref HAL_DAC_MSP_DEINIT_CB_ID         DAC MSP DeInit Callback ID   
+  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
+  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_MSP_INIT_CB_ID           DAC MSP Init Callback ID
+  *          @arg @ref HAL_DAC_MSP_DEINIT_CB_ID         DAC MSP DeInit Callback ID
   *
     * @param pCallback : pointer to the Callback function
   * @retval status
@@ -868,7 +868,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal
 
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   if(hdac->State == HAL_DAC_STATE_READY)
   {
     switch (CallbackId)
@@ -905,7 +905,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal
       break;
     default :
       /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
+      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
       /* update return status */
       status =  HAL_ERROR;
       break;
@@ -923,7 +923,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal
       break;
     default :
       /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
+      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
       /* update return status */
       status =  HAL_ERROR;
       break;
@@ -932,7 +932,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal
   else
   {
     /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
     /* update return status */
     status =  HAL_ERROR;
   }
@@ -944,20 +944,20 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal
 
 /**
   * @brief  Unregister a User DAC Callback
-  *         DAC Callback is redirected to the weak (surcharged) predefined callback 
+  *         DAC Callback is redirected to the weak (surcharged) predefined callback
   * @param hdac : DAC handle
   * @param CallbackId : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
-  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 tranfer Complete Callback ID     
-  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID        
-  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID                
-  *          @arg @ref HAL_DMA_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID             
-  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID             
-  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID        
-  *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID                
-  *          @arg @ref HAL_DMA_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID             
-  *          @arg @ref HAL_DAC_MSP_INIT_CB_ID              DAC MSP Init Callback ID                 
-  *          @arg @ref HAL_DAC_MSP_DEINIT_CB_ID            DAC MSP DeInit Callback ID               
+  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 tranfer Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
+  *          @arg @ref HAL_DMA_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
+  *          @arg @ref HAL_DMA_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_MSP_INIT_CB_ID              DAC MSP Init Callback ID
+  *          @arg @ref HAL_DAC_MSP_DEINIT_CB_ID            DAC MSP DeInit Callback ID
   *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
   * @retval status
   */
@@ -967,7 +967,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_C
 
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   if(hdac->State == HAL_DAC_STATE_READY)
   {
     switch (CallbackId)
@@ -1020,7 +1020,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_C
       break;
     default :
       /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
+      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
       /* update return status */
       status =  HAL_ERROR;
       break;
@@ -1038,7 +1038,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_C
       break;
     default :
       /* Update the error code */
-      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
+      hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
       /* update return status */
       status =  HAL_ERROR;
       break;
@@ -1047,7 +1047,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_C
   else
   {
     /* Update the error code */
-    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
     /* update return status */
     status =  HAL_ERROR;
   }

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c

@@ -3,22 +3,22 @@
   * @file    stm32f3xx_hal_dac_ex.c
   * @author  MCD Application Team
   * @brief   DACEx HAL module driver.
-  *          This file provides firmware functions to manage the extended 
-  *          functionalities of the DAC peripheral.  
-  *     
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the DAC peripheral.
   *
-  @verbatim   
+  *
+  @verbatim
   ==============================================================================
                       ##### How to use this driver #####
   ==============================================================================
-    [..]          
+    [..]
       (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
 
- @endverbatim    
+ @endverbatim
   ******************************************************************************
   * @attention
   *
@@ -57,16 +57,16 @@
   */
 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
 
 #if defined(STM32F303xE) || defined(STM32F398xx)                         || \
     defined(STM32F303xC) || defined(STM32F358xx)                         || \
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
-    defined(STM32F373xC) || defined(STM32F378xx) 
+    defined(STM32F373xC) || defined(STM32F378xx)
 /* DAC channel 2 is available on top of DAC channel 1U */
 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 #endif /* STM32F303xE || STM32F398xx                || */
        /* STM32F303xC || STM32F358xx                || */
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
@@ -81,17 +81,17 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
   */
 
 /** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
- *  @brief   	Peripheral Control functions 
+ *  @brief      Peripheral Control functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
              ##### Peripheral Control functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
       (+) Set the specified data holding register value for DAC channel.
       (+) Set the specified data holding register value for dual DAC channel
-	      (when DAC channel 2 is present in DAC 1U)
-      
+          (when DAC channel 2 is present in DAC 1U)
+
 @endverbatim
   * @{
   */
@@ -100,7 +100,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
   * @brief  Set the specified data holding register value for DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
@@ -110,14 +110,14 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{  
+{
   __IO uint32_t tmp = 0U;
-  
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_ALIGN(Alignment));
   assert_param(IS_DAC_DATA(Data));
-   
+
   tmp = (uint32_t) (hdac->Instance);
 
 /* DAC 1 has 1 or 2 channels - no DAC2 */
@@ -142,7 +142,7 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
 
   /* Set the DAC channel1 selected data holding register */
   *(__IO uint32_t *) tmp = Data;
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -205,20 +205,20 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
   */
 
 /** @defgroup DACEx_Exported_Functions_Group2 DACEx Input and Output operation functions
- *  @brief    IO operation functions 
+ *  @brief    IO operation functions
  *
-@verbatim   
+@verbatim
   ==============================================================================
              ##### IO operation functions #####
-  ==============================================================================  
+  ==============================================================================
     [..]  This section provides functions allowing to:
       (+) Start conversion.
       (+) Start conversion and enable DMA transfer.
       (+) Get result of conversion.
       (+) Handle DAC IRQ's.
-      (+) Generate triangular-wave                   
+      (+) Generate triangular-wave
       (+) Generate noise-wave
-	  (+) Callback functions for DAC1 Channel2 (when supported)
+      (+) Callback functions for DAC1 Channel2 (when supported)
 @endverbatim
   * @{
   */
@@ -233,7 +233,7 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
   * @brief  Enables DAC and starts conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -243,16 +243,16 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
   /* Enable the Peripheral */
   __HAL_DAC_ENABLE(hdac, Channel);
-  
+
   if(Channel == DAC_CHANNEL_1)
   {
     /* Check if software trigger enabled */
@@ -271,13 +271,13 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
     }
   }
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-    
+
   /* Return function status */
   return HAL_OK;
 }
@@ -294,39 +294,39 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
   * @brief  Enables DAC and starts conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  * @retval HAL status 
+  * @retval HAL status
   */
 
 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
   /* Enable the Peripheral */
   __HAL_DAC_ENABLE(hdac, Channel);
-  
+
   /* Check if software trigger enabled */
   if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
   {
     /* Enable the selected DAC software conversion */
     SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
   }
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-    
+
   /* Return function status */
   return HAL_OK;
 }
@@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
   * @brief  Enables DAC and starts conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -360,14 +360,14 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
 {
   uint32_t tmpreg = 0U;
-    
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
   assert_param(IS_DAC_ALIGN(Alignment));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
 
@@ -375,15 +375,15 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
   {
     /* Set the DMA transfer complete callback for channel1 */
     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-    
+
     /* Set the DMA half transfer complete callback for channel1 */
     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-      
+
     /* Set the DMA error callback for channel1 */
     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
 
     /* Enable the selected DAC channel1 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);   
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
 
     /* Case of use of channel 1U */
     switch(Alignment)
@@ -408,16 +408,16 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
   {
     /* Set the DMA transfer complete callback for channel2 */
     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-    
+
     /* Set the DMA half transfer complete callback for channel2 */
     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-       
+
     /* Set the DMA error callback for channel2 */
     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
- 
+
     /* Enable the selected DAC channel2 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); 
-   
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
     /* Case of use of channel 2U */
     switch(Alignment)
     {
@@ -437,7 +437,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
         break;
     }
   }
- 
+
   /* Enable the DMA Channel */
   if(Channel == DAC_CHANNEL_1)
   {
@@ -446,7 +446,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
 
     /* Enable the DMA Channel */
     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  } 
+  }
   else
   {
     /* Enable the DAC DMA underrun interrupt */
@@ -455,13 +455,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
     /* Enable the DMA Channel */
     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
   }
- 
+
   /* Process Unlocked */
   __HAL_UNLOCK(hdac);
 
   /* Enable the Peripheral */
   __HAL_DAC_ENABLE(hdac, Channel);
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -478,7 +478,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
   * @brief  Enables DAC and starts conversion of channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   * @param  pData The destination peripheral Buffer address.
@@ -493,29 +493,29 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
 {
   uint32_t tmpreg = 0U;
-    
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
   assert_param(IS_DAC_ALIGN(Alignment));
-  
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-    
+
   /* Set the DMA transfer complete callback for channel1 */
   hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-  
+
   /* Set the DMA half transfer complete callback for channel1 */
   hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-    
+
   /* Set the DMA error callback for channel1 */
   hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
 
   /* Enable the selected DAC channel1 DMA request */
   SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-    
+
   /* Case of use of channel 1U */
   switch(Alignment)
   {
@@ -534,20 +534,20 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
     default:
       break;
   }
-  
+
   /* Enable the DMA Channel */
   /* Enable the DAC DMA underrun interrupt */
   __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
 
   /* Enable the DMA Channel */
   HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
- 
+
   /* Process Unlocked */
   __HAL_UNLOCK(hdac);
 
   /* Enable the Peripheral */
-  __HAL_DAC_ENABLE(hdac, Channel); 
- 
+  __HAL_DAC_ENABLE(hdac, Channel);
+
   /* Return function status */
   return HAL_OK;
 }
@@ -565,7 +565,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
   * @brief  Returns the last data output value of the selected DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -575,9 +575,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-  
+
   /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1) 
+  if(Channel == DAC_CHANNEL_1)
   {
     return hdac->Instance->DOR1;
   }
@@ -599,7 +599,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
   * @brief  Returns the last data output value of the selected DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  channel The selected DAC channel. 
+  * @param  channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   * @retval The selected DAC channel data output value.
@@ -608,7 +608,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
 {
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-  
+
   /* Returns the DAC channel data output register value */
   return hdac->Instance->DOR1;
 }
@@ -651,7 +651,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
 /**
   * @brief  Handles DAC interrupt request
   *         This function uses the interruption of DMA
-  *         underrun.  
+  *         underrun.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
@@ -659,23 +659,23 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
 void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
 {
   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
-  { 
+  {
     /* Check underrun flag of DAC channel 1U */
     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
     {
       /* Change DAC state to error state */
       hdac->State = HAL_DAC_STATE_ERROR;
-    
+
       /* Set DAC error code to chanel1 DMA underrun error */
       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-          
+
       /* Clear the underrun flag */
       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-    
+
       /* Disable the selected DAC channel1 DMA request */
       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-    
-      /* Error callback */ 
+
+      /* Error callback */
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
       hdac->DMAUnderrunCallbackCh1(hdac);
 #else
@@ -683,7 +683,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
 #endif
     }
   }
-  
+
   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
   {
     /* Check underrun flag of DAC channel 2 */
@@ -691,16 +691,16 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
     {
       /* Change DAC state to error state */
       hdac->State = HAL_DAC_STATE_ERROR;
-    
+
       /* Set DAC error code to channel2 DMA underrun error */
       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
-    
+
       /* Clear the underrun flag */
       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-    
+
       /* Disable the selected DAC channel1 DMA request */
       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-   
+
       /* Error callback */
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
       hdac->DMAUnderrunCallbackCh2(hdac);
@@ -722,7 +722,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
 /**
   * @brief  Handles DAC interrupt request
   *         This function uses the interruption of DMA
-  *         underrun.  
+  *         underrun.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
@@ -730,23 +730,23 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
 void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
 {
   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
-  {  
+  {
     /* Check underrun flag of DAC channel 1U */
     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
     {
       /* Change DAC state to error state */
       hdac->State = HAL_DAC_STATE_ERROR;
-    
+
       /* Set DAC error code to chanel1 DMA underrun error */
       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
-    
+
       /* Clear the underrun flag */
       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-    
+
       /* Disable the selected DAC channel1 DMA request */
       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-    
-      /* Error callback */ 
+
+      /* Error callback */
       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
     }
   }
@@ -760,11 +760,11 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @param  sConfig DAC configuration structure.
-  * @param  Channel The selected DAC channel. 
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
-  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected 
+  *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+  *            @arg DAC_CHANNEL_1: DAC2 Channel1 selected
   * @retval HAL status
   */
 
@@ -776,68 +776,68 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
 
 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-  if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1)) 
+  if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
   {
     /* Output Buffer (BOFF1) control */
-    assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));    
+    assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
   }
   else /* DAC1 channel 2U & DAC2 channel 1U */
   {
     /* Output Switch (OUTEN) control */
-    assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));    
-  }    
+    assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
+  }
 #else
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));    
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
-  assert_param(IS_DAC_CHANNEL(Channel));   
- 
+  assert_param(IS_DAC_CHANNEL(Channel));
+
   /* Process locked */
   __HAL_LOCK(hdac);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_BUSY;
-  
+
   /* Get the DAC CR value */
   tmpreg1 = hdac->Instance->CR;
-  
+
   /* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */
-  
+
   /* Configure for the selected DAC channel: buffer output or switch output, trigger */
   /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value OR */   
-  /* Set OUTEN bit according to DAC_OutputSwitch value */   
+  /* Set BOFFx bit according to DAC_OutputBuffer value OR */
+  /* Set OUTEN bit according to DAC_OutputSwitch value */
 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-  if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1)) 
+  if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
   {
     /* Output Buffer (BOFF1) control */
     tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
-    tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);    
+    tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
   }
   else /* DAC1 channel 2U & DAC2 channel 1U */
   {
     /* Output Switch (OUTEN) control */
-    tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);    
-    tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);    
-  }    
+    tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
+    tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
+  }
 #else
   tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
   tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
 #endif  /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
-  
+
   /* Calculate CR register value depending on DAC_Channel */
   tmpreg1 |= tmpreg2 << Channel;
   /* Write to DAC CR */
   hdac->Instance->CR = tmpreg1;
-  
+
   /* Disable wave generation */
   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
 
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
-  
+
   /* Process unlocked */
   __HAL_UNLOCK(hdac);
-  
+
   /* Return function status */
   return HAL_OK;
 }
@@ -930,7 +930,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
 
   /* Enable the selected wave generation for the selected DAC channel */
   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
-  
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
 
@@ -1024,31 +1024,31 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
 /** @addtogroup DACEx_Private_Functions
   * @{
   */
-  
+
 /**
-  * @brief  DMA conversion complete callback. 
+  * @brief  DMA conversion complete callback.
   * @param  hdma pointer to DMA handle.
   * @retval None
   */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
+static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
 {
   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
+
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   hdac->ConvCpltCallbackCh1(hdac);
 #else
-  HAL_DAC_ConvCpltCallbackCh1(hdac); 
-#endif 
-  
+  HAL_DAC_ConvCpltCallbackCh1(hdac);
+#endif
+
   hdac->State= HAL_DAC_STATE_READY;
 }
 
 /**
-  * @brief  DMA half transfer complete callback. 
+  * @brief  DMA half transfer complete callback.
   * @param  hdma pointer to DMA handle.
   * @retval None
   */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
+static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
 {
     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 
@@ -1056,28 +1056,28 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   hdac->ConvHalfCpltCallbackCh1(hdac);
 #else
-    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
+    HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
 #endif
 }
 
 /**
-  * @brief  DMA error callback 
+  * @brief  DMA error callback
   * @param  hdma pointer to DMA handle.
   * @retval None
   */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
+static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
 {
   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
+
   /* Set DAC error code to DMA error */
   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
+
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   hdac->ErrorCallbackCh1(hdac);
-#else  
-  HAL_DAC_ErrorCallbackCh1(hdac); 
+#else
+  HAL_DAC_ErrorCallbackCh1(hdac);
 #endif
-    
+
   hdac->State= HAL_DAC_STATE_READY;
 }
 
@@ -1087,58 +1087,58 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
      defined(STM32F373xC) || defined(STM32F378xx)
 /* DAC channel 2 is available on top of DAC channel 1U */
 /**
-  * @brief  DMA conversion complete callback. 
+  * @brief  DMA conversion complete callback.
   * @param  hdma pointer to DMA handle.
   * @retval None
   */
-static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
+static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
 {
   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)  
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   hdac->ConvCpltCallbackCh2(hdac);
 #else
-  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
+  HAL_DACEx_ConvCpltCallbackCh2(hdac);
 #endif
-  
+
   hdac->State= HAL_DAC_STATE_READY;
 }
 
 /**
-  * @brief  DMA half transfer complete callback. 
+  * @brief  DMA half transfer complete callback.
   * @param  hdma pointer to DMA handle.
   * @retval None
   */
-static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
+static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
 {
     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 
     /* Conversion complete callback */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)  
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   hdac->ConvHalfCpltCallbackCh2(hdac);
 #else
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
+    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
 #endif
 }
 
 /**
-  * @brief  DMA error callback 
+  * @brief  DMA error callback
   * @param  hdma pointer to DMA handle.
   * @retval None
   */
-static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
+static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
 {
   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
+
   /* Set DAC error code to DMA error */
   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
+
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
   hdac->ErrorCallbackCh2(hdac);
-#else 
-  HAL_DACEx_ErrorCallbackCh2(hdac); 
+#else
+  HAL_DACEx_ErrorCallbackCh2(hdac);
 #endif
-    
+
   hdac->State= HAL_DAC_STATE_READY;
 }
 #endif /* STM32F303xE || STM32F398xx                || */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c

@@ -3,61 +3,61 @@
   * @file    stm32f3xx_hal_dma.c
   * @author  MCD Application Team
   * @brief   DMA HAL module driver.
-  *    
-  *         This file provides firmware functions to manage the following 
+  *
+  *         This file provides firmware functions to manage the following
   *         functionalities of the Direct Memory Access (DMA) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral State and errors functions
-  @verbatim     
-  ==============================================================================      
+  @verbatim
+  ==============================================================================
                         ##### How to use this driver #####
-  ============================================================================== 
+  ==============================================================================
   [..]
    (#) Enable and configure the peripheral to be connected to the DMA Channel
-       (except for internal SRAM / FLASH memories: no initialization is 
+       (except for internal SRAM / FLASH memories: no initialization is
        necessary). Please refer to Reference manual for connection between peripherals
        and DMA requests .
 
-   (#) For a given Channel, program the required configuration through the following parameters:   
-       Transfer Direction, Source and Destination data formats, 
-       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, 
+   (#) For a given Channel, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats,
+       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
        using HAL_DMA_Init() function.
 
-   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
        detection.
-                    
+
    (#) Use HAL_DMA_Abort() function to abort the current transfer
-                   
+
      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
      *** Polling mode IO operation ***
-     =================================   
-    [..] 
-      (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
+     =================================
+    [..]
+      (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
           address and destination address and the Length of data to be transferred
-      (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
+      (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
           case a fixed Timeout can be configured by User depending from his application.
 
-     *** Interrupt mode IO operation ***    
-     =================================== 
+     *** Interrupt mode IO operation ***
+     ===================================
     [..]
       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-      (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
-      (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
-          Source address and destination address and the Length of data to be transferred. 
-          In this case the DMA interrupt is configured 
+      (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+      (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+          Source address and destination address and the Length of data to be transferred.
+          In this case the DMA interrupt is configured
       (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-      (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
-          add his own function by customization of function pointer XferCpltCallback and 
-          XferErrorCallback (i.e a member of DMA handle structure). 
+      (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+          add his own function by customization of function pointer XferCpltCallback and
+          XferErrorCallback (i.e a member of DMA handle structure).
 
      *** DMA HAL driver macros list ***
-     ============================================= 
+     =============================================
      [..]
        Below the list of most used macros in DMA HAL driver.
 
-     [..] 
-      (@) You can refer to the DMA HAL driver header file for more useful macros  
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
 
   @endverbatim
   ******************************************************************************
@@ -72,7 +72,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal.h"
@@ -109,41 +109,41 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
   */
 
 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief   Initialization and de-initialization functions 
+ *  @brief   Initialization and de-initialization functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
              ##### Initialization and de-initialization functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This section provides functions allowing to initialize the DMA Channel source
-    and destination addresses, incrementation and data sizes, transfer direction, 
+    and destination addresses, incrementation and data sizes, transfer direction,
     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
     [..]
     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.  
+    reference manual.
 
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  Initialize the DMA according to the specified
   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
+  *               the configuration information for the specified DMA Channel.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{ 
+{
   uint32_t tmp = 0U;
-  
+
   /* Check the DMA handle allocation */
   if(NULL == hdma)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
@@ -153,18 +153,18 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
   assert_param(IS_DMA_MODE(hdma->Init.Mode));
   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-  
+
   /* Change DMA peripheral state */
   hdma->State = HAL_DMA_STATE_BUSY;
 
   /* Get the CR register value */
   tmp = hdma->Instance->CCR;
-  
+
   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
                       DMA_CCR_DIR));
-  
+
   /* Prepare the DMA Channel configuration */
   tmp |=  hdma->Init.Direction        |
           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
@@ -172,28 +172,28 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
           hdma->Init.Mode                | hdma->Init.Priority;
 
   /* Write to DMA Channel CR register */
-  hdma->Instance->CCR = tmp;  
-  
-  /* Initialize DmaBaseAddress and ChannelIndex parameters used 
+  hdma->Instance->CCR = tmp;
+
+  /* Initialize DmaBaseAddress and ChannelIndex parameters used
      by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
   DMA_CalcBaseAndBitshift(hdma);
-  
+
   /* Initialise the error code */
   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 
   /* Initialize the DMA state*/
   hdma->State = HAL_DMA_STATE_READY;
-  
+
   /* Allocate lock resource and initialize it */
   hdma->Lock = HAL_UNLOCKED;
-  
+
   return HAL_OK;
-}  
-  
+}
+
 /**
-  * @brief  DeInitialize the DMA peripheral 
+  * @brief  DeInitialize the DMA peripheral
   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
+  *               the configuration information for the specified DMA Channel.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
@@ -203,7 +203,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
 
@@ -218,11 +218,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 
   /* Reset DMA Channel peripheral address register */
   hdma->Instance->CPAR  = 0U;
-  
+
   /* Reset DMA Channel memory address register */
   hdma->Instance->CMAR = 0U;
 
-  /* Get DMA Base Address */  
+  /* Get DMA Base Address */
   DMA_CalcBaseAndBitshift(hdma);
 
   /* Clear all flags */
@@ -250,20 +250,20 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   * @}
   */
 
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions 
- *  @brief   I/O operation functions  
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   I/O operation functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       #####  IO operation functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and 
+      (+) Configure the source, destination address and data length and
           Start DMA transfer with interrupt
       (+) Abort DMA transfer
       (+) Poll for transfer complete
-      (+) Handle DMA interrupt request  
+      (+) Handle DMA interrupt request
 
 @endverbatim
   * @{
@@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 /**
   * @brief  Start the DMA Transfer.
   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
+  *                     the configuration information for the specified DMA Channel.
   * @param  SrcAddress The source memory Buffer address
   * @param  DstAddress The destination memory Buffer address
   * @param  DataLength The length of data to be transferred from source to destination
@@ -280,46 +280,46 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   */
 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
-	HAL_StatusTypeDef status = HAL_OK;
+    HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the parameters */
   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma);
-  
+
   if(HAL_DMA_STATE_READY == hdma->State)
   {
-  	/* Change DMA peripheral state */  
-  	hdma->State = HAL_DMA_STATE_BUSY;
-  	
-  	hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-  	
-  	/* Disable the peripheral */
-  	hdma->Instance->CCR &= ~DMA_CCR_EN;  
-  	
-  	/* Configure the source, destination address and the data length */
-  	DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-  	
-  	/* Enable the Peripheral */
-  	hdma->Instance->CCR |= DMA_CCR_EN;  
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    hdma->Instance->CCR |= DMA_CCR_EN;
   }
   else
   {
-  	/* Process Unlocked */
-  	__HAL_UNLOCK(hdma);
-  	
-  	/* Remain BUSY */
-  	status = HAL_BUSY;
-  }  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
 
-  return status; 
-} 
+    /* Remain BUSY */
+    status = HAL_BUSY;
+  }
+
+  return status;
+}
 
 /**
   * @brief  Start the DMA Transfer with interrupt enabled.
   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
+  *                     the configuration information for the specified DMA Channel.
   * @param  SrcAddress The source memory Buffer address
   * @param  DstAddress The destination memory Buffer address
   * @param  DataLength The length of data to be transferred from source to destination
@@ -327,53 +327,53 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
   */
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
-	HAL_StatusTypeDef status = HAL_OK;
+    HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the parameters */
   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
+
   /* Process locked */
   __HAL_LOCK(hdma);
-  
+
   if(HAL_DMA_STATE_READY == hdma->State)
   {
-  	/* Change DMA peripheral state */  
-  	hdma->State = HAL_DMA_STATE_BUSY;
-  	
-  	hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-  	
-  	/* Disable the peripheral */
-  	hdma->Instance->CCR &= ~DMA_CCR_EN;
-  	
-  	/* Configure the source, destination address and the data length */  
-  	DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-  	
-  	/* Enable the transfer complete, & transfer error interrupts */
-  	/* Half transfer interrupt is optional: enable it only if associated callback is available */
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+    /* Disable the peripheral */
+    hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the transfer complete, & transfer error interrupts */
+    /* Half transfer interrupt is optional: enable it only if associated callback is available */
     if(NULL != hdma->XferHalfCpltCallback )
     {
       hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
     }
-  	else
-  	{
-  		hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
-  		hdma->Instance->CCR &= ~DMA_IT_HT;
-  	}
-  	
-  	/* Enable the Peripheral */
-  	hdma->Instance->CCR |= DMA_CCR_EN;
+    else
+    {
+        hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
+        hdma->Instance->CCR &= ~DMA_IT_HT;
+    }
+
+    /* Enable the Peripheral */
+    hdma->Instance->CCR |= DMA_CCR_EN;
   }
   else
   {
-  	/* Process Unlocked */
-    __HAL_UNLOCK(hdma); 
-  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
     /* Remain BUSY */
     status = HAL_BUSY;
-  }     
-  
-  return status;    
-} 
+  }
+
+  return status;
+}
 
 /**
   * @brief  Abort the DMA Transfer.
@@ -387,29 +387,29 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
   {
     /* no transfer ongoing */
     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
-    
+
     return HAL_ERROR;
   }
   else
   {
     /* Disable DMA IT */
      hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-    
+
     /* Disable the channel */
     hdma->Instance->CCR &= ~DMA_CCR_EN;
-    
+
     /* Clear all flags */
     hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
   }
   /* Change the DMA state*/
-  hdma->State = HAL_DMA_STATE_READY; 
-  
+  hdma->State = HAL_DMA_STATE_READY;
+
   /* Process Unlocked */
   __HAL_UNLOCK(hdma);
-  
+
   return HAL_OK;
 }
 
@@ -420,39 +420,39 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{  
+{
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if(HAL_DMA_STATE_BUSY != hdma->State)
   {
     /* no transfer ongoing */
     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-        
+
     status = HAL_ERROR;
   }
   else
-  { 
-  
+  {
+
     /* Disable DMA IT */
     hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-    
+
     /* Disable the channel */
     hdma->Instance->CCR &= ~DMA_CCR_EN;
-    
+
     /* Clear all flags */
     hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-    
+
     /* Change the DMA state */
     hdma->State = HAL_DMA_STATE_READY;
-    
+
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
-    
-    /* Call User Abort callback */ 
+
+    /* Call User Abort callback */
     if(hdma->XferAbortCallback != NULL)
     {
       hdma->XferAbortCallback(hdma);
-    } 
+    }
   }
   return status;
 }
@@ -461,7 +461,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
   * @brief  Polling for transfer complete.
   * @param  hdma    pointer to a DMA_HandleTypeDef structure that contains
   *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel Specifies the DMA level complete.  
+  * @param  CompleteLevel Specifies the DMA level complete.
   * @param  Timeout       Timeout duration.
   * @retval HAL status
   */
@@ -469,7 +469,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
 {
   uint32_t temp;
   uint32_t tickstart = 0U;
-  
+
   if(HAL_DMA_STATE_BUSY != hdma->State)
   {
     /* no transfer ongoing */
@@ -477,14 +477,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     __HAL_UNLOCK(hdma);
     return HAL_ERROR;
   }
-  
+
   /* Polling mode not supported in circular mode */
   if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
   {
     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
     return HAL_ERROR;
   }
-  
+
   /* Get the level transfer complete flag */
   if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
   {
@@ -503,23 +503,23 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
   while(RESET == (hdma->DmaBaseAddress->ISR & temp))
   {
     if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
-    {      
+    {
       /* When a DMA transfer error occurs */
       /* A hardware clear of its EN bits is performed */
       /* Clear all flags */
       hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-      
+
       /* Update error code */
       hdma->ErrorCode = HAL_DMA_ERROR_TE;
 
       /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_READY;       
-      
+      hdma->State= HAL_DMA_STATE_READY;
+
       /* Process Unlocked */
       __HAL_UNLOCK(hdma);
-      
-      return HAL_ERROR;      
-    }      
+
+      return HAL_ERROR;
+    }
     /* Check for the Timeout */
     if(Timeout != HAL_MAX_DELAY)
     {
@@ -527,7 +527,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
       {
         /* Update error code */
         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-        
+
         /* Change the DMA state */
         hdma->State = HAL_DMA_STATE_READY;
 
@@ -544,18 +544,18 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
     /* Clear the transfer complete flag */
     hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
 
-    /* The selected Channelx EN bit is cleared (DMA is disabled and 
+    /* The selected Channelx EN bit is cleared (DMA is disabled and
     all transfers are complete) */
     hdma->State = HAL_DMA_STATE_READY;
   }
   else
-  { 
+  {
     /* Clear the half transfer complete flag */
     hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
   }
-  
+
   /* Process unlocked */
-  __HAL_UNLOCK(hdma);  
+  __HAL_UNLOCK(hdma);
 
   return HAL_OK;
 }
@@ -563,90 +563,90 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
 /**
   * @brief  Handle DMA interrupt request.
   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
+  *               the configuration information for the specified DMA Channel.
   * @retval None
   */
 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 {
-	uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+    uint32_t flag_it = hdma->DmaBaseAddress->ISR;
   uint32_t source_it = hdma->Instance->CCR;
-          
+
   /* Half Transfer Complete Interrupt management ******************************/
   if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
   {
-  	/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-  	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  	{
-  		/* Disable the half transfer interrupt */
-  		hdma->Instance->CCR &= ~DMA_IT_HT;
-  	}
-  	
-  	/* Clear the half transfer complete flag */
-  	hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
-  	
-  	/* DMA peripheral state is not updated in Half Transfer */
-  	/* State is updated only in Transfer Complete case */
-  	
-  	if(hdma->XferHalfCpltCallback != NULL)
-  	{
-  		/* Half transfer callback */
-  		hdma->XferHalfCpltCallback(hdma);
-  	}
+    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+    {
+        /* Disable the half transfer interrupt */
+        hdma->Instance->CCR &= ~DMA_IT_HT;
+    }
+
+    /* Clear the half transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
+
+    /* DMA peripheral state is not updated in Half Transfer */
+    /* State is updated only in Transfer Complete case */
+
+    if(hdma->XferHalfCpltCallback != NULL)
+    {
+        /* Half transfer callback */
+        hdma->XferHalfCpltCallback(hdma);
+    }
   }
-  
+
   /* Transfer Complete Interrupt management ***********************************/
   else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
   {
-  	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
-  	{
-  		/* Disable the transfer complete  & transfer error interrupts */
-  		/* if the DMA mode is not CIRCULAR */
-  		hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
-  		
-  		/* Change the DMA state */
-  		hdma->State = HAL_DMA_STATE_READY;
-  	}
-  	
-  	/* Clear the transfer complete flag */
-  	hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
-  	
-  	/* Process Unlocked */
-  	__HAL_UNLOCK(hdma);
-  	
-  	if(hdma->XferCpltCallback != NULL)
-  	{
-  		/* Transfer complete callback */
-  		hdma->XferCpltCallback(hdma);
-  	}
+    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+    {
+        /* Disable the transfer complete  & transfer error interrupts */
+        /* if the DMA mode is not CIRCULAR */
+        hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+    }
+
+    /* Clear the transfer complete flag */
+    hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+
+    if(hdma->XferCpltCallback != NULL)
+    {
+        /* Transfer complete callback */
+        hdma->XferCpltCallback(hdma);
+    }
   }
-  
+
   /* Transfer Error Interrupt management ***************************************/
   else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
   {
-  	/* When a DMA transfer error occurs */
+    /* When a DMA transfer error occurs */
     /* A hardware clear of its EN bits is performed */
     /* Then, disable all DMA interrupts */
     hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-    
+
     /* Clear all flags */
     hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
-    
+
     /* Update error code */
     hdma->ErrorCode = HAL_DMA_ERROR_TE;
-    
+
     /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;    
-    
+    hdma->State = HAL_DMA_STATE_READY;
+
     /* Process Unlocked */
-    __HAL_UNLOCK(hdma); 
-    
+    __HAL_UNLOCK(hdma);
+
     if(hdma->XferErrorCallback != NULL)
     {
-    	/* Transfer error callback */
-    	hdma->XferErrorCallback(hdma);
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
     }
   }
-}  
+}
 
 /**
   * @brief  Register callbacks
@@ -654,17 +654,17 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
   *                               the configuration information for the specified DMA Stream.
   * @param  CallbackID           User Callback identifer
   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @param  pCallback            pointer to private callback function which has pointer to 
+  * @param  pCallback            pointer to private callback function which has pointer to
   *                               a DMA_HandleTypeDef structure as parameter.
   * @retval HAL status
-  */                          
+  */
 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Process locked */
   __HAL_LOCK(hdma);
-  
+
   if(HAL_DMA_STATE_READY == hdma->State)
   {
     switch (CallbackID)
@@ -672,32 +672,32 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
      case  HAL_DMA_XFER_CPLT_CB_ID:
            hdma->XferCpltCallback = pCallback;
            break;
-       
+
      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
            hdma->XferHalfCpltCallback = pCallback;
-           break;         
+           break;
 
      case  HAL_DMA_XFER_ERROR_CB_ID:
            hdma->XferErrorCallback = pCallback;
-           break;         
-           
+           break;
+
      case  HAL_DMA_XFER_ABORT_CB_ID:
            hdma->XferAbortCallback = pCallback;
-           break; 
-           
+           break;
+
      default:
            status = HAL_ERROR;
-           break;                                                            
+           break;
     }
   }
   else
   {
     status = HAL_ERROR;
-  } 
-  
+  }
+
   /* Release Lock */
   __HAL_UNLOCK(hdma);
-  
+
   return status;
 }
 
@@ -708,14 +708,14 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
   * @param  CallbackID           User Callback identifer
   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
   * @retval HAL status
-  */              
+  */
 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
     /* Process locked */
   __HAL_LOCK(hdma);
-  
+
   if(HAL_DMA_STATE_READY == hdma->State)
   {
     switch (CallbackID)
@@ -723,39 +723,39 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
      case  HAL_DMA_XFER_CPLT_CB_ID:
            hdma->XferCpltCallback = NULL;
            break;
-       
+
      case  HAL_DMA_XFER_HALFCPLT_CB_ID:
            hdma->XferHalfCpltCallback = NULL;
-           break;         
+           break;
 
      case  HAL_DMA_XFER_ERROR_CB_ID:
            hdma->XferErrorCallback = NULL;
-           break;         
-           
+           break;
+
      case  HAL_DMA_XFER_ABORT_CB_ID:
            hdma->XferAbortCallback = NULL;
-           break; 
-     
+           break;
+
     case   HAL_DMA_XFER_ALL_CB_ID:
            hdma->XferCpltCallback = NULL;
            hdma->XferHalfCpltCallback = NULL;
            hdma->XferErrorCallback = NULL;
            hdma->XferAbortCallback = NULL;
-           break; 
-     
+           break;
+
     default:
            status = HAL_ERROR;
-           break;                                                            
+           break;
     }
   }
   else
   {
     status = HAL_ERROR;
-  } 
-  
+  }
+
   /* Release Lock */
   __HAL_UNLOCK(hdma);
-  
+
   return status;
 }
 
@@ -764,12 +764,12 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
   */
 
 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- *  @brief    Peripheral State functions 
+ *  @brief    Peripheral State functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                     ##### State and Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection provides functions allowing to
       (+) Check the DMA state
@@ -777,12 +777,12 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
 
 @endverbatim
   * @{
-  */  
+  */
 
 /**
   * @brief  Returns the DMA state.
   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
+  *               the configuration information for the specified DMA Channel.
   * @retval HAL state
   */
 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
@@ -816,7 +816,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
 /**
   * @brief  Set the DMA Transfer parameters.
   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
+  *                     the configuration information for the specified DMA Channel.
   * @param  SrcAddress The source memory Buffer address
   * @param  DstAddress The destination memory Buffer address
   * @param  DataLength The length of data to be transferred from source to destination
@@ -824,18 +824,18 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
-	/* Clear all flags */
+    /* Clear all flags */
   hdma->DmaBaseAddress->IFCR  = (DMA_FLAG_GL1 << hdma->ChannelIndex);
-  
+
   /* Configure DMA Channel data length */
   hdma->Instance->CNDTR = DataLength;
-  
+
   /* Peripheral to Memory */
   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {   
+  {
     /* Configure DMA Channel destination address */
     hdma->Instance->CPAR = DstAddress;
-    
+
     /* Configure DMA Channel source address */
     hdma->Instance->CMAR = SrcAddress;
   }
@@ -844,7 +844,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
   {
     /* Configure DMA Channel source address */
     hdma->Instance->CPAR = SrcAddress;
-    
+
     /* Configure DMA Channel destination address */
     hdma->Instance->CMAR = DstAddress;
   }
@@ -853,7 +853,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
 /**
   * @brief  Set the DMA base address and channel index depending on DMA instance
   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream. 
+  *                     the configuration information for the specified DMA Stream.
   * @retval None
   */
 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
@@ -866,7 +866,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
     hdma->DmaBaseAddress = DMA1;
   }
-  else 
+  else
   {
     /* DMA2 */
     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
@@ -892,7 +892,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-  
+
   /**
   * @}
   */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c

@@ -3,22 +3,22 @@
   * @file    stm32f3xx_hal_flash.c
   * @author  MCD Application Team
   * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the internal FLASH memory:
   *           + Program operations functions
-  *           + Memory Control functions 
+  *           + Memory Control functions
   *           + Peripheral State functions
-  *         
+  *
   @verbatim
   ==============================================================================
                         ##### FLASH peripheral features #####
   ==============================================================================
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
+       to the Flash memory. It implements the erase and program Flash memory operations
        and the read and write protection mechanisms.
 
   [..] The Flash memory interface accelerates code execution with a system of instruction
-      prefetch. 
+      prefetch.
 
   [..] The FLASH main features are:
       (+) Flash memory read operations
@@ -30,10 +30,10 @@
 
                      ##### How to use this driver #####
   ==============================================================================
-  [..]                             
-      This driver provides functions and macros to configure and program the FLASH 
+  [..]
+      This driver provides functions and macros to configure and program the FLASH
       memory of all STM32F3xx devices.
-    
+
       (#) FLASH Memory I/O Programming functions: this group includes all needed
           functions to erase and program the main memory:
         (++) Lock and Unlock the FLASH interface
@@ -50,8 +50,8 @@
         (++) Program the data Option Bytes
         (++) Get the Write protection.
         (++) Get the user option bytes.
-    
-      (#) Interrupts and flags management functions : this group 
+
+      (#) Interrupts and flags management functions : this group
           includes all needed functions to:
         (++) Handle FLASH interrupts
         (++) Wait for last FLASH operation according to its status
@@ -59,13 +59,13 @@
 
   [..] In addition to these function, this driver includes a set of macros allowing
        to handle the following operations:
-      
+
       (+) Set/Get the latency
       (+) Enable/Disable the prefetch buffer
       (+) Enable/Disable the half cycle access
       (+) Enable/Disable the FLASH interrupts
       (+) Monitor the FLASH flags status
-          
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -108,7 +108,7 @@
 /** @defgroup FLASH_Private_Macros FLASH Private Macros
   * @{
   */
- 
+
 /**
   * @}
   */
@@ -138,11 +138,11 @@ extern void    FLASH_PageErase(uint32_t PageAddress);
 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
   * @{
   */
-  
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
-  *  @brief   Programming operation functions 
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
+  *  @brief   Programming operation functions
   *
-@verbatim   
+@verbatim
 @endverbatim
   * @{
   */
@@ -152,17 +152,17 @@ extern void    FLASH_PageErase(uint32_t PageAddress);
   * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
   *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
   *
-  * @note   If an erase and a program operations are requested simultaneously,    
+  * @note   If an erase and a program operations are requested simultaneously,
   *         the erase operation is performed before the program one.
-  *  
-  * @note   FLASH should be previously erased before new programming (only exception to this 
+  *
+  * @note   FLASH should be previously erased before new programming (only exception to this
   *         is when 0x0000 is programmed)
   *
   * @param  TypeProgram   Indicate the way to program at a specified address.
   *                       This parameter can be a value of @ref FLASH_Type_Program
   * @param  Address       Specifie the address to be programmed.
   * @param  Data          Specifie the data to be programmed
-  * 
+  *
   * @retval HAL_StatusTypeDef HAL Status
   */
 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
@@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
   HAL_StatusTypeDef status = HAL_ERROR;
   uint8_t index = 0U;
   uint8_t nbiterations = 0U;
-  
+
   /* Process Locked */
   __HAL_LOCK(&pFlash);
 
@@ -180,7 +180,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
 
     /* Wait for last operation to be completed */
     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-  
+
   if(status == HAL_OK)
   {
     if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
@@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
 
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
-    
+
         /* If the program operation is completed, disable the PG Bit */
         CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
       /* In case of error, stop programming procedure */
@@ -227,20 +227,20 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
   * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
   *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
   *
-  * @note   If an erase and a program operations are requested simultaneously,    
+  * @note   If an erase and a program operations are requested simultaneously,
   *         the erase operation is performed before the program one.
   *
   * @param  TypeProgram  Indicate the way to program at a specified address.
   *                      This parameter can be a value of @ref FLASH_Type_Program
   * @param  Address      Specifie the address to be programmed.
   * @param  Data         Specifie the data to be programmed
-  * 
+  *
   * @retval HAL_StatusTypeDef HAL Status
   */
 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Process Locked */
   __HAL_LOCK(&pFlash);
 
@@ -250,7 +250,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
 
   /* Enable End of FLASH Operation and Error source interrupts */
   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
-  
+
   pFlash.Address = Address;
   pFlash.Data = Data;
 
@@ -286,7 +286,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
 void HAL_FLASH_IRQHandler(void)
 {
   uint32_t addresstmp = 0U;
-  
+
   /* Check FLASH operation error flags */
   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
   {
@@ -294,10 +294,10 @@ void HAL_FLASH_IRQHandler(void)
     addresstmp = pFlash.Address;
     /* Reset address */
     pFlash.Address = 0xFFFFFFFFU;
-  
+
     /* Save the Error code */
     FLASH_SetErrorCode();
-    
+
     /* FLASH error interrupt user callback */
     HAL_FLASH_OperationErrorCallback(addresstmp);
 
@@ -310,7 +310,7 @@ void HAL_FLASH_IRQHandler(void)
   {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-    
+
     /* Process can continue only if no error detected */
     if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
     {
@@ -361,17 +361,17 @@ void HAL_FLASH_IRQHandler(void)
       {
         /* Nb of 16-bit data to program can be decreased */
         pFlash.DataRemaining--;
-        
+
         /* Check if there are still 16-bit data to program */
         if(pFlash.DataRemaining != 0U)
         {
           /* Increment address to 16-bit */
           pFlash.Address += 2U;
           addresstmp = pFlash.Address;
-          
+
           /* Shift to have next 16-bit data */
           pFlash.Data = (pFlash.Data >> 16U);
-          
+
           /* Operation is completed, disable the PG Bit */
           CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
 
@@ -390,11 +390,11 @@ void HAL_FLASH_IRQHandler(void)
           {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
           }
-          else 
+          else
           {
             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
           }
-        
+
           /* Reset Address and stop Program procedure */
           pFlash.Address = 0xFFFFFFFFU;
           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
@@ -402,7 +402,7 @@ void HAL_FLASH_IRQHandler(void)
       }
     }
   }
-  
+
 
   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
   {
@@ -421,7 +421,7 @@ void HAL_FLASH_IRQHandler(void)
   * @brief  FLASH end of operation interrupt callback
   * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                 - Mass Erase: No return value expected
-  *                 - Pages Erase: Address of the page which has been erased 
+  *                 - Pages Erase: Address of the page which has been erased
   *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
   *                 - Program: Address which was selected for data program
   * @retval none
@@ -433,7 +433,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
@@ -451,22 +451,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
 
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
+   */
 }
 
 /**
   * @}
   */
 
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   management functions 
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   management functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the FLASH 
+    This subsection provides a set of functions allowing to control the FLASH
     memory operations.
 
 @endverbatim
@@ -505,8 +505,8 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void)
 {
   /* Set the LOCK Bit to lock the FLASH Registers access */
   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
-  
-  return HAL_OK;  
+
+  return HAL_OK;
 }
 
 /**
@@ -524,23 +524,23 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
   else
   {
     return HAL_ERROR;
-  }  
-  
-  return HAL_OK;  
+  }
+
+  return HAL_OK;
 }
 
 /**
   * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL Status 
+  * @retval HAL Status
   */
 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
 {
   /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
   CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
-  
-  return HAL_OK;  
+
+  return HAL_OK;
 }
-  
+
 /**
   * @brief  Launch the option byte loading.
   * @note   This function will reset automatically the MCU.
@@ -550,22 +550,22 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
 {
   /* Set the OBL_Launch bit to launch the option byte loading */
   SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
-  
+
   /* Wait for last operation to be completed */
   return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
 }
 
 /**
   * @}
-  */  
+  */
 
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions 
- *  @brief    Peripheral errors functions 
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
+ *  @brief    Peripheral errors functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### Peripheral Errors functions #####
- ===============================================================================  
+ ===============================================================================
     [..]
     This subsection permit to get in run-time errors of  the FLASH peripheral.
 
@@ -605,7 +605,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
 {
   /* Clean the error context */
   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-  
+
     /* Proceed to program the new data */
     SET_BIT(FLASH->CR, FLASH_CR_PG);
 
@@ -623,11 +623,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
      Even if the FLASH operation fails, the BUSY flag will be reset and an error
      flag will be set */
-     
+
   uint32_t tickstart = HAL_GetTick();
-     
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
-  { 
+
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
+  {
     if (Timeout != HAL_MAX_DELAY)
     {
       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
@@ -636,15 +636,15 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
       }
     }
   }
-  
+
   /* Check FLASH End of Operation flag  */
   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
   {
     /* Clear FLASH End of Operation pending bit */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
   }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  || 
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  ||
      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
   {
     /*Save the error code*/
@@ -664,7 +664,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
 static void FLASH_SetErrorCode(void)
 {
   uint32_t flags = 0U;
-  
+
   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
   {
     pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
@@ -677,7 +677,7 @@ static void FLASH_SetErrorCode(void)
   }
   /* Clear FLASH error pending bits */
   __HAL_FLASH_CLEAR_FLAG(flags);
-}  
+}
 /**
   * @}
   */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c

@@ -3,27 +3,27 @@
   * @file    stm32f3xx_hal_flash_ex.c
   * @author  MCD Application Team
   * @brief   Extended FLASH HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
+  *
+  *          This file provides firmware functions to manage the following
   *          functionalities of the FLASH peripheral:
   *           + Extended Initialization/de-initialization functions
   *           + Extended I/O operation functions
-  *           + Extended Peripheral Control functions 
-  *         
+  *           + Extended Peripheral Control functions
+  *
   @verbatim
   ==============================================================================
                ##### Flash peripheral extended features  #####
   ==============================================================================
-           
+
                       ##### How to use this driver #####
   ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory 
+  [..] This driver provides functions to configure and program the FLASH memory
        of all STM32F3xxx devices. It includes
-       
+
         (++) Set/Reset the write protection
         (++) Program the user Option Bytes
         (++) Get the Read protection Level
-  
+
   @endverbatim
   ******************************************************************************
   * @attention
@@ -62,7 +62,7 @@ extern FLASH_ProcessTypeDef pFlash;
 /**
   * @}
   */
-  
+
 /** @defgroup FLASHEx FLASHEx
   * @brief FLASH HAL Extension module driver
   * @{
@@ -86,7 +86,7 @@ extern FLASH_ProcessTypeDef pFlash;
   */
 /**
   * @}
-  */ 
+  */
 
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -115,37 +115,37 @@ static uint8_t           FLASH_OB_GetUser(void);
 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
   * @{
   */
-  
+
 /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
  *  @brief   FLASH Memory Erasing functions
   *
-@verbatim   
+@verbatim
   ==============================================================================
-                ##### FLASH Erasing Programming functions ##### 
+                ##### FLASH Erasing Programming functions #####
   ==============================================================================
 
     [..] The FLASH Memory Erasing functions, includes the following functions:
     (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
-    (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback 
+    (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
         is called with parameter 0xFFFFFFFF
 
     [..] Any operation of erase should follow these steps:
-    (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and 
+    (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
         program memory access.
     (#) Call the desired function to erase page.
-    (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access 
+    (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
        (recommended to protect the FLASH memory against possible unwanted operation).
 
 @endverbatim
   * @{
   */
-  
+
 
 /**
   * @brief  Perform a mass erase or erase the specified FLASH memory pages
   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
   *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access 
+  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
   *         (recommended to protect the FLASH memory against possible unwanted operation)
   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
   *         contains the configuration information for the erasing.
@@ -175,10 +175,10 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
       {
         /*Mass erase to be done*/
         FLASH_MassErase();
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-        
+
         /* If the erase operation is completed, disable the MER Bit */
         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
       }
@@ -189,27 +189,27 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
     /* Check the parameters */
     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
     assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
-    
+
       /* Page Erase requested on address located on bank1 */
       /* Wait for last operation to be completed */
       if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
       {
         /*Initialization of PageError variable*/
         *PageError = 0xFFFFFFFFU;
-        
+
         /* Erase page by page to be done*/
         for(address = pEraseInit->PageAddress;
             address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
             address += FLASH_PAGE_SIZE)
         {
           FLASH_PageErase(address);
-          
+
           /* Wait for last operation to be completed */
           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-          
+
           /* If the erase operation is completed, disable the PER Bit */
           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
-          
+
           if (status != HAL_OK)
           {
             /* In case of error, stop erase procedure and return the faulty address */
@@ -230,7 +230,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
   *         must be called before.
-  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access 
+  *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
   *         (recommended to protect the FLASH memory against possible unwanted operation)
   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
   *         contains the configuration information for the erasing.
@@ -249,7 +249,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
 
@@ -288,12 +288,12 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
 /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
  *  @brief   Option Bytes Programming functions
   *
-@verbatim   
+@verbatim
+  ==============================================================================
+                ##### Option Bytes Programming functions #####
   ==============================================================================
-                ##### Option Bytes Programming functions ##### 
-  ==============================================================================  
     [..]
-    This subsection provides a set of functions allowing to control the FLASH 
+    This subsection provides a set of functions allowing to control the FLASH
     option bytes operations.
 
 @endverbatim
@@ -465,7 +465,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
 {
   uint32_t value = 0U;
-  
+
   if (DATAAdress == OB_DATA_ADDRESS_DATA0)
   {
     /* Get value programmed in OB USER Data0 */
@@ -476,7 +476,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
     /* Get value programmed in OB USER Data1 */
     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
   }
-  
+
   return value;
 }
 
@@ -493,7 +493,7 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
  */
 
 /**
-  * @brief  Full erase of FLASH memory Bank 
+  * @brief  Full erase of FLASH memory Bank
   *
   * @retval None
   */
@@ -509,14 +509,14 @@ static void FLASH_MassErase(void)
 
 /**
   * @brief  Enable the write protection of the desired pages
-  * @note   An option byte erase is done automatically in this function. 
-  * @note   When the memory read protection level is selected (RDP level = 1), 
+  * @note   An option byte erase is done automatically in this function.
+  * @note   When the memory read protection level is selected (RDP level = 1),
   *         it is not possible to program or erase the flash page i if
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * 
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  *
   * @param  WriteProtectPage specifies the page(s) to be write protected.
-  *         The value of this parameter depend on device used within the same series 
-  * @retval HAL status 
+  *         The value of this parameter depend on device used within the same series
+  * @retval HAL status
   */
 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
 {
@@ -531,42 +531,42 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
 #if defined(OB_WRP3_WRP3)
   uint16_t WRP3_Data = 0xFFFFU;
 #endif /* OB_WRP3_WRP3 */
-  
+
   /* Check the parameters */
   assert_param(IS_OB_WRP(WriteProtectPage));
-    
+
   /* Get current write protected pages and the new pages to be protected ******/
   WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
-  
+
 #if defined(OB_WRP_PAGES0TO15MASK)
   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
 #endif /* OB_WRP_PAGES0TO31MASK */
-  
+
 #if defined(OB_WRP_PAGES16TO31MASK)
   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
 #endif /* OB_WRP_PAGES32TO63MASK */
- 
+
 #if defined(OB_WRP_PAGES32TO47MASK)
   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
 #endif /* OB_WRP_PAGES32TO47MASK */
 
 #if defined(OB_WRP_PAGES48TO127MASK)
-  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); 
+  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
 #elif defined(OB_WRP_PAGES48TO255MASK)
-  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); 
+  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
 #endif /* OB_WRP_PAGES48TO63MASK */
-  
+
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
   if(status == HAL_OK)
-  { 
+  {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* To be able to write again option byte, need to perform a option byte erase */
     status = HAL_FLASHEx_OBErase();
-    if (status == HAL_OK)  
+    if (status == HAL_OK)
     {
       /* Enable write protection */
       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
@@ -575,7 +575,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
       if(WRP0_Data != 0xFFU)
       {
         OB->WRP0 &= WRP0_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -585,7 +585,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
       if((status == HAL_OK) && (WRP1_Data != 0xFFU))
       {
         OB->WRP1 &= WRP1_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -595,7 +595,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
       if((status == HAL_OK) && (WRP2_Data != 0xFFU))
       {
         OB->WRP2 &= WRP2_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -605,7 +605,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
       if((status == HAL_OK) && (WRP3_Data != 0xFFU))
       {
         OB->WRP3 &= WRP3_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -615,20 +615,20 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
     }
   }
-  
+
   return status;
 }
 
 /**
   * @brief  Disable the write protection of the desired pages
-  * @note   An option byte erase is done automatically in this function. 
-  * @note   When the memory read protection level is selected (RDP level = 1), 
-  *         it is not possible to program or erase the flash page i if   
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 
-  * 
+  * @note   An option byte erase is done automatically in this function.
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash page i if
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  *
   * @param  WriteProtectPage specifies the page(s) to be write unprotected.
-  *         The value of this parameter depend on device used within the same series 
-  * @retval HAL status 
+  *         The value of this parameter depend on device used within the same series
+  * @retval HAL status
   */
 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 {
@@ -643,7 +643,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 #if defined(OB_WRP3_WRP3)
   uint16_t WRP3_Data = 0xFFFFU;
 #endif /* OB_WRP3_WRP3 */
-  
+
   /* Check the parameters */
   assert_param(IS_OB_WRP(WriteProtectPage));
 
@@ -653,33 +653,33 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 #if defined(OB_WRP_PAGES0TO15MASK)
   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
 #endif /* OB_WRP_PAGES0TO31MASK */
-  
+
 #if defined(OB_WRP_PAGES16TO31MASK)
   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
 #endif /* OB_WRP_PAGES32TO63MASK */
- 
+
 #if defined(OB_WRP_PAGES32TO47MASK)
   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
 #endif /* OB_WRP_PAGES32TO47MASK */
 
 #if defined(OB_WRP_PAGES48TO127MASK)
-  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); 
+  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
 #elif defined(OB_WRP_PAGES48TO255MASK)
-  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); 
+  WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
 #endif /* OB_WRP_PAGES48TO63MASK */
 
-    
+
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
 
   if(status == HAL_OK)
-  { 
+  {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* To be able to write again option byte, need to perform a option byte erase */
     status = HAL_FLASHEx_OBErase();
-    if (status == HAL_OK)  
+    if (status == HAL_OK)
     {
       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
 
@@ -687,7 +687,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
       if(WRP0_Data != 0xFFU)
       {
         OB->WRP0 |= WRP0_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -697,7 +697,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
       if((status == HAL_OK) && (WRP1_Data != 0xFFU))
       {
         OB->WRP1 |= WRP1_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -707,7 +707,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
       if((status == HAL_OK) && (WRP2_Data != 0xFFU))
       {
         OB->WRP2 |= WRP2_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -717,7 +717,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
       if((status == HAL_OK) && (WRP3_Data != 0xFFU))
       {
         OB->WRP3 |= WRP3_Data;
-        
+
         /* Wait for last operation to be completed */
         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
       }
@@ -743,18 +743,18 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Check the parameters */
   assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
-  
+
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
+
   if(status == HAL_OK)
-  { 
+  {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-    
+
     /* If the previous operation is completed, proceed to erase the option bytes */
     SET_BIT(FLASH->CR, FLASH_CR_OPTER);
     SET_BIT(FLASH->CR, FLASH_CR_STRT);
@@ -769,26 +769,26 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
     {
       /* Enable the Option Bytes Programming operation */
       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
-      
+
       WRITE_REG(OB->RDP, ReadProtectLevel);
-      
+
       /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 
-      
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
       /* if the program operation is completed, disable the OPTPG Bit */
       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
     }
   }
-  
+
   return status;
 }
 
 /**
-  * @brief  Program the FLASH User Option Byte.    
+  * @brief  Program the FLASH User Option Byte.
   * @note   Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
   * @param  UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
-  *         VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). 
-  *         And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . 
+  *         VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+  *         And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
   * @retval HAL status
   */
 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
@@ -808,15 +808,15 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
 
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
+
   if(status == HAL_OK)
-  {     
+  {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* Enable the Option Bytes Programming operation */
-    SET_BIT(FLASH->CR, FLASH_CR_OPTPG); 
- 
+    SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
+
 #if   defined(FLASH_OBR_SDADC12_VDD_MONITOR)
     OB->USER = (UserConfig | 0x08U);
 #else
@@ -829,44 +829,44 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
     /* if the program operation is completed, disable the OPTPG Bit */
     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
   }
-  
-  return status; 
+
+  return status;
 }
 
 /**
   * @brief  Programs a half word at a specified Option Byte Data address.
   * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
-  *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes 
+  *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
   *         (system reset will occur)
   *         Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
   * @param  Address specifies the address to be programmed.
-  *         This parameter can be 0x1FFFF804 or 0x1FFFF806. 
+  *         This parameter can be 0x1FFFF804 or 0x1FFFF806.
   * @param  Data specifies the data to be programmed.
   * @retval HAL status
   */
 static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
-  
+
   /* Check the parameters */
   assert_param(IS_OB_DATA_ADDRESS(Address));
-  
+
   /* Wait for last operation to be completed */
   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
+
   if(status == HAL_OK)
   {
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* Enables the Option Bytes Programming operation */
-    SET_BIT(FLASH->CR, FLASH_CR_OPTPG); 
+    SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
     *(__IO uint16_t*)Address = Data;
-    
+
     /* Wait for last operation to be completed */
     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-    
+
     /* If the program operation is completed, disable the OPTPG Bit */
     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
   }
@@ -895,7 +895,7 @@ static uint32_t FLASH_OB_GetWRP(void)
 static uint32_t FLASH_OB_GetRDP(void)
 {
   uint32_t tmp_reg = 0U;
-  
+
   /* Read RDP level bits */
 #if defined(FLASH_OBR_RDPRT)
   tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
@@ -915,7 +915,7 @@ static uint32_t FLASH_OB_GetRDP(void)
   {
     return OB_RDP_LEVEL_0;
   }
-  else 
+  else
   {
     return OB_RDP_LEVEL_1;
   }
@@ -924,8 +924,8 @@ static uint32_t FLASH_OB_GetRDP(void)
 /**
   * @brief  Return the FLASH User Option Byte value.
   * @retval  The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4),
-  *         VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). 
-  *         And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . 
+  *         VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6).
+  *         And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 .
   */
 static uint8_t FLASH_OB_GetUser(void)
 {
@@ -952,8 +952,8 @@ static uint8_t FLASH_OB_GetUser(void)
 /**
   * @brief  Erase the specified FLASH memory page
   * @param  PageAddress FLASH page to erase
-  *         The value of this parameter depend on device used within the same series      
-  * 
+  *         The value of this parameter depend on device used within the same series
+  *
   * @retval None
   */
 void FLASH_PageErase(uint32_t PageAddress)

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c

@@ -74,7 +74,7 @@
         HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
 
    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-  
+
     (#) During and just after reset, the alternate functions are not
         active and the GPIO pins are configured in input floating mode (except JTAG
         pins).
@@ -140,7 +140,7 @@
 /**
   * @}
   */
-  
+
 /* Private macros ------------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup GPIO_Private_Macros GPIO Private Macros
@@ -157,7 +157,7 @@
   * @{
   */
 
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
  *  @brief    Initialization and Configuration functions
  *
 @verbatim
@@ -329,7 +329,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
         /* Clear EXTI line configuration */
         EXTI->IMR &= ~((uint32_t)iocurrent);
         EXTI->EMR &= ~((uint32_t)iocurrent);
-        
+
         /* Clear Rising Falling edge configuration */
         EXTI->RTSR &= ~((uint32_t)iocurrent);
         EXTI->FTSR &= ~((uint32_t)iocurrent);
@@ -364,7 +364,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
   * @}
   */
 
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
  *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
  *
 @verbatim

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c

@@ -3,9 +3,9 @@
   * @file    stm32f3xx_hal_msp_template.c
   * @author  MCD Application Team
   * @brief   HAL MSP module.
-  *          This file template is located in the HAL folder and should be copied 
+  *          This file template is located in the HAL folder and should be copied
   *          to the user folder.
-  *         
+  *
   @verbatim
  ===============================================================================
                      ##### How to use this driver #####
@@ -25,7 +25,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal.h"
@@ -56,7 +56,7 @@
   */
 void HAL_MspInit(void)
 {
-   
+
 }
 
 /**
@@ -65,7 +65,7 @@ void HAL_MspInit(void)
   */
 void HAL_MspDeInit(void)
 {
-  
+
 }
 
 /**
@@ -74,7 +74,7 @@ void HAL_MspDeInit(void)
   */
 void HAL_PPP_MspInit(void)
 {
-   
+
 }
 
 /**
@@ -83,7 +83,7 @@ void HAL_PPP_MspInit(void)
   */
 void HAL_PPP_MspDeInit(void)
 {
-  
+
 }
 
 /**

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c

@@ -358,7 +358,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
                                         hopamp->Init.PgaGain | \
                                         hopamp->Init.UserTrimming | \
                                         (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
-                                        (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));  
+                                        (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
 
     }
     else /* OPAMP_STANDALONE_MODE */
@@ -374,7 +374,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
                                         hopamp->Init.PgaGain | \
                                         hopamp->Init.UserTrimming | \
                                         (hopamp->Init.TrimmingValueP << OPAMP_INPUT_NONINVERTING) | \
-                                        (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));     
+                                        (hopamp->Init.TrimmingValueN << OPAMP_INPUT_INVERTING));
     }
 
     /* Update the OPAMP state*/

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp_ex.c

@@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA
   return status;
 }
 #endif /* STM32F302xE || */
-	   /* STM32F302xC    */
+       /* STM32F302xC    */
 
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
     defined(STM32F303xC) || defined(STM32F358xx)

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c

@@ -48,7 +48,7 @@
   * @{
   */
 
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
   *  @brief    Initialization and de-initialization functions
   *
 @verbatim
@@ -87,7 +87,7 @@ void HAL_PWR_DeInit(void)
   */
 void HAL_PWR_EnableBkUpAccess(void)
 {
-  SET_BIT(PWR->CR, PWR_CR_DBP);  
+  SET_BIT(PWR->CR, PWR_CR_DBP);
 }
 
 /**
@@ -99,14 +99,14 @@ void HAL_PWR_EnableBkUpAccess(void)
   */
 void HAL_PWR_DisableBkUpAccess(void)
 {
-  CLEAR_BIT(PWR->CR, PWR_CR_DBP);  
+  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
 }
 
 /**
   * @}
   */
 
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
   *  @brief Low Power modes configuration functions
   *
 @verbatim
@@ -114,7 +114,7 @@ void HAL_PWR_DisableBkUpAccess(void)
  ===============================================================================
                  ##### Peripheral Control functions #####
  ===============================================================================
-    
+
     *** WakeUp pin configuration ***
     ================================
     [..]
@@ -159,7 +159,7 @@ void HAL_PWR_DisableBkUpAccess(void)
               functions with
           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-     
+
       (+) Exit:
         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
               controller (NVIC) can wake up the device from Sleep mode.
@@ -181,9 +181,9 @@ void HAL_PWR_DisableBkUpAccess(void)
           (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
       (+) Exit:
           (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-          (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, 
-               when programmed in wakeup mode (the peripheral must be 
-               programmed in wakeup mode and the corresponding interrupt vector 
+          (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
+               when programmed in wakeup mode (the peripheral must be
+               programmed in wakeup mode and the corresponding interrupt vector
                must be enabled in the NVIC).
 
    *** Standby mode ***
@@ -207,7 +207,7 @@ void HAL_PWR_DisableBkUpAccess(void)
    =============================================
     [..]
       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
-      Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+      Wakeup event, a tamper event, a time-stamp event, or a comparator event,
       without depending on an external interrupt (Auto-wakeup mode).
 
     (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
@@ -225,10 +225,10 @@ void HAL_PWR_DisableBkUpAccess(void)
     (+) Comparator auto-wakeup (AWU) from the Stop mode
 
       (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
-           (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U) 
-                 to be sensitive to to the selected edges (falling, rising or falling 
+           (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
+                 to be sensitive to to the selected edges (falling, rising or falling
                  and rising) (Interrupt or Event modes) using the EXTI_Init() function.
-           (+++) Configure the comparator to generate the event.      
+           (+++) Configure the comparator to generate the event.
 @endverbatim
   * @{
   */
@@ -270,10 +270,10 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
   *          This parameter can be one of the following values:
   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @note This parameter has no effect in F3 family and is just maintained to 
+  * @note This parameter has no effect in F3 family and is just maintained to
   *       offer full portability of other STM32 families softwares.
   * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
-  *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
+  *           When WFI entry is used, tick interrupt have to be disabled if not desired as
   *           the interrupt wake up source.
   *           This parameter can be one of the following values:
   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
@@ -332,7 +332,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
 
   /* Select the regulator state in STOP mode ---------------------------------*/
   tmpreg = PWR->CR;
-  
+
   /* Clear PDDS and LPDS bits */
   tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
 
@@ -366,9 +366,9 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
 /**
   * @brief Enters STANDBY mode.
   * @note  In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available), 
+  *          - Reset pad (still available),
   *          - RTC alternate function pins if configured for tamper, time-stamp, RTC
-  *            Alarm out, or RTC clock calibration out, 
+  *            Alarm out, or RTC clock calibration out,
   *          - WKUP pins if enabled.
   * @retval None
   */
@@ -389,11 +389,11 @@ void HAL_PWR_EnterSTANDBYMode(void)
 }
 
 /**
-  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
   *       re-enters SLEEP mode when an interruption handling is over.
   *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.         
+  *       interruptions handling.
   * @retval None
   */
 void HAL_PWR_EnableSleepOnExit(void)
@@ -404,9 +404,9 @@ void HAL_PWR_EnableSleepOnExit(void)
 
 
 /**
-  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
-  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.          
+  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
+  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
+  *       re-enters SLEEP mode when an interruption handling is over.
   * @retval None
   */
 void HAL_PWR_DisableSleepOnExit(void)
@@ -418,8 +418,8 @@ void HAL_PWR_DisableSleepOnExit(void)
 
 
 /**
-  * @brief Enables CORTEX M4 SEVONPEND bit. 
-  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
+  * @brief Enables CORTEX M4 SEVONPEND bit.
+  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
   *       WFE to wake up when an interrupt moves from inactive to pended.
   * @retval None
   */
@@ -431,9 +431,9 @@ void HAL_PWR_EnableSEVOnPend(void)
 
 
 /**
-  * @brief Disables CORTEX M4 SEVONPEND bit. 
-  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.         
+  * @brief Disables CORTEX M4 SEVONPEND bit.
+  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
+  *       WFE to wake up when an interrupt moves from inactive to pended.
   * @retval None
   */
 void HAL_PWR_DisableSEVOnPend(void)

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c

@@ -7,7 +7,7 @@
   *          functionalities of the Power Controller (PWR) peripheral:
   *           + Extended Initialization and de-initialization functions
   *           + Extended Peripheral Control functions
-  *         
+  *
   ******************************************************************************
   * @attention
   *
@@ -48,7 +48,7 @@
 /**
   * @}
   */
- 
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -104,7 +104,7 @@
     *** SDADC power configuration ***
     ================================
     [..]
-      (+) On STM32F373xC/STM32F378xx devices, there are up to 
+      (+) On STM32F373xC/STM32F378xx devices, there are up to
           3 SDADC instances that can be enabled/disabled.
 
 @endverbatim
@@ -134,7 +134,7 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
 
   /* Set PLS[7:5] bits according to PVDLevel value */
   MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-  
+
   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
   __HAL_PWR_PVD_EXTI_DISABLE_IT();
@@ -145,19 +145,19 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
   {
     __HAL_PWR_PVD_EXTI_ENABLE_IT();
   }
-  
+
   /* Configure event mode */
   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
   {
     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
   }
-  
+
   /* Configure the edge */
   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
   {
     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
   }
-  
+
   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
   {
     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
@@ -170,7 +170,7 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
   */
 void HAL_PWR_EnablePVD(void)
 {
-  SET_BIT(PWR->CR, PWR_CR_PVDE);  
+  SET_BIT(PWR->CR, PWR_CR_PVDE);
 }
 
 /**
@@ -179,7 +179,7 @@ void HAL_PWR_EnablePVD(void)
   */
 void HAL_PWR_DisablePVD(void)
 {
-  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);  
+  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
 }
 
 /**
@@ -232,7 +232,7 @@ void HAL_PWREx_EnableSDADC(uint32_t Analogx)
 
   /* Enable PWR clock interface for SDADC use */
   __HAL_RCC_PWR_CLK_ENABLE();
-    
+
   PWR->CR |= Analogx;
 }
 
@@ -246,7 +246,7 @@ void HAL_PWREx_DisableSDADC(uint32_t Analogx)
 {
   /* Check the parameters */
   assert_param(IS_PWR_SDADC_ANALOG(Analogx));
-  
+
   PWR->CR &= ~Analogx;
 }
 

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c

@@ -3,18 +3,18 @@
   * @file    stm32f3xx_hal_rcc.c
   * @author  MCD Application Team
   * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
   *           + Initialization and de-initialization functions
   *           + Peripheral Control functions
-  *       
-  @verbatim                
+  *
+  @verbatim
   ==============================================================================
                       ##### RCC specific features #####
   ==============================================================================
-    [..]  
+    [..]
       After reset the device is running from Internal High Speed oscillator
-      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, 
+      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
       and all peripherals are off except internal SRAM, Flash and JTAG.
       (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
           all peripherals mapped on these buses are running at HSI speed.
@@ -24,7 +24,7 @@
     [..] Once the device started from reset, the user application has to:
       (+) Configure the clock source to be used to drive the System clock
           (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings  
+      (+) Configure the System clock frequency and Flash settings
       (+) Configure the AHB and APB buses prescalers
       (+) Enable the clock for the peripheral(s) to be used
       (+) Configure the clock source(s) for peripherals whose clocks are not
@@ -32,14 +32,14 @@
 
                       ##### RCC Limitations #####
   ==============================================================================
-    [..]  
-      A delay between an RCC peripheral clock enable and the effective peripheral 
-      enabling should be taken into account in order to manage the peripheral read/write 
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
       from/to registers.
       (+) This delay depends on the peripheral mapping.
         (++) AHB & APB peripherals, 1 dummy read is necessary
 
-    [..]  
+    [..]
       Workarounds:
       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
@@ -117,10 +117,10 @@ const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
   * @{
   */
 
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
   *
-  @verbatim    
+  @verbatim
   ===============================================================================
            ##### Initialization and de-initialization functions #####
   ===============================================================================
@@ -140,7 +140,7 @@ const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
       (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
           through the PLL as System clock source. Can be used also as RTC clock source.
 
-      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
+      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
 
       (#) PLL (clocked by HSI or HSE), featuring different output clocks:
         (++) The first output is used to generate the high speed system clock (up to 72 MHz)
@@ -149,10 +149,10 @@ const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
         (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
 
       (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-          and if a HSE clock failure occurs(HSE used directly or through PLL as System 
+          and if a HSE clock failure occurs(HSE used directly or through PLL as System
           clock source), the System clocks automatically switched to HSI and an interrupt
-          is generated if enabled. The interrupt is linked to the Cortex-M4 NMI 
-          (Non-Maskable Interrupt) exception vector.   
+          is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+          (Non-Maskable Interrupt) exception vector.
 
       (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
           clock (divided by 2) output on pin (such as PA8 pin).
@@ -186,7 +186,7 @@ const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
   @endverbatim
   * @{
   */
-  
+
 /*
   Additional consideration on the SYSCLK based on Latency settings:
         +-----------------------------------------------+
@@ -330,14 +330,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   /* Check the parameters */
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
 
-  /*------------------------------- HSE Configuration ------------------------*/ 
+  /*------------------------------- HSE Configuration ------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
 
     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
     {
       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
@@ -349,7 +349,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     {
       /* Set the new HSE configuration ---------------------------------------*/
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-      
+
 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
       /* Configure the HSE predivision factor --------------------------------*/
       __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
@@ -360,7 +360,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
+
         /* Wait till HSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
         {
@@ -374,7 +374,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
+
         /* Wait till HSE is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
         {
@@ -386,15 +386,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       }
     }
   }
-  /*----------------------------- HSI Configuration --------------------------*/ 
+  /*----------------------------- HSI Configuration --------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-    
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
     {
       /* When HSI is used as system clock it will not disabled */
@@ -416,10 +416,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       {
        /* Enable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_ENABLE();
-        
+
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
+
         /* Wait till HSI is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
         {
@@ -428,7 +428,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
             return HAL_TIMEOUT;
           }
         }
-                
+
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
       }
@@ -436,10 +436,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       {
         /* Disable the Internal High Speed oscillator (HSI). */
         __HAL_RCC_HSI_DISABLE();
-        
+
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
+
         /* Wait till HSI is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
         {
@@ -451,22 +451,22 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       }
     }
   }
-  /*------------------------------ LSI Configuration -------------------------*/ 
+  /*------------------------------ LSI Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-    
+
     /* Check the LSI State */
     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
-      
+
       /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */  
+
+      /* Wait till LSI is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
@@ -479,11 +479,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     {
       /* Disable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_DISABLE();
-      
+
       /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is disabled */  
+
+      /* Wait till LSI is disabled */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
       {
         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
@@ -493,11 +493,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       }
     }
   }
-  /*------------------------------ LSE Configuration -------------------------*/ 
+  /*------------------------------ LSE Configuration -------------------------*/
   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
   {
     FlagStatus       pwrclkchanged = RESET;
-    
+
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
 
@@ -508,12 +508,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       __HAL_RCC_PWR_CLK_ENABLE();
       pwrclkchanged = SET;
     }
-    
+
     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
     {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
-      
+
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
 
@@ -533,8 +533,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
+
+      /* Wait till LSE is ready */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -547,8 +547,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     {
       /* Get Start Tick */
       tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is disabled */  
+
+      /* Wait till LSE is disabled */
       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
       {
         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -572,7 +572,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     /* Check if the PLL is used as system clock or not */
     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
-    { 
+    {
       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
       {
         /* Check the parameters */
@@ -581,13 +581,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 #if   defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
         assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
 #endif
-  
+
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
-        
+
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
+
         /* Wait till PLL is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
         {
@@ -609,10 +609,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
-        
+
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
+
         /* Wait till PLL is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
         {
@@ -626,11 +626,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
       {
         /* Disable the main PLL. */
         __HAL_RCC_PLL_DISABLE();
- 
+
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is disabled */  
+
+        /* Wait till PLL is disabled */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
         {
           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -653,11 +653,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
         pll_config = RCC->CFGR;
 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
         pll_config2 = RCC->CFGR2;
-        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC)   != RCC_OscInitStruct->PLL.PLLSource) ||      
-           (READ_BIT(pll_config, RCC_CFGR_PLLMUL)   != RCC_OscInitStruct->PLL.PLLMUL)    ||      
-           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV)  != RCC_OscInitStruct->PLL.PREDIV))     
+        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC)   != RCC_OscInitStruct->PLL.PLLSource) ||
+           (READ_BIT(pll_config, RCC_CFGR_PLLMUL)   != RCC_OscInitStruct->PLL.PLLMUL)    ||
+           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV)  != RCC_OscInitStruct->PLL.PREDIV))
 #else
-        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC)   != RCC_OscInitStruct->PLL.PLLSource) ||      
+        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC)   != RCC_OscInitStruct->PLL.PLLSource) ||
            (READ_BIT(pll_config, RCC_CFGR_PLLMUL)   != RCC_OscInitStruct->PLL.PLLMUL))
 #endif
         {
@@ -671,24 +671,24 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 }
 
 /**
-  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified 
+  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
   *         parameters in the RCC_ClkInitStruct.
   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
   *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency FLASH Latency                   
+  * @param  FLatency FLASH Latency
   *          The value of this parameter depend on device used within the same series
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
   *
   * @note   The HSI is used (enabled by hardware) as system clock source after
   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
   *         of failure of the HSE used directly or indirectly as system clock
   *         (if the Clock Security System CSS is enabled).
-  *           
+  *
   * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after start-up delay or PLL locked). 
+  *         clock source is ready (clock stable after start-up delay or PLL locked).
   *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready. 
+  *         occur when the clock source will be ready.
   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
   *         currently used as system clock source.
   * @retval HAL status
@@ -707,16 +707,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
   assert_param(IS_FLASH_LATENCY(FLatency));
 
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
-  must be correctly programmed according to the frequency of the CPU clock 
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+  must be correctly programmed according to the frequency of the CPU clock
     (HCLK) of the device. */
 
   /* Increasing the number of wait states because of higher CPU frequency */
   if(FLatency > __HAL_FLASH_GET_LATENCY())
-  {    
+  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
-    
+
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
@@ -732,15 +732,15 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
   }
 
-  /*------------------------- SYSCLK Configuration ---------------------------*/ 
+  /*------------------------- SYSCLK Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {    
+  {
     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-    
+
     /* HSE is selected as System Clock Source */
     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
     {
-      /* Check the HSE ready flag */  
+      /* Check the HSE ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
       {
         return HAL_ERROR;
@@ -749,7 +749,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
     /* PLL is selected as System Clock Source */
     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
     {
-      /* Check the PLL ready flag */  
+      /* Check the PLL ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
       {
         return HAL_ERROR;
@@ -758,7 +758,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
     /* HSI is selected as System Clock Source */
     else
     {
-      /* Check the HSI ready flag */  
+      /* Check the HSI ready flag */
       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
       {
         return HAL_ERROR;
@@ -769,7 +769,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 
     /* Get Start Tick */
     tickstart = HAL_GetTick();
-    
+
     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
     {
       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
@@ -780,38 +780,38 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   }
   /* Decreasing the number of wait states because of lower CPU frequency */
   if(FLatency < __HAL_FLASH_GET_LATENCY())
-  {    
+  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
-    
+
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
     if(__HAL_FLASH_GET_LATENCY() != FLatency)
     {
       return HAL_ERROR;
     }
-  }    
+  }
 
-  /*-------------------------- PCLK1 Configuration ---------------------------*/ 
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
   }
-  
-  /*-------------------------- PCLK2 Configuration ---------------------------*/ 
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
   }
- 
+
   /* Update the SystemCoreClock global variable */
   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
 
   /* Configure the source of time base considering new system clocks settings*/
   HAL_InitTick (uwTickPrio);
-  
+
   return HAL_OK;
 }
 
@@ -822,12 +822,12 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
   *  @brief   RCC clocks control functions
   *
-  @verbatim   
+  @verbatim
   ===============================================================================
                   ##### Peripheral Control functions #####
-  ===============================================================================  
+  ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
+    This subsection provides a set of functions allowing to control the RCC Clocks
     frequencies.
 
   @endverbatim
@@ -893,7 +893,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
   assert_param(IS_RCC_MCO(RCC_MCOx));
   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-  
+
   /* Configure the MCO1 pin in alternate function mode */
   gpio.Mode      = GPIO_MODE_AF_PP;
   gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
@@ -903,9 +903,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
 
   /* MCO1 Clock Enable */
   MCO1_CLK_ENABLE();
-  
+
   HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-  
+
   /* Configure the MCO clock source */
   __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
 }
@@ -915,8 +915,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
   *         is automatically disabled and an interrupt is generated to inform the
   *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
-  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
   * @retval None
   */
 void HAL_RCC_EnableCSS(void)
@@ -934,9 +934,9 @@ void HAL_RCC_DisableCSS(void)
 }
 
 /**
-  * @brief  Returns the SYSCLK frequency     
-  * @note   The system frequency computed by this function is not the real 
-  *         frequency in the chip. It is calculated based on the predefined 
+  * @brief  Returns the SYSCLK frequency
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
   *         constant and the selected clock source:
   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
   * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
@@ -950,25 +950,25 @@ void HAL_RCC_DisableCSS(void)
   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
   *                frequency of the crystal used. Otherwise, this function may
   *                have wrong result.
-  *                  
+  *
   * @note   The result of this function could be not correct when using fractional
   *         value for HSE crystal.
-  *           
-  * @note   This function can be used by the user application to compute the 
+  *
+  * @note   This function can be used by the user application to compute the
   *         baud-rate for the communication peripherals or configure other parameters.
-  *           
+  *
   * @note   Each time SYSCLK changes, this function must be called to update the
   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *         
+  *
   * @retval SYSCLK frequency
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
   uint32_t sysclockfreq = 0U;
-  
+
   tmpreg = RCC->CFGR;
-  
+
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (tmpreg & RCC_CFGR_SWS)
   {
@@ -1018,11 +1018,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
 }
 
 /**
-  * @brief  Returns the HCLK frequency     
+  * @brief  Returns the HCLK frequency
   * @note   Each time HCLK changes, this function must be called to update the
   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  * 
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
   *         and updated within this function
   * @retval HCLK frequency
   */
@@ -1032,7 +1032,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
 }
 
 /**
-  * @brief  Returns the PCLK1 frequency     
+  * @brief  Returns the PCLK1 frequency
   * @note   Each time PCLK1 changes, this function must be called to update the
   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency
@@ -1041,10 +1041,10 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
 {
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
-}    
+}
 
 /**
-  * @brief  Returns the PCLK2 frequency     
+  * @brief  Returns the PCLK2 frequency
   * @note   Each time PCLK2 changes, this function must be called to update the
   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK2 frequency
@@ -1053,12 +1053,12 @@ uint32_t HAL_RCC_GetPCLK2Freq(void)
 {
   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
-} 
+}
 
 /**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
+  * @brief  Configures the RCC_OscInitStruct according to the internal
   * RCC configuration registers.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that 
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
   * will be configured.
   * @retval None
   */
@@ -1098,9 +1098,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
   }
-  
+
   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-  
+
   /* Get the LSE configuration -----------------------------------------------*/
   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
   {
@@ -1114,7 +1114,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
   }
-  
+
   /* Get the LSI configuration -----------------------------------------------*/
   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
   {
@@ -1124,7 +1124,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   {
     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
   }
-  
+
 
   /* Get the PLL configuration -----------------------------------------------*/
   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
@@ -1143,9 +1143,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 }
 
 /**
-  * @brief  Get the RCC_ClkInitStruct according to the internal 
+  * @brief  Get the RCC_ClkInitStruct according to the internal
   * RCC configuration registers.
-  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that 
+  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
   * contains the current clock configuration.
   * @param  pFLatency Pointer on the Flash Latency.
   * @retval None
@@ -1158,21 +1158,21 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pF
 
   /* Set all possible values for the Clock type parameter --------------------*/
   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-  
-  /* Get the SYSCLK configuration --------------------------------------------*/ 
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-  
-  /* Get the HCLK configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 
-  
-  /* Get the APB1 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   
-  
-  /* Get the APB2 configuration ----------------------------------------------*/ 
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-  
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/   
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 }
 
 /**
@@ -1187,7 +1187,7 @@ void HAL_RCC_NMI_IRQHandler(void)
   {
     /* RCC Clock Security System interrupt user callback */
     HAL_RCC_CSSCallback();
-    
+
     /* Clear RCC CSS pending bit */
     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
   }
@@ -1201,7 +1201,7 @@ __weak void HAL_RCC_CSSCallback(void)
 {
   /* NOTE : This function Should not be modified, when the callback is needed,
     the HAL_RCC_CSSCallback could be implemented in the user file
-    */ 
+    */
 }
 
 /**

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c

@@ -3,10 +3,10 @@
   * @file    stm32f3xx_hal_rcc_ex.c
   * @author  MCD Application Team
   * @brief   Extended RCC HAL module driver.
-  *          This file provides firmware functions to manage the following 
+  *          This file provides firmware functions to manage the following
   *          functionalities RCC extension peripheral:
   *           + Extended Peripheral Control functions
-  *  
+  *
   ******************************************************************************
   * @attention
   *
@@ -19,7 +19,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal.h"
@@ -66,22 +66,22 @@ static uint32_t RCC_GetPLLCLKFreq(void);
   * @{
   */
 
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
   * @brief    Extended Peripheral Control functions
   *
-@verbatim   
+@verbatim
  ===============================================================================
                 ##### Extended Peripheral Control functions  #####
- ===============================================================================  
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
+    This subsection provides a set of functions allowing to control the RCC Clocks
     frequencies.
-    [..] 
+    [..]
     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in  
-        order to modify the RTC Clock source, as consequence RTC registers (including 
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
         the backup registers) are set to their reset values.
-      
+
 @endverbatim
   * @{
   */
@@ -93,12 +93,12 @@ static uint32_t RCC_GetPLLCLKFreq(void);
   *         contains the configuration information for the Extended Peripherals clocks
   *         (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
   *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select 
-  *         the RTC clock source; in this case the Backup domain will be reset in  
-  *         order to modify the RTC Clock source, as consequence RTC registers (including 
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
   *         the backup registers) and RCC_BDCR register are set to their reset values.
   *
-  * @note   When the TIMx clock source is APB clock, so the TIMx clock is APB clock or 
+  * @note   When the TIMx clock source is APB clock, so the TIMx clock is APB clock or
   *         APB clock x 2 depending on the APB prescaler.
   *         When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2.
   *
@@ -109,10 +109,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   uint32_t tickstart = 0U;
   uint32_t temp_reg = 0U;
   FlagStatus       pwrclkchanged = RESET;
-    
+
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-  
+
   /*---------------------------- RTC configuration -------------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
   {
@@ -120,7 +120,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
 
 
-    /* As soon as function is called to change RTC clock source, activation of the 
+    /* As soon as function is called to change RTC clock source, activation of the
        power domain is done. */
     /* Requires to enable write access to Backup Domain of necessary */
     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
@@ -128,15 +128,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_PWR_CLK_ENABLE();
       pwrclkchanged = SET;
     }
-    
+
     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
     {
       /* Enable write access to Backup domain */
       SET_BIT(PWR->CR, PWR_CR_DBP);
-      
+
       /* Wait for Backup domain Write protection disable */
       tickstart = HAL_GetTick();
-      
+
       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
       {
           if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
@@ -145,8 +145,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
         }
       }
     }
-    
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
+
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
     temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
     if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
     {
@@ -157,24 +157,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       __HAL_RCC_BACKUPRESET_RELEASE();
       /* Restore the Content of BDCR register */
       RCC->BDCR = temp_reg;
-    
+
       /* Wait for LSERDY if LSE was enabled */
       if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
       {
         /* Get Start Tick */
         tickstart = HAL_GetTick();
-        
-        /* Wait till LSE is ready */  
+
+        /* Wait till LSE is ready */
         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
         {
             if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
-          }      
-        }  
+          }
+        }
       }
     }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 
     /* Require to disable power clock if necessary */
     if(pwrclkchanged == SET)
@@ -188,41 +188,41 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
-    
+
     /* Configure the USART1 clock source */
     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
   }
 
 #if defined(RCC_CFGR3_USART2SW)
-  /*----------------------------- USART2 Configuration --------------------------*/ 
+  /*----------------------------- USART2 Configuration --------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
-    
+
     /* Configure the USART2 clock source */
     __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
   }
 #endif /* RCC_CFGR3_USART2SW */
 
 #if defined(RCC_CFGR3_USART3SW)
-  /*------------------------------ USART3 Configuration ------------------------*/ 
+  /*------------------------------ USART3 Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
-    
+
     /* Configure the USART3 clock source */
     __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
   }
 #endif /* RCC_CFGR3_USART3SW */
 
-  /*------------------------------ I2C1 Configuration ------------------------*/ 
+  /*------------------------------ I2C1 Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
-    
+
     /* Configure the I2C1 clock source */
     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
   }
@@ -231,12 +231,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
  || defined(STM32F302xC) || defined(STM32F303xC)\
  || defined(STM32F302x8)                        \
  || defined(STM32F373xC)
-  /*------------------------------ USB Configuration ------------------------*/ 
+  /*------------------------------ USB Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
   {
     /* Check the parameters */
     assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
-    
+
     /* Configure the USB clock source */
     __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
   }
@@ -251,12 +251,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
  || defined(STM32F373xC) || defined(STM32F378xx)
 
-  /*------------------------------ I2C2 Configuration ------------------------*/ 
+  /*------------------------------ I2C2 Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
-    
+
     /* Configure the I2C2 clock source */
     __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
   }
@@ -265,41 +265,41 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
        /* STM32F373xC || STM32F378xx                   */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 
-  /*------------------------------ I2C3 Configuration ------------------------*/ 
+  /*------------------------------ I2C3 Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
-    
+
     /* Configure the I2C3 clock source */
     __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
   }
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
 
-  /*------------------------------ UART4 Configuration ------------------------*/ 
+  /*------------------------------ UART4 Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
   {
     /* Check the parameters */
     assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
-    
+
     /* Configure the UART4 clock source */
     __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
   }
 
-  /*------------------------------ UART5 Configuration ------------------------*/ 
+  /*------------------------------ UART5 Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
   {
     /* Check the parameters */
     assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
-    
+
     /* Configure the UART5 clock source */
     __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
   }
@@ -310,12 +310,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-  /*------------------------------ I2S Configuration ------------------------*/ 
+  /*------------------------------ I2S Configuration ------------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
-    
+
     /* Configure the I2S clock source */
     __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
   }
@@ -323,48 +323,48 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
-  
+
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-      
-  /*------------------------------ ADC1 clock Configuration ------------------*/ 
+
+  /*------------------------------ ADC1 clock Configuration ------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
-    
+
     /* Configure the ADC1 clock source */
     __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
   }
 
 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
  || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-      
-  /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ 
+
+  /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
   {
     /* Check the parameters */
     assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
-    
+
     /* Configure the ADC12 clock source */
     __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
   }
 
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
-       /* STM32F303x8 || STM32F334x8 || STM32F328xx    */    
-  
+       /* STM32F303x8 || STM32F334x8 || STM32F328xx    */
+
 #if defined(STM32F303xE) || defined(STM32F398xx)\
  || defined(STM32F303xC) || defined(STM32F358xx)
 
-  /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/ 
+  /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
   {
     /* Check the parameters */
     assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
-    
+
     /* Configure the ADC34 clock source */
     __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
   }
@@ -373,13 +373,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
        /* STM32F303xC || STM32F358xx    */
 
 #if defined(STM32F373xC) || defined(STM32F378xx)
-      
-  /*------------------------------ ADC1 clock Configuration ------------------*/ 
+
+  /*------------------------------ ADC1 clock Configuration ------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
-    
+
     /* Configure the ADC1 clock source */
     __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
   }
@@ -391,12 +391,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
  || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
  || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 
-  /*------------------------------ TIM1 clock Configuration ----------------*/ 
+  /*------------------------------ TIM1 clock Configuration ----------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
-    
+
     /* Configure the TIM1 clock source */
     __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
   }
@@ -405,16 +405,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
-  
+
 #if defined(STM32F303xE) || defined(STM32F398xx)\
  || defined(STM32F303xC) || defined(STM32F358xx)
 
-  /*------------------------------ TIM8 clock Configuration ----------------*/ 
+  /*------------------------------ TIM8 clock Configuration ----------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
-    
+
     /* Configure the TIM8 clock source */
     __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
   }
@@ -424,32 +424,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 
-  /*------------------------------ TIM15 clock Configuration ----------------*/ 
+  /*------------------------------ TIM15 clock Configuration ----------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
-    
+
     /* Configure the TIM15 clock source */
     __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
   }
 
-  /*------------------------------ TIM16 clock Configuration ----------------*/ 
+  /*------------------------------ TIM16 clock Configuration ----------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
-    
+
     /* Configure the TIM16 clock source */
     __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
   }
 
-  /*------------------------------ TIM17 clock Configuration ----------------*/ 
+  /*------------------------------ TIM17 clock Configuration ----------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
-    
+
     /* Configure the TIM17 clock source */
     __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
   }
@@ -458,12 +458,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(STM32F334x8)
 
-  /*------------------------------ HRTIM1 clock Configuration ----------------*/ 
+  /*------------------------------ HRTIM1 clock Configuration ----------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
-    
+
     /* Configure the HRTIM1 clock source */
     __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
   }
@@ -471,96 +471,96 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #endif /* STM32F334x8 */
 
 #if defined(STM32F373xC) || defined(STM32F378xx)
-  
-  /*------------------------------ SDADC clock Configuration -------------------*/ 
+
+  /*------------------------------ SDADC clock Configuration -------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
   {
     /* Check the parameters */
     assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
-    
+
     /* Configure the SDADC clock prescaler */
     __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
   }
 
-  /*------------------------------ CEC clock Configuration -------------------*/ 
+  /*------------------------------ CEC clock Configuration -------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
   {
     /* Check the parameters */
     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
   }
 
 #endif /* STM32F373xC || STM32F378xx */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-  
-  /*------------------------------ TIM2 clock Configuration -------------------*/ 
+
+  /*------------------------------ TIM2 clock Configuration -------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
   }
 
-  /*------------------------------ TIM3 clock Configuration -------------------*/ 
+  /*------------------------------ TIM3 clock Configuration -------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
   }
 
-  /*------------------------------ TIM15 clock Configuration ------------------*/ 
+  /*------------------------------ TIM15 clock Configuration ------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
   }
 
-  /*------------------------------ TIM16 clock Configuration ------------------*/ 
+  /*------------------------------ TIM16 clock Configuration ------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
   }
 
-  /*------------------------------ TIM17 clock Configuration ------------------*/ 
+  /*------------------------------ TIM17 clock Configuration ------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
   }
 
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */  
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 
 #if defined(STM32F303xE) || defined(STM32F398xx)
-  /*------------------------------ TIM20 clock Configuration ------------------*/ 
+  /*------------------------------ TIM20 clock Configuration ------------------*/
   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
-    
+
     /* Configure the CEC clock source */
     __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
   }
-#endif /* STM32F303xE || STM32F398xx */  
+#endif /* STM32F303xE || STM32F398xx */
+
 
-  
   return HAL_OK;
 }
 
@@ -583,7 +583,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \
                                         RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_RTC;
 #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
-  
+
   /* Get the RTC configuration --------------------------------------------*/
   PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
   /* Get the USART1 clock configuration --------------------------------------------*/
@@ -626,7 +626,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
        /* STM32F373xC || STM32F378xx                   */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
     || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 
@@ -636,7 +636,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
-  
+
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
     || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
 
@@ -660,10 +660,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
-  
+
 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
     || defined(STM32F373xC) || defined(STM32F378xx)
-      
+
   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
   /* Get the ADC1 clock configuration -----------------------------------------*/
   PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
@@ -706,7 +706,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
        /* STM32F302xC || STM32F303xC || STM32F358xx || */
        /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
        /* STM32F301x8 || STM32F302x8 || STM32F318xx    */
-  
+
 #if defined(STM32F303xE) || defined(STM32F398xx)\
     || defined(STM32F303xC) || defined(STM32F358xx)
 
@@ -772,7 +772,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
   PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
 
 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-  
+
 #if defined (STM32F303xE) || defined(STM32F398xx)
   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
   /* Get the TIM20 clock configuration -----------------------------------------*/
@@ -958,7 +958,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
 
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
-  
+
   switch (PeriphClk)
   {
   case RCC_PERIPHCLK_RTC:
@@ -1505,7 +1505,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
       break;
     }
 #endif /* RCC_CFGR3_CECSW */
-  default: 
+  default:
     {
       break;
     }
@@ -1570,11 +1570,11 @@ static uint32_t RCC_GetPLLCLKFreq(void)
   */
 
 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */
-  
+
 /**
   * @}
   */
-  
+
 #endif /* HAL_RCC_MODULE_ENABLED */
 
 /**

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c

@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_sdadc.c
   * @author  MCD Application Team
-  * @brief   This file provides firmware functions to manage the following 
+  * @brief   This file provides firmware functions to manage the following
   *          functionalities of the Sigma-Delta Analog to Digital Converter
   *          (SDADC) peripherals:
   *           + Initialization and Configuration
@@ -14,11 +14,11 @@
   @verbatim
   ==============================================================================
                     ##### SDADC specific features #####
-  ==============================================================================           
-  [..] 
+  ==============================================================================
+  [..]
   (#) 16-bit sigma delta architecture.
   (#) Self calibration.
-  (#) Interrupt generation at the end of calibration, regular/injected conversion  
+  (#) Interrupt generation at the end of calibration, regular/injected conversion
       and in case of overrun events.
   (#) Single and continuous conversion modes.
   (#) External trigger option with configurable polarity for injected conversion.
@@ -60,7 +60,7 @@
 
     *** Regular channel conversion ***
     ============================================
-    [..]    
+    [..]
       (#) Select trigger for regular conversion using
           HAL_SDADC_SelectRegularTrigger.
       (#) Select regular channel and enable/disable continuous mode using
@@ -69,19 +69,19 @@
           or HAL_SDADC_Start_DMA.
       (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
           regular conversion.
-      (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the 
+      (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
           end of regular conversion.
       (#) Get value of regular conversion using HAL_SDADC_GetValue.
-      (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and 
-          HAL_SDADC_ConvCpltCallback will be called respectively at the half 
+      (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+          HAL_SDADC_ConvCpltCallback will be called respectively at the half
           transfer and at the transfer complete.
       (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
           or HAL_SDADC_Stop_DMA.
 
     *** Injected channels conversion ***
     ============================================
-    [..]    
-      (#) Enable/disable delay on injected conversion using 
+    [..]
+      (#) Enable/disable delay on injected conversion using
           HAL_SDADC_SelectInjectedDelay.
       (#) If external trigger is used for injected conversion, configure this
           trigger using HAL_SDADC_SelectInjectedExtTrigger.
@@ -95,12 +95,12 @@
           end of injected conversion.
       (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
           at the end of injected conversion.
-      (#) Get value of injected conversion and corresponding channel using 
+      (#) Get value of injected conversion and corresponding channel using
           HAL_SDADC_InjectedGetValue.
-      (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and 
+      (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
           HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
           half transfer and at the transfer complete.
-      (#) Stop injected conversion using HAL_SDADC_InjectedStop, 
+      (#) Stop injected conversion using HAL_SDADC_InjectedStop,
           HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjectedStop_DMA.
 
     *** Multi mode regular channels conversions ***
@@ -113,15 +113,15 @@
       (#) Select regular channel for SDADC1 and SDADC2 (or SDADC3) using
           HAL_SDADC_ConfigChannel.
       (#) Start regular conversion for SDADC2 (or SDADC3) with HAL_SDADC_Start.
-      (#) Start regular conversion for SDADC1 using HAL_SDADC_Start, 
+      (#) Start regular conversion for SDADC1 using HAL_SDADC_Start,
           HAL_SDADC_Start_IT or HAL_SDADC_MultiModeStart_DMA.
       (#) In polling mode, use HAL_SDADC_PollForConversion to detect the end of
           regular conversion for SDADC1.
-      (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the 
+      (#) In interrupt mode, HAL_SDADC_ConvCpltCallback will be called at the
           end of regular conversion for SDADC1.
       (#) Get value of regular conversions using HAL_SDADC_MultiModeGetValue.
-      (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and 
-          HAL_SDADC_ConvCpltCallback will be called respectively at the half 
+      (#) In DMA mode, HAL_SDADC_ConvHalfCpltCallback and
+          HAL_SDADC_ConvCpltCallback will be called respectively at the half
           transfer and at the transfer complete for SDADC1.
       (#) Stop regular conversion using HAL_SDADC_Stop, HAL_SDADC_Stop_IT
           or HAL_SDADC_MultiModeStop_DMA for SDADC1.
@@ -132,29 +132,29 @@
     [..]
       (#) Select type of multimode (SDADC1/SDADC2 or SDADC1/SDADC3) using
           HAL_SDADC_InjectedMultiModeConfigChannel.
-      (#) Select software or external trigger for SDADC1 and synchronized 
+      (#) Select software or external trigger for SDADC1 and synchronized
           trigger for SDADC2 (or SDADC3) using HAL_SDADC_SelectInjectedTrigger.
       (#) Select injected channels for SDADC1 and SDADC2 (or SDADC3) using
           HAL_SDADC_InjectedConfigChannel.
-      (#) Start injected conversion for SDADC2 (or SDADC3) with 
+      (#) Start injected conversion for SDADC2 (or SDADC3) with
           HAL_SDADC_InjectedStart.
       (#) Start injected conversion for SDADC1 using HAL_SDADC_InjectedStart,
           HAL_SDADC_InjectedStart_IT or HAL_SDADC_InjectedMultiModeStart_DMA.
-      (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect 
+      (#) In polling mode, use HAL_SDADC_InjectedPollForConversion to detect
           the end of injected conversion for SDADC1.
       (#) In interrupt mode, HAL_SDADC_InjectedConvCpltCallback will be called
           at the end of injected conversion for SDADC1.
-      (#) Get value of injected conversions using 
+      (#) Get value of injected conversions using
           HAL_SDADC_InjectedMultiModeGetValue.
-      (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and 
+      (#) In DMA mode, HAL_SDADC_InjectedConvHalfCpltCallback and
           HAL_SDADC_InjectedConvCpltCallback will be called respectively at the
           half transfer and at the transfer complete for SDADC1.
-      (#) Stop injected conversion using HAL_SDADC_InjectedStop, 
+      (#) Stop injected conversion using HAL_SDADC_InjectedStop,
           HAL_SDADC_InjectedStop_IT or HAL_SDADC_InjecteddMultiModeStop_DMA
           for SDADC1.
       (#) Stop injected conversion using HAL_SDADC_InjectedStop for SDADC2
           (or SDADC3).
-    
+
     *** Callback registration ***
     =============================================
     [..]
@@ -221,7 +221,7 @@
      When the compilation flag USE_HAL_SDADC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
      are set to the corresponding weak functions.
-  
+
     @endverbatim
   ******************************************************************************
   * @attention
@@ -235,7 +235,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal.h"
@@ -249,7 +249,7 @@
 /** @defgroup SDADC SDADC
   * @brief SDADC HAL driver modules
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -295,16 +295,16 @@ static void              SDADC_DMAError(DMA_HandleTypeDef *hdma);
   */
 
 /** @defgroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and de-initialization functions 
+ *  @brief    Initialization and de-initialization functions
  *
-@verbatim    
+@verbatim
   ===============================================================================
               ##### Initialization and de-initialization functions #####
   ===============================================================================
     [..]  This section provides functions allowing to:
-      (+) Initialize the SDADC. 
-      (+) De-initialize the SDADC. 
-         
+      (+) Initialize the SDADC.
+      (+) De-initialize the SDADC.
+
 @endverbatim
   * @{
   */
@@ -324,14 +324,14 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check parameters */
   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
   assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
   assert_param(IS_SDADC_FAST_CONV_MODE(hsdadc->Init.FastConversionMode));
   assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
   assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
-  
+
   /* Initialize SDADC variables with default values */
   hsdadc->RegularContMode     = SDADC_CONTINUOUS_CONV_OFF;
   hsdadc->InjectedContMode    = SDADC_CONTINUOUS_CONV_OFF;
@@ -343,7 +343,7 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
   hsdadc->RegularMultimode    = SDADC_MULTIMODE_SDADC1_SDADC2;
   hsdadc->InjectedMultimode   = SDADC_MULTIMODE_SDADC1_SDADC2;
   hsdadc->ErrorCode           = SDADC_ERROR_NONE;
-  
+
 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
   if(hsdadc->State == HAL_SDADC_STATE_RESET)
   {
@@ -355,19 +355,19 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
     hsdadc->CalibrationCpltCallback      = HAL_SDADC_CalibrationCpltCallback;
     hsdadc->ErrorCallback                = HAL_SDADC_ErrorCallback;
   }
-  
+
   if (hsdadc->MspInitCallback == NULL)
   {
     hsdadc->MspInitCallback = HAL_SDADC_MspInit; /* Legacy weak MspInit  */
   }
-  
+
   /* Init the low level hardware */
   hsdadc->MspInitCallback(hsdadc);
 #else
   /* Init the low level hardware */
   HAL_SDADC_MspInit(hsdadc);
 #endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
-  
+
   /* Set idle low power and slow clock modes */
   hsdadc->Instance->CR1 &= ~(SDADC_CR1_SBI|SDADC_CR1_PDI|SDADC_CR1_SLOWCK);
   hsdadc->Instance->CR1 |= (hsdadc->Init.IdleLowPowerMode | \
@@ -385,11 +385,11 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
     /* present in SDADC1 register.                                            */
     SDADC1->CR1 &= ~(SDADC_CR1_REFV);
     SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
-    
+
     /* Wait at least 2ms before setting ADON */
     HAL_Delay(2U);
   }
-  
+
   /* Enable SDADC */
   hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
 
@@ -397,14 +397,14 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
   while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0UL)
   {
   }
-  
+
   /* Set SDADC to ready state */
   hsdadc->State = HAL_SDADC_STATE_READY;
-  
+
   /* Return HAL status */
   return HAL_OK;
 }
-  
+
 /**
   * @brief  De-initializes the SDADC.
   * @param  hsdadc SDADC handle.
@@ -439,7 +439,7 @@ HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
     {
       hsdadc->MspDeInitCallback = HAL_SDADC_MspDeInit; /* Legacy weak MspDeInit */
     }
-    
+
     /* DeInit the low level hardware */
     hsdadc->MspDeInitCallback(hsdadc);
 #else
@@ -453,7 +453,7 @@ HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
   /* Return function status */
   return HAL_OK;
 }
-    
+
 /**
   * @brief  Initializes the SDADC MSP.
   * @param  hsdadc SDADC handle
@@ -466,7 +466,7 @@ __weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SDADC_MspInit could be implemented in the user file.
-   */ 
+   */
 }
 
 /**
@@ -481,7 +481,7 @@ __weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
 
   /* NOTE : This function should not be modified, when the callback is needed,
             the HAL_SDADC_MspDeInit could be implemented in the user file.
-   */ 
+   */
 }
 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
 /**
@@ -505,7 +505,7 @@ __weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
 HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SDADC_CallbackIDTypeDef CallbackID, pSDADC_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if (pCallback == NULL)
   {
     /* Update the error code */
@@ -513,7 +513,7 @@ HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SD
 
     return HAL_ERROR;
   }
-  
+
   if (HAL_SDADC_STATE_READY == hsdadc->State)
   {
     switch (CallbackID)
@@ -521,35 +521,35 @@ HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SD
       case HAL_SDADC_CONVERSION_HALF_CB_ID :
         hsdadc->ConvHalfCpltCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_CONVERSION_COMPLETE_CB_ID :
         hsdadc->ConvCpltCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_INJ_CONVERSION_HALF_CB_ID :
         hsdadc->InjectedConvHalfCpltCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_INJ_CONVERSION_COMPLETE_CB_ID :
         hsdadc->InjectedConvCpltCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_CALIBRATION_COMPLETE_CB_ID :
         hsdadc->CalibrationCpltCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_ERROR_CB_ID :
         hsdadc->ErrorCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_MSPINIT_CB_ID :
         hsdadc->MspInitCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_MSPDEINIT_CB_ID :
         hsdadc->MspDeInitCallback = pCallback;
         break;
-      
+
       default :
         /* Update the error code */
         hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
@@ -566,15 +566,15 @@ HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SD
       case HAL_SDADC_MSPINIT_CB_ID :
         hsdadc->MspInitCallback = pCallback;
         break;
-      
+
       case HAL_SDADC_MSPDEINIT_CB_ID :
         hsdadc->MspDeInitCallback = pCallback;
         break;
-      
+
       default :
         /* Update the error code */
         hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status = HAL_ERROR;
         break;
@@ -584,11 +584,11 @@ HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SD
   {
     /* Update the error code */
     hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-    
+
     /* Return error status */
     status =  HAL_ERROR;
   }
-  
+
   return status;
 }
 
@@ -612,7 +612,7 @@ HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SD
 HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_SDADC_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if (HAL_SDADC_STATE_READY == hsdadc->State)
   {
     switch (CallbackID)
@@ -620,39 +620,39 @@ HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_
       case HAL_SDADC_CONVERSION_HALF_CB_ID :
         hsdadc->ConvHalfCpltCallback = HAL_SDADC_ConvHalfCpltCallback;
         break;
-      
+
       case HAL_SDADC_CONVERSION_COMPLETE_CB_ID :
         hsdadc->ConvCpltCallback = HAL_SDADC_ConvCpltCallback;
         break;
-      
+
       case HAL_SDADC_INJ_CONVERSION_HALF_CB_ID :
         hsdadc->InjectedConvHalfCpltCallback = HAL_SDADC_InjectedConvHalfCpltCallback;
         break;
-      
+
       case HAL_SDADC_INJ_CONVERSION_COMPLETE_CB_ID :
         hsdadc->InjectedConvCpltCallback = HAL_SDADC_InjectedConvCpltCallback;
         break;
-      
+
       case HAL_SDADC_CALIBRATION_COMPLETE_CB_ID :
         hsdadc->CalibrationCpltCallback = HAL_SDADC_CalibrationCpltCallback;
         break;
-      
+
       case HAL_SDADC_ERROR_CB_ID :
         hsdadc->ErrorCallback = HAL_SDADC_ErrorCallback;
         break;
-      
+
       case HAL_SDADC_MSPINIT_CB_ID :
         hsdadc->MspInitCallback = HAL_SDADC_MspInit;
         break;
-      
+
       case HAL_SDADC_MSPDEINIT_CB_ID :
         hsdadc->MspDeInitCallback = HAL_SDADC_MspDeInit;
         break;
-      
+
       default :
         /* Update the error code */
         hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status =  HAL_ERROR;
         break;
@@ -665,15 +665,15 @@ HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_
       case HAL_SDADC_MSPINIT_CB_ID :
         hsdadc->MspInitCallback = HAL_SDADC_MspInit;                   /* Legacy weak MspInit              */
         break;
-        
+
       case HAL_SDADC_MSPDEINIT_CB_ID :
         hsdadc->MspDeInitCallback = HAL_SDADC_MspDeInit;               /* Legacy weak MspDeInit            */
         break;
-        
+
       default :
         /* Update the error code */
         hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-        
+
         /* Return error status */
         status =  HAL_ERROR;
         break;
@@ -683,11 +683,11 @@ HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_
   {
     /* Update the error code */
     hsdadc->ErrorCode |= SDADC_ERROR_INVALID_CALLBACK;
-    
+
     /* Return error status */
     status =  HAL_ERROR;
   }
-  
+
   return status;
 }
 
@@ -700,10 +700,10 @@ HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_
 /** @defgroup SDADC_Exported_Functions_Group2 peripheral control functions
  *  @brief    Peripheral control functions
  *
-@verbatim   
+@verbatim
   ===============================================================================
               ##### Peripheral control functions #####
-  ===============================================================================  
+  ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Program one of the three different configurations for channels.
       (+) Associate channel to one of configurations.
@@ -729,7 +729,7 @@ HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *hsdadc, HAL_
   * @param  ConfParamStruct Parameters to apply for this configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, 
+HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
                                                  uint32_t ConfIndex,
                                                  SDADC_ConfParamTypeDef* ConfParamStruct)
 {
@@ -830,7 +830,7 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
       else
       {
         hsdadc->Instance->CONFCHR2 = (uint32_t) (ConfIndex);
-      }      
+      }
       /* Exit init mode */
       SDADC_ExitInitMode(hsdadc);
     }
@@ -859,7 +859,7 @@ HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
   assert_param(IS_SDADC_REGULAR_CHANNEL(Channel));
   assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
-  
+
   /* Check SDADC state */
   if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
   {
@@ -867,11 +867,11 @@ HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
     hsdadc->Instance->CR2 &= (uint32_t) ~(SDADC_CR2_RCH | SDADC_CR2_RCONT);
     if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
     {
-      hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);    
+      hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK) | SDADC_CR2_RCONT);
     }
     else
     {
-      hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));    
+      hsdadc->Instance->CR2 |= (uint32_t) ((Channel & SDADC_MSB_MASK));
     }
     /* Store continuous mode information */
     hsdadc->RegularContMode = ContinuousMode;
@@ -904,7 +904,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
   assert_param(IS_SDADC_INJECTED_CHANNEL(Channel));
   assert_param(IS_SDADC_CONTINUOUS_MODE(ContinuousMode));
-  
+
   /* Check SDADC state */
   if((hsdadc->State != HAL_SDADC_STATE_RESET) && (hsdadc->State != HAL_SDADC_STATE_ERROR))
   {
@@ -913,7 +913,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
     /* Set or clear JCONT bit in SDADC_CR2 */
     if(ContinuousMode == SDADC_CONTINUOUS_CONV_ON)
     {
-      hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;    
+      hsdadc->Instance->CR2 |= SDADC_CR2_JCONT;
     }
     else
     {
@@ -965,7 +965,7 @@ HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, ui
   }
   else
   {
-    status = HAL_ERROR;    
+    status = HAL_ERROR;
   }
   /* Return function status */
   return status;
@@ -1005,7 +1005,7 @@ HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, u
   }
   else
   {
-    status = HAL_ERROR;    
+    status = HAL_ERROR;
   }
   /* Return function status */
   return status;
@@ -1143,7 +1143,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
   }
   else
   {
-    status = HAL_ERROR;    
+    status = HAL_ERROR;
   }
   /* Return function status */
   return status;
@@ -1182,7 +1182,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef*
   }
   else
   {
-    status = HAL_ERROR;    
+    status = HAL_ERROR;
   }
   /* Return function status */
   return status;
@@ -1193,12 +1193,12 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef*
   */
 
 /** @defgroup SDADC_Exported_Functions_Group3 Input and Output operation functions
- *  @brief    IO operation Control functions 
+ *  @brief    IO operation Control functions
  *
-@verbatim   
+@verbatim
   ===============================================================================
               ##### IO operation functions #####
-  ===============================================================================  
+  ===============================================================================
     [..]  This section provides functions allowing to:
       (+) Start calibration.
       (+) Poll for the end of calibration.
@@ -1297,7 +1297,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint3
   else
   {
     /* Get timeout */
-    tickstart = HAL_GetTick();  
+    tickstart = HAL_GetTick();
 
     /* Wait EOCALF bit in SDADC_ISR register */
     while((hsdadc->Instance->ISR & SDADC_ISR_EOCALF) != SDADC_ISR_EOCALF)
@@ -1431,7 +1431,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint3
   else
   {
     /* Get timeout */
-    tickstart = HAL_GetTick();  
+    tickstart = HAL_GetTick();
 
     /* Wait REOCF bit in SDADC_ISR register */
     while((hsdadc->Instance->ISR & SDADC_ISR_REOCF) != SDADC_ISR_REOCF)
@@ -1614,7 +1614,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pDa
     {
       hsdadc->hdma->XferHalfCpltCallback = SDADC_DMARegularHalfConvCplt;
     }
-    
+
     /* Set RDMAEN bit in SDADC_CR1 register */
     hsdadc->Instance->CR1 |= SDADC_CR1_RDMAEN;
 
@@ -1750,7 +1750,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad
   else
   {
     /* Get timeout */
-    tickstart = HAL_GetTick();  
+    tickstart = HAL_GetTick();
 
     /* Wait JEOCF bit in SDADC_ISR register */
     while((hsdadc->Instance->ISR & SDADC_ISR_JEOCF) != SDADC_ISR_JEOCF)
@@ -1943,7 +1943,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint3
     {
       hsdadc->hdma->XferHalfCpltCallback = SDADC_DMAInjectedHalfConvCplt;
     }
-    
+
     /* Set JDMAEN bit in SDADC_CR1 register */
     hsdadc->Instance->CR1 |= SDADC_CR1_JDMAEN;
 
@@ -2029,7 +2029,7 @@ uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Chann
   value = hsdadc->Instance->JDATAR;
   *Channel = ((value & SDADC_JDATAR_JDATACH) >> SDADC_JDATAR_CH_OFFSET);
   value &= SDADC_JDATAR_JDATA;
-  
+
   /* Return injected conversion value */
   return value;
 }
@@ -2177,7 +2177,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
 {
   uint32_t value;
-  
+
   /* Check parameters and check instance is SDADC1 */
   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
   assert_param(hsdadc->Instance == SDADC1);
@@ -2333,7 +2333,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdad
 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
 {
   uint32_t value;
-  
+
   /* Check parameters and check instance is SDADC1 */
   assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
   assert_param(hsdadc->Instance == SDADC1);
@@ -2354,7 +2354,7 @@ uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
 {
   uint32_t tmp_isr = hsdadc->Instance->ISR;
-    
+
   /* Check if end of regular conversion */
   if(((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE) &&
      ((tmp_isr & SDADC_ISR_REOCF) == SDADC_ISR_REOCF))
@@ -2468,12 +2468,12 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
   {
     /* No additional IRQ source */
   }
-  
+
   return;
 }
 
 /**
-  * @brief  Calibration complete callback. 
+  * @brief  Calibration complete callback.
   * @param  hsdadc SDADC handle.
   * @retval None
   */
@@ -2488,7 +2488,7 @@ __weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
 }
 
 /**
-  * @brief  Half regular conversion complete callback. 
+  * @brief  Half regular conversion complete callback.
   * @param  hsdadc SDADC handle.
   * @retval None
   */
@@ -2503,7 +2503,7 @@ __weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
 }
 
 /**
-  * @brief  Regular conversion complete callback. 
+  * @brief  Regular conversion complete callback.
   * @note   In interrupt mode, user has to read conversion value in this function
             using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
   * @param  hsdadc SDADC handle.
@@ -2520,7 +2520,7 @@ __weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
 }
 
 /**
-  * @brief  Half injected conversion complete callback. 
+  * @brief  Half injected conversion complete callback.
   * @param  hsdadc SDADC handle.
   * @retval None
   */
@@ -2535,7 +2535,7 @@ __weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
 }
 
 /**
-  * @brief  Injected conversion complete callback. 
+  * @brief  Injected conversion complete callback.
   * @note   In interrupt mode, user has to read conversion value in this function
             using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
   * @param  hsdadc SDADC handle.
@@ -2552,7 +2552,7 @@ __weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
 }
 
 /**
-  * @brief  Error callback. 
+  * @brief  Error callback.
   * @param  hsdadc SDADC handle.
   * @retval None
   */
@@ -2567,11 +2567,11 @@ __weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
 }
 
 /**
-  * @brief  DMA half transfer complete callback for regular conversion. 
+  * @brief  DMA half transfer complete callback for regular conversion.
   * @param  hdma DMA handle.
   * @retval None
   */
-static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)   
+static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
 {
   /* Get SDADC handle */
   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2585,11 +2585,11 @@ static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief  DMA transfer complete callback for regular conversion. 
+  * @brief  DMA transfer complete callback for regular conversion.
   * @param  hdma DMA handle.
   * @retval None
   */
-static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)   
+static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
 {
   /* Get SDADC handle */
   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2603,11 +2603,11 @@ static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief  DMA half transfer complete callback for injected conversion. 
+  * @brief  DMA half transfer complete callback for injected conversion.
   * @param  hdma DMA handle.
   * @retval None
   */
-static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)   
+static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
 {
   /* Get SDADC handle */
   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2621,11 +2621,11 @@ static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief  DMA transfer complete callback for injected conversion. 
+  * @brief  DMA transfer complete callback for injected conversion.
   * @param  hdma DMA handle.
   * @retval None
   */
-static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)   
+static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
 {
   /* Get SDADC handle */
   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2639,11 +2639,11 @@ static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
 }
 
 /**
-  * @brief  DMA error callback. 
+  * @brief  DMA error callback.
   * @param  hdma DMA handle.
   * @retval None
   */
-static void SDADC_DMAError(DMA_HandleTypeDef *hdma)   
+static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
 {
   /* Get SDADC handle */
   SDADC_HandleTypeDef* hsdadc = (SDADC_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
@@ -2664,20 +2664,20 @@ static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
   */
 
 /** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief   SDADC Peripheral State functions 
+ *  @brief   SDADC Peripheral State functions
  *
-@verbatim   
+@verbatim
   ===============================================================================
              ##### ADC Peripheral State functions #####
-  ===============================================================================  
+  ===============================================================================
     [..] This subsection provides functions allowing to
       (+) Get the SDADC state
       (+) Get the SDADC Error
-         
+
 @endverbatim
   * @{
   */
-  
+
 /**
   * @brief  This function allows to get the current SDADC state.
   * @param  hsdadc SDADC handle.
@@ -2697,7 +2697,7 @@ uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
 {
   return hsdadc->ErrorCode;
 }
-    
+
 /**
   * @}
   */
@@ -2714,7 +2714,7 @@ uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
 static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
 {
   uint32_t tickstart;
-  
+
   /* Set INIT bit on SDADC_CR1 register */
   hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
 
@@ -2723,11 +2723,11 @@ static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
   while((hsdadc->Instance->ISR & SDADC_ISR_INITRDY) == (uint32_t)RESET)
   {
     if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
-    {       
+    {
       return HAL_TIMEOUT;
-    } 
+    }
   }
-  
+
   /* Return HAL status */
   return HAL_OK;
 }
@@ -2752,7 +2752,7 @@ static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
 {
   uint32_t nbChannels = 0UL;
   uint32_t tmp,i;
-  
+
   /* Get the number of channels from bitfield */
   tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
   for(i = 0UL ; i < 9UL ; i++)
@@ -2818,7 +2818,7 @@ static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
 {
   uint32_t tickstart;
   __IO uint32_t dummy_read_for_register_reset;
-  
+
   /* Check continuous mode */
   if(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_ON)
   {
@@ -2830,7 +2830,7 @@ static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
     hsdadc->Instance->CR2 &= ~(SDADC_CR2_RCONT);
   }
   /* Wait for the end of regular conversion */
-  tickstart = HAL_GetTick();  
+  tickstart = HAL_GetTick();
   while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0UL)
   {
     if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
@@ -2942,7 +2942,7 @@ static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
 {
   uint32_t tickstart;
   __IO uint32_t dummy_read_for_register_reset;
-  
+
   /* Check continuous mode */
   if(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_ON)
   {
@@ -2954,7 +2954,7 @@ static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
     hsdadc->Instance->CR2 &= ~(SDADC_CR2_JCONT);
   }
   /* Wait for the end of injected conversion */
-  tickstart = HAL_GetTick();  
+  tickstart = HAL_GetTick();
   while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0UL)
   {
     if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
@@ -3022,12 +3022,12 @@ static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
 
 /**
   * @}
-  */ 
+  */
 
 #endif /* SDADC1 || SDADC2 || SDADC3 */
 #endif /* HAL_SDADC_MODULE_ENABLED */
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c

@@ -3987,7 +3987,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
       if(count == 0U)
       {
         tmp_timeout = 0U;
-      }      
+      }
       count--;
     }
   }

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c

@@ -6,9 +6,9 @@
   *          This file override the native HAL time base functions (defined as weak)
   *          to use the RTC ALARM for time base generation:
   *           + Intializes the RTC peripheral to increment the seconds registers each 1ms
-  *           + The alarm is configured to assert an interrupt when the RTC reaches 1ms 
+  *           + The alarm is configured to assert an interrupt when the RTC reaches 1ms
   *           + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
-  *           + HSE (default), LSE or LSI can be selected as RTC clock source  
+  *           + HSE (default), LSE or LSI can be selected as RTC clock source
  @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -17,13 +17,13 @@
     This file must be copied to the application folder and modified as follows:
     (#) Rename it to 'stm32f3xx_hal_timebase_rtc_alarm.c'
     (#) Add this file and the RTC HAL drivers to your project and uncomment
-       HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h 
+       HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
 
     [..]
-    (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
+    (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
         The wake up capability of the RTC may be intrusive in case of prior low power mode
         configuration requiring different wake up sources.
-        Application/Example behavior is no more guaranteed 
+        Application/Example behavior is no more guaranteed
     (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples
           requiring low power modes
 
@@ -50,26 +50,26 @@
 
 /** @defgroup HAL_TimeBase_RTC_Alarm_Template  HAL TimeBase RTC Alarm Template
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 
-/* Uncomment the line below to select the appropriate RTC Clock source for your application: 
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
   + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
   + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
                           precision.
   + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
                           precision.
   */
-#define RTC_CLOCK_SOURCE_HSE 
+#define RTC_CLOCK_SOURCE_HSE
 /* #define RTC_CLOCK_SOURCE_LSE */
 /* #define RTC_CLOCK_SOURCE_LSI */
 
 #if defined(RTC_CLOCK_SOURCE_HSE)
   #define RTC_ASYNCH_PREDIV       49U
   #define RTC_SYNCH_PREDIV        4U
-#elif defined(RTC_CLOCK_SOURCE_LSE)  
+#elif defined(RTC_CLOCK_SOURCE_LSE)
   #define RTC_ASYNCH_PREDIV       0U
   #define RTC_SYNCH_PREDIV        31U
 #else /*RTC_CLOCK_SOURCE_LSI */
@@ -85,9 +85,9 @@ void RTC_Alarm_IRQHandler(void);
 /* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  This function configures the RTC_ALARMA as a time base source. 
-  *         The time source is configured  to have 1ms time base with a dedicated 
-  *         Tick interrupt priority. 
+  * @brief  This function configures the RTC_ALARMA as a time base source.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
   * @note   This function is called  automatically at the beginning of program after
   *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
   * @param  TickPriority Tick interrupt priority.

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c

@@ -1,13 +1,13 @@
 /**
   ******************************************************************************
-  * @file    stm32f3xx_hal_timebase_rtc_wakeup_template.c 
+  * @file    stm32f3xx_hal_timebase_rtc_wakeup_template.c
   * @brief   HAL time base based on the hardware RTC_WAKEUP Template.
-  *    
+  *
   *          This file overrides the native HAL time base functions (defined as weak)
   *          to use the RTC WAKEUP for the time base generation:
   *           + Intializes the RTC peripheral and configures the wakeup timer to be
   *             incremented each 1ms
-  *           + The wakeup feature is configured to assert an interrupt each 1ms 
+  *           + The wakeup feature is configured to assert an interrupt each 1ms
   *           + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
   *           + HSE (default), LSE or LSI can be selected as RTC clock source
  @verbatim
@@ -18,13 +18,13 @@
     This file must be copied to the application folder and modified as follows:
     (#) Rename it to 'stm32f3xx_hal_timebase_rtc_wakeup.c'
     (#) Add this file and the RTC HAL drivers to your project and uncomment
-       HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h 
+       HAL_RTC_MODULE_ENABLED define in stm32f3xx_hal_conf.h
 
     [..]
-    (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
+    (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
         The wake up capability of the RTC may be intrusive in case of prior low power mode
         configuration requiring different wake up sources.
-        Application/Example behavior is no more guaranteed 
+        Application/Example behavior is no more guaranteed
     (@) The stm32f3xx_hal_timebase_tim use is recommended for the Applications/Examples
           requiring low power modes
 
@@ -51,12 +51,12 @@
 
 /** @defgroup HAL_TimeBase_RTC_WakeUp_Template  HAL TimeBase RTC WakeUp Template
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 
-/* Uncomment the line below to select the appropriate RTC Clock source for your application: 
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
   + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
   + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
                           precision.
@@ -88,15 +88,15 @@ void RTC_WKUP_IRQHandler(void);
 /* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  This function configures the RTC_WKUP as a time base source. 
-  *         The time source is configured  to have 1ms time base with a dedicated 
-  *         Tick interrupt priority. 
-  *         Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK 
+  * @brief  This function configures the RTC_WKUP as a time base source.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
+  *         Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
                              = 1ms
-  *         Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1) 
+  *         Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
                         = 1 ms
   * @note   This function is called  automatically at the beginning of program after
-  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
   * @param  TickPriority Tick interrupt priority.
   * @retval HAL status
   */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c

@@ -1,13 +1,13 @@
 /**
   ******************************************************************************
-  * @file    stm32f3xx_hal_timebase_tim_template.c 
+  * @file    stm32f3xx_hal_timebase_tim_template.c
   * @brief   HAL time base based on the hardware TIM Template.
-  *    
+  *
   *          This file override the native HAL time base functions (defined as weak)
   *          the TIM time base:
   *           + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
   *           + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
-  * 
+  *
   ******************************************************************************
   * @attention
   *
@@ -31,7 +31,7 @@
 
 /** @addtogroup HAL_TimeBase_TIM
   * @{
-  */ 
+  */
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -43,11 +43,11 @@ void TIM6_DAC_IRQHandler(void);
 /* Private functions ---------------------------------------------------------*/
 
 /**
-  * @brief  This function configures the TIM6 as a time base source. 
-  *         The time source is configured  to have 1ms time base with a dedicated 
-  *         Tick interrupt priority. 
+  * @brief  This function configures the TIM6 as a time base source.
+  *         The time source is configured  to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
   * @note   This function is called  automatically at the beginning of program after
-  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). 
+  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
   * @param  TickPriority Tick interrupt priority.
   * @retval HAL status
   */
@@ -170,10 +170,10 @@ void TIM6_DAC_IRQHandler(void)
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c

@@ -40,7 +40,7 @@
         (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
     (+) Typical values:
         (++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler:
-             max timeout before reset: approximately 113.78µs
+             max timeout before reset: approximately 113.78µs
         (++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler
              dividing by 8:
              max timeout before reset: approximately 58.25ms
@@ -55,7 +55,7 @@
     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
     (+) Configure the WWDG prescaler, refresh window value, counter value and early
         interrupt status using HAL_WWDG_Init() function. This will automatically
-        enable WWDG and start its downcounter. Time reference can be taken from 
+        enable WWDG and start its downcounter. Time reference can be taken from
         function exit. Care must be taken to provide a counter value
         greater than 0x40 to prevent generation of immediate reset.
     (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c

@@ -586,7 +586,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
 {
   /* Check the parameters */
   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-  
+
   /* Force reset of ADC clock (core clock) */
   #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
   if(ADCxy_COMMON == ADC12_COMMON)
@@ -602,7 +602,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
   #elif defined(ADC1)
   LL_AHB1_GRP1_ForceReset  (LL_AHB1_GRP1_PERIPH_ADC1);
   #endif
-  
+
   /* Release reset of ADC clock (core clock) */
   #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
   if(ADCxy_COMMON == ADC12_COMMON)
@@ -618,7 +618,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
   #elif defined(ADC1)
   LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
   #endif
-  
+
   return SUCCESS;
 }
 
@@ -640,11 +640,11 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
   assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
-  
+
 #if defined(ADC_MULTIMODE_SUPPORT)
   assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
   if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
@@ -707,7 +707,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni
     /* the same ADC common instance are not disabled.                         */
     status = ERROR;
   }
-  
+
   return status;
 }
 
@@ -723,7 +723,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
   /* Set fields of ADC common */
   /* (all ADC instances belonging to the same ADC common instance) */
   ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
-  
+
 #if defined(ADC_MULTIMODE_SUPPORT)
   /* Set fields of ADC multimode */
   ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
@@ -753,12 +753,12 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
 {
   ErrorStatus status = SUCCESS;
-  
+
   __IO uint32_t timeout_cpu_cycles = 0U;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
+
   /* Disable ADC instance if not already disabled.                            */
   if(LL_ADC_IsEnabled(ADCx) == 1U)
   {
@@ -766,7 +766,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     /* have an external trigger event occurring during the conversion stop    */
     /* ADC disable process.                                                   */
     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-    
+
     /* Stop potential ADC conversion on going on ADC group regular.           */
     if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
     {
@@ -775,12 +775,12 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
         LL_ADC_REG_StopConversion(ADCx);
       }
     }
-    
+
     /* Set ADC group injected trigger source to SW start to ensure to not     */
     /* have an external trigger event occurring during the conversion stop    */
     /* ADC disable process.                                                   */
     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-    
+
     /* Stop potential ADC conversion on going on ADC group injected.          */
     if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
     {
@@ -789,10 +789,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
         LL_ADC_INJ_StopConversion(ADCx);
       }
     }
-    
+
     /* Wait for ADC conversions are effectively stopped                       */
     timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
-    while ((  LL_ADC_REG_IsStopConversionOngoing(ADCx) 
+    while ((  LL_ADC_REG_IsStopConversionOngoing(ADCx)
             | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
     {
       if(timeout_cpu_cycles-- == 0U)
@@ -801,15 +801,15 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
         status = ERROR;
       }
     }
-    
+
     /* Flush group injected contexts queue (register JSQR):                   */
     /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
     /*       contexts queue is maintained with the last active context).      */
     LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
-    
+
     /* Disable the ADC instance */
     LL_ADC_Disable(ADCx);
-    
+
     /* Wait for ADC instance is effectively disabled */
     timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
     while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
@@ -821,7 +821,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
       }
     }
   }
-  
+
   /* Check whether ADC state is compliant with expected state */
   if(READ_BIT(ADCx->CR,
               (  ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
@@ -844,7 +844,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | LL_ADC_IT_AWD2
                | LL_ADC_IT_AWD3 )
              );
-    
+
     /* Reset register ISR */
     SET_BIT(ADCx->ISR,
             (  LL_ADC_FLAG_ADRDY
@@ -859,7 +859,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
              | LL_ADC_FLAG_AWD2
              | LL_ADC_FLAG_AWD3 )
            );
-    
+
     /* Reset register CR */
     /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
     /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
@@ -874,7 +874,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
     /* 2. Set ADVREGEN bits to 0x10 */
     SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
-    
+
     /* Reset register CFGR */
     CLEAR_BIT(ADCx->CFGR,
               (  ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
@@ -884,51 +884,51 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
                | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN  )
              );
-    
+
     /* Reset register SMPR1 */
     CLEAR_BIT(ADCx->SMPR1,
               (  ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
                | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
                | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
              );
-    
+
     /* Reset register SMPR2 */
     CLEAR_BIT(ADCx->SMPR2,
               (  ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
                | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
                | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
              );
-    
+
     /* Reset register TR1 */
     MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
-    
+
     /* Reset register TR2 */
     MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
-    
+
     /* Reset register TR3 */
     MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
-    
+
     /* Reset register SQR1 */
     CLEAR_BIT(ADCx->SQR1,
               (  ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
                | ADC_SQR1_SQ1 | ADC_SQR1_L)
              );
-    
+
     /* Reset register SQR2 */
     CLEAR_BIT(ADCx->SQR2,
               (  ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
                | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
              );
-    
+
     /* Reset register SQR3 */
     CLEAR_BIT(ADCx->SQR3,
               (  ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
                | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
              );
-    
+
     /* Reset register SQR4 */
     CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
-    
+
     /* Reset register JSQR */
     CLEAR_BIT(ADCx->JSQR,
               (  ADC_JSQR_JL
@@ -936,16 +936,16 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
                | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1  )
              );
-    
+
     /* Flush ADC group injected contexts queue */
     SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
     CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
     /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
     SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
-    
+
     /* Reset register DR */
     /* Note: bits in access mode read only, no direct reset applicable */
-    
+
     /* Reset register OFR1 */
     CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
     /* Reset register OFR2 */
@@ -954,19 +954,19 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
     /* Reset register OFR4 */
     CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
-    
+
     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
     /* Note: bits in access mode read only, no direct reset applicable */
-    
+
     /* Reset register AWD2CR */
     CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
-    
+
     /* Reset register AWD3CR */
     CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
-    
+
     /* Reset register DIFSEL */
     CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
-    
+
     /* Reset register CALFACT */
     CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
   }
@@ -983,7 +983,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     /*          all ADC instances belonging to the common ADC instance.       */
     status = ERROR;
   }
-  
+
   return status;
 }
 
@@ -1023,14 +1023,14 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
+
   assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
   assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
-  
+
   /* Note: Hardware constraint (refer to description of this function):       */
   /*       ADC instance must be disabled.                                     */
   if(LL_ADC_IsEnabled(ADCx) == 0U)
@@ -1049,7 +1049,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
                | ADC_InitStruct->DataAlignment
                | ADC_InitStruct->LowPowerMode
               );
-    
+
   }
   else
   {
@@ -1072,7 +1072,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
   ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
   ADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
-  
+
 }
 
 /**
@@ -1110,7 +1110,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
@@ -1126,7 +1126,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
   assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
-  
+
   /* Note: Hardware constraint (refer to description of this function):       */
   /*       ADC instance must be disabled.                                     */
   if(LL_ADC_IsEnabled(ADCx) == 0U)
@@ -1180,7 +1180,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
                  | ADC_REG_InitStruct->Overrun
                 );
     }
-    
+
     /* Set ADC group regular sequencer length and scan direction */
     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
   }
@@ -1238,7 +1238,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
   *          - Set ADC channel sampling time
   *            Refer to function LL_ADC_SetChannelSamplingTime();
-  * @note   Caution to ADC group injected contexts queue: On this STM32 serie, 
+  * @note   Caution to ADC group injected contexts queue: On this STM32 serie,
   *         using successively several times this function will appear has
   *         having no effect.
   *         This is due to ADC group injected contexts queue (this feature
@@ -1254,7 +1254,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
@@ -1268,7 +1268,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I
     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
   }
   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-  
+
   /* Note: Hardware constraint (refer to description of this function):       */
   /*       ADC instance must be disabled.                                     */
   if(LL_ADC_IsEnabled(ADCx) == 0U)
@@ -1302,7 +1302,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I
                  | ADC_INJ_InitStruct->TrigAuto
                 );
     }
-    
+
     MODIFY_REG(ADCx->JSQR,
                  ADC_JSQR_JEXTSEL
                | ADC_JSQR_JEXTEN
@@ -1490,10 +1490,10 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
 {
   /* Check the parameters */
   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
-  
+
   /* Force reset of ADC clock (core clock) */
   LL_APB2_GRP1_ForceReset  (LL_APB2_GRP1_PERIPH_ADC1);
-  
+
   /* Release reset of ADC clock (core clock) */
   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
 
@@ -1513,10 +1513,10 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
+
   /* Disable ADC instance if not already disabled.                            */
   if(LL_ADC_IsEnabled(ADCx) == 1U)
   {
@@ -1524,16 +1524,16 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     /* have an external trigger event occurring during the conversion stop    */
     /* ADC disable process.                                                   */
     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-    
+
     /* Set ADC group injected trigger source to SW start to ensure to not     */
     /* have an external trigger event occurring during the conversion stop    */
     /* ADC disable process.                                                   */
     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-    
+
     /* Disable the ADC instance */
     LL_ADC_Disable(ADCx);
   }
-  
+
   /* Check whether ADC state is compliant with expected state */
   /* (hardware requirements of bits state to reset registers below) */
   if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
@@ -1547,7 +1547,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | LL_ADC_FLAG_JEOS
                | LL_ADC_FLAG_AWD1 )
              );
-    
+
     /* Reset register CR1 */
     CLEAR_BIT(ADCx->CR1,
               (  ADC_CR1_AWDEN   | ADC_CR1_JAWDEN
@@ -1556,7 +1556,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE
                | ADC_CR1_AWDCH                                     )
              );
-    
+
     /* Reset register CR2 */
     CLEAR_BIT(ADCx->CR2,
               (  ADC_CR2_TSVREFE
@@ -1566,14 +1566,14 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | ADC_CR2_RSTCAL   | ADC_CR2_CAL
                | ADC_CR2_CONT     | ADC_CR2_ADON                      )
              );
-    
+
     /* Reset register SMPR1 */
     CLEAR_BIT(ADCx->SMPR1,
               (  ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
                | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
                | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
              );
-    
+
     /* Reset register SMPR2 */
     CLEAR_BIT(ADCx->SMPR2,
               (  ADC_SMPR2_SMP9
@@ -1581,7 +1581,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
                | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
                | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
              );
-    
+
     /* Reset register JOFR1 */
     CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
     /* Reset register JOFR2 */
@@ -1590,41 +1590,41 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
     /* Reset register JOFR4 */
     CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
-    
+
     /* Reset register HTR */
     SET_BIT(ADCx->HTR, ADC_HTR_HT);
     /* Reset register LTR */
     CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
-    
+
     /* Reset register SQR1 */
     CLEAR_BIT(ADCx->SQR1,
               (  ADC_SQR1_L
                | ADC_SQR1_SQ16
                | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
              );
-             
+
     /* Reset register SQR2 */
     CLEAR_BIT(ADCx->SQR2,
               (  ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
                | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
              );
-    
-    
+
+
     /* Reset register JSQR */
     CLEAR_BIT(ADCx->JSQR,
               (  ADC_JSQR_JL
                | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
                | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  )
              );
-    
+
     /* Reset register DR */
     /* bits in access mode read only, no direct reset applicable */
-    
+
     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
     /* bits in access mode read only, no direct reset applicable */
-    
+
   }
-  
+
   return status;
 }
 
@@ -1664,13 +1664,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-  
+
   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
   assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
-  
+
   /* Note: Hardware constraint (refer to description of this function):       */
   /*       ADC instance must be disabled.                                     */
   if(LL_ADC_IsEnabled(ADCx) == 0U)
@@ -1683,7 +1683,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
               ,
                  ADC_InitStruct->SequencersScanMode
               );
-    
+
     MODIFY_REG(ADCx->CR2,
                  ADC_CR2_ALIGN
               ,
@@ -1710,13 +1710,13 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
   /* Set ADC_InitStruct fields to default values */
   /* Set fields of ADC instance */
   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
-  
+
   /* Enable scan mode to have a generic behavior with ADC of other            */
   /* STM32 families, without this setting available:                          */
   /* ADC group regular sequencer and ADC group injected sequencer depend      */
   /* only of their own configuration.                                         */
   ADC_InitStruct->SequencersScanMode      = LL_ADC_SEQ_SCAN_ENABLE;
-  
+
 }
 
 /**
@@ -1754,7 +1754,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
@@ -1763,15 +1763,15 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
   {
     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
   }
-  
+
   /* ADC group regular continuous mode and discontinuous mode                 */
   /* can not be enabled simultenaeously                                       */
   assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
                || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
-  
+
   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
-  
+
   /* Note: Hardware constraint (refer to description of this function):       */
   /*       ADC instance must be disabled.                                     */
   if(LL_ADC_IsEnabled(ADCx) == 0U)
@@ -1807,7 +1807,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
                 );
     }
-    
+
     MODIFY_REG(ADCx->CR2,
                  ADC_CR2_EXTSEL
                | ADC_CR2_CONT
@@ -1890,7 +1890,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
@@ -1900,7 +1900,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I
     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
   }
   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
-  
+
   /* Note: Hardware constraint (refer to description of this function):       */
   /*       ADC instance must be disabled.                                     */
   if(LL_ADC_IsEnabled(ADCx) == 0U)
@@ -1935,13 +1935,13 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I
                  | ADC_INJ_InitStruct->TrigAuto
                 );
     }
-    
+
     MODIFY_REG(ADCx->CR2,
                ADC_CR2_JEXTSEL
               ,
                ADC_INJ_InitStruct->TriggerSource
               );
-    
+
     /* Note: Hardware constraint (refer to description of this function):     */
     /* Note: If ADC instance feature scan mode is disabled                    */
     /*       (refer to  ADC instance initialization structure                 */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c

@@ -73,7 +73,7 @@
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
   )
 
-#elif defined(STM32F303x8) || defined(STM32F328xx) 
+#elif defined(STM32F303x8) || defined(STM32F328xx)
 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
@@ -196,12 +196,12 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
 {
   /* Check the parameters */
   assert_param(IS_DAC_ALL_INSTANCE(DACx));
-  
+
   if(DACx == DAC1)
   {
     /* Force reset of DAC clock */
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
-    
+
     /* Release reset of DAC clock */
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
   }
@@ -210,7 +210,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
   {
     /* Force reset of DAC clock */
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2);
-    
+
     /* Release reset of DAC clock */
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2);
   }
@@ -227,7 +227,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
   * @param  DAC_Channel This parameter can be one of the following values:
   *         @arg @ref LL_DAC_CHANNEL_1
   *         @arg @ref LL_DAC_CHANNEL_2 (1)
-  *         
+  *
   *         (1) On this STM32 serie, parameter not available on all devices.
   *             Refer to device datasheet for channels availability.
   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
@@ -238,7 +238,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
 {
   ErrorStatus status = SUCCESS;
-  
+
   /* Check the parameters */
   assert_param(IS_DAC_ALL_INSTANCE(DACx));
   assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
@@ -249,7 +249,7 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType
   {
     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
   }
-  
+
   /* Note: Hardware constraint (refer to description of this function)        */
   /*       DAC instance must be disabled.                                     */
   if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c

@@ -101,7 +101,7 @@ uint32_t LL_EXTI_DeInit(void)
   LL_EXTI_WriteReg(IMR2,        0xFFFFFFFEU);
 #else
   LL_EXTI_WriteReg(IMR2,        0xFFFFFFFCU);
-#endif  
+#endif
   /* Event mask register 2 set to default reset values */
   LL_EXTI_WriteReg(EMR2,        0x00000000U);
   /* Rising Trigger selection register 2 set to default reset values */

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c

@@ -239,7 +239,7 @@ ErrorStatus LL_RCC_DeInit(void)
   vl_mask = 0xFFFFFFFFU;
   CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 |\
                       RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
- 
+
   /* Write new value in CFGR register */
   LL_RCC_WriteReg(CFGR, vl_mask);
 
@@ -249,10 +249,10 @@ ErrorStatus LL_RCC_DeInit(void)
 
   /* Read CR register */
   vl_mask = LL_RCC_ReadReg(CR);
-  
+
   /* Reset HSEON, CSSON, PLLON bits */
   CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
- 
+
    /* Write new value in CR register */
   LL_RCC_WriteReg(CR, vl_mask);
 
@@ -297,9 +297,9 @@ ErrorStatus LL_RCC_DeInit(void)
   *         and different peripheral clocks available on the device.
   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
-  * @note   If SYSCLK source is PLL, function returns values based on 
+  * @note   If SYSCLK source is PLL, function returns values based on
   *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
-  * @note   (**) HSI_VALUE is a defined constant but the real value may vary 
+  * @note   (**) HSI_VALUE is a defined constant but the real value may vary
   *              depending on the variations in voltage and temperature.
   * @note   (***) HSE_VALUE is a defined constant, user has to ensure that
   *               HSE_VALUE is same as the real frequency of the crystal used.
@@ -586,7 +586,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
         i2c_frequency = RCC_GetSystemClockFreq();
         break;
-	
+
       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
       default:
         if (LL_RCC_HSI_IsReady())

bsp/stm32/libraries/STM32F3xx_HAL/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c

@@ -302,9 +302,9 @@ ErrorStatus LL_SetFlashLatency(uint32_t Frequency)
   * @note   Function is based on the following formula:
   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
   *         - PREDIV: Set to 2 for few devices
-  *         - PLLMUL: The application software must set correctly the PLL multiplication factor to 
+  *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
   *                   not exceed 72MHz
-  * @note   FLASH latency can be modified through this function. 
+  * @note   FLASH latency can be modified through this function.
   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
   *                             the configuration information for the PLL.
   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
@@ -367,9 +367,9 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
   * @note   Function is based on the following formula:
   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
   *         - PREDIV: Set to 2 for few devices
-  *         - PLLMUL: The application software must set correctly the PLL multiplication factor to 
+  *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
   *                   not exceed @ref UTILS_PLL_OUTPUT_MAX
-  * @note   FLASH latency can be modified through this function. 
+  * @note   FLASH latency can be modified through this function.
   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
   * @param  HSEBypass This parameter can be one of the following values:
   *         @arg @ref LL_UTILS_HSEBYPASS_ON
@@ -471,7 +471,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL
   assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
 
   /* Check different PLL parameters according to RM                          */
-  /* The application software must set correctly the PLL multiplication factor to 
+  /* The application software must set correctly the PLL multiplication factor to
      not exceed @ref UTILS_PLL_OUTPUT_MAX */
 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);

bsp/stm32/libraries/templates/stm32f3xx/applications/main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@ int main(void)
 {
     /* LED pin: PB13 */
     rt_uint16_t led = rt_pin_get("PB.13");
-    
+
     /* set LED pin mode to output */
     rt_pin_mode(led, PIN_MODE_OUTPUT);
 

bsp/stm32/libraries/templates/stm32f3xx/board/CubeMX_Config/Src/stm32f3xx_hal_msp.c

@@ -85,7 +85,7 @@ void HAL_MspInit(void)
 */
 
 void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
-                   
+
 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
 {
   if(htim_base->Instance==TIM1)
@@ -169,9 +169,9 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
     __HAL_RCC_USART1_CLK_ENABLE();
 
     __HAL_RCC_GPIOC_CLK_ENABLE();
-    /**USART1 GPIO Configuration    
+    /**USART1 GPIO Configuration
     PC4     ------> USART1_TX
-    PC5     ------> USART1_RX          
+    PC5     ------> USART1_RX
     */
     GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -184,7 +184,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
 
   /* USER CODE END USART1_MspInit 1 */
   }
-  
+
   if(huart->Instance==USART2)
   {
   /* USER CODE BEGIN USART2_MspInit 0 */
@@ -194,10 +194,10 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
     __HAL_RCC_USART2_CLK_ENABLE();
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**USART2 GPIO Configuration    
+    /**USART2 GPIO Configuration
     PA2     ------> USART2_TX
-    PA3     ------> USART2_RX          
-    */ 
+    PA3     ------> USART2_RX
+    */
     GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -219,10 +219,10 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
     __HAL_RCC_USART3_CLK_ENABLE();
 
     __HAL_RCC_GPIOB_CLK_ENABLE();
-    /**USART3 GPIO Configuration    
+    /**USART3 GPIO Configuration
     PB10     ------> USART2_TX
-    PB11     ------> USART2_RX          
-    */ 
+    PB11     ------> USART2_RX
+    */
     GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
     GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -298,8 +298,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
   /* USER CODE BEGIN USART3_MspDeInit 1 */
 
   /* USER CODE END USART3_MspDeInit 1 */
-  } 
-  
+  }
+
 }
 
 /* USER CODE BEGIN 1 */

bsp/stm32/libraries/templates/stm32f3xx/board/CubeMX_Config/Src/system_stm32f3xx.c

@@ -6,7 +6,7 @@
   *
   * 1. This file provides two functions and one global variable to be called from
   *    user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
+  *      - SystemInit(): This function is called at startup just after reset and
   *                      before branch to main program. This call is made inside
   *                      the "startup_stm32f3xx.s" file.
   *
@@ -84,7 +84,7 @@
 /** @addtogroup STM32F3xx_System_Private_Defines
   * @{
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSE_VALUE */
@@ -139,7 +139,7 @@
       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
          Note: If you use this function to configure the system clock there is no need to
-               call the 2 first functions listed above, since SystemCoreClock variable is 
+               call the 2 first functions listed above, since SystemCoreClock variable is
                updated automatically.
   */
 uint32_t SystemCoreClock = 8000000;
@@ -250,7 +250,7 @@ void SystemCoreClockUpdate (void)
         /* HSI oscillator clock selected as PREDIV1 clock entry */
         SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
       }
-#else      
+#else
       if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
       {
         /* HSI oscillator clock divided by 2 selected as PLL clock entry */