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@@ -154,10 +154,10 @@ static struct stm32_hwtimer stm32_hwtimer_obj[] =
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};
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/* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
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-static void pclkx_doubler_get(uint32_t *pclk1_doubler, uint32_t *pclk2_doubler)
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+static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
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{
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- uint32_t flatency = 0;
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- RCC_ClkInitTypeDef RCC_ClkInitStruct;
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+ rt_uint32_t flatency = 0;
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+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RT_ASSERT(pclk1_doubler != RT_NULL);
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RT_ASSERT(pclk1_doubler != RT_NULL);
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@@ -167,15 +167,27 @@ static void pclkx_doubler_get(uint32_t *pclk1_doubler, uint32_t *pclk2_doubler)
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*pclk1_doubler = 1;
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*pclk2_doubler = 1;
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- if(RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
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+#if defined(SOC_SERIES_STM32MP1)
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+ if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
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+ {
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+ *pclk1_doubler = 2;
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+ }
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+ if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
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+ {
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+ *pclk2_doubler = 2;
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+ }
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+#else
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+ if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
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{
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*pclk1_doubler = 2;
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}
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-
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- if(RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
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+#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
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+ if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
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{
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*pclk2_doubler = 2;
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}
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+#endif
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+#endif
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}
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static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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