@@ -36,7 +36,8 @@ if RT_USING_LWP
config LWP_ENABLE_ASID
bool "The switch of ASID feature"
- default n
+ depends on ARCH_ARM_CORTEX_A
+ default y
if ARCH_MM_MMU
config RT_LWP_SHM_MAX_NR
@@ -121,8 +121,10 @@ struct rt_lwp
int debug;
uint32_t bak_first_ins;
+#ifdef LWP_ENABLE_ASID
uint64_t generation;
unsigned int asid;
+#endif
};
struct rt_lwp *lwp_self(void);
@@ -296,6 +298,6 @@ rt_channel_t gdb_server_channel(void);
int dbg_step_type(void);
void dbg_attach_req(void *pc);
int dbg_check_suspend(void);
-void set_process_id(int pid);
+void rt_hw_set_process_id(int pid);
#endif
@@ -289,7 +289,6 @@ rt_hw_mmu_switch:
dsb
isb
mov pc, lr
-
.global rt_hw_mmu_tbl_get
rt_hw_mmu_tbl_get:
mrc p15, 0, r0, c2, c0, 0 /* ttbr0 */
@@ -613,8 +612,8 @@ vector_resv:
b .
#ifdef RT_USING_SMP
-.global rt_clz
-rt_clz:
+.global rt_hw_clz
+rt_hw_clz:
clz r0, r0
bx lr