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@@ -5,15 +5,16 @@
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*
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* Change Logs:
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* Date Author Notes
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- * 2018-11-5 SummerGift change to new framework
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+ * 2018-11-5 SummerGift first version
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* 2018-12-11 greedyhao Porting for stm32f7xx
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+ * 2019-01-03 zylx modify DMA initialization and spixfer function
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*/
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#include "board.h"
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#ifdef RT_USING_SPI
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-#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
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+#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
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/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
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#include "drv_spi.h"
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@@ -72,7 +73,7 @@ static struct stm32_spi_config spi_config[] =
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#endif
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};
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-static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
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+static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
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static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
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{
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@@ -201,6 +202,10 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
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spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
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spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi_handle->State = HAL_SPI_STATE_RESET;
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+#ifdef SOC_SERIES_STM32L4
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+ spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
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+#endif
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+
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if (HAL_SPI_Init(spi_handle) != HAL_OK)
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{
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return RT_EIO;
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@@ -210,204 +215,112 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
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SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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#endif
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- __HAL_SPI_ENABLE(spi_handle);
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-
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- LOG_D("%s init done", spi_drv->config->bus_name);
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- return RT_EOK;
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-}
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-
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-#ifdef BSP_SPI_USING_DMA
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-static uint8_t dummy = 0xFF;
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-static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_message* message)
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-{
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- struct stm32_spi *spi_drv = rt_container_of(spi_bus, struct stm32_spi, spi_bus);
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-
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- DMA_HandleTypeDef * hdma_tx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_tx;
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- DMA_HandleTypeDef * hdma_rx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_rx;
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-
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- HAL_DMA_DeInit(hdma_tx);
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- HAL_DMA_DeInit(hdma_rx);
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-
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- /*
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- * Check if the DMA Stream is disabled before enabling it.
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- * Note that this step is useful when the same Stream is used multiple times.
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- */
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-#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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- while (hdma_tx->Instance->CR & DMA_SxCR_EN);
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- while (hdma_rx->Instance->CR & DMA_SxCR_EN);
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-#endif
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-
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- if(message->recv_buf != RT_NULL)
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+ /* DMA configuration */
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+ if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
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{
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- hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
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- }
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- else
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- {
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- message->recv_buf = &dummy;
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- hdma_rx->Init.MemInc = DMA_MINC_DISABLE;
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- }
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- HAL_DMA_Init(hdma_rx);
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+ HAL_DMA_Init(&spi_drv->dma.handle_rx);
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- __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
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+ __HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
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- if(message->send_buf != RT_NULL)
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- {
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- hdma_tx->Init.MemInc = DMA_MINC_ENABLE;
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+ /* NVIC configuration for DMA transfer complete interrupt */
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+ HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
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+ HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
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}
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- else
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+
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+ if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
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{
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- dummy = 0xFF;
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- message->send_buf = &dummy;
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- hdma_tx->Init.MemInc = DMA_MINC_DISABLE;
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- }
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- HAL_DMA_Init(hdma_tx);
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+ HAL_DMA_Init(&spi_drv->dma.handle_tx);
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- /* link DMA with SPI */
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- __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
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+ __HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
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- LOG_D("%s RX Instance: %x, TX Instance: %x", spi_drv->config->bus_name, hdma_rx->Instance, hdma_tx->Instance);
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- LOG_D("%s dma config done, TX dma_irq number: %d, RX dma_irq number: %d",
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- spi_drv->config->bus_name,
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- spi_drv->config->dma_tx.dma_irq,
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- spi_drv->config->dma_rx.dma_irq);
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+ /* NVIC configuration for DMA transfer complete interrupt */
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+ HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
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+ HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
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+ }
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- /* NVIC configuration for DMA transfer complete interrupt*/
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- HAL_NVIC_SetPriority(spi_drv->config->dma_tx.dma_irq, 0, 1);
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- HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx.dma_irq);
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+ __HAL_SPI_ENABLE(spi_handle);
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- /* NVIC configuration for DMA transfer complete interrupt*/
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- HAL_NVIC_SetPriority(spi_drv->config->dma_rx.dma_irq, 0, 0);
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- HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx.dma_irq);
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+ LOG_D("%s init done", spi_drv->config->bus_name);
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+ return RT_EOK;
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}
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-#endif
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static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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+ HAL_StatusTypeDef state;
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+
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
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- SPI_HandleTypeDef * spi_handle = &spi_drv->handle;
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+ SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
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struct stm32_hw_spi_cs *cs = device->parent.user_data;
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- rt_int32_t length = message->length;
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- rt_int32_t data_width = spi_drv->cfg->data_width;
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if (message->cs_take)
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{
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HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
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}
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-#ifdef BSP_SPI_USING_DMA
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- if(message->length > 32)
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+ LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
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+ LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
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+ spi_drv->config->bus_name,
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+ (uint32_t)message->send_buf,
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+ (uint32_t)message->recv_buf, message->length);
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+
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+ if (message->length)
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{
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- if(data_width <= 8)
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+ /* start once data exchange in DMA mode */
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+ if (message->send_buf && message->recv_buf)
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+ {
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+ if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
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+ {
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+ state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length);
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+ }else
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+ {
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+ state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, 1000);
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+ }
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+ }
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+ else if (message->send_buf)
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{
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- HAL_StatusTypeDef state;
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- LOG_D("%s dma transfer prepare and start", spi_drv->config->bus_name);
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- LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
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- spi_drv->config->bus_name,
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- (uint32_t)message->send_buf,
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- (uint32_t)message->recv_buf, message->length);
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-
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- spi_dma_transfer_prepare(device->bus, message);
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- /* start once data exchange in DMA mode */
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- state = HAL_SPI_TransmitReceive_DMA(spi_handle,
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- (uint8_t*)message->send_buf,
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- (uint8_t*)message->recv_buf,
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- message->length);
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- if (state != HAL_OK)
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+ if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
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{
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- LOG_D("spi flash configuration error : %d", state);
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- message->length = 0;
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- //while(1);
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+ state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)message->send_buf, message->length);
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}
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else
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{
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- LOG_D("%s dma transfer done", spi_drv->config->bus_name);
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+ state = HAL_SPI_Transmit(spi_handle, (uint8_t *)message->send_buf, message->length, 1000);
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}
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-
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- /* For simplicity reasons, this example is just waiting till the end of the
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- transfer, but application may perform other tasks while transfer operation
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- is ongoing. */
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- while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
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- LOG_D("%s get state done", spi_drv->config->bus_name);
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}
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else
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{
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- // TODO
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- }
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- } else
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-#endif
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- {
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- if (data_width == 8)
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- {
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- const rt_uint8_t * send_ptr = message->send_buf;
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- rt_uint8_t * recv_ptr = message->recv_buf;
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-
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- while (length--)
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+ if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
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{
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- rt_uint8_t data = ~0;
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-
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- if(send_ptr != RT_NULL)
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- {
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- data = *send_ptr++;
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- }
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-
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- /* send data once */
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- while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
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- *(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data;
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-
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- /* receive data once */
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-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
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- SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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-#endif
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- while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
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- data = *(volatile rt_uint8_t *)(&spi_handle->Instance->DR);
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-
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- if(recv_ptr != RT_NULL)
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- {
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- *recv_ptr++ = data;
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- }
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+ state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)message->recv_buf, message->length);
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}
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-
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- } else
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- {
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- const rt_uint16_t * send_ptr = message->send_buf;
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- rt_uint16_t * recv_ptr = message->recv_buf;
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-
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- while (length--)
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+ else
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{
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- rt_uint16_t data = ~0;
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-
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- if(send_ptr != RT_NULL)
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- {
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- data = *send_ptr++;
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- }
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-
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- /* send data once */
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- while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
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- *(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data;
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-
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- /* receive data once */
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-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
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- SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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-#endif
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- while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
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- data = *(volatile rt_uint16_t *)(&spi_handle->Instance->DR);
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-
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- if(recv_ptr != RT_NULL)
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- {
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- *recv_ptr++ = data;
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- }
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+ state = HAL_SPI_Receive(spi_handle, (uint8_t *)message->recv_buf, message->length, 1000);
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}
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}
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- }
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-
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- /* Wait until Busy flag is reset before disabling SPI */
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- while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_BSY) == SET);
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+
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+ if (state != HAL_OK)
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+ {
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+ LOG_I("spi transfer error : %d", state);
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+ message->length = 0;
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+ spi_handle->State = HAL_SPI_STATE_READY;
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+ }
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+ else
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+ {
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+ LOG_D("%s transfer done", spi_drv->config->bus_name);
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+ }
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+ /* For simplicity reasons, this example is just waiting till the end of the
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+ transfer, but application may perform other tasks while transfer operation
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+ is ongoing. */
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+ while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
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+ }
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+
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if (message->cs_release)
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{
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HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
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@@ -443,61 +356,81 @@ static int rt_hw_spi_bus_init(void)
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spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
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spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
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-#ifdef BSP_SPI_USING_DMA
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- /* Configure the DMA handler for Transmission process */
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- spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance;
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+ if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
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+ {
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+ /* Configure the DMA handler for Transmission process */
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+ spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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- spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel;
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+ spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
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#elif defined(SOC_SERIES_STM32L4)
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- spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request;
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-#endif
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- spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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- spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
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- spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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- spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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- spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
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- spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
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+ spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
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+#endif
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+ spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
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+ spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
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+ spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
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+ spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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+ spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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+ spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
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+ spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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- spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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- spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
|
- spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
|
|
|
- spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
|
|
|
+ spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
|
+ spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
|
+ spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
|
|
|
+ spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
|
|
|
#endif
|
|
|
|
|
|
- spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance;
|
|
|
+ {
|
|
|
+ rt_uint32_t tmpreg = 0x00U;
|
|
|
+#if defined(SOC_SERIES_STM32F1)
|
|
|
+ /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
|
|
+ SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
|
|
|
+ tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
|
|
|
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
|
|
+ SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
|
|
|
+ /* Delay after an RCC peripheral clock enabling */
|
|
|
+ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
|
|
|
+#endif
|
|
|
+ UNUSED(tmpreg); /* To avoid compiler warnings */
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
|
|
|
+ {
|
|
|
+ /* Configure the DMA handler for Transmission process */
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
|
|
|
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
|
|
|
#elif defined(SOC_SERIES_STM32L4)
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request;
|
|
|
-#endif
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
|
|
|
+#endif
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
|
|
|
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
|
|
|
- spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
|
|
|
+ spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
|
|
|
#endif
|
|
|
+
|
|
|
{
|
|
|
rt_uint32_t tmpreg = 0x00U;
|
|
|
#if defined(SOC_SERIES_STM32F1)
|
|
|
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
|
|
- SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
|
|
|
- tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
|
|
|
+ SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
|
|
|
+ tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
|
|
|
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
|
|
- SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
|
|
|
- /* Delay after an RCC peripheral clock enabling */
|
|
|
- tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
|
|
|
+ SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
|
|
|
+ /* Delay after an RCC peripheral clock enabling */
|
|
|
+ tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
|
|
|
#endif
|
|
|
UNUSED(tmpreg); /* To avoid compiler warnings */
|
|
|
}
|
|
|
-
|
|
|
- LOG_D("%s DMA clock init done", spi_config[i].bus_name);
|
|
|
-#endif /* BSP_SPI_USING_DMA */
|
|
|
+ }
|
|
|
|
|
|
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
@@ -511,7 +444,7 @@ static int rt_hw_spi_bus_init(void)
|
|
|
/**
|
|
|
* Attach the spi device to SPI bus, this function must be used after initialization.
|
|
|
*/
|
|
|
-rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin)
|
|
|
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
|
|
|
{
|
|
|
RT_ASSERT(bus_name != RT_NULL);
|
|
|
RT_ASSERT(device_name != RT_NULL);
|
|
|
@@ -550,7 +483,20 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
|
|
|
return result;
|
|
|
}
|
|
|
|
|
|
-#if defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA)
|
|
|
+#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
|
|
|
+void SPI1_IRQHandler(void)
|
|
|
+{
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
|
* @param None
|
|
|
@@ -566,7 +512,9 @@ void SPI1_DMA_RX_IRQHandler(void)
|
|
|
/* leave interrupt */
|
|
|
rt_interrupt_leave();
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
|
* @param None
|
|
|
@@ -584,7 +532,20 @@ void SPI1_DMA_TX_IRQHandler(void)
|
|
|
}
|
|
|
#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
-#if defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA)
|
|
|
+#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
|
|
|
+void SPI2_IRQHandler(void)
|
|
|
+{
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
|
* @param None
|
|
|
@@ -600,7 +561,9 @@ void SPI2_DMA_RX_IRQHandler(void)
|
|
|
/* leave interrupt */
|
|
|
rt_interrupt_leave();
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
|
* @param None
|
|
|
@@ -618,7 +581,20 @@ void SPI2_DMA_TX_IRQHandler(void)
|
|
|
}
|
|
|
#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
-#if defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA)
|
|
|
+#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
|
|
|
+void SPI3_IRQHandler(void)
|
|
|
+{
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
|
* @param None
|
|
|
@@ -634,7 +610,9 @@ void SPI3_DMA_RX_IRQHandler(void)
|
|
|
/* leave interrupt */
|
|
|
rt_interrupt_leave();
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
|
* @param None
|
|
|
@@ -652,8 +630,20 @@ void SPI3_DMA_TX_IRQHandler(void)
|
|
|
}
|
|
|
#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
+#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
|
|
|
+void SPI4_IRQHandler(void)
|
|
|
+{
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+}
|
|
|
+#endif
|
|
|
|
|
|
-#if defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA)
|
|
|
+#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
|
* @param None
|
|
|
@@ -669,7 +659,9 @@ void SPI4_DMA_RX_IRQHandler(void)
|
|
|
/* leave interrupt */
|
|
|
rt_interrupt_leave();
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
|
* @param None
|
|
|
@@ -687,7 +679,20 @@ void SPI4_DMA_TX_IRQHandler(void)
|
|
|
}
|
|
|
#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
-#if defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA)
|
|
|
+#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
|
|
|
+void SPI5_IRQHandler(void)
|
|
|
+{
|
|
|
+ /* enter interrupt */
|
|
|
+ rt_interrupt_enter();
|
|
|
+
|
|
|
+ HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
|
|
|
+
|
|
|
+ /* leave interrupt */
|
|
|
+ rt_interrupt_leave();
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
|
* @param None
|
|
|
@@ -703,7 +708,9 @@ void SPI5_DMA_RX_IRQHandler(void)
|
|
|
/* leave interrupt */
|
|
|
rt_interrupt_leave();
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
|
* @param None
|
|
|
@@ -721,7 +728,7 @@ void SPI5_DMA_TX_IRQHandler(void)
|
|
|
}
|
|
|
#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
-#if defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA)
|
|
|
+#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Rx interrupt request.
|
|
|
* @param None
|
|
|
@@ -737,7 +744,9 @@ void SPI6_DMA_RX_IRQHandler(void)
|
|
|
/* leave interrupt */
|
|
|
rt_interrupt_leave();
|
|
|
}
|
|
|
+#endif
|
|
|
|
|
|
+#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
|
|
|
/**
|
|
|
* @brief This function handles DMA Tx interrupt request.
|
|
|
* @param None
|
|
|
@@ -755,8 +764,78 @@ void SPI6_DMA_TX_IRQHandler(void)
|
|
|
}
|
|
|
#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
|
|
|
|
|
|
+static void stm32_get_dma_info(void)
|
|
|
+{
|
|
|
+#ifdef BSP_SPI1_RX_USING_DMA
|
|
|
+ spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
|
|
+ static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
|
|
|
+ spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
|
|
|
+#endif
|
|
|
+#ifdef BSP_SPI1_TX_USING_DMA
|
|
|
+ spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
|
|
+ static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
|
|
|
+ spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_SPI2_RX_USING_DMA
|
|
|
+ spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
|
|
+ static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
|
|
|
+ spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
|
|
|
+#endif
|
|
|
+#ifdef BSP_SPI2_TX_USING_DMA
|
|
|
+ spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
|
|
+ static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
|
|
|
+ spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_SPI3_RX_USING_DMA
|
|
|
+ spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
|
|
+ static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
|
|
|
+ spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
|
|
|
+#endif
|
|
|
+#ifdef BSP_SPI3_TX_USING_DMA
|
|
|
+ spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
|
|
+ static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
|
|
|
+ spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_SPI4_RX_USING_DMA
|
|
|
+ spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
|
|
+ static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
|
|
|
+ spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
|
|
|
+#endif
|
|
|
+#ifdef BSP_SPI4_TX_USING_DMA
|
|
|
+ spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
|
|
+ static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
|
|
|
+ spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_SPI5_RX_USING_DMA
|
|
|
+ spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
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+ static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
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+ spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
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+#endif
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+#ifdef BSP_SPI5_TX_USING_DMA
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+ spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
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+ static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
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+ spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
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+#endif
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+
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+#ifdef BSP_SPI6_RX_USING_DMA
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+ spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
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+ static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
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+ spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
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+#endif
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+#ifdef BSP_SPI6_TX_USING_DMA
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+ spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
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+ static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
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+ spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
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+#endif
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+}
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+
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int rt_hw_spi_init(void)
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{
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+ stm32_get_dma_info();
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return rt_hw_spi_bus_init();
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|
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}
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INIT_BOARD_EXPORT(rt_hw_spi_init);
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SummerGift