format link scripts

bsp/CME_M7/CME_M7.sct

@@ -1,22 +1,22 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-; load 		region 			size_region
-LR_IROM1 	(0)				(1024 * 128)
-{
-	; load address = execution address
-	ER_IROM1 (0) 			(1024 * 128)
-	{
-		*.o (RESET, +First)
-		*(InRoot$$Sections)
-		.ANY (+RO)
-	}
-
-	; RW data
-	RW_IRAM1 0x20000000 (1024 * 48)
-	{
-		.ANY (+RW +ZI)
-	}
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+; load      region          size_region
+LR_IROM1    (0)             (1024 * 128)
+{
+    ; load address = execution address
+    ER_IROM1 (0)            (1024 * 128)
+    {
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+
+    ; RW data
+    RW_IRAM1 0x20000000 (1024 * 48)
+    {
+        .ANY (+RW +ZI)
+    }
+}
+

bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct

@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf

@@ -1,253 +1,253 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm0plus.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM0+ core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x08001FFF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x10001FFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-/* Public RAM 
- * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
- * This region is used to place objects that require full access from both cores.
- * Uncomment the following lines, define region size, and uncomment the placement of
- * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
- *  and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
- */
-/*
-define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-*/
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block RO     {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application */
-".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
-place in          IROM1_region  { block RO };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region  { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in          IRAM1_region  { readwrite };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* Public RAM 
- *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
- */
-/*
-place at start of IRAM2_region  { section .cy_sharedmem };
-*/
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_app_header,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm0plus.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x08001FFF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x10001FFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+/* Public RAM
+ * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+ * This region is used to place objects that require full access from both cores.
+ * Uncomment the following lines, define region size, and uncomment the placement of
+ * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
+ *  and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
+ */
+/*
+define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+*/
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application */
+".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
+place in          IROM1_region  { block RO };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* Public RAM
+ *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
+ */
+/*
+place at start of IRAM2_region  { section .cy_sharedmem };
+*/
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_app_header,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x000FD800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x000FD800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf

@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE  = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
-define block RO     {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region  { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in          IROM1_region  { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region  { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in          IRAM1_region  { readwrite };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_m0p_image,
-        section .cy_app_signature,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct

@@ -1,292 +1,292 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct

@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct

@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct

@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct

@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct

@@ -1,311 +1,311 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x80000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00010000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct

@@ -1,288 +1,288 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00010000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08020000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0000C000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00070000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00010000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08020000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0000C000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00070000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct

@@ -1,307 +1,307 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00010000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08020000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0000C000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00010000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08020000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0000C000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x000D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct

@@ -1,307 +1,307 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00010000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x080E0000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0000C000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* is equal to MBED_ROM_START
+;*
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    MBED_ROM_START
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00010000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* is equal to MBED_ROM_SIZE
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x080E0000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0000C000
+#endif
+
+#if !defined(MBED_PUBLIC_RAM_SIZE)
+  #define MBED_PUBLIC_RAM_SIZE     0x200
+#endif
+
+; The size of the stack section at the end of CM0+ SRAM
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+#if !defined(MBED_PUBLIC_RAM_START)
+  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
+#endif
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Public RAM
+#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
+#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x001D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct

@@ -1,295 +1,295 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x2000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00040000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0001D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x2000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00040000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0001D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct

@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x2000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00080000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0003D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x2000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00080000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0003D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct

@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x2000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00080000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0001D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x2000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00080000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0001D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct

@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x2000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00100000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00045800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x2000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00100000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x00045800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct

@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x2000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00100000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0007D800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x2000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00100000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0007D800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct

@@ -1,314 +1,314 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x2000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00200000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08002000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x000FD800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x2000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00200000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08002000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x000FD800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct

@@ -1,298 +1,298 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x10000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00030000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000800
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0001F800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00070000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x10000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00030000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000800
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0001F800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00070000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct

@@ -1,317 +1,317 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x10000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x00068000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000800
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0001F800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x10000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x00068000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000800
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x0001F800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x000D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MBED/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct

@@ -1,317 +1,317 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE     0x10000
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. In case if MBED_APP_START address is
-;* customized by the bootloader config, the application image should not
-;* include CM0p prebuilt image.
-;*
-
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
-#endif
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x000E0000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system.
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000800
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x000DF800
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x10000
+
+#if !defined(MBED_ROM_START)
+  #define MBED_ROM_START    0x10000000
+#endif
+
+;* MBED_APP_START is being  used by the bootloader build script and
+;* will be calculate by the system. In case if MBED_APP_START address is
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
+;*
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
+#endif
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+#if !defined(MBED_ROM_SIZE)
+  #define MBED_ROM_SIZE     0x000E0000
+#endif
+
+;* MBED_APP_SIZE is being  used by the bootloader build script and
+;* will be calculate by the system.
+;*
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
+#endif
+
+#if !defined(MBED_RAM_START)
+  #define MBED_RAM_START    0x08000800
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+  #define MBED_RAM_SIZE     0x000DF800
+#endif
+
+#if !defined(MBED_BOOT_STACK_SIZE)
+  #define MBED_BOOT_STACK_SIZE 0x400
+#endif
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE MBED_BOOT_STACK_SIZE
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               MBED_RAM_START
+#define RAM_SIZE                MBED_RAM_SIZE
+; Flash
+#define FLASH_START             MBED_APP_START
+#define FLASH_SIZE              MBED_APP_SIZE
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x001D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx4_cm0plus.sct

@@ -1,253 +1,253 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct

@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx6_cm0plus.sct

@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx7_cm0plus.sct

@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx8_cm0plus.sct

@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct

@@ -1,272 +1,272 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00002000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00002000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM 
-; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
-; This region is used to place objects that require full access from both cores.
-; Uncomment the following lines, define the region size and uncomment placement of
-; .cy_sharedmem section below.
-; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
-; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    .cy_app_header +0
-    {
-        * (.cy_app_header)
-    }
-
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
-    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
-    ;{
-    ;    * (.cy_sharedmem)
-    ;}
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx5_cm0plus.sct

@@ -1,244 +1,244 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08020000
-#define RAM_SIZE                0x0000C000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00010000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM
-#define PUBLIC_RAM_SIZE         0x800
-#define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00070000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08020000
+#define RAM_SIZE                0x0000C000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00010000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+#define PUBLIC_RAM_SIZE         0x800
+#define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00070000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct

@@ -1,263 +1,263 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x08020000
-#define RAM_SIZE                0x0000C000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00010000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM
-#define PUBLIC_RAM_SIZE         0x800
-#define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08020000
+#define RAM_SIZE                0x0000C000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00010000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+#define PUBLIC_RAM_SIZE         0x800
+#define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x000D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct

@@ -1,263 +1,263 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm0plus.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               0x080E0000
-#define RAM_SIZE                0x0000C000
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00010000
-
-; The size of the stack section at the end of CM0+ SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-; Public RAM
-#define PUBLIC_RAM_SIZE         0x800
-#define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x080E0000
+#define RAM_SIZE                0x0000C000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00010000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM
+#define PUBLIC_RAM_SIZE         0x800
+#define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    RW_IRAM2 PUBLIC_RAM_START UNINIT
+    {
+        * (.cy_sharedmem)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM2), 8)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x001D0000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx4_cm0plus.icf

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
 define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
 define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
 
-/* Public RAM 
+/* Public RAM
  * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
  * This region is used to place objects that require full access from both cores.
  * Uncomment the following lines, define region size, and uncomment the placement of
@@ -198,7 +198,7 @@ place at start of IRAM1_region  { readwrite section .intvec_ram};
 place in          IRAM1_region  { readwrite };
 place at end   of IRAM1_region  { block HSTACK };
 
-/* Public RAM 
+/* Public RAM
  *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
  */
 /*

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
 define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
 define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
 
-/* Public RAM 
+/* Public RAM
  * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
  * This region is used to place objects that require full access from both cores.
  * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region  { readwrite section .intvec_ram};
 place in          IRAM1_region  { readwrite };
 place at end   of IRAM1_region  { block HSTACK };
 
-/* Public RAM 
+/* Public RAM
  *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
  */
 /*

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx6_cm0plus.icf

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
 define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
 define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
 
-/* Public RAM 
+/* Public RAM
  * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
  * This region is used to place objects that require full access from both cores.
  * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region  { readwrite section .intvec_ram};
 place in          IRAM1_region  { readwrite };
 place at end   of IRAM1_region  { block HSTACK };
 
-/* Public RAM 
+/* Public RAM
  *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
  */
 /*

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
 define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
 define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
 
-/* Public RAM 
+/* Public RAM
  * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
  * This region is used to place objects that require full access from both cores.
  * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region  { readwrite section .intvec_ram};
 place in          IRAM1_region  { readwrite };
 place at end   of IRAM1_region  { block HSTACK };
 
-/* Public RAM 
+/* Public RAM
  *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
  */
 /*

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx8_cm0plus.icf

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
 define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
 define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
 
-/* Public RAM 
+/* Public RAM
  * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
  * This region is used to place objects that require full access from both cores.
  * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region  { readwrite section .intvec_ram};
 place in          IRAM1_region  { readwrite };
 place at end   of IRAM1_region  { block HSTACK };
 
-/* Public RAM 
+/* Public RAM
  *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
  */
 /*

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf

@@ -142,7 +142,7 @@ define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFED
 define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
 define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
 
-/* Public RAM 
+/* Public RAM
  * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
  * This region is used to place objects that require full access from both cores.
  * Uncomment the following lines, define region size, and uncomment the placement of
@@ -200,7 +200,7 @@ place at start of IRAM1_region  { readwrite section .intvec_ram};
 place in          IRAM1_region  { readwrite };
 place at end   of IRAM1_region  { block HSTACK };
 
-/* Public RAM 
+/* Public RAM
  *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
  */
 /*

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4.sct

@@ -1,240 +1,240 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x0001F780
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00040000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x0001F780
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00040000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx4_cm4_dual.sct

@@ -1,258 +1,258 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx4_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x0001D800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00040000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00040000
-#define __cy_memory_0_row_size 0x200
-
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx4_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x0001D800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00040000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00040000
+#define __cy_memory_0_row_size 0x200
+
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4.sct

@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x0003F780
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x0003F780
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x0003D800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x0003D800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4.sct

@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x0001F780
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x0001F780
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx6_cm4_dual.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx6_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x0001D800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00080000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00080000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx6_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x0001D800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00080000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00080000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4.sct

@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x00047780
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00047780
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x00045800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x00045800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual_cm0p_bless.sct

@@ -1,280 +1,280 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;* 
-;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08003000
-#define RAM_SIZE                0x00044800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-; Size and start address of the Cortex-M0+ application image
-FLASH_CM0P_SIZE  = 0x20000;
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual_cm0p_bless.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* This linker script is modified from cy8c6xx7_cm4_dual.sct for CM0P_BLESS image.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08003000
+#define RAM_SIZE                0x00044800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+; Size and start address of the Cortex-M0+ application image
+FLASH_CM0P_SIZE  = 0x20000;
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4.sct

@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x0007F780
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x0007F780
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx8_cm4_dual.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx8_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x0007D800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00100000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx8_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x0007D800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00100000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4.sct

@@ -1,259 +1,259 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; RAM
-#define RAM_START               0x08000000
-#define RAM_SIZE                0x000FF780
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x000FF780
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M4 application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x000FD800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x000FD800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4.sct

@@ -1,133 +1,133 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10020000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START               0x08001800
-#define RAM_SIZE                0x0001E800
-; Flash
-#define FLASH_START             0x10020000
-#define FLASH_SIZE              0x00020000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10020000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START               0x08001800
+#define RAM_SIZE                0x0001E800
+; Flash
+#define FLASH_START             0x10020000
+#define FLASH_SIZE              0x00020000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx5_cm4_dual.sct

@@ -1,147 +1,147 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx5_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08000800
-#define RAM_SIZE                0x0001F800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00030000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The size of the Cortex-M0+ application image (including MCU boot header area)
-#define FLASH_CM0P_SIZE         0x10000
-
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
-    .cy_m0p_image +0
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx5_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08000800
+#define RAM_SIZE                0x0001F800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00030000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The size of the Cortex-M0+ application image (including MCU boot header area)
+#define FLASH_CM0P_SIZE         0x10000
+
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4.sct

@@ -1,148 +1,148 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10060000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START               0x08001800
-#define RAM_SIZE                0x0001E800
-; Flash
-#define FLASH_START             0x10060000
-#define FLASH_SIZE              0x00030000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10060000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START               0x08001800
+#define RAM_SIZE                0x0001E800
+; Flash
+#define FLASH_START             0x10060000
+#define FLASH_SIZE              0x00030000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct

@@ -1,162 +1,162 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08000800
-#define RAM_SIZE                0x0001F800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00068000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The size of the Cortex-M0+ application image (including MCU boot header area)
-#define FLASH_CM0P_SIZE         0x10000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
-    .cy_m0p_image +0
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xx7_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08000800
+#define RAM_SIZE                0x0001F800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00068000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The size of the Cortex-M0+ application image (including MCU boot header area)
+#define FLASH_CM0P_SIZE         0x10000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct

@@ -1,148 +1,148 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x100E0000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START               0x08001800
-#define RAM_SIZE                0x000DE800
-; Flash
-#define FLASH_START             0x100E0000
-#define FLASH_SIZE              0x00070000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x100E0000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START               0x08001800
+#define RAM_SIZE                0x000DE800
+; Flash
+#define FLASH_START             0x100E0000
+#define FLASH_SIZE              0x00070000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct

@@ -1,162 +1,162 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08000800
-#define RAM_SIZE                0x000DF800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x000E0000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The size of the Cortex-M0+ application image (including MCU boot header area)
-#define FLASH_CM0P_SIZE         0x10000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
-{
-    .cy_m0p_image +0
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyb06xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08000800
+#define RAM_SIZE                0x000DF800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x000E0000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The size of the Cortex-M0+ application image (including MCU boot header area)
+#define FLASH_CM0P_SIZE         0x10000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM4/TOOLCHAIN_ARM/cys06xxa_cm4.sct

@@ -1,148 +1,148 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cys06xxa_cm4.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10050000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START               0x08030000
-#define RAM_SIZE                0x000B7000
-; Flash
-#define FLASH_START             0x10050000
-#define FLASH_SIZE              0x0011C000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cys06xxa_cm4.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10050000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; RAM
+#define RAM_START               0x08030000
+#define RAM_SIZE                0x000B7000
+; Flash
+#define FLASH_START             0x10050000
+#define FLASH_SIZE              0x0011C000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_flash_cbus.sct

@@ -1,159 +1,159 @@
-#! armclang -E  --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-/***************************************************************************//**
-* \file cyw20829_ns_flash_cbus.sct
-* \version 1.0.0
-*
-* Linker file for the ARMCC compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location starts at 0x0401e000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#define flash_start_addr_cbus 0x08000000
-#define ram_start_addr_sahb 0x20000000
-#define ram_start_addr_cbus 0x04000000
-#define ram_end_addr_sahb 0x20020000
-
-#define app_code_offset_flash 0x00002200
-#define bootstrap_offset_ram 0x0001E000
-
-; The size of the stack section at the end of CM33 SRAM
-#define STACK_SIZE              0x00001000
-
-
-/* VMA for bootstrap Text */
-#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */
-/* Size of bootstrap section */
-#define bootstrapText_size 0x00002000
-
-/* VMA for bootstrap Data */
-#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */
-
-/* VMA for flash */
-#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */
-
-/* Memory reserved for Bootstrap code and data */
-#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */
-
-; Cortex-M33 application flash area
-LR_1 bootstrapText_vma BOOTSTRAP_SIZE
-{
-    bootstrap bootstrapText_vma bootstrapText_size
-    {
-        * (RESET, +FIRST)
-        * (InRoot$$Sections)
-
-        ns_start_cyw20829.o (+RO)
-        ns_system_cyw20829.o (+RO)
-
-        /* drivers */
-        cy_device.o (+RO)
-        cy_btss.o (+RO)
-        cy_sysclk_v2.o (+RO)
-        cy_syspm_v2.o (+RO)
-        cy_sysint_v2.o (+RO)
-        cy_syslib*.o (+RO)
-        ppu_v1.o (+RO)
-        cy_mpc.o (+RO)
-        cy_pd_ppu.o (+RO)
-        *(.cy_l1func*)
-    }
-
-/* converting c-bus to sahb address */
-#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4)
-
-    bootstrapData bootstrapData_vma ALIGN 4
-    {
-        ns_start_cyw20829.o (+RW, +ZI)
-        ns_system_cyw20829.o (+RW, +ZI)
-
-        /* drivers */
-        cy_device.o (+RW, +ZI)
-        cy_btss.o (+RW, +ZI)
-        cy_sysclk_v2.o (+RW, +ZI)
-        cy_syspm_v2.o (+RW, +ZI)
-        cy_sysint_v2.o (+RW, +ZI)
-        cy_syslib*.o (+RW, +ZI)
-        ppu_v1.o (+RW, +ZI)
-        cy_mpc.o (+RW, +ZI)
-        cy_pd_ppu.o (+RW, +ZI)
-    }
-
-    bootstrap_vector bootstrapRamVect_vma UNINIT
-    {
-        * (.bss.noinit.RESET_RAM, +FIRST)
-    }
-}
-
-#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8)
-
-LR_2 appText_vma
-{
-    app appText_vma
-    {
-        * (+RO)
-    }
-
-    appTextRam appTextRam_vma
-    {
-        * (.cy_ramfunc)
-        cy_smif.o (+RO)
-        cy_smif_memslot.o (+RO)
-    }
-
-#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8)
-
-    appData appData_vma
-    {
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    appData_noinit +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8))
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE
-    {
-    }
-}
-/* [] END OF FILE */
+#! armclang -E  --target=arm-arm-none-eabi -x c -mcpu=cortex-m33 -march=armv8-m.main
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+/***************************************************************************//**
+* \file cyw20829_ns_flash_cbus.sct
+* \version 1.0.0
+*
+* Linker file for the ARMCC compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location starts at 0x0401e000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#define flash_start_addr_cbus 0x08000000
+#define ram_start_addr_sahb 0x20000000
+#define ram_start_addr_cbus 0x04000000
+#define ram_end_addr_sahb 0x20020000
+
+#define app_code_offset_flash 0x00002200
+#define bootstrap_offset_ram 0x0001E000
+
+; The size of the stack section at the end of CM33 SRAM
+#define STACK_SIZE              0x00001000
+
+
+/* VMA for bootstrap Text */
+#define bootstrapText_vma ram_start_addr_cbus + bootstrap_offset_ram /* 0x0401E000 */
+/* Size of bootstrap section */
+#define bootstrapText_size 0x00002000
+
+/* VMA for bootstrap Data */
+#define bootstrapRamVect_vma ram_start_addr_sahb + STACK_SIZE /* 0x20001000 */
+
+/* VMA for flash */
+#define appText_vma flash_start_addr_cbus + app_code_offset_flash /* 0x08002200 */
+
+/* Memory reserved for Bootstrap code and data */
+#define BOOTSTRAP_SIZE ram_end_addr_sahb - ram_start_addr_sahb - bootstrap_offset_ram; /* 0x00002000 */
+
+; Cortex-M33 application flash area
+LR_1 bootstrapText_vma BOOTSTRAP_SIZE
+{
+    bootstrap bootstrapText_vma bootstrapText_size
+    {
+        * (RESET, +FIRST)
+        * (InRoot$$Sections)
+
+        ns_start_cyw20829.o (+RO)
+        ns_system_cyw20829.o (+RO)
+
+        /* drivers */
+        cy_device.o (+RO)
+        cy_btss.o (+RO)
+        cy_sysclk_v2.o (+RO)
+        cy_syspm_v2.o (+RO)
+        cy_sysint_v2.o (+RO)
+        cy_syslib*.o (+RO)
+        ppu_v1.o (+RO)
+        cy_mpc.o (+RO)
+        cy_pd_ppu.o (+RO)
+        *(.cy_l1func*)
+    }
+
+/* converting c-bus to sahb address */
+#define bootstrapData_vma AlignExpr((ImageLimit(bootstrap) - ram_start_addr_cbus) + ram_start_addr_sahb, 4)
+
+    bootstrapData bootstrapData_vma ALIGN 4
+    {
+        ns_start_cyw20829.o (+RW, +ZI)
+        ns_system_cyw20829.o (+RW, +ZI)
+
+        /* drivers */
+        cy_device.o (+RW, +ZI)
+        cy_btss.o (+RW, +ZI)
+        cy_sysclk_v2.o (+RW, +ZI)
+        cy_syspm_v2.o (+RW, +ZI)
+        cy_sysint_v2.o (+RW, +ZI)
+        cy_syslib*.o (+RW, +ZI)
+        ppu_v1.o (+RW, +ZI)
+        cy_mpc.o (+RW, +ZI)
+        cy_pd_ppu.o (+RW, +ZI)
+    }
+
+    bootstrap_vector bootstrapRamVect_vma UNINIT
+    {
+        * (.bss.noinit.RESET_RAM, +FIRST)
+    }
+}
+
+#define appTextRam_vma AlignExpr(ImageLimit( bootstrap_vector), 8)
+
+LR_2 appText_vma
+{
+    app appText_vma
+    {
+        * (+RO)
+    }
+
+    appTextRam appTextRam_vma
+    {
+        * (.cy_ramfunc)
+        cy_smif.o (+RO)
+        cy_smif_memslot.o (+RO)
+    }
+
+#define appData_vma AlignExpr((ImageLimit(appTextRam) - ImageBase(appTextRam) + ImageLimit(bootstrap_vector)), 8)
+
+    appData appData_vma
+    {
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    appData_noinit +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 ALIGN 8 EMPTY ((ram_start_addr_sahb + bootstrap_offset_ram)-AlignExpr(ImageLimit(appData_noinit), 8))
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (ram_start_addr_sahb + STACK_SIZE) ALIGN 32 EMPTY -STACK_SIZE
+    {
+    }
+}
+/* [] END OF FILE */

bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/TOOLCHAIN_ARM/cyw20829_ns_ram_cbus.sct

@@ -1,163 +1,163 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyw20829_ns.sct
-;* \version 1.0.0
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2020 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM33 core.
-; RAM
-
-#define CODE_ROM_NS_CBUS_START 0x00000000
-#define CODE_ROM_NS_CBUS_SIZE 0x00010000
-#define CODE_SRAM0_NS_CBUS_START 0x04004200
-#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000
-#define CODE_XIP_NS_CBUS_START 0x08000000
-#define CODE_XIP_NS_CBUS_SIZE 0x08000000
-
-#define DATA_ROM_NS_SAHB_START 0x00000000
-#define DATA_ROM_NS_SAHB_SIZE  0x00000000
-#define BSS_ROM_NS_SAHB_START 0x00000000
-#define BSS_ROM_NS_SAHB_SIZE 0x00000000
-#define DATA_SRAM0_NS_SAHB_START 0x20012200
-#define DATA_SRAM0_NS_SAHB_SIZE  0x0000DE00
-#define BSS_SRAM0_NS_SAHB_START 0x20000000
-#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000
-#define DATA_XIP_NS_SAHB_START 0x60000000
-#define DATA_XIP_NS_SAHB_SIZE  0x00000000
-#define BSS_XIP_NS_SAHB_START 0x60000000
-#define BSS_XIP_NS_SAHB_SIZE 0x00000000
-
-
-/*
-#define RAM_START               0x20004200
-#define RAM_SIZE                0x0001BE00
-*/
-#define RAM_START               DATA_SRAM0_NS_SAHB_START
-#define RAM_SIZE                DATA_SRAM0_NS_SAHB_SIZE
-
-; Flash
-/*
-#define FLASH_START             0x60000000
-#define FLASH_SIZE              0x00010000
-*/
-
-#define FLASH_START             CODE_SRAM0_NS_CBUS_START
-#define FLASH_SIZE              CODE_SRAM0_NS_CBUS_SIZE
-
-; The size of the stack section at the end of CM33 SRAM
-#define STACK_SIZE              0x00001000
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000000
-
-; The following defines describe device specific memory regions and must not be changed.
-
-; External memory
-#define XIP_START               CODE_XIP_NS_CBUS_START
-#define XIP_SIZE                CODE_XIP_NS_CBUS_SIZE
-
-
-; Cortex-M33 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (.bss.noinit.RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cyw20829_ns.sct
+;* \version 1.0.0
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2020 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM33 core.
+; RAM
+
+#define CODE_ROM_NS_CBUS_START 0x00000000
+#define CODE_ROM_NS_CBUS_SIZE 0x00010000
+#define CODE_SRAM0_NS_CBUS_START 0x04004200
+#define CODE_SRAM0_NS_CBUS_SIZE 0x0000E000
+#define CODE_XIP_NS_CBUS_START 0x08000000
+#define CODE_XIP_NS_CBUS_SIZE 0x08000000
+
+#define DATA_ROM_NS_SAHB_START 0x00000000
+#define DATA_ROM_NS_SAHB_SIZE  0x00000000
+#define BSS_ROM_NS_SAHB_START 0x00000000
+#define BSS_ROM_NS_SAHB_SIZE 0x00000000
+#define DATA_SRAM0_NS_SAHB_START 0x20012200
+#define DATA_SRAM0_NS_SAHB_SIZE  0x0000DE00
+#define BSS_SRAM0_NS_SAHB_START 0x20000000
+#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000
+#define DATA_XIP_NS_SAHB_START 0x60000000
+#define DATA_XIP_NS_SAHB_SIZE  0x00000000
+#define BSS_XIP_NS_SAHB_START 0x60000000
+#define BSS_XIP_NS_SAHB_SIZE 0x00000000
+
+
+/*
+#define RAM_START               0x20004200
+#define RAM_SIZE                0x0001BE00
+*/
+#define RAM_START               DATA_SRAM0_NS_SAHB_START
+#define RAM_SIZE                DATA_SRAM0_NS_SAHB_SIZE
+
+; Flash
+/*
+#define FLASH_START             0x60000000
+#define FLASH_SIZE              0x00010000
+*/
+
+#define FLASH_START             CODE_SRAM0_NS_CBUS_START
+#define FLASH_SIZE              CODE_SRAM0_NS_CBUS_SIZE
+
+; The size of the stack section at the end of CM33 SRAM
+#define STACK_SIZE              0x00001000
+
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000000
+
+; The following defines describe device specific memory regions and must not be changed.
+
+; External memory
+#define XIP_START               CODE_XIP_NS_CBUS_START
+#define XIP_SIZE                CODE_XIP_NS_CBUS_SIZE
+
+
+; Cortex-M33 application flash area
+LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (.bss.noinit.RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+/* [] END OF FILE */

bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.icf

@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE  = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
-define block RO     {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region  { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in          IROM1_region  { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region  { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in          IRAM1_region  { readwrite };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_m0p_image,
-        section .cy_app_signature,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/libraries/templates/PSOC62/board/linker_scripts/link.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x000FD800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x000FD800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.icf

@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE  = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
-define block RO     {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region  { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in          IROM1_region  { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region  { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in          IRAM1_region  { readwrite };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_m0p_image,
-        section .cy_app_signature,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/linker_scripts/link.sct

@@ -1,277 +1,277 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xxa_cm4_dual.sct
-;* \version 2.91
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2021 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x000FD800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00200000
-
-; The size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-; More about CM0+ prebuilt images, see here:
-; https://github.com/cypresssemiconductorco/psoc6cm0p
-; The size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00200000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x000FD800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct

@@ -1,274 +1,274 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cy8c6xx7_cm4_dual.sct
-;* \version 2.60
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2019 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; You can change the memory allocation by editing RAM and Flash defines.
-; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
-; Using this memory region for other purposes will lead to unexpected behavior.
-; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
-; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
-; RAM
-#define RAM_START               0x08002000
-#define RAM_SIZE                0x00045800
-; Flash
-#define FLASH_START             0x10000000
-#define FLASH_SIZE              0x00100000
-
-; Size of the stack section at the end of CM4 SRAM
-#define STACK_SIZE              0x00001000
-
-; Size of the Cortex-M0+ application flash image
-#define FLASH_CM0P_SIZE         0x2000
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash image area
-LR_IROM FLASH_START FLASH_CM0P_SIZE
-{
-    .cy_m0p_image +0 FLASH_CM0P_SIZE
-    {
-        * (.cy_m0p_image)
-    }
-}
-
-; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
-    {
-    }
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    .cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x00100000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xx7_cm4_dual.sct
+;* \version 2.60
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2019 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x00045800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00100000
+
+; Size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; Size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    .cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00100000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/Infineon/psoc6-pioneerkit_modus/libs/TARGET_CY8CKIT-062-BLE/linker/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf

@@ -1,240 +1,240 @@
-/***************************************************************************//**
-* \file cy8c6xx7_cm4_dual.icf
-* \version 2.60
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x08047800;
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x10100000;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* Size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE  = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
-define block RO     {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region  { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in          IROM1_region  { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region  { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in          IRAM1_region  { readwrite };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_m0p_image,
-        section .cy_app_signature,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00100000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/***************************************************************************//**
+* \file cy8c6xx7_cm4_dual.icf
+* \version 2.60
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x08047800;
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x10100000;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* Size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+".cy_xip" : place at start of EROM1_region  { section .cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00100000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/Vango/v85xx/Target_FLASH.icf

@@ -28,4 +28,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 place at address mem:__Reset_Handler_text_start__ { readonly section .Reset_Handler_text };
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
+                        block CSTACK, block HEAP };

bsp/acm32/acm32f0x0-nucleo/drivers/linker_scripts/link.icf

@@ -1,34 +1,34 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0001FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x0800;
-define symbol __ICFEDIT_size_heap__   = 0x0000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-
-export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/acm32/acm32f4xx-nucleo/drivers/linker_scripts/link.icf

@@ -1,34 +1,34 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x0800;
-define symbol __ICFEDIT_size_heap__   = 0x0000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-
-export symbol __ICFEDIT_region_RAM_start__;
-export symbol __ICFEDIT_region_RAM_end__;
-
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/airm2m/air105/board/linker_scripts/link.lds

@@ -90,7 +90,7 @@ SECTIONS
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/airm2m/air32f103/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/airm2m/air32f103/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/allwinner/d1/link.lds

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,7 +38,7 @@ SECTIONS
 
     . = ALIGN(8);
 
-    .text : 
+    .text :
     {
         *(.text)                        /* remaining code */
         *(.text.*)                      /* remaining code */
@@ -47,7 +47,7 @@ SECTIONS
         *(.glue_7)
         *(.glue_7t)
         *(.gnu.linkonce.t*)
-     
+
         /* section information for finsh shell */
         . = ALIGN(8);
         __fsymtab_start = .;
@@ -74,20 +74,20 @@ SECTIONS
         _etext = .;
     } > SRAM
 
-    .eh_frame_hdr : 
-    { 
-         *(.eh_frame_hdr) 
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
          *(.eh_frame_entry)
     } > SRAM
     .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
 
     . = ALIGN(8);
 
-    .data : 
+    .data :
     {
         *(.data)
         *(.data.*)
-    
+
         *(.data1)
         *(.data1.*)
 
@@ -97,7 +97,7 @@ SECTIONS
         *(.sdata)
         *(.sdata.*)
     } > SRAM
-    
+
     . = ALIGN(8);
     .ctors :
     {
@@ -139,7 +139,7 @@ SECTIONS
 
     . = ALIGN(8);
 
-    .sbss : 
+    .sbss :
     {
     __bss_start = .;
         *(.sbss)

bsp/allwinner/d1/link_stacksize.lds

@@ -1 +1 @@
-__STACKSIZE__ = 16384;
+__STACKSIZE__ = 16384;

bsp/allwinner/d1s/link.lds

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,7 +38,7 @@ SECTIONS
 
     . = ALIGN(8);
 
-    .text : 
+    .text :
     {
         *(.text)                        /* remaining code */
         *(.text.*)                      /* remaining code */
@@ -47,7 +47,7 @@ SECTIONS
         *(.glue_7)
         *(.glue_7t)
         *(.gnu.linkonce.t*)
-     
+
         /* section information for finsh shell */
         . = ALIGN(8);
         __fsymtab_start = .;
@@ -74,9 +74,9 @@ SECTIONS
         _etext = .;
     } > SRAM
 
-    .eh_frame_hdr : 
-    { 
-         *(.eh_frame_hdr) 
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
          *(.eh_frame_entry)
     } > SRAM
     .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
@@ -85,11 +85,11 @@ SECTIONS
     __text_end = .;
     __text_size = __text_end - __text_start;
 
-    .data : 
+    .data :
     {
         *(.data)
         *(.data.*)
-    
+
         *(.data1)
         *(.data1.*)
 
@@ -141,7 +141,7 @@ SECTIONS
 
     . = ALIGN(8);
 
-    .sbss : 
+    .sbss :
     {
     __bss_start = .;
         *(.sbss)

bsp/allwinner/d1s/link_stacksize.lds

@@ -1 +1 @@
-__STACKSIZE__ = 16384;
+__STACKSIZE__ = 16384;

bsp/allwinner_tina/link.lds

@@ -4,7 +4,7 @@ OUTPUT_ARCH(arm)
 SECTIONS
 {
     . = 0x80000000;
-    
+
     . = ALIGN(4);
     __text_start = .;
     .text :
@@ -12,7 +12,7 @@ SECTIONS
         *(.vectors)
         *(.text)
         *(.text.*)
-	KEEP(*(.fini))
+    KEEP(*(.fini))
 
         /* section information for finsh shell */
         . = ALIGN(4);
@@ -47,18 +47,18 @@ SECTIONS
     .ctors :
     {
         PROVIDE(__ctors_start__ = .);
-	*crtbegin.o(.ctors)
-	*crtbegin?.o(.ctors)
-	*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-	*(SORT(.ctors.*))
-	*(.ctors)
-        PROVIDE(__ctors_end__ = .);       
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+        PROVIDE(__ctors_end__ = .);
     }
 
-    .ARM.extab : 
+    .ARM.extab :
     {
-	*(.ARM.extab* .gnu.linkonce.armextab.*)
-    } 
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    }
     /* The .ARM.exidx section is used for C++ exception handling. */
     /* .ARM.exidx is sorted, so has to go in its own output section.  */
     __exidx_start = .;
@@ -70,15 +70,15 @@ SECTIONS
         _sidata = .;
     }
     __exidx_end = .;
-    
+
     .dtors :
     {
         PROVIDE(__dtors_start__ = .);
         *crtbegin.o(.dtors)
- 		*crtbegin?.o(.dtors)
- 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- 		*(SORT(.dtors.*))
- 		*(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
         PROVIDE(__dtors_end__ = .);
     }
 
@@ -89,30 +89,30 @@ SECTIONS
         *(.data)
         *(.data.*)
 
-		. = ALIGN(4);
-		/* preinit data */
-		PROVIDE_HIDDEN (__preinit_array_start = .);
-		KEEP(*(.preinit_array))
-		PROVIDE_HIDDEN (__preinit_array_end = .);
-
-		. = ALIGN(4);
-		/* init data */
-		PROVIDE_HIDDEN (__init_array_start = .);
-		KEEP(*(SORT(.init_array.*)))
-		KEEP(*(.init_array))
-		PROVIDE_HIDDEN (__init_array_end = .);
-
-
-		. = ALIGN(4);
-		/* finit data */
-		PROVIDE_HIDDEN (__fini_array_start = .);
-		KEEP(*(SORT(.fini_array.*)))
-		KEEP(*(.fini_array))
-		PROVIDE_HIDDEN (__fini_array_end = .);
-
-		KEEP(*(.jcr*))
-		. = ALIGN(4);
-		/* All data end */
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
 
         *(.gnu.linkonce.d*)
     }

bsp/amebaz/bootloader_symbol.icf

@@ -1,13 +1,13 @@
-/* Bootloader symbol list */ 
-define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;  
-define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;  
-define exported symbol BOOT_FLASH_Image1 = 0x0800043b;  
-define exported symbol IMAGE1$$Base = 0x10002001;  
-define exported symbol RamStartTable = 0x10002001;  
-define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;  
-define exported symbol boot_export_symbol = 0x10002021;  
-define exported symbol BOOT_System_Init1 = 0x10002251;  
-define exported symbol BOOT_System_Init2 = 0x10002263;  
-define exported symbol BOOT_Swd_Off = 0x10002275;  
-define exported symbol boot_ram_end = 0x10002455;  
-define exported symbol IMAGE1$$Limit = 0x10002459;  
+/* Bootloader symbol list */
+define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;
+define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;
+define exported symbol BOOT_FLASH_Image1 = 0x0800043b;
+define exported symbol IMAGE1$$Base = 0x10002001;
+define exported symbol RamStartTable = 0x10002001;
+define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;
+define exported symbol boot_export_symbol = 0x10002021;
+define exported symbol BOOT_System_Init1 = 0x10002251;
+define exported symbol BOOT_System_Init2 = 0x10002263;
+define exported symbol BOOT_Swd_Off = 0x10002275;
+define exported symbol boot_ram_end = 0x10002455;
+define exported symbol IMAGE1$$Limit = 0x10002459;

bsp/amebaz/image2.icf

@@ -9,24 +9,24 @@ include "rom_symbol_v01_iar.icf";
 /****************************************
  * Memory Regions                   *
  ****************************************/
-define symbol __ICFEDIT_region_ROM_start__       	= 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__         	= 0x0007FFFF;
+define symbol __ICFEDIT_region_ROM_start__          = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__            = 0x0007FFFF;
 define symbol __ICFEDIT_region_ROMBSS_RAM_start__       = 0x10000000;
-define symbol __ICFEDIT_region_ROMBSS_RAM_end__        	= 0x10001FFF;
+define symbol __ICFEDIT_region_ROMBSS_RAM_end__         = 0x10001FFF;
 define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__   = 0x10002000;
 define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__     = 0x10004FFF;
-define symbol __ICFEDIT_region_BD_RAM_start__    	= 0x10005000;
-define symbol __ICFEDIT_region_BD_RAM_end__      	= 0x1002FFFF;
-define symbol __ICFEDIT_region_MSP_RAM_start__    	= 0x1003E000;
-define symbol __ICFEDIT_region_MSP_RAM_end__      	= 0x1003EFFF;
-define symbol __ICFEDIT_region_RDP_RAM_start__    	= 0x1003F000;
-define symbol __ICFEDIT_region_RDP_RAM_end__      	= 0x1003FFEF;
-define symbol __ICFEDIT_region_IMG2_TEMP_start__ 	= 0x10006000;
-define symbol __ICFEDIT_region_IMG2_TEMP_end__   	= 0x1000BFFF;
-define symbol __ICFEDIT_region_XIP_BOOT_start__ 	= 0x08000000+0x20;
-define symbol __ICFEDIT_region_XIP_BOOT_end__   	= 0x08003FFF;
-define symbol __ICFEDIT_region_XIP_OTA1_start__ 	= 0x0800B000+0x20;
-define symbol __ICFEDIT_region_XIP_OTA1_end__   	= 0x080FFFFF;
+define symbol __ICFEDIT_region_BD_RAM_start__       = 0x10005000;
+define symbol __ICFEDIT_region_BD_RAM_end__         = 0x1002FFFF;
+define symbol __ICFEDIT_region_MSP_RAM_start__      = 0x1003E000;
+define symbol __ICFEDIT_region_MSP_RAM_end__        = 0x1003EFFF;
+define symbol __ICFEDIT_region_RDP_RAM_start__      = 0x1003F000;
+define symbol __ICFEDIT_region_RDP_RAM_end__        = 0x1003FFEF;
+define symbol __ICFEDIT_region_IMG2_TEMP_start__    = 0x10006000;
+define symbol __ICFEDIT_region_IMG2_TEMP_end__      = 0x1000BFFF;
+define symbol __ICFEDIT_region_XIP_BOOT_start__     = 0x08000000+0x20;
+define symbol __ICFEDIT_region_XIP_BOOT_end__       = 0x08003FFF;
+define symbol __ICFEDIT_region_XIP_OTA1_start__     = 0x0800B000+0x20;
+define symbol __ICFEDIT_region_XIP_OTA1_end__       = 0x080FFFFF;
 /****************************************
  * Sizes                   *
  ****************************************/
@@ -68,16 +68,16 @@ keep { section .hal.rom.bss* };
 keep { section .wlan_ram_map* };
 keep { section .libc.ram.bss* };
 keep { section .ssl_ram_map* };
-define block .hal.rom.bss with fixed order{         section .ram_vector_table1, 
+define block .hal.rom.bss with fixed order{         section .ram_vector_table1,
                                                 section .ram_vector_table2,
                                                 section .ram_vector_table3,
                                                 section .hal.rom.bss*,
                                                 section .wlan_ram_map*,
                                                 section .libc.ram.bss*,
-                                                section .ssl_ram_map*, 
+                                                section .ssl_ram_map*,
                                       };
 define block ROM_BSS with fixed order { block .hal.rom.bss};
-place at start of ROM_BSS_region  { readwrite, 
+place at start of ROM_BSS_region  { readwrite,
                                       block ROM_BSS,
                                       };
 /****************************************
@@ -86,21 +86,21 @@ place at start of ROM_BSS_region  { readwrite,
 keep { section .image1.entry.data* };
 keep { section .image1.validate.rodata* };
 define block .ram_image1.entry with fixed order{section .image1.entry.data*,
-						section .image1.validate.rodata*,
-						};
+                        section .image1.validate.rodata*,
+                        };
 keep { section .boot.ram.text* };
 keep { section .boot.rodata* };
 define block .ram_image1.text with fixed order{section .boot.ram.text*,
-						section .boot.rodata*,
-						};
+                        section .boot.rodata*,
+                        };
 keep { section .boot.ram.data* };
 define block .ram_image1.data with fixed order{section .boot.ram.data*,
-						};
+                        };
 keep { section .boot.ram.bss* };
 define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
-						};
+                        };
 define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
-place at start of BOOT_RAM_region   { readwrite, 
+place at start of BOOT_RAM_region   { readwrite,
                                     block IMAGE1,
                                   };
 /****************************************
@@ -109,39 +109,39 @@ place at start of BOOT_RAM_region   { readwrite,
 keep { section .image2.entry.data* };
 keep { section .image2.validate.rodata* };
 define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
-						section .image2.validate.rodata*,
-						};
+                        section .image2.validate.rodata*,
+                        };
 define block SHT$$PREINIT_ARRAY { preinit_array };
 define block SHT$$INIT_ARRAY { init_array };
 define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
-					block SHT$$INIT_ARRAY };
-define block .ram.data with fixed order{ section .data*, 
-					 section DATA, 
-					 section .iar.init_table,
-					 section __DLIB_PERTHREAD,				 	 
-					 block CPP_INIT,
-					 section .mdns.data,
-					 section .mdns.text
-					};
+                    block SHT$$INIT_ARRAY };
+define block .ram.data with fixed order{ section .data*,
+                     section DATA,
+                     section .iar.init_table,
+                     section __DLIB_PERTHREAD,
+                     block CPP_INIT,
+                     section .mdns.data,
+                     section .mdns.text
+                    };
 define block .ram.text with fixed order{ section .image2.ram.text*,
-					}; 
+                    };
 define block IMAGE2 with fixed order {  block .ram_image2.entry,
-					block .ram.data,  
-					block .ram.text,  
-					};
+                    block .ram.data,
+                    block .ram.text,
+                    };
 define block .ram_image2.bss with fixed order{ section .bss*,
                                         section COMMON,
                                       };
 define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
 define block .ram_heap.data with fixed order{ section .bfsram.data* };
-place in BD_RAM_region  { readwrite, 
-					block IMAGE2,
-					block .ram_image2.bss,
-					block .ram_image2.skb.bss,
-					block .ram_heap.data,
-					section .heap.stdlib,	
+place in BD_RAM_region  { readwrite,
+                    block IMAGE2,
+                    block .ram_image2.bss,
+                    block .ram_image2.skb.bss,
+                    block .ram_heap.data,
+                    section .heap.stdlib,
                     last block HEAP,
-					};
+                    };
 /****************************************
  * XIP BOOT Section config                *
  ****************************************/
@@ -149,8 +149,8 @@ keep { section .flashboot.text* };
 define block .xip_image1.text with fixed order{ section .flashboot.text* };
 define block Bootloader with fixed order { section LOADER };
 place at start of XIP_BOOT_region   {   block Bootloader,
-					readwrite,
-					 block .xip_image1.text };
+                    readwrite,
+                     block .xip_image1.text };
 /****************************************
  * XIP OTA1 Section config                *
  ****************************************/
@@ -158,30 +158,30 @@ keep { section FSymTab };
 keep { section VSymTab };
 keep { section .rti_fn* };
 define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
-						section .text*,
-						section .rodata*,
-						section .debug_trace,
-						section CODE,
-						section Veneer, // object startup.o,
-						section FSymTab,
-						section VSymTab,
-						section .rti_fn*,
-						};
-place at start of  XIP_OTA1_region   {  readwrite, 
-					  block .xip_image2.text };
+                        section .text*,
+                        section .rodata*,
+                        section .debug_trace,
+                        section CODE,
+                        section Veneer, // object startup.o,
+                        section FSymTab,
+                        section VSymTab,
+                        section .rti_fn*,
+                        };
+place at start of  XIP_OTA1_region   {  readwrite,
+                      block .xip_image2.text };
 /****************************************
  * RDP Section config                    *
  ****************************************/
-keep {	section .rdp.ram.text* };
-keep {	section .rdp.ram.data* };
+keep {  section .rdp.ram.text* };
+keep {  section .rdp.ram.data* };
 define block .RDP_RAM with fixed order {
-	section .rdp.ram.text*,
-	section .rdp.ram.data* };
+    section .rdp.ram.text*,
+    section .rdp.ram.data* };
 place at start of  RDP_RAM_region{
-	readwrite, 
-	block .RDP_RAM };
-define exported symbol __ram_start_table_start__= 0x10002000;	// use in rom
-define exported symbol __image1_validate_code__= 0x10002018;	// needed by ram code
-define exported symbol __rom_top_4k_start_= 0x1003F000;	// needed by ram code
+    readwrite,
+    block .RDP_RAM };
+define exported symbol __ram_start_table_start__= 0x10002000;   // use in rom
+define exported symbol __image1_validate_code__= 0x10002018;    // needed by ram code
+define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
 define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
-define exported symbol boot_export_symbol = 0x10002020;  
+define exported symbol boot_export_symbol = 0x10002020;

bsp/amebaz/rom_symbol_v01_iar.icf

@@ -1,1424 +1,1424 @@
-define exported symbol __vectors_table = 0x0;
-define exported symbol Reset_Handler = 0x101;
-define exported symbol NMI_Handler = 0x115;
-/*define exported symbol HardFault_Handler = 0x119;*/
-define exported symbol MemManage_Handler = 0x12d;
-define exported symbol BusFault_Handler = 0x131;
-define exported symbol UsageFault_Handler = 0x135;
-define exported symbol VSprintf = 0x201;
-define exported symbol DiagPrintf = 0x4dd;
-define exported symbol DiagSPrintf = 0x509;
-define exported symbol DiagSnPrintf = 0x535;
-define exported symbol prvDiagPrintf = 0x7ed;
-define exported symbol prvDiagSPrintf = 0x821;
-define exported symbol UARTIMG_Write = 0x855;
-define exported symbol UARTIMG_Download = 0x901;
-define exported symbol _memcmp = 0x991;
-define exported symbol _memcpy = 0x9c5;
-define exported symbol _memset = 0xa7d;
-define exported symbol DumpForOneBytes = 0xae9;
-define exported symbol CmdRomHelp = 0xc69;
-define exported symbol CmdDumpWord = 0xccd;
-define exported symbol CmdWriteWord = 0xd7d;
-define exported symbol CmdFlash = 0xdd1;
-define exported symbol CmdEfuse = 0x12c1;
-define exported symbol CmdDumpByte = 0x1775;
-define exported symbol CmdDumpHalfWord = 0x17c9;
-define exported symbol CmdWriteByte = 0x1881;
-define exported symbol SramReadWriteCpy = 0x18c1;
-define exported symbol SramReadWriteTest = 0x19f9;
-define exported symbol CmdSRamTest = 0x1ac9;
-define exported symbol GetRomCmdNum = 0x1b59;
-define exported symbol Rand = 0x1b5d;
-define exported symbol Rand_Arc4 = 0x1bdd;
-define exported symbol RandBytes_Get = 0x1c0d;
-define exported symbol Isspace = 0x1c59;
-define exported symbol Strtoul = 0x1c6d;
-define exported symbol ArrayInitialize = 0x1d15;
-define exported symbol GetArgc = 0x1d29;
-define exported symbol GetArgv = 0x1d55;
-define exported symbol UartLogCmdExecute = 0x1db1;
-define exported symbol UartLogShowBackSpace = 0x1e49;
-define exported symbol UartLogRecallOldCmd = 0x1e7d;
-define exported symbol UartLogHistoryCmd = 0x1eb1;
-define exported symbol UartLogCmdChk = 0x1f2d;
-define exported symbol UartLogIrqHandle = 0x2035;
-define exported symbol RtlConsolInit = 0x2101;
-define exported symbol RtlConsolTaskRom = 0x218d;
-define exported symbol RtlExitConsol = 0x21b9;
-define exported symbol RtlConsolRom = 0x2205;
-define exported symbol BKUP_Write = 0x2249;
-define exported symbol BKUP_Read = 0x226d;
-define exported symbol BKUP_Set = 0x228d;
-define exported symbol BKUP_Clear = 0x22b9;
-define exported symbol NCO32K_Init = 0x22e9;
-define exported symbol EXT32K_Cmd = 0x2349;
-define exported symbol NCO8M_Init = 0x2365;
-define exported symbol NCO8M_Cmd = 0x23bd;
-define exported symbol ISO_Set = 0x23d9;
-define exported symbol PLL0_Set = 0x23f1;
-define exported symbol PLL1_Set = 0x2409;
-define exported symbol PLL2_Set = 0x2421;
-define exported symbol PLL3_Set = 0x2439;
-define exported symbol XTAL0_Set = 0x2451;
-define exported symbol XTAL1_Set = 0x2469;
-define exported symbol XTAL2_Set = 0x2481;
-define exported symbol XTAL_ClkGet = 0x2499;
-define exported symbol CPU_ClkSet = 0x24b1;
-define exported symbol CPU_ClkGet = 0x24c5;
-define exported symbol OSC32K_Calibration = 0x24e5;
-define exported symbol OSC32K_Cmd = 0x25f9;
-define exported symbol OSC8M_Get = 0x2631;
-define exported symbol rtl_cryptoEngine_SrcDesc_Show = 0x2641;
-define exported symbol rtl_cryptoEngine_info = 0x27f1;
-define exported symbol rtl_cryptoEngine_init = 0x2949;
-define exported symbol rtl_crypto_md5_init = 0x2975;
-define exported symbol rtl_crypto_md5_process = 0x29b1;
-define exported symbol rtl_crypto_md5 = 0x2a09;
-define exported symbol rtl_crypto_sha1_init = 0x2a2d;
-define exported symbol rtl_crypto_sha1_process = 0x2a69;
-define exported symbol rtl_crypto_sha1 = 0x2a9d;
-define exported symbol rtl_crypto_sha2_init = 0x2ac1;
-define exported symbol rtl_crypto_sha2_process = 0x2b15;
-define exported symbol rtl_crypto_sha2 = 0x2b4d;
-define exported symbol rtl_crypto_hmac_md5_init = 0x2b71;
-define exported symbol rtl_crypto_hmac_md5_process = 0x2bd1;
-define exported symbol rtl_crypto_hmac_md5 = 0x2c0d;
-define exported symbol rtl_crypto_hmac_sha1_init = 0x2c31;
-define exported symbol rtl_crypto_hmac_sha1_process = 0x2c91;
-define exported symbol rtl_crypto_hmac_sha1 = 0x2cc9;
-define exported symbol rtl_crypto_hmac_sha2_init = 0x2ced;
-define exported symbol rtl_crypto_hmac_sha2_process = 0x2d65;
-define exported symbol rtl_crypto_hmac_sha2 = 0x2da1;
-define exported symbol rtl_crypto_aes_cbc_init = 0x2dc5;
-define exported symbol rtl_crypto_aes_cbc_encrypt = 0x2dfd;
-define exported symbol rtl_crypto_aes_cbc_decrypt = 0x2e45;
-define exported symbol rtl_crypto_aes_ecb_init = 0x2e8d;
-define exported symbol rtl_crypto_aes_ecb_encrypt = 0x2ec5;
-define exported symbol rtl_crypto_aes_ecb_decrypt = 0x2ef5;
-define exported symbol rtl_crypto_aes_ctr_init = 0x2f25;
-define exported symbol rtl_crypto_aes_ctr_encrypt = 0x2f5d;
-define exported symbol rtl_crypto_aes_ctr_decrypt = 0x2f99;
-define exported symbol rtl_crypto_3des_cbc_init = 0x2fd5;
-define exported symbol rtl_crypto_3des_cbc_encrypt = 0x300d;
-define exported symbol rtl_crypto_3des_cbc_decrypt = 0x3055;
-define exported symbol rtl_crypto_3des_ecb_init = 0x309d;
-define exported symbol rtl_crypto_3des_ecb_encrypt = 0x30d5;
-define exported symbol rtl_crypto_3des_ecb_decrypt = 0x311d;
-define exported symbol rtl_crypto_des_cbc_init = 0x3165;
-define exported symbol rtl_crypto_des_cbc_encrypt = 0x319d;
-define exported symbol rtl_crypto_des_cbc_decrypt = 0x31f5;
-define exported symbol rtl_crypto_des_ecb_init = 0x324d;
-define exported symbol rtl_crypto_des_ecb_encrypt = 0x3285;
-define exported symbol rtl_crypto_des_ecb_decrypt = 0x32dd;
-define exported symbol SYSTIMER_Init = 0x3335;
-define exported symbol SYSTIMER_TickGet = 0x33a1;
-define exported symbol SYSTIMER_GetPassTime = 0x33c1;
-define exported symbol DelayNop = 0x3401;
-define exported symbol DelayUs = 0x3411;
-define exported symbol DelayMs = 0x346d;
-define exported symbol USOC_DongleSpecialCmd = 0x3481;
-define exported symbol USOC_DongleCmd = 0x35d9;
-define exported symbol USOC_DongleIsr = 0x35f9;
-define exported symbol USOC_SIE_INTConfig = 0x3621;
-define exported symbol USOC_SIE_INTClear = 0x3639;
-define exported symbol USOC_PHY_Write = 0x3645;
-define exported symbol USOC_PHY_Read = 0x3679;
-define exported symbol USOC_PHY_Autoload = 0x36c1;
-define exported symbol USOC_DongleInit = 0x37a5;
-define exported symbol EFUSE_USER_Read = 0x386d;
-define exported symbol EFUSE_USER1_Read = 0x3971;
-define exported symbol EFUSE_USER2_Read = 0x397d;
-define exported symbol EFUSE_USER3_Read = 0x3989;
-define exported symbol EFUSE_RemainLength = 0x3995;
-define exported symbol EFUSE_USER_Write = 0x3a21;
-define exported symbol EFUSE_USER1_Write = 0x3bb1;
-define exported symbol EFUSE_USER2_Write = 0x3bc1;
-define exported symbol EFUSE_USER3_Write = 0x3bd1;
-define exported symbol EFUSE_OTP_Read1B = 0x3be1;
-define exported symbol EFUSE_OTP_Write1B = 0x3c01;
-define exported symbol EFUSE_OTP_Read32B = 0x3c21;
-define exported symbol EFUSE_OTP_Write32B = 0x3c4d;
-define exported symbol EFUSE_RDP_EN = 0x3cad;
-define exported symbol EFUSE_RDP_KEY = 0x3ccd;
-define exported symbol EFUSE_OTF_KEY = 0x3cf9;
-define exported symbol EFUSE_JTAG_OFF = 0x3d25;
-define exported symbol PAD_DrvStrength = 0x3d45;
-define exported symbol PAD_PullCtrl = 0x3d75;
-define exported symbol Pinmux_Config = 0x3dc5;
-define exported symbol Pinmux_ConfigGet = 0x3dfd;
-define exported symbol Pinmux_Deinit = 0x3e19;
-define exported symbol PINMUX_UART0_Ctrl = 0x3e39;
-define exported symbol PINMUX_UART1_Ctrl = 0x3e81;
-define exported symbol PINMUX_UARTLOG_Ctrl = 0x3ea9;
-define exported symbol PINMUX_SPI0_Ctrl = 0x3ef9;
-define exported symbol PINMUX_SPI1_Ctrl = 0x3f8d;
-define exported symbol PINMUX_SPIF_Ctrl = 0x400d;
-define exported symbol PINMUX_I2C0_Ctrl = 0x406d;
-define exported symbol PINMUX_I2C1_Ctrl = 0x40e1;
-define exported symbol PINMUX_SDIOD_Ctrl = 0x4151;
-define exported symbol PINMUX_I2S0_Ctrl = 0x41e5;
-define exported symbol PINMUX_SWD_Ctrl = 0x4265;
-define exported symbol PINMUX_SWD_OFF = 0x42b5;
-define exported symbol PINMUX_SWD_REG = 0x42d9;
-define exported symbol PINMUX_Ctrl = 0x42fd;
-define exported symbol SOCPS_BackupCPUClk = 0x4391;
-define exported symbol SOCPS_RestoreCPUClk = 0x43b1;
-define exported symbol SOCPS_BootFromPS = 0x43d1;
-define exported symbol SOCPS_TrapPin = 0x43f1;
-define exported symbol SOCPS_ANACKSel = 0x4411;
-define exported symbol SOCPS_CLKCal = 0x442d;
-define exported symbol SOCPS_SetWakeEvent = 0x4485;
-define exported symbol SOCPS_ClearWakeEvent = 0x449d;
-define exported symbol SOCPS_WakePinsCtrl = 0x44a9;
-define exported symbol SOCPS_WakePinCtrl = 0x44d9;
-define exported symbol SOCPS_WakePinClear = 0x4529;
-define exported symbol SOCPS_GetANATimerParam = 0x4539;
-define exported symbol SOCPS_SetANATimer = 0x4575;
-define exported symbol SOCPS_SetReguWakepin = 0x45dd;
-define exported symbol SOCPS_SetReguTimer = 0x4605;
-define exported symbol SOCPS_PWROption = 0x46d9;
-define exported symbol SOCPS_PWROptionExt = 0x46e5;
-define exported symbol SOCPS_PWRMode = 0x46f9;
-define exported symbol SOCPS_SNZMode = 0x4721;
-define exported symbol SOCPS_DeepStandby = 0x473d;
-define exported symbol SOCPS_DeepSleep = 0x4791;
-define exported symbol SDIO_StructInit = 0x47d5;
-define exported symbol SDIO_Init = 0x47f1;
-define exported symbol SDIO_INTClear = 0x486d;
-define exported symbol SDIO_INTConfig = 0x487d;
-define exported symbol SDIO_RPWM1_Get = 0x4895;
-define exported symbol SDIO_RPWM2_Get = 0x48a1;
-define exported symbol SDIO_CPWM1_Set = 0x48ad;
-define exported symbol SDIO_CPWM2_Set = 0x48c1;
-define exported symbol SDIO_RXBD_RPTR_Get = 0x48dd;
-define exported symbol SDIO_RXBD_WPTR_Set = 0x48e9;
-define exported symbol SDIO_TXBD_WPTR_Get = 0x48f5;
-define exported symbol SDIO_TXBD_RPTR_Set = 0x4901;
-define exported symbol SDIO_DMA_Reset = 0x490d;
-define exported symbol BOOT_ROM_Simulation = 0x4919;
-define exported symbol USOC_BOOT_TXBD_Proc = 0x491d;
-define exported symbol USOC_BOOT_Init = 0x4a3d;
-define exported symbol USB_Boot_ROM = 0x4aa9;
-define exported symbol USOC_CH_Cmd = 0x4b59;
-define exported symbol USOC_Cmd = 0x4bb1;
-define exported symbol USOC_PHY_Cmd = 0x4bf5;
-define exported symbol USOC_MODE_Cfg = 0x4c09;
-define exported symbol USOC_TXBD_SWIDX_Cfg = 0x4c25;
-define exported symbol USOC_TXBD_SWIDX_Get = 0x4c2d;
-define exported symbol USOC_TXBD_HWIDX_Get = 0x4c35;
-define exported symbol USOC_RXBD_HWIDX_Get = 0x4c3d;
-define exported symbol USOC_RXBD_SWIDX_Cfg = 0x4c45;
-define exported symbol USOC_RXBD_SWIDX_Get = 0x4c4d;
-define exported symbol USOC_StructInit = 0x4c55;
-define exported symbol USOC_Init = 0x4c85;
-define exported symbol USOC_SW_RST = 0x4d7d;
-define exported symbol USOC_INTCfg = 0x4d91;
-define exported symbol USOC_INTClr = 0x4d95;
-define exported symbol USOC_INTGet = 0x4d9d;
-define exported symbol USOC_MIT_Cfg = 0x4da1;
-define exported symbol USOC_TXSTUCK_Cfg = 0x4dc5;
-define exported symbol USOC_RXSTUCK_Cfg = 0x4de9;
-define exported symbol USOC_POWER_On = 0x4e0d;
-define exported symbol ADC_RXGDMA_Init = 0x4e9d;
-define exported symbol ADC_SetAudio = 0x4f45;
-define exported symbol ADC_SetAnalog = 0x4f61;
-define exported symbol ADC_Cmd = 0x4fbd;
-define exported symbol ADC_INTConfig = 0x5031;
-define exported symbol ADC_SetOneShot = 0x5049;
-define exported symbol ADC_SetComp = 0x50fd;
-define exported symbol ADC_INTClear = 0x517d;
-define exported symbol ADC_INTClearPendingBits = 0x5189;
-define exported symbol ADC_GetISR = 0x5195;
-define exported symbol ADC_Read = 0x51a1;
-define exported symbol ADC_ReceiveBuf = 0x51ad;
-define exported symbol ADC_InitStruct = 0x5205;
-define exported symbol ADC_Init = 0x524d;
-define exported symbol BOOT_ROM_ShowBuildInfo = 0x52ed;
-define exported symbol BOOT_ROM_OTFCheck = 0x5335;
-define exported symbol BOOT_ROM_InitFlash = 0x5345;
-define exported symbol BOOT_ROM_FromFlash = 0x5405;
-define exported symbol BOOT_ROM_InitUsb = 0x5511;
-define exported symbol BOOT_ROM_Process = 0x553d;
-define exported symbol BOOT_ROM_InitDebugFlg = 0x5605;
-define exported symbol HalResetVsr = 0x5639;
-define exported symbol Cache_Enable = 0x5811;
-define exported symbol Cache_Flush = 0x5831;
-define exported symbol Cache_Debug = 0x5851;
-define exported symbol CRYPTO_AlignToBe32 = 0x58bd;
-define exported symbol CRYPTO_MemDump = 0x58d5;
-define exported symbol CRYPTO_GetAESKey = 0x599d;
-define exported symbol CRYPTO_SetAESKey = 0x5cb5;
-define exported symbol CRYPTO_SetSecurityMode = 0x5d29;
-define exported symbol CRYPTO_Init = 0x5f5d;
-define exported symbol CRYPTO_DeInit = 0x60b9;
-define exported symbol CRYPTO_Reset = 0x6101;
-define exported symbol CRYPTO_Process = 0x6129;
-define exported symbol CRYPTO_CipherInit = 0x6a11;
-define exported symbol CRYPTO_CipherEncrypt = 0x6a35;
-define exported symbol CRYPTO_CipherDecrypt = 0x6a61;
-define exported symbol CRYPTO_SetCheckSumEn = 0x6a95;
-define exported symbol CRYPTO_GetCheckSumData = 0x6ab1;
-define exported symbol LOGUART_StructInit = 0x6abd;
-define exported symbol LOGUART_Init = 0x6ad5;
-define exported symbol LOGUART_PutChar = 0x6b15;
-define exported symbol LOGUART_GetChar = 0x6b49;
-define exported symbol LOGUART_GetIMR = 0x6b65;
-define exported symbol LOGUART_SetIMR = 0x6b71;
-define exported symbol LOGUART_WaitBusy = 0x6b7d;
-define exported symbol DIAG_UartInit = 0x6b9d;
-define exported symbol DIAG_UartReInit = 0x6c25;
-define exported symbol EFUSE_PowerSwitchROM = 0x6c49;
-define exported symbol EFUSE_OneByteReadROM = 0x6d65;
-define exported symbol EFUSE_OneByteWriteROM = 0x6e0d;
-define exported symbol EFUSE_PG_Packet = 0x6e29;
-define exported symbol EFUSE_LogicalMap_Read = 0x7091;
-define exported symbol EFUSE_LogicalMap_Write = 0x71f5;
-define exported symbol FLASH_SetSpiMode = 0x73dd;
-define exported symbol FLASH_RxCmd = 0x7465;
-define exported symbol FLASH_WaitBusy = 0x74cd;
-define exported symbol FLASH_RxData = 0x754d;
-define exported symbol FLASH_TxCmd = 0x75cd;
-define exported symbol FLASH_WriteEn = 0x763d;
-define exported symbol FLASH_TxData12B = 0x7661;
-define exported symbol FLASH_SetStatus = 0x7735;
-define exported symbol FLASH_Erase = 0x7755;
-define exported symbol FLASH_DeepPowerDown = 0x77f5;
-define exported symbol FLASH_SetStatusBits = 0x784d;
-define exported symbol FLASH_Calibration = 0x791d;
-define exported symbol FLASH_StructInit_Micron = 0x7a65;
-define exported symbol FLASH_StructInit_MXIC = 0x7af5;
-define exported symbol FLASH_StructInit_GD = 0x7b81;
-define exported symbol FLASH_StructInit = 0x7c11;
-define exported symbol FLASH_Init = 0x7ca1;
-define exported symbol FLASH_ClockDiv = 0x7d15;
-define exported symbol FLASH_CalibrationInit = 0x7d99;
-define exported symbol FLASH_Calibration500MPSCmd = 0x7db1;
-define exported symbol FLASH_CalibrationPhase = 0x7dcd;
-define exported symbol FLASH_CalibrationPhaseIdx = 0x7e59;
-define exported symbol FLASH_CalibrationNewCmd = 0x7e6d;
-define exported symbol FLASH_CalibrationNew = 0x7ea9;
-define exported symbol GDMA_StructInit = 0x80dd;
-define exported symbol GDMA_SetLLP = 0x80f9;
-define exported symbol GDMA_ClearINTPendingBit = 0x8191;
-define exported symbol GDMA_ClearINT = 0x81d5;
-define exported symbol GDMA_INTConfig = 0x8211;
-define exported symbol GDMA_Cmd = 0x8259;
-define exported symbol GDMA_Init = 0x828d;
-define exported symbol GDMA_ChCleanAutoReload = 0x83c1;
-define exported symbol GDMA_SetSrcAddr = 0x83f9;
-define exported symbol GDMA_GetSrcAddr = 0x8411;
-define exported symbol GDMA_GetDstAddr = 0x8429;
-define exported symbol GDMA_SetDstAddr = 0x843d;
-define exported symbol GDMA_SetBlkSize = 0x8459;
-define exported symbol GDMA_GetBlkSize = 0x8489;
-define exported symbol GDMA_ChnlRegister = 0x84a1;
-define exported symbol GDMA_ChnlUnRegister = 0x8529;
-define exported symbol GDMA_ChnlAlloc = 0x8591;
-define exported symbol GDMA_ChnlFree = 0x8615;
-define exported symbol GPIO_INTMode = 0x864d;
-define exported symbol GPIO_INTConfig = 0x86e5;
-define exported symbol GPIO_INTHandler = 0x8725;
-define exported symbol GPIO_Direction = 0x8771;
-define exported symbol GPIO_Init = 0x87a1;
-define exported symbol GPIO_DeInit = 0x886d;
-define exported symbol GPIO_ReadDataBit = 0x88c9;
-define exported symbol GPIO_WriteBit = 0x88ed;
-define exported symbol GPIO_PortDirection = 0x891d;
-define exported symbol GPIO_PortRead = 0x893d;
-define exported symbol GPIO_PortWrite = 0x894d;
-define exported symbol GPIO_UserRegIrq = 0x8969;
-define exported symbol I2C_StructInit = 0x899d;
-define exported symbol I2C_SetSpeed = 0x89e5;
-define exported symbol I2C_SetSlaveAddress = 0x8b3d;
-define exported symbol I2C_CheckFlagState = 0x8b79;
-define exported symbol I2C_INTConfig = 0x8bad;
-define exported symbol I2C_ClearINT = 0x8be5;
-define exported symbol I2C_ClearAllINT = 0x8c85;
-define exported symbol I2C_Init = 0x8cad;
-define exported symbol I2C_GetRawINT = 0x8dc9;
-define exported symbol I2C_GetINT = 0x8df1;
-define exported symbol I2C_MasterSendNullData = 0x8e19;
-define exported symbol I2C_MasterSend = 0x8e65;
-define exported symbol I2C_SlaveSend = 0x8ead;
-define exported symbol I2C_ReceiveData = 0x8ed9;
-define exported symbol I2C_MasterWrite = 0x8f05;
-define exported symbol I2C_MasterReadDW = 0x8f89;
-define exported symbol I2C_MasterRead = 0x9019;
-define exported symbol I2C_SlaveWrite = 0x9089;
-define exported symbol I2C_SlaveRead = 0x90f1;
-define exported symbol I2C_MasterRepeatRead = 0x9141;
-define exported symbol I2C_Cmd = 0x91c1;
-define exported symbol I2C_PinMuxInit = 0x91fd;
-define exported symbol I2C_PinMuxDeInit = 0x9255;
-define exported symbol I2C_DMAControl = 0x92ad;
-define exported symbol I2C_DmaMode1Config = 0x92e9;
-define exported symbol I2C_DmaMode2Config = 0x9331;
-define exported symbol I2C_TXGDMA_Init = 0x9375;
-define exported symbol I2C_RXGDMA_Init = 0x9459;
-define exported symbol I2C_Sleep_Cmd = 0x9521;
-define exported symbol I2C_WakeUp = 0x95a1;
-define exported symbol I2S_StructInit = 0x95e9;
-define exported symbol I2S_Cmd = 0x9611;
-define exported symbol I2S_TxDmaCmd = 0x962d;
-define exported symbol I2S_RxDmaCmd = 0x9641;
-define exported symbol I2S_INTConfig = 0x9655;
-define exported symbol I2S_INTClear = 0x965d;
-define exported symbol I2S_INTClearAll = 0x9665;
-define exported symbol I2S_Init = 0x9671;
-define exported symbol I2S_ISRGet = 0x97a9;
-define exported symbol I2S_SetRate = 0x97b5;
-define exported symbol I2S_SetWordLen = 0x9811;
-define exported symbol I2S_SetChNum = 0x9839;
-define exported symbol I2S_SetPageNum = 0x9861;
-define exported symbol I2S_SetPageSize = 0x9895;
-define exported symbol I2S_GetPageSize = 0x98a9;
-define exported symbol I2S_SetDirection = 0x98b5;
-define exported symbol I2S_SetDMABuf = 0x98dd;
-define exported symbol I2S_TxPageBusy = 0x9905;
-define exported symbol I2S_GetTxPage = 0x9911;
-define exported symbol I2S_GetRxPage = 0x991d;
-define exported symbol I2S_SetTxPageAddr = 0x9929;
-define exported symbol I2S_GetTxPageAddr = 0x9939;
-define exported symbol I2S_SetRxPageAddr = 0x9949;
-define exported symbol I2S_GetRxPageAddr = 0x9959;
-define exported symbol I2S_TxPageDMA_EN = 0x9969;
-define exported symbol I2S_RxPageDMA_EN = 0x998d;
-define exported symbol io_assert_failed = 0x99d9;
-define exported symbol OTF_init = 0x99fd;
-define exported symbol OTF_Cmd = 0x9a79;
-define exported symbol OTF_Mask = 0x9a8d;
-define exported symbol KEY_Request = 0x9add;
-define exported symbol RDP_EN_Request = 0x9b21;
-define exported symbol RCC_PeriphClockCmd = 0x9b65;
-define exported symbol FUNC_HCI_COM = 0x9c95;
-define exported symbol RTC_ByteToBcd2 = 0x9cad;
-define exported symbol RTC_Bcd2ToByte = 0x9cc9;
-define exported symbol RTC_ClokSource = 0x9cdd;
-define exported symbol RTC_EnterInitMode = 0x9d19;
-define exported symbol RTC_ExitInitMode = 0x9d51;
-define exported symbol RTC_WaitForSynchro = 0x9d61;
-define exported symbol RTC_BypassShadowCmd = 0x9da9;
-define exported symbol RTC_StructInit = 0x9dd9;
-define exported symbol RTC_Init = 0x9de5;
-define exported symbol RTC_TimeStructInit = 0x9e7d;
-define exported symbol RTC_SetTime = 0x9e8d;
-define exported symbol RTC_GetTime = 0x9ff9;
-define exported symbol RTC_SetAlarm = 0xa051;
-define exported symbol RTC_AlarmStructInit = 0xa211;
-define exported symbol RTC_GetAlarm = 0xa231;
-define exported symbol RTC_AlarmCmd = 0xa2a1;
-define exported symbol RTC_AlarmClear = 0xa2f5;
-define exported symbol RTC_DayLightSavingConfig = 0xa305;
-define exported symbol RTC_GetStoreOperation = 0xa355;
-define exported symbol RTC_OutputConfig = 0xa365;
-define exported symbol RTC_SmoothCalibConfig = 0xa39d;
-define exported symbol SDIO_IsTimeout = 0xa459;
-define exported symbol SDIOB_Init = 0xa481;
-define exported symbol SDIOB_INTConfig = 0xa575;
-define exported symbol SDIOB_DeInit = 0xa591;
-define exported symbol SDIOB_H2C_WriteMem = 0xa5d9;
-define exported symbol SDIOB_H2C_SetMem = 0xa605;
-define exported symbol SDIOB_H2C_DataHandle = 0xa631;
-define exported symbol SDIOB_H2C_DataReady = 0xa73d;
-define exported symbol SDIOB_IRQ_Handler_BH = 0xa80d;
-define exported symbol SDIOB_H2C_Task = 0xa8c9;
-define exported symbol SDIO_Boot_Up = 0xa8e5;
-define exported symbol SPI_DmaInit = 0xa91d;
-define exported symbol SPI_DataHandle = 0xa9d1;
-define exported symbol SPI_Boot_DmaRxIrqHandle = 0xaa01;
-define exported symbol SPI_Boot_ROM = 0xaa5d;
-define exported symbol SSI_StructInit = 0xabbd;
-define exported symbol SSI_Cmd = 0xabf5;
-define exported symbol SSI_INTConfig = 0xac09;
-define exported symbol SSI_SetSclkPolarity = 0xac19;
-define exported symbol SSI_SetSclkPhase = 0xac3d;
-define exported symbol SSI_SetDataFrameSize = 0xac61;
-define exported symbol SSI_SetReadLen = 0xac81;
-define exported symbol SSI_SetBaudDiv = 0xacb1;
-define exported symbol SSI_SetBaud = 0xaccd;
-define exported symbol SSI_SetDmaEnable = 0xad2d;
-define exported symbol SSI_SetDmaLevel = 0xad41;
-define exported symbol SSI_SetIsrClean = 0xad49;
-define exported symbol SSI_WriteData = 0xad65;
-define exported symbol SSI_SetRxFifoLevel = 0xad6d;
-define exported symbol SSI_SetTxFifoLevel = 0xad71;
-define exported symbol SSI_ReadData = 0xad75;
-define exported symbol SSI_GetRxCount = 0xad79;
-define exported symbol SSI_GetTxCount = 0xad81;
-define exported symbol SSI_GetStatus = 0xad89;
-define exported symbol SSI_Writeable = 0xad8d;
-define exported symbol SSI_Readable = 0xad9d;
-define exported symbol SSI_GetDataFrameSize = 0xadad;
-define exported symbol SSI_TXGDMA_Init = 0xadb9;
-define exported symbol SSI_RXGDMA_Init = 0xaef9;
-define exported symbol SSI_ReceiveData = 0xb021;
-define exported symbol SSI_SendData = 0xb0b9;
-define exported symbol SSI_Busy = 0xb165;
-define exported symbol SSI_SetSlaveEnable = 0xb175;
-define exported symbol SSI_Init = 0xb1ad;
-define exported symbol SSI_GetIsr = 0xb235;
-define exported symbol SSI_GetRawIsr = 0xb239;
-define exported symbol SSI_GetSlaveEnable = 0xb23d;
-define exported symbol SSI_PinmuxInit = 0xb241;
-define exported symbol SSI_PinmuxDeInit = 0xb2a9;
-define exported symbol SYSCFG0_Get = 0xb311;
-define exported symbol SYSCFG0_CUTVersion = 0xb31d;
-define exported symbol SYSCFG0_BDOption = 0xb32d;
-define exported symbol SYSCFG1_Get = 0xb33d;
-define exported symbol SYSCFG1_AutoLoadDone = 0xb349;
-define exported symbol SYSCFG1_TRP_LDOMode = 0xb359;
-define exported symbol SYSCFG1_TRP_UARTImage = 0xb369;
-define exported symbol SYSCFG1_TRP_ICFG = 0xb37d;
-define exported symbol SYSCFG2_Get = 0xb389;
-define exported symbol SYSCFG2_ROMINFO_Get = 0xb395;
-define exported symbol SYSCFG2_ROMINFO_Set = 0xb3a1;
-define exported symbol RTIM_TimeBaseStructInit = 0xb3b5;
-define exported symbol RTIM_Cmd = 0xb3cd;
-define exported symbol RTIM_GetCount = 0xb42d;
-define exported symbol RTIM_UpdateDisableConfig = 0xb475;
-define exported symbol RTIM_ARRPreloadConfig = 0xb4c5;
-define exported symbol RTIM_UpdateRequestConfig = 0xb515;
-define exported symbol RTIM_PrescalerConfig = 0xb575;
-define exported symbol RTIM_GenerateEvent = 0xb5a1;
-define exported symbol RTIM_ChangePeriod = 0xb5f9;
-define exported symbol RTIM_Reset = 0xb64d;
-define exported symbol RTIM_CCStructInit = 0xb68d;
-define exported symbol RTIM_CCxInit = 0xb6a1;
-define exported symbol RTIM_CCRxMode = 0xb749;
-define exported symbol RTIM_CCRxSet = 0xb785;
-define exported symbol RTIM_CCRxGet = 0xb7dd;
-define exported symbol RTIM_OCxPreloadConfig = 0xb80d;
-define exported symbol RTIM_CCxPolarityConfig = 0xb85d;
-define exported symbol RTIM_CCxCmd = 0xb8ad;
-define exported symbol RTIM_SetOnePulseOutputMode = 0xb901;
-define exported symbol RTIM_DMACmd = 0xb959;
-define exported symbol RTIM_TXGDMA_Init = 0xb9a9;
-define exported symbol RTIM_RXGDMA_Init = 0xba5d;
-define exported symbol RTIM_INTConfig = 0xbb3d;
-define exported symbol RTIM_INTClear = 0xbba9;
-define exported symbol RTIM_TimeBaseInit = 0xbbed;
-define exported symbol RTIM_DeInit = 0xbced;
-define exported symbol RTIM_INTClearPendingBit = 0xbd41;
-define exported symbol RTIM_GetFlagStatus = 0xbd81;
-define exported symbol RTIM_GetINTStatus = 0xbded;
-define exported symbol UART_DeInit = 0xbe61;
-define exported symbol UART_StructInit = 0xbe69;
-define exported symbol UART_BaudParaGet = 0xbe81;
-define exported symbol UART_BaudParaGetFull = 0xbec9;
-define exported symbol UART_SetBaud = 0xbf01;
-define exported symbol UART_SetBaudExt = 0xbf71;
-define exported symbol UART_SetRxLevel = 0xbfc1;
-define exported symbol UART_RxCmd = 0xbfe9;
-define exported symbol UART_Writable = 0xbffd;
-define exported symbol UART_Readable = 0xc005;
-define exported symbol UART_CharPut = 0xc00d;
-define exported symbol UART_CharGet = 0xc011;
-define exported symbol UART_ReceiveData = 0xc019;
-define exported symbol UART_SendData = 0xc041;
-define exported symbol UART_ReceiveDataTO = 0xc069;
-define exported symbol UART_SendDataTO = 0xc0a9;
-define exported symbol UART_RxByteCntClear = 0xc0e9;
-define exported symbol UART_RxByteCntGet = 0xc0f5;
-define exported symbol UART_BreakCtl = 0xc0fd;
-define exported symbol UART_ClearRxFifo = 0xc111;
-define exported symbol UART_Init = 0xc135;
-define exported symbol UART_ClearTxFifo = 0xc1d1;
-define exported symbol UART_INTConfig = 0xc1dd;
-define exported symbol UART_IntStatus = 0xc1ed;
-define exported symbol UART_ModemStatusGet = 0xc1f1;
-define exported symbol UART_LineStatusGet = 0xc1f5;
-define exported symbol UART_WaitBusy = 0xc1f9;
-define exported symbol UART_PinMuxInit = 0xc221;
-define exported symbol UART_PinMuxDeinit = 0xc289;
-define exported symbol UART_TXDMAConfig = 0xc2f1;
-define exported symbol UART_RXDMAConfig = 0xc301;
-define exported symbol UART_TXDMACmd = 0xc315;
-define exported symbol UART_RXDMACmd = 0xc329;
-define exported symbol UART_TXGDMA_Init = 0xc33d;
-define exported symbol UART_RXGDMA_Init = 0xc425;
-define exported symbol UART_LPRxStructInit = 0xc501;
-define exported symbol UART_LPRxInit = 0xc50d;
-define exported symbol UART_LPRxBaudSet = 0xc575;
-define exported symbol UART_LPRxMonitorCmd = 0xc5f1;
-define exported symbol UART_LPRxpathSet = 0xc62d;
-define exported symbol UART_LPRxIPClockSet = 0xc641;
-define exported symbol UART_LPRxCmd = 0xc6b1;
-define exported symbol UART_LPRxMonBaudCtrlRegGet = 0xc6c5;
-define exported symbol UART_LPRxMonitorSatusGet = 0xc6c9;
-define exported symbol UART_IrDAStructInit = 0xc6cd;
-define exported symbol UART_IrDAInit = 0xc6e5;
-define exported symbol UART_IrDACmd = 0xc7bd;
-define exported symbol INT_SysOn = 0xc7d1;
-define exported symbol INT_Wdg = 0xc811;
-define exported symbol INT_Timer0 = 0xc855;
-define exported symbol INT_Timer1 = 0xc899;
-define exported symbol INT_Timer2 = 0xc8dd;
-define exported symbol INT_Timer3 = 0xc921;
-define exported symbol INT_SPI0 = 0xc965;
-define exported symbol INT_GPIO = 0xc9a9;
-define exported symbol INT_Uart0 = 0xc9ed;
-define exported symbol INT_SPIFlash = 0xca31;
-define exported symbol INT_Uart1 = 0xca75;
-define exported symbol INT_Timer4 = 0xcab9;
-define exported symbol INT_I2S0 = 0xcafd;
-define exported symbol INT_Timer5 = 0xcb41;
-define exported symbol INT_WlDma = 0xcb85;
-define exported symbol INT_WlProtocol = 0xcbc9;
-define exported symbol INT_IPSEC = 0xcc0d;
-define exported symbol INT_SPI1 = 0xcc51;
-define exported symbol INT_Peripheral = 0xcc95;
-define exported symbol INT_Gdma0Ch0 = 0xccd9;
-define exported symbol INT_Gdma0Ch1 = 0xcd1d;
-define exported symbol INT_Gdma0Ch2 = 0xcd61;
-define exported symbol INT_Gdma0Ch3 = 0xcda5;
-define exported symbol INT_Gdma0Ch4 = 0xcde9;
-define exported symbol INT_Gdma0Ch5 = 0xce2d;
-define exported symbol INT_I2C0 = 0xce71;
-define exported symbol INT_I2C1 = 0xceb5;
-define exported symbol INT_Uartlog = 0xcef9;
-define exported symbol INT_ADC = 0xcf3d;
-define exported symbol INT_RDP = 0xcf81;
-define exported symbol INT_RTC = 0xcfc5;
-define exported symbol INT_Gdma1Ch0 = 0xd009;
-define exported symbol INT_Gdma1Ch1 = 0xd051;
-define exported symbol INT_Gdma1Ch2 = 0xd099;
-define exported symbol INT_Gdma1Ch3 = 0xd0e1;
-define exported symbol INT_Gdma1Ch4 = 0xd129;
-define exported symbol INT_Gdma1Ch5 = 0xd171;
-define exported symbol INT_USB = 0xd1b9;
-define exported symbol INT_RXI300 = 0xd201;
-define exported symbol INT_USB_SIE = 0xd249;
-define exported symbol INT_SdioD = 0xd291;
-define exported symbol INT_NMI = 0xd2d1;
-define exported symbol INT_HardFault = 0xd305;
-define exported symbol INT_MemManage = 0xd4b5;
-define exported symbol INT_BusFault = 0xd4d5;
-define exported symbol INT_UsageFault = 0xd4f5;
-define exported symbol VECTOR_TableInit = 0xd515;
-define exported symbol VECTOR_TableInitForOS = 0xd6c5;
-define exported symbol VECTOR_IrqRegister = 0xd6d5;
-define exported symbol VECTOR_IrqUnRegister = 0xd6f9;
-define exported symbol VECTOR_IrqEn = 0xd715;
-define exported symbol VECTOR_IrqDis = 0xd765;
-define exported symbol WDG_Scalar = 0xd7a1;
-define exported symbol WDG_Init = 0xd7e1;
-define exported symbol WDG_IrqClear = 0xd7fd;
-define exported symbol WDG_IrqInit = 0xd80d;
-define exported symbol WDG_Cmd = 0xd83d;
-define exported symbol WDG_Refresh = 0xd85d;
-define exported symbol _strncpy = 0xd86d;
-define exported symbol _strcpy = 0xd889;
-define exported symbol prvStrCpy = 0xd899;
-define exported symbol _strlen = 0xd8b1;
-define exported symbol _strnlen = 0xd8c9;
-define exported symbol prvStrLen = 0xd8fd;
-define exported symbol _strcmp = 0xd919;
-define exported symbol _strncmp = 0xd939;
-define exported symbol prvStrCmp = 0xd985;
-define exported symbol StrUpr = 0xd9b5;
-define exported symbol prvAtoi = 0xd9d1;
-define exported symbol prvStrtok = 0xda29;
-define exported symbol prvStrStr = 0xda81;
-define exported symbol _strsep = 0xdab9;
-define exported symbol skip_spaces = 0xdaf5;
-define exported symbol skip_atoi = 0xdb11;
-define exported symbol _parse_integer_fixup_radix = 0xdb49;
-define exported symbol _parse_integer = 0xdb9d;
-define exported symbol simple_strtoull = 0xdc01;
-define exported symbol simple_strtoll = 0xdc21;
-define exported symbol simple_strtoul = 0xdc41;
-define exported symbol simple_strtol = 0xdc49;
-define exported symbol _vsscanf = 0xdc61;
-define exported symbol _sscanf = 0xe1c9;
-define exported symbol div_u64 = 0xe1e5;
-define exported symbol div_s64 = 0xe1ed;
-define exported symbol div_u64_rem = 0xe1f5;
-define exported symbol div_s64_rem = 0xe205;
-define exported symbol _strpbrk = 0xe215;
-define exported symbol _strchr = 0xe241;
-define exported symbol COMMPORT_GET_T = 0xe259;
-define exported symbol COMMPORT_CLEAN_RX = 0xe289;
-define exported symbol xModemDebugInit = 0xe2a5;
-define exported symbol xModemDebug = 0xe2dd;
-define exported symbol xModemInquiry = 0xe315;
-define exported symbol xModemGetFirst = 0xe339;
-define exported symbol xModemGetOthers = 0xe45d;
-define exported symbol xModemRxFrame = 0xe691;
-define exported symbol xModemHandshake = 0xe6d5;
-define exported symbol xModemRxBuffer = 0xe945;
-define exported symbol xmodem_log_close = 0xe9f5;
-define exported symbol xmodem_log_open = 0xea01;
-define exported symbol xmodem_uart_init = 0xea39;
-define exported symbol xmodem_uart_deinit = 0xeb25;
-define exported symbol xmodem_uart_port_init = 0xeb35;
-define exported symbol xmodem_uart_port_deinit = 0xeb99;
-define exported symbol xmodem_uart_readable = 0xebdd;
-define exported symbol xmodem_uart_writable = 0xebf5;
-define exported symbol xmodem_uart_getc = 0xec0d;
-define exported symbol xmodem_uart_putc = 0xec35;
-define exported symbol xmodem_uart_putdata = 0xec49;
-define exported symbol aes_set_key = 0xec65;
-define exported symbol aes_encrypt = 0xf021;
-define exported symbol aes_decrypt = 0x10171;
-define exported symbol AES_WRAP = 0x112b1;
-define exported symbol AES_UnWRAP = 0x113fd;
-define exported symbol crc32_get = 0x11549;
-define exported symbol arc4_byte = 0x1157d;
-define exported symbol rt_arc4_init = 0x115a5;
-define exported symbol rt_arc4_crypt = 0x115e9;
-define exported symbol rt_md5_init = 0x11df5;
-define exported symbol rt_md5_append = 0x11e25;
-define exported symbol rt_md5_final = 0x11ec9;
-define exported symbol rt_md5_hmac = 0x11f21;
-define exported symbol RC4 = 0x12061;
-define exported symbol RC4_set_key = 0x1238d;
-define exported symbol ROM_WIFI_ReadPowerValue = 0x1246d;
-define exported symbol ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d;
-define exported symbol ROM_WIFI_8051Reset = 0x125c5;
-define exported symbol ROM_WIFI_FWDownloadEnable = 0x125dd;
-define exported symbol ROM_WIFI_BlockWrite = 0x12619;
-define exported symbol ROM_WIFI_PageWrite = 0x12661;
-define exported symbol ROM_WIFI_FillDummy = 0x12685;
-define exported symbol ROM_WIFI_WriteFW = 0x126b1;
-define exported symbol ROM_WIFI_FWFreeToGo = 0x1275d;
-define exported symbol ROM_WIFI_InitLLTTable = 0x127f9;
-define exported symbol ROM_WIFI_GetChnlGroup = 0x12879;
-define exported symbol ROM_WIFI_BWMapping = 0x129f1;
-define exported symbol ROM_WIFI_SCMapping = 0x12a19;
-define exported symbol ROM_WIFI_FillTxdescSectype = 0x12a99;
-define exported symbol ROM_WIFI_FillFakeTxdesc = 0x12ab9;
-define exported symbol ROM_WIFI_32K_Cmd = 0x12b91;
-define exported symbol ROM_WIFI_DISCONNECT = 0x12bc1;
-define exported symbol ROM_WIFI_SET_TSF = 0x12bfd;
-define exported symbol ROM_WIFI_BCN_FUNC = 0x12ca5;
-define exported symbol ROM_WIFI_BSSID_SET = 0x12ccd;
-define exported symbol ROM_WIFI_MACADDR_SET = 0x12d09;
-define exported symbol ROM_WIFI_EnableInterrupt = 0x12d39;
-define exported symbol ROM_WIFI_DisableInterrupt = 0x12d4d;
-define exported symbol ROM_WIFI_RESUME_TxBeacon = 0x12d61;
-define exported symbol ROM_WIFI_STOP_TXBeacon = 0x12d91;
-define exported symbol ROM_WIFI_BCN_Interval = 0x12dc1;
-define exported symbol ROM_WIFI_BCN_FUNC_Enable = 0x12dcd;
-define exported symbol ROM_WIFI_INIT_BeaconParameters = 0x12de5;
-define exported symbol ROM_WIFI_MEDIA_STATUS1 = 0x12e35;
-define exported symbol ROM_WIFI_MEDIA_STATUS = 0x12e4d;
-define exported symbol ROM_WIFI_SetBrateCfg = 0x12e61;
-define exported symbol ROM_WIFI_BASIC_RATE = 0x12f69;
-define exported symbol ROM_WIFI_CHECK_BSSID = 0x12fc9;
-define exported symbol ROM_WIFI_RESP_SIFS = 0x12fe9;
-define exported symbol ROM_WIFI_CAM_WRITE = 0x13001;
-define exported symbol ROM_WIFI_ACM_CTRL = 0x13021;
-define exported symbol ROM_WIFI_FIFO_CLEARN_UP = 0x13051;
-define exported symbol ROM_WIFI_CHECK_TXBUF = 0x130b9;
-define exported symbol ROM_WIFI_BCN_VALID = 0x130fd;
-define exported symbol ROM_WIFI_PROMISC_Cmd = 0x13119;
-define exported symbol ROM_WIFI_SetOpmodeAP = 0x13189;
-define exported symbol ROM_WIFI_ReadChipVersion = 0x132a9;
-define exported symbol ROM_WIFI_DumpChipInfo = 0x1330d;
-define exported symbol ROM_WIFI_InitLxDma = 0x135b1;
-define exported symbol ROM_WIFI_InitQueueReservedPage = 0x13671;
-define exported symbol ROM_WIFI_InitTxBufferBoundary = 0x136f1;
-define exported symbol ROM_WIFI_InitNormalChipRegPriority = 0x1373d;
-define exported symbol ROM_WIFI_InitPageBoundary = 0x13789;
-define exported symbol ROM_WIFI_InitTransferPageSize = 0x13795;
-define exported symbol ROM_WIFI_InitDriverInfoSize = 0x137a1;
-define exported symbol ROM_WIFI_InitNetworkType = 0x137ad;
-define exported symbol ROM_WIFI_InitRCR = 0x137c5;
-define exported symbol ROM_WIFI_InitAdaptiveCtrl = 0x13805;
-define exported symbol ROM_WIFI_InitSIFS = 0x1383d;
-define exported symbol ROM_WIFI_InitEDCA = 0x13865;
-define exported symbol ROM_WIFI_InitRateFallback = 0x138a1;
-define exported symbol ROM_WIFI_InitRetryFunction = 0x138c9;
-define exported symbol ROM_WIFI_InitOperationMode = 0x138e5;
-define exported symbol ROM_WIFI_InitBurstPktLen = 0x138f9;
-define exported symbol phy_CalculateBitShift = 0x13905;
-define exported symbol PHY_SetBBReg_8711B = 0x1391d;
-define exported symbol PHY_QueryBBReg_8711B = 0x13921;
-define exported symbol ROM_odm_QueryRxPwrPercentage = 0x13925;
-define exported symbol ROM_odm_EVMdbToPercentage = 0x13931;
-define exported symbol ROM_odm_SignalScaleMapping_8711B = 0x13935;
-define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x13a11;
-define exported symbol ROM_odm_SetEDCCAThreshold = 0x13d39;
-define exported symbol ROM_odm_SetTRxMux = 0x13d61;
-define exported symbol ROM_odm_SetCrystalCap = 0x13d89;
-define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x13ded;
-define exported symbol ROM_ODM_CfoTrackingReset = 0x13dfd;
-define exported symbol ROM_odm_CfoTrackingFlow = 0x13e21;
-define exported symbol rtw_get_bit_value_from_ieee_value = 0x14045;
-define exported symbol rtw_is_cckrates_included = 0x14071;
-define exported symbol rtw_is_cckratesonly_included = 0x140a5;
-define exported symbol rtw_check_network_type = 0x140cd;
-define exported symbol rtw_set_fixed_ie = 0x14155;
-define exported symbol rtw_set_ie = 0x14175;
-define exported symbol rtw_get_ie = 0x141a1;
-define exported symbol rtw_set_supported_rate = 0x141b5;
-define exported symbol rtw_get_rateset_len = 0x14229;
-define exported symbol rtw_get_wpa_ie = 0x14245;
-define exported symbol rtw_get_wpa2_ie = 0x142d1;
-define exported symbol rtw_get_wpa_cipher_suite = 0x142e5;
-define exported symbol rtw_get_wpa2_cipher_suite = 0x1434d;
-define exported symbol rtw_parse_wpa_ie = 0x143b5;
-define exported symbol rtw_parse_wpa2_ie = 0x14481;
-define exported symbol rtw_get_sec_ie = 0x14535;
-define exported symbol rtw_get_wps_ie = 0x145e5;
-define exported symbol rtw_get_wps_attr = 0x14659;
-define exported symbol rtw_get_wps_attr_content = 0x146f1;
-define exported symbol rtw_ieee802_11_parse_elems = 0x14739;
-define exported symbol str_2char2num = 0x14909;
-define exported symbol key_2char2num = 0x14925;
-define exported symbol convert_ip_addr = 0x1493d;
-define exported symbol rom_psk_PasswordHash = 0x14a21;
-define exported symbol rom_psk_CalcGTK = 0x14a59;
-define exported symbol rom_psk_CalcPTK = 0x14ae9;
-define exported symbol _htons_rom = 0x14bdd;
-define exported symbol _ntohs_rom = 0x14be5;
-define exported symbol _htonl_rom = 0x14bed;
-define exported symbol _ntohl_rom = 0x14bf1;
-define exported symbol Message_ReplayCounter_OC2LI = 0x14bf5;
-define exported symbol Message_EqualReplayCounter = 0x14c35;
-define exported symbol Message_SmallerEqualReplayCounter = 0x14c6d;
-define exported symbol Message_LargerReplayCounter = 0x14cad;
-define exported symbol Message_setReplayCounter = 0x14ce5;
-define exported symbol INCLargeInteger = 0x14d15;
-define exported symbol INCOctet16_INTEGER = 0x14d25;
-define exported symbol INCOctet32_INTEGER = 0x14d8d;
-define exported symbol SetEAPOL_KEYIV = 0x14df5;
-define exported symbol CheckMIC = 0x14e89;
-define exported symbol CalcMIC = 0x14f29;
-define exported symbol DecWPA2KeyData_rom = 0x14f9d;
-define exported symbol DecGTK = 0x15055;
-define exported symbol GetRandomBuffer = 0x15119;
-define exported symbol GenNonce = 0x15181;
-define exported symbol ClientConstructEAPOL_2Of4Way = 0x151c5;
-define exported symbol ClientConstructEAPOL_4Of4Way = 0x152cd;
-define exported symbol ClientConstructEAPOL_2Of2Way = 0x1537d;
-define exported symbol ClientConstructEAPOL_MICOf2Way = 0x15459;
-define exported symbol psk_strip_rsn_pairwise = 0x1552d;
-define exported symbol psk_strip_wpa_pairwise = 0x155c1;
-define exported symbol wep_80211_encrypt = 0x1587d;
-define exported symbol wep_80211_decrypt = 0x158e1;
-define exported symbol tkip_micappendbyte = 0x15975;
-define exported symbol rtw_secmicsetkey = 0x159b9;
-define exported symbol rtw_secmicappend = 0x159f9;
-define exported symbol rtw_secgetmic = 0x15a15;
-define exported symbol rtw_seccalctkipmic = 0x15a89;
-define exported symbol tkip_phase1 = 0x15b7d;
-define exported symbol tkip_phase2 = 0x15ce5;
-define exported symbol tkip_80211_encrypt = 0x15f01;
-define exported symbol tkip_80211_decrypt = 0x15f91;
-define exported symbol aes1_encrypt = 0x16055;
-define exported symbol aesccmp_construct_mic_iv = 0x1625d;
-define exported symbol aesccmp_construct_mic_header1 = 0x162b1;
-define exported symbol aesccmp_construct_mic_header2 = 0x16321;
-define exported symbol aesccmp_construct_ctr_preload = 0x163a5;
-define exported symbol aes_80211_encrypt = 0x16429;
-define exported symbol aes_80211_decrypt = 0x167f9;
-define exported symbol cckrates_included = 0x16c39;
-define exported symbol cckratesonly_included = 0x16c7d;
-define exported symbol networktype_to_raid_ex_rom = 0x16ca9;
-define exported symbol judge_network_type_rom = 0x16cf5;
-define exported symbol ratetbl_val_2wifirate = 0x16d89;
-define exported symbol is_basicrate_rom = 0x16d9d;
-define exported symbol ratetbl2rateset_rom = 0x16dd5;
-define exported symbol get_rate_set_rom = 0x16e3d;
-define exported symbol UpdateBrateTbl_rom = 0x16e71;
-define exported symbol UpdateBrateTblForSoftAP = 0x16ec9;
-define exported symbol write_cam_rom = 0x16f0d;
-define exported symbol HT_caps_handler_rom = 0x16fc1;
-define exported symbol wifirate2_ratetbl_inx = 0x17015;
-define exported symbol update_basic_rate = 0x170bd;
-define exported symbol update_supported_rate = 0x170f5;
-define exported symbol update_MCS_rate = 0x17125;
-define exported symbol get_highest_rate_idx = 0x17131;
-define exported symbol _sha1_process_message_block = 0x1714d;
-define exported symbol _sha1_pad_message = 0x172d1;
-define exported symbol rt_sha1_init = 0x1736d;
-define exported symbol rt_sha1_update = 0x173b1;
-define exported symbol rt_sha1_finish = 0x17429;
-define exported symbol rt_hmac_sha1 = 0x17489;
-define exported symbol rom_aes_128_cbc_encrypt = 0x175e5;
-define exported symbol rom_aes_128_cbc_decrypt = 0x17669;
-define exported symbol rom_rijndaelKeySetupEnc = 0x176ed;
-define exported symbol rom_aes_decrypt_init = 0x177c1;
-define exported symbol rom_aes_internal_decrypt = 0x17899;
-define exported symbol rom_aes_decrypt_deinit = 0x17bdd;
-define exported symbol rom_aes_encrypt_init = 0x17be9;
-define exported symbol rom_aes_internal_encrypt = 0x17c01;
-define exported symbol rom_aes_encrypt_deinit = 0x17f81;
-define exported symbol bignum_init = 0x1963d;
-define exported symbol bignum_deinit = 0x19665;
-define exported symbol bignum_get_unsigned_bin_len = 0x19685;
-define exported symbol bignum_get_unsigned_bin = 0x19689;
-define exported symbol bignum_set_unsigned_bin = 0x19741;
-define exported symbol bignum_cmp = 0x197f9;
-define exported symbol bignum_cmp_d = 0x197fd;
-define exported symbol bignum_add = 0x19825;
-define exported symbol bignum_sub = 0x19835;
-define exported symbol bignum_mul = 0x19845;
-define exported symbol bignum_exptmod = 0x19855;
-define exported symbol WPS_realloc = 0x19879;
-define exported symbol os_zalloc = 0x198bd;
-define exported symbol rom_hmac_sha256_vector = 0x198e1;
-define exported symbol rom_hmac_sha256 = 0x199e1;
-define exported symbol rom_sha256_vector = 0x19b3d;
-define exported symbol CRYPTO_chacha_20 = 0x19d45;
-define exported symbol rom_ed25519_gen_keypair = 0x1a1bd;
-define exported symbol rom_ed25519_gen_signature = 0x1a1c1;
-define exported symbol rom_ed25519_verify_signature = 0x1a1d9;
-define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9;
-define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1;
-define exported symbol rom_ed25519_ge_p3_tobytes = 0x1d43d;
-define exported symbol rom_ed25519_ge_scalarmult_base = 0x1d489;
-define exported symbol rom_ed25519_ge_tobytes = 0x1d64d;
-define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x1d699;
-define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x1d6f1;
-define exported symbol rom_ed25519_sc_muladd = 0x1d9e5;
-define exported symbol rom_ed25519_sc_reduce = 0x24175;
-define exported symbol rom_ed25519_crypto_sign_detached = 0x26c25;
-define exported symbol CRYPTO_poly1305_init = 0x270dd;
-define exported symbol CRYPTO_poly1305_update = 0x271b5;
-define exported symbol CRYPTO_poly1305_finish = 0x27245;
-define exported symbol rom_sha512_starts = 0x28511;
-define exported symbol rom_sha512_update = 0x28659;
-define exported symbol rom_sha512_finish = 0x28661;
-define exported symbol rom_sha512 = 0x288a9;
-define exported symbol rom_sha512_hmac_starts = 0x288e1;
-define exported symbol rom_sha512_hmac_update = 0x289a5;
-define exported symbol rom_sha512_hmac_finish = 0x289ad;
-define exported symbol rom_sha512_hmac_reset = 0x289fd;
-define exported symbol rom_sha512_hmac = 0x28a19;
-define exported symbol rom_sha512_hkdf = 0x28a51;
-define exported symbol aes_test_alignment_detection = 0x28b59;
-define exported symbol aes_mode_reset = 0x28bbd;
-define exported symbol aes_ecb_encrypt = 0x28bc9;
-define exported symbol aes_ecb_decrypt = 0x28c05;
-define exported symbol aes_cbc_encrypt = 0x28c41;
-define exported symbol aes_cbc_decrypt = 0x28dad;
-define exported symbol aes_cfb_encrypt = 0x28f49;
-define exported symbol aes_cfb_decrypt = 0x2920d;
-define exported symbol aes_ofb_crypt = 0x294d5;
-define exported symbol aes_ctr_crypt = 0x29769;
-define exported symbol aes_encrypt_key128 = 0x29a79;
-define exported symbol aes_encrypt_key192 = 0x29a95;
-define exported symbol aes_encrypt_key256 = 0x29ab1;
-define exported symbol aes_encrypt_key = 0x29ad1;
-define exported symbol aes_decrypt_key128 = 0x29b41;
-define exported symbol aes_decrypt_key192 = 0x29b5d;
-define exported symbol aes_decrypt_key256 = 0x29b79;
-define exported symbol aes_decrypt_key = 0x29b99;
-define exported symbol aes_init = 0x29c09;
-define exported symbol curve25519_donna = 0x2a939;
-define exported symbol __rtl_dtoa_r_v1_00 = 0x2b7f1;
-define exported symbol __rtl_ltoa_v1_00 = 0x2c7f9;
-define exported symbol __rtl_ultoa_v1_00 = 0x2c885;
-define exported symbol __rtl_dtoi_v1_00 = 0x2c8ed;
-define exported symbol __rtl_dtoi64_v1_00 = 0x2c96d;
-define exported symbol __rtl_dtoui_v1_00 = 0x2ca09;
-define exported symbol __rtl_ftol_v1_00 = 0x2ca11;
-define exported symbol __rtl_itof_v1_00 = 0x2ca75;
-define exported symbol __rtl_itod_v1_00 = 0x2cb05;
-define exported symbol __rtl_i64tod_v1_00 = 0x2cb71;
-define exported symbol __rtl_uitod_v1_00 = 0x2cc4d;
-define exported symbol __rtl_ftod_v1_00 = 0x2cd29;
-define exported symbol __rtl_dtof_v1_00 = 0x2cde1;
-define exported symbol __rtl_uitof_v1_00 = 0x2ce75;
-define exported symbol __rtl_fadd_v1_00 = 0x2cf59;
-define exported symbol __rtl_fsub_v1_00 = 0x2d259;
-define exported symbol __rtl_fmul_v1_00 = 0x2d565;
-define exported symbol __rtl_fdiv_v1_00 = 0x2d695;
-define exported symbol __rtl_dadd_v1_00 = 0x2d809;
-define exported symbol __rtl_dsub_v1_00 = 0x2de49;
-define exported symbol __rtl_dmul_v1_00 = 0x2e4a1;
-define exported symbol __rtl_ddiv_v1_00 = 0x2e7dd;
-define exported symbol __rtl_dcmpeq_v1_00 = 0x2ed71;
-define exported symbol __rtl_dcmplt_v1_00 = 0x2eded;
-define exported symbol __rtl_dcmpgt_v1_00 = 0x2ee85;
-define exported symbol __rtl_dcmple_v1_00 = 0x2ef95;
-define exported symbol __rtl_fcmplt_v1_00 = 0x2f0a9;
-define exported symbol __rtl_fcmpgt_v1_00 = 0x2f105;
-define exported symbol __rtl_fpclassifyd = 0x2f1ad;
-define exported symbol __rtl_close_v1_00 = 0x2f205;
-define exported symbol __rtl_fstat_v1_00 = 0x2f219;
-define exported symbol __rtl_isatty_v1_00 = 0x2f22d;
-define exported symbol __rtl_lseek_v1_00 = 0x2f23d;
-define exported symbol __rtl_open_v1_00 = 0x2f251;
-define exported symbol __rtl_read_v1_00 = 0x2f265;
-define exported symbol __rtl_write_v1_00 = 0x2f279;
-define exported symbol __rtl_sbrk_v1_00 = 0x2f28d;
-define exported symbol __rom_mallocr_init_v1_00 = 0x2f29d;
-define exported symbol __rtl_free_r_v1_00 = 0x2f309;
-define exported symbol __rtl_malloc_r_v1_00 = 0x2f521;
-define exported symbol __rtl_realloc_r_v1_00 = 0x2f9f5;
-define exported symbol __rtl_memalign_r_v1_00 = 0x2fdb5;
-define exported symbol __rtl_valloc_r_v1_00 = 0x2fe81;
-define exported symbol __rtl_pvalloc_r_v1_00 = 0x2fe8d;
-define exported symbol __rtl_calloc_r_v1_00 = 0x2fea1;
-define exported symbol __rtl_cfree_r_v1_00 = 0x2ff05;
-define exported symbol __rtl_cos_f32_v1_00 = 0x2ff15;
-define exported symbol __rtl_sin_f32_v1_00 = 0x300e9;
-define exported symbol __rtl_fabs_v1_00 = 0x302ad;
-define exported symbol __rtl_fabsf_v1_00 = 0x302b5;
-define exported symbol __rtl_memchr_v1_00 = 0x302bd;
-define exported symbol __rtl_memcmp_v1_00 = 0x30351;
-define exported symbol __rtl_memcpy_v1_00 = 0x303b5;
-define exported symbol __rtl_memmove_v1_00 = 0x3045d;
-define exported symbol __rtl_memset_v1_00 = 0x30525;
-define exported symbol __rtl_Balloc_v1_00 = 0x3061d;
-define exported symbol __rtl_Bfree_v1_00 = 0x3066d;
-define exported symbol __rtl_i2b_v1_00 = 0x30681;
-define exported symbol __rtl_multadd_v1_00 = 0x30695;
-define exported symbol __rtl_mult_v1_00 = 0x30721;
-define exported symbol __rtl_pow5mult_v1_00 = 0x30855;
-define exported symbol __rtl_hi0bits_v1_00 = 0x308f5;
-define exported symbol __rtl_d2b_v1_00 = 0x30935;
-define exported symbol __rtl_lshift_v1_00 = 0x309ed;
-define exported symbol __rtl_cmp_v1_00 = 0x30a99;
-define exported symbol __rtl_diff_v1_00 = 0x30ae1;
-define exported symbol __rtl_sread_v1_00 = 0x30bb5;
-define exported symbol __rtl_seofread_v1_00 = 0x30c01;
-define exported symbol __rtl_swrite_v1_00 = 0x30c05;
-define exported symbol __rtl_sseek_v1_00 = 0x30c75;
-define exported symbol __rtl_sclose_v1_00 = 0x30cc1;
-define exported symbol __rtl_sbrk_r_v1_00 = 0x30ced;
-define exported symbol __rtl_strcat_v1_00 = 0x30d15;
-define exported symbol __rtl_strchr_v1_00 = 0x30d59;
-define exported symbol __rtl_strcmp_v1_00 = 0x30e25;
-define exported symbol __rtl_strcpy_v1_00 = 0x30e99;
-define exported symbol __rtl_strlen_v1_00 = 0x30ee5;
-define exported symbol __rtl_strncat_v1_00 = 0x30f39;
-define exported symbol __rtl_strncmp_v1_00 = 0x30f95;
-define exported symbol __rtl_strncpy_v1_00 = 0x3102d;
-define exported symbol __rtl_strsep_v1_00 = 0x31095;
-define exported symbol __rtl_strstr_v1_00 = 0x3136d;
-define exported symbol __rtl_strtok_v1_00 = 0x315a5;
-define exported symbol __rtl__strtok_r_v1_00 = 0x315b5;
-define exported symbol __rtl_strtok_r_v1_00 = 0x31619;
-define exported symbol __rtl_fflush_r_v1_00 = 0x31ae9;
-define exported symbol __rtl_vfprintf_r_v1_00 = 0x31f99;
-define exported symbol polarssl_aes_init = 0x335b9;
-define exported symbol aes_free = 0x335c9;
-define exported symbol aes_setkey_enc = 0x335dd;
-define exported symbol aes_setkey_dec = 0x33829;
-define exported symbol aes_crypt_ecb = 0x339a1;
-define exported symbol aes_crypt_cbc = 0x343d1;
-define exported symbol aes_crypt_cfb128 = 0x34649;
-define exported symbol aes_crypt_cfb8 = 0x346c9;
-define exported symbol aes_crypt_ctr = 0x3474d;
-define exported symbol arc4_init = 0x347b1;
-define exported symbol arc4_free = 0x347bd;
-define exported symbol arc4_setup = 0x347d1;
-define exported symbol arc4_crypt = 0x3481d;
-define exported symbol asn1_get_len = 0x34861;
-define exported symbol asn1_get_tag = 0x34901;
-define exported symbol asn1_get_bool = 0x34929;
-define exported symbol asn1_get_int = 0x3495d;
-define exported symbol asn1_get_mpi = 0x349a9;
-define exported symbol asn1_get_bitstring = 0x349d1;
-define exported symbol asn1_get_bitstring_null = 0x34a19;
-define exported symbol asn1_get_sequence_of = 0x34a4d;
-define exported symbol asn1_get_alg = 0x34ad1;
-define exported symbol asn1_get_alg_null = 0x34b65;
-define exported symbol asn1_free_named_data = 0x34ba5;
-define exported symbol asn1_free_named_data_list = 0x34bcd;
-define exported symbol asn1_find_named_data = 0x34bf5;
-define exported symbol asn1_write_len = 0x34c25;
-define exported symbol asn1_write_tag = 0x34c8d;
-define exported symbol asn1_write_raw_buffer = 0x34ca9;
-define exported symbol asn1_write_mpi = 0x34ccd;
-define exported symbol asn1_write_null = 0x34d41;
-define exported symbol asn1_write_oid = 0x34d6d;
-define exported symbol asn1_write_algorithm_identifier = 0x34dc5;
-define exported symbol asn1_write_bool = 0x34e21;
-define exported symbol asn1_write_int = 0x34e65;
-define exported symbol asn1_write_printable_string = 0x34ecd;
-define exported symbol asn1_write_ia5_string = 0x34f25;
-define exported symbol asn1_write_bitstring = 0x34f7d;
-define exported symbol asn1_write_octet_string = 0x34fe5;
-define exported symbol asn1_store_named_data = 0x3503d;
-define exported symbol base64_encode = 0x35111;
-define exported symbol base64_decode = 0x3523d;
-define exported symbol mpi_init = 0x35e09;
-define exported symbol mpi_free = 0x35e19;
-define exported symbol mpi_grow = 0x35e55;
-define exported symbol mpi_shrink = 0x35e79;
-define exported symbol mpi_copy = 0x35f21;
-define exported symbol mpi_swap = 0x35fa1;
-define exported symbol mpi_safe_cond_assign = 0x35fcd;
-define exported symbol mpi_safe_cond_swap = 0x36069;
-define exported symbol mpi_lset = 0x3610d;
-define exported symbol mpi_get_bit = 0x3614d;
-define exported symbol mpi_set_bit = 0x3616d;
-define exported symbol mpi_lsb = 0x361d5;
-define exported symbol mpi_msb = 0x36215;
-define exported symbol mpi_size = 0x36261;
-define exported symbol mpi_read_binary = 0x3626d;
-define exported symbol mpi_write_binary = 0x362f9;
-define exported symbol mpi_shift_l = 0x36341;
-define exported symbol mpi_shift_r = 0x363f1;
-define exported symbol mpi_cmp_abs = 0x36475;
-define exported symbol mpi_cmp_mpi = 0x36619;
-define exported symbol mpi_cmp_int = 0x366f1;
-define exported symbol mpi_add_abs = 0x3671d;
-define exported symbol mpi_sub_abs = 0x3680d;
-define exported symbol mpi_add_mpi = 0x3689d;
-define exported symbol mpi_sub_mpi = 0x368ed;
-define exported symbol mpi_add_int = 0x3693d;
-define exported symbol mpi_sub_int = 0x36969;
-define exported symbol mpi_mul_mpi = 0x36995;
-define exported symbol mpi_read_string = 0x36ac5;
-define exported symbol mpi_mul_int = 0x36c45;
-define exported symbol mpi_div_mpi = 0x36c61;
-define exported symbol mpi_div_int = 0x370ed;
-define exported symbol mpi_mod_mpi = 0x37119;
-define exported symbol mpi_mod_int = 0x3717d;
-define exported symbol mpi_write_string = 0x3722d;
-define exported symbol mpi_exp_mod = 0x37395;
-define exported symbol mpi_gcd = 0x37915;
-define exported symbol mpi_fill_random = 0x37a39;
-define exported symbol mpi_inv_mod = 0x37c4d;
-define exported symbol mpi_is_prime = 0x37f15;
-define exported symbol mpi_gen_prime = 0x37f71;
-define exported symbol ctr_drbg_free = 0x38285;
-define exported symbol ctr_drbg_set_prediction_resistance = 0x382a1;
-define exported symbol ctr_drbg_set_entropy_len = 0x382a5;
-define exported symbol ctr_drbg_set_reseed_interval = 0x382a9;
-define exported symbol ctr_drbg_update = 0x382ad;
-define exported symbol ctr_drbg_reseed = 0x382c9;
-define exported symbol ctr_drbg_init_entropy_len = 0x38341;
-define exported symbol ctr_drbg_init = 0x38399;
-define exported symbol ctr_drbg_random_with_add = 0x383ad;
-define exported symbol ctr_drbg_random = 0x38469;
-define exported symbol des_init = 0x388a5;
-define exported symbol des_free = 0x388b1;
-define exported symbol des3_init = 0x388c5;
-define exported symbol des3_free = 0x388d5;
-define exported symbol des_key_set_parity = 0x388e9;
-define exported symbol des_key_check_key_parity = 0x38909;
-define exported symbol des_key_check_weak = 0x38939;
-define exported symbol des_setkey_enc = 0x38965;
-define exported symbol des_setkey_dec = 0x3898d;
-define exported symbol des3_set2key_enc = 0x389d9;
-define exported symbol des3_set2key_dec = 0x38a25;
-define exported symbol des3_set3key_enc = 0x38a71;
-define exported symbol des3_set3key_dec = 0x38ab1;
-define exported symbol des_crypt_ecb = 0x38af1;
-define exported symbol des_crypt_cbc = 0x38d09;
-define exported symbol des3_crypt_ecb = 0x38f99;
-define exported symbol des3_crypt_cbc = 0x39401;
-define exported symbol dhm_init = 0x39729;
-define exported symbol dhm_read_params = 0x39731;
-define exported symbol dhm_make_params = 0x3978d;
-define exported symbol dhm_read_public = 0x398c1;
-define exported symbol dhm_make_public = 0x398e9;
-define exported symbol dhm_calc_secret = 0x399ad;
-define exported symbol dhm_free = 0x39ba1;
-define exported symbol dhm_parse_dhm = 0x39c01;
-define exported symbol ecdh_gen_public = 0x39cc5;
-define exported symbol ecdh_compute_shared = 0x39cc9;
-define exported symbol ecdh_init = 0x39d2d;
-define exported symbol ecdh_free = 0x39d39;
-define exported symbol ecdh_make_params = 0x39d81;
-define exported symbol ecdh_read_params = 0x39e05;
-define exported symbol ecdh_get_params = 0x39e2d;
-define exported symbol ecdh_make_public = 0x39e79;
-define exported symbol ecdh_read_public = 0x39ed1;
-define exported symbol ecdh_calc_secret = 0x39f01;
-define exported symbol ecdsa_sign = 0x3a041;
-define exported symbol ecdsa_sign_det = 0x3a1c5;
-define exported symbol ecdsa_verify = 0x3a2a9;
-define exported symbol ecdsa_write_signature = 0x3a431;
-define exported symbol ecdsa_write_signature_det = 0x3a46d;
-define exported symbol ecdsa_read_signature = 0x3a4a5;
-define exported symbol ecdsa_genkey = 0x3a531;
-define exported symbol ecdsa_init = 0x3a565;
-define exported symbol ecdsa_free = 0x3a591;
-define exported symbol ecdsa_from_keypair = 0x3a5bd;
-define exported symbol ecp_curve_list = 0x3aee5;
-define exported symbol ecp_curve_info_from_grp_id = 0x3aeed;
-define exported symbol ecp_curve_info_from_tls_id = 0x3af0d;
-define exported symbol ecp_curve_info_from_name = 0x3af31;
-define exported symbol ecp_point_init = 0x3af61;
-define exported symbol ecp_group_init = 0x3af81;
-define exported symbol ecp_keypair_init = 0x3af8d;
-define exported symbol ecp_point_free = 0x3afb1;
-define exported symbol ecp_group_free = 0x3afd1;
-define exported symbol ecp_keypair_free = 0x3b03d;
-define exported symbol ecp_copy = 0x3b05d;
-define exported symbol ecp_group_copy = 0x3b08d;
-define exported symbol ecp_set_zero = 0x3b095;
-define exported symbol ecp_is_zero = 0x3ba61;
-define exported symbol ecp_point_read_string = 0x3ba75;
-define exported symbol ecp_point_write_binary = 0x3baa5;
-define exported symbol ecp_point_read_binary = 0x3bb4d;
-define exported symbol ecp_tls_read_point = 0x3bbc1;
-define exported symbol ecp_tls_write_point = 0x3bbf5;
-define exported symbol ecp_group_read_string = 0x3bc25;
-define exported symbol ecp_tls_read_group = 0x3bc95;
-define exported symbol ecp_tls_write_group = 0x3bcf1;
-define exported symbol ecp_add = 0x3bd39;
-define exported symbol ecp_sub = 0x3bd65;
-define exported symbol ecp_check_pubkey = 0x3bddd;
-define exported symbol ecp_check_privkey = 0x3bf8d;
-define exported symbol ecp_mul = 0x3bff5;
-define exported symbol ecp_gen_keypair = 0x3c565;
-define exported symbol ecp_gen_key = 0x3c669;
-define exported symbol ecp_use_known_dp = 0x3d741;
-define exported symbol hmac_drbg_update = 0x3daa9;
-define exported symbol hmac_drbg_init_buf = 0x3db41;
-define exported symbol hmac_drbg_reseed = 0x3db91;
-define exported symbol hmac_drbg_init = 0x3dc09;
-define exported symbol hmac_drbg_set_prediction_resistance = 0x3dc81;
-define exported symbol hmac_drbg_set_entropy_len = 0x3dc85;
-define exported symbol hmac_drbg_set_reseed_interval = 0x3dc89;
-define exported symbol hmac_drbg_random_with_add = 0x3dc8d;
-define exported symbol hmac_drbg_random = 0x3dd4d;
-define exported symbol hmac_drbg_free = 0x3dd61;
-define exported symbol md_list = 0x3dd7d;
-define exported symbol md_info_from_string = 0x3dd85;
-define exported symbol md_info_from_type = 0x3de59;
-define exported symbol md_init = 0x3de9d;
-define exported symbol md_free = 0x3dea5;
-define exported symbol md_init_ctx = 0x3dec5;
-define exported symbol md_free_ctx = 0x3defd;
-define exported symbol md_starts = 0x3df09;
-define exported symbol md_update = 0x3df29;
-define exported symbol md_finish = 0x3df49;
-define exported symbol md = 0x3df69;
-define exported symbol md_file = 0x3df89;
-define exported symbol md_hmac_starts = 0x3dfa1;
-define exported symbol md_hmac_update = 0x3dfc1;
-define exported symbol md_hmac_finish = 0x3dfe1;
-define exported symbol md_hmac_reset = 0x3e001;
-define exported symbol md_hmac = 0x3e021;
-define exported symbol md_process = 0x3e049;
-define exported symbol md5_init = 0x3e301;
-define exported symbol md5_free = 0x3e309;
-define exported symbol md5_starts = 0x3e31d;
-define exported symbol md5_process = 0x3e34d;
-define exported symbol md5_update = 0x3ed51;
-define exported symbol md5_finish = 0x3ed59;
-define exported symbol md5 = 0x3ee11;
-define exported symbol md5_hmac_starts = 0x3ee75;
-define exported symbol md5_hmac_update = 0x3ef51;
-define exported symbol md5_hmac_finish = 0x3ef59;
-define exported symbol md5_hmac_reset = 0x3efbd;
-define exported symbol md5_hmac = 0x3eff1;
-define exported symbol oid_get_attr_short_name = 0x3f071;
-define exported symbol oid_get_x509_ext_type = 0x3f0b1;
-define exported symbol oid_get_extended_key_usage = 0x3f0f1;
-define exported symbol oid_get_sig_alg_desc = 0x3f131;
-define exported symbol oid_get_sig_alg = 0x3f149;
-define exported symbol oid_get_oid_by_sig_alg = 0x3f169;
-define exported symbol oid_get_pk_alg = 0x3f1a1;
-define exported symbol oid_get_oid_by_pk_alg = 0x3f1e1;
-define exported symbol oid_get_ec_grp = 0x3f219;
-define exported symbol oid_get_oid_by_ec_grp = 0x3f259;
-define exported symbol oid_get_cipher_alg = 0x3f291;
-define exported symbol oid_get_md_alg = 0x3f2d1;
-define exported symbol oid_get_oid_by_md = 0x3f311;
-define exported symbol oid_get_pkcs12_pbe_alg = 0x3f349;
-define exported symbol oid_get_numeric_string = 0x3f391;
-define exported symbol pem_init = 0x3f649;
-define exported symbol pem_read_buffer = 0x3f651;
-define exported symbol pem_free = 0x3f955;
-define exported symbol pem_write_buffer = 0x3f97d;
-define exported symbol pk_init = 0x3fa81;
-define exported symbol pk_free = 0x3fa8d;
-define exported symbol pk_info_from_type = 0x3faad;
-define exported symbol pk_init_ctx = 0x3fae1;
-define exported symbol pk_init_ctx_rsa_alt = 0x3fb11;
-define exported symbol pk_can_do = 0x3fb69;
-define exported symbol pk_verify = 0x3fb79;
-define exported symbol pk_verify_ext = 0x3fbc9;
-define exported symbol pk_sign = 0x3fc8d;
-define exported symbol pk_decrypt = 0x3fce9;
-define exported symbol pk_encrypt = 0x3fd15;
-define exported symbol pk_get_size = 0x3fd41;
-define exported symbol pk_debug = 0x3fd51;
-define exported symbol pk_get_name = 0x3fd79;
-define exported symbol pk_get_type = 0x3fd8d;
-define exported symbol pk_write_pubkey = 0x40181;
-define exported symbol pk_write_pubkey_der = 0x40201;
-define exported symbol pk_write_key_der = 0x402dd;
-define exported symbol pk_write_pubkey_pem = 0x404f5;
-define exported symbol pk_write_key_pem = 0x40545;
-define exported symbol rsa_init = 0x4065d;
-define exported symbol rsa_set_padding = 0x40679;
-define exported symbol rsa_check_pubkey = 0x40685;
-define exported symbol rsa_check_privkey = 0x406e1;
-define exported symbol rsa_public = 0x409a5;
-define exported symbol rsa_private = 0x40a25;
-define exported symbol rsa_rsaes_oaep_encrypt = 0x40c29;
-define exported symbol rsa_rsaes_pkcs1_v15_encrypt = 0x40d31;
-define exported symbol rsa_pkcs1_encrypt = 0x40e19;
-define exported symbol rsa_rsaes_oaep_decrypt = 0x40e59;
-define exported symbol rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd;
-define exported symbol rsa_pkcs1_decrypt = 0x410c1;
-define exported symbol rsa_rsassa_pss_sign = 0x4110d;
-define exported symbol rsa_rsassa_pkcs1_v15_sign = 0x41271;
-define exported symbol rsa_pkcs1_sign = 0x41389;
-define exported symbol rsa_rsassa_pss_verify_ext = 0x413c9;
-define exported symbol rsa_rsassa_pss_verify = 0x41575;
-define exported symbol rsa_rsassa_pkcs1_v15_verify = 0x415a5;
-define exported symbol rsa_pkcs1_verify = 0x41709;
-define exported symbol rsa_free = 0x41765;
-define exported symbol rsa_gen_key = 0x417d5;
-define exported symbol rsa_copy = 0x4198d;
-define exported symbol sha1_init = 0x41a9d;
-define exported symbol sha1_free = 0x41aa5;
-define exported symbol sha1_starts = 0x41ab9;
-define exported symbol sha1_process = 0x41aed;
-define exported symbol sha1_update = 0x42e15;
-define exported symbol sha1_finish = 0x42e1d;
-define exported symbol sha1 = 0x42ee5;
-define exported symbol sha1_hmac_starts = 0x42f51;
-define exported symbol sha1_hmac_update = 0x43039;
-define exported symbol sha1_hmac_finish = 0x43041;
-define exported symbol sha1_hmac_reset = 0x430b5;
-define exported symbol sha1_hmac = 0x430f1;
-define exported symbol sha256_init = 0x43139;
-define exported symbol sha256_free = 0x43141;
-define exported symbol sha256_starts = 0x43155;
-define exported symbol sha256_process = 0x431e5;
-define exported symbol sha256_update = 0x4513d;
-define exported symbol sha256_finish = 0x45145;
-define exported symbol sha256 = 0x4524d;
-define exported symbol sha256_hmac_starts = 0x45325;
-define exported symbol sha256_hmac_update = 0x45475;
-define exported symbol sha256_hmac_finish = 0x4547d;
-define exported symbol sha256_hmac_reset = 0x45569;
-define exported symbol sha256_hmac = 0x45601;
-define exported symbol sha512_init = 0x45651;
-define exported symbol sha512_free = 0x4565d;
-define exported symbol sha512_starts = 0x45671;
-define exported symbol sha512_process = 0x457b9;
-define exported symbol sha512_update = 0x46879;
-define exported symbol sha512_finish = 0x46881;
-define exported symbol sha512 = 0x46ac9;
-define exported symbol sha512_hmac_starts = 0x46b11;
-define exported symbol sha512_hmac_update = 0x46bd9;
-define exported symbol sha512_hmac_finish = 0x46be1;
-define exported symbol sha512_hmac_reset = 0x46c35;
-define exported symbol sha512_hmac = 0x46c51;
-define exported symbol UartLogRomCmdTable = 0x46ca0;
-define exported symbol XTAL_CLK = 0x46e10;
-define exported symbol CpkClkTbl_FPAG = 0x46e50;
-define exported symbol CpkClkTbl_ASIC = 0x46e68;
-define exported symbol ROM_IMG1_VALID_PATTEN = 0x46e90;
-define exported symbol __AES_rcon = 0x46e98;
-define exported symbol __AES_Te4 = 0x46ec0;
-define exported symbol SpicCalibrationPattern = 0x472c0;
-define exported symbol NEW_CALIBREATION_DIV = 0x472c8;
-define exported symbol NEW_CALIBREATION_DATA = 0x472e4;
-define exported symbol GDMA_IrqNum = 0x47344;
-define exported symbol I2C_DEV_TABLE = 0x47350;
-define exported symbol spi_clk_pin = 0x47370;
-define exported symbol SPI_DEV_TABLE = 0x47374;
-define exported symbol PWM_GDMA_HSx = 0x47394;
-define exported symbol TIM_DMA_CCx = 0x473ac;
-define exported symbol TIM_IT_CCx = 0x473c4;
-define exported symbol TIMx = 0x473dc;
-define exported symbol TIMx_irq = 0x473f4;
-define exported symbol BAUDRATE_TABLE_40M = 0x4740c;
-define exported symbol UART_DEV_TABLE = 0x475bc;
-define exported symbol RTW_WPA_OUI_TYPE = 0x4b270;
-define exported symbol WPA_CIPHER_SUITE_NONE = 0x4b274;
-define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x4b278;
-define exported symbol WPA_CIPHER_SUITE_TKIP = 0x4b27c;
-define exported symbol WPA_CIPHER_SUITE_CCMP = 0x4b280;
-define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x4b284;
-define exported symbol RSN_CIPHER_SUITE_NONE = 0x4b288;
-define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x4b28c;
-define exported symbol RSN_CIPHER_SUITE_TKIP = 0x4b290;
-define exported symbol RSN_CIPHER_SUITE_CCMP = 0x4b294;
-define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x4b298;
-define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8;
-define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac;
-define exported symbol RSN_VERSION_BSD = 0x4b2b0;
-define exported symbol rom_e_rtw_msgp_str_ = 0x4b2b4;
-define exported symbol rtw_basic_rate_mix = 0x4b9a8;
-define exported symbol rtw_basic_rate_ofdm = 0x4b9b0;
-define exported symbol rtw_basic_rate_cck = 0x4b9b4;
-define exported symbol REALTEK_96B_IE = 0x4b9b8;
-define exported symbol AIRGOCAP_OUI = 0x4b9c0;
-define exported symbol REALTEK_OUI = 0x4b9c4;
-define exported symbol RALINK_OUI = 0x4b9c8;
-define exported symbol MARVELL_OUI = 0x4b9cc;
-define exported symbol CISCO_OUI = 0x4b9d0;
-define exported symbol BROADCOM_OUI3 = 0x4b9d4;
-define exported symbol BROADCOM_OUI2 = 0x4b9d8;
-define exported symbol BROADCOM_OUI1 = 0x4b9dc;
-define exported symbol ARTHEROS_OUI2 = 0x4b9e0;
-define exported symbol ARTHEROS_OUI1 = 0x4b9e4;
-define exported symbol rom_wps_rcons = 0x4b9e8;
-define exported symbol rom_wps_Te0 = 0x4b9f4;
-define exported symbol rom_wps_Td4s = 0x4bdf4;
-define exported symbol rom_wps_Td0 = 0x4bef4;
-define exported symbol sha512_info = 0x5850c;
-define exported symbol sha384_info = 0x5854c;
-define exported symbol sha256_info = 0x5858c;
-define exported symbol sha224_info = 0x585cc;
-define exported symbol sha1_info = 0x5860c;
-define exported symbol md5_info = 0x5864c;
-define exported symbol rsa_alt_info = 0x58d28;
-define exported symbol ecdsa_info = 0x58d54;
-define exported symbol eckeydh_info = 0x58d80;
-define exported symbol eckey_info = 0x58dac;
-define exported symbol rsa_info = 0x58dd8;
-define exported symbol __rom_bss_start__ = 0x10000000;
-define exported symbol NewVectorTable = 0x10000000;
-define exported symbol UserIrqFunTable = 0x10000100;
-define exported symbol UserIrqDataTable = 0x10000200;
-define exported symbol ConfigDebugClose = 0x10000300;
-define exported symbol CfgSysDebugWarn = 0x10000304;
-define exported symbol CfgSysDebugInfo = 0x10000308;
-define exported symbol CfgSysDebugErr = 0x1000030c;
-define exported symbol ConfigDebugWarn = 0x10000310;
-define exported symbol ConfigDebugInfo = 0x10000314;
-define exported symbol ConfigDebugErr = 0x10000318;
-define exported symbol sector_addr = 0x1000031c;
-define exported symbol _rtl_impure_ptr = 0x10000338;
-define exported symbol ArgvArray = 0x1000033c;
-define exported symbol pUartLogCtl = 0x10000364;
-define exported symbol UartLogBuf = 0x10000368;
-define exported symbol UartLogCtl = 0x100003e8;
-define exported symbol UartLogHistoryBuf = 0x10000408;
-define exported symbol NCO32K_Enable = 0x10000684;
-define exported symbol g_rtl_cipherEngine = 0x100006a0;
-define exported symbol DONGLE_InitStruct = 0x10000ba0;
-define exported symbol EFUSE_MAP = 0x10000ba4;
-define exported symbol USOC_BOOT_TXBD = 0x10000da4;
-define exported symbol USOC_BOOT_RXBD = 0x10000db4;
-define exported symbol USB_RXBuff = 0x10000dc4;
-define exported symbol USB_TXBuff = 0x10000dcc;
-define exported symbol ADC_AnaparAd = 0x10000dd4;
-define exported symbol flash_init_para = 0x10000dec;
-define exported symbol NEW_CALIBREATION_END = 0x10000e44;
-define exported symbol GDMA_Reg = 0x10000e4c;
-define exported symbol PortA_IrqHandler = 0x10000e50;
-define exported symbol PortA_IrqData = 0x10000ed0;
-define exported symbol IC_FS_SCL_HCNT_TRIM = 0x10000f50;
-define exported symbol IC_FS_SCL_LCNT_TRIM = 0x10000f54;
-define exported symbol I2C_SLAVEWRITE_PATCH = 0x10000f58;
-define exported symbol i2s_cur_tx_page = 0x10000f5c;
-define exported symbol i2s_cur_rx_page = 0x10000f60;
-define exported symbol i2s_page_num = 0x10000f64;
-define exported symbol i2s_txpage_entry = 0x10000f68;
-define exported symbol i2s_rxpage_entry = 0x10000f78;
-define exported symbol TXBDAddrAligned = 0x10000f88;
-define exported symbol H2C_Buff = 0x10000f90;
-define exported symbol SPI_RECV_Buff = 0x10000f94;
-define exported symbol spi_boot_recv_done = 0x10000f98;
-define exported symbol UART_StateRx = 0x10000f9c;
-define exported symbol UART_StateTx = 0x10000fa8;
-define exported symbol xMCtrl = 0x10000fb8;
-define exported symbol XComUARTx = 0x10000fc4;
-define exported symbol FalseAlmCnt = 0x10000fc8;
-define exported symbol ROMInfo = 0x10001008;
-define exported symbol DM_CfoTrack = 0x10001020;
-define exported symbol rom_wlan_ram_map = 0x10001048;
-define exported symbol rom_libgloss_ram_map = 0x10001050;
-define exported symbol __rtl_errno = 0x100014b4;
-define exported symbol rom_ssl_ram_map = 0x100014b8;
-define exported symbol __rom_bss_end__ = 0x100014f8;
+define exported symbol __vectors_table = 0x0;
+define exported symbol Reset_Handler = 0x101;
+define exported symbol NMI_Handler = 0x115;
+/*define exported symbol HardFault_Handler = 0x119;*/
+define exported symbol MemManage_Handler = 0x12d;
+define exported symbol BusFault_Handler = 0x131;
+define exported symbol UsageFault_Handler = 0x135;
+define exported symbol VSprintf = 0x201;
+define exported symbol DiagPrintf = 0x4dd;
+define exported symbol DiagSPrintf = 0x509;
+define exported symbol DiagSnPrintf = 0x535;
+define exported symbol prvDiagPrintf = 0x7ed;
+define exported symbol prvDiagSPrintf = 0x821;
+define exported symbol UARTIMG_Write = 0x855;
+define exported symbol UARTIMG_Download = 0x901;
+define exported symbol _memcmp = 0x991;
+define exported symbol _memcpy = 0x9c5;
+define exported symbol _memset = 0xa7d;
+define exported symbol DumpForOneBytes = 0xae9;
+define exported symbol CmdRomHelp = 0xc69;
+define exported symbol CmdDumpWord = 0xccd;
+define exported symbol CmdWriteWord = 0xd7d;
+define exported symbol CmdFlash = 0xdd1;
+define exported symbol CmdEfuse = 0x12c1;
+define exported symbol CmdDumpByte = 0x1775;
+define exported symbol CmdDumpHalfWord = 0x17c9;
+define exported symbol CmdWriteByte = 0x1881;
+define exported symbol SramReadWriteCpy = 0x18c1;
+define exported symbol SramReadWriteTest = 0x19f9;
+define exported symbol CmdSRamTest = 0x1ac9;
+define exported symbol GetRomCmdNum = 0x1b59;
+define exported symbol Rand = 0x1b5d;
+define exported symbol Rand_Arc4 = 0x1bdd;
+define exported symbol RandBytes_Get = 0x1c0d;
+define exported symbol Isspace = 0x1c59;
+define exported symbol Strtoul = 0x1c6d;
+define exported symbol ArrayInitialize = 0x1d15;
+define exported symbol GetArgc = 0x1d29;
+define exported symbol GetArgv = 0x1d55;
+define exported symbol UartLogCmdExecute = 0x1db1;
+define exported symbol UartLogShowBackSpace = 0x1e49;
+define exported symbol UartLogRecallOldCmd = 0x1e7d;
+define exported symbol UartLogHistoryCmd = 0x1eb1;
+define exported symbol UartLogCmdChk = 0x1f2d;
+define exported symbol UartLogIrqHandle = 0x2035;
+define exported symbol RtlConsolInit = 0x2101;
+define exported symbol RtlConsolTaskRom = 0x218d;
+define exported symbol RtlExitConsol = 0x21b9;
+define exported symbol RtlConsolRom = 0x2205;
+define exported symbol BKUP_Write = 0x2249;
+define exported symbol BKUP_Read = 0x226d;
+define exported symbol BKUP_Set = 0x228d;
+define exported symbol BKUP_Clear = 0x22b9;
+define exported symbol NCO32K_Init = 0x22e9;
+define exported symbol EXT32K_Cmd = 0x2349;
+define exported symbol NCO8M_Init = 0x2365;
+define exported symbol NCO8M_Cmd = 0x23bd;
+define exported symbol ISO_Set = 0x23d9;
+define exported symbol PLL0_Set = 0x23f1;
+define exported symbol PLL1_Set = 0x2409;
+define exported symbol PLL2_Set = 0x2421;
+define exported symbol PLL3_Set = 0x2439;
+define exported symbol XTAL0_Set = 0x2451;
+define exported symbol XTAL1_Set = 0x2469;
+define exported symbol XTAL2_Set = 0x2481;
+define exported symbol XTAL_ClkGet = 0x2499;
+define exported symbol CPU_ClkSet = 0x24b1;
+define exported symbol CPU_ClkGet = 0x24c5;
+define exported symbol OSC32K_Calibration = 0x24e5;
+define exported symbol OSC32K_Cmd = 0x25f9;
+define exported symbol OSC8M_Get = 0x2631;
+define exported symbol rtl_cryptoEngine_SrcDesc_Show = 0x2641;
+define exported symbol rtl_cryptoEngine_info = 0x27f1;
+define exported symbol rtl_cryptoEngine_init = 0x2949;
+define exported symbol rtl_crypto_md5_init = 0x2975;
+define exported symbol rtl_crypto_md5_process = 0x29b1;
+define exported symbol rtl_crypto_md5 = 0x2a09;
+define exported symbol rtl_crypto_sha1_init = 0x2a2d;
+define exported symbol rtl_crypto_sha1_process = 0x2a69;
+define exported symbol rtl_crypto_sha1 = 0x2a9d;
+define exported symbol rtl_crypto_sha2_init = 0x2ac1;
+define exported symbol rtl_crypto_sha2_process = 0x2b15;
+define exported symbol rtl_crypto_sha2 = 0x2b4d;
+define exported symbol rtl_crypto_hmac_md5_init = 0x2b71;
+define exported symbol rtl_crypto_hmac_md5_process = 0x2bd1;
+define exported symbol rtl_crypto_hmac_md5 = 0x2c0d;
+define exported symbol rtl_crypto_hmac_sha1_init = 0x2c31;
+define exported symbol rtl_crypto_hmac_sha1_process = 0x2c91;
+define exported symbol rtl_crypto_hmac_sha1 = 0x2cc9;
+define exported symbol rtl_crypto_hmac_sha2_init = 0x2ced;
+define exported symbol rtl_crypto_hmac_sha2_process = 0x2d65;
+define exported symbol rtl_crypto_hmac_sha2 = 0x2da1;
+define exported symbol rtl_crypto_aes_cbc_init = 0x2dc5;
+define exported symbol rtl_crypto_aes_cbc_encrypt = 0x2dfd;
+define exported symbol rtl_crypto_aes_cbc_decrypt = 0x2e45;
+define exported symbol rtl_crypto_aes_ecb_init = 0x2e8d;
+define exported symbol rtl_crypto_aes_ecb_encrypt = 0x2ec5;
+define exported symbol rtl_crypto_aes_ecb_decrypt = 0x2ef5;
+define exported symbol rtl_crypto_aes_ctr_init = 0x2f25;
+define exported symbol rtl_crypto_aes_ctr_encrypt = 0x2f5d;
+define exported symbol rtl_crypto_aes_ctr_decrypt = 0x2f99;
+define exported symbol rtl_crypto_3des_cbc_init = 0x2fd5;
+define exported symbol rtl_crypto_3des_cbc_encrypt = 0x300d;
+define exported symbol rtl_crypto_3des_cbc_decrypt = 0x3055;
+define exported symbol rtl_crypto_3des_ecb_init = 0x309d;
+define exported symbol rtl_crypto_3des_ecb_encrypt = 0x30d5;
+define exported symbol rtl_crypto_3des_ecb_decrypt = 0x311d;
+define exported symbol rtl_crypto_des_cbc_init = 0x3165;
+define exported symbol rtl_crypto_des_cbc_encrypt = 0x319d;
+define exported symbol rtl_crypto_des_cbc_decrypt = 0x31f5;
+define exported symbol rtl_crypto_des_ecb_init = 0x324d;
+define exported symbol rtl_crypto_des_ecb_encrypt = 0x3285;
+define exported symbol rtl_crypto_des_ecb_decrypt = 0x32dd;
+define exported symbol SYSTIMER_Init = 0x3335;
+define exported symbol SYSTIMER_TickGet = 0x33a1;
+define exported symbol SYSTIMER_GetPassTime = 0x33c1;
+define exported symbol DelayNop = 0x3401;
+define exported symbol DelayUs = 0x3411;
+define exported symbol DelayMs = 0x346d;
+define exported symbol USOC_DongleSpecialCmd = 0x3481;
+define exported symbol USOC_DongleCmd = 0x35d9;
+define exported symbol USOC_DongleIsr = 0x35f9;
+define exported symbol USOC_SIE_INTConfig = 0x3621;
+define exported symbol USOC_SIE_INTClear = 0x3639;
+define exported symbol USOC_PHY_Write = 0x3645;
+define exported symbol USOC_PHY_Read = 0x3679;
+define exported symbol USOC_PHY_Autoload = 0x36c1;
+define exported symbol USOC_DongleInit = 0x37a5;
+define exported symbol EFUSE_USER_Read = 0x386d;
+define exported symbol EFUSE_USER1_Read = 0x3971;
+define exported symbol EFUSE_USER2_Read = 0x397d;
+define exported symbol EFUSE_USER3_Read = 0x3989;
+define exported symbol EFUSE_RemainLength = 0x3995;
+define exported symbol EFUSE_USER_Write = 0x3a21;
+define exported symbol EFUSE_USER1_Write = 0x3bb1;
+define exported symbol EFUSE_USER2_Write = 0x3bc1;
+define exported symbol EFUSE_USER3_Write = 0x3bd1;
+define exported symbol EFUSE_OTP_Read1B = 0x3be1;
+define exported symbol EFUSE_OTP_Write1B = 0x3c01;
+define exported symbol EFUSE_OTP_Read32B = 0x3c21;
+define exported symbol EFUSE_OTP_Write32B = 0x3c4d;
+define exported symbol EFUSE_RDP_EN = 0x3cad;
+define exported symbol EFUSE_RDP_KEY = 0x3ccd;
+define exported symbol EFUSE_OTF_KEY = 0x3cf9;
+define exported symbol EFUSE_JTAG_OFF = 0x3d25;
+define exported symbol PAD_DrvStrength = 0x3d45;
+define exported symbol PAD_PullCtrl = 0x3d75;
+define exported symbol Pinmux_Config = 0x3dc5;
+define exported symbol Pinmux_ConfigGet = 0x3dfd;
+define exported symbol Pinmux_Deinit = 0x3e19;
+define exported symbol PINMUX_UART0_Ctrl = 0x3e39;
+define exported symbol PINMUX_UART1_Ctrl = 0x3e81;
+define exported symbol PINMUX_UARTLOG_Ctrl = 0x3ea9;
+define exported symbol PINMUX_SPI0_Ctrl = 0x3ef9;
+define exported symbol PINMUX_SPI1_Ctrl = 0x3f8d;
+define exported symbol PINMUX_SPIF_Ctrl = 0x400d;
+define exported symbol PINMUX_I2C0_Ctrl = 0x406d;
+define exported symbol PINMUX_I2C1_Ctrl = 0x40e1;
+define exported symbol PINMUX_SDIOD_Ctrl = 0x4151;
+define exported symbol PINMUX_I2S0_Ctrl = 0x41e5;
+define exported symbol PINMUX_SWD_Ctrl = 0x4265;
+define exported symbol PINMUX_SWD_OFF = 0x42b5;
+define exported symbol PINMUX_SWD_REG = 0x42d9;
+define exported symbol PINMUX_Ctrl = 0x42fd;
+define exported symbol SOCPS_BackupCPUClk = 0x4391;
+define exported symbol SOCPS_RestoreCPUClk = 0x43b1;
+define exported symbol SOCPS_BootFromPS = 0x43d1;
+define exported symbol SOCPS_TrapPin = 0x43f1;
+define exported symbol SOCPS_ANACKSel = 0x4411;
+define exported symbol SOCPS_CLKCal = 0x442d;
+define exported symbol SOCPS_SetWakeEvent = 0x4485;
+define exported symbol SOCPS_ClearWakeEvent = 0x449d;
+define exported symbol SOCPS_WakePinsCtrl = 0x44a9;
+define exported symbol SOCPS_WakePinCtrl = 0x44d9;
+define exported symbol SOCPS_WakePinClear = 0x4529;
+define exported symbol SOCPS_GetANATimerParam = 0x4539;
+define exported symbol SOCPS_SetANATimer = 0x4575;
+define exported symbol SOCPS_SetReguWakepin = 0x45dd;
+define exported symbol SOCPS_SetReguTimer = 0x4605;
+define exported symbol SOCPS_PWROption = 0x46d9;
+define exported symbol SOCPS_PWROptionExt = 0x46e5;
+define exported symbol SOCPS_PWRMode = 0x46f9;
+define exported symbol SOCPS_SNZMode = 0x4721;
+define exported symbol SOCPS_DeepStandby = 0x473d;
+define exported symbol SOCPS_DeepSleep = 0x4791;
+define exported symbol SDIO_StructInit = 0x47d5;
+define exported symbol SDIO_Init = 0x47f1;
+define exported symbol SDIO_INTClear = 0x486d;
+define exported symbol SDIO_INTConfig = 0x487d;
+define exported symbol SDIO_RPWM1_Get = 0x4895;
+define exported symbol SDIO_RPWM2_Get = 0x48a1;
+define exported symbol SDIO_CPWM1_Set = 0x48ad;
+define exported symbol SDIO_CPWM2_Set = 0x48c1;
+define exported symbol SDIO_RXBD_RPTR_Get = 0x48dd;
+define exported symbol SDIO_RXBD_WPTR_Set = 0x48e9;
+define exported symbol SDIO_TXBD_WPTR_Get = 0x48f5;
+define exported symbol SDIO_TXBD_RPTR_Set = 0x4901;
+define exported symbol SDIO_DMA_Reset = 0x490d;
+define exported symbol BOOT_ROM_Simulation = 0x4919;
+define exported symbol USOC_BOOT_TXBD_Proc = 0x491d;
+define exported symbol USOC_BOOT_Init = 0x4a3d;
+define exported symbol USB_Boot_ROM = 0x4aa9;
+define exported symbol USOC_CH_Cmd = 0x4b59;
+define exported symbol USOC_Cmd = 0x4bb1;
+define exported symbol USOC_PHY_Cmd = 0x4bf5;
+define exported symbol USOC_MODE_Cfg = 0x4c09;
+define exported symbol USOC_TXBD_SWIDX_Cfg = 0x4c25;
+define exported symbol USOC_TXBD_SWIDX_Get = 0x4c2d;
+define exported symbol USOC_TXBD_HWIDX_Get = 0x4c35;
+define exported symbol USOC_RXBD_HWIDX_Get = 0x4c3d;
+define exported symbol USOC_RXBD_SWIDX_Cfg = 0x4c45;
+define exported symbol USOC_RXBD_SWIDX_Get = 0x4c4d;
+define exported symbol USOC_StructInit = 0x4c55;
+define exported symbol USOC_Init = 0x4c85;
+define exported symbol USOC_SW_RST = 0x4d7d;
+define exported symbol USOC_INTCfg = 0x4d91;
+define exported symbol USOC_INTClr = 0x4d95;
+define exported symbol USOC_INTGet = 0x4d9d;
+define exported symbol USOC_MIT_Cfg = 0x4da1;
+define exported symbol USOC_TXSTUCK_Cfg = 0x4dc5;
+define exported symbol USOC_RXSTUCK_Cfg = 0x4de9;
+define exported symbol USOC_POWER_On = 0x4e0d;
+define exported symbol ADC_RXGDMA_Init = 0x4e9d;
+define exported symbol ADC_SetAudio = 0x4f45;
+define exported symbol ADC_SetAnalog = 0x4f61;
+define exported symbol ADC_Cmd = 0x4fbd;
+define exported symbol ADC_INTConfig = 0x5031;
+define exported symbol ADC_SetOneShot = 0x5049;
+define exported symbol ADC_SetComp = 0x50fd;
+define exported symbol ADC_INTClear = 0x517d;
+define exported symbol ADC_INTClearPendingBits = 0x5189;
+define exported symbol ADC_GetISR = 0x5195;
+define exported symbol ADC_Read = 0x51a1;
+define exported symbol ADC_ReceiveBuf = 0x51ad;
+define exported symbol ADC_InitStruct = 0x5205;
+define exported symbol ADC_Init = 0x524d;
+define exported symbol BOOT_ROM_ShowBuildInfo = 0x52ed;
+define exported symbol BOOT_ROM_OTFCheck = 0x5335;
+define exported symbol BOOT_ROM_InitFlash = 0x5345;
+define exported symbol BOOT_ROM_FromFlash = 0x5405;
+define exported symbol BOOT_ROM_InitUsb = 0x5511;
+define exported symbol BOOT_ROM_Process = 0x553d;
+define exported symbol BOOT_ROM_InitDebugFlg = 0x5605;
+define exported symbol HalResetVsr = 0x5639;
+define exported symbol Cache_Enable = 0x5811;
+define exported symbol Cache_Flush = 0x5831;
+define exported symbol Cache_Debug = 0x5851;
+define exported symbol CRYPTO_AlignToBe32 = 0x58bd;
+define exported symbol CRYPTO_MemDump = 0x58d5;
+define exported symbol CRYPTO_GetAESKey = 0x599d;
+define exported symbol CRYPTO_SetAESKey = 0x5cb5;
+define exported symbol CRYPTO_SetSecurityMode = 0x5d29;
+define exported symbol CRYPTO_Init = 0x5f5d;
+define exported symbol CRYPTO_DeInit = 0x60b9;
+define exported symbol CRYPTO_Reset = 0x6101;
+define exported symbol CRYPTO_Process = 0x6129;
+define exported symbol CRYPTO_CipherInit = 0x6a11;
+define exported symbol CRYPTO_CipherEncrypt = 0x6a35;
+define exported symbol CRYPTO_CipherDecrypt = 0x6a61;
+define exported symbol CRYPTO_SetCheckSumEn = 0x6a95;
+define exported symbol CRYPTO_GetCheckSumData = 0x6ab1;
+define exported symbol LOGUART_StructInit = 0x6abd;
+define exported symbol LOGUART_Init = 0x6ad5;
+define exported symbol LOGUART_PutChar = 0x6b15;
+define exported symbol LOGUART_GetChar = 0x6b49;
+define exported symbol LOGUART_GetIMR = 0x6b65;
+define exported symbol LOGUART_SetIMR = 0x6b71;
+define exported symbol LOGUART_WaitBusy = 0x6b7d;
+define exported symbol DIAG_UartInit = 0x6b9d;
+define exported symbol DIAG_UartReInit = 0x6c25;
+define exported symbol EFUSE_PowerSwitchROM = 0x6c49;
+define exported symbol EFUSE_OneByteReadROM = 0x6d65;
+define exported symbol EFUSE_OneByteWriteROM = 0x6e0d;
+define exported symbol EFUSE_PG_Packet = 0x6e29;
+define exported symbol EFUSE_LogicalMap_Read = 0x7091;
+define exported symbol EFUSE_LogicalMap_Write = 0x71f5;
+define exported symbol FLASH_SetSpiMode = 0x73dd;
+define exported symbol FLASH_RxCmd = 0x7465;
+define exported symbol FLASH_WaitBusy = 0x74cd;
+define exported symbol FLASH_RxData = 0x754d;
+define exported symbol FLASH_TxCmd = 0x75cd;
+define exported symbol FLASH_WriteEn = 0x763d;
+define exported symbol FLASH_TxData12B = 0x7661;
+define exported symbol FLASH_SetStatus = 0x7735;
+define exported symbol FLASH_Erase = 0x7755;
+define exported symbol FLASH_DeepPowerDown = 0x77f5;
+define exported symbol FLASH_SetStatusBits = 0x784d;
+define exported symbol FLASH_Calibration = 0x791d;
+define exported symbol FLASH_StructInit_Micron = 0x7a65;
+define exported symbol FLASH_StructInit_MXIC = 0x7af5;
+define exported symbol FLASH_StructInit_GD = 0x7b81;
+define exported symbol FLASH_StructInit = 0x7c11;
+define exported symbol FLASH_Init = 0x7ca1;
+define exported symbol FLASH_ClockDiv = 0x7d15;
+define exported symbol FLASH_CalibrationInit = 0x7d99;
+define exported symbol FLASH_Calibration500MPSCmd = 0x7db1;
+define exported symbol FLASH_CalibrationPhase = 0x7dcd;
+define exported symbol FLASH_CalibrationPhaseIdx = 0x7e59;
+define exported symbol FLASH_CalibrationNewCmd = 0x7e6d;
+define exported symbol FLASH_CalibrationNew = 0x7ea9;
+define exported symbol GDMA_StructInit = 0x80dd;
+define exported symbol GDMA_SetLLP = 0x80f9;
+define exported symbol GDMA_ClearINTPendingBit = 0x8191;
+define exported symbol GDMA_ClearINT = 0x81d5;
+define exported symbol GDMA_INTConfig = 0x8211;
+define exported symbol GDMA_Cmd = 0x8259;
+define exported symbol GDMA_Init = 0x828d;
+define exported symbol GDMA_ChCleanAutoReload = 0x83c1;
+define exported symbol GDMA_SetSrcAddr = 0x83f9;
+define exported symbol GDMA_GetSrcAddr = 0x8411;
+define exported symbol GDMA_GetDstAddr = 0x8429;
+define exported symbol GDMA_SetDstAddr = 0x843d;
+define exported symbol GDMA_SetBlkSize = 0x8459;
+define exported symbol GDMA_GetBlkSize = 0x8489;
+define exported symbol GDMA_ChnlRegister = 0x84a1;
+define exported symbol GDMA_ChnlUnRegister = 0x8529;
+define exported symbol GDMA_ChnlAlloc = 0x8591;
+define exported symbol GDMA_ChnlFree = 0x8615;
+define exported symbol GPIO_INTMode = 0x864d;
+define exported symbol GPIO_INTConfig = 0x86e5;
+define exported symbol GPIO_INTHandler = 0x8725;
+define exported symbol GPIO_Direction = 0x8771;
+define exported symbol GPIO_Init = 0x87a1;
+define exported symbol GPIO_DeInit = 0x886d;
+define exported symbol GPIO_ReadDataBit = 0x88c9;
+define exported symbol GPIO_WriteBit = 0x88ed;
+define exported symbol GPIO_PortDirection = 0x891d;
+define exported symbol GPIO_PortRead = 0x893d;
+define exported symbol GPIO_PortWrite = 0x894d;
+define exported symbol GPIO_UserRegIrq = 0x8969;
+define exported symbol I2C_StructInit = 0x899d;
+define exported symbol I2C_SetSpeed = 0x89e5;
+define exported symbol I2C_SetSlaveAddress = 0x8b3d;
+define exported symbol I2C_CheckFlagState = 0x8b79;
+define exported symbol I2C_INTConfig = 0x8bad;
+define exported symbol I2C_ClearINT = 0x8be5;
+define exported symbol I2C_ClearAllINT = 0x8c85;
+define exported symbol I2C_Init = 0x8cad;
+define exported symbol I2C_GetRawINT = 0x8dc9;
+define exported symbol I2C_GetINT = 0x8df1;
+define exported symbol I2C_MasterSendNullData = 0x8e19;
+define exported symbol I2C_MasterSend = 0x8e65;
+define exported symbol I2C_SlaveSend = 0x8ead;
+define exported symbol I2C_ReceiveData = 0x8ed9;
+define exported symbol I2C_MasterWrite = 0x8f05;
+define exported symbol I2C_MasterReadDW = 0x8f89;
+define exported symbol I2C_MasterRead = 0x9019;
+define exported symbol I2C_SlaveWrite = 0x9089;
+define exported symbol I2C_SlaveRead = 0x90f1;
+define exported symbol I2C_MasterRepeatRead = 0x9141;
+define exported symbol I2C_Cmd = 0x91c1;
+define exported symbol I2C_PinMuxInit = 0x91fd;
+define exported symbol I2C_PinMuxDeInit = 0x9255;
+define exported symbol I2C_DMAControl = 0x92ad;
+define exported symbol I2C_DmaMode1Config = 0x92e9;
+define exported symbol I2C_DmaMode2Config = 0x9331;
+define exported symbol I2C_TXGDMA_Init = 0x9375;
+define exported symbol I2C_RXGDMA_Init = 0x9459;
+define exported symbol I2C_Sleep_Cmd = 0x9521;
+define exported symbol I2C_WakeUp = 0x95a1;
+define exported symbol I2S_StructInit = 0x95e9;
+define exported symbol I2S_Cmd = 0x9611;
+define exported symbol I2S_TxDmaCmd = 0x962d;
+define exported symbol I2S_RxDmaCmd = 0x9641;
+define exported symbol I2S_INTConfig = 0x9655;
+define exported symbol I2S_INTClear = 0x965d;
+define exported symbol I2S_INTClearAll = 0x9665;
+define exported symbol I2S_Init = 0x9671;
+define exported symbol I2S_ISRGet = 0x97a9;
+define exported symbol I2S_SetRate = 0x97b5;
+define exported symbol I2S_SetWordLen = 0x9811;
+define exported symbol I2S_SetChNum = 0x9839;
+define exported symbol I2S_SetPageNum = 0x9861;
+define exported symbol I2S_SetPageSize = 0x9895;
+define exported symbol I2S_GetPageSize = 0x98a9;
+define exported symbol I2S_SetDirection = 0x98b5;
+define exported symbol I2S_SetDMABuf = 0x98dd;
+define exported symbol I2S_TxPageBusy = 0x9905;
+define exported symbol I2S_GetTxPage = 0x9911;
+define exported symbol I2S_GetRxPage = 0x991d;
+define exported symbol I2S_SetTxPageAddr = 0x9929;
+define exported symbol I2S_GetTxPageAddr = 0x9939;
+define exported symbol I2S_SetRxPageAddr = 0x9949;
+define exported symbol I2S_GetRxPageAddr = 0x9959;
+define exported symbol I2S_TxPageDMA_EN = 0x9969;
+define exported symbol I2S_RxPageDMA_EN = 0x998d;
+define exported symbol io_assert_failed = 0x99d9;
+define exported symbol OTF_init = 0x99fd;
+define exported symbol OTF_Cmd = 0x9a79;
+define exported symbol OTF_Mask = 0x9a8d;
+define exported symbol KEY_Request = 0x9add;
+define exported symbol RDP_EN_Request = 0x9b21;
+define exported symbol RCC_PeriphClockCmd = 0x9b65;
+define exported symbol FUNC_HCI_COM = 0x9c95;
+define exported symbol RTC_ByteToBcd2 = 0x9cad;
+define exported symbol RTC_Bcd2ToByte = 0x9cc9;
+define exported symbol RTC_ClokSource = 0x9cdd;
+define exported symbol RTC_EnterInitMode = 0x9d19;
+define exported symbol RTC_ExitInitMode = 0x9d51;
+define exported symbol RTC_WaitForSynchro = 0x9d61;
+define exported symbol RTC_BypassShadowCmd = 0x9da9;
+define exported symbol RTC_StructInit = 0x9dd9;
+define exported symbol RTC_Init = 0x9de5;
+define exported symbol RTC_TimeStructInit = 0x9e7d;
+define exported symbol RTC_SetTime = 0x9e8d;
+define exported symbol RTC_GetTime = 0x9ff9;
+define exported symbol RTC_SetAlarm = 0xa051;
+define exported symbol RTC_AlarmStructInit = 0xa211;
+define exported symbol RTC_GetAlarm = 0xa231;
+define exported symbol RTC_AlarmCmd = 0xa2a1;
+define exported symbol RTC_AlarmClear = 0xa2f5;
+define exported symbol RTC_DayLightSavingConfig = 0xa305;
+define exported symbol RTC_GetStoreOperation = 0xa355;
+define exported symbol RTC_OutputConfig = 0xa365;
+define exported symbol RTC_SmoothCalibConfig = 0xa39d;
+define exported symbol SDIO_IsTimeout = 0xa459;
+define exported symbol SDIOB_Init = 0xa481;
+define exported symbol SDIOB_INTConfig = 0xa575;
+define exported symbol SDIOB_DeInit = 0xa591;
+define exported symbol SDIOB_H2C_WriteMem = 0xa5d9;
+define exported symbol SDIOB_H2C_SetMem = 0xa605;
+define exported symbol SDIOB_H2C_DataHandle = 0xa631;
+define exported symbol SDIOB_H2C_DataReady = 0xa73d;
+define exported symbol SDIOB_IRQ_Handler_BH = 0xa80d;
+define exported symbol SDIOB_H2C_Task = 0xa8c9;
+define exported symbol SDIO_Boot_Up = 0xa8e5;
+define exported symbol SPI_DmaInit = 0xa91d;
+define exported symbol SPI_DataHandle = 0xa9d1;
+define exported symbol SPI_Boot_DmaRxIrqHandle = 0xaa01;
+define exported symbol SPI_Boot_ROM = 0xaa5d;
+define exported symbol SSI_StructInit = 0xabbd;
+define exported symbol SSI_Cmd = 0xabf5;
+define exported symbol SSI_INTConfig = 0xac09;
+define exported symbol SSI_SetSclkPolarity = 0xac19;
+define exported symbol SSI_SetSclkPhase = 0xac3d;
+define exported symbol SSI_SetDataFrameSize = 0xac61;
+define exported symbol SSI_SetReadLen = 0xac81;
+define exported symbol SSI_SetBaudDiv = 0xacb1;
+define exported symbol SSI_SetBaud = 0xaccd;
+define exported symbol SSI_SetDmaEnable = 0xad2d;
+define exported symbol SSI_SetDmaLevel = 0xad41;
+define exported symbol SSI_SetIsrClean = 0xad49;
+define exported symbol SSI_WriteData = 0xad65;
+define exported symbol SSI_SetRxFifoLevel = 0xad6d;
+define exported symbol SSI_SetTxFifoLevel = 0xad71;
+define exported symbol SSI_ReadData = 0xad75;
+define exported symbol SSI_GetRxCount = 0xad79;
+define exported symbol SSI_GetTxCount = 0xad81;
+define exported symbol SSI_GetStatus = 0xad89;
+define exported symbol SSI_Writeable = 0xad8d;
+define exported symbol SSI_Readable = 0xad9d;
+define exported symbol SSI_GetDataFrameSize = 0xadad;
+define exported symbol SSI_TXGDMA_Init = 0xadb9;
+define exported symbol SSI_RXGDMA_Init = 0xaef9;
+define exported symbol SSI_ReceiveData = 0xb021;
+define exported symbol SSI_SendData = 0xb0b9;
+define exported symbol SSI_Busy = 0xb165;
+define exported symbol SSI_SetSlaveEnable = 0xb175;
+define exported symbol SSI_Init = 0xb1ad;
+define exported symbol SSI_GetIsr = 0xb235;
+define exported symbol SSI_GetRawIsr = 0xb239;
+define exported symbol SSI_GetSlaveEnable = 0xb23d;
+define exported symbol SSI_PinmuxInit = 0xb241;
+define exported symbol SSI_PinmuxDeInit = 0xb2a9;
+define exported symbol SYSCFG0_Get = 0xb311;
+define exported symbol SYSCFG0_CUTVersion = 0xb31d;
+define exported symbol SYSCFG0_BDOption = 0xb32d;
+define exported symbol SYSCFG1_Get = 0xb33d;
+define exported symbol SYSCFG1_AutoLoadDone = 0xb349;
+define exported symbol SYSCFG1_TRP_LDOMode = 0xb359;
+define exported symbol SYSCFG1_TRP_UARTImage = 0xb369;
+define exported symbol SYSCFG1_TRP_ICFG = 0xb37d;
+define exported symbol SYSCFG2_Get = 0xb389;
+define exported symbol SYSCFG2_ROMINFO_Get = 0xb395;
+define exported symbol SYSCFG2_ROMINFO_Set = 0xb3a1;
+define exported symbol RTIM_TimeBaseStructInit = 0xb3b5;
+define exported symbol RTIM_Cmd = 0xb3cd;
+define exported symbol RTIM_GetCount = 0xb42d;
+define exported symbol RTIM_UpdateDisableConfig = 0xb475;
+define exported symbol RTIM_ARRPreloadConfig = 0xb4c5;
+define exported symbol RTIM_UpdateRequestConfig = 0xb515;
+define exported symbol RTIM_PrescalerConfig = 0xb575;
+define exported symbol RTIM_GenerateEvent = 0xb5a1;
+define exported symbol RTIM_ChangePeriod = 0xb5f9;
+define exported symbol RTIM_Reset = 0xb64d;
+define exported symbol RTIM_CCStructInit = 0xb68d;
+define exported symbol RTIM_CCxInit = 0xb6a1;
+define exported symbol RTIM_CCRxMode = 0xb749;
+define exported symbol RTIM_CCRxSet = 0xb785;
+define exported symbol RTIM_CCRxGet = 0xb7dd;
+define exported symbol RTIM_OCxPreloadConfig = 0xb80d;
+define exported symbol RTIM_CCxPolarityConfig = 0xb85d;
+define exported symbol RTIM_CCxCmd = 0xb8ad;
+define exported symbol RTIM_SetOnePulseOutputMode = 0xb901;
+define exported symbol RTIM_DMACmd = 0xb959;
+define exported symbol RTIM_TXGDMA_Init = 0xb9a9;
+define exported symbol RTIM_RXGDMA_Init = 0xba5d;
+define exported symbol RTIM_INTConfig = 0xbb3d;
+define exported symbol RTIM_INTClear = 0xbba9;
+define exported symbol RTIM_TimeBaseInit = 0xbbed;
+define exported symbol RTIM_DeInit = 0xbced;
+define exported symbol RTIM_INTClearPendingBit = 0xbd41;
+define exported symbol RTIM_GetFlagStatus = 0xbd81;
+define exported symbol RTIM_GetINTStatus = 0xbded;
+define exported symbol UART_DeInit = 0xbe61;
+define exported symbol UART_StructInit = 0xbe69;
+define exported symbol UART_BaudParaGet = 0xbe81;
+define exported symbol UART_BaudParaGetFull = 0xbec9;
+define exported symbol UART_SetBaud = 0xbf01;
+define exported symbol UART_SetBaudExt = 0xbf71;
+define exported symbol UART_SetRxLevel = 0xbfc1;
+define exported symbol UART_RxCmd = 0xbfe9;
+define exported symbol UART_Writable = 0xbffd;
+define exported symbol UART_Readable = 0xc005;
+define exported symbol UART_CharPut = 0xc00d;
+define exported symbol UART_CharGet = 0xc011;
+define exported symbol UART_ReceiveData = 0xc019;
+define exported symbol UART_SendData = 0xc041;
+define exported symbol UART_ReceiveDataTO = 0xc069;
+define exported symbol UART_SendDataTO = 0xc0a9;
+define exported symbol UART_RxByteCntClear = 0xc0e9;
+define exported symbol UART_RxByteCntGet = 0xc0f5;
+define exported symbol UART_BreakCtl = 0xc0fd;
+define exported symbol UART_ClearRxFifo = 0xc111;
+define exported symbol UART_Init = 0xc135;
+define exported symbol UART_ClearTxFifo = 0xc1d1;
+define exported symbol UART_INTConfig = 0xc1dd;
+define exported symbol UART_IntStatus = 0xc1ed;
+define exported symbol UART_ModemStatusGet = 0xc1f1;
+define exported symbol UART_LineStatusGet = 0xc1f5;
+define exported symbol UART_WaitBusy = 0xc1f9;
+define exported symbol UART_PinMuxInit = 0xc221;
+define exported symbol UART_PinMuxDeinit = 0xc289;
+define exported symbol UART_TXDMAConfig = 0xc2f1;
+define exported symbol UART_RXDMAConfig = 0xc301;
+define exported symbol UART_TXDMACmd = 0xc315;
+define exported symbol UART_RXDMACmd = 0xc329;
+define exported symbol UART_TXGDMA_Init = 0xc33d;
+define exported symbol UART_RXGDMA_Init = 0xc425;
+define exported symbol UART_LPRxStructInit = 0xc501;
+define exported symbol UART_LPRxInit = 0xc50d;
+define exported symbol UART_LPRxBaudSet = 0xc575;
+define exported symbol UART_LPRxMonitorCmd = 0xc5f1;
+define exported symbol UART_LPRxpathSet = 0xc62d;
+define exported symbol UART_LPRxIPClockSet = 0xc641;
+define exported symbol UART_LPRxCmd = 0xc6b1;
+define exported symbol UART_LPRxMonBaudCtrlRegGet = 0xc6c5;
+define exported symbol UART_LPRxMonitorSatusGet = 0xc6c9;
+define exported symbol UART_IrDAStructInit = 0xc6cd;
+define exported symbol UART_IrDAInit = 0xc6e5;
+define exported symbol UART_IrDACmd = 0xc7bd;
+define exported symbol INT_SysOn = 0xc7d1;
+define exported symbol INT_Wdg = 0xc811;
+define exported symbol INT_Timer0 = 0xc855;
+define exported symbol INT_Timer1 = 0xc899;
+define exported symbol INT_Timer2 = 0xc8dd;
+define exported symbol INT_Timer3 = 0xc921;
+define exported symbol INT_SPI0 = 0xc965;
+define exported symbol INT_GPIO = 0xc9a9;
+define exported symbol INT_Uart0 = 0xc9ed;
+define exported symbol INT_SPIFlash = 0xca31;
+define exported symbol INT_Uart1 = 0xca75;
+define exported symbol INT_Timer4 = 0xcab9;
+define exported symbol INT_I2S0 = 0xcafd;
+define exported symbol INT_Timer5 = 0xcb41;
+define exported symbol INT_WlDma = 0xcb85;
+define exported symbol INT_WlProtocol = 0xcbc9;
+define exported symbol INT_IPSEC = 0xcc0d;
+define exported symbol INT_SPI1 = 0xcc51;
+define exported symbol INT_Peripheral = 0xcc95;
+define exported symbol INT_Gdma0Ch0 = 0xccd9;
+define exported symbol INT_Gdma0Ch1 = 0xcd1d;
+define exported symbol INT_Gdma0Ch2 = 0xcd61;
+define exported symbol INT_Gdma0Ch3 = 0xcda5;
+define exported symbol INT_Gdma0Ch4 = 0xcde9;
+define exported symbol INT_Gdma0Ch5 = 0xce2d;
+define exported symbol INT_I2C0 = 0xce71;
+define exported symbol INT_I2C1 = 0xceb5;
+define exported symbol INT_Uartlog = 0xcef9;
+define exported symbol INT_ADC = 0xcf3d;
+define exported symbol INT_RDP = 0xcf81;
+define exported symbol INT_RTC = 0xcfc5;
+define exported symbol INT_Gdma1Ch0 = 0xd009;
+define exported symbol INT_Gdma1Ch1 = 0xd051;
+define exported symbol INT_Gdma1Ch2 = 0xd099;
+define exported symbol INT_Gdma1Ch3 = 0xd0e1;
+define exported symbol INT_Gdma1Ch4 = 0xd129;
+define exported symbol INT_Gdma1Ch5 = 0xd171;
+define exported symbol INT_USB = 0xd1b9;
+define exported symbol INT_RXI300 = 0xd201;
+define exported symbol INT_USB_SIE = 0xd249;
+define exported symbol INT_SdioD = 0xd291;
+define exported symbol INT_NMI = 0xd2d1;
+define exported symbol INT_HardFault = 0xd305;
+define exported symbol INT_MemManage = 0xd4b5;
+define exported symbol INT_BusFault = 0xd4d5;
+define exported symbol INT_UsageFault = 0xd4f5;
+define exported symbol VECTOR_TableInit = 0xd515;
+define exported symbol VECTOR_TableInitForOS = 0xd6c5;
+define exported symbol VECTOR_IrqRegister = 0xd6d5;
+define exported symbol VECTOR_IrqUnRegister = 0xd6f9;
+define exported symbol VECTOR_IrqEn = 0xd715;
+define exported symbol VECTOR_IrqDis = 0xd765;
+define exported symbol WDG_Scalar = 0xd7a1;
+define exported symbol WDG_Init = 0xd7e1;
+define exported symbol WDG_IrqClear = 0xd7fd;
+define exported symbol WDG_IrqInit = 0xd80d;
+define exported symbol WDG_Cmd = 0xd83d;
+define exported symbol WDG_Refresh = 0xd85d;
+define exported symbol _strncpy = 0xd86d;
+define exported symbol _strcpy = 0xd889;
+define exported symbol prvStrCpy = 0xd899;
+define exported symbol _strlen = 0xd8b1;
+define exported symbol _strnlen = 0xd8c9;
+define exported symbol prvStrLen = 0xd8fd;
+define exported symbol _strcmp = 0xd919;
+define exported symbol _strncmp = 0xd939;
+define exported symbol prvStrCmp = 0xd985;
+define exported symbol StrUpr = 0xd9b5;
+define exported symbol prvAtoi = 0xd9d1;
+define exported symbol prvStrtok = 0xda29;
+define exported symbol prvStrStr = 0xda81;
+define exported symbol _strsep = 0xdab9;
+define exported symbol skip_spaces = 0xdaf5;
+define exported symbol skip_atoi = 0xdb11;
+define exported symbol _parse_integer_fixup_radix = 0xdb49;
+define exported symbol _parse_integer = 0xdb9d;
+define exported symbol simple_strtoull = 0xdc01;
+define exported symbol simple_strtoll = 0xdc21;
+define exported symbol simple_strtoul = 0xdc41;
+define exported symbol simple_strtol = 0xdc49;
+define exported symbol _vsscanf = 0xdc61;
+define exported symbol _sscanf = 0xe1c9;
+define exported symbol div_u64 = 0xe1e5;
+define exported symbol div_s64 = 0xe1ed;
+define exported symbol div_u64_rem = 0xe1f5;
+define exported symbol div_s64_rem = 0xe205;
+define exported symbol _strpbrk = 0xe215;
+define exported symbol _strchr = 0xe241;
+define exported symbol COMMPORT_GET_T = 0xe259;
+define exported symbol COMMPORT_CLEAN_RX = 0xe289;
+define exported symbol xModemDebugInit = 0xe2a5;
+define exported symbol xModemDebug = 0xe2dd;
+define exported symbol xModemInquiry = 0xe315;
+define exported symbol xModemGetFirst = 0xe339;
+define exported symbol xModemGetOthers = 0xe45d;
+define exported symbol xModemRxFrame = 0xe691;
+define exported symbol xModemHandshake = 0xe6d5;
+define exported symbol xModemRxBuffer = 0xe945;
+define exported symbol xmodem_log_close = 0xe9f5;
+define exported symbol xmodem_log_open = 0xea01;
+define exported symbol xmodem_uart_init = 0xea39;
+define exported symbol xmodem_uart_deinit = 0xeb25;
+define exported symbol xmodem_uart_port_init = 0xeb35;
+define exported symbol xmodem_uart_port_deinit = 0xeb99;
+define exported symbol xmodem_uart_readable = 0xebdd;
+define exported symbol xmodem_uart_writable = 0xebf5;
+define exported symbol xmodem_uart_getc = 0xec0d;
+define exported symbol xmodem_uart_putc = 0xec35;
+define exported symbol xmodem_uart_putdata = 0xec49;
+define exported symbol aes_set_key = 0xec65;
+define exported symbol aes_encrypt = 0xf021;
+define exported symbol aes_decrypt = 0x10171;
+define exported symbol AES_WRAP = 0x112b1;
+define exported symbol AES_UnWRAP = 0x113fd;
+define exported symbol crc32_get = 0x11549;
+define exported symbol arc4_byte = 0x1157d;
+define exported symbol rt_arc4_init = 0x115a5;
+define exported symbol rt_arc4_crypt = 0x115e9;
+define exported symbol rt_md5_init = 0x11df5;
+define exported symbol rt_md5_append = 0x11e25;
+define exported symbol rt_md5_final = 0x11ec9;
+define exported symbol rt_md5_hmac = 0x11f21;
+define exported symbol RC4 = 0x12061;
+define exported symbol RC4_set_key = 0x1238d;
+define exported symbol ROM_WIFI_ReadPowerValue = 0x1246d;
+define exported symbol ROM_WIFI_EfuseParseTxPowerInfo = 0x1251d;
+define exported symbol ROM_WIFI_8051Reset = 0x125c5;
+define exported symbol ROM_WIFI_FWDownloadEnable = 0x125dd;
+define exported symbol ROM_WIFI_BlockWrite = 0x12619;
+define exported symbol ROM_WIFI_PageWrite = 0x12661;
+define exported symbol ROM_WIFI_FillDummy = 0x12685;
+define exported symbol ROM_WIFI_WriteFW = 0x126b1;
+define exported symbol ROM_WIFI_FWFreeToGo = 0x1275d;
+define exported symbol ROM_WIFI_InitLLTTable = 0x127f9;
+define exported symbol ROM_WIFI_GetChnlGroup = 0x12879;
+define exported symbol ROM_WIFI_BWMapping = 0x129f1;
+define exported symbol ROM_WIFI_SCMapping = 0x12a19;
+define exported symbol ROM_WIFI_FillTxdescSectype = 0x12a99;
+define exported symbol ROM_WIFI_FillFakeTxdesc = 0x12ab9;
+define exported symbol ROM_WIFI_32K_Cmd = 0x12b91;
+define exported symbol ROM_WIFI_DISCONNECT = 0x12bc1;
+define exported symbol ROM_WIFI_SET_TSF = 0x12bfd;
+define exported symbol ROM_WIFI_BCN_FUNC = 0x12ca5;
+define exported symbol ROM_WIFI_BSSID_SET = 0x12ccd;
+define exported symbol ROM_WIFI_MACADDR_SET = 0x12d09;
+define exported symbol ROM_WIFI_EnableInterrupt = 0x12d39;
+define exported symbol ROM_WIFI_DisableInterrupt = 0x12d4d;
+define exported symbol ROM_WIFI_RESUME_TxBeacon = 0x12d61;
+define exported symbol ROM_WIFI_STOP_TXBeacon = 0x12d91;
+define exported symbol ROM_WIFI_BCN_Interval = 0x12dc1;
+define exported symbol ROM_WIFI_BCN_FUNC_Enable = 0x12dcd;
+define exported symbol ROM_WIFI_INIT_BeaconParameters = 0x12de5;
+define exported symbol ROM_WIFI_MEDIA_STATUS1 = 0x12e35;
+define exported symbol ROM_WIFI_MEDIA_STATUS = 0x12e4d;
+define exported symbol ROM_WIFI_SetBrateCfg = 0x12e61;
+define exported symbol ROM_WIFI_BASIC_RATE = 0x12f69;
+define exported symbol ROM_WIFI_CHECK_BSSID = 0x12fc9;
+define exported symbol ROM_WIFI_RESP_SIFS = 0x12fe9;
+define exported symbol ROM_WIFI_CAM_WRITE = 0x13001;
+define exported symbol ROM_WIFI_ACM_CTRL = 0x13021;
+define exported symbol ROM_WIFI_FIFO_CLEARN_UP = 0x13051;
+define exported symbol ROM_WIFI_CHECK_TXBUF = 0x130b9;
+define exported symbol ROM_WIFI_BCN_VALID = 0x130fd;
+define exported symbol ROM_WIFI_PROMISC_Cmd = 0x13119;
+define exported symbol ROM_WIFI_SetOpmodeAP = 0x13189;
+define exported symbol ROM_WIFI_ReadChipVersion = 0x132a9;
+define exported symbol ROM_WIFI_DumpChipInfo = 0x1330d;
+define exported symbol ROM_WIFI_InitLxDma = 0x135b1;
+define exported symbol ROM_WIFI_InitQueueReservedPage = 0x13671;
+define exported symbol ROM_WIFI_InitTxBufferBoundary = 0x136f1;
+define exported symbol ROM_WIFI_InitNormalChipRegPriority = 0x1373d;
+define exported symbol ROM_WIFI_InitPageBoundary = 0x13789;
+define exported symbol ROM_WIFI_InitTransferPageSize = 0x13795;
+define exported symbol ROM_WIFI_InitDriverInfoSize = 0x137a1;
+define exported symbol ROM_WIFI_InitNetworkType = 0x137ad;
+define exported symbol ROM_WIFI_InitRCR = 0x137c5;
+define exported symbol ROM_WIFI_InitAdaptiveCtrl = 0x13805;
+define exported symbol ROM_WIFI_InitSIFS = 0x1383d;
+define exported symbol ROM_WIFI_InitEDCA = 0x13865;
+define exported symbol ROM_WIFI_InitRateFallback = 0x138a1;
+define exported symbol ROM_WIFI_InitRetryFunction = 0x138c9;
+define exported symbol ROM_WIFI_InitOperationMode = 0x138e5;
+define exported symbol ROM_WIFI_InitBurstPktLen = 0x138f9;
+define exported symbol phy_CalculateBitShift = 0x13905;
+define exported symbol PHY_SetBBReg_8711B = 0x1391d;
+define exported symbol PHY_QueryBBReg_8711B = 0x13921;
+define exported symbol ROM_odm_QueryRxPwrPercentage = 0x13925;
+define exported symbol ROM_odm_EVMdbToPercentage = 0x13931;
+define exported symbol ROM_odm_SignalScaleMapping_8711B = 0x13935;
+define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x13a11;
+define exported symbol ROM_odm_SetEDCCAThreshold = 0x13d39;
+define exported symbol ROM_odm_SetTRxMux = 0x13d61;
+define exported symbol ROM_odm_SetCrystalCap = 0x13d89;
+define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x13ded;
+define exported symbol ROM_ODM_CfoTrackingReset = 0x13dfd;
+define exported symbol ROM_odm_CfoTrackingFlow = 0x13e21;
+define exported symbol rtw_get_bit_value_from_ieee_value = 0x14045;
+define exported symbol rtw_is_cckrates_included = 0x14071;
+define exported symbol rtw_is_cckratesonly_included = 0x140a5;
+define exported symbol rtw_check_network_type = 0x140cd;
+define exported symbol rtw_set_fixed_ie = 0x14155;
+define exported symbol rtw_set_ie = 0x14175;
+define exported symbol rtw_get_ie = 0x141a1;
+define exported symbol rtw_set_supported_rate = 0x141b5;
+define exported symbol rtw_get_rateset_len = 0x14229;
+define exported symbol rtw_get_wpa_ie = 0x14245;
+define exported symbol rtw_get_wpa2_ie = 0x142d1;
+define exported symbol rtw_get_wpa_cipher_suite = 0x142e5;
+define exported symbol rtw_get_wpa2_cipher_suite = 0x1434d;
+define exported symbol rtw_parse_wpa_ie = 0x143b5;
+define exported symbol rtw_parse_wpa2_ie = 0x14481;
+define exported symbol rtw_get_sec_ie = 0x14535;
+define exported symbol rtw_get_wps_ie = 0x145e5;
+define exported symbol rtw_get_wps_attr = 0x14659;
+define exported symbol rtw_get_wps_attr_content = 0x146f1;
+define exported symbol rtw_ieee802_11_parse_elems = 0x14739;
+define exported symbol str_2char2num = 0x14909;
+define exported symbol key_2char2num = 0x14925;
+define exported symbol convert_ip_addr = 0x1493d;
+define exported symbol rom_psk_PasswordHash = 0x14a21;
+define exported symbol rom_psk_CalcGTK = 0x14a59;
+define exported symbol rom_psk_CalcPTK = 0x14ae9;
+define exported symbol _htons_rom = 0x14bdd;
+define exported symbol _ntohs_rom = 0x14be5;
+define exported symbol _htonl_rom = 0x14bed;
+define exported symbol _ntohl_rom = 0x14bf1;
+define exported symbol Message_ReplayCounter_OC2LI = 0x14bf5;
+define exported symbol Message_EqualReplayCounter = 0x14c35;
+define exported symbol Message_SmallerEqualReplayCounter = 0x14c6d;
+define exported symbol Message_LargerReplayCounter = 0x14cad;
+define exported symbol Message_setReplayCounter = 0x14ce5;
+define exported symbol INCLargeInteger = 0x14d15;
+define exported symbol INCOctet16_INTEGER = 0x14d25;
+define exported symbol INCOctet32_INTEGER = 0x14d8d;
+define exported symbol SetEAPOL_KEYIV = 0x14df5;
+define exported symbol CheckMIC = 0x14e89;
+define exported symbol CalcMIC = 0x14f29;
+define exported symbol DecWPA2KeyData_rom = 0x14f9d;
+define exported symbol DecGTK = 0x15055;
+define exported symbol GetRandomBuffer = 0x15119;
+define exported symbol GenNonce = 0x15181;
+define exported symbol ClientConstructEAPOL_2Of4Way = 0x151c5;
+define exported symbol ClientConstructEAPOL_4Of4Way = 0x152cd;
+define exported symbol ClientConstructEAPOL_2Of2Way = 0x1537d;
+define exported symbol ClientConstructEAPOL_MICOf2Way = 0x15459;
+define exported symbol psk_strip_rsn_pairwise = 0x1552d;
+define exported symbol psk_strip_wpa_pairwise = 0x155c1;
+define exported symbol wep_80211_encrypt = 0x1587d;
+define exported symbol wep_80211_decrypt = 0x158e1;
+define exported symbol tkip_micappendbyte = 0x15975;
+define exported symbol rtw_secmicsetkey = 0x159b9;
+define exported symbol rtw_secmicappend = 0x159f9;
+define exported symbol rtw_secgetmic = 0x15a15;
+define exported symbol rtw_seccalctkipmic = 0x15a89;
+define exported symbol tkip_phase1 = 0x15b7d;
+define exported symbol tkip_phase2 = 0x15ce5;
+define exported symbol tkip_80211_encrypt = 0x15f01;
+define exported symbol tkip_80211_decrypt = 0x15f91;
+define exported symbol aes1_encrypt = 0x16055;
+define exported symbol aesccmp_construct_mic_iv = 0x1625d;
+define exported symbol aesccmp_construct_mic_header1 = 0x162b1;
+define exported symbol aesccmp_construct_mic_header2 = 0x16321;
+define exported symbol aesccmp_construct_ctr_preload = 0x163a5;
+define exported symbol aes_80211_encrypt = 0x16429;
+define exported symbol aes_80211_decrypt = 0x167f9;
+define exported symbol cckrates_included = 0x16c39;
+define exported symbol cckratesonly_included = 0x16c7d;
+define exported symbol networktype_to_raid_ex_rom = 0x16ca9;
+define exported symbol judge_network_type_rom = 0x16cf5;
+define exported symbol ratetbl_val_2wifirate = 0x16d89;
+define exported symbol is_basicrate_rom = 0x16d9d;
+define exported symbol ratetbl2rateset_rom = 0x16dd5;
+define exported symbol get_rate_set_rom = 0x16e3d;
+define exported symbol UpdateBrateTbl_rom = 0x16e71;
+define exported symbol UpdateBrateTblForSoftAP = 0x16ec9;
+define exported symbol write_cam_rom = 0x16f0d;
+define exported symbol HT_caps_handler_rom = 0x16fc1;
+define exported symbol wifirate2_ratetbl_inx = 0x17015;
+define exported symbol update_basic_rate = 0x170bd;
+define exported symbol update_supported_rate = 0x170f5;
+define exported symbol update_MCS_rate = 0x17125;
+define exported symbol get_highest_rate_idx = 0x17131;
+define exported symbol _sha1_process_message_block = 0x1714d;
+define exported symbol _sha1_pad_message = 0x172d1;
+define exported symbol rt_sha1_init = 0x1736d;
+define exported symbol rt_sha1_update = 0x173b1;
+define exported symbol rt_sha1_finish = 0x17429;
+define exported symbol rt_hmac_sha1 = 0x17489;
+define exported symbol rom_aes_128_cbc_encrypt = 0x175e5;
+define exported symbol rom_aes_128_cbc_decrypt = 0x17669;
+define exported symbol rom_rijndaelKeySetupEnc = 0x176ed;
+define exported symbol rom_aes_decrypt_init = 0x177c1;
+define exported symbol rom_aes_internal_decrypt = 0x17899;
+define exported symbol rom_aes_decrypt_deinit = 0x17bdd;
+define exported symbol rom_aes_encrypt_init = 0x17be9;
+define exported symbol rom_aes_internal_encrypt = 0x17c01;
+define exported symbol rom_aes_encrypt_deinit = 0x17f81;
+define exported symbol bignum_init = 0x1963d;
+define exported symbol bignum_deinit = 0x19665;
+define exported symbol bignum_get_unsigned_bin_len = 0x19685;
+define exported symbol bignum_get_unsigned_bin = 0x19689;
+define exported symbol bignum_set_unsigned_bin = 0x19741;
+define exported symbol bignum_cmp = 0x197f9;
+define exported symbol bignum_cmp_d = 0x197fd;
+define exported symbol bignum_add = 0x19825;
+define exported symbol bignum_sub = 0x19835;
+define exported symbol bignum_mul = 0x19845;
+define exported symbol bignum_exptmod = 0x19855;
+define exported symbol WPS_realloc = 0x19879;
+define exported symbol os_zalloc = 0x198bd;
+define exported symbol rom_hmac_sha256_vector = 0x198e1;
+define exported symbol rom_hmac_sha256 = 0x199e1;
+define exported symbol rom_sha256_vector = 0x19b3d;
+define exported symbol CRYPTO_chacha_20 = 0x19d45;
+define exported symbol rom_ed25519_gen_keypair = 0x1a1bd;
+define exported symbol rom_ed25519_gen_signature = 0x1a1c1;
+define exported symbol rom_ed25519_verify_signature = 0x1a1d9;
+define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x1c4c9;
+define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x1c8c1;
+define exported symbol rom_ed25519_ge_p3_tobytes = 0x1d43d;
+define exported symbol rom_ed25519_ge_scalarmult_base = 0x1d489;
+define exported symbol rom_ed25519_ge_tobytes = 0x1d64d;
+define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x1d699;
+define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x1d6f1;
+define exported symbol rom_ed25519_sc_muladd = 0x1d9e5;
+define exported symbol rom_ed25519_sc_reduce = 0x24175;
+define exported symbol rom_ed25519_crypto_sign_detached = 0x26c25;
+define exported symbol CRYPTO_poly1305_init = 0x270dd;
+define exported symbol CRYPTO_poly1305_update = 0x271b5;
+define exported symbol CRYPTO_poly1305_finish = 0x27245;
+define exported symbol rom_sha512_starts = 0x28511;
+define exported symbol rom_sha512_update = 0x28659;
+define exported symbol rom_sha512_finish = 0x28661;
+define exported symbol rom_sha512 = 0x288a9;
+define exported symbol rom_sha512_hmac_starts = 0x288e1;
+define exported symbol rom_sha512_hmac_update = 0x289a5;
+define exported symbol rom_sha512_hmac_finish = 0x289ad;
+define exported symbol rom_sha512_hmac_reset = 0x289fd;
+define exported symbol rom_sha512_hmac = 0x28a19;
+define exported symbol rom_sha512_hkdf = 0x28a51;
+define exported symbol aes_test_alignment_detection = 0x28b59;
+define exported symbol aes_mode_reset = 0x28bbd;
+define exported symbol aes_ecb_encrypt = 0x28bc9;
+define exported symbol aes_ecb_decrypt = 0x28c05;
+define exported symbol aes_cbc_encrypt = 0x28c41;
+define exported symbol aes_cbc_decrypt = 0x28dad;
+define exported symbol aes_cfb_encrypt = 0x28f49;
+define exported symbol aes_cfb_decrypt = 0x2920d;
+define exported symbol aes_ofb_crypt = 0x294d5;
+define exported symbol aes_ctr_crypt = 0x29769;
+define exported symbol aes_encrypt_key128 = 0x29a79;
+define exported symbol aes_encrypt_key192 = 0x29a95;
+define exported symbol aes_encrypt_key256 = 0x29ab1;
+define exported symbol aes_encrypt_key = 0x29ad1;
+define exported symbol aes_decrypt_key128 = 0x29b41;
+define exported symbol aes_decrypt_key192 = 0x29b5d;
+define exported symbol aes_decrypt_key256 = 0x29b79;
+define exported symbol aes_decrypt_key = 0x29b99;
+define exported symbol aes_init = 0x29c09;
+define exported symbol curve25519_donna = 0x2a939;
+define exported symbol __rtl_dtoa_r_v1_00 = 0x2b7f1;
+define exported symbol __rtl_ltoa_v1_00 = 0x2c7f9;
+define exported symbol __rtl_ultoa_v1_00 = 0x2c885;
+define exported symbol __rtl_dtoi_v1_00 = 0x2c8ed;
+define exported symbol __rtl_dtoi64_v1_00 = 0x2c96d;
+define exported symbol __rtl_dtoui_v1_00 = 0x2ca09;
+define exported symbol __rtl_ftol_v1_00 = 0x2ca11;
+define exported symbol __rtl_itof_v1_00 = 0x2ca75;
+define exported symbol __rtl_itod_v1_00 = 0x2cb05;
+define exported symbol __rtl_i64tod_v1_00 = 0x2cb71;
+define exported symbol __rtl_uitod_v1_00 = 0x2cc4d;
+define exported symbol __rtl_ftod_v1_00 = 0x2cd29;
+define exported symbol __rtl_dtof_v1_00 = 0x2cde1;
+define exported symbol __rtl_uitof_v1_00 = 0x2ce75;
+define exported symbol __rtl_fadd_v1_00 = 0x2cf59;
+define exported symbol __rtl_fsub_v1_00 = 0x2d259;
+define exported symbol __rtl_fmul_v1_00 = 0x2d565;
+define exported symbol __rtl_fdiv_v1_00 = 0x2d695;
+define exported symbol __rtl_dadd_v1_00 = 0x2d809;
+define exported symbol __rtl_dsub_v1_00 = 0x2de49;
+define exported symbol __rtl_dmul_v1_00 = 0x2e4a1;
+define exported symbol __rtl_ddiv_v1_00 = 0x2e7dd;
+define exported symbol __rtl_dcmpeq_v1_00 = 0x2ed71;
+define exported symbol __rtl_dcmplt_v1_00 = 0x2eded;
+define exported symbol __rtl_dcmpgt_v1_00 = 0x2ee85;
+define exported symbol __rtl_dcmple_v1_00 = 0x2ef95;
+define exported symbol __rtl_fcmplt_v1_00 = 0x2f0a9;
+define exported symbol __rtl_fcmpgt_v1_00 = 0x2f105;
+define exported symbol __rtl_fpclassifyd = 0x2f1ad;
+define exported symbol __rtl_close_v1_00 = 0x2f205;
+define exported symbol __rtl_fstat_v1_00 = 0x2f219;
+define exported symbol __rtl_isatty_v1_00 = 0x2f22d;
+define exported symbol __rtl_lseek_v1_00 = 0x2f23d;
+define exported symbol __rtl_open_v1_00 = 0x2f251;
+define exported symbol __rtl_read_v1_00 = 0x2f265;
+define exported symbol __rtl_write_v1_00 = 0x2f279;
+define exported symbol __rtl_sbrk_v1_00 = 0x2f28d;
+define exported symbol __rom_mallocr_init_v1_00 = 0x2f29d;
+define exported symbol __rtl_free_r_v1_00 = 0x2f309;
+define exported symbol __rtl_malloc_r_v1_00 = 0x2f521;
+define exported symbol __rtl_realloc_r_v1_00 = 0x2f9f5;
+define exported symbol __rtl_memalign_r_v1_00 = 0x2fdb5;
+define exported symbol __rtl_valloc_r_v1_00 = 0x2fe81;
+define exported symbol __rtl_pvalloc_r_v1_00 = 0x2fe8d;
+define exported symbol __rtl_calloc_r_v1_00 = 0x2fea1;
+define exported symbol __rtl_cfree_r_v1_00 = 0x2ff05;
+define exported symbol __rtl_cos_f32_v1_00 = 0x2ff15;
+define exported symbol __rtl_sin_f32_v1_00 = 0x300e9;
+define exported symbol __rtl_fabs_v1_00 = 0x302ad;
+define exported symbol __rtl_fabsf_v1_00 = 0x302b5;
+define exported symbol __rtl_memchr_v1_00 = 0x302bd;
+define exported symbol __rtl_memcmp_v1_00 = 0x30351;
+define exported symbol __rtl_memcpy_v1_00 = 0x303b5;
+define exported symbol __rtl_memmove_v1_00 = 0x3045d;
+define exported symbol __rtl_memset_v1_00 = 0x30525;
+define exported symbol __rtl_Balloc_v1_00 = 0x3061d;
+define exported symbol __rtl_Bfree_v1_00 = 0x3066d;
+define exported symbol __rtl_i2b_v1_00 = 0x30681;
+define exported symbol __rtl_multadd_v1_00 = 0x30695;
+define exported symbol __rtl_mult_v1_00 = 0x30721;
+define exported symbol __rtl_pow5mult_v1_00 = 0x30855;
+define exported symbol __rtl_hi0bits_v1_00 = 0x308f5;
+define exported symbol __rtl_d2b_v1_00 = 0x30935;
+define exported symbol __rtl_lshift_v1_00 = 0x309ed;
+define exported symbol __rtl_cmp_v1_00 = 0x30a99;
+define exported symbol __rtl_diff_v1_00 = 0x30ae1;
+define exported symbol __rtl_sread_v1_00 = 0x30bb5;
+define exported symbol __rtl_seofread_v1_00 = 0x30c01;
+define exported symbol __rtl_swrite_v1_00 = 0x30c05;
+define exported symbol __rtl_sseek_v1_00 = 0x30c75;
+define exported symbol __rtl_sclose_v1_00 = 0x30cc1;
+define exported symbol __rtl_sbrk_r_v1_00 = 0x30ced;
+define exported symbol __rtl_strcat_v1_00 = 0x30d15;
+define exported symbol __rtl_strchr_v1_00 = 0x30d59;
+define exported symbol __rtl_strcmp_v1_00 = 0x30e25;
+define exported symbol __rtl_strcpy_v1_00 = 0x30e99;
+define exported symbol __rtl_strlen_v1_00 = 0x30ee5;
+define exported symbol __rtl_strncat_v1_00 = 0x30f39;
+define exported symbol __rtl_strncmp_v1_00 = 0x30f95;
+define exported symbol __rtl_strncpy_v1_00 = 0x3102d;
+define exported symbol __rtl_strsep_v1_00 = 0x31095;
+define exported symbol __rtl_strstr_v1_00 = 0x3136d;
+define exported symbol __rtl_strtok_v1_00 = 0x315a5;
+define exported symbol __rtl__strtok_r_v1_00 = 0x315b5;
+define exported symbol __rtl_strtok_r_v1_00 = 0x31619;
+define exported symbol __rtl_fflush_r_v1_00 = 0x31ae9;
+define exported symbol __rtl_vfprintf_r_v1_00 = 0x31f99;
+define exported symbol polarssl_aes_init = 0x335b9;
+define exported symbol aes_free = 0x335c9;
+define exported symbol aes_setkey_enc = 0x335dd;
+define exported symbol aes_setkey_dec = 0x33829;
+define exported symbol aes_crypt_ecb = 0x339a1;
+define exported symbol aes_crypt_cbc = 0x343d1;
+define exported symbol aes_crypt_cfb128 = 0x34649;
+define exported symbol aes_crypt_cfb8 = 0x346c9;
+define exported symbol aes_crypt_ctr = 0x3474d;
+define exported symbol arc4_init = 0x347b1;
+define exported symbol arc4_free = 0x347bd;
+define exported symbol arc4_setup = 0x347d1;
+define exported symbol arc4_crypt = 0x3481d;
+define exported symbol asn1_get_len = 0x34861;
+define exported symbol asn1_get_tag = 0x34901;
+define exported symbol asn1_get_bool = 0x34929;
+define exported symbol asn1_get_int = 0x3495d;
+define exported symbol asn1_get_mpi = 0x349a9;
+define exported symbol asn1_get_bitstring = 0x349d1;
+define exported symbol asn1_get_bitstring_null = 0x34a19;
+define exported symbol asn1_get_sequence_of = 0x34a4d;
+define exported symbol asn1_get_alg = 0x34ad1;
+define exported symbol asn1_get_alg_null = 0x34b65;
+define exported symbol asn1_free_named_data = 0x34ba5;
+define exported symbol asn1_free_named_data_list = 0x34bcd;
+define exported symbol asn1_find_named_data = 0x34bf5;
+define exported symbol asn1_write_len = 0x34c25;
+define exported symbol asn1_write_tag = 0x34c8d;
+define exported symbol asn1_write_raw_buffer = 0x34ca9;
+define exported symbol asn1_write_mpi = 0x34ccd;
+define exported symbol asn1_write_null = 0x34d41;
+define exported symbol asn1_write_oid = 0x34d6d;
+define exported symbol asn1_write_algorithm_identifier = 0x34dc5;
+define exported symbol asn1_write_bool = 0x34e21;
+define exported symbol asn1_write_int = 0x34e65;
+define exported symbol asn1_write_printable_string = 0x34ecd;
+define exported symbol asn1_write_ia5_string = 0x34f25;
+define exported symbol asn1_write_bitstring = 0x34f7d;
+define exported symbol asn1_write_octet_string = 0x34fe5;
+define exported symbol asn1_store_named_data = 0x3503d;
+define exported symbol base64_encode = 0x35111;
+define exported symbol base64_decode = 0x3523d;
+define exported symbol mpi_init = 0x35e09;
+define exported symbol mpi_free = 0x35e19;
+define exported symbol mpi_grow = 0x35e55;
+define exported symbol mpi_shrink = 0x35e79;
+define exported symbol mpi_copy = 0x35f21;
+define exported symbol mpi_swap = 0x35fa1;
+define exported symbol mpi_safe_cond_assign = 0x35fcd;
+define exported symbol mpi_safe_cond_swap = 0x36069;
+define exported symbol mpi_lset = 0x3610d;
+define exported symbol mpi_get_bit = 0x3614d;
+define exported symbol mpi_set_bit = 0x3616d;
+define exported symbol mpi_lsb = 0x361d5;
+define exported symbol mpi_msb = 0x36215;
+define exported symbol mpi_size = 0x36261;
+define exported symbol mpi_read_binary = 0x3626d;
+define exported symbol mpi_write_binary = 0x362f9;
+define exported symbol mpi_shift_l = 0x36341;
+define exported symbol mpi_shift_r = 0x363f1;
+define exported symbol mpi_cmp_abs = 0x36475;
+define exported symbol mpi_cmp_mpi = 0x36619;
+define exported symbol mpi_cmp_int = 0x366f1;
+define exported symbol mpi_add_abs = 0x3671d;
+define exported symbol mpi_sub_abs = 0x3680d;
+define exported symbol mpi_add_mpi = 0x3689d;
+define exported symbol mpi_sub_mpi = 0x368ed;
+define exported symbol mpi_add_int = 0x3693d;
+define exported symbol mpi_sub_int = 0x36969;
+define exported symbol mpi_mul_mpi = 0x36995;
+define exported symbol mpi_read_string = 0x36ac5;
+define exported symbol mpi_mul_int = 0x36c45;
+define exported symbol mpi_div_mpi = 0x36c61;
+define exported symbol mpi_div_int = 0x370ed;
+define exported symbol mpi_mod_mpi = 0x37119;
+define exported symbol mpi_mod_int = 0x3717d;
+define exported symbol mpi_write_string = 0x3722d;
+define exported symbol mpi_exp_mod = 0x37395;
+define exported symbol mpi_gcd = 0x37915;
+define exported symbol mpi_fill_random = 0x37a39;
+define exported symbol mpi_inv_mod = 0x37c4d;
+define exported symbol mpi_is_prime = 0x37f15;
+define exported symbol mpi_gen_prime = 0x37f71;
+define exported symbol ctr_drbg_free = 0x38285;
+define exported symbol ctr_drbg_set_prediction_resistance = 0x382a1;
+define exported symbol ctr_drbg_set_entropy_len = 0x382a5;
+define exported symbol ctr_drbg_set_reseed_interval = 0x382a9;
+define exported symbol ctr_drbg_update = 0x382ad;
+define exported symbol ctr_drbg_reseed = 0x382c9;
+define exported symbol ctr_drbg_init_entropy_len = 0x38341;
+define exported symbol ctr_drbg_init = 0x38399;
+define exported symbol ctr_drbg_random_with_add = 0x383ad;
+define exported symbol ctr_drbg_random = 0x38469;
+define exported symbol des_init = 0x388a5;
+define exported symbol des_free = 0x388b1;
+define exported symbol des3_init = 0x388c5;
+define exported symbol des3_free = 0x388d5;
+define exported symbol des_key_set_parity = 0x388e9;
+define exported symbol des_key_check_key_parity = 0x38909;
+define exported symbol des_key_check_weak = 0x38939;
+define exported symbol des_setkey_enc = 0x38965;
+define exported symbol des_setkey_dec = 0x3898d;
+define exported symbol des3_set2key_enc = 0x389d9;
+define exported symbol des3_set2key_dec = 0x38a25;
+define exported symbol des3_set3key_enc = 0x38a71;
+define exported symbol des3_set3key_dec = 0x38ab1;
+define exported symbol des_crypt_ecb = 0x38af1;
+define exported symbol des_crypt_cbc = 0x38d09;
+define exported symbol des3_crypt_ecb = 0x38f99;
+define exported symbol des3_crypt_cbc = 0x39401;
+define exported symbol dhm_init = 0x39729;
+define exported symbol dhm_read_params = 0x39731;
+define exported symbol dhm_make_params = 0x3978d;
+define exported symbol dhm_read_public = 0x398c1;
+define exported symbol dhm_make_public = 0x398e9;
+define exported symbol dhm_calc_secret = 0x399ad;
+define exported symbol dhm_free = 0x39ba1;
+define exported symbol dhm_parse_dhm = 0x39c01;
+define exported symbol ecdh_gen_public = 0x39cc5;
+define exported symbol ecdh_compute_shared = 0x39cc9;
+define exported symbol ecdh_init = 0x39d2d;
+define exported symbol ecdh_free = 0x39d39;
+define exported symbol ecdh_make_params = 0x39d81;
+define exported symbol ecdh_read_params = 0x39e05;
+define exported symbol ecdh_get_params = 0x39e2d;
+define exported symbol ecdh_make_public = 0x39e79;
+define exported symbol ecdh_read_public = 0x39ed1;
+define exported symbol ecdh_calc_secret = 0x39f01;
+define exported symbol ecdsa_sign = 0x3a041;
+define exported symbol ecdsa_sign_det = 0x3a1c5;
+define exported symbol ecdsa_verify = 0x3a2a9;
+define exported symbol ecdsa_write_signature = 0x3a431;
+define exported symbol ecdsa_write_signature_det = 0x3a46d;
+define exported symbol ecdsa_read_signature = 0x3a4a5;
+define exported symbol ecdsa_genkey = 0x3a531;
+define exported symbol ecdsa_init = 0x3a565;
+define exported symbol ecdsa_free = 0x3a591;
+define exported symbol ecdsa_from_keypair = 0x3a5bd;
+define exported symbol ecp_curve_list = 0x3aee5;
+define exported symbol ecp_curve_info_from_grp_id = 0x3aeed;
+define exported symbol ecp_curve_info_from_tls_id = 0x3af0d;
+define exported symbol ecp_curve_info_from_name = 0x3af31;
+define exported symbol ecp_point_init = 0x3af61;
+define exported symbol ecp_group_init = 0x3af81;
+define exported symbol ecp_keypair_init = 0x3af8d;
+define exported symbol ecp_point_free = 0x3afb1;
+define exported symbol ecp_group_free = 0x3afd1;
+define exported symbol ecp_keypair_free = 0x3b03d;
+define exported symbol ecp_copy = 0x3b05d;
+define exported symbol ecp_group_copy = 0x3b08d;
+define exported symbol ecp_set_zero = 0x3b095;
+define exported symbol ecp_is_zero = 0x3ba61;
+define exported symbol ecp_point_read_string = 0x3ba75;
+define exported symbol ecp_point_write_binary = 0x3baa5;
+define exported symbol ecp_point_read_binary = 0x3bb4d;
+define exported symbol ecp_tls_read_point = 0x3bbc1;
+define exported symbol ecp_tls_write_point = 0x3bbf5;
+define exported symbol ecp_group_read_string = 0x3bc25;
+define exported symbol ecp_tls_read_group = 0x3bc95;
+define exported symbol ecp_tls_write_group = 0x3bcf1;
+define exported symbol ecp_add = 0x3bd39;
+define exported symbol ecp_sub = 0x3bd65;
+define exported symbol ecp_check_pubkey = 0x3bddd;
+define exported symbol ecp_check_privkey = 0x3bf8d;
+define exported symbol ecp_mul = 0x3bff5;
+define exported symbol ecp_gen_keypair = 0x3c565;
+define exported symbol ecp_gen_key = 0x3c669;
+define exported symbol ecp_use_known_dp = 0x3d741;
+define exported symbol hmac_drbg_update = 0x3daa9;
+define exported symbol hmac_drbg_init_buf = 0x3db41;
+define exported symbol hmac_drbg_reseed = 0x3db91;
+define exported symbol hmac_drbg_init = 0x3dc09;
+define exported symbol hmac_drbg_set_prediction_resistance = 0x3dc81;
+define exported symbol hmac_drbg_set_entropy_len = 0x3dc85;
+define exported symbol hmac_drbg_set_reseed_interval = 0x3dc89;
+define exported symbol hmac_drbg_random_with_add = 0x3dc8d;
+define exported symbol hmac_drbg_random = 0x3dd4d;
+define exported symbol hmac_drbg_free = 0x3dd61;
+define exported symbol md_list = 0x3dd7d;
+define exported symbol md_info_from_string = 0x3dd85;
+define exported symbol md_info_from_type = 0x3de59;
+define exported symbol md_init = 0x3de9d;
+define exported symbol md_free = 0x3dea5;
+define exported symbol md_init_ctx = 0x3dec5;
+define exported symbol md_free_ctx = 0x3defd;
+define exported symbol md_starts = 0x3df09;
+define exported symbol md_update = 0x3df29;
+define exported symbol md_finish = 0x3df49;
+define exported symbol md = 0x3df69;
+define exported symbol md_file = 0x3df89;
+define exported symbol md_hmac_starts = 0x3dfa1;
+define exported symbol md_hmac_update = 0x3dfc1;
+define exported symbol md_hmac_finish = 0x3dfe1;
+define exported symbol md_hmac_reset = 0x3e001;
+define exported symbol md_hmac = 0x3e021;
+define exported symbol md_process = 0x3e049;
+define exported symbol md5_init = 0x3e301;
+define exported symbol md5_free = 0x3e309;
+define exported symbol md5_starts = 0x3e31d;
+define exported symbol md5_process = 0x3e34d;
+define exported symbol md5_update = 0x3ed51;
+define exported symbol md5_finish = 0x3ed59;
+define exported symbol md5 = 0x3ee11;
+define exported symbol md5_hmac_starts = 0x3ee75;
+define exported symbol md5_hmac_update = 0x3ef51;
+define exported symbol md5_hmac_finish = 0x3ef59;
+define exported symbol md5_hmac_reset = 0x3efbd;
+define exported symbol md5_hmac = 0x3eff1;
+define exported symbol oid_get_attr_short_name = 0x3f071;
+define exported symbol oid_get_x509_ext_type = 0x3f0b1;
+define exported symbol oid_get_extended_key_usage = 0x3f0f1;
+define exported symbol oid_get_sig_alg_desc = 0x3f131;
+define exported symbol oid_get_sig_alg = 0x3f149;
+define exported symbol oid_get_oid_by_sig_alg = 0x3f169;
+define exported symbol oid_get_pk_alg = 0x3f1a1;
+define exported symbol oid_get_oid_by_pk_alg = 0x3f1e1;
+define exported symbol oid_get_ec_grp = 0x3f219;
+define exported symbol oid_get_oid_by_ec_grp = 0x3f259;
+define exported symbol oid_get_cipher_alg = 0x3f291;
+define exported symbol oid_get_md_alg = 0x3f2d1;
+define exported symbol oid_get_oid_by_md = 0x3f311;
+define exported symbol oid_get_pkcs12_pbe_alg = 0x3f349;
+define exported symbol oid_get_numeric_string = 0x3f391;
+define exported symbol pem_init = 0x3f649;
+define exported symbol pem_read_buffer = 0x3f651;
+define exported symbol pem_free = 0x3f955;
+define exported symbol pem_write_buffer = 0x3f97d;
+define exported symbol pk_init = 0x3fa81;
+define exported symbol pk_free = 0x3fa8d;
+define exported symbol pk_info_from_type = 0x3faad;
+define exported symbol pk_init_ctx = 0x3fae1;
+define exported symbol pk_init_ctx_rsa_alt = 0x3fb11;
+define exported symbol pk_can_do = 0x3fb69;
+define exported symbol pk_verify = 0x3fb79;
+define exported symbol pk_verify_ext = 0x3fbc9;
+define exported symbol pk_sign = 0x3fc8d;
+define exported symbol pk_decrypt = 0x3fce9;
+define exported symbol pk_encrypt = 0x3fd15;
+define exported symbol pk_get_size = 0x3fd41;
+define exported symbol pk_debug = 0x3fd51;
+define exported symbol pk_get_name = 0x3fd79;
+define exported symbol pk_get_type = 0x3fd8d;
+define exported symbol pk_write_pubkey = 0x40181;
+define exported symbol pk_write_pubkey_der = 0x40201;
+define exported symbol pk_write_key_der = 0x402dd;
+define exported symbol pk_write_pubkey_pem = 0x404f5;
+define exported symbol pk_write_key_pem = 0x40545;
+define exported symbol rsa_init = 0x4065d;
+define exported symbol rsa_set_padding = 0x40679;
+define exported symbol rsa_check_pubkey = 0x40685;
+define exported symbol rsa_check_privkey = 0x406e1;
+define exported symbol rsa_public = 0x409a5;
+define exported symbol rsa_private = 0x40a25;
+define exported symbol rsa_rsaes_oaep_encrypt = 0x40c29;
+define exported symbol rsa_rsaes_pkcs1_v15_encrypt = 0x40d31;
+define exported symbol rsa_pkcs1_encrypt = 0x40e19;
+define exported symbol rsa_rsaes_oaep_decrypt = 0x40e59;
+define exported symbol rsa_rsaes_pkcs1_v15_decrypt = 0x40fbd;
+define exported symbol rsa_pkcs1_decrypt = 0x410c1;
+define exported symbol rsa_rsassa_pss_sign = 0x4110d;
+define exported symbol rsa_rsassa_pkcs1_v15_sign = 0x41271;
+define exported symbol rsa_pkcs1_sign = 0x41389;
+define exported symbol rsa_rsassa_pss_verify_ext = 0x413c9;
+define exported symbol rsa_rsassa_pss_verify = 0x41575;
+define exported symbol rsa_rsassa_pkcs1_v15_verify = 0x415a5;
+define exported symbol rsa_pkcs1_verify = 0x41709;
+define exported symbol rsa_free = 0x41765;
+define exported symbol rsa_gen_key = 0x417d5;
+define exported symbol rsa_copy = 0x4198d;
+define exported symbol sha1_init = 0x41a9d;
+define exported symbol sha1_free = 0x41aa5;
+define exported symbol sha1_starts = 0x41ab9;
+define exported symbol sha1_process = 0x41aed;
+define exported symbol sha1_update = 0x42e15;
+define exported symbol sha1_finish = 0x42e1d;
+define exported symbol sha1 = 0x42ee5;
+define exported symbol sha1_hmac_starts = 0x42f51;
+define exported symbol sha1_hmac_update = 0x43039;
+define exported symbol sha1_hmac_finish = 0x43041;
+define exported symbol sha1_hmac_reset = 0x430b5;
+define exported symbol sha1_hmac = 0x430f1;
+define exported symbol sha256_init = 0x43139;
+define exported symbol sha256_free = 0x43141;
+define exported symbol sha256_starts = 0x43155;
+define exported symbol sha256_process = 0x431e5;
+define exported symbol sha256_update = 0x4513d;
+define exported symbol sha256_finish = 0x45145;
+define exported symbol sha256 = 0x4524d;
+define exported symbol sha256_hmac_starts = 0x45325;
+define exported symbol sha256_hmac_update = 0x45475;
+define exported symbol sha256_hmac_finish = 0x4547d;
+define exported symbol sha256_hmac_reset = 0x45569;
+define exported symbol sha256_hmac = 0x45601;
+define exported symbol sha512_init = 0x45651;
+define exported symbol sha512_free = 0x4565d;
+define exported symbol sha512_starts = 0x45671;
+define exported symbol sha512_process = 0x457b9;
+define exported symbol sha512_update = 0x46879;
+define exported symbol sha512_finish = 0x46881;
+define exported symbol sha512 = 0x46ac9;
+define exported symbol sha512_hmac_starts = 0x46b11;
+define exported symbol sha512_hmac_update = 0x46bd9;
+define exported symbol sha512_hmac_finish = 0x46be1;
+define exported symbol sha512_hmac_reset = 0x46c35;
+define exported symbol sha512_hmac = 0x46c51;
+define exported symbol UartLogRomCmdTable = 0x46ca0;
+define exported symbol XTAL_CLK = 0x46e10;
+define exported symbol CpkClkTbl_FPAG = 0x46e50;
+define exported symbol CpkClkTbl_ASIC = 0x46e68;
+define exported symbol ROM_IMG1_VALID_PATTEN = 0x46e90;
+define exported symbol __AES_rcon = 0x46e98;
+define exported symbol __AES_Te4 = 0x46ec0;
+define exported symbol SpicCalibrationPattern = 0x472c0;
+define exported symbol NEW_CALIBREATION_DIV = 0x472c8;
+define exported symbol NEW_CALIBREATION_DATA = 0x472e4;
+define exported symbol GDMA_IrqNum = 0x47344;
+define exported symbol I2C_DEV_TABLE = 0x47350;
+define exported symbol spi_clk_pin = 0x47370;
+define exported symbol SPI_DEV_TABLE = 0x47374;
+define exported symbol PWM_GDMA_HSx = 0x47394;
+define exported symbol TIM_DMA_CCx = 0x473ac;
+define exported symbol TIM_IT_CCx = 0x473c4;
+define exported symbol TIMx = 0x473dc;
+define exported symbol TIMx_irq = 0x473f4;
+define exported symbol BAUDRATE_TABLE_40M = 0x4740c;
+define exported symbol UART_DEV_TABLE = 0x475bc;
+define exported symbol RTW_WPA_OUI_TYPE = 0x4b270;
+define exported symbol WPA_CIPHER_SUITE_NONE = 0x4b274;
+define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x4b278;
+define exported symbol WPA_CIPHER_SUITE_TKIP = 0x4b27c;
+define exported symbol WPA_CIPHER_SUITE_CCMP = 0x4b280;
+define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x4b284;
+define exported symbol RSN_CIPHER_SUITE_NONE = 0x4b288;
+define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x4b28c;
+define exported symbol RSN_CIPHER_SUITE_TKIP = 0x4b290;
+define exported symbol RSN_CIPHER_SUITE_CCMP = 0x4b294;
+define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x4b298;
+define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x4b2a8;
+define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x4b2ac;
+define exported symbol RSN_VERSION_BSD = 0x4b2b0;
+define exported symbol rom_e_rtw_msgp_str_ = 0x4b2b4;
+define exported symbol rtw_basic_rate_mix = 0x4b9a8;
+define exported symbol rtw_basic_rate_ofdm = 0x4b9b0;
+define exported symbol rtw_basic_rate_cck = 0x4b9b4;
+define exported symbol REALTEK_96B_IE = 0x4b9b8;
+define exported symbol AIRGOCAP_OUI = 0x4b9c0;
+define exported symbol REALTEK_OUI = 0x4b9c4;
+define exported symbol RALINK_OUI = 0x4b9c8;
+define exported symbol MARVELL_OUI = 0x4b9cc;
+define exported symbol CISCO_OUI = 0x4b9d0;
+define exported symbol BROADCOM_OUI3 = 0x4b9d4;
+define exported symbol BROADCOM_OUI2 = 0x4b9d8;
+define exported symbol BROADCOM_OUI1 = 0x4b9dc;
+define exported symbol ARTHEROS_OUI2 = 0x4b9e0;
+define exported symbol ARTHEROS_OUI1 = 0x4b9e4;
+define exported symbol rom_wps_rcons = 0x4b9e8;
+define exported symbol rom_wps_Te0 = 0x4b9f4;
+define exported symbol rom_wps_Td4s = 0x4bdf4;
+define exported symbol rom_wps_Td0 = 0x4bef4;
+define exported symbol sha512_info = 0x5850c;
+define exported symbol sha384_info = 0x5854c;
+define exported symbol sha256_info = 0x5858c;
+define exported symbol sha224_info = 0x585cc;
+define exported symbol sha1_info = 0x5860c;
+define exported symbol md5_info = 0x5864c;
+define exported symbol rsa_alt_info = 0x58d28;
+define exported symbol ecdsa_info = 0x58d54;
+define exported symbol eckeydh_info = 0x58d80;
+define exported symbol eckey_info = 0x58dac;
+define exported symbol rsa_info = 0x58dd8;
+define exported symbol __rom_bss_start__ = 0x10000000;
+define exported symbol NewVectorTable = 0x10000000;
+define exported symbol UserIrqFunTable = 0x10000100;
+define exported symbol UserIrqDataTable = 0x10000200;
+define exported symbol ConfigDebugClose = 0x10000300;
+define exported symbol CfgSysDebugWarn = 0x10000304;
+define exported symbol CfgSysDebugInfo = 0x10000308;
+define exported symbol CfgSysDebugErr = 0x1000030c;
+define exported symbol ConfigDebugWarn = 0x10000310;
+define exported symbol ConfigDebugInfo = 0x10000314;
+define exported symbol ConfigDebugErr = 0x10000318;
+define exported symbol sector_addr = 0x1000031c;
+define exported symbol _rtl_impure_ptr = 0x10000338;
+define exported symbol ArgvArray = 0x1000033c;
+define exported symbol pUartLogCtl = 0x10000364;
+define exported symbol UartLogBuf = 0x10000368;
+define exported symbol UartLogCtl = 0x100003e8;
+define exported symbol UartLogHistoryBuf = 0x10000408;
+define exported symbol NCO32K_Enable = 0x10000684;
+define exported symbol g_rtl_cipherEngine = 0x100006a0;
+define exported symbol DONGLE_InitStruct = 0x10000ba0;
+define exported symbol EFUSE_MAP = 0x10000ba4;
+define exported symbol USOC_BOOT_TXBD = 0x10000da4;
+define exported symbol USOC_BOOT_RXBD = 0x10000db4;
+define exported symbol USB_RXBuff = 0x10000dc4;
+define exported symbol USB_TXBuff = 0x10000dcc;
+define exported symbol ADC_AnaparAd = 0x10000dd4;
+define exported symbol flash_init_para = 0x10000dec;
+define exported symbol NEW_CALIBREATION_END = 0x10000e44;
+define exported symbol GDMA_Reg = 0x10000e4c;
+define exported symbol PortA_IrqHandler = 0x10000e50;
+define exported symbol PortA_IrqData = 0x10000ed0;
+define exported symbol IC_FS_SCL_HCNT_TRIM = 0x10000f50;
+define exported symbol IC_FS_SCL_LCNT_TRIM = 0x10000f54;
+define exported symbol I2C_SLAVEWRITE_PATCH = 0x10000f58;
+define exported symbol i2s_cur_tx_page = 0x10000f5c;
+define exported symbol i2s_cur_rx_page = 0x10000f60;
+define exported symbol i2s_page_num = 0x10000f64;
+define exported symbol i2s_txpage_entry = 0x10000f68;
+define exported symbol i2s_rxpage_entry = 0x10000f78;
+define exported symbol TXBDAddrAligned = 0x10000f88;
+define exported symbol H2C_Buff = 0x10000f90;
+define exported symbol SPI_RECV_Buff = 0x10000f94;
+define exported symbol spi_boot_recv_done = 0x10000f98;
+define exported symbol UART_StateRx = 0x10000f9c;
+define exported symbol UART_StateTx = 0x10000fa8;
+define exported symbol xMCtrl = 0x10000fb8;
+define exported symbol XComUARTx = 0x10000fc4;
+define exported symbol FalseAlmCnt = 0x10000fc8;
+define exported symbol ROMInfo = 0x10001008;
+define exported symbol DM_CfoTrack = 0x10001020;
+define exported symbol rom_wlan_ram_map = 0x10001048;
+define exported symbol rom_libgloss_ram_map = 0x10001050;
+define exported symbol __rtl_errno = 0x100014b4;
+define exported symbol rom_ssl_ram_map = 0x100014b8;
+define exported symbol __rom_bss_end__ = 0x100014f8;

bsp/apm32/apm32f072vb-miniboard/board/linker_scripts/link.lds

@@ -65,7 +65,7 @@ SECTIONS
 
         /* This is used by the startup in order to initialize the .data secion */
         _sidata = .;
-		_start_address_init_data = .;
+        _start_address_init_data = .;
     } > ROM
     __exidx_end = .;
 
@@ -76,7 +76,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _sdata = . ;
-		_start_address_data = .;
+        _start_address_data = .;
 
         *(.data)
         *(.data.*)
@@ -91,21 +91,21 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
-		_end_address_data = .;
+        _end_address_data = .;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
         . = . + _system_stack_size;
         . = ALIGN(4);
         _estack = .;
-		_end_stack = .;
+        _end_stack = .;
     } >RAM
 
     __bss_start = .;
-	_start_address_bss = .;
+    _start_address_bss = .;
     .bss :
     {
         . = ALIGN(4);
@@ -119,11 +119,11 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;
-	_end_address_bss = .;
+    _end_address_bss = .;
 
     _end = .;
 

bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.lds

@@ -80,7 +80,7 @@ SECTIONS
         _end_address_data = .;
     } >DATA
 
-    .stack : 
+    .stack :
     {
         . = . + _system_stack_size;
         . = ALIGN(4);
@@ -102,7 +102,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > DATA
     __bss_end = .;

bsp/apm32/apm32f407ig-minibroard/board/linker_scripts/link.lds

@@ -77,7 +77,7 @@ SECTIONS
         _edata = . ;
     } >DATA
 
-    .stack : 
+    .stack :
     {
         . = . + _system_stack_size;
         . = ALIGN(4);
@@ -98,7 +98,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > DATA
     __bss_end = .;

bsp/at32/at32f403a-start/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/at32/at32f403a-start/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/at32/at32f407-start/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/at32/at32f407-start/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/at32/at32f413-start/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/at32/at32f413-start/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/at32/at32f415-start/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/at32/at32f415-start/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/at32/at32f435-start/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/at32/at32f435-start/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/at32/at32f437-start/board/linker_scripts/link.icf

@@ -25,4 +25,4 @@ do not initialize  { section .noinit };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, last block CSTACK};
+place in RAM_region   { readwrite, last block CSTACK};

bsp/at32/at32f437-start/board/linker_scripts/link.lds

@@ -52,7 +52,7 @@ SECTIONS
         KEEP (*(.init_array))
         PROVIDE(__ctors_end__ = .);
 
-        . = ALIGN(4); 
+        . = ALIGN(4);
 
         _etext = .;
     } > ROM = 0
@@ -84,13 +84,13 @@ SECTIONS
         KEEP(*(SORT(.dtors.*)))
         KEEP(*(.dtors))
         PROVIDE(__dtors_end__ = .);
-        
+
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .data secion */
         _edata = . ;
     } >RAM
 
-    .stack : 
+    .stack :
     {
         . = ALIGN(4);
         _sstack = .;
@@ -113,7 +113,7 @@ SECTIONS
         . = ALIGN(4);
         /* This is used by the startup in order to initialize the .bss secion */
         _ebss = . ;
-        
+
         *(.bss.init)
     } > RAM
     __bss_end = .;

bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxC.icf

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
+                        block CSTACK, block HEAP };

bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxE.icf

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
+                        block CSTACK, block HEAP };

bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
+                        block CSTACK, block HEAP };

bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xC.icf

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
+                        block CSTACK, block HEAP };

bsp/at32/libraries/AT32F403A_407_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F407xE.icf

@@ -27,4 +27,4 @@ place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
+                        block CSTACK, block HEAP };