设置tlb表项nG位并在mmu_switch时区分内核和用户进程的tlb表项。

bsp/imx6ull-artpi-smart/rtconfig.h

@@ -395,4 +395,8 @@
 
 #define BSP_USING_USB_DEVICE
 
+/* enable ASID */
+// #define RT_LWP_ENABLE_ASID
+// #define MAX_ASID_BITS 8
+
 #endif

components/lwp/lwp_user_mm.c

@@ -35,12 +35,6 @@ static uint64_t global_generation = 1;
 static char asid_valid_bitmap[MAX_ASID];
 static unsigned get_update_asid(struct rt_lwp *l)
 {
-    if (l == RT_NULL)
-    {
-        // kernel thread
-        return 0;
-    }
-
     if (l->generation == global_generation)
     {
         return l->asid;
@@ -65,7 +59,7 @@ static unsigned get_update_asid(struct rt_lwp *l)
     l->asid = 1;
 
     // invalidate all TLB entries
-    asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(0)); 
+    asm volatile ("mcr p15, 0, r0, c8, c7, 0\ndsb\nisb" ::: "memory");
 
     return 1;
 }
@@ -78,7 +72,8 @@ void remove_asid(uint64_t generation, unsigned asid)
     }
 }
 
-void rt_hw_mmu_switch(void *mtable, unsigned char asid);
+void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned char asid);
+void rt_hw_mmu_switch_kernel(void *mtable);
 #else
 void rt_hw_mmu_switch(void *mtable);
 #endif
@@ -102,8 +97,15 @@ void lwp_mmu_switch(struct rt_thread *thread)
     if (pre_mmu_table != new_mmu_table)
     {
         #ifdef RT_LWP_ENABLE_ASID
-        unsigned asid = get_update_asid(l);
-        rt_hw_mmu_switch(new_mmu_table, asid);
+        if (l)
+        {
+            unsigned asid = get_update_asid(l);
+            rt_hw_mmu_switch(new_mmu_table, l->pid, asid);
+        }
+        else 
+        {
+            rt_hw_mmu_switch_kernel(new_mmu_table);
+        }
         #else
         rt_hw_mmu_switch(new_mmu_table);
         #endif

libcpu/arm/cortex-a/mmu.h

@@ -61,15 +61,16 @@ struct mem_desc
 #define MMU_MAP_MTBL_TEX(x)   (x<<6)
 #define MMU_MAP_MTBL_AP2(x)   (x<<9)
 #define MMU_MAP_MTBL_SHARE    (1<<10)
-
-#define MMU_MAP_K_RO          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_K_RWCB        (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_K_RW          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_K_DEVICE      (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_RO          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_RWCB        (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_RW          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_DEVICE      (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_MTBL_NG(x)    (x<<11)
+
+#define MMU_MAP_K_RO          (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_RWCB        (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_RW          (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_DEVICE      (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RO          (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RWCB        (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RW          (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_DEVICE      (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
 
 #define ARCH_SECTION_SHIFT  20
 #define ARCH_SECTION_SIZE   (1 << ARCH_SECTION_SHIFT)