|
@@ -71,4 +71,22 @@
|
|
|
|
|
|
#endif /* PHY_USING_DM9161CEP */
|
|
|
|
|
|
+#ifdef PHY_USING_DP83848C
|
|
|
+#define PHY_Status_REG 0x10U
|
|
|
+#define PHY_10M_MASK (1<<1)
|
|
|
+#define PHY_FULL_DUPLEX_MASK (1<<2)
|
|
|
+#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
|
|
+#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
|
|
|
+#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
|
|
+/* The PHY interrupt source flag register. */
|
|
|
+#define PHY_INTERRUPT_FLAG_REG 0x12U
|
|
|
+#define PHY_LINK_CHANGE_FLAG (1<<13)
|
|
|
+/* The PHY interrupt control register. */
|
|
|
+#define PHY_INTERRUPT_CTRL_REG 0x11U
|
|
|
+#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
|
|
|
+/* The PHY interrupt mask register. */
|
|
|
+#define PHY_INTERRUPT_MASK_REG 0x12U
|
|
|
+#define PHY_INT_MASK (1<<5)
|
|
|
+#endif /* PHY_USING_DP83848C */
|
|
|
+
|
|
|
#endif /* __DRV_ETH_H__ */
|