[bsp][x86] clean code

.gitignore

@@ -34,3 +34,4 @@ ncscope.*
 #ctag files
 tags
 
+.vscode/

.vscode/settings.json

@@ -1,8 +0,0 @@
-{
-    "files.associations": {
-        "lwp_arch.h": "c",
-        "cpuport.h": "c",
-        "rtdevice.h": "c",
-        "rtthread.h": "c"
-    }
-}

bsp/x86/applications/romfs.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-05     JasonHu      first version
+ */
+
 #include <dfs_romfs.h>
 
 static const struct romfs_dirent _romfs_root[] = {

components/lwp/arch/x86/i386/reloc.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-07-28     JasonHu      first version
+ */
+
 #include <rtthread.h>
 #include <stdint.h>
 #include <string.h>

libcpu/x86/i386/backtrace.c

@@ -1,3 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-07-28     JasonHu      first version
+ */
+
 #include <rtthread.h>
 #include <backtrace.h>
 

libcpu/x86/i386/context_gcc.S

@@ -23,10 +23,10 @@ rt_hw_context_switch_to_real:
     movl (%eax), %esp       // restore sp
     
     popl %ebp
-	popl %ebx
-	popl %edi
-	popl %esi
-	ret
+    popl %ebx
+    popl %edi
+    popl %esi
+    ret
 
 /*
  * void rt_hw_context_switch_real(rt_ubase_t from, rt_ubase_t to);
@@ -45,7 +45,7 @@ rt_hw_context_switch_real:
     movl (%eax), %esp       // restore sp
 
     popl %ebp
-	popl %ebx
-	popl %edi
-	popl %esi
-	ret
+    popl %ebx
+    popl %edi
+    popl %esi
+    ret

libcpu/x86/i386/interrupt.h

@@ -20,7 +20,24 @@
 
 #define EXCEPTION_PAGE_FAULT 14
 
-#include "irq.h"
+#define IRQ0_CLOCK          0
+#define IRQ1_KEYBOARD       1
+#define IRQ2_CONNECT        2   /* connect to slave */
+#define IRQ3_SERIAL2        3
+#define IRQ4_SERIAL1        4
+#define IRQ5_PARALLEL2      5
+#define IRQ6_FLOPPY         6
+#define IRQ7_PARALLEL1      7
+
+#define IRQ8_RTCLOCK        8   /* real-time clock */
+#define IRQ9_REDIRECT       9   /* redirect to IRQ2 */
+#define IRQ10_RESERVED      10
+#define IRQ11_RESERVED      11
+#define IRQ12_MOUSE         12
+#define IRQ13_FPU           13
+#define IRQ14_HARDDISK      14
+#define IRQ15_RESERVE       15
+
 #include "i386.h"
 
 #endif  /* __INTERRUPT_H__ */

libcpu/x86/i386/interrupt_gcc.S

@@ -35,8 +35,8 @@ rt_hw_intr_entry\p1:
     pushal
 
     movl %ss, %edx
-	movl %edx, %ds
-	movl %edx, %es
+    movl %edx, %ds
+    movl %edx, %es
 
     pushl $\p1
 
@@ -58,10 +58,10 @@ rt_hw_intr_entry\p1:
      *     jmp rt_hw_intr_thread_switch
      * end
      */
-	movl $rt_thread_switch_interrupt_flag, %eax
-	movl (%eax), %ebx
-	cmp $0x1, %ebx
-	jz rt_hw_intr_thread_switch
+    movl $rt_thread_switch_interrupt_flag, %eax
+    movl (%eax), %ebx
+    cmp $0x1, %ebx
+    jz rt_hw_intr_thread_switch
 
     // jmp to exit
     movl $rt_hw_intr_exit, %eax
@@ -81,8 +81,8 @@ rt_hw_intr_entry\p1:
     pushal
 
     movl %ss, %edx
-	movl %edx, %ds
-	movl %edx, %es
+    movl %edx, %ds
+    movl %edx, %es
 
     pushl $\p1
 
@@ -104,10 +104,10 @@ rt_hw_intr_entry\p1:
      *     jmp rt_hw_intr_thread_switch
      * end
      */
-	movl $rt_thread_switch_interrupt_flag, %eax
-	movl (%eax), %ebx
-	cmp $0x1, %ebx
-	jz rt_hw_intr_thread_switch
+    movl $rt_thread_switch_interrupt_flag, %eax
+    movl (%eax), %ebx
+    cmp $0x1, %ebx
+    jz rt_hw_intr_thread_switch
 
     // jmp to exit
     movl $rt_hw_intr_exit, %eax
@@ -162,17 +162,17 @@ rt_hw_intr_entry_push_errcode 0x2c
 rt_hw_intr_entry_push_errcode 0x2d
 rt_hw_intr_entry_push_errcode 0x2e
 rt_hw_intr_entry_push_errcode 0x2f
-rt_hw_intr_entry_push_errcode 0x80	// syscall
+rt_hw_intr_entry_push_errcode 0x80    // syscall
 
 rt_hw_intr_thread_switch:
     // set rt_thread_switch_interrupt_flag as 0
-	movl $0x0, %ebx
-	movl %ebx, (%eax)
+    movl $0x0, %ebx
+    movl %ebx, (%eax)
 
     // push to into stack
     movl $rt_interrupt_to_thread, %eax   // get "to"
     movl (%eax), %ebx
-	
+    
     // push from into stack
     movl $rt_interrupt_from_thread, %ecx   // get "from"
     movl (%ecx), %edx
@@ -182,7 +182,7 @@ rt_hw_intr_thread_switch:
     call rt_hw_context_switch
     addl $8, %esp   // restore stack
 
-	// jmp to exit
+    // jmp to exit
     movl $rt_hw_intr_exit, %eax
     jmp *%eax
 
@@ -206,8 +206,8 @@ hw_syscall_entry:
     pushal
 
     movl %ss, %edx
-	movl %edx, %ds
-	movl %edx, %es
+    movl %edx, %ds
+    movl %edx, %es
 
     pushl $0x80
 
@@ -235,7 +235,7 @@ syscall_exit:
 #endif /* RT_USING_USERSPACE */
 .global rt_hw_intr_exit
 rt_hw_intr_exit:
-    addl $4, %esp			   // skip intr no
+    addl $4, %esp               // skip intr no
 
     popal
     
@@ -244,6 +244,6 @@ rt_hw_intr_exit:
     popl %es
     popl %ds
 
-    addl $4, %esp			   // skip error_code
+    addl $4, %esp               // skip error_code
 
     iret

libcpu/x86/i386/irq.h

@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-07-16     JasonHu      first version
- */
-
-#ifndef __IRQ_H__
-#define __IRQ_H__
-
-#define IRQ0_CLOCK          0
-#define IRQ1_KEYBOARD       1
-#define IRQ2_CONNECT        2   /* connect to slave */
-#define IRQ3_SERIAL2        3
-#define IRQ4_SERIAL1        4
-#define IRQ5_PARALLEL2      5
-#define IRQ6_FLOPPY         6
-#define IRQ7_PARALLEL1      7
-
-#define IRQ8_RTCLOCK        8   /* real-time clock */
-#define IRQ9_REDIRECT       9   /* redirect to IRQ2 */
-#define IRQ10_RESERVED      10
-#define IRQ11_RESERVED      11
-#define IRQ12_MOUSE         12
-#define IRQ13_FPU           13
-#define IRQ14_HARDDISK      14
-#define IRQ15_RESERVE       15
-
-#endif /* __IRQ_H__ */

libcpu/x86/i386/mmu.c

@@ -16,6 +16,7 @@
 
 #include "mmu.h"
 #include "cache.h"
+#include "i386.h"
 
 #ifdef RT_USING_USERSPACE
 #include "page.h"
@@ -662,3 +663,22 @@ void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info,void *v_addr)
     rt_hw_interrupt_enable(level);
     return ret;
 }
+
+void mmu_set_pagetable(rt_ubase_t addr)
+{
+    /* set new pgdir will flush tlb */
+    write_cr3(addr);
+}
+
+void mmu_enable_user_page_access()
+{
+}
+
+void mmu_disable_user_page_access()
+{
+}
+
+void mmu_enable()
+{
+    write_cr0(read_cr0() | CR0_PG);
+}

libcpu/x86/i386/mmu.h

@@ -15,7 +15,53 @@
 #include <rtdef.h>
 #include <rtconfig.h>
 
-#include "x86_mmu.h"
+#undef PAGE_SIZE
+
+#define ADDRESS_WIDTH_BITS 32
+#define PHYSICAL_ADDRESS_WIDTH_BITS ADDRESS_WIDTH_BITS
+#define ARCH_ADDRESS_WIDTH_BITS ADDRESS_WIDTH_BITS
+
+#define __SIZE(bit) (1U << (bit))
+#define __MASK(bit) (__SIZE(bit) - 1UL)
+#define __UMASK(bit) (~(__MASK(bit)))
+#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
+#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))
+#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)(value)) & (~__MASK(bit_count))))
+#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)(value)) & (__MASK(start_bit))))
+
+#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length))
+
+#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
+#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
+
+#define PAGE_OFFSET_SHIFT 0
+#define PAGE_OFFSET_BIT 12
+#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
+#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
+#define PAGE_ADDR_MASK __UMASK(PAGE_OFFSET_BIT)
+
+#define PTE_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
+#define PTE_BIT 10
+#define PDE_SHIFT (PTE_SHIFT + PTE_BIT)
+#define PDE_BIT 10
+
+#define mmu_flush_tlb() \
+    do \
+    { \
+        unsigned long tmpreg; \
+        __asm__ __volatile__ ( \
+                    "movl   %%cr3,  %0  \n\t" \
+                    "movl   %0, %%cr3   \n\t" \
+                    :"=r"(tmpreg) \
+                    : \
+                    :"memory" \
+                    ); \
+    } \
+    while(0)
+
+#define ARCH_PAGE_SIZE PAGE_SIZE
+#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
+#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
 
 typedef struct
 {
@@ -76,6 +122,11 @@ typedef rt_size_t pte_t; /* page table entry */
 
 #define PAGE_ATTR_MASK   PAGE_OFFSET_MASK
 
+void mmu_set_pagetable(rt_ubase_t addr);
+void mmu_enable_user_page_access();
+void mmu_disable_user_page_access();
+void mmu_enable();
+
 void *mmu_table_get();
 void switch_mmu(void *mmu_table);
 int rt_hw_mmu_map_init(rt_mmu_info *mmu_info,void *v_address,rt_size_t size,rt_size_t *vtable,rt_size_t pv_off);

libcpu/x86/i386/start_gcc.S

@@ -62,7 +62,7 @@ multiboot_entry:
     popl %eax
     cmpl $-1, %eax
     je setup_fail
-	
+    
     # set kernel stack top
     movl $KSTACK_TOP_PHY, %esp
 

libcpu/x86/i386/x86_gcc.S

@@ -13,47 +13,47 @@
 
 .global load_new_gdt
 load_new_gdt:
-	movl 4(%esp), %eax
-	movw %ax, 6(%esp)		
-	lgdt 6(%esp)
-	
+    movl 4(%esp), %eax
+    movw %ax, 6(%esp)
+    lgdt 6(%esp)
+    
     # flush segment registers
     movw $KERNEL_DATA_SEL, %ax
-	movw %ax, %ds 
-	movw %ax, %es 
-	movw %ax, %ss
-	xor %eax, %eax 
-	movw %ax, %fs
-	movw %ax, %gs
-	ljmp $KERNEL_CODE_SEL, $.newpc
+    movw %ax, %ds
+    movw %ax, %es
+    movw %ax, %ss
+    xor %eax, %eax
+    movw %ax, %fs
+    movw %ax, %gs
+    ljmp $KERNEL_CODE_SEL, $.newpc
 .newpc:
-	ret
+    ret
 
 .global load_new_idt
 load_new_idt:
-	movl 4(%esp), %eax
-	movw %ax, 6(%esp)		
-	lidt 6(%esp)
-	ret
+    movl 4(%esp), %eax
+    movw %ax, 6(%esp)
+    lidt 6(%esp)
+    ret
 
-.global write_cr3 
+.global write_cr3
 write_cr3:
-	movl 4(%esp), %eax
-	movl %eax, %cr3
-	ret
+    movl 4(%esp), %eax
+    movl %eax, %cr3
+    ret
 
 .global read_cr0
 read_cr0:
-	movl %cr0, %eax
-	ret
+    movl %cr0, %eax
+    ret
 
 .global read_cr2
 read_cr2:
-	movl %cr2, %eax
-	ret
-	
-.global write_cr0 
+    movl %cr2, %eax
+    ret
+    
+.global write_cr0
 write_cr0:
-	movl 4(%esp), %eax
-	movl %eax, %cr0
-	ret
+    movl 4(%esp), %eax
+    movl %eax, %cr0
+    ret

libcpu/x86/i386/x86_mmu.c

@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-07-17     JasonHu      first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "mmu.h"
-#include <i386.h>
-
-void mmu_set_pagetable(rt_ubase_t addr)
-{
-    /* set new pgdir will flush tlb */
-    write_cr3(addr);
-}
-
-void mmu_enable_user_page_access()
-{
-}
-
-void mmu_disable_user_page_access()
-{
-}
-
-void mmu_enable()
-{
-    write_cr0(read_cr0() | CR0_PG);
-}

libcpu/x86/i386/x86_mmu.h

@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-07-17     JasonHu      first version
- */
-
-#ifndef __X86_MMU_H__
-#define __X86_MMU_H__
-
-#include <rtdef.h>
-
-#undef PAGE_SIZE
-
-#define ADDRESS_WIDTH_BITS 32
-#define PHYSICAL_ADDRESS_WIDTH_BITS ADDRESS_WIDTH_BITS
-#define ARCH_ADDRESS_WIDTH_BITS ADDRESS_WIDTH_BITS
-
-#define __SIZE(bit) (1U << (bit))
-#define __MASK(bit) (__SIZE(bit) - 1UL)
-#define __UMASK(bit) (~(__MASK(bit)))
-#define __MASKVALUE(value,maskvalue) ((value) & (maskvalue))
-#define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue)))
-#define __CHECKUPBOUND(value,bit_count) (!(((rt_size_t)(value)) & (~__MASK(bit_count))))
-#define __CHECKALIGN(value,start_bit) (!(((rt_size_t)(value)) & (__MASK(start_bit))))
-
-#define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length))
-
-#define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit))
-#define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit))
-
-#define PAGE_OFFSET_SHIFT 0
-#define PAGE_OFFSET_BIT 12
-#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
-#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
-#define PAGE_ADDR_MASK __UMASK(PAGE_OFFSET_BIT)
-
-#define PTE_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
-#define PTE_BIT 10
-#define PDE_SHIFT (PTE_SHIFT + PTE_BIT)
-#define PDE_BIT 10
-
-#define mmu_flush_tlb() \
-    do \
-    { \
-        unsigned long tmpreg; \
-        __asm__ __volatile__ ( \
-                    "movl   %%cr3,  %0  \n\t" \
-                    "movl   %0, %%cr3   \n\t" \
-                    :"=r"(tmpreg) \
-                    : \
-                    :"memory" \
-                    ); \
-    } \
-    while(0)
-
-#define ARCH_PAGE_SIZE PAGE_SIZE
-#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
-#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
-
-void mmu_set_pagetable(rt_ubase_t addr);
-void mmu_enable_user_page_access();
-void mmu_disable_user_page_access();
-void mmu_enable();
-
-#endif  /* __X86_MMU_H__ */